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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: tlu_ssd_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module tlu_ssd_dp ( | |
36 | shscan_l2clk, | |
37 | tcu_shscan_scan_in, | |
38 | tcu_shscan_pce_ov, | |
39 | tcu_shscan_aclk, | |
40 | tcu_shscan_bclk, | |
41 | tcu_shscan_scan_en, | |
42 | trl1_shscanid_2, | |
43 | sse_shscan_clk_stop, | |
44 | sse_shadow_pc, | |
45 | tsd0_shadow_pstate, | |
46 | tsd1_shadow_pstate, | |
47 | tsd0_shadow_tpc, | |
48 | tsd1_shadow_tpc, | |
49 | tsd0_shadow_tt, | |
50 | tsd1_shadow_tt, | |
51 | trl0_shadow_tl, | |
52 | trl1_shadow_tl, | |
53 | trl0_tl_for_tt, | |
54 | trl1_tl_for_tt, | |
55 | spc_shscan_scan_out); | |
56 | wire pce_ov; | |
57 | wire stop; | |
58 | wire siclk; | |
59 | wire soclk; | |
60 | wire en; | |
61 | wire clk; | |
62 | wire se; | |
63 | wire shadow_0_lat_scan_out; | |
64 | wire [117:0] shadow_unused; | |
65 | ||
66 | ||
67 | ||
68 | input shscan_l2clk; | |
69 | input tcu_shscan_scan_in; | |
70 | input tcu_shscan_pce_ov; | |
71 | input tcu_shscan_aclk; | |
72 | input tcu_shscan_bclk; | |
73 | input tcu_shscan_scan_en; | |
74 | ||
75 | input trl1_shscanid_2; | |
76 | ||
77 | input sse_shscan_clk_stop; | |
78 | input [47:2] sse_shadow_pc; | |
79 | ||
80 | input [10:0] tsd0_shadow_pstate; | |
81 | input [10:0] tsd1_shadow_pstate; | |
82 | ||
83 | input [47:2] tsd0_shadow_tpc; | |
84 | input [47:2] tsd1_shadow_tpc; | |
85 | ||
86 | input [8:0] tsd0_shadow_tt; | |
87 | input [8:0] tsd1_shadow_tt; | |
88 | ||
89 | input [2:0] trl0_shadow_tl; | |
90 | input [2:0] trl1_shadow_tl; | |
91 | ||
92 | input [2:0] trl0_tl_for_tt; | |
93 | input [2:0] trl1_tl_for_tt; | |
94 | ||
95 | ||
96 | output spc_shscan_scan_out; | |
97 | ||
98 | ||
99 | ||
100 | ||
101 | ||
102 | ////////////////////////////////////////////////////////////////////// | |
103 | ||
104 | assign pce_ov = tcu_shscan_pce_ov; | |
105 | assign stop = sse_shscan_clk_stop; // Synchronized | |
106 | assign siclk = tcu_shscan_aclk; | |
107 | assign soclk = tcu_shscan_bclk; | |
108 | assign en = 1'b1; | |
109 | assign clk = shscan_l2clk; | |
110 | assign se = tcu_shscan_scan_en; | |
111 | ||
112 | ||
113 | ||
114 | ////////////////////////////////////////////////////////////////////// | |
115 | // | |
116 | // Shadow scan flops | |
117 | // | |
118 | ||
119 | // Note: These ports are supposed to be cross-wired! | |
120 | tlu_ssd_dp_msff_macro__mux_aope__ports_2__stack_60c__width_60 shadow_0_lat ( | |
121 | .scan_in(tcu_shscan_scan_in), | |
122 | .scan_out(shadow_0_lat_scan_out), | |
123 | .din1 ({sse_shadow_pc [47:2], | |
124 | tsd0_shadow_pstate [10:0], | |
125 | trl0_shadow_tl [2:0]}), | |
126 | .din0 ({sse_shadow_pc [47:2], | |
127 | tsd1_shadow_pstate [10:0], | |
128 | trl1_shadow_tl [2:0]}), | |
129 | .sel0 (trl1_shscanid_2 ), | |
130 | .dout (shadow_unused [117:58]), | |
131 | .clk(clk), | |
132 | .en(en), | |
133 | .se(se), | |
134 | .siclk(siclk), | |
135 | .soclk(soclk), | |
136 | .pce_ov(pce_ov), | |
137 | .stop(stop) | |
138 | ); | |
139 | ||
140 | tlu_ssd_dp_msff_macro__mux_aope__ports_2__stack_60c__width_58 shadow_1_lat ( | |
141 | .scan_in(shadow_0_lat_scan_out), | |
142 | .scan_out(spc_shscan_scan_out), | |
143 | .din1 ({tsd0_shadow_tpc [47:2], | |
144 | tsd0_shadow_tt [8:0], | |
145 | trl0_tl_for_tt [2:0]}), | |
146 | .din0 ({tsd1_shadow_tpc [47:2], | |
147 | tsd1_shadow_tt [8:0], | |
148 | trl1_tl_for_tt [2:0]}), | |
149 | .sel0 (trl1_shscanid_2 ), | |
150 | .dout (shadow_unused [57:0] ), | |
151 | .clk(clk), | |
152 | .en(en), | |
153 | .se(se), | |
154 | .siclk(siclk), | |
155 | .soclk(soclk), | |
156 | .pce_ov(pce_ov), | |
157 | .stop(stop) | |
158 | ); | |
159 | ||
160 | ||
161 | ||
162 | // Do NOT run fixscan on this file! | |
163 | endmodule | |
164 | ||
165 | ||
166 | ||
167 | ||
168 | ||
169 | ||
170 | ||
171 | ||
172 | // any PARAMS parms go into naming of macro | |
173 | ||
174 | module tlu_ssd_dp_msff_macro__mux_aope__ports_2__stack_60c__width_60 ( | |
175 | din0, | |
176 | din1, | |
177 | sel0, | |
178 | clk, | |
179 | en, | |
180 | se, | |
181 | scan_in, | |
182 | siclk, | |
183 | soclk, | |
184 | pce_ov, | |
185 | stop, | |
186 | dout, | |
187 | scan_out); | |
188 | wire psel0; | |
189 | wire psel1; | |
190 | wire [59:0] muxout; | |
191 | wire l1clk; | |
192 | wire siclk_out; | |
193 | wire soclk_out; | |
194 | wire [58:0] so; | |
195 | ||
196 | input [59:0] din0; | |
197 | input [59:0] din1; | |
198 | input sel0; | |
199 | ||
200 | ||
201 | input clk; | |
202 | input en; | |
203 | input se; | |
204 | input scan_in; | |
205 | input siclk; | |
206 | input soclk; | |
207 | input pce_ov; | |
208 | input stop; | |
209 | ||
210 | ||
211 | ||
212 | output [59:0] dout; | |
213 | ||
214 | ||
215 | output scan_out; | |
216 | ||
217 | ||
218 | ||
219 | ||
220 | cl_dp1_penc2_8x c1_0 ( | |
221 | .sel0(sel0), | |
222 | .psel0(psel0), | |
223 | .psel1(psel1) | |
224 | ); | |
225 | ||
226 | mux2s #(60) d1_0 ( | |
227 | .sel0(psel0), | |
228 | .sel1(psel1), | |
229 | .in0(din0[59:0]), | |
230 | .in1(din1[59:0]), | |
231 | .dout(muxout[59:0]) | |
232 | ); | |
233 | cl_dp1_l1hdr_8x c0_0 ( | |
234 | .l2clk(clk), | |
235 | .pce(en), | |
236 | .aclk(siclk), | |
237 | .bclk(soclk), | |
238 | .l1clk(l1clk), | |
239 | .se(se), | |
240 | .pce_ov(pce_ov), | |
241 | .stop(stop), | |
242 | .siclk_out(siclk_out), | |
243 | .soclk_out(soclk_out) | |
244 | ); | |
245 | dff #(60) d0_0 ( | |
246 | .l1clk(l1clk), | |
247 | .siclk(siclk_out), | |
248 | .soclk(soclk_out), | |
249 | .d(muxout[59:0]), | |
250 | .si({scan_in,so[58:0]}), | |
251 | .so({so[58:0],scan_out}), | |
252 | .q(dout[59:0]) | |
253 | ); | |
254 | ||
255 | ||
256 | ||
257 | ||
258 | ||
259 | ||
260 | ||
261 | ||
262 | ||
263 | ||
264 | ||
265 | ||
266 | ||
267 | ||
268 | ||
269 | ||
270 | ||
271 | ||
272 | ||
273 | ||
274 | endmodule | |
275 | ||
276 | ||
277 | ||
278 | ||
279 | ||
280 | ||
281 | ||
282 | ||
283 | ||
284 | ||
285 | ||
286 | ||
287 | ||
288 | // any PARAMS parms go into naming of macro | |
289 | ||
290 | module tlu_ssd_dp_msff_macro__mux_aope__ports_2__stack_60c__width_58 ( | |
291 | din0, | |
292 | din1, | |
293 | sel0, | |
294 | clk, | |
295 | en, | |
296 | se, | |
297 | scan_in, | |
298 | siclk, | |
299 | soclk, | |
300 | pce_ov, | |
301 | stop, | |
302 | dout, | |
303 | scan_out); | |
304 | wire psel0; | |
305 | wire psel1; | |
306 | wire [57:0] muxout; | |
307 | wire l1clk; | |
308 | wire siclk_out; | |
309 | wire soclk_out; | |
310 | wire [56:0] so; | |
311 | ||
312 | input [57:0] din0; | |
313 | input [57:0] din1; | |
314 | input sel0; | |
315 | ||
316 | ||
317 | input clk; | |
318 | input en; | |
319 | input se; | |
320 | input scan_in; | |
321 | input siclk; | |
322 | input soclk; | |
323 | input pce_ov; | |
324 | input stop; | |
325 | ||
326 | ||
327 | ||
328 | output [57:0] dout; | |
329 | ||
330 | ||
331 | output scan_out; | |
332 | ||
333 | ||
334 | ||
335 | ||
336 | cl_dp1_penc2_8x c1_0 ( | |
337 | .sel0(sel0), | |
338 | .psel0(psel0), | |
339 | .psel1(psel1) | |
340 | ); | |
341 | ||
342 | mux2s #(58) d1_0 ( | |
343 | .sel0(psel0), | |
344 | .sel1(psel1), | |
345 | .in0(din0[57:0]), | |
346 | .in1(din1[57:0]), | |
347 | .dout(muxout[57:0]) | |
348 | ); | |
349 | cl_dp1_l1hdr_8x c0_0 ( | |
350 | .l2clk(clk), | |
351 | .pce(en), | |
352 | .aclk(siclk), | |
353 | .bclk(soclk), | |
354 | .l1clk(l1clk), | |
355 | .se(se), | |
356 | .pce_ov(pce_ov), | |
357 | .stop(stop), | |
358 | .siclk_out(siclk_out), | |
359 | .soclk_out(soclk_out) | |
360 | ); | |
361 | dff #(58) d0_0 ( | |
362 | .l1clk(l1clk), | |
363 | .siclk(siclk_out), | |
364 | .soclk(soclk_out), | |
365 | .d(muxout[57:0]), | |
366 | .si({scan_in,so[56:0]}), | |
367 | .so({so[56:0],scan_out}), | |
368 | .q(dout[57:0]) | |
369 | ); | |
370 | ||
371 | ||
372 | ||
373 | ||
374 | ||
375 | ||
376 | ||
377 | ||
378 | ||
379 | ||
380 | ||
381 | ||
382 | ||
383 | ||
384 | ||
385 | ||
386 | ||
387 | ||
388 | ||
389 | ||
390 | endmodule | |
391 | ||
392 | ||
393 | ||
394 | ||
395 | ||
396 | ||
397 | ||
398 |