[OpenSPARC-T2-DV] / README_FPGA

This is README_FPGA file.
First read the README file in this dir for general opensparc directions. 

===============================================================================
 User Instructions for OpenSPARC T2 Synthesizable System Level Models 
===============================================================================
The information in this file requires you to be familiar with general info
on the OpenSPARC T2 found in the README file. 


Overview:
=========

   A fully synthesizable, reduced footprint, System-level model has been 
   developed, suitable for FPGA and Emulation Platforms. 
   This model has CORE, CROSSBAR and WISHBONE Memory Controller (OpenCores). 
   This environment supports RTL Simulation, FPGA Synthesis and Gate-
   level simulation with a one-to-one correspondence (i.e a given test
   runs unchanged in the RTL & Gate environments. 
   This model is platform-independent. 

   This model uses Opencore models, which reside in dir: 
     $DV_ROOT/OpenSparc_N2/design/fpga/opencores
   For more info on opencores, visit: 
     http://www.opencores.org

   Setup environment variables by editing OpenSPARCT2.cshrc file. 
   

Supported Environments: 
=======================

Simulation: VCS on Solaris Platform.
Synthesis: Synplicity on Linux Platform.

Setup your OpenSPARC run-time environment by using following command :

   % source OpenSPARCT2.cshrc


RTL SIMULATION:
===============

A. Simulating the OpenSPARC T2 FPGA System-level environment
------------------------------------------------------------

   This environment consists of one SPARC CPU core, crossbar, spc-to-
   Wishbone-memory-controller-bridge. This model does *not* have the Level 2 
   cache, T2 memory controller unit, and all of the on-chip I/O sub-systems. 
   Due to synthesizability requirement, we have eliminated the RTL monitors. 
   This model also does not support co-simulation with Riesling. Simple 
   PC trace monitor and memory transaction monitors are included to provide
   basic debug information. This environment comes with a suite of random-
   generated self-checking tests. 

   Use "sims" to build simulation model and run your tests. 
   See README file for details on "sims" utility. 

   "sims" system environment type: fpga_1c8t
       -sys=fpga_1c8t

   "sims" regression group:  -group=<diag_groups>
        where <diag_group> can be one of the following:
          fpga_1c8t_short  has 5 short diags
          fpga_1c8t_mini  has   50 diags
          fpga_1c8t_long  has  100 diags
          fpga_1c8t_all = all of the above, a total of 155 diags 

    For example:  
 1.  To build a simulation model: 
       sims -sys=fpga_1c8t -vcs_build 

 2.  To run short regression:
       sims -sys=fpga_1c8t -vcs_run -group=fpga_1c8t_short
 
 3.  To build and run a short regression: 
       sims -sys=fpga_1c8t -group=fpga_1c8t_short

 4.  To build and run a a complete regression suite: 
       sims -sys=fpga_1c8t -group=fpga_1c8t_all

 5.  To run a single diag:
       sims -sys=fpga_1c8t -model_rel_name=rel-0.1 mpgen_50l.s -model=fpga_1c8t -vcs_run -nocache -exe_dir=$DV_ROOT/model_dir/fpga_1c8t/rel-0.1 

 6.  To run a single diag and generate waveform dumps (use -debussy):
         use   -debussy  for .fsdb waveform file
         use   -vcd      for .vcd waveform file
       sims -sys=fpga_1c8t -model_rel_name=rel-0.1 -debussy  mpgen_50l.s -model=fpga_1c8t -vcs_run -nocache -exe_dir=$DV_ROOT/model_dir/fpga_1c8t/rel-0.1 


     The testbench module t2_fpga, is the top for this env, can be found here:
           $DV_ROOT/OpenSparc_N2/design/fpga/rtl/t2_fpga.v

     The simulation file list can be found here:
           $DV_ROOT/OpenSparc_N2/design/fpga/rtl/fpga_rtl.flist


B. Simulating the OpenSPARC T2 Core in other environments
------------------------------------------------------------

   You can also simulate the synthesizable version of the core in other
   existing system environments supported by "sims" such as cmp1, cmp8, 
   fc1 or fc8 by using sims option: -vcs_build_args="+define+FPGA"

   For example: 
  1.   sims -sys=cmp1 -group=cmp1_mini_T2 -vcs_build_args="+define+FPGA" 

  2.   sims -sys=fc1 -group=fc1_mini_T2 -vcs_build_args="+define+FPGA" 

  3.   sims -sys=cmp8 -group=cmp8_mini_T2 -vcs_build_args="+define+FPGA" 

  4.   sims -sys=fc8 -group=fc8_mini_T2 -vcs_build_args="+define+FPGA" 


FPGA SYNTHESIS:
===============
   The OpenSPARC T2 FPGA System-level environment is fully synthesizable. 
   Currently following synthesis environment is supported: 
   
     1. Synplify_pro  for Xilinx LX330 device on Linux Platform
        Xilinx device type can be easily changed. 

   Synthesis can be performed for any top-level module, for example, the 
   top can be the t2 (system-level) or spc (core-level). For highest
   speedup on platforms such as an emulator, the test-bench t2_fpga
   can also be synthesized. This requires support for handling few 
   verilog system calls such as $readmemh, $display, etc. 


   The filelist used for synthesis is found here: 
        $DV_ROOT/design/fpga/rtl/fpga_rtl_synth.flist
 
   The top-level module for synthesis purposes is: t2
   and the verilog file can be found here: 
        $DV_ROOT/design/fpga/rtl/t2.v

   Define SYNP_HOME to point to Synplicity tool. 

   FPGA Synthesis is supported by the fpga_synth utility, found here:
        $DV_ROOT/tools/fpga/fpga_synth

   NOTE: 
   -----
   The fpga_synth utility is platform independent and can be run
   on any machine type. However, the synthesis have to be performed
   (running run.script) on a platform that supports the synthesis tool. 
   For example, please use a Linux machine for Synplify_pro. 

 
   fpga_synth synopsis: 
   -------------------
   $DV_ROOT/tools/fpga/fpga_synth -h

	fpga_synth 
	----------
	Utility  to synthesize T2 system level environment for FPGA  
		-f  <flist>              : optional, file list , default fpga_rtl_synth.flist
		-user_compile_dir  <dir> : optional, user specified dir , default $MODEL_DIR/fpga_synth 
		-synplicity              : required, uses synplify pro
		-top <module>            : required, top module, default t2
		-device  <keyword>       : optional, FPGA device, default LX330
		-project_file <file>     : optional, user specified project file
		-no_run                  : optional, generates script files only
		-clean                   : optional, removes temp directories/files
		-h                       : optional, help
  

A. Synthesizing the T2 FPGA System-level environment
----------------------------------------------------
   Run command:
     $DV_ROOT/tools/fpga/fpga_synth -synplicity -top t2 

   Files of interest: 
   Check for the synthesis report in: t2.srr 

   Generated gate netlist is in file: t2.vm
  
   Generated file list for gate-level model build: fpga_gate.flist
   
   A sample gate model and report file can be found in dir: 
     $DV_ROOT/design/fpga/gate


B. Synthesizing the CORE only
-----------------------------
   Run command:
     $DV_ROOT/tools/fpga/fpga_synth -synplicity -top spc 

   Files of interest: 
   Check for the synthesis report in: spc.srr 

   Generated gate netlist is in file: spc.vm

   Generated file list for gate-level model build: fpga_gate.flist

   A sample gate model and rport file can be found in dir: 
     $DV_ROOT/design/fpga/gate


GATE-LEVEL SIMULATION
=====================
Gate-level simulation is integrated into the "sims" utility. The
test-bench module t2_fpga contains the simulation infrastructure
that facilitates simulation of the gate-level netlist. A simple 
PC-trace monitor and Good/Bad Trap detection is included. 


   A master file-list to support gate-level model build is generated
   by "fpga_synth" utility and can be found in the fpga_synth dir: 
                 fpga_gate.flist

   A link to this file-list, for use by "sims" is installed in the dir:
                 $DV_ROOT/design/fpga/gate/fpga_gate_master.flist
   NOTE: This link is over-written by successive runs of fpga_synth 
         utility and corresponds to last run of fpga_synth. 

   Use "sims" to build and run your tests on your gate-model. Use the
   following parameter to enable gate model build: 
         -config_cpp_args=-DGATESIM

   You will also need to use the 64-bit VCS executables: 
         -vcs_build_args="-full64"

   You may want to specify model build dir:
         -model_rel_name=gate_model

   NOTE:
   -----
   By default "sims" will overwrite the RTL model build during a 
   gate-level model build. 
   
   
A. Simulating the OpenSPARC T2 FPGA Synthesis net-list
------------------------------------------------------
Here are the different command lines to build and simulate a gate-level
model. 

 
 1.  To build a simulation model: 
       sims -sys=fpga_1c8t -vcs_build -config_cpp_args=-DGATESIM -vcs_build_args="-full64"

 2.  To run short regression:
       sims -sys=fpga_1c8t -vcs_run -group=fpga_1c8t_short 
 
 3.  To build and run a short regression: 
       sims -sys=fpga_1c8t -group=fpga_1c8t_short -config_cpp_args=-DGATESIM -vcs_build_args="-full64"

 4.  To build and run a a complete regression suite: 
       sims -sys=fpga_1c8t -group=fpga_1c8t_all -config_cpp_args=-DGATESIM -vcs_build_args="-full64"

 5.  To run a single diag:
       sims -sys=fpga_1c8t -model_rel_name=rel-0.1 mpgen_50l.s -model=fpga_1c8t -vcs_run -nocache -exe_dir=$DV_ROOT/model_dir/fpga_1c8t/rel-0.1 

 6.  To run a single diag and generate waveform dumps (use -debussy):
         use   -debussy  for .fsdb waveform file
         use   -vcd      for .vcd waveform file
       sims -sys=fpga_1c8t -model_rel_name=rel-0.1 -debussy  mpgen_50l.s -model=fpga_1c8t -vcs_run -nocache -exe_dir=$DV_ROOT/model_dir/fpga_1c8t/rel-0.1 

     NOTE:  By default the models are built with dumping PLI linked-in. 
     To eliminate dumping PLI from the model build use, "sims" option: 
               -novcs_use_fsdb -novcs_use_vcsd
    

B. Simulating the SPC (Core) FPGA Synthesis net-list
-----------------------------------------------------
You can also simulate just the SPC gate-level netlist using the same system-
level test-bench environment. In addition to the SPC gate-model, you will
require RTL for all other modules instantiated in this environment. When you
mix RTL and gate netlist, you may run into library naming conflict. To 
solve this problem, you will need a pre-processing step before running "sims"
to build the mixed-mode gate-RTL model. 

Here are the commands to build a mixed-mode gate-RTL model: 

 1. Uniquify the modules in the gate-netlist to prevent name conflicts with RTL.
    uniquify_module -top spc -netlist 

 2. Build and simulate your model using the commands listed in Section A. 


----------End of README_FPGA file
Commit	Line	Data
86530b38 AT	1	This is README_FPGA file.
	2	First read the README file in this dir for general opensparc directions.
	3
	4	===============================================================================
	5	User Instructions for OpenSPARC T2 Synthesizable System Level Models
	6	===============================================================================
	7	The information in this file requires you to be familiar with general info
	8	on the OpenSPARC T2 found in the README file.
	9
	10
	11	Overview:
	12	=========
	13
	14	A fully synthesizable, reduced footprint, System-level model has been
	15	developed, suitable for FPGA and Emulation Platforms.
	16	This model has CORE, CROSSBAR and WISHBONE Memory Controller (OpenCores).
	17	This environment supports RTL Simulation, FPGA Synthesis and Gate-
	18	level simulation with a one-to-one correspondence (i.e a given test
	19	runs unchanged in the RTL & Gate environments.
	20	This model is platform-independent.
	21
	22	This model uses Opencore models, which reside in dir:
	23	$DV_ROOT/OpenSparc_N2/design/fpga/opencores
	24	For more info on opencores, visit:
	25	http://www.opencores.org
	26
	27	Setup environment variables by editing OpenSPARCT2.cshrc file.
	28
	29
	30
	31	Supported Environments:
	32	=======================
	33
	34	Simulation: VCS on Solaris Platform.
	35	Synthesis: Synplicity on Linux Platform.
	36
	37	Setup your OpenSPARC run-time environment by using following command :
	38
	39	% source OpenSPARCT2.cshrc
	40
	41
	42
	43
	44
	45
	46
	47	RTL SIMULATION:
	48	===============
	49
	50	A. Simulating the OpenSPARC T2 FPGA System-level environment
	51	------------------------------------------------------------
	52
	53	This environment consists of one SPARC CPU core, crossbar, spc-to-
	54	Wishbone-memory-controller-bridge. This model does not have the Level 2
	55	cache, T2 memory controller unit, and all of the on-chip I/O sub-systems.
	56	Due to synthesizability requirement, we have eliminated the RTL monitors.
	57	This model also does not support co-simulation with Riesling. Simple
	58	PC trace monitor and memory transaction monitors are included to provide
	59	basic debug information. This environment comes with a suite of random-
	60	generated self-checking tests.
	61
	62	Use "sims" to build simulation model and run your tests.
	63	See README file for details on "sims" utility.
	64
65	"sims" system environment type: fpga_1c8t
66	-sys=fpga_1c8t
67
68	"sims" regression group: -group=<diag_groups>
69	where <diag_group> can be one of the following:
70	fpga_1c8t_short has 5 short diags
71	fpga_1c8t_mini has 50 diags
72	fpga_1c8t_long has 100 diags
73	fpga_1c8t_all = all of the above, a total of 155 diags
74
75	For example:
76	1. To build a simulation model:
77	sims -sys=fpga_1c8t -vcs_build
78
79	2. To run short regression:
80	sims -sys=fpga_1c8t -vcs_run -group=fpga_1c8t_short
81
82	3. To build and run a short regression:
83	sims -sys=fpga_1c8t -group=fpga_1c8t_short
84
85	4. To build and run a a complete regression suite:
86	sims -sys=fpga_1c8t -group=fpga_1c8t_all
87
88	5. To run a single diag:
89	sims -sys=fpga_1c8t -model_rel_name=rel-0.1 mpgen_50l.s -model=fpga_1c8t -vcs_run -nocache -exe_dir=$DV_ROOT/model_dir/fpga_1c8t/rel-0.1
90
91	6. To run a single diag and generate waveform dumps (use -debussy):
92	use -debussy for .fsdb waveform file
93	use -vcd for .vcd waveform file
94	sims -sys=fpga_1c8t -model_rel_name=rel-0.1 -debussy mpgen_50l.s -model=fpga_1c8t -vcs_run -nocache -exe_dir=$DV_ROOT/model_dir/fpga_1c8t/rel-0.1
95
96
97	The testbench module t2_fpga, is the top for this env, can be found here:
98	$DV_ROOT/OpenSparc_N2/design/fpga/rtl/t2_fpga.v
99
100	The simulation file list can be found here:
101	$DV_ROOT/OpenSparc_N2/design/fpga/rtl/fpga_rtl.flist
102
103
104
105	B. Simulating the OpenSPARC T2 Core in other environments
106	------------------------------------------------------------
107
108	You can also simulate the synthesizable version of the core in other
109	existing system environments supported by "sims" such as cmp1, cmp8,
110	fc1 or fc8 by using sims option: -vcs_build_args="+define+FPGA"
111
112	For example:
113	1. sims -sys=cmp1 -group=cmp1_mini_T2 -vcs_build_args="+define+FPGA"
114
115	2. sims -sys=fc1 -group=fc1_mini_T2 -vcs_build_args="+define+FPGA"
116
117	3. sims -sys=cmp8 -group=cmp8_mini_T2 -vcs_build_args="+define+FPGA"
118
119	4. sims -sys=fc8 -group=fc8_mini_T2 -vcs_build_args="+define+FPGA"
120
121
122
123
124
125
126
127
128	FPGA SYNTHESIS:
129	===============
130	The OpenSPARC T2 FPGA System-level environment is fully synthesizable.
131	Currently following synthesis environment is supported:
132
133	1. Synplify_pro for Xilinx LX330 device on Linux Platform
134	Xilinx device type can be easily changed.
135
136	Synthesis can be performed for any top-level module, for example, the
137	top can be the t2 (system-level) or spc (core-level). For highest
138	speedup on platforms such as an emulator, the test-bench t2_fpga
139	can also be synthesized. This requires support for handling few
140	verilog system calls such as $readmemh, $display, etc.
141
142
143	The filelist used for synthesis is found here:
144	$DV_ROOT/design/fpga/rtl/fpga_rtl_synth.flist
145
146	The top-level module for synthesis purposes is: t2
147	and the verilog file can be found here:
148	$DV_ROOT/design/fpga/rtl/t2.v
149
150	Define SYNP_HOME to point to Synplicity tool.
151
152	FPGA Synthesis is supported by the fpga_synth utility, found here:
153	$DV_ROOT/tools/fpga/fpga_synth
154
155	NOTE:
156	-----
157	The fpga_synth utility is platform independent and can be run
158	on any machine type. However, the synthesis have to be performed
159	(running run.script) on a platform that supports the synthesis tool.
160	For example, please use a Linux machine for Synplify_pro.
161
162
163	fpga_synth synopsis:
164	-------------------
165	$DV_ROOT/tools/fpga/fpga_synth -h
166
167	fpga_synth
168	----------
169	Utility to synthesize T2 system level environment for FPGA
170	-f <flist> : optional, file list , default fpga_rtl_synth.flist
171	-user_compile_dir <dir> : optional, user specified dir , default $MODEL_DIR/fpga_synth
172	-synplicity : required, uses synplify pro
173	-top <module> : required, top module, default t2
174	-device <keyword> : optional, FPGA device, default LX330
175	-project_file <file> : optional, user specified project file
176	-no_run : optional, generates script files only
177	-clean : optional, removes temp directories/files
178	-h : optional, help
179
180
181
182
183
184	A. Synthesizing the T2 FPGA System-level environment
185	----------------------------------------------------
186	Run command:
187	$DV_ROOT/tools/fpga/fpga_synth -synplicity -top t2
188
189	Files of interest:
190	Check for the synthesis report in: t2.srr
191
192	Generated gate netlist is in file: t2.vm
193
194	Generated file list for gate-level model build: fpga_gate.flist
195
196	A sample gate model and report file can be found in dir:
197	$DV_ROOT/design/fpga/gate
198
199
200
201	B. Synthesizing the CORE only
202	-----------------------------
203	Run command:
204	$DV_ROOT/tools/fpga/fpga_synth -synplicity -top spc
205
206	Files of interest:
207	Check for the synthesis report in: spc.srr
208
209	Generated gate netlist is in file: spc.vm
210
211	Generated file list for gate-level model build: fpga_gate.flist
212
213	A sample gate model and rport file can be found in dir:
214	$DV_ROOT/design/fpga/gate
215
216
217
218
219
220	GATE-LEVEL SIMULATION
221	=====================
222	Gate-level simulation is integrated into the "sims" utility. The
223	test-bench module t2_fpga contains the simulation infrastructure
224	that facilitates simulation of the gate-level netlist. A simple
225	PC-trace monitor and Good/Bad Trap detection is included.
226
227
228	A master file-list to support gate-level model build is generated
229	by "fpga_synth" utility and can be found in the fpga_synth dir:
230	fpga_gate.flist
231
232	A link to this file-list, for use by "sims" is installed in the dir:
233	$DV_ROOT/design/fpga/gate/fpga_gate_master.flist
234	NOTE: This link is over-written by successive runs of fpga_synth
235	utility and corresponds to last run of fpga_synth.
236
237	Use "sims" to build and run your tests on your gate-model. Use the
238	following parameter to enable gate model build:
239	-config_cpp_args=-DGATESIM
240
241	You will also need to use the 64-bit VCS executables:
242	-vcs_build_args="-full64"
243
244	You may want to specify model build dir:
245	-model_rel_name=gate_model
246
247	NOTE:
248	-----
249	By default "sims" will overwrite the RTL model build during a
250	gate-level model build.
251
252
253
254	A. Simulating the OpenSPARC T2 FPGA Synthesis net-list
255	------------------------------------------------------
256	Here are the different command lines to build and simulate a gate-level
257	model.
258
259
260	1. To build a simulation model:
261	sims -sys=fpga_1c8t -vcs_build -config_cpp_args=-DGATESIM -vcs_build_args="-full64"
262
263	2. To run short regression:
264	sims -sys=fpga_1c8t -vcs_run -group=fpga_1c8t_short
265
266	3. To build and run a short regression:
267	sims -sys=fpga_1c8t -group=fpga_1c8t_short -config_cpp_args=-DGATESIM -vcs_build_args="-full64"
268
269	4. To build and run a a complete regression suite:
270	sims -sys=fpga_1c8t -group=fpga_1c8t_all -config_cpp_args=-DGATESIM -vcs_build_args="-full64"
271
272	5. To run a single diag:
273	sims -sys=fpga_1c8t -model_rel_name=rel-0.1 mpgen_50l.s -model=fpga_1c8t -vcs_run -nocache -exe_dir=$DV_ROOT/model_dir/fpga_1c8t/rel-0.1
274
275	6. To run a single diag and generate waveform dumps (use -debussy):
276	use -debussy for .fsdb waveform file
277	use -vcd for .vcd waveform file
278	sims -sys=fpga_1c8t -model_rel_name=rel-0.1 -debussy mpgen_50l.s -model=fpga_1c8t -vcs_run -nocache -exe_dir=$DV_ROOT/model_dir/fpga_1c8t/rel-0.1
279
280	NOTE: By default the models are built with dumping PLI linked-in.
281	To eliminate dumping PLI from the model build use, "sims" option:
282	-novcs_use_fsdb -novcs_use_vcsd
283
284
285
286
287	B. Simulating the SPC (Core) FPGA Synthesis net-list
288	-----------------------------------------------------
289	You can also simulate just the SPC gate-level netlist using the same system-
290	level test-bench environment. In addition to the SPC gate-model, you will
291	require RTL for all other modules instantiated in this environment. When you
292	mix RTL and gate netlist, you may run into library naming conflict. To
293	solve this problem, you will need a pre-processing step before running "sims"
294	to build the mixed-mode gate-RTL model.
295
296	Here are the commands to build a mixed-mode gate-RTL model:
297
298	1. Uniquify the modules in the gate-netlist to prevent name conflicts with RTL.
299	uniquify_module -top spc -netlist
300
301	2. Build and simulate your model using the commands listed in Section A.
302
303
304
305
306
307	----------End of README_FPGA file