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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: pcx_rep_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `ifndef FPGA | |
36 | module pcx_rep_dp ( | |
37 | mac0_rep_out, | |
38 | mac1_rep_out, | |
39 | mac2_rep_out, | |
40 | mac3_rep_out, | |
41 | mac4_rep_out, | |
42 | mac5_rep_out, | |
43 | mac6_rep_out, | |
44 | scan_rep_out, | |
45 | mac0_rep_in, | |
46 | mac1_rep_in, | |
47 | mac2_rep_in, | |
48 | mac3_rep_in, | |
49 | mac4_rep_in, | |
50 | mac5_rep_in, | |
51 | mac6_rep_in, | |
52 | scan_rep_in); | |
53 | wire [4:0] mac2_rep_0; | |
54 | wire [4:0] mac3_rep_0; | |
55 | wire [4:0] mac4_rep_0; | |
56 | wire scan_rep7_out; | |
57 | wire scan_rep5_out; | |
58 | wire scan_rep3_out; | |
59 | ||
60 | ||
61 | output [4:0] mac0_rep_out; | |
62 | output [4:0] mac1_rep_out; | |
63 | output [4:0] mac2_rep_out; | |
64 | output [4:0] mac3_rep_out; | |
65 | output [4:0] mac4_rep_out; | |
66 | output [4:0] mac5_rep_out; | |
67 | output [4:0] mac6_rep_out; | |
68 | output scan_rep_out; | |
69 | ||
70 | ||
71 | input [4:0] mac0_rep_in; | |
72 | input [4:0] mac1_rep_in; | |
73 | input [4:0] mac2_rep_in; | |
74 | input [4:0] mac3_rep_in; | |
75 | input [4:0] mac4_rep_in; | |
76 | input [4:0] mac5_rep_in; | |
77 | input [4:0] mac6_rep_in; | |
78 | input scan_rep_in; | |
79 | ||
80 | ||
81 | ||
82 | // sparc0 sparc2 sparc1 sparc3 sparc5 sparc7 sparc4 sparc6 | |
83 | // | | | | | | | | | |
84 | // v v v v v v v v | |
85 | // mac0 - mac1 - mac2 - mac3 - mac4 - mac5 - mac6 - mac7 | |
86 | ||
87 | ||
88 | // mac0 input go through 1 buffer | |
89 | pcx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac0 ( | |
90 | .din ({mac0_rep_in[4:0]}), | |
91 | .dout ({mac0_rep_out[4:0]}) | |
92 | ); | |
93 | ||
94 | // mac1 input go through 1 buffer | |
95 | pcx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac1 ( | |
96 | .din ({mac1_rep_in[4:0]}), | |
97 | .dout ({mac1_rep_out[4:0]}) | |
98 | ); | |
99 | ||
100 | ||
101 | // mac2 input go through 2 buffers | |
102 | pcx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac2_0 ( | |
103 | .din ({mac2_rep_in[4:0]}), | |
104 | .dout ({mac2_rep_0[4:0]}) | |
105 | ); | |
106 | ||
107 | pcx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac2_1 ( | |
108 | .din ({mac2_rep_0[4:0]}), | |
109 | .dout ({mac2_rep_out[4:0]}) | |
110 | ); | |
111 | ||
112 | // mac3 input go through 2 buffers | |
113 | pcx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac3_0 ( | |
114 | .din ({mac3_rep_in[4:0]}), | |
115 | .dout ({mac3_rep_0[4:0]}) | |
116 | ); | |
117 | ||
118 | pcx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac3_1 ( | |
119 | .din ({mac3_rep_0[4:0]}), | |
120 | .dout ({mac3_rep_out[4:0]}) | |
121 | ); | |
122 | ||
123 | // mac4 input go through 2 buffers | |
124 | pcx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac4_0 ( | |
125 | .din ({mac4_rep_in[4:0]}), | |
126 | .dout ({mac4_rep_0[4:0]}) | |
127 | ); | |
128 | ||
129 | pcx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac4_1 ( | |
130 | .din ({mac4_rep_0[4:0]}), | |
131 | .dout ({mac4_rep_out[4:0]}) | |
132 | ); | |
133 | ||
134 | // mac5 input go through 1 buffer | |
135 | pcx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac5 ( | |
136 | .din ({mac5_rep_in[4:0]}), | |
137 | .dout ({mac5_rep_out[4:0]}) | |
138 | ); | |
139 | ||
140 | // mac6 input go through 1 buffer | |
141 | pcx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac6 ( | |
142 | .din ({mac6_rep_in[4:0]}), | |
143 | .dout ({mac6_rep_out[4:0]}) | |
144 | ); | |
145 | ||
146 | ||
147 | // repeat the scan chain | |
148 | ||
149 | // buffer on top of mac7 | |
150 | pcx_rep_dp_buff_macro__dbuff_32x__stack_none__width_1 buf_scan7 ( | |
151 | .din (scan_rep_in), | |
152 | .dout (scan_rep7_out) | |
153 | ); | |
154 | ||
155 | // buffer on top of mac5 | |
156 | pcx_rep_dp_buff_macro__dbuff_32x__stack_none__width_1 buf_scan5 ( | |
157 | .din (scan_rep7_out), | |
158 | .dout (scan_rep5_out) | |
159 | ); | |
160 | ||
161 | // buffer on top of mac3 | |
162 | pcx_rep_dp_buff_macro__dbuff_32x__stack_none__width_1 buf_scan3 ( | |
163 | .din (scan_rep5_out), | |
164 | .dout (scan_rep3_out) | |
165 | ); | |
166 | ||
167 | // buffer on top of mac1 | |
168 | pcx_rep_dp_buff_macro__dbuff_32x__stack_none__width_1 buf_scan1 ( | |
169 | .din (scan_rep3_out), | |
170 | .dout (scan_rep_out) | |
171 | ); | |
172 | ||
173 | endmodule | |
174 | ||
175 | ||
176 | // | |
177 | // buff macro | |
178 | // | |
179 | // | |
180 | ||
181 | ||
182 | ||
183 | ||
184 | ||
185 | module pcx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 ( | |
186 | din, | |
187 | dout); | |
188 | input [4:0] din; | |
189 | output [4:0] dout; | |
190 | ||
191 | ||
192 | ||
193 | ||
194 | ||
195 | ||
196 | buff #(5) d0_0 ( | |
197 | .in(din[4:0]), | |
198 | .out(dout[4:0]) | |
199 | ); | |
200 | ||
201 | ||
202 | ||
203 | ||
204 | ||
205 | ||
206 | ||
207 | ||
208 | endmodule | |
209 | ||
210 | ||
211 | ||
212 | ||
213 | ||
214 | // | |
215 | // buff macro | |
216 | // | |
217 | // | |
218 | ||
219 | ||
220 | ||
221 | ||
222 | ||
223 | module pcx_rep_dp_buff_macro__dbuff_32x__stack_none__width_1 ( | |
224 | din, | |
225 | dout); | |
226 | input [0:0] din; | |
227 | output [0:0] dout; | |
228 | ||
229 | ||
230 | ||
231 | ||
232 | ||
233 | ||
234 | buff #(1) d0_0 ( | |
235 | .in(din[0:0]), | |
236 | .out(dout[0:0]) | |
237 | ); | |
238 | ||
239 | ||
240 | ||
241 | ||
242 | ||
243 | ||
244 | ||
245 | ||
246 | endmodule | |
247 | ||
248 | ||
249 | `endif // `ifndef FPGA | |
250 | ||
251 | `ifdef FPGA | |
252 | `timescale 1 ns / 100 ps | |
253 | module pcx_rep_dp(mac0_rep_out, mac1_rep_out, mac2_rep_out, mac3_rep_out, | |
254 | mac4_rep_out, mac5_rep_out, mac6_rep_out, scan_rep_out, mac0_rep_in, | |
255 | mac1_rep_in, mac2_rep_in, mac3_rep_in, mac4_rep_in, mac5_rep_in, | |
256 | mac6_rep_in, scan_rep_in); | |
257 | ||
258 | output [4:0] mac0_rep_out; | |
259 | output [4:0] mac1_rep_out; | |
260 | output [4:0] mac2_rep_out; | |
261 | output [4:0] mac3_rep_out; | |
262 | output [4:0] mac4_rep_out; | |
263 | output [4:0] mac5_rep_out; | |
264 | output [4:0] mac6_rep_out; | |
265 | output scan_rep_out; | |
266 | input [4:0] mac0_rep_in; | |
267 | input [4:0] mac1_rep_in; | |
268 | input [4:0] mac2_rep_in; | |
269 | input [4:0] mac3_rep_in; | |
270 | input [4:0] mac4_rep_in; | |
271 | input [4:0] mac5_rep_in; | |
272 | input [4:0] mac6_rep_in; | |
273 | input scan_rep_in; | |
274 | ||
275 | wire [4:0] mac2_rep_0; | |
276 | wire [4:0] mac3_rep_0; | |
277 | wire [4:0] mac4_rep_0; | |
278 | wire scan_rep7_out; | |
279 | wire scan_rep5_out; | |
280 | wire scan_rep3_out; | |
281 | ||
282 | buff_macro__dbuff_32x__stack_6l__width_5 buf_mac0( | |
283 | .din ({mac0_rep_in[4:0]}), | |
284 | .dout ({mac0_rep_out[4:0]})); | |
285 | buff_macro__dbuff_32x__stack_6l__width_5 buf_mac1( | |
286 | .din ({mac1_rep_in[4:0]}), | |
287 | .dout ({mac1_rep_out[4:0]})); | |
288 | buff_macro__dbuff_32x__stack_6l__width_5 buf_mac2_0( | |
289 | .din ({mac2_rep_in[4:0]}), | |
290 | .dout ({mac2_rep_0[4:0]})); | |
291 | buff_macro__dbuff_32x__stack_6l__width_5 buf_mac2_1( | |
292 | .din ({mac2_rep_0[4:0]}), | |
293 | .dout ({mac2_rep_out[4:0]})); | |
294 | buff_macro__dbuff_32x__stack_6l__width_5 buf_mac3_0( | |
295 | .din ({mac3_rep_in[4:0]}), | |
296 | .dout ({mac3_rep_0[4:0]})); | |
297 | buff_macro__dbuff_32x__stack_6l__width_5 buf_mac3_1( | |
298 | .din ({mac3_rep_0[4:0]}), | |
299 | .dout ({mac3_rep_out[4:0]})); | |
300 | buff_macro__dbuff_32x__stack_6l__width_5 buf_mac4_0( | |
301 | .din ({mac4_rep_in[4:0]}), | |
302 | .dout ({mac4_rep_0[4:0]})); | |
303 | buff_macro__dbuff_32x__stack_6l__width_5 buf_mac4_1( | |
304 | .din ({mac4_rep_0[4:0]}), | |
305 | .dout ({mac4_rep_out[4:0]})); | |
306 | buff_macro__dbuff_32x__stack_6l__width_5 buf_mac5( | |
307 | .din ({mac5_rep_in[4:0]}), | |
308 | .dout ({mac5_rep_out[4:0]})); | |
309 | buff_macro__dbuff_32x__stack_6l__width_5 buf_mac6( | |
310 | .din ({mac6_rep_in[4:0]}), | |
311 | .dout ({mac6_rep_out[4:0]})); | |
312 | buff_macro__dbuff_32x__stack_none__width_1 buf_scan7( | |
313 | .din (scan_rep_in), | |
314 | .dout (scan_rep7_out)); | |
315 | buff_macro__dbuff_32x__stack_none__width_1 buf_scan5( | |
316 | .din (scan_rep7_out), | |
317 | .dout (scan_rep5_out)); | |
318 | buff_macro__dbuff_32x__stack_none__width_1 buf_scan3( | |
319 | .din (scan_rep5_out), | |
320 | .dout (scan_rep3_out)); | |
321 | buff_macro__dbuff_32x__stack_none__width_1 buf_scan1( | |
322 | .din (scan_rep3_out), | |
323 | .dout (scan_rep_out)); | |
324 | endmodule | |
325 | ||
326 | ||
327 | `endif // `ifdef FPGA | |
328 | ||
329 | ||
330 |