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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: dmu_imu_eqs_defines.h | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | `ifdef FIRE_DLC_IMU_EQS_DEFINES | |
39 | `else | |
40 | `define FIRE_DLC_IMU_EQS_DEFINES | |
41 | ||
42 | `define FIRE_DLC_IMU_EQS_INSTANCE_ID_VALUE_A 1'h0 | |
43 | `define FIRE_DLC_IMU_EQS_INSTANCE_ID_VALUE_B 1'h1 | |
44 | ||
45 | //------------------------------------------------------- | |
46 | //----- Variable definitions for register fire_dlc_imu_eqs_csr_eq_base_address | |
47 | //------------------------------------------------------- | |
48 | ||
49 | `define FIRE_DLC_IMU_EQS_CSR_A_EQ_BASE_ADDRESS_HW_ADDR 27'b000000011000010000000000000 | |
50 | `define FIRE_DLC_IMU_EQS_CSR_A_EQ_BASE_ADDRESS_ADDR 30'b000000011000010000000000000000 | |
51 | `define FIRE_DLC_IMU_EQS_CSR_B_EQ_BASE_ADDRESS_HW_ADDR 27'b000000011100010000000000000 | |
52 | `define FIRE_DLC_IMU_EQS_CSR_B_EQ_BASE_ADDRESS_ADDR 30'b000000011100010000000000000000 | |
53 | ||
54 | `define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_WIDTH 64 | |
55 | `define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_DEPTH 1 | |
56 | `define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_SLC 63:0 | |
57 | `define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_INT_SLC 63:0 | |
58 | `define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_POSITION 0 | |
59 | `define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_LOW_ADDR_WIDTH 0 | |
60 | `define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_ADDR_RANGE 26:0 | |
61 | `define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_READ_MASK 64'b1111111111111111111111111111111111111111111110000000000000000000 | |
62 | `define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
63 | `define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_WRITE_MASK 64'b1111111111111111111111111111111111111111111110000000000000000000 | |
64 | `define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
65 | `define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
66 | `define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
67 | `define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
68 | `define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_RMASK 64'b1111111111111111111111111111111111111111111110000000000000000000 | |
69 | `define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_RESERVED_BIT_MASK 64'b0000000000000000000000000000000000000000000001111111111111111111 | |
70 | `define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
71 | `define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
72 | `define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_INTERNAL_REG 1 | |
73 | `define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_ZERO_TIME_OMNI 1 | |
74 | `define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_NUM_FIELDS 1 | |
75 | `define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_ADDRESS_FID 0 | |
76 | `define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_ADDRESS_SLC 63:19 | |
77 | `define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_ADDRESS_WIDTH 45 | |
78 | `define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_ADDRESS_INT_SLC 44:0 | |
79 | `define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_ADDRESS_POSITION 19 | |
80 | `define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_ADDRESS_FMASK 64'b1111111111111111111111111111111111111111111110000000000000000000 | |
81 | `define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_ADDRESS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
82 | `define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_ADDRESS_POR_VALUE 45'b000000000000000000000000000000000000000000000 | |
83 | ||
84 | //------------------------------------------------------- | |
85 | //----- Variable definitions for register fire_dlc_imu_eqs_csr_eq_ctrl_set | |
86 | //------------------------------------------------------- | |
87 | ||
88 | `define FIRE_DLC_IMU_EQS_CSR_A_EQ_CTRL_SET_HW_ADDR 27'b000000011000010001000000000 | |
89 | `define FIRE_DLC_IMU_EQS_CSR_A_EQ_CTRL_SET_ADDR 30'b000000011000010001000000000000 | |
90 | `define FIRE_DLC_IMU_EQS_CSR_B_EQ_CTRL_SET_HW_ADDR 27'b000000011100010001000000000 | |
91 | `define FIRE_DLC_IMU_EQS_CSR_B_EQ_CTRL_SET_ADDR 30'b000000011100010001000000000000 | |
92 | ||
93 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_WIDTH 64 | |
94 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_DEPTH 36 | |
95 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_SLC 63:0 | |
96 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_INT_SLC 63:0 | |
97 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_POSITION 0 | |
98 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH 6 | |
99 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_SEL_RANGE 5:0 | |
100 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_ADDR_RANGE 26:6 | |
101 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
102 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
103 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_WRITE_MASK 64'b0000001000000000000100000000000000000000000000000000000000000000 | |
104 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_WRITE_ONLY_MASK 64'b0000001000000000000100000000000000000000000000000000000000000000 | |
105 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
106 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
107 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
108 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_RMASK 64'b0000001000000000000100000000000000000000000000000000000000000000 | |
109 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_RESERVED_BIT_MASK 64'b1111110111111111111011111111111111111111111111111111111111111111 | |
110 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
111 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
112 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_INTERNAL_REG 0 | |
113 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_EXTERNAL_DECODE_REG 1 | |
114 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_ZERO_TIME_OMNI 0 | |
115 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_NUM_FIELDS 2 | |
116 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_ENOVERR_FID 0 | |
117 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_ENOVERR_SLC 57:57 | |
118 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_ENOVERR_WIDTH 1 | |
119 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_ENOVERR_INT_SLC 0:0 | |
120 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_ENOVERR_POSITION 57 | |
121 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_ENOVERR_FMASK 64'b0000001000000000000000000000000000000000000000000000000000000000 | |
122 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_ENOVERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
123 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_ENOVERR_POR_VALUE 1'b0 | |
124 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_EN_FID 1 | |
125 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_EN_SLC 44:44 | |
126 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_EN_WIDTH 1 | |
127 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_EN_INT_SLC 0:0 | |
128 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_EN_POSITION 44 | |
129 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_EN_FMASK 64'b0000000000000000000100000000000000000000000000000000000000000000 | |
130 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
131 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_EN_POR_VALUE 1'b0 | |
132 | ||
133 | //------------------------------------------------------- | |
134 | //----- Variable definitions for register fire_dlc_imu_eqs_csr_eq_ctrl_clr | |
135 | //------------------------------------------------------- | |
136 | ||
137 | `define FIRE_DLC_IMU_EQS_CSR_A_EQ_CTRL_CLR_HW_ADDR 27'b000000011000010001001000000 | |
138 | `define FIRE_DLC_IMU_EQS_CSR_A_EQ_CTRL_CLR_ADDR 30'b000000011000010001001000000000 | |
139 | `define FIRE_DLC_IMU_EQS_CSR_B_EQ_CTRL_CLR_HW_ADDR 27'b000000011100010001001000000 | |
140 | `define FIRE_DLC_IMU_EQS_CSR_B_EQ_CTRL_CLR_ADDR 30'b000000011100010001001000000000 | |
141 | ||
142 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_WIDTH 64 | |
143 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_DEPTH 36 | |
144 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_SLC 63:0 | |
145 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_INT_SLC 63:0 | |
146 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_POSITION 0 | |
147 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH 6 | |
148 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_SEL_RANGE 5:0 | |
149 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_ADDR_RANGE 26:6 | |
150 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
151 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
152 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_WRITE_MASK 64'b0000001000000000100100000000000000000000000000000000000000000000 | |
153 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_WRITE_ONLY_MASK 64'b0000001000000000100100000000000000000000000000000000000000000000 | |
154 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
155 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
156 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
157 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_RMASK 64'b0000001000000000100100000000000000000000000000000000000000000000 | |
158 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_RESERVED_BIT_MASK 64'b1111110111111111011011111111111111111111111111111111111111111111 | |
159 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
160 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
161 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_INTERNAL_REG 0 | |
162 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_EXTERNAL_DECODE_REG 1 | |
163 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_ZERO_TIME_OMNI 0 | |
164 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_NUM_FIELDS 3 | |
165 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_COVERR_FID 0 | |
166 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_COVERR_SLC 57:57 | |
167 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_COVERR_WIDTH 1 | |
168 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_COVERR_INT_SLC 0:0 | |
169 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_COVERR_POSITION 57 | |
170 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_COVERR_FMASK 64'b0000001000000000000000000000000000000000000000000000000000000000 | |
171 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_COVERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
172 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_COVERR_POR_VALUE 1'b0 | |
173 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_E2I_FID 1 | |
174 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_E2I_SLC 47:47 | |
175 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_E2I_WIDTH 1 | |
176 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_E2I_INT_SLC 0:0 | |
177 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_E2I_POSITION 47 | |
178 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_E2I_FMASK 64'b0000000000000000100000000000000000000000000000000000000000000000 | |
179 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_E2I_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
180 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_E2I_POR_VALUE 1'b0 | |
181 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_DIS_FID 2 | |
182 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_DIS_SLC 44:44 | |
183 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_DIS_WIDTH 1 | |
184 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_DIS_INT_SLC 0:0 | |
185 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_DIS_POSITION 44 | |
186 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_DIS_FMASK 64'b0000000000000000000100000000000000000000000000000000000000000000 | |
187 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_DIS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
188 | `define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_DIS_POR_VALUE 1'b0 | |
189 | ||
190 | //------------------------------------------------------- | |
191 | //----- Variable definitions for register fire_dlc_imu_eqs_csr_eq_state | |
192 | //------------------------------------------------------- | |
193 | ||
194 | `define FIRE_DLC_IMU_EQS_CSR_A_EQ_STATE_HW_ADDR 27'b000000011000010001010000000 | |
195 | `define FIRE_DLC_IMU_EQS_CSR_A_EQ_STATE_ADDR 30'b000000011000010001010000000000 | |
196 | `define FIRE_DLC_IMU_EQS_CSR_B_EQ_STATE_HW_ADDR 27'b000000011100010001010000000 | |
197 | `define FIRE_DLC_IMU_EQS_CSR_B_EQ_STATE_ADDR 30'b000000011100010001010000000000 | |
198 | ||
199 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_WIDTH 64 | |
200 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_DEPTH 36 | |
201 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_SLC 63:0 | |
202 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_INT_SLC 63:0 | |
203 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_POSITION 0 | |
204 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH 6 | |
205 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_SEL_RANGE 5:0 | |
206 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_ADDR_RANGE 26:6 | |
207 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000111 | |
208 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000111 | |
209 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
210 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
211 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
212 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
213 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
214 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000111 | |
215 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111000 | |
216 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000111 | |
217 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000001 | |
218 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_INTERNAL_REG 0 | |
219 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_EXTERNAL_DECODE_REG 1 | |
220 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_ZERO_TIME_OMNI 0 | |
221 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_NUM_FIELDS 1 | |
222 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_STATE_FID 0 | |
223 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_STATE_SLC 2:0 | |
224 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_STATE_WIDTH 3 | |
225 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_STATE_INT_SLC 2:0 | |
226 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_STATE_POSITION 0 | |
227 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000111 | |
228 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000111 | |
229 | `define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_STATE_POR_VALUE 3'b001 | |
230 | ||
231 | //------------------------------------------------------- | |
232 | //----- Variable definitions for register fire_dlc_imu_eqs_csr_eq_tail | |
233 | //------------------------------------------------------- | |
234 | ||
235 | `define FIRE_DLC_IMU_EQS_CSR_A_EQ_TAIL_HW_ADDR 27'b000000011000010001011000000 | |
236 | `define FIRE_DLC_IMU_EQS_CSR_A_EQ_TAIL_ADDR 30'b000000011000010001011000000000 | |
237 | `define FIRE_DLC_IMU_EQS_CSR_B_EQ_TAIL_HW_ADDR 27'b000000011100010001011000000 | |
238 | `define FIRE_DLC_IMU_EQS_CSR_B_EQ_TAIL_ADDR 30'b000000011100010001011000000000 | |
239 | ||
240 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH 64 | |
241 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_DEPTH 36 | |
242 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_SLC 63:0 | |
243 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_INT_SLC 63:0 | |
244 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_POSITION 0 | |
245 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH 6 | |
246 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_SEL_RANGE 5:0 | |
247 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_ADDR_RANGE 26:6 | |
248 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_READ_MASK 64'b0000001000000000000000000000000000000000000000000000000001111111 | |
249 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_READ_ONLY_MASK 64'b0000001000000000000000000000000000000000000000000000000000000000 | |
250 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000001111111 | |
251 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
252 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
253 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
254 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
255 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_RMASK 64'b0000001000000000000000000000000000000000000000000000000001111111 | |
256 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_RESERVED_BIT_MASK 64'b1111110111111111111111111111111111111111111111111111111110000000 | |
257 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_HW_LD_MASK 64'b0000001000000000000000000000000000000000000000000000000001111111 | |
258 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
259 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_INTERNAL_REG 1 | |
260 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_ZERO_TIME_OMNI 1 | |
261 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_NUM_FIELDS 2 | |
262 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_OVERR_FID 0 | |
263 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_OVERR_SLC 57:57 | |
264 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_OVERR_WIDTH 1 | |
265 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_OVERR_INT_SLC 0:0 | |
266 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_OVERR_POSITION 57 | |
267 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_OVERR_FMASK 64'b0000001000000000000000000000000000000000000000000000000000000000 | |
268 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_OVERR_HW_LD_MASK 64'b0000001000000000000000000000000000000000000000000000000000000000 | |
269 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_OVERR_POR_VALUE 1'b0 | |
270 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_FID 1 | |
271 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC 6:0 | |
272 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_WIDTH 7 | |
273 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC 6:0 | |
274 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_POSITION 0 | |
275 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_FMASK 64'b0000000000000000000000000000000000000000000000000000000001111111 | |
276 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000001111111 | |
277 | `define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_POR_VALUE 7'b0000000 | |
278 | ||
279 | //------------------------------------------------------- | |
280 | //----- Variable definitions for register fire_dlc_imu_eqs_csr_eq_head | |
281 | //------------------------------------------------------- | |
282 | ||
283 | `define FIRE_DLC_IMU_EQS_CSR_A_EQ_HEAD_HW_ADDR 27'b000000011000010001100000000 | |
284 | `define FIRE_DLC_IMU_EQS_CSR_A_EQ_HEAD_ADDR 30'b000000011000010001100000000000 | |
285 | `define FIRE_DLC_IMU_EQS_CSR_B_EQ_HEAD_HW_ADDR 27'b000000011100010001100000000 | |
286 | `define FIRE_DLC_IMU_EQS_CSR_B_EQ_HEAD_ADDR 30'b000000011100010001100000000000 | |
287 | ||
288 | `define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH 64 | |
289 | `define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_DEPTH 36 | |
290 | `define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_SLC 63:0 | |
291 | `define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_INT_SLC 63:0 | |
292 | `define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_POSITION 0 | |
293 | `define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH 6 | |
294 | `define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_SEL_RANGE 5:0 | |
295 | `define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_ADDR_RANGE 26:6 | |
296 | `define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000001111111 | |
297 | `define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
298 | `define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000001111111 | |
299 | `define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
300 | `define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
301 | `define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
302 | `define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
303 | `define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_RMASK 64'b0000000000000000000000000000000000000000000000000000000001111111 | |
304 | `define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111110000000 | |
305 | `define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
306 | `define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
307 | `define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_INTERNAL_REG 1 | |
308 | `define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_ZERO_TIME_OMNI 1 | |
309 | `define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_NUM_FIELDS 1 | |
310 | `define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_FID 0 | |
311 | `define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC 6:0 | |
312 | `define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_WIDTH 7 | |
313 | `define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC 6:0 | |
314 | `define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_POSITION 0 | |
315 | `define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_FMASK 64'b0000000000000000000000000000000000000000000000000000000001111111 | |
316 | `define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
317 | `define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_POR_VALUE 7'b0000000 | |
318 | ||
319 | ||
320 | `endif |