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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_imu_iss_csr_interrupt_mapping_43_entry.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
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31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_imu_iss_csr_interrupt_mapping_43_entry | |
36 | ( | |
37 | // synopsys translate_off | |
38 | omni_ld, | |
39 | omni_data, | |
40 | // synopsys translate_on | |
41 | clk, | |
42 | rst_l, | |
43 | w_ld, | |
44 | csrbus_wr_data, | |
45 | interrupt_mapping_43_csrbus_read_data | |
46 | ); | |
47 | ||
48 | //==================================================================== | |
49 | // Polarity declarations | |
50 | //==================================================================== | |
51 | // synopsys translate_off | |
52 | input omni_ld; // Omni load | |
53 | // vlint flag_input_port_not_connected off | |
54 | input [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_WIDTH - 1:0] omni_data; | |
55 | // Omni write data | |
56 | // synopsys translate_on | |
57 | // vlint flag_input_port_not_connected on | |
58 | input clk; // Clock signal | |
59 | input rst_l; // Reset signal | |
60 | input w_ld; // SW load | |
61 | // vlint flag_input_port_not_connected off | |
62 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
63 | // vlint flag_input_port_not_connected on | |
64 | output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_WIDTH-1:0] interrupt_mapping_43_csrbus_read_data; | |
65 | // SW read data | |
66 | ||
67 | //==================================================================== | |
68 | // Type declarations | |
69 | //==================================================================== | |
70 | // synopsys translate_off | |
71 | wire omni_ld; // Omni load | |
72 | // vlint flag_dangling_net_within_module off | |
73 | // vlint flag_net_has_no_load off | |
74 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_WIDTH - 1:0] omni_data; | |
75 | // Omni write data | |
76 | // synopsys translate_on | |
77 | // vlint flag_dangling_net_within_module on | |
78 | // vlint flag_net_has_no_load on | |
79 | wire clk; // Clock signal | |
80 | wire rst_l; // Reset signal | |
81 | wire w_ld; // SW load | |
82 | // vlint flag_dangling_net_within_module off | |
83 | // vlint flag_net_has_no_load off | |
84 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
85 | // vlint flag_dangling_net_within_module on | |
86 | // vlint flag_net_has_no_load on | |
87 | wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_WIDTH-1:0] interrupt_mapping_43_csrbus_read_data; | |
88 | // SW read data | |
89 | ||
90 | //==================================================================== | |
91 | // Logic | |
92 | //==================================================================== | |
93 | ||
94 | //----- Reset values | |
95 | // verilint 531 off | |
96 | wire [0:0] reset_mdo_mode = 1'h0; | |
97 | wire [0:0] reset_v = 1'h0; | |
98 | wire [5:0] reset_t_id = 6'h0; | |
99 | wire [3:0] reset_int_cntrl_num = 4'h0; | |
100 | // verilint 531 on | |
101 | ||
102 | //----- Active high reset wires | |
103 | wire rst_l_active_high = ~rst_l; | |
104 | ||
105 | //==================================================== | |
106 | // Instantiation of flops | |
107 | //==================================================== | |
108 | ||
109 | assign interrupt_mapping_43_csrbus_read_data[0] = 1'b0; // bit 0 | |
110 | assign interrupt_mapping_43_csrbus_read_data[1] = 1'b0; // bit 1 | |
111 | assign interrupt_mapping_43_csrbus_read_data[2] = 1'b0; // bit 2 | |
112 | assign interrupt_mapping_43_csrbus_read_data[3] = 1'b0; // bit 3 | |
113 | assign interrupt_mapping_43_csrbus_read_data[4] = 1'b0; // bit 4 | |
114 | assign interrupt_mapping_43_csrbus_read_data[5] = 1'b0; // bit 5 | |
115 | // bit 6 | |
116 | csr_sw csr_sw_6 | |
117 | ( | |
118 | // synopsys translate_off | |
119 | .omni_ld (omni_ld), | |
120 | .omni_data (omni_data[6]), | |
121 | .omni_rw_alias (1'b1), | |
122 | .omni_rw1c_alias (1'b0), | |
123 | .omni_rw1s_alias (1'b0), | |
124 | // synopsys translate_on | |
125 | .rst (rst_l_active_high), | |
126 | .rst_val (reset_int_cntrl_num[0]), | |
127 | .csr_ld (w_ld), | |
128 | .csr_data (csrbus_wr_data[6]), | |
129 | .rw_alias (1'b1), | |
130 | .rw1c_alias (1'b0), | |
131 | .rw1s_alias (1'b0), | |
132 | .hw_ld (1'b0), | |
133 | .hw_data (1'b0), | |
134 | .cp (clk), | |
135 | .q (interrupt_mapping_43_csrbus_read_data[6]) | |
136 | ); | |
137 | ||
138 | // bit 7 | |
139 | csr_sw csr_sw_7 | |
140 | ( | |
141 | // synopsys translate_off | |
142 | .omni_ld (omni_ld), | |
143 | .omni_data (omni_data[7]), | |
144 | .omni_rw_alias (1'b1), | |
145 | .omni_rw1c_alias (1'b0), | |
146 | .omni_rw1s_alias (1'b0), | |
147 | // synopsys translate_on | |
148 | .rst (rst_l_active_high), | |
149 | .rst_val (reset_int_cntrl_num[1]), | |
150 | .csr_ld (w_ld), | |
151 | .csr_data (csrbus_wr_data[7]), | |
152 | .rw_alias (1'b1), | |
153 | .rw1c_alias (1'b0), | |
154 | .rw1s_alias (1'b0), | |
155 | .hw_ld (1'b0), | |
156 | .hw_data (1'b0), | |
157 | .cp (clk), | |
158 | .q (interrupt_mapping_43_csrbus_read_data[7]) | |
159 | ); | |
160 | ||
161 | // bit 8 | |
162 | csr_sw csr_sw_8 | |
163 | ( | |
164 | // synopsys translate_off | |
165 | .omni_ld (omni_ld), | |
166 | .omni_data (omni_data[8]), | |
167 | .omni_rw_alias (1'b1), | |
168 | .omni_rw1c_alias (1'b0), | |
169 | .omni_rw1s_alias (1'b0), | |
170 | // synopsys translate_on | |
171 | .rst (rst_l_active_high), | |
172 | .rst_val (reset_int_cntrl_num[2]), | |
173 | .csr_ld (w_ld), | |
174 | .csr_data (csrbus_wr_data[8]), | |
175 | .rw_alias (1'b1), | |
176 | .rw1c_alias (1'b0), | |
177 | .rw1s_alias (1'b0), | |
178 | .hw_ld (1'b0), | |
179 | .hw_data (1'b0), | |
180 | .cp (clk), | |
181 | .q (interrupt_mapping_43_csrbus_read_data[8]) | |
182 | ); | |
183 | ||
184 | // bit 9 | |
185 | csr_sw csr_sw_9 | |
186 | ( | |
187 | // synopsys translate_off | |
188 | .omni_ld (omni_ld), | |
189 | .omni_data (omni_data[9]), | |
190 | .omni_rw_alias (1'b1), | |
191 | .omni_rw1c_alias (1'b0), | |
192 | .omni_rw1s_alias (1'b0), | |
193 | // synopsys translate_on | |
194 | .rst (rst_l_active_high), | |
195 | .rst_val (reset_int_cntrl_num[3]), | |
196 | .csr_ld (w_ld), | |
197 | .csr_data (csrbus_wr_data[9]), | |
198 | .rw_alias (1'b1), | |
199 | .rw1c_alias (1'b0), | |
200 | .rw1s_alias (1'b0), | |
201 | .hw_ld (1'b0), | |
202 | .hw_data (1'b0), | |
203 | .cp (clk), | |
204 | .q (interrupt_mapping_43_csrbus_read_data[9]) | |
205 | ); | |
206 | ||
207 | assign interrupt_mapping_43_csrbus_read_data[10] = 1'b0; // bit 10 | |
208 | assign interrupt_mapping_43_csrbus_read_data[11] = 1'b0; // bit 11 | |
209 | assign interrupt_mapping_43_csrbus_read_data[12] = 1'b0; // bit 12 | |
210 | assign interrupt_mapping_43_csrbus_read_data[13] = 1'b0; // bit 13 | |
211 | assign interrupt_mapping_43_csrbus_read_data[14] = 1'b0; // bit 14 | |
212 | assign interrupt_mapping_43_csrbus_read_data[15] = 1'b0; // bit 15 | |
213 | assign interrupt_mapping_43_csrbus_read_data[16] = 1'b0; // bit 16 | |
214 | assign interrupt_mapping_43_csrbus_read_data[17] = 1'b0; // bit 17 | |
215 | assign interrupt_mapping_43_csrbus_read_data[18] = 1'b0; // bit 18 | |
216 | assign interrupt_mapping_43_csrbus_read_data[19] = 1'b0; // bit 19 | |
217 | assign interrupt_mapping_43_csrbus_read_data[20] = 1'b0; // bit 20 | |
218 | assign interrupt_mapping_43_csrbus_read_data[21] = 1'b0; // bit 21 | |
219 | assign interrupt_mapping_43_csrbus_read_data[22] = 1'b0; // bit 22 | |
220 | assign interrupt_mapping_43_csrbus_read_data[23] = 1'b0; // bit 23 | |
221 | assign interrupt_mapping_43_csrbus_read_data[24] = 1'b0; // bit 24 | |
222 | // bit 25 | |
223 | csr_sw csr_sw_25 | |
224 | ( | |
225 | // synopsys translate_off | |
226 | .omni_ld (omni_ld), | |
227 | .omni_data (omni_data[25]), | |
228 | .omni_rw_alias (1'b1), | |
229 | .omni_rw1c_alias (1'b0), | |
230 | .omni_rw1s_alias (1'b0), | |
231 | // synopsys translate_on | |
232 | .rst (rst_l_active_high), | |
233 | .rst_val (reset_t_id[0]), | |
234 | .csr_ld (w_ld), | |
235 | .csr_data (csrbus_wr_data[25]), | |
236 | .rw_alias (1'b1), | |
237 | .rw1c_alias (1'b0), | |
238 | .rw1s_alias (1'b0), | |
239 | .hw_ld (1'b0), | |
240 | .hw_data (1'b0), | |
241 | .cp (clk), | |
242 | .q (interrupt_mapping_43_csrbus_read_data[25]) | |
243 | ); | |
244 | ||
245 | // bit 26 | |
246 | csr_sw csr_sw_26 | |
247 | ( | |
248 | // synopsys translate_off | |
249 | .omni_ld (omni_ld), | |
250 | .omni_data (omni_data[26]), | |
251 | .omni_rw_alias (1'b1), | |
252 | .omni_rw1c_alias (1'b0), | |
253 | .omni_rw1s_alias (1'b0), | |
254 | // synopsys translate_on | |
255 | .rst (rst_l_active_high), | |
256 | .rst_val (reset_t_id[1]), | |
257 | .csr_ld (w_ld), | |
258 | .csr_data (csrbus_wr_data[26]), | |
259 | .rw_alias (1'b1), | |
260 | .rw1c_alias (1'b0), | |
261 | .rw1s_alias (1'b0), | |
262 | .hw_ld (1'b0), | |
263 | .hw_data (1'b0), | |
264 | .cp (clk), | |
265 | .q (interrupt_mapping_43_csrbus_read_data[26]) | |
266 | ); | |
267 | ||
268 | // bit 27 | |
269 | csr_sw csr_sw_27 | |
270 | ( | |
271 | // synopsys translate_off | |
272 | .omni_ld (omni_ld), | |
273 | .omni_data (omni_data[27]), | |
274 | .omni_rw_alias (1'b1), | |
275 | .omni_rw1c_alias (1'b0), | |
276 | .omni_rw1s_alias (1'b0), | |
277 | // synopsys translate_on | |
278 | .rst (rst_l_active_high), | |
279 | .rst_val (reset_t_id[2]), | |
280 | .csr_ld (w_ld), | |
281 | .csr_data (csrbus_wr_data[27]), | |
282 | .rw_alias (1'b1), | |
283 | .rw1c_alias (1'b0), | |
284 | .rw1s_alias (1'b0), | |
285 | .hw_ld (1'b0), | |
286 | .hw_data (1'b0), | |
287 | .cp (clk), | |
288 | .q (interrupt_mapping_43_csrbus_read_data[27]) | |
289 | ); | |
290 | ||
291 | // bit 28 | |
292 | csr_sw csr_sw_28 | |
293 | ( | |
294 | // synopsys translate_off | |
295 | .omni_ld (omni_ld), | |
296 | .omni_data (omni_data[28]), | |
297 | .omni_rw_alias (1'b1), | |
298 | .omni_rw1c_alias (1'b0), | |
299 | .omni_rw1s_alias (1'b0), | |
300 | // synopsys translate_on | |
301 | .rst (rst_l_active_high), | |
302 | .rst_val (reset_t_id[3]), | |
303 | .csr_ld (w_ld), | |
304 | .csr_data (csrbus_wr_data[28]), | |
305 | .rw_alias (1'b1), | |
306 | .rw1c_alias (1'b0), | |
307 | .rw1s_alias (1'b0), | |
308 | .hw_ld (1'b0), | |
309 | .hw_data (1'b0), | |
310 | .cp (clk), | |
311 | .q (interrupt_mapping_43_csrbus_read_data[28]) | |
312 | ); | |
313 | ||
314 | // bit 29 | |
315 | csr_sw csr_sw_29 | |
316 | ( | |
317 | // synopsys translate_off | |
318 | .omni_ld (omni_ld), | |
319 | .omni_data (omni_data[29]), | |
320 | .omni_rw_alias (1'b1), | |
321 | .omni_rw1c_alias (1'b0), | |
322 | .omni_rw1s_alias (1'b0), | |
323 | // synopsys translate_on | |
324 | .rst (rst_l_active_high), | |
325 | .rst_val (reset_t_id[4]), | |
326 | .csr_ld (w_ld), | |
327 | .csr_data (csrbus_wr_data[29]), | |
328 | .rw_alias (1'b1), | |
329 | .rw1c_alias (1'b0), | |
330 | .rw1s_alias (1'b0), | |
331 | .hw_ld (1'b0), | |
332 | .hw_data (1'b0), | |
333 | .cp (clk), | |
334 | .q (interrupt_mapping_43_csrbus_read_data[29]) | |
335 | ); | |
336 | ||
337 | // bit 30 | |
338 | csr_sw csr_sw_30 | |
339 | ( | |
340 | // synopsys translate_off | |
341 | .omni_ld (omni_ld), | |
342 | .omni_data (omni_data[30]), | |
343 | .omni_rw_alias (1'b1), | |
344 | .omni_rw1c_alias (1'b0), | |
345 | .omni_rw1s_alias (1'b0), | |
346 | // synopsys translate_on | |
347 | .rst (rst_l_active_high), | |
348 | .rst_val (reset_t_id[5]), | |
349 | .csr_ld (w_ld), | |
350 | .csr_data (csrbus_wr_data[30]), | |
351 | .rw_alias (1'b1), | |
352 | .rw1c_alias (1'b0), | |
353 | .rw1s_alias (1'b0), | |
354 | .hw_ld (1'b0), | |
355 | .hw_data (1'b0), | |
356 | .cp (clk), | |
357 | .q (interrupt_mapping_43_csrbus_read_data[30]) | |
358 | ); | |
359 | ||
360 | // bit 31 | |
361 | csr_sw csr_sw_31 | |
362 | ( | |
363 | // synopsys translate_off | |
364 | .omni_ld (omni_ld), | |
365 | .omni_data (omni_data[31]), | |
366 | .omni_rw_alias (1'b1), | |
367 | .omni_rw1c_alias (1'b0), | |
368 | .omni_rw1s_alias (1'b0), | |
369 | // synopsys translate_on | |
370 | .rst (rst_l_active_high), | |
371 | .rst_val (reset_v[0]), | |
372 | .csr_ld (w_ld), | |
373 | .csr_data (csrbus_wr_data[31]), | |
374 | .rw_alias (1'b1), | |
375 | .rw1c_alias (1'b0), | |
376 | .rw1s_alias (1'b0), | |
377 | .hw_ld (1'b0), | |
378 | .hw_data (1'b0), | |
379 | .cp (clk), | |
380 | .q (interrupt_mapping_43_csrbus_read_data[31]) | |
381 | ); | |
382 | ||
383 | assign interrupt_mapping_43_csrbus_read_data[32] = 1'b0; // bit 32 | |
384 | assign interrupt_mapping_43_csrbus_read_data[33] = 1'b0; // bit 33 | |
385 | assign interrupt_mapping_43_csrbus_read_data[34] = 1'b0; // bit 34 | |
386 | assign interrupt_mapping_43_csrbus_read_data[35] = 1'b0; // bit 35 | |
387 | assign interrupt_mapping_43_csrbus_read_data[36] = 1'b0; // bit 36 | |
388 | assign interrupt_mapping_43_csrbus_read_data[37] = 1'b0; // bit 37 | |
389 | assign interrupt_mapping_43_csrbus_read_data[38] = 1'b0; // bit 38 | |
390 | assign interrupt_mapping_43_csrbus_read_data[39] = 1'b0; // bit 39 | |
391 | assign interrupt_mapping_43_csrbus_read_data[40] = 1'b0; // bit 40 | |
392 | assign interrupt_mapping_43_csrbus_read_data[41] = 1'b0; // bit 41 | |
393 | assign interrupt_mapping_43_csrbus_read_data[42] = 1'b0; // bit 42 | |
394 | assign interrupt_mapping_43_csrbus_read_data[43] = 1'b0; // bit 43 | |
395 | assign interrupt_mapping_43_csrbus_read_data[44] = 1'b0; // bit 44 | |
396 | assign interrupt_mapping_43_csrbus_read_data[45] = 1'b0; // bit 45 | |
397 | assign interrupt_mapping_43_csrbus_read_data[46] = 1'b0; // bit 46 | |
398 | assign interrupt_mapping_43_csrbus_read_data[47] = 1'b0; // bit 47 | |
399 | assign interrupt_mapping_43_csrbus_read_data[48] = 1'b0; // bit 48 | |
400 | assign interrupt_mapping_43_csrbus_read_data[49] = 1'b0; // bit 49 | |
401 | assign interrupt_mapping_43_csrbus_read_data[50] = 1'b0; // bit 50 | |
402 | assign interrupt_mapping_43_csrbus_read_data[51] = 1'b0; // bit 51 | |
403 | assign interrupt_mapping_43_csrbus_read_data[52] = 1'b0; // bit 52 | |
404 | assign interrupt_mapping_43_csrbus_read_data[53] = 1'b0; // bit 53 | |
405 | assign interrupt_mapping_43_csrbus_read_data[54] = 1'b0; // bit 54 | |
406 | assign interrupt_mapping_43_csrbus_read_data[55] = 1'b0; // bit 55 | |
407 | assign interrupt_mapping_43_csrbus_read_data[56] = 1'b0; // bit 56 | |
408 | assign interrupt_mapping_43_csrbus_read_data[57] = 1'b0; // bit 57 | |
409 | assign interrupt_mapping_43_csrbus_read_data[58] = 1'b0; // bit 58 | |
410 | assign interrupt_mapping_43_csrbus_read_data[59] = 1'b0; // bit 59 | |
411 | assign interrupt_mapping_43_csrbus_read_data[60] = 1'b0; // bit 60 | |
412 | assign interrupt_mapping_43_csrbus_read_data[61] = 1'b0; // bit 61 | |
413 | assign interrupt_mapping_43_csrbus_read_data[62] = 1'b0; // bit 62 | |
414 | // bit 63 | |
415 | csr_sw csr_sw_63 | |
416 | ( | |
417 | // synopsys translate_off | |
418 | .omni_ld (omni_ld), | |
419 | .omni_data (omni_data[63]), | |
420 | .omni_rw_alias (1'b1), | |
421 | .omni_rw1c_alias (1'b0), | |
422 | .omni_rw1s_alias (1'b0), | |
423 | // synopsys translate_on | |
424 | .rst (rst_l_active_high), | |
425 | .rst_val (reset_mdo_mode[0]), | |
426 | .csr_ld (w_ld), | |
427 | .csr_data (csrbus_wr_data[63]), | |
428 | .rw_alias (1'b1), | |
429 | .rw1c_alias (1'b0), | |
430 | .rw1s_alias (1'b0), | |
431 | .hw_ld (1'b0), | |
432 | .hw_data (1'b0), | |
433 | .cp (clk), | |
434 | .q (interrupt_mapping_43_csrbus_read_data[63]) | |
435 | ); | |
436 | ||
437 | ||
438 | endmodule // dmu_imu_iss_csr_interrupt_mapping_43_entry |