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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: l2b_l2defu_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module l2b_l2defu_ctl ( | |
36 | efu_hdr_write_data, | |
37 | efu_hdr_xfer_en, | |
38 | efu_hdr_clr, | |
39 | hdr_efu_read_data, | |
40 | hdr_efu_xfer_en, | |
41 | hdr_sram_rvalue, | |
42 | hdr_sram_rid, | |
43 | hdr_sram_wr_en, | |
44 | hdr_sram_red_clr, | |
45 | sram_hdr_read_data, | |
46 | io_cmp_sync_en, | |
47 | cmp_io_sync_en, | |
48 | l2clk, | |
49 | tcu_pce_ov, | |
50 | tcu_aclk, | |
51 | tcu_bclk, | |
52 | tcu_scan_en, | |
53 | tcu_clk_stop, | |
54 | scan_in, | |
55 | scan_out); | |
56 | wire [9:0] int_hdr_sram_rvalue; | |
57 | wire [4:0] unused; | |
58 | ||
59 | ||
60 | ||
61 | input efu_hdr_write_data; | |
62 | input efu_hdr_xfer_en; | |
63 | input efu_hdr_clr; | |
64 | output hdr_efu_read_data; | |
65 | output hdr_efu_xfer_en; | |
66 | output [9:0] hdr_sram_rvalue; | |
67 | output [6:0] hdr_sram_rid; | |
68 | output hdr_sram_wr_en; | |
69 | output hdr_sram_red_clr; | |
70 | input [9:0] sram_hdr_read_data; | |
71 | input io_cmp_sync_en; | |
72 | input cmp_io_sync_en; | |
73 | input l2clk; | |
74 | input tcu_pce_ov; | |
75 | input tcu_aclk; | |
76 | input tcu_bclk; | |
77 | input tcu_scan_en; | |
78 | input tcu_clk_stop; | |
79 | input scan_in; | |
80 | output scan_out; | |
81 | ||
82 | ||
83 | assign hdr_sram_rvalue[9:0] = {int_hdr_sram_rvalue[0],int_hdr_sram_rvalue[0], | |
84 | int_hdr_sram_rvalue[8:1]}; | |
85 | ||
86 | ||
87 | ||
88 | ||
89 | n2_efuhdr1_ctl efuse_l2d_header | |
90 | ( | |
91 | .efu_hdr_write_data (efu_hdr_write_data), | |
92 | .efu_hdr_xfer_en (efu_hdr_xfer_en), | |
93 | .efu_hdr_clr (efu_hdr_clr), | |
94 | .hdr_efu_read_data (hdr_efu_read_data), | |
95 | .hdr_efu_xfer_en (hdr_efu_xfer_en), | |
96 | .hdr_sram_rvalue ({unused[4],int_hdr_sram_rvalue[9:0]}), | |
97 | .hdr_sram_rid ({unused[3:0],hdr_sram_rid[6:0]}), | |
98 | .hdr_sram_wr_en (hdr_sram_wr_en), | |
99 | .hdr_sram_red_clr (hdr_sram_red_clr), | |
100 | .sram_hdr_read_data ({1'b0,sram_hdr_read_data[9:0]}), | |
101 | .cmp_io_sync_en (cmp_io_sync_en), | |
102 | .io_cmp_sync_en (io_cmp_sync_en), | |
103 | .l2clk (l2clk), | |
104 | .tcu_pce_ov (tcu_pce_ov), | |
105 | .tcu_aclk (tcu_aclk), | |
106 | .tcu_bclk (tcu_bclk), | |
107 | .tcu_scan_en (tcu_scan_en), | |
108 | .tcu_clk_stop (tcu_clk_stop), | |
109 | .scan_in (scan_in), | |
110 | .scan_out (scan_out) | |
111 | ); | |
112 | ||
113 | endmodule | |
114 | ||
115 | ||
116 | ||
117 | // any PARAMS parms go into naming of macro | |
118 | ||
119 | module l2b_l2defu_ctl_l1clkhdr_ctl_macro ( | |
120 | l2clk, | |
121 | l1en, | |
122 | pce_ov, | |
123 | stop, | |
124 | se, | |
125 | l1clk); | |
126 | ||
127 | ||
128 | input l2clk; | |
129 | input l1en; | |
130 | input pce_ov; | |
131 | input stop; | |
132 | input se; | |
133 | output l1clk; | |
134 | ||
135 | ||
136 | ||
137 | ||
138 | ||
139 | cl_sc1_l1hdr_8x c_0 ( | |
140 | ||
141 | ||
142 | .l2clk(l2clk), | |
143 | .pce(l1en), | |
144 | .l1clk(l1clk), | |
145 | .se(se), | |
146 | .pce_ov(pce_ov), | |
147 | .stop(stop) | |
148 | ); | |
149 | ||
150 | ||
151 | ||
152 | endmodule | |
153 | ||
154 | ||
155 | ||
156 | ||
157 | ||
158 | ||
159 | ||
160 | ||
161 | ||
162 | ||
163 | ||
164 | ||
165 | ||
166 | // any PARAMS parms go into naming of macro | |
167 | ||
168 | module l2b_l2defu_ctl_msff_ctl_macro__width_1 ( | |
169 | din, | |
170 | l1clk, | |
171 | scan_in, | |
172 | siclk, | |
173 | soclk, | |
174 | dout, | |
175 | scan_out); | |
176 | wire [0:0] fdin; | |
177 | ||
178 | input [0:0] din; | |
179 | input l1clk; | |
180 | input scan_in; | |
181 | ||
182 | ||
183 | input siclk; | |
184 | input soclk; | |
185 | ||
186 | output [0:0] dout; | |
187 | output scan_out; | |
188 | assign fdin[0:0] = din[0:0]; | |
189 | ||
190 | ||
191 | ||
192 | ||
193 | ||
194 | ||
195 | dff #(1) d0_0 ( | |
196 | .l1clk(l1clk), | |
197 | .siclk(siclk), | |
198 | .soclk(soclk), | |
199 | .d(fdin[0:0]), | |
200 | .si(scan_in), | |
201 | .so(scan_out), | |
202 | .q(dout[0:0]) | |
203 | ); | |
204 | ||
205 | ||
206 | ||
207 | ||
208 | ||
209 | ||
210 | ||
211 | ||
212 | ||
213 | ||
214 | ||
215 | ||
216 | endmodule | |
217 | ||
218 | ||
219 | ||
220 | ||
221 | ||
222 | ||
223 | ||
224 | ||
225 | ||
226 | ||
227 | ||
228 | ||
229 | ||
230 | // any PARAMS parms go into naming of macro | |
231 | ||
232 | module l2b_l2defu_ctl_msff_ctl_macro__en_1__width_4 ( | |
233 | din, | |
234 | en, | |
235 | l1clk, | |
236 | scan_in, | |
237 | siclk, | |
238 | soclk, | |
239 | dout, | |
240 | scan_out); | |
241 | wire [3:0] fdin; | |
242 | wire [2:0] so; | |
243 | ||
244 | input [3:0] din; | |
245 | input en; | |
246 | input l1clk; | |
247 | input scan_in; | |
248 | ||
249 | ||
250 | input siclk; | |
251 | input soclk; | |
252 | ||
253 | output [3:0] dout; | |
254 | output scan_out; | |
255 | assign fdin[3:0] = (din[3:0] & {4{en}}) | (dout[3:0] & ~{4{en}}); | |
256 | ||
257 | ||
258 | ||
259 | ||
260 | ||
261 | ||
262 | dff #(4) d0_0 ( | |
263 | .l1clk(l1clk), | |
264 | .siclk(siclk), | |
265 | .soclk(soclk), | |
266 | .d(fdin[3:0]), | |
267 | .si({scan_in,so[2:0]}), | |
268 | .so({so[2:0],scan_out}), | |
269 | .q(dout[3:0]) | |
270 | ); | |
271 | ||
272 | ||
273 | ||
274 | ||
275 | ||
276 | ||
277 | ||
278 | ||
279 | ||
280 | ||
281 | ||
282 | ||
283 | endmodule | |
284 | ||
285 | ||
286 | ||
287 | ||
288 | ||
289 | ||
290 | ||
291 | ||
292 | ||
293 | ||
294 | ||
295 | ||
296 | ||
297 | // any PARAMS parms go into naming of macro | |
298 | ||
299 | module l2b_l2defu_ctl_msff_ctl_macro__en_1__width_22 ( | |
300 | din, | |
301 | en, | |
302 | l1clk, | |
303 | scan_in, | |
304 | siclk, | |
305 | soclk, | |
306 | dout, | |
307 | scan_out); | |
308 | wire [21:0] fdin; | |
309 | wire [20:0] so; | |
310 | ||
311 | input [21:0] din; | |
312 | input en; | |
313 | input l1clk; | |
314 | input scan_in; | |
315 | ||
316 | ||
317 | input siclk; | |
318 | input soclk; | |
319 | ||
320 | output [21:0] dout; | |
321 | output scan_out; | |
322 | assign fdin[21:0] = (din[21:0] & {22{en}}) | (dout[21:0] & ~{22{en}}); | |
323 | ||
324 | ||
325 | ||
326 | ||
327 | ||
328 | ||
329 | dff #(22) d0_0 ( | |
330 | .l1clk(l1clk), | |
331 | .siclk(siclk), | |
332 | .soclk(soclk), | |
333 | .d(fdin[21:0]), | |
334 | .si({scan_in,so[20:0]}), | |
335 | .so({so[20:0],scan_out}), | |
336 | .q(dout[21:0]) | |
337 | ); | |
338 | ||
339 | ||
340 | ||
341 | ||
342 | ||
343 | ||
344 | ||
345 | ||
346 | ||
347 | ||
348 | ||
349 | ||
350 | endmodule | |
351 | ||
352 | ||
353 | ||
354 | ||
355 | ||
356 | ||
357 | ||
358 | ||
359 | ||
360 | ||
361 | ||
362 | ||
363 | ||
364 | // any PARAMS parms go into naming of macro | |
365 | ||
366 | module l2b_l2defu_ctl_msff_ctl_macro__en_1__width_1 ( | |
367 | din, | |
368 | en, | |
369 | l1clk, | |
370 | scan_in, | |
371 | siclk, | |
372 | soclk, | |
373 | dout, | |
374 | scan_out); | |
375 | wire [0:0] fdin; | |
376 | ||
377 | input [0:0] din; | |
378 | input en; | |
379 | input l1clk; | |
380 | input scan_in; | |
381 | ||
382 | ||
383 | input siclk; | |
384 | input soclk; | |
385 | ||
386 | output [0:0] dout; | |
387 | output scan_out; | |
388 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); | |
389 | ||
390 | ||
391 | ||
392 | ||
393 | ||
394 | ||
395 | dff #(1) d0_0 ( | |
396 | .l1clk(l1clk), | |
397 | .siclk(siclk), | |
398 | .soclk(soclk), | |
399 | .d(fdin[0:0]), | |
400 | .si(scan_in), | |
401 | .so(scan_out), | |
402 | .q(dout[0:0]) | |
403 | ); | |
404 | ||
405 | ||
406 | ||
407 | ||
408 | ||
409 | ||
410 | ||
411 | ||
412 | ||
413 | ||
414 | ||
415 | ||
416 | endmodule | |
417 | ||
418 | ||
419 | ||
420 | ||
421 | ||
422 | ||
423 | ||
424 | ||
425 | ||
426 | ||
427 | ||
428 | ||
429 | ||
430 | // any PARAMS parms go into naming of macro | |
431 | ||
432 | module l2b_l2defu_ctl_msff_ctl_macro__en_1__width_5 ( | |
433 | din, | |
434 | en, | |
435 | l1clk, | |
436 | scan_in, | |
437 | siclk, | |
438 | soclk, | |
439 | dout, | |
440 | scan_out); | |
441 | wire [4:0] fdin; | |
442 | wire [3:0] so; | |
443 | ||
444 | input [4:0] din; | |
445 | input en; | |
446 | input l1clk; | |
447 | input scan_in; | |
448 | ||
449 | ||
450 | input siclk; | |
451 | input soclk; | |
452 | ||
453 | output [4:0] dout; | |
454 | output scan_out; | |
455 | assign fdin[4:0] = (din[4:0] & {5{en}}) | (dout[4:0] & ~{5{en}}); | |
456 | ||
457 | ||
458 | ||
459 | ||
460 | ||
461 | ||
462 | dff #(5) d0_0 ( | |
463 | .l1clk(l1clk), | |
464 | .siclk(siclk), | |
465 | .soclk(soclk), | |
466 | .d(fdin[4:0]), | |
467 | .si({scan_in,so[3:0]}), | |
468 | .so({so[3:0],scan_out}), | |
469 | .q(dout[4:0]) | |
470 | ); | |
471 | ||
472 | ||
473 | ||
474 | ||
475 | ||
476 | ||
477 | ||
478 | ||
479 | ||
480 | ||
481 | ||
482 | ||
483 | endmodule | |
484 | ||
485 | ||
486 | ||
487 | ||
488 | ||
489 | ||
490 | ||
491 | ||
492 | ||
493 | // Description: Spare gate macro for control blocks | |
494 | // | |
495 | // Param num controls the number of times the macro is added | |
496 | // flops=0 can be used to use only combination spare logic | |
497 | ||
498 | ||
499 | module l2b_l2defu_ctl_spare_ctl_macro__num_4 ( | |
500 | l1clk, | |
501 | scan_in, | |
502 | siclk, | |
503 | soclk, | |
504 | scan_out); | |
505 | wire si_0; | |
506 | wire so_0; | |
507 | wire spare0_flop_unused; | |
508 | wire spare0_buf_32x_unused; | |
509 | wire spare0_nand3_8x_unused; | |
510 | wire spare0_inv_8x_unused; | |
511 | wire spare0_aoi22_4x_unused; | |
512 | wire spare0_buf_8x_unused; | |
513 | wire spare0_oai22_4x_unused; | |
514 | wire spare0_inv_16x_unused; | |
515 | wire spare0_nand2_16x_unused; | |
516 | wire spare0_nor3_4x_unused; | |
517 | wire spare0_nand2_8x_unused; | |
518 | wire spare0_buf_16x_unused; | |
519 | wire spare0_nor2_16x_unused; | |
520 | wire spare0_inv_32x_unused; | |
521 | wire si_1; | |
522 | wire so_1; | |
523 | wire spare1_flop_unused; | |
524 | wire spare1_buf_32x_unused; | |
525 | wire spare1_nand3_8x_unused; | |
526 | wire spare1_inv_8x_unused; | |
527 | wire spare1_aoi22_4x_unused; | |
528 | wire spare1_buf_8x_unused; | |
529 | wire spare1_oai22_4x_unused; | |
530 | wire spare1_inv_16x_unused; | |
531 | wire spare1_nand2_16x_unused; | |
532 | wire spare1_nor3_4x_unused; | |
533 | wire spare1_nand2_8x_unused; | |
534 | wire spare1_buf_16x_unused; | |
535 | wire spare1_nor2_16x_unused; | |
536 | wire spare1_inv_32x_unused; | |
537 | wire si_2; | |
538 | wire so_2; | |
539 | wire spare2_flop_unused; | |
540 | wire spare2_buf_32x_unused; | |
541 | wire spare2_nand3_8x_unused; | |
542 | wire spare2_inv_8x_unused; | |
543 | wire spare2_aoi22_4x_unused; | |
544 | wire spare2_buf_8x_unused; | |
545 | wire spare2_oai22_4x_unused; | |
546 | wire spare2_inv_16x_unused; | |
547 | wire spare2_nand2_16x_unused; | |
548 | wire spare2_nor3_4x_unused; | |
549 | wire spare2_nand2_8x_unused; | |
550 | wire spare2_buf_16x_unused; | |
551 | wire spare2_nor2_16x_unused; | |
552 | wire spare2_inv_32x_unused; | |
553 | wire si_3; | |
554 | wire so_3; | |
555 | wire spare3_flop_unused; | |
556 | wire spare3_buf_32x_unused; | |
557 | wire spare3_nand3_8x_unused; | |
558 | wire spare3_inv_8x_unused; | |
559 | wire spare3_aoi22_4x_unused; | |
560 | wire spare3_buf_8x_unused; | |
561 | wire spare3_oai22_4x_unused; | |
562 | wire spare3_inv_16x_unused; | |
563 | wire spare3_nand2_16x_unused; | |
564 | wire spare3_nor3_4x_unused; | |
565 | wire spare3_nand2_8x_unused; | |
566 | wire spare3_buf_16x_unused; | |
567 | wire spare3_nor2_16x_unused; | |
568 | wire spare3_inv_32x_unused; | |
569 | ||
570 | ||
571 | input l1clk; | |
572 | input scan_in; | |
573 | input siclk; | |
574 | input soclk; | |
575 | output scan_out; | |
576 | ||
577 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
578 | .siclk(siclk), | |
579 | .soclk(soclk), | |
580 | .si(si_0), | |
581 | .so(so_0), | |
582 | .d(1'b0), | |
583 | .q(spare0_flop_unused)); | |
584 | assign si_0 = scan_in; | |
585 | ||
586 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
587 | .out(spare0_buf_32x_unused)); | |
588 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
589 | .in1(1'b1), | |
590 | .in2(1'b1), | |
591 | .out(spare0_nand3_8x_unused)); | |
592 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
593 | .out(spare0_inv_8x_unused)); | |
594 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
595 | .in01(1'b1), | |
596 | .in10(1'b1), | |
597 | .in11(1'b1), | |
598 | .out(spare0_aoi22_4x_unused)); | |
599 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
600 | .out(spare0_buf_8x_unused)); | |
601 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
602 | .in01(1'b1), | |
603 | .in10(1'b1), | |
604 | .in11(1'b1), | |
605 | .out(spare0_oai22_4x_unused)); | |
606 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
607 | .out(spare0_inv_16x_unused)); | |
608 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
609 | .in1(1'b1), | |
610 | .out(spare0_nand2_16x_unused)); | |
611 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
612 | .in1(1'b0), | |
613 | .in2(1'b0), | |
614 | .out(spare0_nor3_4x_unused)); | |
615 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
616 | .in1(1'b1), | |
617 | .out(spare0_nand2_8x_unused)); | |
618 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
619 | .out(spare0_buf_16x_unused)); | |
620 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
621 | .in1(1'b0), | |
622 | .out(spare0_nor2_16x_unused)); | |
623 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
624 | .out(spare0_inv_32x_unused)); | |
625 | ||
626 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), | |
627 | .siclk(siclk), | |
628 | .soclk(soclk), | |
629 | .si(si_1), | |
630 | .so(so_1), | |
631 | .d(1'b0), | |
632 | .q(spare1_flop_unused)); | |
633 | assign si_1 = so_0; | |
634 | ||
635 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
636 | .out(spare1_buf_32x_unused)); | |
637 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
638 | .in1(1'b1), | |
639 | .in2(1'b1), | |
640 | .out(spare1_nand3_8x_unused)); | |
641 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
642 | .out(spare1_inv_8x_unused)); | |
643 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
644 | .in01(1'b1), | |
645 | .in10(1'b1), | |
646 | .in11(1'b1), | |
647 | .out(spare1_aoi22_4x_unused)); | |
648 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
649 | .out(spare1_buf_8x_unused)); | |
650 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
651 | .in01(1'b1), | |
652 | .in10(1'b1), | |
653 | .in11(1'b1), | |
654 | .out(spare1_oai22_4x_unused)); | |
655 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
656 | .out(spare1_inv_16x_unused)); | |
657 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
658 | .in1(1'b1), | |
659 | .out(spare1_nand2_16x_unused)); | |
660 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
661 | .in1(1'b0), | |
662 | .in2(1'b0), | |
663 | .out(spare1_nor3_4x_unused)); | |
664 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
665 | .in1(1'b1), | |
666 | .out(spare1_nand2_8x_unused)); | |
667 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
668 | .out(spare1_buf_16x_unused)); | |
669 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
670 | .in1(1'b0), | |
671 | .out(spare1_nor2_16x_unused)); | |
672 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
673 | .out(spare1_inv_32x_unused)); | |
674 | ||
675 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), | |
676 | .siclk(siclk), | |
677 | .soclk(soclk), | |
678 | .si(si_2), | |
679 | .so(so_2), | |
680 | .d(1'b0), | |
681 | .q(spare2_flop_unused)); | |
682 | assign si_2 = so_1; | |
683 | ||
684 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), | |
685 | .out(spare2_buf_32x_unused)); | |
686 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), | |
687 | .in1(1'b1), | |
688 | .in2(1'b1), | |
689 | .out(spare2_nand3_8x_unused)); | |
690 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), | |
691 | .out(spare2_inv_8x_unused)); | |
692 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), | |
693 | .in01(1'b1), | |
694 | .in10(1'b1), | |
695 | .in11(1'b1), | |
696 | .out(spare2_aoi22_4x_unused)); | |
697 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), | |
698 | .out(spare2_buf_8x_unused)); | |
699 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), | |
700 | .in01(1'b1), | |
701 | .in10(1'b1), | |
702 | .in11(1'b1), | |
703 | .out(spare2_oai22_4x_unused)); | |
704 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), | |
705 | .out(spare2_inv_16x_unused)); | |
706 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), | |
707 | .in1(1'b1), | |
708 | .out(spare2_nand2_16x_unused)); | |
709 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), | |
710 | .in1(1'b0), | |
711 | .in2(1'b0), | |
712 | .out(spare2_nor3_4x_unused)); | |
713 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), | |
714 | .in1(1'b1), | |
715 | .out(spare2_nand2_8x_unused)); | |
716 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), | |
717 | .out(spare2_buf_16x_unused)); | |
718 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), | |
719 | .in1(1'b0), | |
720 | .out(spare2_nor2_16x_unused)); | |
721 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), | |
722 | .out(spare2_inv_32x_unused)); | |
723 | ||
724 | cl_sc1_msff_8x spare3_flop (.l1clk(l1clk), | |
725 | .siclk(siclk), | |
726 | .soclk(soclk), | |
727 | .si(si_3), | |
728 | .so(so_3), | |
729 | .d(1'b0), | |
730 | .q(spare3_flop_unused)); | |
731 | assign si_3 = so_2; | |
732 | ||
733 | cl_u1_buf_32x spare3_buf_32x (.in(1'b1), | |
734 | .out(spare3_buf_32x_unused)); | |
735 | cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1), | |
736 | .in1(1'b1), | |
737 | .in2(1'b1), | |
738 | .out(spare3_nand3_8x_unused)); | |
739 | cl_u1_inv_8x spare3_inv_8x (.in(1'b1), | |
740 | .out(spare3_inv_8x_unused)); | |
741 | cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1), | |
742 | .in01(1'b1), | |
743 | .in10(1'b1), | |
744 | .in11(1'b1), | |
745 | .out(spare3_aoi22_4x_unused)); | |
746 | cl_u1_buf_8x spare3_buf_8x (.in(1'b1), | |
747 | .out(spare3_buf_8x_unused)); | |
748 | cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1), | |
749 | .in01(1'b1), | |
750 | .in10(1'b1), | |
751 | .in11(1'b1), | |
752 | .out(spare3_oai22_4x_unused)); | |
753 | cl_u1_inv_16x spare3_inv_16x (.in(1'b1), | |
754 | .out(spare3_inv_16x_unused)); | |
755 | cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1), | |
756 | .in1(1'b1), | |
757 | .out(spare3_nand2_16x_unused)); | |
758 | cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0), | |
759 | .in1(1'b0), | |
760 | .in2(1'b0), | |
761 | .out(spare3_nor3_4x_unused)); | |
762 | cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1), | |
763 | .in1(1'b1), | |
764 | .out(spare3_nand2_8x_unused)); | |
765 | cl_u1_buf_16x spare3_buf_16x (.in(1'b1), | |
766 | .out(spare3_buf_16x_unused)); | |
767 | cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0), | |
768 | .in1(1'b0), | |
769 | .out(spare3_nor2_16x_unused)); | |
770 | cl_u1_inv_32x spare3_inv_32x (.in(1'b1), | |
771 | .out(spare3_inv_32x_unused)); | |
772 | assign scan_out = so_3; | |
773 | ||
774 | ||
775 | ||
776 | endmodule | |
777 |