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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: l2t_l2drpt_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module l2t_l2drpt_dp ( | |
36 | l2clk, | |
37 | tcu_pce_ov, | |
38 | tcu_aclk, | |
39 | tcu_bclk, | |
40 | tcu_scan_en, | |
41 | tcu_clk_stop, | |
42 | scan_in, | |
43 | scan_out, | |
44 | arb_l2drpt_waysel_gate_c1, | |
45 | mbist_run, | |
46 | misbuf_tag_hit_unqual_c2, | |
47 | arb_inst_vld_c2_prev, | |
48 | csr_l2_bypass_mode_on, | |
49 | arb_decdp_ld64_inst_c1, | |
50 | tag_way_sel_c2, | |
51 | tagctl_l2drpt_mux4_way_sel_c1, | |
52 | vlddir_vuad_valid_c2, | |
53 | tag_rdma_gate_off_c2, | |
54 | tag_l2d_way_sel_c2, | |
55 | tagdp_lru_way_sel_c3, | |
56 | arb_evict_vld_c2, | |
57 | tagdp_tag_par_err_c3); | |
58 | wire pce_ov; | |
59 | wire siclk; | |
60 | wire soclk; | |
61 | wire stop; | |
62 | wire se; | |
63 | wire ld64_l2_bypass_mode_on_c1; | |
64 | wire arb_inst_vld_c2_prev_n; | |
65 | wire [15:0] temp_way_sel_c2_n; | |
66 | wire mbist_run_r1_n; | |
67 | wire tagdp_tag_par_err_c3_n; | |
68 | wire tag_rdma_gate_off_c2_n; | |
69 | wire [15:0] temp_way_sel_c2; | |
70 | wire mbist_run_r1; | |
71 | wire ld64_l2_bypass_mode_on_c1_qual; | |
72 | wire arb_evict_vld_c2_qual; | |
73 | wire arb_inst_vld_c2_prev_qual; | |
74 | wire ff_all_signals_scanin; | |
75 | wire ff_all_signals_scanout; | |
76 | wire arb_waysel_gate_c2; | |
77 | wire arb_waysel_inst_vld_c2; | |
78 | wire ld64_l2_bypass_mode_on_c2; | |
79 | wire evict_unqual_vld_c3; | |
80 | wire term_2_qual; | |
81 | wire [15:0] hit_way_n; | |
82 | wire [15:0] replace_way_n; | |
83 | wire [15:0] tag_l2d_way_sel_c2_fnl_1; | |
84 | wire [15:0] tag_l2d_way_sel_c2_fnl_n; | |
85 | wire vld_mbf_miss_c2_1; | |
86 | wire vld_mbf_miss_c2_2; | |
87 | wire vld_mbf_miss_c2_3; | |
88 | wire vld_mbf_miss_c2_4; | |
89 | ||
90 | ||
91 | input l2clk; | |
92 | input tcu_pce_ov; | |
93 | input tcu_aclk; | |
94 | input tcu_bclk; | |
95 | input tcu_scan_en; | |
96 | input tcu_clk_stop; | |
97 | input scan_in; | |
98 | output scan_out; | |
99 | ||
100 | input arb_l2drpt_waysel_gate_c1; | |
101 | input mbist_run; | |
102 | input misbuf_tag_hit_unqual_c2; | |
103 | input arb_inst_vld_c2_prev; | |
104 | input csr_l2_bypass_mode_on; | |
105 | input arb_decdp_ld64_inst_c1; | |
106 | ||
107 | input [15:0] tag_way_sel_c2; // from the tag | |
108 | input [15:0] tagctl_l2drpt_mux4_way_sel_c1; // from the tag | |
109 | input [15:0] vlddir_vuad_valid_c2; // from vuad dp | |
110 | input tag_rdma_gate_off_c2; | |
111 | ||
112 | output [15:0] tag_l2d_way_sel_c2; | |
113 | input [15:0] tagdp_lru_way_sel_c3; | |
114 | ||
115 | ||
116 | input arb_evict_vld_c2; | |
117 | input tagdp_tag_par_err_c3; | |
118 | //input arb_waysel_gate_c2; | |
119 | ||
120 | assign pce_ov = tcu_pce_ov; | |
121 | assign siclk = tcu_aclk; | |
122 | assign soclk = tcu_bclk; | |
123 | assign stop = tcu_clk_stop; | |
124 | assign se = tcu_scan_en; | |
125 | ||
126 | ||
127 | ||
128 | l2t_l2drpt_dp_nor_macro__dnor_4x__ports_3__stack_2r__width_1 nor_ld64_l2_bypass_mode_on_c1 | |
129 | ( | |
130 | .dout (ld64_l2_bypass_mode_on_c1), | |
131 | .din0 (arb_decdp_ld64_inst_c1), | |
132 | .din1 (csr_l2_bypass_mode_on), | |
133 | .din2 (arb_inst_vld_c2_prev_n) | |
134 | ); | |
135 | ||
136 | ||
137 | l2t_l2drpt_dp_inv_macro__dinv_32x__width_20 inv_all_signals | |
138 | ( | |
139 | .dout ({temp_way_sel_c2_n[15:0], | |
140 | mbist_run_r1_n, | |
141 | tagdp_tag_par_err_c3_n, | |
142 | tag_rdma_gate_off_c2_n, | |
143 | arb_inst_vld_c2_prev_n}), | |
144 | .din ({temp_way_sel_c2[15:0], | |
145 | mbist_run_r1, | |
146 | tagdp_tag_par_err_c3, | |
147 | tag_rdma_gate_off_c2, | |
148 | arb_inst_vld_c2_prev}) | |
149 | ); | |
150 | ||
151 | ||
152 | l2t_l2drpt_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__width_3 mux_misc_signals | |
153 | ( | |
154 | .dout ({ld64_l2_bypass_mode_on_c1_qual,arb_evict_vld_c2_qual,arb_inst_vld_c2_prev_qual}), | |
155 | .din0 ({ld64_l2_bypass_mode_on_c1,arb_evict_vld_c2,arb_inst_vld_c2_prev}), | |
156 | .din1 (3'b0), | |
157 | .sel0 (mbist_run_r1_n), | |
158 | .sel1 (mbist_run_r1) | |
159 | ); | |
160 | ||
161 | l2t_l2drpt_dp_msff_macro__dmsff_32x__stack_26r__width_21 ff_all_signals | |
162 | ( | |
163 | .scan_in(ff_all_signals_scanin), | |
164 | .scan_out(ff_all_signals_scanout), | |
165 | .dout ({arb_waysel_gate_c2, | |
166 | arb_waysel_inst_vld_c2, | |
167 | temp_way_sel_c2[15:0], | |
168 | ld64_l2_bypass_mode_on_c2, | |
169 | evict_unqual_vld_c3, | |
170 | mbist_run_r1}), | |
171 | .din ({arb_l2drpt_waysel_gate_c1, | |
172 | arb_inst_vld_c2_prev_qual, | |
173 | tagctl_l2drpt_mux4_way_sel_c1[15:0], | |
174 | ld64_l2_bypass_mode_on_c1_qual, | |
175 | arb_evict_vld_c2_qual, | |
176 | mbist_run}), | |
177 | .clk (l2clk), | |
178 | .en (1'b1), | |
179 | .se(se), | |
180 | .siclk(siclk), | |
181 | .soclk(soclk), | |
182 | .pce_ov(pce_ov), | |
183 | .stop(stop) | |
184 | ); | |
185 | ||
186 | l2t_l2drpt_dp_and_macro__dinv_48x__dnand_16x__ports_3__stack_2r__width_1 and_term_2_qual | |
187 | ( | |
188 | .dout (term_2_qual), | |
189 | .din0 (ld64_l2_bypass_mode_on_c2), | |
190 | .din1 (tag_rdma_gate_off_c2_n), | |
191 | .din2 (arb_waysel_gate_c2) | |
192 | ); | |
193 | ||
194 | ||
195 | l2t_l2drpt_dp_nand_macro__dnand_24x__ports_3__stack_16r__width_16 nand_term_2 | |
196 | ( | |
197 | .dout (hit_way_n[15:0]), | |
198 | .din0 (tag_way_sel_c2[15:0]), | |
199 | .din1 (vlddir_vuad_valid_c2[15:0]), | |
200 | .din2 ({16{term_2_qual}}) | |
201 | ); | |
202 | ||
203 | ||
204 | l2t_l2drpt_dp_nand_macro__dnand_24x__ports_3__stack_16r__width_16 nand_term_3 | |
205 | ( | |
206 | .dout (replace_way_n[15:0]), | |
207 | .din0 (tagdp_lru_way_sel_c3[15:0]), | |
208 | .din1 ({16{evict_unqual_vld_c3}}), | |
209 | .din2 ({16{tagdp_tag_par_err_c3_n}}) | |
210 | ); | |
211 | l2t_l2drpt_dp_nand_macro__dnand_24x__ports_3__stack_16r__width_16 nand_level_1 | |
212 | ( | |
213 | .dout (tag_l2d_way_sel_c2_fnl_1[15:0]), | |
214 | .din0 (temp_way_sel_c2_n[15:0]), | |
215 | .din1 (hit_way_n[15:0]), | |
216 | .din2 (replace_way_n[15:0]) | |
217 | ); | |
218 | ||
219 | //nand_macro nand_vld_mbf_miss_c2 (width=4,stack=4r,dnand=32x) | |
220 | // ( | |
221 | // .dout (vld_mbf_miss_c2), | |
222 | // .din0 (misbuf_tag_hit_unqual_c2), | |
223 | // .din1 (4{arb_waysel_inst_vld_c2) | |
224 | // ); | |
225 | ||
226 | l2t_l2drpt_dp_nand_macro__dnand_32x__stack_16r__width_5 nand_tag_l2d_way_sel_c2_fnl_slice1 | |
227 | ( | |
228 | .dout ({tag_l2d_way_sel_c2_fnl_n[15:14],vld_mbf_miss_c2_1, tag_l2d_way_sel_c2_fnl_n[13:12]}), | |
229 | .din0 ({tag_l2d_way_sel_c2_fnl_1[15:14],misbuf_tag_hit_unqual_c2,tag_l2d_way_sel_c2_fnl_1[13:12]}), | |
230 | .din1 ({{2{vld_mbf_miss_c2_1}}, arb_waysel_inst_vld_c2, {2{vld_mbf_miss_c2_1}}}) | |
231 | ); | |
232 | ||
233 | ||
234 | l2t_l2drpt_dp_nand_macro__dnand_32x__stack_16r__width_5 nand_tag_l2d_way_sel_c2_fnl_slice2 | |
235 | ( | |
236 | .dout ({tag_l2d_way_sel_c2_fnl_n[11:10],vld_mbf_miss_c2_2, tag_l2d_way_sel_c2_fnl_n[9:8]}), | |
237 | .din0 ({tag_l2d_way_sel_c2_fnl_1[11:10],misbuf_tag_hit_unqual_c2,tag_l2d_way_sel_c2_fnl_1[9:8]}), | |
238 | .din1 ({{2{vld_mbf_miss_c2_2}}, arb_waysel_inst_vld_c2, {2{vld_mbf_miss_c2_2}}}) | |
239 | ); | |
240 | ||
241 | ||
242 | l2t_l2drpt_dp_nand_macro__dnand_32x__stack_16r__width_5 nand_tag_l2d_way_sel_c2_fnl_slice3 | |
243 | ( | |
244 | .dout ({tag_l2d_way_sel_c2_fnl_n[7:6],vld_mbf_miss_c2_3, tag_l2d_way_sel_c2_fnl_n[5:4]}), | |
245 | .din0 ({tag_l2d_way_sel_c2_fnl_1[7:6],misbuf_tag_hit_unqual_c2,tag_l2d_way_sel_c2_fnl_1[5:4]}), | |
246 | .din1 ({{2{vld_mbf_miss_c2_3}}, arb_waysel_inst_vld_c2, {2{vld_mbf_miss_c2_3}}}) | |
247 | ); | |
248 | ||
249 | ||
250 | l2t_l2drpt_dp_nand_macro__dnand_32x__stack_16r__width_5 nand_tag_l2d_way_sel_c2_fnl_slice4 | |
251 | ( | |
252 | .dout ({tag_l2d_way_sel_c2_fnl_n[3:2],vld_mbf_miss_c2_4, tag_l2d_way_sel_c2_fnl_n[1:0]}), | |
253 | .din0 ({tag_l2d_way_sel_c2_fnl_1[3:2],misbuf_tag_hit_unqual_c2,tag_l2d_way_sel_c2_fnl_1[1:0]}), | |
254 | .din1 ({{2{vld_mbf_miss_c2_4}}, arb_waysel_inst_vld_c2, {2{vld_mbf_miss_c2_4}}}) | |
255 | ); | |
256 | ||
257 | ||
258 | ||
259 | ||
260 | l2t_l2drpt_dp_inv_macro__dinv_48x__stack_16r__width_16 inv_tag_l2d_way_sel_c2_n | |
261 | ( | |
262 | .dout (tag_l2d_way_sel_c2[15:0]), | |
263 | .din (tag_l2d_way_sel_c2_fnl_n[15:0]) | |
264 | ); | |
265 | ||
266 | ||
267 | ||
268 | ||
269 | // fixscan start: | |
270 | assign ff_all_signals_scanin = scan_in ; | |
271 | assign scan_out = ff_all_signals_scanout ; | |
272 | // fixscan end: | |
273 | endmodule | |
274 | ||
275 | ||
276 | // | |
277 | // nor macro for ports = 2,3 | |
278 | // | |
279 | // | |
280 | ||
281 | ||
282 | ||
283 | ||
284 | ||
285 | module l2t_l2drpt_dp_nor_macro__dnor_4x__ports_3__stack_2r__width_1 ( | |
286 | din0, | |
287 | din1, | |
288 | din2, | |
289 | dout); | |
290 | input [0:0] din0; | |
291 | input [0:0] din1; | |
292 | input [0:0] din2; | |
293 | output [0:0] dout; | |
294 | ||
295 | ||
296 | ||
297 | ||
298 | ||
299 | ||
300 | nor3 #(1) d0_0 ( | |
301 | .in0(din0[0:0]), | |
302 | .in1(din1[0:0]), | |
303 | .in2(din2[0:0]), | |
304 | .out(dout[0:0]) | |
305 | ); | |
306 | ||
307 | ||
308 | ||
309 | ||
310 | ||
311 | ||
312 | ||
313 | endmodule | |
314 | ||
315 | ||
316 | ||
317 | ||
318 | ||
319 | // | |
320 | // invert macro | |
321 | // | |
322 | // | |
323 | ||
324 | ||
325 | ||
326 | ||
327 | ||
328 | module l2t_l2drpt_dp_inv_macro__dinv_32x__width_20 ( | |
329 | din, | |
330 | dout); | |
331 | input [19:0] din; | |
332 | output [19:0] dout; | |
333 | ||
334 | ||
335 | ||
336 | ||
337 | ||
338 | ||
339 | inv #(20) d0_0 ( | |
340 | .in(din[19:0]), | |
341 | .out(dout[19:0]) | |
342 | ); | |
343 | ||
344 | ||
345 | ||
346 | ||
347 | ||
348 | ||
349 | ||
350 | ||
351 | ||
352 | endmodule | |
353 | ||
354 | ||
355 | ||
356 | ||
357 | ||
358 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
359 | // also for pass-gate with decoder | |
360 | ||
361 | ||
362 | ||
363 | ||
364 | ||
365 | // any PARAMS parms go into naming of macro | |
366 | ||
367 | module l2t_l2drpt_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__width_3 ( | |
368 | din0, | |
369 | sel0, | |
370 | din1, | |
371 | sel1, | |
372 | dout); | |
373 | wire buffout0; | |
374 | wire buffout1; | |
375 | ||
376 | input [2:0] din0; | |
377 | input sel0; | |
378 | input [2:0] din1; | |
379 | input sel1; | |
380 | output [2:0] dout; | |
381 | ||
382 | ||
383 | ||
384 | ||
385 | ||
386 | cl_dp1_muxbuff2_8x c0_0 ( | |
387 | .in0(sel0), | |
388 | .in1(sel1), | |
389 | .out0(buffout0), | |
390 | .out1(buffout1) | |
391 | ); | |
392 | mux2s #(3) d0_0 ( | |
393 | .sel0(buffout0), | |
394 | .sel1(buffout1), | |
395 | .in0(din0[2:0]), | |
396 | .in1(din1[2:0]), | |
397 | .dout(dout[2:0]) | |
398 | ); | |
399 | ||
400 | ||
401 | ||
402 | ||
403 | ||
404 | ||
405 | ||
406 | ||
407 | ||
408 | ||
409 | ||
410 | ||
411 | ||
412 | endmodule | |
413 | ||
414 | ||
415 | ||
416 | ||
417 | ||
418 | ||
419 | // any PARAMS parms go into naming of macro | |
420 | ||
421 | module l2t_l2drpt_dp_msff_macro__dmsff_32x__stack_26r__width_21 ( | |
422 | din, | |
423 | clk, | |
424 | en, | |
425 | se, | |
426 | scan_in, | |
427 | siclk, | |
428 | soclk, | |
429 | pce_ov, | |
430 | stop, | |
431 | dout, | |
432 | scan_out); | |
433 | wire l1clk; | |
434 | wire siclk_out; | |
435 | wire soclk_out; | |
436 | wire [19:0] so; | |
437 | ||
438 | input [20:0] din; | |
439 | ||
440 | ||
441 | input clk; | |
442 | input en; | |
443 | input se; | |
444 | input scan_in; | |
445 | input siclk; | |
446 | input soclk; | |
447 | input pce_ov; | |
448 | input stop; | |
449 | ||
450 | ||
451 | ||
452 | output [20:0] dout; | |
453 | ||
454 | ||
455 | output scan_out; | |
456 | ||
457 | ||
458 | ||
459 | ||
460 | cl_dp1_l1hdr_8x c0_0 ( | |
461 | .l2clk(clk), | |
462 | .pce(en), | |
463 | .aclk(siclk), | |
464 | .bclk(soclk), | |
465 | .l1clk(l1clk), | |
466 | .se(se), | |
467 | .pce_ov(pce_ov), | |
468 | .stop(stop), | |
469 | .siclk_out(siclk_out), | |
470 | .soclk_out(soclk_out) | |
471 | ); | |
472 | dff #(21) d0_0 ( | |
473 | .l1clk(l1clk), | |
474 | .siclk(siclk_out), | |
475 | .soclk(soclk_out), | |
476 | .d(din[20:0]), | |
477 | .si({scan_in,so[19:0]}), | |
478 | .so({so[19:0],scan_out}), | |
479 | .q(dout[20:0]) | |
480 | ); | |
481 | ||
482 | ||
483 | ||
484 | ||
485 | ||
486 | ||
487 | ||
488 | ||
489 | ||
490 | ||
491 | ||
492 | ||
493 | ||
494 | ||
495 | ||
496 | ||
497 | ||
498 | ||
499 | ||
500 | ||
501 | endmodule | |
502 | ||
503 | ||
504 | ||
505 | ||
506 | ||
507 | ||
508 | ||
509 | ||
510 | ||
511 | // | |
512 | // and macro for ports = 2,3,4 | |
513 | // | |
514 | // | |
515 | ||
516 | ||
517 | ||
518 | ||
519 | ||
520 | module l2t_l2drpt_dp_and_macro__dinv_48x__dnand_16x__ports_3__stack_2r__width_1 ( | |
521 | din0, | |
522 | din1, | |
523 | din2, | |
524 | dout); | |
525 | input [0:0] din0; | |
526 | input [0:0] din1; | |
527 | input [0:0] din2; | |
528 | output [0:0] dout; | |
529 | ||
530 | ||
531 | ||
532 | ||
533 | ||
534 | ||
535 | and3 #(1) d0_0 ( | |
536 | .in0(din0[0:0]), | |
537 | .in1(din1[0:0]), | |
538 | .in2(din2[0:0]), | |
539 | .out(dout[0:0]) | |
540 | ); | |
541 | ||
542 | ||
543 | ||
544 | ||
545 | ||
546 | ||
547 | ||
548 | ||
549 | ||
550 | endmodule | |
551 | ||
552 | ||
553 | ||
554 | ||
555 | ||
556 | // | |
557 | // nand macro for ports = 2,3,4 | |
558 | // | |
559 | // | |
560 | ||
561 | ||
562 | ||
563 | ||
564 | ||
565 | module l2t_l2drpt_dp_nand_macro__dnand_24x__ports_3__stack_16r__width_16 ( | |
566 | din0, | |
567 | din1, | |
568 | din2, | |
569 | dout); | |
570 | input [15:0] din0; | |
571 | input [15:0] din1; | |
572 | input [15:0] din2; | |
573 | output [15:0] dout; | |
574 | ||
575 | ||
576 | ||
577 | ||
578 | ||
579 | ||
580 | nand3 #(16) d0_0 ( | |
581 | .in0(din0[15:0]), | |
582 | .in1(din1[15:0]), | |
583 | .in2(din2[15:0]), | |
584 | .out(dout[15:0]) | |
585 | ); | |
586 | ||
587 | ||
588 | ||
589 | ||
590 | ||
591 | ||
592 | ||
593 | ||
594 | ||
595 | endmodule | |
596 | ||
597 | ||
598 | ||
599 | ||
600 | ||
601 | // | |
602 | // nand macro for ports = 2,3,4 | |
603 | // | |
604 | // | |
605 | ||
606 | ||
607 | ||
608 | ||
609 | ||
610 | module l2t_l2drpt_dp_nand_macro__dnand_32x__stack_16r__width_5 ( | |
611 | din0, | |
612 | din1, | |
613 | dout); | |
614 | input [4:0] din0; | |
615 | input [4:0] din1; | |
616 | output [4:0] dout; | |
617 | ||
618 | ||
619 | ||
620 | ||
621 | ||
622 | ||
623 | nand2 #(5) d0_0 ( | |
624 | .in0(din0[4:0]), | |
625 | .in1(din1[4:0]), | |
626 | .out(dout[4:0]) | |
627 | ); | |
628 | ||
629 | ||
630 | ||
631 | ||
632 | ||
633 | ||
634 | ||
635 | ||
636 | ||
637 | endmodule | |
638 | ||
639 | ||
640 | ||
641 | ||
642 | ||
643 | // | |
644 | // invert macro | |
645 | // | |
646 | // | |
647 | ||
648 | ||
649 | ||
650 | ||
651 | ||
652 | module l2t_l2drpt_dp_inv_macro__dinv_48x__stack_16r__width_16 ( | |
653 | din, | |
654 | dout); | |
655 | input [15:0] din; | |
656 | output [15:0] dout; | |
657 | ||
658 | ||
659 | ||
660 | ||
661 | ||
662 | ||
663 | inv #(16) d0_0 ( | |
664 | .in(din[15:0]), | |
665 | .out(dout[15:0]) | |
666 | ); | |
667 | ||
668 | ||
669 | ||
670 | ||
671 | ||
672 | ||
673 | ||
674 | ||
675 | ||
676 | endmodule | |
677 | ||
678 | ||
679 | ||
680 |