Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: fflp_hdr_cntl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | /**********************************************************************/ | |
36 | /*project name: NIU */ | |
37 | /*module name: fflp_hdr_cntl */ | |
38 | /*description: Controls the hdr_shft portion of the hdr_dp */ | |
39 | /* */ | |
40 | /*parent module in: fflp_hdr.v */ | |
41 | /*child modules in: none */ | |
42 | /*interface modules: */ | |
43 | /*author name: Jeanne Cai */ | |
44 | /*date created: 03-18-04 */ | |
45 | /* */ | |
46 | /* Copyright (c) 2004, Sun Microsystems, Inc. */ | |
47 | /* Sun Proprietary and Confidential */ | |
48 | /* */ | |
49 | /**********************************************************************/ | |
50 | ||
51 | module fflp_hdr_cntl | |
52 | ( | |
53 | cclk, | |
54 | reset, | |
55 | ipp_fflp_dvalid, | |
56 | hdr_fifo_space_avail, | |
57 | hdr_fifo_full, | |
58 | ||
59 | fflp_ipp_ready, | |
60 | shft0_reg_en, | |
61 | shft1_reg_en, | |
62 | shft2_reg_en, | |
63 | shft3_reg_en, | |
64 | shft4_reg_en, | |
65 | shft5_reg_en, | |
66 | shft6_reg_en, | |
67 | shft7_reg_en, | |
68 | hdr_shft_done | |
69 | ); | |
70 | ||
71 | input cclk; | |
72 | input reset; | |
73 | input ipp_fflp_dvalid; | |
74 | input hdr_fifo_space_avail; | |
75 | input hdr_fifo_full; | |
76 | ||
77 | output fflp_ipp_ready; | |
78 | output shft0_reg_en; | |
79 | output shft1_reg_en; | |
80 | output shft2_reg_en; | |
81 | output shft3_reg_en; | |
82 | output shft4_reg_en; | |
83 | output shft5_reg_en; | |
84 | output shft6_reg_en; | |
85 | output shft7_reg_en; | |
86 | output hdr_shft_done; | |
87 | ||
88 | reg fflp_ready; | |
89 | reg shft0_reg_en; | |
90 | reg shft1_reg_en; | |
91 | reg shft2_reg_en; | |
92 | reg shft3_reg_en; | |
93 | reg shft4_reg_en; | |
94 | reg shft5_reg_en; | |
95 | reg shft6_reg_en; | |
96 | reg shft7_reg_en; | |
97 | reg[2:0] next_state; | |
98 | ||
99 | wire hdr_shft_done; | |
100 | wire[2:0] state; | |
101 | wire hdr_dvalid; | |
102 | wire fflp_ipp_ready_in; | |
103 | wire fflp_ipp_ready_en; | |
104 | wire fflp_ipp_ready; | |
105 | ||
106 | ||
107 | //state machine states | |
108 | parameter | |
109 | IDLE = 3'b000, | |
110 | HDR_DATA_CYC1 = 3'b001, | |
111 | HDR_DATA_CYC2 = 3'b010, | |
112 | HDR_DATA_CYC3 = 3'b011, | |
113 | HDR_DATA_CYC4 = 3'b100, | |
114 | HDR_DATA_CYC5 = 3'b101, | |
115 | HDR_DATA_CYC6 = 3'b110, | |
116 | HDR_DATA_CYC7 = 3'b111; | |
117 | ||
118 | ||
119 | always @ ( | |
120 | state or | |
121 | hdr_dvalid or | |
122 | hdr_fifo_space_avail or | |
123 | hdr_fifo_full or | |
124 | hdr_shft_done or | |
125 | fflp_ipp_ready) | |
126 | begin | |
127 | shft0_reg_en = 1'b0; | |
128 | shft1_reg_en = 1'b0; | |
129 | shft2_reg_en = 1'b0; | |
130 | shft3_reg_en = 1'b0; | |
131 | shft4_reg_en = 1'b0; | |
132 | shft5_reg_en = 1'b0; | |
133 | shft6_reg_en = 1'b0; | |
134 | shft7_reg_en = 1'b0; | |
135 | fflp_ready = 1'b0; | |
136 | next_state = IDLE; | |
137 | ||
138 | case (state) //synopsys parallel_case full_case | |
139 | // 0in < case -full -parallel -message "0in ERROR: case check in fflp_hdr_cntl" | |
140 | IDLE: | |
141 | begin | |
142 | if (hdr_dvalid) | |
143 | begin | |
144 | shft0_reg_en = 1'b1; | |
145 | next_state = HDR_DATA_CYC1; | |
146 | end | |
147 | else | |
148 | begin | |
149 | shft0_reg_en = 1'b0; | |
150 | next_state = state; | |
151 | end | |
152 | ||
153 | if (!fflp_ipp_ready & (hdr_fifo_space_avail | !hdr_shft_done & !hdr_fifo_full)) | |
154 | fflp_ready = 1'b1; | |
155 | else | |
156 | fflp_ready = 1'b0; | |
157 | end | |
158 | ||
159 | HDR_DATA_CYC1: | |
160 | begin | |
161 | shft1_reg_en = 1'b1; | |
162 | next_state = HDR_DATA_CYC2; | |
163 | end | |
164 | ||
165 | HDR_DATA_CYC2: | |
166 | begin | |
167 | shft2_reg_en = 1'b1; | |
168 | next_state = HDR_DATA_CYC3; | |
169 | end | |
170 | ||
171 | HDR_DATA_CYC3: | |
172 | begin | |
173 | shft3_reg_en = 1'b1; | |
174 | next_state = HDR_DATA_CYC4; | |
175 | end | |
176 | ||
177 | HDR_DATA_CYC4: | |
178 | begin | |
179 | shft4_reg_en = 1'b1; | |
180 | next_state = HDR_DATA_CYC5; | |
181 | end | |
182 | ||
183 | HDR_DATA_CYC5: | |
184 | begin | |
185 | shft5_reg_en = 1'b1; | |
186 | next_state = HDR_DATA_CYC6; | |
187 | end | |
188 | ||
189 | HDR_DATA_CYC6: | |
190 | begin | |
191 | shft6_reg_en = 1'b1; | |
192 | next_state = HDR_DATA_CYC7; | |
193 | if (hdr_fifo_space_avail) | |
194 | fflp_ready = 1'b1; | |
195 | else | |
196 | fflp_ready = 1'b0; | |
197 | end | |
198 | ||
199 | HDR_DATA_CYC7: | |
200 | begin | |
201 | shft7_reg_en = 1'b1; | |
202 | next_state = IDLE; | |
203 | if (!fflp_ipp_ready & hdr_fifo_space_avail | fflp_ipp_ready) | |
204 | fflp_ready = 1'b1; | |
205 | else | |
206 | fflp_ready = 1'b0; | |
207 | end | |
208 | ||
209 | ||
210 | default: | |
211 | next_state = IDLE; | |
212 | ||
213 | endcase | |
214 | ||
215 | end | |
216 | ||
217 | dffr #(3) state_reg (cclk, reset, next_state, state); | |
218 | dffr #(1) hdr_shft_done_reg (cclk, reset, shft7_reg_en, hdr_shft_done); | |
219 | ||
220 | /*****************************************/ | |
221 | //fflp-ipp interface signals | |
222 | /*****************************************/ | |
223 | /* | |
224 | always @ (posedge cclk) | |
225 | if (reset) | |
226 | hdr_dvalid <= 1'b0; | |
227 | else | |
228 | hdr_dvalid <= ipp_fflp_dvalid; | |
229 | */ | |
230 | ||
231 | assign hdr_dvalid = ipp_fflp_dvalid; | |
232 | ||
233 | assign fflp_ipp_ready_in = fflp_ready ? 1'b1 : 1'b0; | |
234 | assign fflp_ipp_ready_en = fflp_ready | hdr_dvalid; | |
235 | ||
236 | dffre #(1) fflp_ipp_ready_reg (cclk, reset, fflp_ipp_ready_en, fflp_ipp_ready_in, fflp_ipp_ready); | |
237 | ||
238 | endmodule | |
239 | ||
240 | ||
241 | ||
242 | ||
243 | ||
244 | ||
245 |