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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: rst_ucbbusout4_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `define ASSERT 1'b0 // For active low signal. | |
36 | `define DEASSERT 1'b1 // For active low signal. | |
37 | ||
38 | `define INFO 20 | |
39 | // (Origin:) | |
40 | `define IOB_CREG_RESET_GEN 40'h89_0000_0808 //Adr of RESET_GEN reg (Fire.) | |
41 | `define IOB_CREG_RESET_SOURCE 40'h89_0000_0818 //Adr of RESET_SOURCE reg (Fire.) | |
42 | `define IOB_CREG_SSYSRESET 40'h89_0000_0838 //Adr of SSYS_RESET reg (N1.) | |
43 | `define IOB_CREG_RESETSTAT 40'h89_0000_0810 //Adr of RSET_STAT reg (N1.) | |
44 | `define IOB_CREG_CCU_TIME 40'h89_0000_0860 //Adr of CCU_TIME reg (N2.) | |
45 | `define IOB_CREG_LOCK_TIME 40'h89_0000_0870 //Adr of LOCK_TIME reg (N2.) | |
46 | `define IOB_CREG_PROP_TIME 40'h89_0000_0880 //Adr of PROP_TIME reg (N2.) | |
47 | `define IOB_CREG_NIU_TIME 40'h89_0000_0890 //Adr of NIU_TIME reg (N2.) | |
48 | `define IOB_CREG_RESET_FEE 40'h89_0000_0820 //Adr of RESET_FEE reg (N2.) | |
49 | //________________________________________________________________ | |
50 | ||
51 | `define RST_FSM_WIDTH 33 | |
52 | `define RST_INIT_STATE 33'h0_0000_0001 | |
53 | `define POR1_LOCK_TIME 33'h0_0000_0002 | |
54 | `define POR1_ARST_TIME 33'h0_0000_0004 | |
55 | `define POR1_SYNC_STABLE 33'h0_0000_0008 | |
56 | `define POR1_ASICFLUSH_STOP_ACK 33'h0_0000_0010 | |
57 | `define POR1_NIU_TIME 33'h0_0000_0020 | |
58 | `define POR1_FLUSH_STOP_ACK 33'h0_0000_0040 | |
59 | `define POR1_BISX_DONE 33'h0_0000_0080 | |
60 | `define POR2_FLUSH_INIT_ACK 33'h0_0000_0100 | |
61 | `define POR2_LOCK_TIME 33'h0_0000_0200 | |
62 | `define POR2_FLUSH_STOP_ACK 33'h0_0000_0400 | |
63 | `define POR2_EFU_DONE 33'h0_0000_0800 | |
64 | `define POR2_ASSERT_RUN 33'h0_0000_1000 | |
65 | `define POR2_UNPARK_THREAD 33'h0_0000_2000 | |
66 | `define WMR1_WMR_GEN 33'h0_0000_4000 | |
67 | `define WMR1_DEASSERT_RUN 33'h0_0000_8000 | |
68 | `define WMR1_FLUSH_INIT_ACK 33'h0_0001_0000 | |
69 | `define WMR1_PRE_PLL1 33'h0_0002_0000 | |
70 | `define WMR1_PRE_PLL2 33'h0_0004_0000 | |
71 | `define WMR1_CCU_PLL 33'h0_0008_0000 | |
72 | `define WMR1_LOCK_TIME 33'h0_0010_0000 | |
73 | `define WMR1_ARST_TIME 33'h0_0020_0000 | |
74 | `define WMR1_PROP_TIME 33'h0_0040_0000 | |
75 | `define WMR1_SYNC_STABLE 33'h0_0080_0000 | |
76 | `define WMR1_FLUSH_STOP_ACK 33'h0_0100_0000 | |
77 | `define WMR1_BISX_DONE 33'h0_0200_0000 | |
78 | `define WMR2_FLUSH_INIT_ACK 33'h0_0400_0000 | |
79 | `define WMR2_PROP_TIME 33'h0_0800_0000 | |
80 | `define WMR2_FLUSH_STOP_ACK 33'h0_1000_0000 | |
81 | `define WMR2_NIU_TIME 33'h1_0000_0000 | |
82 | `define WMR2_ASSERT_RUN 33'h0_2000_0000 | |
83 | `define WMR2_UNPARK_THREAD 33'h0_4000_0000 | |
84 | `define RST_ARBITER 33'h0_8000_0000 | |
85 | ||
86 | `define XIR_IDLE 2'h1 | |
87 | `define XIR_DONE 2'h2 | |
88 | ||
89 | `define DMU_IDLE 3'h1 | |
90 | `define DMU_TIME1 3'h2 | |
91 | `define DMU_TIME2 3'h4 | |
92 | ||
93 | `define NIU_IDLE 2'h1 | |
94 | `define NIU_TIME 2'h2 | |
95 | //________________________________________________________________ | |
96 | ||
97 | // Already taken addresses, in address order: | |
98 | // sort -t "'" -k 2 /home/jl148824/project/NCU/include/iop.h: | |
99 | ||
100 | //`define IOB_CREG_INTMAN 32'h00000000 | |
101 | //`define IOB_CREG_INTSTAT 32'h00000000 | |
102 | //`define IOB_CREG_INTCTL 32'h00000400 | |
103 | //`define IOB_CREG_MDATA0 32'h00000400 | |
104 | //`define IOB_CREG_MDATA1 32'h00000500 | |
105 | //`define IOB_CREG_MDATA0_ALIAS 32'h00000600 | |
106 | //`define IOB_CREG_MDATA1_ALIAS 32'h00000700 | |
107 | //`define IOB_CREG_INTVECDISP 32'h00000800 | |
108 | // 32'h00000808 // Adr of RESET_GEN reg. | |
109 | // Bill Bryg removed the CHIP_RESET reg from the Niagara 1 spec Feb 4 '03. | |
110 | //`define IOB_CREG_RESETSTAT 32'h00000810 // Adr of RSET_STAT reg. | |
111 | //`define IOB_CREG_SERNUM 32'h00000820 | |
112 | //`define IOB_CREG_TMSTATCTRL 32'h00000828 | |
113 | //`define IOB_CREG_COREAVAIL 32'h00000830 | |
114 | //`define IOB_CREG_SSYSRESET 32'h00000838 // Adr of SSYS_RESET reg. | |
115 | //`define IOB_CREG_FUSESTAT 32'h00000840 | |
116 | //`define IOB_CREG_MARGIN 32'h00000850 | |
117 | //`define IOB_CREG_MBUSY 32'h00000900 | |
118 | //`define IOB_CREG_JINTV 32'h00000a00 | |
119 | //`define IOB_CREG_MBUSY_ALIAS 32'h00000b00 | |
120 | //`define IOB_CREG_DBG_IOBVIS_CTRL 32'h00001000 | |
121 | //`define IOB_CREG_DBG_L2VIS_CTRL 32'h00001800 | |
122 | //`define IOB_CREG_DBG_L2VIS_MASKA 32'h00001820 | |
123 | //`define IOB_CREG_DBG_L2VIS_MASKB 32'h00001828 | |
124 | //`define IOB_CREG_DBG_L2VIS_CMPA 32'h00001830 | |
125 | //`define IOB_CREG_DBG_L2VIS_CMPB 32'h00001838 | |
126 | //`define IOB_CREG_DBG_L2VIS_TRIG 32'h00001840 | |
127 | //`define IOB_CREG_DBG_ENET_CTRL 32'h00002000 | |
128 | //`define IOB_CREG_DBG_ENET_IDLEVAL 32'h00002008 | |
129 | //`define IOB_CREG_DBG_JBUS_CTRL 32'h00002100 | |
130 | //`define IOB_CREG_DBG_JBUS_LO_MASK0 32'h00002140 | |
131 | //`define IOB_CREG_DBG_JBUS_LO_CMP0 32'h00002148 | |
132 | //`define IOB_CREG_DBG_JBUS_LO_CNT0 32'h00002150 | |
133 | //`define IOB_CREG_DBG_JBUS_LO_MASK1 32'h00002160 | |
134 | //`define IOB_CREG_DBG_JBUS_LO_CMP1 32'h00002168 | |
135 | //`define IOB_CREG_DBG_JBUS_LO_CNT1 32'h00002170 | |
136 | //`define IOB_CREG_DBG_JBUS_HI_MASK0 32'h00002180 | |
137 | //`define IOB_CREG_DBG_JBUS_HI_CMP0 32'h00002188 | |
138 | //`define IOB_CREG_DBG_JBUS_HI_CNT0 32'h00002190 | |
139 | //`define IOB_CREG_DBG_JBUS_HI_MASK1 32'h000021a0 | |
140 | //`define IOB_CREG_DBG_JBUS_HI_CMP1 32'h000021a8 | |
141 | //`define IOB_CREG_DBG_JBUS_HI_CNT1 32'h000021b0 | |
142 | //________________________________________________________________ | |
143 | ||
144 | // Verilog define statements for: | |
145 | // rst_ucbbusin4_ctl.sv and: | |
146 | // rst_ucbbusout4_ctl.sv: | |
147 | ||
148 | `define UCB_BUS_WIDTH 4 | |
149 | `define UCB_BUS_WIDTH_M1 3 | |
150 | `define CYC_NUM 32 | |
151 | `define CYC_NUM_M1 31 | |
152 | ||
153 | `define RST_UCB_DATA_WIDTH 16 | |
154 | // Width of: | |
155 | // data_in_io ;// Convert from io to cmp to sys. | |
156 | // data_in_sys ;// Convert from io to cmp to sys. | |
157 | // data_out_sys2 ;// Convert from sys to cmp. | |
158 | // data_out_cmp2 ;// Convert from sys to cmp to io. | |
159 | // The following stay 64 bits wide: | |
160 | // data_in ;// Convert from io to cmp to sys. | |
161 | // data_out ;// Converted from cmp to io. | |
162 | // If you modify RST_UCB_DATA_WIDTH, adjust the width of x'b0 in | |
163 | // the following two concatenations: | |
164 | // assign data_out [ 63:0] = | |
165 | // assign data_out_sys[`RST_UCB_DATA_WIDTH-1:0] = | |
166 | ||
167 | `define RST_TIME_WIDTH 16 | |
168 | // Width of: | |
169 | // lock_time_addr ? {32'b0, lock_time_q [31:0] }:// LOCK_TIME | |
170 | // prop_time_addr ? {32'b0, prop_time_q [31:0] }:// PROP_TIME | |
171 | // niu_time_addr ? {32'b0, niu_time_q [31:0] }:// NIU_TIME | |
172 | // msff_ctl_macro lock_time_ff (width=32,en=1,clr_=1) | |
173 | // msff_ctl_macro lock_count_ff (width=32,en=0,clr_=1) | |
174 | // msff_ctl_macro prop_time_ff (width=32,en=1,clr_=1) | |
175 | // msff_ctl_macro prop_count_ff (width=32,en=0,clr_=1) | |
176 | // msff_ctl_macro niu_time_ff (width=32,en=1,clr_=1) | |
177 | // msff_ctl_macro niu_count_ff (width=32,en=0,clr_=1) | |
178 | // msff_ctl_macro dmu_time_ff (width=32,en=1,clr_=1) | |
179 | // msff_ctl_macro dmu_count_ff (width=32,en=0,clr_=1) | |
180 | ||
181 | ||
182 | // `define UCB_BUS_WIDTH 4 | |
183 | // `define UCB_BUS_WIDTH_M1 3 | |
184 | // `define CYC_NUM 32 | |
185 | // `define CYC_NUM_M1 31 | |
186 | ||
187 | module rst_ucbbusout4_ctl ( | |
188 | iol2clk, | |
189 | ucb_clr_io_, | |
190 | scan_in, | |
191 | scan_out, | |
192 | tcu_pce_ov, | |
193 | tcu_clk_stop, | |
194 | tcu_aclk, | |
195 | tcu_bclk, | |
196 | tcu_scan_en, | |
197 | vld, | |
198 | data, | |
199 | stall, | |
200 | outdata_buf_busy, | |
201 | outdata_buf_in, | |
202 | outdata_vec_in, | |
203 | outdata_buf_wr) ; | |
204 | wire [31:0] outdata_vec; | |
205 | wire [127:0] outdata_buf; | |
206 | wire stall_d1_ff_scanin; | |
207 | wire stall_d1_ff_scanout; | |
208 | wire stall_d1; | |
209 | wire l1clk; | |
210 | wire load_outdata; | |
211 | wire shift_outdata; | |
212 | wire [31:0] outdata_vec_next; | |
213 | wire outdata_vec_ff_scanin; | |
214 | wire outdata_vec_ff_scanout; | |
215 | wire [127:0] outdata_buf_next; | |
216 | wire outdata_buf_ff_scanin; | |
217 | wire outdata_buf_ff_scanout; | |
218 | wire siclk; | |
219 | wire soclk; | |
220 | wire pce_ov; | |
221 | wire stop; | |
222 | wire se; | |
223 | ||
224 | ||
225 | // Globals | |
226 | input iol2clk; | |
227 | input ucb_clr_io_; //BP 8-19-05 | |
228 | input scan_in; | |
229 | output scan_out; | |
230 | input tcu_pce_ov; | |
231 | input tcu_clk_stop; | |
232 | input tcu_aclk ; | |
233 | input tcu_bclk ; | |
234 | input tcu_scan_en ; | |
235 | ||
236 | // UCB bus interface | |
237 | output vld; | |
238 | output [`UCB_BUS_WIDTH_M1 :0] data; | |
239 | input stall; | |
240 | ||
241 | // Local interface | |
242 | output outdata_buf_busy; | |
243 | input [127:0] outdata_buf_in; | |
244 | input [`CYC_NUM_M1 :0] outdata_vec_in; | |
245 | input outdata_buf_wr; | |
246 | ||
247 | // Local signals | |
248 | ||
249 | //////////////////////////////////////////////////////////////////////// | |
250 | // Code starts here | |
251 | //////////////////////////////////////////////////////////////////////// | |
252 | /************************************************************ | |
253 | * UCB bus interface flops | |
254 | ************************************************************/ | |
255 | assign vld = outdata_vec[0]; | |
256 | assign data[`UCB_BUS_WIDTH_M1 :0] = outdata_buf[`UCB_BUS_WIDTH_M1 :0]; | |
257 | ||
258 | rst_ucbbusout4_ctl_msff_ctl_macro__clr__1__width_1 stall_d1_ff | |
259 | ( | |
260 | .scan_in(stall_d1_ff_scanin), | |
261 | .scan_out(stall_d1_ff_scanout), | |
262 | .dout (stall_d1), | |
263 | .clr_ (ucb_clr_io_), //BP 8-19-05 | |
264 | .l1clk (l1clk), | |
265 | .din (stall), | |
266 | .siclk(siclk), | |
267 | .soclk(soclk) | |
268 | ); | |
269 | ||
270 | /************************************************************ | |
271 | * Outbound Data | |
272 | ************************************************************/ | |
273 | // accept new data only if there is none being processed | |
274 | assign load_outdata = outdata_buf_wr & ~outdata_buf_busy; | |
275 | ||
276 | assign outdata_buf_busy = outdata_vec[0] | stall_d1; | |
277 | ||
278 | assign shift_outdata = outdata_vec[0] & ~stall_d1; | |
279 | ||
280 | assign outdata_vec_next[`CYC_NUM_M1 :0] = | |
281 | load_outdata ? outdata_vec_in[`CYC_NUM_M1 :0] : | |
282 | shift_outdata ? {1'b0,outdata_vec[`CYC_NUM_M1 :1]} : | |
283 | outdata_vec[`CYC_NUM_M1 :0] ; | |
284 | ||
285 | rst_ucbbusout4_ctl_msff_ctl_macro__clr__1__width_32 outdata_vec_ff | |
286 | ( | |
287 | .scan_in(outdata_vec_ff_scanin), | |
288 | .scan_out(outdata_vec_ff_scanout), | |
289 | .dout (outdata_vec[`CYC_NUM_M1 :0]), | |
290 | .clr_ (ucb_clr_io_), //BP 8-19-05 | |
291 | .l1clk (l1clk), | |
292 | .din (outdata_vec_next[`CYC_NUM_M1 :0]), | |
293 | .siclk(siclk), | |
294 | .soclk(soclk) | |
295 | ); | |
296 | ||
297 | assign outdata_buf_next[127:0] = load_outdata ? outdata_buf_in[127:0] : | |
298 | shift_outdata ? (outdata_buf[127:0] >> `UCB_BUS_WIDTH ) : | |
299 | outdata_buf[127:0] ; | |
300 | ||
301 | rst_ucbbusout4_ctl_msff_ctl_macro__clr__1__width_128 outdata_buf_ff | |
302 | ( | |
303 | .scan_in(outdata_buf_ff_scanin), | |
304 | .scan_out(outdata_buf_ff_scanout), | |
305 | .dout (outdata_buf[127:0]), | |
306 | .clr_ (ucb_clr_io_), //BP 8-19-05 | |
307 | .l1clk (l1clk), | |
308 | .din (outdata_buf_next[127:0]), | |
309 | .siclk(siclk), | |
310 | .soclk(soclk) | |
311 | ); | |
312 | ||
313 | ||
314 | ||
315 | /**** adding clock header ****/ | |
316 | rst_ucbbusout4_ctl_l1clkhdr_ctl_macro clkgen ( | |
317 | .l2clk (iol2clk), | |
318 | .l1en (1'b1), | |
319 | // .pce_ov (1'b0 ), | |
320 | .stop (1'b0 ), | |
321 | // .se (1'b0 ), | |
322 | .l1clk (l1clk), | |
323 | .pce_ov(pce_ov), | |
324 | .se(se) | |
325 | ); | |
326 | ||
327 | /*** building tcu port ***/ | |
328 | assign siclk = tcu_aclk ; | |
329 | assign soclk = tcu_bclk ; | |
330 | assign pce_ov = tcu_pce_ov ; | |
331 | assign stop = tcu_clk_stop; | |
332 | // scan renames | |
333 | assign se = tcu_scan_en ; | |
334 | // end scan | |
335 | ||
336 | // fixscan start: | |
337 | assign stall_d1_ff_scanin = scan_in ; | |
338 | assign outdata_vec_ff_scanin = stall_d1_ff_scanout ; | |
339 | assign outdata_buf_ff_scanin = outdata_vec_ff_scanout ; | |
340 | assign scan_out = outdata_buf_ff_scanout ; | |
341 | // fixscan end: | |
342 | endmodule // ucb_bus_out | |
343 | ||
344 | ||
345 | ||
346 | ||
347 | ||
348 | ||
349 | ||
350 | ||
351 | ||
352 | ||
353 | ||
354 | ||
355 | // any PARAMS parms go into naming of macro | |
356 | ||
357 | module rst_ucbbusout4_ctl_msff_ctl_macro__clr__1__width_1 ( | |
358 | din, | |
359 | clr_, | |
360 | l1clk, | |
361 | scan_in, | |
362 | siclk, | |
363 | soclk, | |
364 | dout, | |
365 | scan_out); | |
366 | wire [0:0] fdin; | |
367 | ||
368 | input [0:0] din; | |
369 | input clr_; | |
370 | input l1clk; | |
371 | input scan_in; | |
372 | ||
373 | ||
374 | input siclk; | |
375 | input soclk; | |
376 | ||
377 | output [0:0] dout; | |
378 | output scan_out; | |
379 | assign fdin[0:0] = din[0:0] & ~{1{(~clr_)}}; | |
380 | ||
381 | ||
382 | ||
383 | ||
384 | ||
385 | ||
386 | dff #(1) d0_0 ( | |
387 | .l1clk(l1clk), | |
388 | .siclk(siclk), | |
389 | .soclk(soclk), | |
390 | .d(fdin[0:0]), | |
391 | .si(scan_in), | |
392 | .so(scan_out), | |
393 | .q(dout[0:0]) | |
394 | ); | |
395 | ||
396 | ||
397 | ||
398 | ||
399 | ||
400 | ||
401 | ||
402 | ||
403 | ||
404 | ||
405 | ||
406 | ||
407 | endmodule | |
408 | ||
409 | ||
410 | ||
411 | ||
412 | ||
413 | ||
414 | ||
415 | ||
416 | ||
417 | ||
418 | ||
419 | ||
420 | ||
421 | // any PARAMS parms go into naming of macro | |
422 | ||
423 | module rst_ucbbusout4_ctl_msff_ctl_macro__clr__1__width_32 ( | |
424 | din, | |
425 | clr_, | |
426 | l1clk, | |
427 | scan_in, | |
428 | siclk, | |
429 | soclk, | |
430 | dout, | |
431 | scan_out); | |
432 | wire [31:0] fdin; | |
433 | wire [30:0] so; | |
434 | ||
435 | input [31:0] din; | |
436 | input clr_; | |
437 | input l1clk; | |
438 | input scan_in; | |
439 | ||
440 | ||
441 | input siclk; | |
442 | input soclk; | |
443 | ||
444 | output [31:0] dout; | |
445 | output scan_out; | |
446 | assign fdin[31:0] = din[31:0] & ~{32{(~clr_)}}; | |
447 | ||
448 | ||
449 | ||
450 | ||
451 | ||
452 | ||
453 | dff #(32) d0_0 ( | |
454 | .l1clk(l1clk), | |
455 | .siclk(siclk), | |
456 | .soclk(soclk), | |
457 | .d(fdin[31:0]), | |
458 | .si({scan_in,so[30:0]}), | |
459 | .so({so[30:0],scan_out}), | |
460 | .q(dout[31:0]) | |
461 | ); | |
462 | ||
463 | ||
464 | ||
465 | ||
466 | ||
467 | ||
468 | ||
469 | ||
470 | ||
471 | ||
472 | ||
473 | ||
474 | endmodule | |
475 | ||
476 | ||
477 | ||
478 | ||
479 | ||
480 | ||
481 | ||
482 | ||
483 | ||
484 | ||
485 | ||
486 | ||
487 | ||
488 | // any PARAMS parms go into naming of macro | |
489 | ||
490 | module rst_ucbbusout4_ctl_msff_ctl_macro__clr__1__width_128 ( | |
491 | din, | |
492 | clr_, | |
493 | l1clk, | |
494 | scan_in, | |
495 | siclk, | |
496 | soclk, | |
497 | dout, | |
498 | scan_out); | |
499 | wire [127:0] fdin; | |
500 | wire [126:0] so; | |
501 | ||
502 | input [127:0] din; | |
503 | input clr_; | |
504 | input l1clk; | |
505 | input scan_in; | |
506 | ||
507 | ||
508 | input siclk; | |
509 | input soclk; | |
510 | ||
511 | output [127:0] dout; | |
512 | output scan_out; | |
513 | assign fdin[127:0] = din[127:0] & ~{128{(~clr_)}}; | |
514 | ||
515 | ||
516 | ||
517 | ||
518 | ||
519 | ||
520 | dff #(128) d0_0 ( | |
521 | .l1clk(l1clk), | |
522 | .siclk(siclk), | |
523 | .soclk(soclk), | |
524 | .d(fdin[127:0]), | |
525 | .si({scan_in,so[126:0]}), | |
526 | .so({so[126:0],scan_out}), | |
527 | .q(dout[127:0]) | |
528 | ); | |
529 | ||
530 | ||
531 | ||
532 | ||
533 | ||
534 | ||
535 | ||
536 | ||
537 | ||
538 | ||
539 | ||
540 | ||
541 | endmodule | |
542 | ||
543 | ||
544 | ||
545 | ||
546 | ||
547 | ||
548 | ||
549 | ||
550 | ||
551 | ||
552 | ||
553 | ||
554 | ||
555 | // any PARAMS parms go into naming of macro | |
556 | ||
557 | module rst_ucbbusout4_ctl_l1clkhdr_ctl_macro ( | |
558 | l2clk, | |
559 | l1en, | |
560 | pce_ov, | |
561 | stop, | |
562 | se, | |
563 | l1clk); | |
564 | ||
565 | ||
566 | input l2clk; | |
567 | input l1en; | |
568 | input pce_ov; | |
569 | input stop; | |
570 | input se; | |
571 | output l1clk; | |
572 | ||
573 | ||
574 | ||
575 | ||
576 | ||
577 | cl_sc1_l1hdr_8x c_0 ( | |
578 | ||
579 | ||
580 | .l2clk(l2clk), | |
581 | .pce(l1en), | |
582 | .l1clk(l1clk), | |
583 | .se(se), | |
584 | .pce_ov(pce_ov), | |
585 | .stop(stop) | |
586 | ); | |
587 | ||
588 | ||
589 | ||
590 | endmodule | |
591 | ||
592 | ||
593 | ||
594 | ||
595 | ||
596 | ||
597 | ||
598 |