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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: tlu_ras_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module tlu_ras_ctl ( | |
36 | l2clk, | |
37 | scan_in, | |
38 | tcu_pce_ov, | |
39 | spc_aclk, | |
40 | spc_bclk, | |
41 | tcu_scan_en, | |
42 | spc_aclk_wmr, | |
43 | wmr_scan_in, | |
44 | lsu_tlu_pmen, | |
45 | ftu_excp_way_d, | |
46 | ftu_excp_tid_d, | |
47 | ftu_excp_way_valid_d, | |
48 | dec_exc0_m, | |
49 | dec_exc1_m, | |
50 | dec_icache_perr_m, | |
51 | dec_tid0_m, | |
52 | dec_tid1_m, | |
53 | dec_inst_valid_m, | |
54 | dec_fgu_inst_m, | |
55 | dec_lsu_inst_m, | |
56 | dec_flush_b, | |
57 | fls_irf_cecc_b, | |
58 | fls_irf_uecc_b, | |
59 | fls_kill_irf_ecc_w, | |
60 | exu0_ecc_addr_m, | |
61 | exu1_ecc_addr_m, | |
62 | exu0_ecc_check_m, | |
63 | exu1_ecc_check_m, | |
64 | fls_f_cecc_w, | |
65 | fls_f_uecc_w, | |
66 | fgu_ecc_addr_fx2, | |
67 | fgu_ecc_check_fx2, | |
68 | fgu_pdist_beat2_fx1, | |
69 | lsu_tlu_twocycle_m, | |
70 | lsu_block_store_b, | |
71 | fls_load_dsfar, | |
72 | fls_ipe_dme_request, | |
73 | lsu_dttp_err_b, | |
74 | lsu_dtdp_err_b, | |
75 | lsu_dtmh_err_b, | |
76 | lsu_dcmh_err_g, | |
77 | lsu_dcvp_err_g, | |
78 | lsu_dctp_err_g, | |
79 | lsu_dcdp_err_g, | |
80 | lsu_dcl2c_err_g, | |
81 | lsu_dcl2u_err_g, | |
82 | lsu_dcl2nd_err_g, | |
83 | lsu_dcsoc_err_g, | |
84 | lsu_dcerr_tid_g, | |
85 | lsu_dcerr_sfar_g, | |
86 | lsu_sbdlc_err_g, | |
87 | lsu_sbdlu_err_g, | |
88 | lsu_sbdpc_err_g, | |
89 | lsu_sbdpu_err_g, | |
90 | lsu_sbapp_err_g, | |
91 | lsu_sbdiou_err_g, | |
92 | lsu_stberr_tid_g, | |
93 | lsu_stberr_index_g, | |
94 | lsu_stberr_priv_g, | |
95 | lsu_stb_flush_g, | |
96 | cel_tccp, | |
97 | cel_tcup, | |
98 | cel_syndrome, | |
99 | tlu_tca_tid, | |
100 | tlu_tca_index, | |
101 | tlu_tsac, | |
102 | tlu_tsau, | |
103 | asi_tsac, | |
104 | asi_tsau, | |
105 | asi_tsacu_tid, | |
106 | tlu_tccd, | |
107 | tlu_tcud, | |
108 | tlu_tca_index_0, | |
109 | tlu_tca_index_1, | |
110 | tsd_pc_0_w, | |
111 | tsd_pc_1_w, | |
112 | fls_flush, | |
113 | fls_disrupting_flush_w, | |
114 | trl_gl0, | |
115 | trl_gl1, | |
116 | trl_gl2, | |
117 | trl_gl3, | |
118 | trl_gl4, | |
119 | trl_gl5, | |
120 | trl_gl6, | |
121 | trl_gl7, | |
122 | mmu_asi_cecc, | |
123 | mmu_asi_uecc, | |
124 | mmu_asi_index, | |
125 | mmu_asi_mra_not_sca, | |
126 | mmu_i_l2cerr, | |
127 | mmu_d_l2cerr, | |
128 | mmu_i_eccerr, | |
129 | mmu_d_eccerr, | |
130 | mmu_thr0_err_type, | |
131 | mmu_thr1_err_type, | |
132 | mmu_thr2_err_type, | |
133 | mmu_thr3_err_type, | |
134 | mmu_thr4_err_type, | |
135 | mmu_thr5_err_type, | |
136 | mmu_thr6_err_type, | |
137 | mmu_thr7_err_type, | |
138 | mmu_thr0_err_index, | |
139 | mmu_thr1_err_index, | |
140 | mmu_thr2_err_index, | |
141 | mmu_thr3_err_index, | |
142 | mmu_thr4_err_index, | |
143 | mmu_thr5_err_index, | |
144 | mmu_thr6_err_index, | |
145 | mmu_thr7_err_index, | |
146 | spu_tlu_mamu_err_req_v, | |
147 | spu_tlu_mamu_err_req, | |
148 | spu_tlu_ma_int_req, | |
149 | spu_tlu_cwq_int_req, | |
150 | spu_tlu_l2_error, | |
151 | cxi_l2_soc_sre, | |
152 | cxi_l2_soc_err_type, | |
153 | cxi_l2_soc_tid, | |
154 | cxi_l2_err, | |
155 | cxi_soc_err, | |
156 | asi_rd_isfsr, | |
157 | asi_rd_dsfsr, | |
158 | asi_rd_dsfar, | |
159 | asi_rd_desr, | |
160 | asi_rd_fesr, | |
161 | asi_rd_tid, | |
162 | asi_wr_isfsr, | |
163 | asi_wr_dsfsr, | |
164 | asi_wr_data, | |
165 | dfd_desr_f, | |
166 | dfd_desr_s, | |
167 | dfd_fesr_f, | |
168 | dfd_fesr_priv_0, | |
169 | dfd_fesr_priv_1, | |
170 | dfd_fesr_priv_2, | |
171 | dfd_fesr_priv_3, | |
172 | dfd_fesr_priv_4, | |
173 | dfd_fesr_priv_5, | |
174 | dfd_fesr_priv_6, | |
175 | dfd_fesr_priv_7, | |
176 | wmr_scan_out, | |
177 | scan_out, | |
178 | ras_asi_data, | |
179 | ras_dsfar_0, | |
180 | ras_dsfar_1, | |
181 | ras_dsfar_2, | |
182 | ras_dsfar_3, | |
183 | ras_dsfar_4, | |
184 | ras_dsfar_5, | |
185 | ras_dsfar_6, | |
186 | ras_dsfar_7, | |
187 | ras_dsfar_sel_lsu_va, | |
188 | ras_dsfar_sel_ras, | |
189 | ras_dsfar_sel_tsa, | |
190 | ras_rd_dsfar, | |
191 | ras_desr_et_0, | |
192 | ras_desr_et_1, | |
193 | ras_desr_et_2, | |
194 | ras_desr_et_3, | |
195 | ras_desr_et_4, | |
196 | ras_desr_et_5, | |
197 | ras_desr_et_6, | |
198 | ras_desr_et_7, | |
199 | ras_desr_ea_0, | |
200 | ras_desr_ea_1, | |
201 | ras_desr_ea_2, | |
202 | ras_desr_ea_3, | |
203 | ras_desr_ea_4, | |
204 | ras_desr_ea_5, | |
205 | ras_desr_ea_6, | |
206 | ras_desr_ea_7, | |
207 | ras_desr_me_0, | |
208 | ras_desr_me_1, | |
209 | ras_desr_me_2, | |
210 | ras_desr_me_3, | |
211 | ras_desr_me_4, | |
212 | ras_desr_me_5, | |
213 | ras_desr_me_6, | |
214 | ras_desr_me_7, | |
215 | ras_desr_en, | |
216 | ras_write_desr_1st, | |
217 | ras_write_desr_2nd, | |
218 | ras_rd_desr, | |
219 | ras_fesr_et_0, | |
220 | ras_fesr_et_1, | |
221 | ras_fesr_et_2, | |
222 | ras_fesr_et_3, | |
223 | ras_fesr_et_4, | |
224 | ras_fesr_et_5, | |
225 | ras_fesr_et_6, | |
226 | ras_fesr_et_7, | |
227 | ras_fesr_ea_0, | |
228 | ras_fesr_ea_1, | |
229 | ras_fesr_ea_2, | |
230 | ras_fesr_ea_3, | |
231 | ras_fesr_ea_4, | |
232 | ras_fesr_ea_5, | |
233 | ras_fesr_ea_6, | |
234 | ras_fesr_ea_7, | |
235 | ras_fesr_en, | |
236 | ras_write_fesr, | |
237 | ras_fesr_priv, | |
238 | ras_update_priv, | |
239 | ras_rd_fesr, | |
240 | ras_precise_error, | |
241 | ras_disrupting_error, | |
242 | ras_deferred_error); | |
243 | wire pce_ov; | |
244 | wire stop; | |
245 | wire siclk; | |
246 | wire soclk; | |
247 | wire se; | |
248 | wire l1clk; | |
249 | wire l1en_any_b2w; | |
250 | wire [1:0] inst_valid_b; | |
251 | wire w_en; | |
252 | wire w1_en; | |
253 | wire l1clk_pm1; | |
254 | wire l1en_pm2; | |
255 | wire excp_way_valid; | |
256 | wire l1clk_pm2; | |
257 | wire [1:0] twocycle_inst_m; | |
258 | wire twocycle_inst_b_lat_scanin; | |
259 | wire twocycle_inst_b_lat_scanout; | |
260 | wire [1:0] ptwocycle_inst_b; | |
261 | wire [1:0] twocycle_inst_b; | |
262 | wire [1:0] fgu_inst_b; | |
263 | wire [1:0] inst_valid_m; | |
264 | wire inst_valid_b_lat_scanin; | |
265 | wire inst_valid_b_lat_scanout; | |
266 | wire w_en_in; | |
267 | wire w_en_lat_scanin; | |
268 | wire w_en_lat_scanout; | |
269 | wire w1_en_lat_scanin; | |
270 | wire w1_en_lat_scanout; | |
271 | wire [1:0] flush_b; | |
272 | wire [7:0] tid_dec_b; | |
273 | wire [1:0] inst_valid_w_in; | |
274 | wire inst_valid_w_lat_scanin; | |
275 | wire inst_valid_w_lat_scanout; | |
276 | wire [1:0] pre_inst_valid_w; | |
277 | wire [7:0] block_store_w_in; | |
278 | wire block_store_w_lat_scanin; | |
279 | wire block_store_w_lat_scanout; | |
280 | wire [7:0] pblock_store_w; | |
281 | wire [7:0] block_store_w; | |
282 | wire seen_bsee; | |
283 | wire [1:0] inst_valid_w; | |
284 | wire [1:0] tid1_m; | |
285 | wire [1:0] tid1_b; | |
286 | wire tid1_b_lat_scanin; | |
287 | wire tid1_b_lat_scanout; | |
288 | wire [1:0] tid0_m; | |
289 | wire [1:0] tid0_b; | |
290 | wire tid0_b_lat_scanin; | |
291 | wire tid0_b_lat_scanout; | |
292 | wire tid1_w_lat_scanin; | |
293 | wire tid1_w_lat_scanout; | |
294 | wire [1:0] tid1_w; | |
295 | wire tid0_w_lat_scanin; | |
296 | wire tid0_w_lat_scanout; | |
297 | wire [1:0] tid0_w; | |
298 | wire [7:0] tid_dec_w; | |
299 | wire [1:0] fgu_inst_m; | |
300 | wire fgu_inst_b_lat_scanin; | |
301 | wire fgu_inst_b_lat_scanout; | |
302 | wire fgu_inst_w_lat_scanin; | |
303 | wire fgu_inst_w_lat_scanout; | |
304 | wire [1:0] pfgu_inst_w; | |
305 | wire [1:0] fgu_inst_w; | |
306 | wire [1:0] lsu_inst_m; | |
307 | wire lsu_inst_b_lat_scanin; | |
308 | wire lsu_inst_b_lat_scanout; | |
309 | wire [1:0] lsu_inst_b; | |
310 | wire [1:0] ittp_m; | |
311 | wire [1:0] ittm_m; | |
312 | wire [1:0] itdp_m; | |
313 | wire [1:0] icl2u_m; | |
314 | wire [1:0] icl2nd_m; | |
315 | wire [2:0] i_isfsr1_m; | |
316 | wire [2:0] i_isfsr0_m; | |
317 | wire i_isfsr1_b_lat_scanin; | |
318 | wire i_isfsr1_b_lat_scanout; | |
319 | wire [2:0] i_isfsr1_b; | |
320 | wire i_isfsr0_b_lat_scanin; | |
321 | wire i_isfsr0_b_lat_scanout; | |
322 | wire [2:0] i_isfsr0_b; | |
323 | wire [1:0] icvp_m; | |
324 | wire [1:0] ictp_m; | |
325 | wire [1:0] ictm_m; | |
326 | wire [1:0] icl2c_m; | |
327 | wire [1:0] icdp_m; | |
328 | wire [3:0] i_desr1_m; | |
329 | wire [3:0] i_desr0_m; | |
330 | wire i_desr1_b_lat_scanin; | |
331 | wire i_desr1_b_lat_scanout; | |
332 | wire [3:0] i_desr1_b; | |
333 | wire i_desr0_b_lat_scanin; | |
334 | wire i_desr0_b_lat_scanout; | |
335 | wire [3:0] i_desr0_b; | |
336 | wire irf0_ecc_addr_b_lat_scanin; | |
337 | wire irf0_ecc_addr_b_lat_scanout; | |
338 | wire [4:0] irf0_ecc_addr_b; | |
339 | wire irf1_ecc_addr_b_lat_scanin; | |
340 | wire irf1_ecc_addr_b_lat_scanout; | |
341 | wire [4:0] irf1_ecc_addr_b; | |
342 | wire irf0_ecc_check_b_lat_scanin; | |
343 | wire irf0_ecc_check_b_lat_scanout; | |
344 | wire [7:0] irf0_ecc_check_b; | |
345 | wire irf1_ecc_check_b_lat_scanin; | |
346 | wire irf1_ecc_check_b_lat_scanout; | |
347 | wire [7:0] irf1_ecc_check_b; | |
348 | wire i_isfsr1_w_lat_scanin; | |
349 | wire i_isfsr1_w_lat_scanout; | |
350 | wire [2:0] i_isfsr1_w; | |
351 | wire i_isfsr0_w_lat_scanin; | |
352 | wire i_isfsr0_w_lat_scanout; | |
353 | wire [2:0] i_isfsr0_w; | |
354 | wire i_desr1_w_lat_scanin; | |
355 | wire i_desr1_w_lat_scanout; | |
356 | wire [3:0] i_desr1_w; | |
357 | wire i_desr0_w_lat_scanin; | |
358 | wire i_desr0_w_lat_scanout; | |
359 | wire [3:0] i_desr0_w; | |
360 | wire [1:0] irfu_b; | |
361 | wire [1:0] irfc_b; | |
362 | wire [1:0] dtmh_b; | |
363 | wire [1:0] dttp_b; | |
364 | wire [1:0] dtdp_b; | |
365 | wire irfu_w_lat_scanin; | |
366 | wire irfu_w_lat_scanout; | |
367 | wire [1:0] pirfu_w; | |
368 | wire [1:0] irfu_w; | |
369 | wire irfc_w_lat_scanin; | |
370 | wire irfc_w_lat_scanout; | |
371 | wire [1:0] pirfc_w; | |
372 | wire [1:0] irfc_w; | |
373 | wire [1:0] pfrfu_w; | |
374 | wire [1:0] pfrfc_w; | |
375 | wire [1:0] frfu_w; | |
376 | wire [1:0] frfc_w; | |
377 | wire seen_bsee_in; | |
378 | wire seen_bsee_lat_scanin; | |
379 | wire seen_bsee_lat_scanout; | |
380 | wire dttp_w_lat_scanin; | |
381 | wire dttp_w_lat_scanout; | |
382 | wire [1:0] pdttp_w; | |
383 | wire [1:0] dttp_w; | |
384 | wire dtmh_w_lat_scanin; | |
385 | wire dtmh_w_lat_scanout; | |
386 | wire [1:0] pdtmh_w; | |
387 | wire [1:0] dtmh_w; | |
388 | wire dtdp_w_lat_scanin; | |
389 | wire dtdp_w_lat_scanout; | |
390 | wire [1:0] pdtdp_w; | |
391 | wire [1:0] dtdp_w; | |
392 | wire irf0_ecc_addr_w_lat_scanin; | |
393 | wire irf0_ecc_addr_w_lat_scanout; | |
394 | wire [4:0] irf0_ecc_addr_w; | |
395 | wire irf1_ecc_addr_w_lat_scanin; | |
396 | wire irf1_ecc_addr_w_lat_scanout; | |
397 | wire [4:0] irf1_ecc_addr_w; | |
398 | wire irf0_ecc_check_w_lat_scanin; | |
399 | wire irf0_ecc_check_w_lat_scanout; | |
400 | wire [7:0] irf0_ecc_check_w; | |
401 | wire irf1_ecc_check_w_lat_scanin; | |
402 | wire irf1_ecc_check_w_lat_scanout; | |
403 | wire [7:0] irf1_ecc_check_w; | |
404 | wire frf_ecc_addr_w_lat_scanin; | |
405 | wire frf_ecc_addr_w_lat_scanout; | |
406 | wire [5:0] frf_ecc_addr_w; | |
407 | wire frf_ecc_check_w_lat_scanin; | |
408 | wire frf_ecc_check_w_lat_scanout; | |
409 | wire [13:0] frf_ecc_check_w; | |
410 | wire [2:0] pipe_isfsr_7; | |
411 | wire [2:0] pipe_isfsr_6; | |
412 | wire [2:0] pipe_isfsr_5; | |
413 | wire [2:0] pipe_isfsr_4; | |
414 | wire [2:0] pipe_isfsr_3; | |
415 | wire [2:0] pipe_isfsr_2; | |
416 | wire [2:0] pipe_isfsr_1; | |
417 | wire [2:0] pipe_isfsr_0; | |
418 | wire [2:0] pipe_dsfsr1_w; | |
419 | wire [2:0] pipe_dsfsr0_w; | |
420 | wire [1:0] gl1_w; | |
421 | wire [1:0] gl0_w; | |
422 | wire [19:0] pipe_dsfar1_w; | |
423 | wire [19:0] pipe_dsfar0_w; | |
424 | wire [1:0] ecc_w; | |
425 | wire ecc_w1_lat_scanin; | |
426 | wire ecc_w1_lat_scanout; | |
427 | wire [1:0] ecc_w1; | |
428 | wire [1:0] tid1_w1_in; | |
429 | wire tid1_w1_lat_scanin; | |
430 | wire tid1_w1_lat_scanout; | |
431 | wire [1:0] tid1_w1; | |
432 | wire [1:0] tid0_w1_in; | |
433 | wire tid0_w1_lat_scanin; | |
434 | wire tid0_w1_lat_scanout; | |
435 | wire [1:0] tid0_w1; | |
436 | wire pipe_dsfsr1_lat_scanin; | |
437 | wire pipe_dsfsr1_lat_scanout; | |
438 | wire [2:0] pipe_dsfsr1; | |
439 | wire pipe_dsfsr0_lat_scanin; | |
440 | wire pipe_dsfsr0_lat_scanout; | |
441 | wire [2:0] pipe_dsfsr0; | |
442 | wire pipe_dsfar1_lat_scanin; | |
443 | wire pipe_dsfar1_lat_scanout; | |
444 | wire [19:0] pipe_dsfar1; | |
445 | wire pipe_dsfar0_lat_scanin; | |
446 | wire pipe_dsfar0_lat_scanout; | |
447 | wire [19:0] pipe_dsfar0; | |
448 | wire [7:0] tid_dec_w1; | |
449 | wire [2:0] pipe_dsfsr_7; | |
450 | wire [2:0] pipe_dsfsr_6; | |
451 | wire [2:0] pipe_dsfsr_5; | |
452 | wire [2:0] pipe_dsfsr_4; | |
453 | wire [2:0] pipe_dsfsr_3; | |
454 | wire [2:0] pipe_dsfsr_2; | |
455 | wire [2:0] pipe_dsfsr_1; | |
456 | wire [2:0] pipe_dsfsr_0; | |
457 | wire [19:0] pipe_dsfar_7; | |
458 | wire [19:0] pipe_dsfar_6; | |
459 | wire [19:0] pipe_dsfar_5; | |
460 | wire [19:0] pipe_dsfar_4; | |
461 | wire [19:0] pipe_dsfar_3; | |
462 | wire [19:0] pipe_dsfar_2; | |
463 | wire [19:0] pipe_dsfar_1; | |
464 | wire [19:0] pipe_dsfar_0; | |
465 | wire [7:0] dsfar_sel_lsu_va_for_error; | |
466 | wire load_dsfar_lat_scanin; | |
467 | wire load_dsfar_lat_scanout; | |
468 | wire [7:0] load_dsfar; | |
469 | wire [3:0] i_desr1_w1_in; | |
470 | wire [3:0] i_desr0_w1_in; | |
471 | wire i_desr1_w1_lat_scanin; | |
472 | wire i_desr1_w1_lat_scanout; | |
473 | wire [3:0] i_desr1_w1; | |
474 | wire i_desr0_w1_lat_scanin; | |
475 | wire i_desr0_w1_lat_scanout; | |
476 | wire [3:0] i_desr0_w1; | |
477 | wire [5:0] pipe_desr_et_7; | |
478 | wire [5:0] pipe_desr_et_6; | |
479 | wire [5:0] pipe_desr_et_5; | |
480 | wire [5:0] pipe_desr_et_4; | |
481 | wire [5:0] pipe_desr_et_3; | |
482 | wire [5:0] pipe_desr_et_2; | |
483 | wire [5:0] pipe_desr_et_1; | |
484 | wire [5:0] pipe_desr_et_0; | |
485 | wire excp_way_lat_scanin; | |
486 | wire excp_way_lat_scanout; | |
487 | wire [2:0] excp_tid; | |
488 | wire [2:0] excp_way; | |
489 | wire [7:0] sel_ftu_excp_way; | |
490 | wire [2:0] ic_way7_in; | |
491 | wire [2:0] ic_way7; | |
492 | wire [2:0] ic_way6_in; | |
493 | wire [2:0] ic_way6; | |
494 | wire [2:0] ic_way5_in; | |
495 | wire [2:0] ic_way5; | |
496 | wire [2:0] ic_way4_in; | |
497 | wire [2:0] ic_way4; | |
498 | wire [2:0] ic_way3_in; | |
499 | wire [2:0] ic_way3; | |
500 | wire [2:0] ic_way2_in; | |
501 | wire [2:0] ic_way2; | |
502 | wire [2:0] ic_way1_in; | |
503 | wire [2:0] ic_way1; | |
504 | wire [2:0] ic_way0_in; | |
505 | wire [2:0] ic_way0; | |
506 | wire ic_way7_lat_scanin; | |
507 | wire ic_way7_lat_scanout; | |
508 | wire ic_way6_lat_scanin; | |
509 | wire ic_way6_lat_scanout; | |
510 | wire ic_way5_lat_scanin; | |
511 | wire ic_way5_lat_scanout; | |
512 | wire ic_way4_lat_scanin; | |
513 | wire ic_way4_lat_scanout; | |
514 | wire ic_way3_lat_scanin; | |
515 | wire ic_way3_lat_scanout; | |
516 | wire ic_way2_lat_scanin; | |
517 | wire ic_way2_lat_scanout; | |
518 | wire ic_way1_lat_scanin; | |
519 | wire ic_way1_lat_scanout; | |
520 | wire ic_way0_lat_scanin; | |
521 | wire ic_way0_lat_scanout; | |
522 | wire pc_1_w1_lat_scanin; | |
523 | wire pc_1_w1_lat_scanout; | |
524 | wire [10:5] pc_1_w1; | |
525 | wire pc_0_w1_lat_scanin; | |
526 | wire pc_0_w1_lat_scanout; | |
527 | wire [10:5] pc_0_w1; | |
528 | wire [8:0] pipe_desr_ea_7; | |
529 | wire [8:0] pipe_desr_ea_6; | |
530 | wire [8:0] pipe_desr_ea_5; | |
531 | wire [8:0] pipe_desr_ea_4; | |
532 | wire [8:0] pipe_desr_ea_3; | |
533 | wire [8:0] pipe_desr_ea_2; | |
534 | wire [8:0] pipe_desr_ea_1; | |
535 | wire [8:0] pipe_desr_ea_0; | |
536 | wire itmu_7; | |
537 | wire itmu_6; | |
538 | wire itmu_5; | |
539 | wire itmu_4; | |
540 | wire itmu_3; | |
541 | wire itmu_2; | |
542 | wire itmu_1; | |
543 | wire itmu_0; | |
544 | wire itl2u_7; | |
545 | wire itl2u_6; | |
546 | wire itl2u_5; | |
547 | wire itl2u_4; | |
548 | wire itl2u_3; | |
549 | wire itl2u_2; | |
550 | wire itl2u_1; | |
551 | wire itl2u_0; | |
552 | wire itl2nd_7; | |
553 | wire itl2nd_6; | |
554 | wire itl2nd_5; | |
555 | wire itl2nd_4; | |
556 | wire itl2nd_3; | |
557 | wire itl2nd_2; | |
558 | wire itl2nd_1; | |
559 | wire itl2nd_0; | |
560 | wire [2:0] m_isfsr_7; | |
561 | wire [2:0] m_isfsr_6; | |
562 | wire [2:0] m_isfsr_5; | |
563 | wire [2:0] m_isfsr_4; | |
564 | wire [2:0] m_isfsr_3; | |
565 | wire [2:0] m_isfsr_2; | |
566 | wire [2:0] m_isfsr_1; | |
567 | wire [2:0] m_isfsr_0; | |
568 | wire dtmu_7; | |
569 | wire dtmu_6; | |
570 | wire dtmu_5; | |
571 | wire dtmu_4; | |
572 | wire dtmu_3; | |
573 | wire dtmu_2; | |
574 | wire dtmu_1; | |
575 | wire dtmu_0; | |
576 | wire dtl2u_7; | |
577 | wire dtl2u_6; | |
578 | wire dtl2u_5; | |
579 | wire dtl2u_4; | |
580 | wire dtl2u_3; | |
581 | wire dtl2u_2; | |
582 | wire dtl2u_1; | |
583 | wire dtl2u_0; | |
584 | wire dtl2nd_7; | |
585 | wire dtl2nd_6; | |
586 | wire dtl2nd_5; | |
587 | wire dtl2nd_4; | |
588 | wire dtl2nd_3; | |
589 | wire dtl2nd_2; | |
590 | wire dtl2nd_1; | |
591 | wire dtl2nd_0; | |
592 | wire [2:0] m_dsfsr_7; | |
593 | wire [2:0] m_dsfsr_6; | |
594 | wire [2:0] m_dsfsr_5; | |
595 | wire [2:0] m_dsfsr_4; | |
596 | wire [2:0] m_dsfsr_3; | |
597 | wire [2:0] m_dsfsr_2; | |
598 | wire [2:0] m_dsfsr_1; | |
599 | wire [2:0] m_dsfsr_0; | |
600 | wire [2:0] m_dsfar_7; | |
601 | wire [2:0] m_dsfar_6; | |
602 | wire [2:0] m_dsfar_5; | |
603 | wire [2:0] m_dsfar_4; | |
604 | wire [2:0] m_dsfar_3; | |
605 | wire [2:0] m_dsfar_2; | |
606 | wire [2:0] m_dsfar_1; | |
607 | wire [2:0] m_dsfar_0; | |
608 | wire it2lc_lat_scanin; | |
609 | wire it2lc_lat_scanout; | |
610 | wire [7:0] m_i_l2cerr; | |
611 | wire dt2lc_lat_scanin; | |
612 | wire dt2lc_lat_scanout; | |
613 | wire [7:0] m_d_l2cerr; | |
614 | wire itl2c_7; | |
615 | wire itl2c_6; | |
616 | wire itl2c_5; | |
617 | wire itl2c_4; | |
618 | wire itl2c_3; | |
619 | wire itl2c_2; | |
620 | wire itl2c_1; | |
621 | wire itl2c_0; | |
622 | wire dtl2c_7; | |
623 | wire dtl2c_6; | |
624 | wire dtl2c_5; | |
625 | wire dtl2c_4; | |
626 | wire dtl2c_3; | |
627 | wire dtl2c_2; | |
628 | wire dtl2c_1; | |
629 | wire dtl2c_0; | |
630 | wire [5:0] m_desr_et_7; | |
631 | wire [5:0] m_desr_et_6; | |
632 | wire [5:0] m_desr_et_5; | |
633 | wire [5:0] m_desr_et_4; | |
634 | wire [5:0] m_desr_et_3; | |
635 | wire [5:0] m_desr_et_2; | |
636 | wire [5:0] m_desr_et_1; | |
637 | wire [5:0] m_desr_et_0; | |
638 | wire [2:0] a_tid; | |
639 | wire [7:0] a_dec_tid; | |
640 | wire mrau; | |
641 | wire scac; | |
642 | wire scau; | |
643 | wire tca_error_lat_scanin; | |
644 | wire tca_error_lat_scanout; | |
645 | wire tccp; | |
646 | wire tcup; | |
647 | wire [2:0] tca_tid; | |
648 | wire [7:0] tca_dec_tid; | |
649 | wire [3:0] a_dsfsr; | |
650 | wire [3:0] tca_dsfsr; | |
651 | wire [3:0] a_dsfsr_7; | |
652 | wire [3:0] a_dsfsr_6; | |
653 | wire [3:0] a_dsfsr_5; | |
654 | wire [3:0] a_dsfsr_4; | |
655 | wire [3:0] a_dsfsr_3; | |
656 | wire [3:0] a_dsfsr_2; | |
657 | wire [3:0] a_dsfsr_1; | |
658 | wire [3:0] a_dsfsr_0; | |
659 | wire [10:0] a_dsfar; | |
660 | wire [10:0] tca_dsfar; | |
661 | wire [10:0] a_dsfar_7; | |
662 | wire [10:0] a_dsfar_6; | |
663 | wire [10:0] a_dsfar_5; | |
664 | wire [10:0] a_dsfar_4; | |
665 | wire [10:0] a_dsfar_3; | |
666 | wire [10:0] a_dsfar_2; | |
667 | wire [10:0] a_dsfar_1; | |
668 | wire [10:0] a_dsfar_0; | |
669 | wire [7:0] ta_dec_tid; | |
670 | wire [7:0] tsac; | |
671 | wire [7:0] tsau; | |
672 | wire [3:0] t_dsfsr_7; | |
673 | wire [3:0] t_dsfsr_6; | |
674 | wire [3:0] t_dsfsr_5; | |
675 | wire [3:0] t_dsfsr_4; | |
676 | wire [3:0] t_dsfsr_3; | |
677 | wire [3:0] t_dsfsr_2; | |
678 | wire [3:0] t_dsfsr_1; | |
679 | wire [3:0] t_dsfsr_0; | |
680 | wire l_dsfar_lat_scanin; | |
681 | wire l_dsfar_lat_scanout; | |
682 | wire [8:0] l_dsfar; | |
683 | wire l_tid_lat_scanin; | |
684 | wire l_tid_lat_scanout; | |
685 | wire [2:0] l_tid; | |
686 | wire dcl2c_lat_scanin; | |
687 | wire dcl2c_lat_scanout; | |
688 | wire dcl2c; | |
689 | wire dcl2u_lat_scanin; | |
690 | wire dcl2u_lat_scanout; | |
691 | wire dcl2u; | |
692 | wire dcl2nd_lat_scanin; | |
693 | wire dcl2nd_lat_scanout; | |
694 | wire dcl2nd; | |
695 | wire dcsoc_lat_scanin; | |
696 | wire dcsoc_lat_scanout; | |
697 | wire dcsoc; | |
698 | wire [7:0] l_dec_tid; | |
699 | wire [2:0] l_dsfsr; | |
700 | wire [2:0] l_dsfsr_7; | |
701 | wire [2:0] l_dsfsr_6; | |
702 | wire [2:0] l_dsfsr_5; | |
703 | wire [2:0] l_dsfsr_4; | |
704 | wire [2:0] l_dsfsr_3; | |
705 | wire [2:0] l_dsfsr_2; | |
706 | wire [2:0] l_dsfsr_1; | |
707 | wire [2:0] l_dsfsr_0; | |
708 | wire [8:0] l_dsfar_7; | |
709 | wire [8:0] l_dsfar_6; | |
710 | wire [8:0] l_dsfar_5; | |
711 | wire [8:0] l_dsfar_4; | |
712 | wire [8:0] l_dsfar_3; | |
713 | wire [8:0] l_dsfar_2; | |
714 | wire [8:0] l_dsfar_1; | |
715 | wire [8:0] l_dsfar_0; | |
716 | wire [5:0] l_desr_et; | |
717 | wire [5:0] l_desr_et_7; | |
718 | wire [5:0] l_desr_et_6; | |
719 | wire [5:0] l_desr_et_5; | |
720 | wire [5:0] l_desr_et_4; | |
721 | wire [5:0] l_desr_et_3; | |
722 | wire [5:0] l_desr_et_2; | |
723 | wire [5:0] l_desr_et_1; | |
724 | wire [5:0] l_desr_et_0; | |
725 | wire s_dsfar_lat_scanin; | |
726 | wire s_dsfar_lat_scanout; | |
727 | wire [1:0] fesr_priv; | |
728 | wire [2:0] s_dsfar; | |
729 | wire s_tid_lat_scanin; | |
730 | wire s_tid_lat_scanout; | |
731 | wire [2:0] s_tid; | |
732 | wire stb_flush_lat_scanin; | |
733 | wire stb_flush_lat_scanout; | |
734 | wire stb_flush; | |
735 | wire [7:0] update_priv; | |
736 | wire [7:0] s_dsfsr_dec_tid_raw; | |
737 | wire sbdlc_lat_scanin; | |
738 | wire sbdlc_lat_scanout; | |
739 | wire sbdlc; | |
740 | wire sbdlu_lat_scanin; | |
741 | wire sbdlu_lat_scanout; | |
742 | wire sbdlu; | |
743 | wire [7:0] s_dsfsr_dec_tid; | |
744 | wire [2:0] s_dsfsr; | |
745 | wire [2:0] s_dsfsr_7; | |
746 | wire [2:0] s_dsfsr_6; | |
747 | wire [2:0] s_dsfsr_5; | |
748 | wire [2:0] s_dsfsr_4; | |
749 | wire [2:0] s_dsfsr_3; | |
750 | wire [2:0] s_dsfsr_2; | |
751 | wire [2:0] s_dsfsr_1; | |
752 | wire [2:0] s_dsfsr_0; | |
753 | wire [2:0] s_dsfar_7; | |
754 | wire [2:0] s_dsfar_6; | |
755 | wire [2:0] s_dsfar_5; | |
756 | wire [2:0] s_dsfar_4; | |
757 | wire [2:0] s_dsfar_3; | |
758 | wire [2:0] s_dsfar_2; | |
759 | wire [2:0] s_dsfar_1; | |
760 | wire [2:0] s_dsfar_0; | |
761 | wire [2:0] isfsr_7_new_in; | |
762 | wire [2:0] isfsr_6_new_in; | |
763 | wire [2:0] isfsr_5_new_in; | |
764 | wire [2:0] isfsr_4_new_in; | |
765 | wire [2:0] isfsr_3_new_in; | |
766 | wire [2:0] isfsr_2_new_in; | |
767 | wire [2:0] isfsr_1_new_in; | |
768 | wire [2:0] isfsr_0_new_in; | |
769 | wire [2:0] isfsr_7_in; | |
770 | wire [2:0] isfsr_7; | |
771 | wire [2:0] isfsr_6_in; | |
772 | wire [2:0] isfsr_6; | |
773 | wire [2:0] isfsr_5_in; | |
774 | wire [2:0] isfsr_5; | |
775 | wire [2:0] isfsr_4_in; | |
776 | wire [2:0] isfsr_4; | |
777 | wire [2:0] isfsr_3_in; | |
778 | wire [2:0] isfsr_3; | |
779 | wire [2:0] isfsr_2_in; | |
780 | wire [2:0] isfsr_2; | |
781 | wire [2:0] isfsr_1_in; | |
782 | wire [2:0] isfsr_1; | |
783 | wire [2:0] isfsr_0_in; | |
784 | wire [2:0] isfsr_0; | |
785 | wire [7:0] precise_i_error; | |
786 | wire isfsr_7_lat_wmr_scanin; | |
787 | wire isfsr_7_lat_wmr_scanout; | |
788 | wire isfsr_6_lat_wmr_scanin; | |
789 | wire isfsr_6_lat_wmr_scanout; | |
790 | wire isfsr_5_lat_wmr_scanin; | |
791 | wire isfsr_5_lat_wmr_scanout; | |
792 | wire isfsr_4_lat_wmr_scanin; | |
793 | wire isfsr_4_lat_wmr_scanout; | |
794 | wire isfsr_3_lat_wmr_scanin; | |
795 | wire isfsr_3_lat_wmr_scanout; | |
796 | wire isfsr_2_lat_wmr_scanin; | |
797 | wire isfsr_2_lat_wmr_scanout; | |
798 | wire isfsr_1_lat_wmr_scanin; | |
799 | wire isfsr_1_lat_wmr_scanout; | |
800 | wire isfsr_0_lat_wmr_scanin; | |
801 | wire isfsr_0_lat_wmr_scanout; | |
802 | wire [3:0] dsfsr_7_new_in; | |
803 | wire [3:0] dsfsr_6_new_in; | |
804 | wire [3:0] dsfsr_5_new_in; | |
805 | wire [3:0] dsfsr_4_new_in; | |
806 | wire [3:0] dsfsr_3_new_in; | |
807 | wire [3:0] dsfsr_2_new_in; | |
808 | wire [3:0] dsfsr_1_new_in; | |
809 | wire [3:0] dsfsr_0_new_in; | |
810 | wire [3:0] dsfsr_7_in; | |
811 | wire [3:0] dsfsr_7; | |
812 | wire [3:0] dsfsr_6_in; | |
813 | wire [3:0] dsfsr_6; | |
814 | wire [3:0] dsfsr_5_in; | |
815 | wire [3:0] dsfsr_5; | |
816 | wire [3:0] dsfsr_4_in; | |
817 | wire [3:0] dsfsr_4; | |
818 | wire [3:0] dsfsr_3_in; | |
819 | wire [3:0] dsfsr_3; | |
820 | wire [3:0] dsfsr_2_in; | |
821 | wire [3:0] dsfsr_2; | |
822 | wire [3:0] dsfsr_1_in; | |
823 | wire [3:0] dsfsr_1; | |
824 | wire [3:0] dsfsr_0_in; | |
825 | wire [3:0] dsfsr_0; | |
826 | wire [7:0] precise_d_error; | |
827 | wire dsfsr_7_lat_wmr_scanin; | |
828 | wire dsfsr_7_lat_wmr_scanout; | |
829 | wire dsfsr_6_lat_wmr_scanin; | |
830 | wire dsfsr_6_lat_wmr_scanout; | |
831 | wire dsfsr_5_lat_wmr_scanin; | |
832 | wire dsfsr_5_lat_wmr_scanout; | |
833 | wire dsfsr_4_lat_wmr_scanin; | |
834 | wire dsfsr_4_lat_wmr_scanout; | |
835 | wire dsfsr_3_lat_wmr_scanin; | |
836 | wire dsfsr_3_lat_wmr_scanout; | |
837 | wire dsfsr_2_lat_wmr_scanin; | |
838 | wire dsfsr_2_lat_wmr_scanout; | |
839 | wire dsfsr_1_lat_wmr_scanin; | |
840 | wire dsfsr_1_lat_wmr_scanout; | |
841 | wire dsfsr_0_lat_wmr_scanin; | |
842 | wire dsfsr_0_lat_wmr_scanout; | |
843 | wire asi_rd_ctl_lat_scanin; | |
844 | wire asi_rd_ctl_lat_scanout; | |
845 | wire rd_isfsr; | |
846 | wire rd_dsfsr; | |
847 | wire rd_dsfar; | |
848 | wire rd_desr; | |
849 | wire rd_fesr; | |
850 | wire [2:0] rd_tid; | |
851 | wire [7:0] rd_tid_dec; | |
852 | wire [7:0] rd_isfsr_dec; | |
853 | wire [7:0] rd_dsfsr_dec; | |
854 | wire [7:0] rd_desr_dec; | |
855 | wire dcvp_lat_scanin; | |
856 | wire dcvp_lat_scanout; | |
857 | wire dcvp; | |
858 | wire dctp_lat_scanin; | |
859 | wire dctp_lat_scanout; | |
860 | wire dctp; | |
861 | wire dctm_lat_scanin; | |
862 | wire dctm_lat_scanout; | |
863 | wire dctm; | |
864 | wire dcdp_lat_scanin; | |
865 | wire dcdp_lat_scanout; | |
866 | wire dcdp; | |
867 | wire [7:0] d_dec_tid; | |
868 | wire [3:0] d_desr_et; | |
869 | wire [3:0] d_desr_et_7; | |
870 | wire [3:0] d_desr_et_6; | |
871 | wire [3:0] d_desr_et_5; | |
872 | wire [3:0] d_desr_et_4; | |
873 | wire [3:0] d_desr_et_3; | |
874 | wire [3:0] d_desr_et_2; | |
875 | wire [3:0] d_desr_et_1; | |
876 | wire [3:0] d_desr_et_0; | |
877 | wire [8:0] d_desr_ea_7; | |
878 | wire [8:0] d_desr_ea_6; | |
879 | wire [8:0] d_desr_ea_5; | |
880 | wire [8:0] d_desr_ea_4; | |
881 | wire [8:0] d_desr_ea_3; | |
882 | wire [8:0] d_desr_ea_2; | |
883 | wire [8:0] d_desr_ea_1; | |
884 | wire [8:0] d_desr_ea_0; | |
885 | wire cxi_lat_scanin; | |
886 | wire cxi_lat_scanout; | |
887 | wire l2_err; | |
888 | wire soc_err; | |
889 | wire [1:0] c_l2_soc_err_type; | |
890 | wire [2:0] c_l2_soc_tid; | |
891 | wire c_l2_soc_sre; | |
892 | wire [7:0] c_l2_soc_dec_tid; | |
893 | wire [7:0] c_l2_err; | |
894 | wire [7:0] c_soc_err; | |
895 | wire [7:0] l2_dec_tid; | |
896 | wire l2ch; | |
897 | wire l2cs; | |
898 | wire soc; | |
899 | wire l2u; | |
900 | wire sou; | |
901 | wire l2nd; | |
902 | wire [5:0] l2_desr_et; | |
903 | wire [5:0] l2_desr_et_7; | |
904 | wire [5:0] l2_desr_et_6; | |
905 | wire [5:0] l2_desr_et_5; | |
906 | wire [5:0] l2_desr_et_4; | |
907 | wire [5:0] l2_desr_et_3; | |
908 | wire [5:0] l2_desr_et_2; | |
909 | wire [5:0] l2_desr_et_1; | |
910 | wire [5:0] l2_desr_et_0; | |
911 | wire sbdpc_lat_scanin; | |
912 | wire sbdpc_lat_scanout; | |
913 | wire sbdpc; | |
914 | wire sbdpu_lat_scanin; | |
915 | wire sbdpu_lat_scanout; | |
916 | wire sbdpu; | |
917 | wire [7:0] sb_dec_tid; | |
918 | wire [5:0] s_desr_et; | |
919 | wire [5:0] s_desr_et_7; | |
920 | wire [5:0] s_desr_et_6; | |
921 | wire [5:0] s_desr_et_5; | |
922 | wire [5:0] s_desr_et_4; | |
923 | wire [5:0] s_desr_et_3; | |
924 | wire [5:0] s_desr_et_2; | |
925 | wire [5:0] s_desr_et_1; | |
926 | wire [5:0] s_desr_et_0; | |
927 | wire [2:0] s_desr_ea_7; | |
928 | wire [2:0] s_desr_ea_6; | |
929 | wire [2:0] s_desr_ea_5; | |
930 | wire [2:0] s_desr_ea_4; | |
931 | wire [2:0] s_desr_ea_3; | |
932 | wire [2:0] s_desr_ea_2; | |
933 | wire [2:0] s_desr_ea_1; | |
934 | wire [2:0] s_desr_ea_0; | |
935 | wire mamu_err_lat_scanin; | |
936 | wire mamu_err_lat_scanout; | |
937 | wire mamu_err_v; | |
938 | wire [10:0] mamu_err; | |
939 | wire [7:0] mamu_dec_tid; | |
940 | wire [7:0] ma_dec_tid; | |
941 | wire [5:0] mamu_desr_et; | |
942 | wire [5:0] mamu_desr_et_7; | |
943 | wire [5:0] mamu_desr_et_6; | |
944 | wire [5:0] mamu_desr_et_5; | |
945 | wire [5:0] mamu_desr_et_4; | |
946 | wire [5:0] mamu_desr_et_3; | |
947 | wire [5:0] mamu_desr_et_2; | |
948 | wire [5:0] mamu_desr_et_1; | |
949 | wire [5:0] mamu_desr_et_0; | |
950 | wire [10:0] mamu_desr_ea_7; | |
951 | wire [10:0] mamu_desr_ea_6; | |
952 | wire [10:0] mamu_desr_ea_5; | |
953 | wire [10:0] mamu_desr_ea_4; | |
954 | wire [10:0] mamu_desr_ea_3; | |
955 | wire [10:0] mamu_desr_ea_2; | |
956 | wire [10:0] mamu_desr_ea_1; | |
957 | wire [10:0] mamu_desr_ea_0; | |
958 | wire ma_tid_lat_scanin; | |
959 | wire ma_tid_lat_scanout; | |
960 | wire [2:0] ma_tid; | |
961 | wire cwq_tid_lat_scanin; | |
962 | wire cwq_tid_lat_scanout; | |
963 | wire [2:0] cwq_tid; | |
964 | wire spu_error_lat_scanin; | |
965 | wire spu_error_lat_scanout; | |
966 | wire [5:0] spu_error; | |
967 | wire [7:0] cwq_dec_tid; | |
968 | wire mal2c; | |
969 | wire mal2u; | |
970 | wire mal2nd; | |
971 | wire cwql2c; | |
972 | wire cwql2u; | |
973 | wire cwql2nd; | |
974 | wire [5:0] ma_desr_et; | |
975 | wire [5:0] cwq_desr_et; | |
976 | wire [5:0] ma_desr_et_7; | |
977 | wire [5:0] ma_desr_et_6; | |
978 | wire [5:0] ma_desr_et_5; | |
979 | wire [5:0] ma_desr_et_4; | |
980 | wire [5:0] ma_desr_et_3; | |
981 | wire [5:0] ma_desr_et_2; | |
982 | wire [5:0] ma_desr_et_1; | |
983 | wire [5:0] ma_desr_et_0; | |
984 | wire [5:0] cwq_desr_et_7; | |
985 | wire [5:0] cwq_desr_et_6; | |
986 | wire [5:0] cwq_desr_et_5; | |
987 | wire [5:0] cwq_desr_et_4; | |
988 | wire [5:0] cwq_desr_et_3; | |
989 | wire [5:0] cwq_desr_et_2; | |
990 | wire [5:0] cwq_desr_et_1; | |
991 | wire [5:0] cwq_desr_et_0; | |
992 | wire [5:0] t_desr_et_7; | |
993 | wire [5:0] t_desr_et_6; | |
994 | wire [5:0] t_desr_et_5; | |
995 | wire [5:0] t_desr_et_4; | |
996 | wire [5:0] t_desr_et_3; | |
997 | wire [5:0] t_desr_et_2; | |
998 | wire [5:0] t_desr_et_1; | |
999 | wire [5:0] t_desr_et_0; | |
1000 | wire [9:0] t_desr_ea_7; | |
1001 | wire [9:0] t_desr_ea_6; | |
1002 | wire [9:0] t_desr_ea_5; | |
1003 | wire [9:0] t_desr_ea_4; | |
1004 | wire [9:0] t_desr_ea_3; | |
1005 | wire [9:0] t_desr_ea_2; | |
1006 | wire [9:0] t_desr_ea_1; | |
1007 | wire [9:0] t_desr_ea_0; | |
1008 | wire pipe_desr_exc_7; | |
1009 | wire pipe_desr_exc_6; | |
1010 | wire pipe_desr_exc_5; | |
1011 | wire pipe_desr_exc_4; | |
1012 | wire pipe_desr_exc_3; | |
1013 | wire pipe_desr_exc_2; | |
1014 | wire pipe_desr_exc_1; | |
1015 | wire pipe_desr_exc_0; | |
1016 | wire m_desr_exc_7; | |
1017 | wire m_desr_exc_6; | |
1018 | wire m_desr_exc_5; | |
1019 | wire m_desr_exc_4; | |
1020 | wire m_desr_exc_3; | |
1021 | wire m_desr_exc_2; | |
1022 | wire m_desr_exc_1; | |
1023 | wire m_desr_exc_0; | |
1024 | wire l_desr_exc_7; | |
1025 | wire l_desr_exc_6; | |
1026 | wire l_desr_exc_5; | |
1027 | wire l_desr_exc_4; | |
1028 | wire l_desr_exc_3; | |
1029 | wire l_desr_exc_2; | |
1030 | wire l_desr_exc_1; | |
1031 | wire l_desr_exc_0; | |
1032 | wire d_desr_exc_7; | |
1033 | wire d_desr_exc_6; | |
1034 | wire d_desr_exc_5; | |
1035 | wire d_desr_exc_4; | |
1036 | wire d_desr_exc_3; | |
1037 | wire d_desr_exc_2; | |
1038 | wire d_desr_exc_1; | |
1039 | wire d_desr_exc_0; | |
1040 | wire l2_desr_exc_7; | |
1041 | wire l2_desr_exc_6; | |
1042 | wire l2_desr_exc_5; | |
1043 | wire l2_desr_exc_4; | |
1044 | wire l2_desr_exc_3; | |
1045 | wire l2_desr_exc_2; | |
1046 | wire l2_desr_exc_1; | |
1047 | wire l2_desr_exc_0; | |
1048 | wire s_desr_exc_7; | |
1049 | wire s_desr_exc_6; | |
1050 | wire s_desr_exc_5; | |
1051 | wire s_desr_exc_4; | |
1052 | wire s_desr_exc_3; | |
1053 | wire s_desr_exc_2; | |
1054 | wire s_desr_exc_1; | |
1055 | wire s_desr_exc_0; | |
1056 | wire mamu_desr_exc_7; | |
1057 | wire mamu_desr_exc_6; | |
1058 | wire mamu_desr_exc_5; | |
1059 | wire mamu_desr_exc_4; | |
1060 | wire mamu_desr_exc_3; | |
1061 | wire mamu_desr_exc_2; | |
1062 | wire mamu_desr_exc_1; | |
1063 | wire mamu_desr_exc_0; | |
1064 | wire ma_desr_exc_7; | |
1065 | wire ma_desr_exc_6; | |
1066 | wire ma_desr_exc_5; | |
1067 | wire ma_desr_exc_4; | |
1068 | wire ma_desr_exc_3; | |
1069 | wire ma_desr_exc_2; | |
1070 | wire ma_desr_exc_1; | |
1071 | wire ma_desr_exc_0; | |
1072 | wire cwq_desr_exc_7; | |
1073 | wire cwq_desr_exc_6; | |
1074 | wire cwq_desr_exc_5; | |
1075 | wire cwq_desr_exc_4; | |
1076 | wire cwq_desr_exc_3; | |
1077 | wire cwq_desr_exc_2; | |
1078 | wire cwq_desr_exc_1; | |
1079 | wire cwq_desr_exc_0; | |
1080 | wire t_desr_exc_7; | |
1081 | wire t_desr_exc_6; | |
1082 | wire t_desr_exc_5; | |
1083 | wire t_desr_exc_4; | |
1084 | wire t_desr_exc_3; | |
1085 | wire t_desr_exc_2; | |
1086 | wire t_desr_exc_1; | |
1087 | wire t_desr_exc_0; | |
1088 | wire take_s_7; | |
1089 | wire no_desr_s_7; | |
1090 | wire take_s_6; | |
1091 | wire no_desr_s_6; | |
1092 | wire take_s_5; | |
1093 | wire no_desr_s_5; | |
1094 | wire take_s_4; | |
1095 | wire no_desr_s_4; | |
1096 | wire take_s_3; | |
1097 | wire no_desr_s_3; | |
1098 | wire take_s_2; | |
1099 | wire no_desr_s_2; | |
1100 | wire take_s_1; | |
1101 | wire no_desr_s_1; | |
1102 | wire take_s_0; | |
1103 | wire no_desr_s_0; | |
1104 | wire take_t_7; | |
1105 | wire take_t_6; | |
1106 | wire take_t_5; | |
1107 | wire take_t_4; | |
1108 | wire take_t_3; | |
1109 | wire take_t_2; | |
1110 | wire take_t_1; | |
1111 | wire take_t_0; | |
1112 | wire take_ma_7; | |
1113 | wire take_ma_6; | |
1114 | wire take_ma_5; | |
1115 | wire take_ma_4; | |
1116 | wire take_ma_3; | |
1117 | wire take_ma_2; | |
1118 | wire take_ma_1; | |
1119 | wire take_ma_0; | |
1120 | wire take_mamu_7; | |
1121 | wire take_mamu_6; | |
1122 | wire take_mamu_5; | |
1123 | wire take_mamu_4; | |
1124 | wire take_mamu_3; | |
1125 | wire take_mamu_2; | |
1126 | wire take_mamu_1; | |
1127 | wire take_mamu_0; | |
1128 | wire take_cwq_7; | |
1129 | wire take_cwq_6; | |
1130 | wire take_cwq_5; | |
1131 | wire take_cwq_4; | |
1132 | wire take_cwq_3; | |
1133 | wire take_cwq_2; | |
1134 | wire take_cwq_1; | |
1135 | wire take_cwq_0; | |
1136 | wire take_l2_7; | |
1137 | wire take_l2_6; | |
1138 | wire take_l2_5; | |
1139 | wire take_l2_4; | |
1140 | wire take_l2_3; | |
1141 | wire take_l2_2; | |
1142 | wire take_l2_1; | |
1143 | wire take_l2_0; | |
1144 | wire take_pipe_7; | |
1145 | wire take_pipe_6; | |
1146 | wire take_pipe_5; | |
1147 | wire take_pipe_4; | |
1148 | wire take_pipe_3; | |
1149 | wire take_pipe_2; | |
1150 | wire take_pipe_1; | |
1151 | wire take_pipe_0; | |
1152 | wire take_m_7; | |
1153 | wire take_m_6; | |
1154 | wire take_m_5; | |
1155 | wire take_m_4; | |
1156 | wire take_m_3; | |
1157 | wire take_m_2; | |
1158 | wire take_m_1; | |
1159 | wire take_m_0; | |
1160 | wire take_l_7; | |
1161 | wire take_l_6; | |
1162 | wire take_l_5; | |
1163 | wire take_l_4; | |
1164 | wire take_l_3; | |
1165 | wire take_l_2; | |
1166 | wire take_l_1; | |
1167 | wire take_l_0; | |
1168 | wire take_d_7; | |
1169 | wire take_d_6; | |
1170 | wire take_d_5; | |
1171 | wire take_d_4; | |
1172 | wire take_d_3; | |
1173 | wire take_d_2; | |
1174 | wire take_d_1; | |
1175 | wire take_d_0; | |
1176 | wire [7:0] write_desr; | |
1177 | wire [7:0] write_desr_s; | |
1178 | wire sbdiou_lat_scanin; | |
1179 | wire sbdiou_lat_scanout; | |
1180 | wire sbdiou; | |
1181 | wire sbapp_lat_scanin; | |
1182 | wire sbapp_lat_scanout; | |
1183 | wire sbapp; | |
1184 | wire [7:0] f_dec_tid; | |
1185 | wire [7:0] write_fesr; | |
1186 | wire [7:0] error_event_1_in; | |
1187 | wire [7:0] error_event_0_in; | |
1188 | wire event_1_lat_scanin; | |
1189 | wire event_1_lat_scanout; | |
1190 | wire [7:0] error_event_1; | |
1191 | wire event_0_lat_scanin; | |
1192 | wire event_0_lat_scanout; | |
1193 | wire [7:0] error_event_0; | |
1194 | wire spares_scanin; | |
1195 | wire spares_scanout; | |
1196 | wire spare0_lat_scanin; | |
1197 | wire spare0_lat_scanout; | |
1198 | wire spare0_unused; | |
1199 | wire spare1_lat_scanin; | |
1200 | wire spare1_lat_scanout; | |
1201 | wire spare1_unused; | |
1202 | wire spare2_lat_scanin; | |
1203 | wire spare2_lat_scanout; | |
1204 | wire spare2_unused; | |
1205 | wire spare3_lat_scanin; | |
1206 | wire spare3_lat_scanout; | |
1207 | wire spare3_unused; | |
1208 | wire spare4_lat_scanin; | |
1209 | wire spare4_lat_scanout; | |
1210 | wire spare4_unused; | |
1211 | wire spare5_lat_scanin; | |
1212 | wire spare5_lat_scanout; | |
1213 | wire spare5_unused; | |
1214 | wire spare6_lat_scanin; | |
1215 | wire spare6_lat_scanout; | |
1216 | wire spare6_unused; | |
1217 | wire spare7_lat_scanin; | |
1218 | wire spare7_lat_scanout; | |
1219 | wire spare7_unused; | |
1220 | wire spare8_lat_scanin; | |
1221 | wire spare8_lat_scanout; | |
1222 | wire spare8_unused; | |
1223 | wire spare9_lat_scanin; | |
1224 | wire spare9_lat_scanout; | |
1225 | wire spare9_unused; | |
1226 | wire spare10_lat_scanin; | |
1227 | wire spare10_lat_scanout; | |
1228 | wire spare10_unused; | |
1229 | wire spare11_lat_scanin; | |
1230 | wire spare11_lat_scanout; | |
1231 | wire spare11_unused; | |
1232 | wire spare12_lat_scanin; | |
1233 | wire spare12_lat_scanout; | |
1234 | wire spare12_unused; | |
1235 | wire spare13_lat_scanin; | |
1236 | wire spare13_lat_scanout; | |
1237 | wire spare13_unused; | |
1238 | wire spare14_lat_scanin; | |
1239 | wire spare14_lat_scanout; | |
1240 | wire spare14_unused; | |
1241 | wire spare15_lat_scanin; | |
1242 | wire spare15_lat_scanout; | |
1243 | wire spare15_unused; | |
1244 | ||
1245 | ||
1246 | ||
1247 | ||
1248 | input l2clk; | |
1249 | input scan_in; | |
1250 | input tcu_pce_ov; | |
1251 | input spc_aclk; | |
1252 | input spc_bclk; | |
1253 | input tcu_scan_en; | |
1254 | ||
1255 | input spc_aclk_wmr; // Warm reset (non)scan | |
1256 | input wmr_scan_in; | |
1257 | ||
1258 | input lsu_tlu_pmen; // Power management | |
1259 | ||
1260 | input [2:0] ftu_excp_way_d; | |
1261 | input [2:0] ftu_excp_tid_d; | |
1262 | input ftu_excp_way_valid_d; | |
1263 | ||
1264 | input [4:0] dec_exc0_m; | |
1265 | input [4:0] dec_exc1_m; | |
1266 | input [1:0] dec_icache_perr_m; | |
1267 | input [1:0] dec_tid0_m; | |
1268 | input [1:0] dec_tid1_m; | |
1269 | input [1:0] dec_inst_valid_m; | |
1270 | input [1:0] dec_fgu_inst_m; | |
1271 | input [1:0] dec_lsu_inst_m; | |
1272 | input [1:0] dec_flush_b; | |
1273 | ||
1274 | input [1:0] fls_irf_cecc_b; | |
1275 | input [1:0] fls_irf_uecc_b; | |
1276 | input [1:0] fls_kill_irf_ecc_w; | |
1277 | input [4:0] exu0_ecc_addr_m; | |
1278 | input [4:0] exu1_ecc_addr_m; | |
1279 | input [7:0] exu0_ecc_check_m; | |
1280 | input [7:0] exu1_ecc_check_m; | |
1281 | ||
1282 | input fls_f_cecc_w; | |
1283 | input fls_f_uecc_w; | |
1284 | input [5:0] fgu_ecc_addr_fx2; | |
1285 | input [13:0] fgu_ecc_check_fx2; | |
1286 | input fgu_pdist_beat2_fx1; | |
1287 | ||
1288 | input lsu_tlu_twocycle_m; // LSU takes extra cycle on this inst | |
1289 | input [7:0] lsu_block_store_b; // LSU reads FRF for block store | |
1290 | ||
1291 | input [7:0] fls_load_dsfar; // Trap that loads DSFAR | |
1292 | input [1:0] fls_ipe_dme_request; // Update DSFSR/DSFAR for IRF/FRF ECC | |
1293 | input lsu_dttp_err_b; // DTLB tag parity error | |
1294 | input lsu_dtdp_err_b; // DTLB data parity error | |
1295 | input lsu_dtmh_err_b; // DTLB data parity error | |
1296 | ||
1297 | input lsu_dcmh_err_g; // LSU data cache multiple hit | |
1298 | input lsu_dcvp_err_g; // LSU data cache valid parity error | |
1299 | input lsu_dctp_err_g; // LSU data cache tag parity error | |
1300 | input lsu_dcdp_err_g; // LSU data cache parity error | |
1301 | input lsu_dcl2c_err_g; // LSU data cache L2 correctable ECC | |
1302 | input lsu_dcl2u_err_g; // LSU data cache L2 uncorrectable ECC | |
1303 | input lsu_dcl2nd_err_g; // LSU data cache L2 NotData | |
1304 | input lsu_dcsoc_err_g; // LSU data cache SOC error | |
1305 | input [2:0] lsu_dcerr_tid_g; // TID for G stage errors (above) | |
1306 | input [8:0] lsu_dcerr_sfar_g; // Contains way and index of the error | |
1307 | ||
1308 | input lsu_sbdlc_err_g; // STB RAW error (CE) | |
1309 | input lsu_sbdlu_err_g; // STB RAW error (UE) | |
1310 | input lsu_sbdpc_err_g; // STB read for issue data (CE) | |
1311 | input lsu_sbdpu_err_g; // STB read for issue data (UE) | |
1312 | input lsu_sbapp_err_g; // STB read for issue addr parity error | |
1313 | input lsu_sbdiou_err_g; // STB read for issue IO/ext ASI parity | |
1314 | input [2:0] lsu_stberr_tid_g; // TID of STB error | |
1315 | input [2:0] lsu_stberr_index_g; // Index of STB error | |
1316 | input [1:0] lsu_stberr_priv_g; // Privilege of STB error | |
1317 | input lsu_stb_flush_g; // STB entry flushed STB (capture priv) | |
1318 | ||
1319 | input cel_tccp; | |
1320 | input cel_tcup; | |
1321 | input [7:0] cel_syndrome; | |
1322 | input [2:0] tlu_tca_tid; | |
1323 | input [1:0] tlu_tca_index; // Index for precise TCA errors | |
1324 | input [7:0] tlu_tsac; // Only one per TG can report tsa[cu] | |
1325 | input [7:0] tlu_tsau; | |
1326 | input asi_tsac; // ASI TSA access errors | |
1327 | input asi_tsau; | |
1328 | input [2:0] asi_tsacu_tid; // Only one per TG can report tsa[cu] | |
1329 | input [7:0] tlu_tccd; | |
1330 | input [7:0] tlu_tcud; | |
1331 | input [1:0] tlu_tca_index_0; | |
1332 | input [1:0] tlu_tca_index_1; | |
1333 | input [10:5] tsd_pc_0_w; | |
1334 | input [10:5] tsd_pc_1_w; | |
1335 | input [7:0] fls_flush; | |
1336 | input [1:0] fls_disrupting_flush_w; | |
1337 | input [1:0] trl_gl0; | |
1338 | input [1:0] trl_gl1; | |
1339 | input [1:0] trl_gl2; | |
1340 | input [1:0] trl_gl3; | |
1341 | input [1:0] trl_gl4; | |
1342 | input [1:0] trl_gl5; | |
1343 | input [1:0] trl_gl6; | |
1344 | input [1:0] trl_gl7; | |
1345 | ||
1346 | input mmu_asi_cecc; // Correctable ECC error on ASI read | |
1347 | input mmu_asi_uecc; // Uncorrectable ECC error on ASI read | |
1348 | input [10:0] mmu_asi_index; // Syndrome and index of the failure | |
1349 | input mmu_asi_mra_not_sca; // 1: MRA error 0: Scratchpad error | |
1350 | input [7:0] mmu_i_l2cerr; | |
1351 | input [7:0] mmu_d_l2cerr; | |
1352 | input [7:0] mmu_i_eccerr; | |
1353 | input [7:0] mmu_d_eccerr; | |
1354 | input [2:0] mmu_thr0_err_type; | |
1355 | input [2:0] mmu_thr1_err_type; | |
1356 | input [2:0] mmu_thr2_err_type; | |
1357 | input [2:0] mmu_thr3_err_type; | |
1358 | input [2:0] mmu_thr4_err_type; | |
1359 | input [2:0] mmu_thr5_err_type; | |
1360 | input [2:0] mmu_thr6_err_type; | |
1361 | input [2:0] mmu_thr7_err_type; | |
1362 | input [2:0] mmu_thr0_err_index; | |
1363 | input [2:0] mmu_thr1_err_index; | |
1364 | input [2:0] mmu_thr2_err_index; | |
1365 | input [2:0] mmu_thr3_err_index; | |
1366 | input [2:0] mmu_thr4_err_index; | |
1367 | input [2:0] mmu_thr5_err_index; | |
1368 | input [2:0] mmu_thr6_err_index; | |
1369 | input [2:0] mmu_thr7_err_index; | |
1370 | ||
1371 | input spu_tlu_mamu_err_req_v; // SPU MAMEM parity error | |
1372 | input [10:0] spu_tlu_mamu_err_req; // SPU MAMEM index | |
1373 | input [2:0] spu_tlu_ma_int_req; // SPU MA 2:0 thread ID | |
1374 | input [2:0] spu_tlu_cwq_int_req; // SPU CWQ 2:0 thread ID | |
1375 | input [5:0] spu_tlu_l2_error; // MAL2[C,U,ND],CWQL2[C,U,ND] | |
1376 | ||
1377 | input cxi_l2_soc_sre; // software_recoverable_error | |
1378 | input [1:0] cxi_l2_soc_err_type; // C=01, UC=10, ND=11 | |
1379 | input [2:0] cxi_l2_soc_tid; | |
1380 | input cxi_l2_err; // L2 error reported | |
1381 | input cxi_soc_err; // SOC error reported | |
1382 | ||
1383 | input asi_rd_isfsr; // ASI read control in ASI cycle 1 | |
1384 | input asi_rd_dsfsr; // but actual read is in ASI cycle 2 | |
1385 | input asi_rd_dsfar; | |
1386 | input asi_rd_desr; | |
1387 | input asi_rd_fesr; | |
1388 | input [2:0] asi_rd_tid; | |
1389 | input [7:0] asi_wr_isfsr; | |
1390 | input [7:0] asi_wr_dsfsr; | |
1391 | input [3:0] asi_wr_data; | |
1392 | ||
1393 | input [7:0] dfd_desr_f; | |
1394 | input [7:0] dfd_desr_s; | |
1395 | input [7:0] dfd_fesr_f; | |
1396 | input [1:0] dfd_fesr_priv_0; | |
1397 | input [1:0] dfd_fesr_priv_1; | |
1398 | input [1:0] dfd_fesr_priv_2; | |
1399 | input [1:0] dfd_fesr_priv_3; | |
1400 | input [1:0] dfd_fesr_priv_4; | |
1401 | input [1:0] dfd_fesr_priv_5; | |
1402 | input [1:0] dfd_fesr_priv_6; | |
1403 | input [1:0] dfd_fesr_priv_7; | |
1404 | ||
1405 | ||
1406 | ||
1407 | output wmr_scan_out; | |
1408 | ||
1409 | output scan_out; | |
1410 | ||
1411 | output [3:0] ras_asi_data; | |
1412 | ||
1413 | // DSFAR | |
1414 | output [19:0] ras_dsfar_0; | |
1415 | output [19:0] ras_dsfar_1; | |
1416 | output [19:0] ras_dsfar_2; | |
1417 | output [19:0] ras_dsfar_3; | |
1418 | output [19:0] ras_dsfar_4; | |
1419 | output [19:0] ras_dsfar_5; | |
1420 | output [19:0] ras_dsfar_6; | |
1421 | output [19:0] ras_dsfar_7; | |
1422 | output [7:0] ras_dsfar_sel_lsu_va; | |
1423 | output [7:0] ras_dsfar_sel_ras; | |
1424 | output [7:0] ras_dsfar_sel_tsa; | |
1425 | output [7:0] ras_rd_dsfar; | |
1426 | ||
1427 | // DESRs | |
1428 | output [61:56] ras_desr_et_0; | |
1429 | output [61:56] ras_desr_et_1; | |
1430 | output [61:56] ras_desr_et_2; | |
1431 | output [61:56] ras_desr_et_3; | |
1432 | output [61:56] ras_desr_et_4; | |
1433 | output [61:56] ras_desr_et_5; | |
1434 | output [61:56] ras_desr_et_6; | |
1435 | output [61:56] ras_desr_et_7; | |
1436 | output [10:0] ras_desr_ea_0; | |
1437 | output [10:0] ras_desr_ea_1; | |
1438 | output [10:0] ras_desr_ea_2; | |
1439 | output [10:0] ras_desr_ea_3; | |
1440 | output [10:0] ras_desr_ea_4; | |
1441 | output [10:0] ras_desr_ea_5; | |
1442 | output [10:0] ras_desr_ea_6; | |
1443 | output [10:0] ras_desr_ea_7; | |
1444 | output ras_desr_me_0; | |
1445 | output ras_desr_me_1; | |
1446 | output ras_desr_me_2; | |
1447 | output ras_desr_me_3; | |
1448 | output ras_desr_me_4; | |
1449 | output ras_desr_me_5; | |
1450 | output ras_desr_me_6; | |
1451 | output ras_desr_me_7; | |
1452 | output [7:0] ras_desr_en; | |
1453 | output [7:0] ras_write_desr_1st; | |
1454 | output [7:0] ras_write_desr_2nd; | |
1455 | output [7:0] ras_rd_desr; | |
1456 | ||
1457 | // FESRs | |
1458 | output [61:60] ras_fesr_et_0; | |
1459 | output [61:60] ras_fesr_et_1; | |
1460 | output [61:60] ras_fesr_et_2; | |
1461 | output [61:60] ras_fesr_et_3; | |
1462 | output [61:60] ras_fesr_et_4; | |
1463 | output [61:60] ras_fesr_et_5; | |
1464 | output [61:60] ras_fesr_et_6; | |
1465 | output [61:60] ras_fesr_et_7; | |
1466 | output [59:55] ras_fesr_ea_0; | |
1467 | output [59:55] ras_fesr_ea_1; | |
1468 | output [59:55] ras_fesr_ea_2; | |
1469 | output [59:55] ras_fesr_ea_3; | |
1470 | output [59:55] ras_fesr_ea_4; | |
1471 | output [59:55] ras_fesr_ea_5; | |
1472 | output [59:55] ras_fesr_ea_6; | |
1473 | output [59:55] ras_fesr_ea_7; | |
1474 | output [7:0] ras_fesr_en; | |
1475 | output [7:0] ras_write_fesr; | |
1476 | output [59:58] ras_fesr_priv; | |
1477 | output [7:0] ras_update_priv; | |
1478 | output [7:0] ras_rd_fesr; | |
1479 | ||
1480 | output [7:0] ras_precise_error; // For debug events | |
1481 | output [7:0] ras_disrupting_error; // For debug events | |
1482 | output [7:0] ras_deferred_error; // For debug events | |
1483 | ||
1484 | ||
1485 | ||
1486 | ||
1487 | ||
1488 | ////////////////////////////////////////////////////////////////////////////// | |
1489 | ||
1490 | assign pce_ov = tcu_pce_ov; | |
1491 | assign stop = 1'b0; | |
1492 | assign siclk = spc_aclk; | |
1493 | assign soclk = spc_bclk; | |
1494 | assign se = tcu_scan_en; | |
1495 | ||
1496 | ||
1497 | ||
1498 | ////////////////////////////////////////////////////////////////////////////// | |
1499 | // Clock header | |
1500 | ||
1501 | tlu_ras_ctl_l1clkhdr_ctl_macro free_clken ( | |
1502 | .l2clk (l2clk ), | |
1503 | .l1en (1'b1 ), | |
1504 | .l1clk (l1clk ), | |
1505 | .pce_ov(pce_ov), | |
1506 | .stop(stop), | |
1507 | .se(se) | |
1508 | ); | |
1509 | ||
1510 | ||
1511 | ||
1512 | ////////////////////////////////////////////////////////////////////////////// | |
1513 | // Power management | |
1514 | ||
1515 | assign l1en_any_b2w = | |
1516 | (| {inst_valid_b[1:0], | |
1517 | lsu_block_store_b[7:0], | |
1518 | w_en, w1_en, ~lsu_tlu_pmen}); | |
1519 | ||
1520 | tlu_ras_ctl_l1clkhdr_ctl_macro b2w_clken ( | |
1521 | .l2clk (l2clk ), | |
1522 | .l1en (l1en_any_b2w ), | |
1523 | .l1clk (l1clk_pm1 ), | |
1524 | .pce_ov(pce_ov), | |
1525 | .stop(stop), | |
1526 | .se(se) | |
1527 | ); | |
1528 | ||
1529 | assign l1en_pm2 = | |
1530 | excp_way_valid | ~lsu_tlu_pmen; | |
1531 | ||
1532 | tlu_ras_ctl_l1clkhdr_ctl_macro exc_way_clken ( | |
1533 | .l2clk (l2clk ), | |
1534 | .l1en (l1en_pm2 ), | |
1535 | .l1clk (l1clk_pm2 ), | |
1536 | .pce_ov(pce_ov), | |
1537 | .stop(stop), | |
1538 | .se(se) | |
1539 | ); | |
1540 | ||
1541 | ||
1542 | ||
1543 | ////////////////////////////////////////////////////////////////////////////// | |
1544 | // | |
1545 | // Pipe TIDs, etc. for in-pipe errors | |
1546 | // | |
1547 | ||
1548 | assign twocycle_inst_m[1:0] = | |
1549 | {2 {lsu_tlu_twocycle_m}} & dec_lsu_inst_m[1:0] & | |
1550 | dec_inst_valid_m[1:0]; | |
1551 | ||
1552 | tlu_ras_ctl_msff_ctl_macro__width_2 twocycle_inst_b_lat ( | |
1553 | .scan_in(twocycle_inst_b_lat_scanin), | |
1554 | .scan_out(twocycle_inst_b_lat_scanout), | |
1555 | .din (twocycle_inst_m [1:0] ), | |
1556 | .dout (ptwocycle_inst_b [1:0] ), | |
1557 | .l1clk(l1clk), | |
1558 | .siclk(siclk), | |
1559 | .soclk(soclk) | |
1560 | ); | |
1561 | ||
1562 | assign twocycle_inst_b[1:0] = | |
1563 | (ptwocycle_inst_b[1:0] | | |
1564 | ({2 {fgu_pdist_beat2_fx1}} & fgu_inst_b[1:0])) & | |
1565 | ~dec_flush_b[1:0] & | |
1566 | ~fls_irf_cecc_b[1:0] & ~fls_irf_uecc_b[1:0]; | |
1567 | ||
1568 | assign inst_valid_m[1:0] = | |
1569 | dec_inst_valid_m[1:0] | twocycle_inst_b[1:0]; | |
1570 | ||
1571 | tlu_ras_ctl_msff_ctl_macro__width_2 inst_valid_b_lat ( | |
1572 | .scan_in(inst_valid_b_lat_scanin), | |
1573 | .scan_out(inst_valid_b_lat_scanout), | |
1574 | .din (inst_valid_m [1:0] ), | |
1575 | .dout (inst_valid_b [1:0] ), | |
1576 | .l1clk(l1clk), | |
1577 | .siclk(siclk), | |
1578 | .soclk(soclk) | |
1579 | ); | |
1580 | ||
1581 | assign w_en_in = | |
1582 | | {inst_valid_b[1:0], lsu_block_store_b[7:0]}; | |
1583 | ||
1584 | tlu_ras_ctl_msff_ctl_macro__width_1 w_en_lat ( | |
1585 | .scan_in(w_en_lat_scanin), | |
1586 | .scan_out(w_en_lat_scanout), | |
1587 | .din (w_en_in ), | |
1588 | .dout (w_en ), | |
1589 | .l1clk(l1clk), | |
1590 | .siclk(siclk), | |
1591 | .soclk(soclk) | |
1592 | ); | |
1593 | ||
1594 | tlu_ras_ctl_msff_ctl_macro__width_1 w1_en_lat ( | |
1595 | .scan_in(w1_en_lat_scanin), | |
1596 | .scan_out(w1_en_lat_scanout), | |
1597 | .din (w_en ), | |
1598 | .dout (w1_en ), | |
1599 | .l1clk(l1clk), | |
1600 | .siclk(siclk), | |
1601 | .soclk(soclk) | |
1602 | ); | |
1603 | ||
1604 | assign flush_b[1:0] = | |
1605 | {(fls_flush[7] & tid_dec_b[7]) | | |
1606 | (fls_flush[6] & tid_dec_b[6]) | | |
1607 | (fls_flush[5] & tid_dec_b[5]) | | |
1608 | (fls_flush[4] & tid_dec_b[4]), | |
1609 | (fls_flush[3] & tid_dec_b[3]) | | |
1610 | (fls_flush[2] & tid_dec_b[2]) | | |
1611 | (fls_flush[1] & tid_dec_b[1]) | | |
1612 | (fls_flush[0] & tid_dec_b[0])}; | |
1613 | ||
1614 | assign inst_valid_w_in[1:0] = | |
1615 | inst_valid_b[1:0] & ~dec_flush_b[1:0] & ~flush_b[1:0]; | |
1616 | ||
1617 | tlu_ras_ctl_msff_ctl_macro__width_2 inst_valid_w_lat ( | |
1618 | .scan_in(inst_valid_w_lat_scanin), | |
1619 | .scan_out(inst_valid_w_lat_scanout), | |
1620 | .l1clk (l1clk_pm1 ), | |
1621 | .din (inst_valid_w_in [1:0] ), | |
1622 | .dout (pre_inst_valid_w [1:0] ), | |
1623 | .siclk(siclk), | |
1624 | .soclk(soclk) | |
1625 | ); | |
1626 | ||
1627 | // block_store_b is not actually in B, so it can't be flushed | |
1628 | assign block_store_w_in[7:0] = | |
1629 | lsu_block_store_b[7:0]; | |
1630 | ||
1631 | tlu_ras_ctl_msff_ctl_macro__width_8 block_store_w_lat ( | |
1632 | .scan_in(block_store_w_lat_scanin), | |
1633 | .scan_out(block_store_w_lat_scanout), | |
1634 | .din (block_store_w_in [7:0] ), | |
1635 | .dout (pblock_store_w [7:0] ), | |
1636 | .l1clk(l1clk), | |
1637 | .siclk(siclk), | |
1638 | .soclk(soclk) | |
1639 | ); | |
1640 | ||
1641 | assign block_store_w[7:0] = | |
1642 | pblock_store_w[7:0] & ~{8 {seen_bsee}}; | |
1643 | ||
1644 | assign inst_valid_w[1:0] = | |
1645 | pre_inst_valid_w[1:0] & ~fls_disrupting_flush_w[1:0]; | |
1646 | ||
1647 | assign tid1_m[1:0] = | |
1648 | (dec_tid1_m[1:0] & {2 {~twocycle_inst_b[1]}}) | | |
1649 | ( tid1_b[1:0] & {2 { twocycle_inst_b[1]}}) ; | |
1650 | ||
1651 | tlu_ras_ctl_msff_ctl_macro__width_2 tid1_b_lat ( | |
1652 | .scan_in(tid1_b_lat_scanin), | |
1653 | .scan_out(tid1_b_lat_scanout), | |
1654 | .din (tid1_m [1:0] ), | |
1655 | .dout (tid1_b [1:0] ), | |
1656 | .l1clk(l1clk), | |
1657 | .siclk(siclk), | |
1658 | .soclk(soclk) | |
1659 | ); | |
1660 | ||
1661 | assign tid0_m[1:0] = | |
1662 | (dec_tid0_m[1:0] & {2 {~twocycle_inst_b[0]}}) | | |
1663 | ( tid0_b[1:0] & {2 { twocycle_inst_b[0]}}) ; | |
1664 | ||
1665 | tlu_ras_ctl_msff_ctl_macro__width_2 tid0_b_lat ( | |
1666 | .scan_in(tid0_b_lat_scanin), | |
1667 | .scan_out(tid0_b_lat_scanout), | |
1668 | .din (tid0_m [1:0] ), | |
1669 | .dout (tid0_b [1:0] ), | |
1670 | .l1clk(l1clk), | |
1671 | .siclk(siclk), | |
1672 | .soclk(soclk) | |
1673 | ); | |
1674 | ||
1675 | assign tid_dec_b[7:0] = | |
1676 | { tid1_b[1] & tid1_b[0], | |
1677 | tid1_b[1] & ~tid1_b[0], | |
1678 | ~tid1_b[1] & tid1_b[0], | |
1679 | ~tid1_b[1] & ~tid1_b[0], | |
1680 | tid0_b[1] & tid0_b[0], | |
1681 | tid0_b[1] & ~tid0_b[0], | |
1682 | ~tid0_b[1] & tid0_b[0], | |
1683 | ~tid0_b[1] & ~tid0_b[0]}; | |
1684 | ||
1685 | tlu_ras_ctl_msff_ctl_macro__width_2 tid1_w_lat ( | |
1686 | .scan_in(tid1_w_lat_scanin), | |
1687 | .scan_out(tid1_w_lat_scanout), | |
1688 | .l1clk (l1clk_pm1 ), | |
1689 | .din (tid1_b [1:0] ), | |
1690 | .dout (tid1_w [1:0] ), | |
1691 | .siclk(siclk), | |
1692 | .soclk(soclk) | |
1693 | ); | |
1694 | ||
1695 | tlu_ras_ctl_msff_ctl_macro__width_2 tid0_w_lat ( | |
1696 | .scan_in(tid0_w_lat_scanin), | |
1697 | .scan_out(tid0_w_lat_scanout), | |
1698 | .l1clk (l1clk_pm1 ), | |
1699 | .din (tid0_b [1:0] ), | |
1700 | .dout (tid0_w [1:0] ), | |
1701 | .siclk(siclk), | |
1702 | .soclk(soclk) | |
1703 | ); | |
1704 | ||
1705 | assign tid_dec_w[7:0] = | |
1706 | { tid1_w[1] & tid1_w[0], | |
1707 | tid1_w[1] & ~tid1_w[0], | |
1708 | ~tid1_w[1] & tid1_w[0], | |
1709 | ~tid1_w[1] & ~tid1_w[0], | |
1710 | tid0_w[1] & tid0_w[0], | |
1711 | tid0_w[1] & ~tid0_w[0], | |
1712 | ~tid0_w[1] & tid0_w[0], | |
1713 | ~tid0_w[1] & ~tid0_w[0]} & | |
1714 | {{4 {inst_valid_w[1]}}, {4 {inst_valid_w[0]}}} | | |
1715 | block_store_w[7:0]; | |
1716 | ||
1717 | assign fgu_inst_m[1:0] = | |
1718 | (dec_fgu_inst_m[1:0] & dec_inst_valid_m[1:0]) | | |
1719 | ( fgu_inst_b[1:0] & twocycle_inst_b[1:0]) ; | |
1720 | ||
1721 | tlu_ras_ctl_msff_ctl_macro__width_2 fgu_inst_b_lat ( | |
1722 | .scan_in(fgu_inst_b_lat_scanin), | |
1723 | .scan_out(fgu_inst_b_lat_scanout), | |
1724 | .din (fgu_inst_m [1:0] ), | |
1725 | .dout (fgu_inst_b [1:0] ), | |
1726 | .l1clk(l1clk), | |
1727 | .siclk(siclk), | |
1728 | .soclk(soclk) | |
1729 | ); | |
1730 | ||
1731 | tlu_ras_ctl_msff_ctl_macro__width_2 fgu_inst_w_lat ( | |
1732 | .scan_in(fgu_inst_w_lat_scanin), | |
1733 | .scan_out(fgu_inst_w_lat_scanout), | |
1734 | .din (fgu_inst_b [1:0] ), | |
1735 | .dout (pfgu_inst_w [1:0] ), | |
1736 | .l1clk(l1clk), | |
1737 | .siclk(siclk), | |
1738 | .soclk(soclk) | |
1739 | ); | |
1740 | ||
1741 | assign fgu_inst_w[1:0] = | |
1742 | pfgu_inst_w[1:0] | {| block_store_w[7:4], | block_store_w[3:0]}; | |
1743 | ||
1744 | // lsu_inst_m doesn't need twocycle stuff because TLB is only accessed once | |
1745 | assign lsu_inst_m[1:0] = | |
1746 | dec_lsu_inst_m[1:0] & dec_inst_valid_m[1:0] ; | |
1747 | ||
1748 | tlu_ras_ctl_msff_ctl_macro__width_2 lsu_inst_b_lat ( | |
1749 | .scan_in(lsu_inst_b_lat_scanin), | |
1750 | .scan_out(lsu_inst_b_lat_scanout), | |
1751 | .din (lsu_inst_m [1:0] ), | |
1752 | .dout (lsu_inst_b [1:0] ), | |
1753 | .l1clk(l1clk), | |
1754 | .siclk(siclk), | |
1755 | .soclk(soclk) | |
1756 | ); | |
1757 | ||
1758 | ||
1759 | ||
1760 | ////////////////////////////////////////////////////////////////////////////// | |
1761 | // | |
1762 | // In-pipe precise errors from M to B | |
1763 | // | |
1764 | ||
1765 | // Instruction cache and TLB errors | |
1766 | // The precise errors for ISFSR are encoded in the exc bits as | |
1767 | // ittp 5'b00111 | |
1768 | // ittm 5'b01001 | |
1769 | // itdp 5'b11111 | |
1770 | // icl2u 5'b01111 | |
1771 | // icl2nd 5'b10000 | |
1772 | // | |
1773 | // but architecturally should be | |
1774 | // ittm 001 1 | |
1775 | // ittp 010 2 | |
1776 | // itdp 011 3 | |
1777 | // icl2u 001 1 | |
1778 | // icl2nd 010 2 | |
1779 | // | |
1780 | // DESR errors from this source are | |
1781 | // icl2c 5'b01110 | |
1782 | // icvp 5'b01010 | |
1783 | // ictp 5'b01011 | |
1784 | // ictm 5'b01100 | |
1785 | // icdp 5'b01101 | |
1786 | // | |
1787 | // but architecturally should be | |
1788 | // icvp 00001 1 | |
1789 | // ictp 00010 2 | |
1790 | // ictm 00011 3 | |
1791 | // icdp 00100 4 | |
1792 | // All these have S = 0 | |
1793 | // icl2c 00010 0 | |
1794 | // This has S = 1 | |
1795 | ||
1796 | assign ittp_m[1:0] = | |
1797 | {dec_exc1_m[4:0] == 5'b00111, | |
1798 | dec_exc0_m[4:0] == 5'b00111} & | |
1799 | dec_inst_valid_m[1:0]; | |
1800 | assign ittm_m[1:0] = | |
1801 | {dec_exc1_m[4:0] == 5'b01001, | |
1802 | dec_exc0_m[4:0] == 5'b01001} & | |
1803 | dec_inst_valid_m[1:0]; | |
1804 | assign itdp_m[1:0] = | |
1805 | {dec_exc1_m[4:0] == 5'b11111, | |
1806 | dec_exc0_m[4:0] == 5'b11111} & | |
1807 | dec_inst_valid_m[1:0]; | |
1808 | assign icl2u_m[1:0] = | |
1809 | {dec_exc1_m[4:0] == 5'b01111 | dec_exc1_m[4:0] == 5'b10111, | |
1810 | dec_exc0_m[4:0] == 5'b01111 | dec_exc0_m[4:0] == 5'b10111} & | |
1811 | dec_inst_valid_m[1:0]; | |
1812 | assign icl2nd_m[1:0] = | |
1813 | {dec_exc1_m[4:0] == 5'b10000 | dec_exc1_m[4:0] == 5'b11000, | |
1814 | dec_exc0_m[4:0] == 5'b10000 | dec_exc0_m[4:0] == 5'b11000} & | |
1815 | dec_inst_valid_m[1:0]; | |
1816 | ||
1817 | assign i_isfsr1_m[2:0] = | |
1818 | ({3 { ittm_m[1]}} & 3'b001) | | |
1819 | ({3 { ittp_m[1]}} & 3'b010) | | |
1820 | ({3 { itdp_m[1]}} & 3'b011) | | |
1821 | ({3 { icl2u_m[1]}} & 3'b001) | | |
1822 | ({3 {icl2nd_m[1]}} & 3'b010) ; | |
1823 | ||
1824 | assign i_isfsr0_m[2:0] = | |
1825 | ({3 { ittm_m[0]}} & 3'b001) | | |
1826 | ({3 { ittp_m[0]}} & 3'b010) | | |
1827 | ({3 { itdp_m[0]}} & 3'b011) | | |
1828 | ({3 { icl2u_m[0]}} & 3'b001) | | |
1829 | ({3 {icl2nd_m[0]}} & 3'b010) ; | |
1830 | ||
1831 | tlu_ras_ctl_msff_ctl_macro__width_3 i_isfsr1_b_lat ( | |
1832 | .scan_in(i_isfsr1_b_lat_scanin), | |
1833 | .scan_out(i_isfsr1_b_lat_scanout), | |
1834 | .din (i_isfsr1_m [2:0] ), | |
1835 | .dout (i_isfsr1_b [2:0] ), | |
1836 | .l1clk(l1clk), | |
1837 | .siclk(siclk), | |
1838 | .soclk(soclk) | |
1839 | ); | |
1840 | ||
1841 | tlu_ras_ctl_msff_ctl_macro__width_3 i_isfsr0_b_lat ( | |
1842 | .scan_in(i_isfsr0_b_lat_scanin), | |
1843 | .scan_out(i_isfsr0_b_lat_scanout), | |
1844 | .din (i_isfsr0_m [2:0] ), | |
1845 | .dout (i_isfsr0_b [2:0] ), | |
1846 | .l1clk(l1clk), | |
1847 | .siclk(siclk), | |
1848 | .soclk(soclk) | |
1849 | ); | |
1850 | ||
1851 | ||
1852 | assign icvp_m[1:0] = | |
1853 | {dec_exc1_m[4:0] == 5'b01010, | |
1854 | dec_exc0_m[4:0] == 5'b01010} & | |
1855 | dec_inst_valid_m[1:0]; | |
1856 | assign ictp_m[1:0] = | |
1857 | {dec_exc1_m[4:0] == 5'b01011, | |
1858 | dec_exc0_m[4:0] == 5'b01011} & | |
1859 | dec_inst_valid_m[1:0]; | |
1860 | assign ictm_m[1:0] = | |
1861 | {dec_exc1_m[4:0] == 5'b01100, | |
1862 | dec_exc0_m[4:0] == 5'b01100} & | |
1863 | dec_inst_valid_m[1:0]; | |
1864 | assign icl2c_m[1:0] = | |
1865 | {dec_exc1_m[4:0] == 5'b01110 | dec_exc1_m[4:0] == 5'b11110, | |
1866 | dec_exc0_m[4:0] == 5'b01110 | dec_exc0_m[4:0] == 5'b11110} & | |
1867 | dec_inst_valid_m[1:0]; | |
1868 | assign icdp_m[1:0] = | |
1869 | dec_icache_perr_m[1:0] & ~icvp_m[1:0] & ~ictp_m[1:0] & | |
1870 | ~ictm_m[1:0] & ~ittp_m[1:0] & ~ittm_m[1:0] & ~itdp_m[1:0] & | |
1871 | ~icl2c_m[1:0] & | |
1872 | ~{( ~dec_exc1_m[2] & dec_exc1_m[1] ) | | |
1873 | ( ~dec_exc1_m[2] & dec_exc1_m[0]) | | |
1874 | (~dec_exc1_m[4] & dec_exc1_m[2] & ~dec_exc1_m[1] & ~dec_exc1_m[0]) , | |
1875 | ( ~dec_exc0_m[2] & dec_exc0_m[1] ) | | |
1876 | ( ~dec_exc0_m[2] & dec_exc0_m[0]) | | |
1877 | (~dec_exc0_m[4] & dec_exc0_m[2] & ~dec_exc0_m[1] & ~dec_exc0_m[0]) } & | |
1878 | dec_inst_valid_m[1:0]; | |
1879 | ||
1880 | assign i_desr1_m[3:0] = | |
1881 | ({4 { icvp_m[1]}} & 4'b0001) | | |
1882 | ({4 { ictp_m[1]}} & 4'b0010) | | |
1883 | ({4 { ictm_m[1]}} & 4'b0011) | | |
1884 | ({4 { icdp_m[1]}} & 4'b0100) | | |
1885 | ({4 { icl2c_m[1]}} & 4'b1010) ; | |
1886 | ||
1887 | assign i_desr0_m[3:0] = | |
1888 | ({4 { icvp_m[0]}} & 4'b0001) | | |
1889 | ({4 { ictp_m[0]}} & 4'b0010) | | |
1890 | ({4 { ictm_m[0]}} & 4'b0011) | | |
1891 | ({4 { icdp_m[0]}} & 4'b0100) | | |
1892 | ({4 { icl2c_m[0]}} & 4'b1010) ; | |
1893 | ||
1894 | tlu_ras_ctl_msff_ctl_macro__width_4 i_desr1_b_lat ( | |
1895 | .scan_in(i_desr1_b_lat_scanin), | |
1896 | .scan_out(i_desr1_b_lat_scanout), | |
1897 | .din (i_desr1_m [3:0] ), | |
1898 | .dout (i_desr1_b [3:0] ), | |
1899 | .l1clk(l1clk), | |
1900 | .siclk(siclk), | |
1901 | .soclk(soclk) | |
1902 | ); | |
1903 | ||
1904 | tlu_ras_ctl_msff_ctl_macro__width_4 i_desr0_b_lat ( | |
1905 | .scan_in(i_desr0_b_lat_scanin), | |
1906 | .scan_out(i_desr0_b_lat_scanout), | |
1907 | .din (i_desr0_m [3:0] ), | |
1908 | .dout (i_desr0_b [3:0] ), | |
1909 | .l1clk(l1clk), | |
1910 | .siclk(siclk), | |
1911 | .soclk(soclk) | |
1912 | ); | |
1913 | ||
1914 | ||
1915 | ||
1916 | // IRF ECC errors | |
1917 | tlu_ras_ctl_msff_ctl_macro__width_5 irf0_ecc_addr_b_lat ( | |
1918 | .scan_in(irf0_ecc_addr_b_lat_scanin), | |
1919 | .scan_out(irf0_ecc_addr_b_lat_scanout), | |
1920 | .din (exu0_ecc_addr_m [4:0] ), | |
1921 | .dout (irf0_ecc_addr_b [4:0] ), | |
1922 | .l1clk(l1clk), | |
1923 | .siclk(siclk), | |
1924 | .soclk(soclk) | |
1925 | ); | |
1926 | ||
1927 | tlu_ras_ctl_msff_ctl_macro__width_5 irf1_ecc_addr_b_lat ( | |
1928 | .scan_in(irf1_ecc_addr_b_lat_scanin), | |
1929 | .scan_out(irf1_ecc_addr_b_lat_scanout), | |
1930 | .din (exu1_ecc_addr_m [4:0] ), | |
1931 | .dout (irf1_ecc_addr_b [4:0] ), | |
1932 | .l1clk(l1clk), | |
1933 | .siclk(siclk), | |
1934 | .soclk(soclk) | |
1935 | ); | |
1936 | ||
1937 | tlu_ras_ctl_msff_ctl_macro__width_8 irf0_ecc_check_b_lat ( | |
1938 | .scan_in(irf0_ecc_check_b_lat_scanin), | |
1939 | .scan_out(irf0_ecc_check_b_lat_scanout), | |
1940 | .din (exu0_ecc_check_m [7:0] ), | |
1941 | .dout (irf0_ecc_check_b [7:0] ), | |
1942 | .l1clk(l1clk), | |
1943 | .siclk(siclk), | |
1944 | .soclk(soclk) | |
1945 | ); | |
1946 | ||
1947 | tlu_ras_ctl_msff_ctl_macro__width_8 irf1_ecc_check_b_lat ( | |
1948 | .scan_in(irf1_ecc_check_b_lat_scanin), | |
1949 | .scan_out(irf1_ecc_check_b_lat_scanout), | |
1950 | .din (exu1_ecc_check_m [7:0] ), | |
1951 | .dout (irf1_ecc_check_b [7:0] ), | |
1952 | .l1clk(l1clk), | |
1953 | .siclk(siclk), | |
1954 | .soclk(soclk) | |
1955 | ); | |
1956 | ||
1957 | ||
1958 | ||
1959 | ////////////////////////////////////////////////////////////////////////////// | |
1960 | // | |
1961 | // Flop in-pipe errors from B to W | |
1962 | // | |
1963 | ||
1964 | tlu_ras_ctl_msff_ctl_macro__width_3 i_isfsr1_w_lat ( | |
1965 | .scan_in(i_isfsr1_w_lat_scanin), | |
1966 | .scan_out(i_isfsr1_w_lat_scanout), | |
1967 | .l1clk (l1clk_pm1 ), | |
1968 | .din (i_isfsr1_b [2:0] ), | |
1969 | .dout (i_isfsr1_w [2:0] ), | |
1970 | .siclk(siclk), | |
1971 | .soclk(soclk) | |
1972 | ); | |
1973 | ||
1974 | tlu_ras_ctl_msff_ctl_macro__width_3 i_isfsr0_w_lat ( | |
1975 | .scan_in(i_isfsr0_w_lat_scanin), | |
1976 | .scan_out(i_isfsr0_w_lat_scanout), | |
1977 | .l1clk (l1clk_pm1 ), | |
1978 | .din (i_isfsr0_b [2:0] ), | |
1979 | .dout (i_isfsr0_w [2:0] ), | |
1980 | .siclk(siclk), | |
1981 | .soclk(soclk) | |
1982 | ); | |
1983 | ||
1984 | tlu_ras_ctl_msff_ctl_macro__width_4 i_desr1_w_lat ( | |
1985 | .scan_in(i_desr1_w_lat_scanin), | |
1986 | .scan_out(i_desr1_w_lat_scanout), | |
1987 | .l1clk (l1clk_pm1 ), | |
1988 | .din (i_desr1_b [3:0] ), | |
1989 | .dout (i_desr1_w [3:0] ), | |
1990 | .siclk(siclk), | |
1991 | .soclk(soclk) | |
1992 | ); | |
1993 | ||
1994 | tlu_ras_ctl_msff_ctl_macro__width_4 i_desr0_w_lat ( | |
1995 | .scan_in(i_desr0_w_lat_scanin), | |
1996 | .scan_out(i_desr0_w_lat_scanout), | |
1997 | .l1clk (l1clk_pm1 ), | |
1998 | .din (i_desr0_b [3:0] ), | |
1999 | .dout (i_desr0_w [3:0] ), | |
2000 | .siclk(siclk), | |
2001 | .soclk(soclk) | |
2002 | ); | |
2003 | ||
2004 | ||
2005 | // | |
2006 | // Encodings for DSFSR errors | |
2007 | // irfu 0001 1 | |
2008 | // irfc 0010 2 | |
2009 | // frfu 0011 3 | |
2010 | // frfc 0100 4 | |
2011 | // dtmh 0001 1 | |
2012 | // dttp 0010 2 | |
2013 | // dtdp 0011 3 | |
2014 | ||
2015 | assign irfu_b[1:0] = | |
2016 | fls_irf_uecc_b[1:0] & inst_valid_b[1:0]; | |
2017 | assign irfc_b[1:0] = | |
2018 | fls_irf_cecc_b[1:0] & inst_valid_b[1:0]; | |
2019 | ||
2020 | assign dtmh_b[1:0] = | |
2021 | ~irfu_b[1:0] & ~irfc_b[1:0] & | |
2022 | {2 {lsu_dtmh_err_b}} & | |
2023 | lsu_inst_b[1:0] & inst_valid_b[1:0]; | |
2024 | assign dttp_b[1:0] = | |
2025 | ~irfu_b[1:0] & ~irfc_b[1:0] & | |
2026 | {2 {~lsu_dtmh_err_b & lsu_dttp_err_b}} & lsu_inst_b[1:0] & | |
2027 | inst_valid_b[1:0]; | |
2028 | assign dtdp_b[1:0] = | |
2029 | ~irfu_b[1:0] & ~irfc_b[1:0] & | |
2030 | {2 {~lsu_dttp_err_b & ~lsu_dtmh_err_b & lsu_dtdp_err_b}} & | |
2031 | lsu_inst_b[1:0] & inst_valid_b[1:0]; | |
2032 | ||
2033 | tlu_ras_ctl_msff_ctl_macro__width_2 irfu_w_lat ( | |
2034 | .scan_in(irfu_w_lat_scanin), | |
2035 | .scan_out(irfu_w_lat_scanout), | |
2036 | .l1clk (l1clk_pm1 ), | |
2037 | .din (irfu_b [1:0] ), | |
2038 | .dout (pirfu_w [1:0] ), | |
2039 | .siclk(siclk), | |
2040 | .soclk(soclk) | |
2041 | ); | |
2042 | ||
2043 | assign irfu_w[1:0] = | |
2044 | pirfu_w[1:0] & ~fls_kill_irf_ecc_w[1:0]; | |
2045 | ||
2046 | tlu_ras_ctl_msff_ctl_macro__width_2 irfc_w_lat ( | |
2047 | .scan_in(irfc_w_lat_scanin), | |
2048 | .scan_out(irfc_w_lat_scanout), | |
2049 | .l1clk (l1clk_pm1 ), | |
2050 | .din (irfc_b [1:0] ), | |
2051 | .dout (pirfc_w [1:0] ), | |
2052 | .siclk(siclk), | |
2053 | .soclk(soclk) | |
2054 | ); | |
2055 | ||
2056 | assign irfc_w[1:0] = | |
2057 | pirfc_w[1:0] & ~fls_kill_irf_ecc_w[1:0]; | |
2058 | ||
2059 | assign pfrfu_w[1:0] = | |
2060 | {2 {fls_f_uecc_w}} & fgu_inst_w[1:0]; | |
2061 | ||
2062 | assign pfrfc_w[1:0] = | |
2063 | {2 {fls_f_cecc_w}} & fgu_inst_w[1:0]; | |
2064 | ||
2065 | assign frfu_w[1:0] = | |
2066 | pfrfu_w[1:0] & | |
2067 | ((inst_valid_w[1:0] & | |
2068 | ~irfu_w[1:0] & ~irfc_w[1:0]) | | |
2069 | {| block_store_w[7:4], | block_store_w[3:0]}); | |
2070 | ||
2071 | assign frfc_w[1:0] = | |
2072 | pfrfc_w[1:0] & | |
2073 | ((inst_valid_w[1:0] & | |
2074 | ~irfu_w[1:0] & ~irfc_w[1:0]) | | |
2075 | {| block_store_w[7:4], | block_store_w[3:0]}); | |
2076 | ||
2077 | ||
2078 | // Only capture first FGU ECC error on block store | |
2079 | assign seen_bsee_in = | |
2080 | (| ((pfrfu_w[1:0] | pfrfc_w[1:0]) & | |
2081 | {| block_store_w[7:4], | block_store_w[3:0]})) | | |
2082 | (seen_bsee & (| pblock_store_w[7:0])); | |
2083 | ||
2084 | tlu_ras_ctl_msff_ctl_macro__width_1 seen_bsee_lat ( | |
2085 | .scan_in(seen_bsee_lat_scanin), | |
2086 | .scan_out(seen_bsee_lat_scanout), | |
2087 | .din (seen_bsee_in ), | |
2088 | .dout (seen_bsee ), | |
2089 | .l1clk(l1clk), | |
2090 | .siclk(siclk), | |
2091 | .soclk(soclk) | |
2092 | ); | |
2093 | ||
2094 | ||
2095 | tlu_ras_ctl_msff_ctl_macro__width_2 dttp_w_lat ( | |
2096 | .scan_in(dttp_w_lat_scanin), | |
2097 | .scan_out(dttp_w_lat_scanout), | |
2098 | .l1clk (l1clk_pm1 ), | |
2099 | .din (dttp_b [1:0] ), | |
2100 | .dout (pdttp_w [1:0] ), | |
2101 | .siclk(siclk), | |
2102 | .soclk(soclk) | |
2103 | ); | |
2104 | ||
2105 | assign dttp_w[1:0] = | |
2106 | pdttp_w[1:0] & ~pfrfc_w[1:0] & ~pfrfu_w[1:0]; | |
2107 | ||
2108 | tlu_ras_ctl_msff_ctl_macro__width_2 dtmh_w_lat ( | |
2109 | .scan_in(dtmh_w_lat_scanin), | |
2110 | .scan_out(dtmh_w_lat_scanout), | |
2111 | .l1clk (l1clk_pm1 ), | |
2112 | .din (dtmh_b [1:0] ), | |
2113 | .dout (pdtmh_w [1:0] ), | |
2114 | .siclk(siclk), | |
2115 | .soclk(soclk) | |
2116 | ); | |
2117 | ||
2118 | assign dtmh_w[1:0] = | |
2119 | pdtmh_w[1:0] & ~pfrfc_w[1:0] & ~pfrfu_w[1:0]; | |
2120 | ||
2121 | tlu_ras_ctl_msff_ctl_macro__width_2 dtdp_w_lat ( | |
2122 | .scan_in(dtdp_w_lat_scanin), | |
2123 | .scan_out(dtdp_w_lat_scanout), | |
2124 | .l1clk (l1clk_pm1 ), | |
2125 | .din (dtdp_b [1:0] ), | |
2126 | .dout (pdtdp_w [1:0] ), | |
2127 | .siclk(siclk), | |
2128 | .soclk(soclk) | |
2129 | ); | |
2130 | ||
2131 | assign dtdp_w[1:0] = | |
2132 | pdtdp_w[1:0] & ~pfrfc_w[1:0] & ~pfrfu_w[1:0]; | |
2133 | ||
2134 | tlu_ras_ctl_msff_ctl_macro__width_5 irf0_ecc_addr_w_lat ( | |
2135 | .scan_in(irf0_ecc_addr_w_lat_scanin), | |
2136 | .scan_out(irf0_ecc_addr_w_lat_scanout), | |
2137 | .l1clk (l1clk_pm1 ), | |
2138 | .din (irf0_ecc_addr_b [4:0] ), | |
2139 | .dout (irf0_ecc_addr_w [4:0] ), | |
2140 | .siclk(siclk), | |
2141 | .soclk(soclk) | |
2142 | ); | |
2143 | ||
2144 | tlu_ras_ctl_msff_ctl_macro__width_5 irf1_ecc_addr_w_lat ( | |
2145 | .scan_in(irf1_ecc_addr_w_lat_scanin), | |
2146 | .scan_out(irf1_ecc_addr_w_lat_scanout), | |
2147 | .l1clk (l1clk_pm1 ), | |
2148 | .din (irf1_ecc_addr_b [4:0] ), | |
2149 | .dout (irf1_ecc_addr_w [4:0] ), | |
2150 | .siclk(siclk), | |
2151 | .soclk(soclk) | |
2152 | ); | |
2153 | ||
2154 | tlu_ras_ctl_msff_ctl_macro__width_8 irf0_ecc_check_w_lat ( | |
2155 | .scan_in(irf0_ecc_check_w_lat_scanin), | |
2156 | .scan_out(irf0_ecc_check_w_lat_scanout), | |
2157 | .l1clk (l1clk_pm1 ), | |
2158 | .din (irf0_ecc_check_b [7:0] ), | |
2159 | .dout (irf0_ecc_check_w [7:0] ), | |
2160 | .siclk(siclk), | |
2161 | .soclk(soclk) | |
2162 | ); | |
2163 | ||
2164 | tlu_ras_ctl_msff_ctl_macro__width_8 irf1_ecc_check_w_lat ( | |
2165 | .scan_in(irf1_ecc_check_w_lat_scanin), | |
2166 | .scan_out(irf1_ecc_check_w_lat_scanout), | |
2167 | .l1clk (l1clk_pm1 ), | |
2168 | .din (irf1_ecc_check_b [7:0] ), | |
2169 | .dout (irf1_ecc_check_w [7:0] ), | |
2170 | .siclk(siclk), | |
2171 | .soclk(soclk) | |
2172 | ); | |
2173 | ||
2174 | tlu_ras_ctl_msff_ctl_macro__width_6 frf_ecc_addr_w_lat ( | |
2175 | .scan_in(frf_ecc_addr_w_lat_scanin), | |
2176 | .scan_out(frf_ecc_addr_w_lat_scanout), | |
2177 | .din (fgu_ecc_addr_fx2 [5:0] ), | |
2178 | .dout (frf_ecc_addr_w [5:0] ), | |
2179 | .l1clk(l1clk), | |
2180 | .siclk(siclk), | |
2181 | .soclk(soclk) | |
2182 | ); | |
2183 | ||
2184 | tlu_ras_ctl_msff_ctl_macro__width_14 frf_ecc_check_w_lat ( | |
2185 | .scan_in(frf_ecc_check_w_lat_scanin), | |
2186 | .scan_out(frf_ecc_check_w_lat_scanout), | |
2187 | .din (fgu_ecc_check_fx2 [13:0] ), | |
2188 | .dout (frf_ecc_check_w [13:0] ), | |
2189 | .l1clk(l1clk), | |
2190 | .siclk(siclk), | |
2191 | .soclk(soclk) | |
2192 | ); | |
2193 | ||
2194 | ||
2195 | ||
2196 | // Decode in-pipe errors at W | |
2197 | ||
2198 | assign pipe_isfsr_7[2:0] = | |
2199 | i_isfsr1_w[2:0] & {3 {tid_dec_w[7]}}; | |
2200 | assign pipe_isfsr_6[2:0] = | |
2201 | i_isfsr1_w[2:0] & {3 {tid_dec_w[6]}}; | |
2202 | assign pipe_isfsr_5[2:0] = | |
2203 | i_isfsr1_w[2:0] & {3 {tid_dec_w[5]}}; | |
2204 | assign pipe_isfsr_4[2:0] = | |
2205 | i_isfsr1_w[2:0] & {3 {tid_dec_w[4]}}; | |
2206 | assign pipe_isfsr_3[2:0] = | |
2207 | i_isfsr0_w[2:0] & {3 {tid_dec_w[3]}}; | |
2208 | assign pipe_isfsr_2[2:0] = | |
2209 | i_isfsr0_w[2:0] & {3 {tid_dec_w[2]}}; | |
2210 | assign pipe_isfsr_1[2:0] = | |
2211 | i_isfsr0_w[2:0] & {3 {tid_dec_w[1]}}; | |
2212 | assign pipe_isfsr_0[2:0] = | |
2213 | i_isfsr0_w[2:0] & {3 {tid_dec_w[0]}}; | |
2214 | ||
2215 | assign pipe_dsfsr1_w[2:0] = | |
2216 | (({3 {irfu_w[1]}} & 3'b001) | | |
2217 | ({3 {irfc_w[1]}} & 3'b010) | | |
2218 | ({3 {frfu_w[1]}} & 3'b011) | | |
2219 | ({3 {frfc_w[1]}} & 3'b100) | | |
2220 | ({3 {dtmh_w[1]}} & 3'b001) | | |
2221 | ({3 {dttp_w[1]}} & 3'b010) | | |
2222 | ({3 {dtdp_w[1]}} & 3'b011) ) & | |
2223 | {3 {fls_ipe_dme_request[1] | (| block_store_w[7:4])}}; | |
2224 | ||
2225 | assign pipe_dsfsr0_w[2:0] = | |
2226 | (({3 {irfu_w[0]}} & 3'b001) | | |
2227 | ({3 {irfc_w[0]}} & 3'b010) | | |
2228 | ({3 {frfu_w[0]}} & 3'b011) | | |
2229 | ({3 {frfc_w[0]}} & 3'b100) | | |
2230 | ({3 {dtmh_w[0]}} & 3'b001) | | |
2231 | ({3 {dttp_w[0]}} & 3'b010) | | |
2232 | ({3 {dtdp_w[0]}} & 3'b011) ) & | |
2233 | {3 {fls_ipe_dme_request[0] | (| block_store_w[3:0])}}; | |
2234 | ||
2235 | assign gl1_w[1:0] = | |
2236 | (trl_gl7[1:0] & {2 {tid_dec_w[7]}}) | | |
2237 | (trl_gl6[1:0] & {2 {tid_dec_w[6]}}) | | |
2238 | (trl_gl5[1:0] & {2 {tid_dec_w[5]}}) | | |
2239 | (trl_gl4[1:0] & {2 {tid_dec_w[4]}}) ; | |
2240 | ||
2241 | assign gl0_w[1:0] = | |
2242 | (trl_gl3[1:0] & {2 {tid_dec_w[3]}}) | | |
2243 | (trl_gl2[1:0] & {2 {tid_dec_w[2]}}) | | |
2244 | (trl_gl1[1:0] & {2 {tid_dec_w[1]}}) | | |
2245 | (trl_gl0[1:0] & {2 {tid_dec_w[0]}}) ; | |
2246 | ||
2247 | assign pipe_dsfar1_w[19:0] = | |
2248 | (({20 {irfu_w[1] | irfc_w[1]}} & | |
2249 | {{5 {1'b0}}, irf1_ecc_check_w[7:0], gl1_w[1:0], | |
2250 | irf1_ecc_addr_w[4:0]}) | | |
2251 | ({20 {frfu_w[1] | frfc_w[1]}} & | |
2252 | {frf_ecc_check_w[13:0], frf_ecc_addr_w[5:0]})) & | |
2253 | {20 {(| tid_dec_w[7:4]) & | |
2254 | (fls_ipe_dme_request[1] | (| block_store_w[7:4]))}}; | |
2255 | ||
2256 | assign pipe_dsfar0_w[19:0] = | |
2257 | (({20 {irfu_w[0] | irfc_w[0]}} & | |
2258 | {{5 {1'b0}}, irf0_ecc_check_w[7:0], gl0_w[1:0], | |
2259 | irf0_ecc_addr_w[4:0]}) | | |
2260 | ({20 {frfu_w[0] | frfc_w[0]}} & | |
2261 | {frf_ecc_check_w[13:0], frf_ecc_addr_w[5:0]})) & | |
2262 | {20 {(| tid_dec_w[3:0]) & | |
2263 | (fls_ipe_dme_request[0] | (| block_store_w[3:0]))}}; | |
2264 | ||
2265 | // Carry pipe DSFSR errors out one more cycle so they only update DSFSR/DSFAR | |
2266 | // if they are the highest priority exceptions | |
2267 | ||
2268 | assign ecc_w[1:0] = | |
2269 | irfu_w[1:0] | irfc_w[1:0] | frfu_w[1:0] | frfc_w[1:0]; | |
2270 | ||
2271 | tlu_ras_ctl_msff_ctl_macro__width_2 ecc_w1_lat ( | |
2272 | .scan_in(ecc_w1_lat_scanin), | |
2273 | .scan_out(ecc_w1_lat_scanout), | |
2274 | .din (ecc_w [1:0] ), | |
2275 | .dout (ecc_w1 [1:0] ), | |
2276 | .l1clk(l1clk), | |
2277 | .siclk(siclk), | |
2278 | .soclk(soclk) | |
2279 | ); | |
2280 | ||
2281 | assign tid1_w1_in[1:0] = | |
2282 | (tid1_w[1:0] & ~{2 {| block_store_w[7:4]}}) | | |
2283 | {block_store_w[7] | block_store_w[6], | |
2284 | block_store_w[7] | block_store_w[5]}; | |
2285 | ||
2286 | tlu_ras_ctl_msff_ctl_macro__width_2 tid1_w1_lat ( | |
2287 | .scan_in(tid1_w1_lat_scanin), | |
2288 | .scan_out(tid1_w1_lat_scanout), | |
2289 | .l1clk (l1clk_pm1 ), | |
2290 | .din (tid1_w1_in [1:0] ), | |
2291 | .dout (tid1_w1 [1:0] ), | |
2292 | .siclk(siclk), | |
2293 | .soclk(soclk) | |
2294 | ); | |
2295 | ||
2296 | assign tid0_w1_in[1:0] = | |
2297 | (tid0_w[1:0] & ~{2 {| block_store_w[3:0]}}) | | |
2298 | {block_store_w[3] | block_store_w[2], | |
2299 | block_store_w[3] | block_store_w[1]}; | |
2300 | ||
2301 | tlu_ras_ctl_msff_ctl_macro__width_2 tid0_w1_lat ( | |
2302 | .scan_in(tid0_w1_lat_scanin), | |
2303 | .scan_out(tid0_w1_lat_scanout), | |
2304 | .l1clk (l1clk_pm1 ), | |
2305 | .din (tid0_w1_in [1:0] ), | |
2306 | .dout (tid0_w1 [1:0] ), | |
2307 | .siclk(siclk), | |
2308 | .soclk(soclk) | |
2309 | ); | |
2310 | ||
2311 | tlu_ras_ctl_msff_ctl_macro__width_3 pipe_dsfsr1_lat ( | |
2312 | .scan_in(pipe_dsfsr1_lat_scanin), | |
2313 | .scan_out(pipe_dsfsr1_lat_scanout), | |
2314 | .din (pipe_dsfsr1_w [2:0] ), | |
2315 | .dout (pipe_dsfsr1 [2:0] ), | |
2316 | .l1clk(l1clk), | |
2317 | .siclk(siclk), | |
2318 | .soclk(soclk) | |
2319 | ); | |
2320 | ||
2321 | tlu_ras_ctl_msff_ctl_macro__width_3 pipe_dsfsr0_lat ( | |
2322 | .scan_in(pipe_dsfsr0_lat_scanin), | |
2323 | .scan_out(pipe_dsfsr0_lat_scanout), | |
2324 | .din (pipe_dsfsr0_w [2:0] ), | |
2325 | .dout (pipe_dsfsr0 [2:0] ), | |
2326 | .l1clk(l1clk), | |
2327 | .siclk(siclk), | |
2328 | .soclk(soclk) | |
2329 | ); | |
2330 | ||
2331 | tlu_ras_ctl_msff_ctl_macro__width_20 pipe_dsfar1_lat ( | |
2332 | .scan_in(pipe_dsfar1_lat_scanin), | |
2333 | .scan_out(pipe_dsfar1_lat_scanout), | |
2334 | .din (pipe_dsfar1_w [19:0] ), | |
2335 | .dout (pipe_dsfar1 [19:0] ), | |
2336 | .l1clk(l1clk), | |
2337 | .siclk(siclk), | |
2338 | .soclk(soclk) | |
2339 | ); | |
2340 | ||
2341 | tlu_ras_ctl_msff_ctl_macro__width_20 pipe_dsfar0_lat ( | |
2342 | .scan_in(pipe_dsfar0_lat_scanin), | |
2343 | .scan_out(pipe_dsfar0_lat_scanout), | |
2344 | .din (pipe_dsfar0_w [19:0] ), | |
2345 | .dout (pipe_dsfar0 [19:0] ), | |
2346 | .l1clk(l1clk), | |
2347 | .siclk(siclk), | |
2348 | .soclk(soclk) | |
2349 | ); | |
2350 | ||
2351 | assign tid_dec_w1[7:0] = | |
2352 | { tid1_w1[1] & tid1_w1[0], | |
2353 | tid1_w1[1] & ~tid1_w1[0], | |
2354 | ~tid1_w1[1] & tid1_w1[0], | |
2355 | ~tid1_w1[1] & ~tid1_w1[0], | |
2356 | tid0_w1[1] & tid0_w1[0], | |
2357 | tid0_w1[1] & ~tid0_w1[0], | |
2358 | ~tid0_w1[1] & tid0_w1[0], | |
2359 | ~tid0_w1[1] & ~tid0_w1[0]}; | |
2360 | ||
2361 | ||
2362 | ||
2363 | assign pipe_dsfsr_7[2:0] = | |
2364 | pipe_dsfsr1[2:0] & {3 {tid_dec_w1[7]}}; | |
2365 | assign pipe_dsfsr_6[2:0] = | |
2366 | pipe_dsfsr1[2:0] & {3 {tid_dec_w1[6]}}; | |
2367 | assign pipe_dsfsr_5[2:0] = | |
2368 | pipe_dsfsr1[2:0] & {3 {tid_dec_w1[5]}}; | |
2369 | assign pipe_dsfsr_4[2:0] = | |
2370 | pipe_dsfsr1[2:0] & {3 {tid_dec_w1[4]}}; | |
2371 | assign pipe_dsfsr_3[2:0] = | |
2372 | pipe_dsfsr0[2:0] & {3 {tid_dec_w1[3]}}; | |
2373 | assign pipe_dsfsr_2[2:0] = | |
2374 | pipe_dsfsr0[2:0] & {3 {tid_dec_w1[2]}}; | |
2375 | assign pipe_dsfsr_1[2:0] = | |
2376 | pipe_dsfsr0[2:0] & {3 {tid_dec_w1[1]}}; | |
2377 | assign pipe_dsfsr_0[2:0] = | |
2378 | pipe_dsfsr0[2:0] & {3 {tid_dec_w1[0]}}; | |
2379 | ||
2380 | assign pipe_dsfar_7[19:0] = | |
2381 | {20 {ecc_w1[1] & tid_dec_w1[7]}} & pipe_dsfar1[19:0]; | |
2382 | assign pipe_dsfar_6[19:0] = | |
2383 | {20 {ecc_w1[1] & tid_dec_w1[6]}} & pipe_dsfar1[19:0]; | |
2384 | assign pipe_dsfar_5[19:0] = | |
2385 | {20 {ecc_w1[1] & tid_dec_w1[5]}} & pipe_dsfar1[19:0]; | |
2386 | assign pipe_dsfar_4[19:0] = | |
2387 | {20 {ecc_w1[1] & tid_dec_w1[4]}} & pipe_dsfar1[19:0]; | |
2388 | assign pipe_dsfar_3[19:0] = | |
2389 | {20 {ecc_w1[0] & tid_dec_w1[3]}} & pipe_dsfar0[19:0]; | |
2390 | assign pipe_dsfar_2[19:0] = | |
2391 | {20 {ecc_w1[0] & tid_dec_w1[2]}} & pipe_dsfar0[19:0]; | |
2392 | assign pipe_dsfar_1[19:0] = | |
2393 | {20 {ecc_w1[0] & tid_dec_w1[1]}} & pipe_dsfar0[19:0]; | |
2394 | assign pipe_dsfar_0[19:0] = | |
2395 | {20 {ecc_w1[0] & tid_dec_w1[0]}} & pipe_dsfar0[19:0]; | |
2396 | ||
2397 | assign dsfar_sel_lsu_va_for_error[7:0] = | |
2398 | ({{4 {~ecc_w1[1] & (| pipe_dsfsr1[2:0])}}, | |
2399 | {4 {~ecc_w1[0] & (| pipe_dsfsr0[2:0])}}} & tid_dec_w1[7:0]) ; | |
2400 | ||
2401 | tlu_ras_ctl_msff_ctl_macro__width_8 load_dsfar_lat ( | |
2402 | .scan_in(load_dsfar_lat_scanin), | |
2403 | .scan_out(load_dsfar_lat_scanout), | |
2404 | .din (fls_load_dsfar [7:0] ), | |
2405 | .dout (load_dsfar [7:0] ), | |
2406 | .l1clk(l1clk), | |
2407 | .siclk(siclk), | |
2408 | .soclk(soclk) | |
2409 | ); | |
2410 | ||
2411 | assign ras_dsfar_sel_lsu_va[7:0] = | |
2412 | dsfar_sel_lsu_va_for_error[7:0] | | |
2413 | load_dsfar[7:0]; | |
2414 | ||
2415 | // Update DESR in W1 | |
2416 | ||
2417 | assign i_desr1_w1_in[3:0] = | |
2418 | i_desr1_w[3:0] & {4 {| tid_dec_w[7:4]}}; | |
2419 | ||
2420 | assign i_desr0_w1_in[3:0] = | |
2421 | i_desr0_w[3:0] & {4 {| tid_dec_w[3:0]}}; | |
2422 | ||
2423 | tlu_ras_ctl_msff_ctl_macro__width_4 i_desr1_w1_lat ( | |
2424 | .scan_in(i_desr1_w1_lat_scanin), | |
2425 | .scan_out(i_desr1_w1_lat_scanout), | |
2426 | .l1clk (l1clk_pm1 ), | |
2427 | .din (i_desr1_w1_in [3:0] ), | |
2428 | .dout (i_desr1_w1 [3:0] ), | |
2429 | .siclk(siclk), | |
2430 | .soclk(soclk) | |
2431 | ); | |
2432 | ||
2433 | tlu_ras_ctl_msff_ctl_macro__width_4 i_desr0_w1_lat ( | |
2434 | .scan_in(i_desr0_w1_lat_scanin), | |
2435 | .scan_out(i_desr0_w1_lat_scanout), | |
2436 | .l1clk (l1clk_pm1 ), | |
2437 | .din (i_desr0_w1_in [3:0] ), | |
2438 | .dout (i_desr0_w1 [3:0] ), | |
2439 | .siclk(siclk), | |
2440 | .soclk(soclk) | |
2441 | ); | |
2442 | ||
2443 | assign pipe_desr_et_7[5:0] = | |
2444 | {i_desr1_w1[3], 2'b00, i_desr1_w1[2:0]} & {6 {tid_dec_w1[7]}}; | |
2445 | assign pipe_desr_et_6[5:0] = | |
2446 | {i_desr1_w1[3], 2'b00, i_desr1_w1[2:0]} & {6 {tid_dec_w1[6]}}; | |
2447 | assign pipe_desr_et_5[5:0] = | |
2448 | {i_desr1_w1[3], 2'b00, i_desr1_w1[2:0]} & {6 {tid_dec_w1[5]}}; | |
2449 | assign pipe_desr_et_4[5:0] = | |
2450 | {i_desr1_w1[3], 2'b00, i_desr1_w1[2:0]} & {6 {tid_dec_w1[4]}}; | |
2451 | assign pipe_desr_et_3[5:0] = | |
2452 | {i_desr0_w1[3], 2'b00, i_desr0_w1[2:0]} & {6 {tid_dec_w1[3]}}; | |
2453 | assign pipe_desr_et_2[5:0] = | |
2454 | {i_desr0_w1[3], 2'b00, i_desr0_w1[2:0]} & {6 {tid_dec_w1[2]}}; | |
2455 | assign pipe_desr_et_1[5:0] = | |
2456 | {i_desr0_w1[3], 2'b00, i_desr0_w1[2:0]} & {6 {tid_dec_w1[1]}}; | |
2457 | assign pipe_desr_et_0[5:0] = | |
2458 | {i_desr0_w1[3], 2'b00, i_desr0_w1[2:0]} & {6 {tid_dec_w1[0]}}; | |
2459 | ||
2460 | ||
2461 | // Hold exception way | |
2462 | tlu_ras_ctl_msff_ctl_macro__width_7 excp_way_lat ( | |
2463 | .scan_in(excp_way_lat_scanin), | |
2464 | .scan_out(excp_way_lat_scanout), | |
2465 | .din ({ftu_excp_tid_d [2:0], | |
2466 | ftu_excp_way_d [2:0], | |
2467 | ftu_excp_way_valid_d }), | |
2468 | .dout ({excp_tid [2:0], | |
2469 | excp_way [2:0], | |
2470 | excp_way_valid }), | |
2471 | .l1clk(l1clk), | |
2472 | .siclk(siclk), | |
2473 | .soclk(soclk) | |
2474 | ); | |
2475 | ||
2476 | assign sel_ftu_excp_way[7:0] = | |
2477 | {(excp_tid[2:0] == 3'b111) & excp_way_valid, | |
2478 | (excp_tid[2:0] == 3'b110) & excp_way_valid, | |
2479 | (excp_tid[2:0] == 3'b101) & excp_way_valid, | |
2480 | (excp_tid[2:0] == 3'b100) & excp_way_valid, | |
2481 | (excp_tid[2:0] == 3'b011) & excp_way_valid, | |
2482 | (excp_tid[2:0] == 3'b010) & excp_way_valid, | |
2483 | (excp_tid[2:0] == 3'b001) & excp_way_valid, | |
2484 | (excp_tid[2:0] == 3'b000) & excp_way_valid}; | |
2485 | ||
2486 | assign ic_way7_in[2:0] = | |
2487 | (excp_way[2:0] & {3 { sel_ftu_excp_way[7]}}) | | |
2488 | (ic_way7 [2:0] & {3 {~sel_ftu_excp_way[7]}}) ; | |
2489 | ||
2490 | assign ic_way6_in[2:0] = | |
2491 | (excp_way[2:0] & {3 { sel_ftu_excp_way[6]}}) | | |
2492 | (ic_way6 [2:0] & {3 {~sel_ftu_excp_way[6]}}) ; | |
2493 | ||
2494 | assign ic_way5_in[2:0] = | |
2495 | (excp_way[2:0] & {3 { sel_ftu_excp_way[5]}}) | | |
2496 | (ic_way5 [2:0] & {3 {~sel_ftu_excp_way[5]}}) ; | |
2497 | ||
2498 | assign ic_way4_in[2:0] = | |
2499 | (excp_way[2:0] & {3 { sel_ftu_excp_way[4]}}) | | |
2500 | (ic_way4 [2:0] & {3 {~sel_ftu_excp_way[4]}}) ; | |
2501 | ||
2502 | assign ic_way3_in[2:0] = | |
2503 | (excp_way[2:0] & {3 { sel_ftu_excp_way[3]}}) | | |
2504 | (ic_way3 [2:0] & {3 {~sel_ftu_excp_way[3]}}) ; | |
2505 | ||
2506 | assign ic_way2_in[2:0] = | |
2507 | (excp_way[2:0] & {3 { sel_ftu_excp_way[2]}}) | | |
2508 | (ic_way2 [2:0] & {3 {~sel_ftu_excp_way[2]}}) ; | |
2509 | ||
2510 | assign ic_way1_in[2:0] = | |
2511 | (excp_way[2:0] & {3 { sel_ftu_excp_way[1]}}) | | |
2512 | (ic_way1 [2:0] & {3 {~sel_ftu_excp_way[1]}}) ; | |
2513 | ||
2514 | assign ic_way0_in[2:0] = | |
2515 | (excp_way[2:0] & {3 { sel_ftu_excp_way[0]}}) | | |
2516 | (ic_way0 [2:0] & {3 {~sel_ftu_excp_way[0]}}) ; | |
2517 | ||
2518 | tlu_ras_ctl_msff_ctl_macro__width_3 ic_way7_lat ( | |
2519 | .scan_in(ic_way7_lat_scanin), | |
2520 | .scan_out(ic_way7_lat_scanout), | |
2521 | .l1clk (l1clk_pm2 ), | |
2522 | .din (ic_way7_in [2:0] ), | |
2523 | .dout (ic_way7 [2:0] ), | |
2524 | .siclk(siclk), | |
2525 | .soclk(soclk) | |
2526 | ); | |
2527 | ||
2528 | tlu_ras_ctl_msff_ctl_macro__width_3 ic_way6_lat ( | |
2529 | .scan_in(ic_way6_lat_scanin), | |
2530 | .scan_out(ic_way6_lat_scanout), | |
2531 | .l1clk (l1clk_pm2 ), | |
2532 | .din (ic_way6_in [2:0] ), | |
2533 | .dout (ic_way6 [2:0] ), | |
2534 | .siclk(siclk), | |
2535 | .soclk(soclk) | |
2536 | ); | |
2537 | ||
2538 | tlu_ras_ctl_msff_ctl_macro__width_3 ic_way5_lat ( | |
2539 | .scan_in(ic_way5_lat_scanin), | |
2540 | .scan_out(ic_way5_lat_scanout), | |
2541 | .l1clk (l1clk_pm2 ), | |
2542 | .din (ic_way5_in [2:0] ), | |
2543 | .dout (ic_way5 [2:0] ), | |
2544 | .siclk(siclk), | |
2545 | .soclk(soclk) | |
2546 | ); | |
2547 | ||
2548 | tlu_ras_ctl_msff_ctl_macro__width_3 ic_way4_lat ( | |
2549 | .scan_in(ic_way4_lat_scanin), | |
2550 | .scan_out(ic_way4_lat_scanout), | |
2551 | .l1clk (l1clk_pm2 ), | |
2552 | .din (ic_way4_in [2:0] ), | |
2553 | .dout (ic_way4 [2:0] ), | |
2554 | .siclk(siclk), | |
2555 | .soclk(soclk) | |
2556 | ); | |
2557 | ||
2558 | tlu_ras_ctl_msff_ctl_macro__width_3 ic_way3_lat ( | |
2559 | .scan_in(ic_way3_lat_scanin), | |
2560 | .scan_out(ic_way3_lat_scanout), | |
2561 | .l1clk (l1clk_pm2 ), | |
2562 | .din (ic_way3_in [2:0] ), | |
2563 | .dout (ic_way3 [2:0] ), | |
2564 | .siclk(siclk), | |
2565 | .soclk(soclk) | |
2566 | ); | |
2567 | ||
2568 | tlu_ras_ctl_msff_ctl_macro__width_3 ic_way2_lat ( | |
2569 | .scan_in(ic_way2_lat_scanin), | |
2570 | .scan_out(ic_way2_lat_scanout), | |
2571 | .l1clk (l1clk_pm2 ), | |
2572 | .din (ic_way2_in [2:0] ), | |
2573 | .dout (ic_way2 [2:0] ), | |
2574 | .siclk(siclk), | |
2575 | .soclk(soclk) | |
2576 | ); | |
2577 | ||
2578 | tlu_ras_ctl_msff_ctl_macro__width_3 ic_way1_lat ( | |
2579 | .scan_in(ic_way1_lat_scanin), | |
2580 | .scan_out(ic_way1_lat_scanout), | |
2581 | .l1clk (l1clk_pm2 ), | |
2582 | .din (ic_way1_in [2:0] ), | |
2583 | .dout (ic_way1 [2:0] ), | |
2584 | .siclk(siclk), | |
2585 | .soclk(soclk) | |
2586 | ); | |
2587 | ||
2588 | tlu_ras_ctl_msff_ctl_macro__width_3 ic_way0_lat ( | |
2589 | .scan_in(ic_way0_lat_scanin), | |
2590 | .scan_out(ic_way0_lat_scanout), | |
2591 | .l1clk (l1clk_pm2 ), | |
2592 | .din (ic_way0_in [2:0] ), | |
2593 | .dout (ic_way0 [2:0] ), | |
2594 | .siclk(siclk), | |
2595 | .soclk(soclk) | |
2596 | ); | |
2597 | ||
2598 | // Hold pipe DESR address to W1 | |
2599 | tlu_ras_ctl_msff_ctl_macro__width_6 pc_1_w1_lat ( | |
2600 | .scan_in(pc_1_w1_lat_scanin), | |
2601 | .scan_out(pc_1_w1_lat_scanout), | |
2602 | .l1clk (l1clk_pm1 ), | |
2603 | .din (tsd_pc_1_w [10:5] ), | |
2604 | .dout (pc_1_w1 [10:5] ), | |
2605 | .siclk(siclk), | |
2606 | .soclk(soclk) | |
2607 | ); | |
2608 | ||
2609 | tlu_ras_ctl_msff_ctl_macro__width_6 pc_0_w1_lat ( | |
2610 | .scan_in(pc_0_w1_lat_scanin), | |
2611 | .scan_out(pc_0_w1_lat_scanout), | |
2612 | .l1clk (l1clk_pm1 ), | |
2613 | .din (tsd_pc_0_w [10:5] ), | |
2614 | .dout (pc_0_w1 [10:5] ), | |
2615 | .siclk(siclk), | |
2616 | .soclk(soclk) | |
2617 | ); | |
2618 | ||
2619 | ||
2620 | // Force ea to zero for icl2c | |
2621 | assign pipe_desr_ea_7[8:0] = | |
2622 | {ic_way7[2:0], pc_1_w1[10:5]} & | |
2623 | {9 {(| pipe_desr_et_7[2:0]) & ~pipe_desr_et_7[5]}}; | |
2624 | assign pipe_desr_ea_6[8:0] = | |
2625 | {ic_way6[2:0], pc_1_w1[10:5]} & | |
2626 | {9 {(| pipe_desr_et_6[2:0]) & ~pipe_desr_et_6[5]}}; | |
2627 | assign pipe_desr_ea_5[8:0] = | |
2628 | {ic_way5[2:0], pc_1_w1[10:5]} & | |
2629 | {9 {(| pipe_desr_et_5[2:0]) & ~pipe_desr_et_5[5]}}; | |
2630 | assign pipe_desr_ea_4[8:0] = | |
2631 | {ic_way4[2:0], pc_1_w1[10:5]} & | |
2632 | {9 {(| pipe_desr_et_4[2:0]) & ~pipe_desr_et_4[5]}}; | |
2633 | assign pipe_desr_ea_3[8:0] = | |
2634 | {ic_way3[2:0], pc_0_w1[10:5]} & | |
2635 | {9 {(| pipe_desr_et_3[2:0]) & ~pipe_desr_et_3[5]}}; | |
2636 | assign pipe_desr_ea_2[8:0] = | |
2637 | {ic_way2[2:0], pc_0_w1[10:5]} & | |
2638 | {9 {(| pipe_desr_et_2[2:0]) & ~pipe_desr_et_2[5]}}; | |
2639 | assign pipe_desr_ea_1[8:0] = | |
2640 | {ic_way1[2:0], pc_0_w1[10:5]} & | |
2641 | {9 {(| pipe_desr_et_1[2:0]) & ~pipe_desr_et_1[5]}}; | |
2642 | assign pipe_desr_ea_0[8:0] = | |
2643 | {ic_way0[2:0], pc_0_w1[10:5]} & | |
2644 | {9 {(| pipe_desr_et_0[2:0]) & ~pipe_desr_et_0[5]}}; | |
2645 | ||
2646 | ||
2647 | ||
2648 | ////////////////////////////////////////////////////////////////////////////// | |
2649 | // | |
2650 | // Handle out-of-pipe errors (flop, decode, and record) | |
2651 | // | |
2652 | ||
2653 | // | |
2654 | // Incoming encoding | |
2655 | // i/dtmu 101 | |
2656 | // i/dtl2c 001 | |
2657 | // i/dtl2u 010 | |
2658 | // i/dtl2nd 011 | |
2659 | // | |
2660 | // ISFSR encodings | |
2661 | // itmu 100 | |
2662 | // itl2u 101 | |
2663 | // itl2nd 110 | |
2664 | // | |
2665 | // DSFSR encodings | |
2666 | // dtmu 100 | |
2667 | // dtl2u 101 | |
2668 | // dtl2nd 110 | |
2669 | // | |
2670 | // DESR encodings | |
2671 | // itl2c 001 | |
2672 | // dtl2c 011 | |
2673 | // Both have S = 1 | |
2674 | ||
2675 | assign itmu_7 = mmu_i_eccerr[7] & (mmu_thr7_err_type[2 ] == 1'b1 ); | |
2676 | assign itmu_6 = mmu_i_eccerr[6] & (mmu_thr6_err_type[2 ] == 1'b1 ); | |
2677 | assign itmu_5 = mmu_i_eccerr[5] & (mmu_thr5_err_type[2 ] == 1'b1 ); | |
2678 | assign itmu_4 = mmu_i_eccerr[4] & (mmu_thr4_err_type[2 ] == 1'b1 ); | |
2679 | assign itmu_3 = mmu_i_eccerr[3] & (mmu_thr3_err_type[2 ] == 1'b1 ); | |
2680 | assign itmu_2 = mmu_i_eccerr[2] & (mmu_thr2_err_type[2 ] == 1'b1 ); | |
2681 | assign itmu_1 = mmu_i_eccerr[1] & (mmu_thr1_err_type[2 ] == 1'b1 ); | |
2682 | assign itmu_0 = mmu_i_eccerr[0] & (mmu_thr0_err_type[2 ] == 1'b1 ); | |
2683 | ||
2684 | assign itl2u_7 = mmu_i_eccerr[7] & (mmu_thr7_err_type[2:0] == 3'b010 ); | |
2685 | assign itl2u_6 = mmu_i_eccerr[6] & (mmu_thr6_err_type[2:0] == 3'b010 ); | |
2686 | assign itl2u_5 = mmu_i_eccerr[5] & (mmu_thr5_err_type[2:0] == 3'b010 ); | |
2687 | assign itl2u_4 = mmu_i_eccerr[4] & (mmu_thr4_err_type[2:0] == 3'b010 ); | |
2688 | assign itl2u_3 = mmu_i_eccerr[3] & (mmu_thr3_err_type[2:0] == 3'b010 ); | |
2689 | assign itl2u_2 = mmu_i_eccerr[2] & (mmu_thr2_err_type[2:0] == 3'b010 ); | |
2690 | assign itl2u_1 = mmu_i_eccerr[1] & (mmu_thr1_err_type[2:0] == 3'b010 ); | |
2691 | assign itl2u_0 = mmu_i_eccerr[0] & (mmu_thr0_err_type[2:0] == 3'b010 ); | |
2692 | ||
2693 | assign itl2nd_7 = mmu_i_eccerr[7] & (mmu_thr7_err_type[2:0] == 3'b011 ); | |
2694 | assign itl2nd_6 = mmu_i_eccerr[6] & (mmu_thr6_err_type[2:0] == 3'b011 ); | |
2695 | assign itl2nd_5 = mmu_i_eccerr[5] & (mmu_thr5_err_type[2:0] == 3'b011 ); | |
2696 | assign itl2nd_4 = mmu_i_eccerr[4] & (mmu_thr4_err_type[2:0] == 3'b011 ); | |
2697 | assign itl2nd_3 = mmu_i_eccerr[3] & (mmu_thr3_err_type[2:0] == 3'b011 ); | |
2698 | assign itl2nd_2 = mmu_i_eccerr[2] & (mmu_thr2_err_type[2:0] == 3'b011 ); | |
2699 | assign itl2nd_1 = mmu_i_eccerr[1] & (mmu_thr1_err_type[2:0] == 3'b011 ); | |
2700 | assign itl2nd_0 = mmu_i_eccerr[0] & (mmu_thr0_err_type[2:0] == 3'b011 ); | |
2701 | ||
2702 | ||
2703 | assign m_isfsr_7[2:0] = | |
2704 | ({3 { itmu_7}} & 3'b100) | | |
2705 | ({3 { itl2u_7}} & 3'b101) | | |
2706 | ({3 {itl2nd_7}} & 3'b110) ; | |
2707 | assign m_isfsr_6[2:0] = | |
2708 | ({3 { itmu_6}} & 3'b100) | | |
2709 | ({3 { itl2u_6}} & 3'b101) | | |
2710 | ({3 {itl2nd_6}} & 3'b110) ; | |
2711 | assign m_isfsr_5[2:0] = | |
2712 | ({3 { itmu_5}} & 3'b100) | | |
2713 | ({3 { itl2u_5}} & 3'b101) | | |
2714 | ({3 {itl2nd_5}} & 3'b110) ; | |
2715 | assign m_isfsr_4[2:0] = | |
2716 | ({3 { itmu_4}} & 3'b100) | | |
2717 | ({3 { itl2u_4}} & 3'b101) | | |
2718 | ({3 {itl2nd_4}} & 3'b110) ; | |
2719 | assign m_isfsr_3[2:0] = | |
2720 | ({3 { itmu_3}} & 3'b100) | | |
2721 | ({3 { itl2u_3}} & 3'b101) | | |
2722 | ({3 {itl2nd_3}} & 3'b110) ; | |
2723 | assign m_isfsr_2[2:0] = | |
2724 | ({3 { itmu_2}} & 3'b100) | | |
2725 | ({3 { itl2u_2}} & 3'b101) | | |
2726 | ({3 {itl2nd_2}} & 3'b110) ; | |
2727 | assign m_isfsr_1[2:0] = | |
2728 | ({3 { itmu_1}} & 3'b100) | | |
2729 | ({3 { itl2u_1}} & 3'b101) | | |
2730 | ({3 {itl2nd_1}} & 3'b110) ; | |
2731 | assign m_isfsr_0[2:0] = | |
2732 | ({3 { itmu_0}} & 3'b100) | | |
2733 | ({3 { itl2u_0}} & 3'b101) | | |
2734 | ({3 {itl2nd_0}} & 3'b110) ; | |
2735 | ||
2736 | ||
2737 | assign dtmu_7 = mmu_d_eccerr[7] & (mmu_thr7_err_type[2 ] == 1'b1 ); | |
2738 | assign dtmu_6 = mmu_d_eccerr[6] & (mmu_thr6_err_type[2 ] == 1'b1 ); | |
2739 | assign dtmu_5 = mmu_d_eccerr[5] & (mmu_thr5_err_type[2 ] == 1'b1 ); | |
2740 | assign dtmu_4 = mmu_d_eccerr[4] & (mmu_thr4_err_type[2 ] == 1'b1 ); | |
2741 | assign dtmu_3 = mmu_d_eccerr[3] & (mmu_thr3_err_type[2 ] == 1'b1 ); | |
2742 | assign dtmu_2 = mmu_d_eccerr[2] & (mmu_thr2_err_type[2 ] == 1'b1 ); | |
2743 | assign dtmu_1 = mmu_d_eccerr[1] & (mmu_thr1_err_type[2 ] == 1'b1 ); | |
2744 | assign dtmu_0 = mmu_d_eccerr[0] & (mmu_thr0_err_type[2 ] == 1'b1 ); | |
2745 | ||
2746 | assign dtl2u_7 = mmu_d_eccerr[7] & (mmu_thr7_err_type[2:0] == 3'b010); | |
2747 | assign dtl2u_6 = mmu_d_eccerr[6] & (mmu_thr6_err_type[2:0] == 3'b010); | |
2748 | assign dtl2u_5 = mmu_d_eccerr[5] & (mmu_thr5_err_type[2:0] == 3'b010); | |
2749 | assign dtl2u_4 = mmu_d_eccerr[4] & (mmu_thr4_err_type[2:0] == 3'b010); | |
2750 | assign dtl2u_3 = mmu_d_eccerr[3] & (mmu_thr3_err_type[2:0] == 3'b010); | |
2751 | assign dtl2u_2 = mmu_d_eccerr[2] & (mmu_thr2_err_type[2:0] == 3'b010); | |
2752 | assign dtl2u_1 = mmu_d_eccerr[1] & (mmu_thr1_err_type[2:0] == 3'b010); | |
2753 | assign dtl2u_0 = mmu_d_eccerr[0] & (mmu_thr0_err_type[2:0] == 3'b010); | |
2754 | ||
2755 | assign dtl2nd_7 = mmu_d_eccerr[7] & (mmu_thr7_err_type[2:0] == 3'b011); | |
2756 | assign dtl2nd_6 = mmu_d_eccerr[6] & (mmu_thr6_err_type[2:0] == 3'b011); | |
2757 | assign dtl2nd_5 = mmu_d_eccerr[5] & (mmu_thr5_err_type[2:0] == 3'b011); | |
2758 | assign dtl2nd_4 = mmu_d_eccerr[4] & (mmu_thr4_err_type[2:0] == 3'b011); | |
2759 | assign dtl2nd_3 = mmu_d_eccerr[3] & (mmu_thr3_err_type[2:0] == 3'b011); | |
2760 | assign dtl2nd_2 = mmu_d_eccerr[2] & (mmu_thr2_err_type[2:0] == 3'b011); | |
2761 | assign dtl2nd_1 = mmu_d_eccerr[1] & (mmu_thr1_err_type[2:0] == 3'b011); | |
2762 | assign dtl2nd_0 = mmu_d_eccerr[0] & (mmu_thr0_err_type[2:0] == 3'b011); | |
2763 | ||
2764 | assign m_dsfsr_7[2:0] = | |
2765 | ({3 { dtmu_7}} & 3'b100) | | |
2766 | ({3 { dtl2u_7}} & 3'b101) | | |
2767 | ({3 {dtl2nd_7}} & 3'b110) ; | |
2768 | assign m_dsfsr_6[2:0] = | |
2769 | ({3 { dtmu_6}} & 3'b100) | | |
2770 | ({3 { dtl2u_6}} & 3'b101) | | |
2771 | ({3 {dtl2nd_6}} & 3'b110) ; | |
2772 | assign m_dsfsr_5[2:0] = | |
2773 | ({3 { dtmu_5}} & 3'b100) | | |
2774 | ({3 { dtl2u_5}} & 3'b101) | | |
2775 | ({3 {dtl2nd_5}} & 3'b110) ; | |
2776 | assign m_dsfsr_4[2:0] = | |
2777 | ({3 { dtmu_4}} & 3'b100) | | |
2778 | ({3 { dtl2u_4}} & 3'b101) | | |
2779 | ({3 {dtl2nd_4}} & 3'b110) ; | |
2780 | assign m_dsfsr_3[2:0] = | |
2781 | ({3 { dtmu_3}} & 3'b100) | | |
2782 | ({3 { dtl2u_3}} & 3'b101) | | |
2783 | ({3 {dtl2nd_3}} & 3'b110) ; | |
2784 | assign m_dsfsr_2[2:0] = | |
2785 | ({3 { dtmu_2}} & 3'b100) | | |
2786 | ({3 { dtl2u_2}} & 3'b101) | | |
2787 | ({3 {dtl2nd_2}} & 3'b110) ; | |
2788 | assign m_dsfsr_1[2:0] = | |
2789 | ({3 { dtmu_1}} & 3'b100) | | |
2790 | ({3 { dtl2u_1}} & 3'b101) | | |
2791 | ({3 {dtl2nd_1}} & 3'b110) ; | |
2792 | assign m_dsfsr_0[2:0] = | |
2793 | ({3 { dtmu_0}} & 3'b100) | | |
2794 | ({3 { dtl2u_0}} & 3'b101) | | |
2795 | ({3 {dtl2nd_0}} & 3'b110) ; | |
2796 | ||
2797 | assign m_dsfar_7[2:0] = | |
2798 | mmu_thr7_err_index[2:0] & {3 {mmu_i_eccerr[7] | mmu_d_eccerr[7]}}; | |
2799 | assign m_dsfar_6[2:0] = | |
2800 | mmu_thr6_err_index[2:0] & {3 {mmu_i_eccerr[6] | mmu_d_eccerr[6]}}; | |
2801 | assign m_dsfar_5[2:0] = | |
2802 | mmu_thr5_err_index[2:0] & {3 {mmu_i_eccerr[5] | mmu_d_eccerr[5]}}; | |
2803 | assign m_dsfar_4[2:0] = | |
2804 | mmu_thr4_err_index[2:0] & {3 {mmu_i_eccerr[4] | mmu_d_eccerr[4]}}; | |
2805 | assign m_dsfar_3[2:0] = | |
2806 | mmu_thr3_err_index[2:0] & {3 {mmu_i_eccerr[3] | mmu_d_eccerr[3]}}; | |
2807 | assign m_dsfar_2[2:0] = | |
2808 | mmu_thr2_err_index[2:0] & {3 {mmu_i_eccerr[2] | mmu_d_eccerr[2]}}; | |
2809 | assign m_dsfar_1[2:0] = | |
2810 | mmu_thr1_err_index[2:0] & {3 {mmu_i_eccerr[1] | mmu_d_eccerr[1]}}; | |
2811 | assign m_dsfar_0[2:0] = | |
2812 | mmu_thr0_err_index[2:0] & {3 {mmu_i_eccerr[0] | mmu_d_eccerr[0]}}; | |
2813 | ||
2814 | ||
2815 | tlu_ras_ctl_msff_ctl_macro__width_8 it2lc_lat ( | |
2816 | .scan_in(it2lc_lat_scanin), | |
2817 | .scan_out(it2lc_lat_scanout), | |
2818 | .din (mmu_i_l2cerr [7:0] ), | |
2819 | .dout (m_i_l2cerr [7:0] ), | |
2820 | .l1clk(l1clk), | |
2821 | .siclk(siclk), | |
2822 | .soclk(soclk) | |
2823 | ); | |
2824 | ||
2825 | tlu_ras_ctl_msff_ctl_macro__width_8 dt2lc_lat ( | |
2826 | .scan_in(dt2lc_lat_scanin), | |
2827 | .scan_out(dt2lc_lat_scanout), | |
2828 | .din (mmu_d_l2cerr [7:0] ), | |
2829 | .dout (m_d_l2cerr [7:0] ), | |
2830 | .l1clk(l1clk), | |
2831 | .siclk(siclk), | |
2832 | .soclk(soclk) | |
2833 | ); | |
2834 | ||
2835 | assign itl2c_7 = m_i_l2cerr[7]; | |
2836 | assign itl2c_6 = m_i_l2cerr[6]; | |
2837 | assign itl2c_5 = m_i_l2cerr[5]; | |
2838 | assign itl2c_4 = m_i_l2cerr[4]; | |
2839 | assign itl2c_3 = m_i_l2cerr[3]; | |
2840 | assign itl2c_2 = m_i_l2cerr[2]; | |
2841 | assign itl2c_1 = m_i_l2cerr[1]; | |
2842 | assign itl2c_0 = m_i_l2cerr[0]; | |
2843 | ||
2844 | assign dtl2c_7 = m_d_l2cerr[7]; | |
2845 | assign dtl2c_6 = m_d_l2cerr[6]; | |
2846 | assign dtl2c_5 = m_d_l2cerr[5]; | |
2847 | assign dtl2c_4 = m_d_l2cerr[4]; | |
2848 | assign dtl2c_3 = m_d_l2cerr[3]; | |
2849 | assign dtl2c_2 = m_d_l2cerr[2]; | |
2850 | assign dtl2c_1 = m_d_l2cerr[1]; | |
2851 | assign dtl2c_0 = m_d_l2cerr[0]; | |
2852 | ||
2853 | assign m_desr_et_7[5:0] = | |
2854 | ({6 { itl2c_7}} & 6'b100001) | | |
2855 | ({6 { dtl2c_7}} & 6'b100011) ; | |
2856 | assign m_desr_et_6[5:0] = | |
2857 | ({6 { itl2c_6}} & 6'b100001) | | |
2858 | ({6 { dtl2c_6}} & 6'b100011) ; | |
2859 | assign m_desr_et_5[5:0] = | |
2860 | ({6 { itl2c_5}} & 6'b100001) | | |
2861 | ({6 { dtl2c_5}} & 6'b100011) ; | |
2862 | assign m_desr_et_4[5:0] = | |
2863 | ({6 { itl2c_4}} & 6'b100001) | | |
2864 | ({6 { dtl2c_4}} & 6'b100011) ; | |
2865 | assign m_desr_et_3[5:0] = | |
2866 | ({6 { itl2c_3}} & 6'b100001) | | |
2867 | ({6 { dtl2c_3}} & 6'b100011) ; | |
2868 | assign m_desr_et_2[5:0] = | |
2869 | ({6 { itl2c_2}} & 6'b100001) | | |
2870 | ({6 { dtl2c_2}} & 6'b100011) ; | |
2871 | assign m_desr_et_1[5:0] = | |
2872 | ({6 { itl2c_1}} & 6'b100001) | | |
2873 | ({6 { dtl2c_1}} & 6'b100011) ; | |
2874 | assign m_desr_et_0[5:0] = | |
2875 | ({6 { itl2c_0}} & 6'b100001) | | |
2876 | ({6 { dtl2c_0}} & 6'b100011) ; | |
2877 | ||
2878 | // No desr_ea for L2 correctable errors for MMU | |
2879 | ||
2880 | ||
2881 | ||
2882 | // | |
2883 | // MRA, SCA, and TCA precise but out-of-pipe errors (ASI access) | |
2884 | // | |
2885 | // DSFSR | |
2886 | // mrau 0111 | |
2887 | // scac 1010 | |
2888 | // scau 1001 | |
2889 | // tccp 1100 | |
2890 | // tccu(tcup) 1101 | |
2891 | ||
2892 | // Both sources should have same TID | |
2893 | // but TCA errors take a cycle longer to be recorded due to longer path for | |
2894 | // disrupting TCA errors | |
2895 | assign a_tid[2:0] = | |
2896 | tlu_tca_tid[2:0]; | |
2897 | ||
2898 | assign a_dec_tid[7:0] = | |
2899 | { a_tid[2] & a_tid[1] & a_tid[0], | |
2900 | a_tid[2] & a_tid[1] & ~a_tid[0], | |
2901 | a_tid[2] & ~a_tid[1] & a_tid[0], | |
2902 | a_tid[2] & ~a_tid[1] & ~a_tid[0], | |
2903 | ~a_tid[2] & a_tid[1] & a_tid[0], | |
2904 | ~a_tid[2] & a_tid[1] & ~a_tid[0], | |
2905 | ~a_tid[2] & ~a_tid[1] & a_tid[0], | |
2906 | ~a_tid[2] & ~a_tid[1] & ~a_tid[0]} & | |
2907 | {8 {mrau | scac | scau}}; | |
2908 | ||
2909 | ||
2910 | tlu_ras_ctl_msff_ctl_macro__width_5 tca_error_lat ( | |
2911 | .scan_in(tca_error_lat_scanin), | |
2912 | .scan_out(tca_error_lat_scanout), | |
2913 | .din ({cel_tccp , | |
2914 | cel_tcup , | |
2915 | tlu_tca_tid [2:0]}), | |
2916 | .dout ({tccp , | |
2917 | tcup , | |
2918 | tca_tid [2:0]}), | |
2919 | .l1clk(l1clk), | |
2920 | .siclk(siclk), | |
2921 | .soclk(soclk) | |
2922 | ); | |
2923 | ||
2924 | assign tca_dec_tid[7:0] = | |
2925 | { tca_tid[2] & tca_tid[1] & tca_tid[0], | |
2926 | tca_tid[2] & tca_tid[1] & ~tca_tid[0], | |
2927 | tca_tid[2] & ~tca_tid[1] & tca_tid[0], | |
2928 | tca_tid[2] & ~tca_tid[1] & ~tca_tid[0], | |
2929 | ~tca_tid[2] & tca_tid[1] & tca_tid[0], | |
2930 | ~tca_tid[2] & tca_tid[1] & ~tca_tid[0], | |
2931 | ~tca_tid[2] & ~tca_tid[1] & tca_tid[0], | |
2932 | ~tca_tid[2] & ~tca_tid[1] & ~tca_tid[0]} & | |
2933 | {8 {tccp | tcup}}; | |
2934 | ||
2935 | assign mrau = | |
2936 | mmu_asi_uecc & mmu_asi_mra_not_sca; | |
2937 | assign scac = | |
2938 | mmu_asi_cecc & ~mmu_asi_mra_not_sca; | |
2939 | assign scau = | |
2940 | mmu_asi_uecc & ~mmu_asi_mra_not_sca; | |
2941 | ||
2942 | assign a_dsfsr[3:0] = | |
2943 | ({4 {mrau}} & 4'b0111) | | |
2944 | ({4 {scac}} & 4'b1010) | | |
2945 | ({4 {scau}} & 4'b1011) ; | |
2946 | assign tca_dsfsr[3:0] = | |
2947 | ({4 {tccp}} & 4'b1100) | | |
2948 | ({4 {tcup}} & 4'b1101) ; | |
2949 | assign a_dsfsr_7[3:0] = | |
2950 | ( a_dsfsr[3:0] & {4 { a_dec_tid[7]}}) | | |
2951 | (tca_dsfsr[3:0] & {4 {tca_dec_tid[7]}}) ; | |
2952 | assign a_dsfsr_6[3:0] = | |
2953 | ( a_dsfsr[3:0] & {4 { a_dec_tid[6]}}) | | |
2954 | (tca_dsfsr[3:0] & {4 {tca_dec_tid[6]}}) ; | |
2955 | assign a_dsfsr_5[3:0] = | |
2956 | ( a_dsfsr[3:0] & {4 { a_dec_tid[5]}}) | | |
2957 | (tca_dsfsr[3:0] & {4 {tca_dec_tid[5]}}) ; | |
2958 | assign a_dsfsr_4[3:0] = | |
2959 | ( a_dsfsr[3:0] & {4 { a_dec_tid[4]}}) | | |
2960 | (tca_dsfsr[3:0] & {4 {tca_dec_tid[4]}}) ; | |
2961 | assign a_dsfsr_3[3:0] = | |
2962 | ( a_dsfsr[3:0] & {4 { a_dec_tid[3]}}) | | |
2963 | (tca_dsfsr[3:0] & {4 {tca_dec_tid[3]}}) ; | |
2964 | assign a_dsfsr_2[3:0] = | |
2965 | ( a_dsfsr[3:0] & {4 { a_dec_tid[2]}}) | | |
2966 | (tca_dsfsr[3:0] & {4 {tca_dec_tid[2]}}) ; | |
2967 | assign a_dsfsr_1[3:0] = | |
2968 | ( a_dsfsr[3:0] & {4 { a_dec_tid[1]}}) | | |
2969 | (tca_dsfsr[3:0] & {4 {tca_dec_tid[1]}}) ; | |
2970 | assign a_dsfsr_0[3:0] = | |
2971 | ( a_dsfsr[3:0] & {4 { a_dec_tid[0]}}) | | |
2972 | (tca_dsfsr[3:0] & {4 {tca_dec_tid[0]}}) ; | |
2973 | ||
2974 | assign a_dsfar[10:0] = | |
2975 | ({11 {scac | scau}} & mmu_asi_index[10:0] ) | | |
2976 | ({11 {mrau }} &{{8 {1'b0}}, mmu_asi_index[2:0]}) ; | |
2977 | assign tca_dsfar[10:0] = | |
2978 | ({11 {tccp | tcup}} & | |
2979 | {1'b0, cel_syndrome[7:0], tlu_tca_index[1:0]}) ; | |
2980 | ||
2981 | assign a_dsfar_7[10:0] = | |
2982 | ( a_dsfar[10:0] & {11 { a_dec_tid[7]}}) | | |
2983 | (tca_dsfar[10:0] & {11 {tca_dec_tid[7]}}) ; | |
2984 | assign a_dsfar_6[10:0] = | |
2985 | ( a_dsfar[10:0] & {11 { a_dec_tid[6]}}) | | |
2986 | (tca_dsfar[10:0] & {11 {tca_dec_tid[6]}}) ; | |
2987 | assign a_dsfar_5[10:0] = | |
2988 | ( a_dsfar[10:0] & {11 { a_dec_tid[5]}}) | | |
2989 | (tca_dsfar[10:0] & {11 {tca_dec_tid[5]}}) ; | |
2990 | assign a_dsfar_4[10:0] = | |
2991 | ( a_dsfar[10:0] & {11 { a_dec_tid[4]}}) | | |
2992 | (tca_dsfar[10:0] & {11 {tca_dec_tid[4]}}) ; | |
2993 | assign a_dsfar_3[10:0] = | |
2994 | ( a_dsfar[10:0] & {11 { a_dec_tid[3]}}) | | |
2995 | (tca_dsfar[10:0] & {11 {tca_dec_tid[3]}}) ; | |
2996 | assign a_dsfar_2[10:0] = | |
2997 | ( a_dsfar[10:0] & {11 { a_dec_tid[2]}}) | | |
2998 | (tca_dsfar[10:0] & {11 {tca_dec_tid[2]}}) ; | |
2999 | assign a_dsfar_1[10:0] = | |
3000 | ( a_dsfar[10:0] & {11 { a_dec_tid[1]}}) | | |
3001 | (tca_dsfar[10:0] & {11 {tca_dec_tid[1]}}) ; | |
3002 | assign a_dsfar_0[10:0] = | |
3003 | ( a_dsfar[10:0] & {11 { a_dec_tid[0]}}) | | |
3004 | (tca_dsfar[10:0] & {11 {tca_dec_tid[0]}}) ; | |
3005 | ||
3006 | ||
3007 | ||
3008 | // | |
3009 | // TSA precise but out-of-pipe errors (ASI access and done and retry) | |
3010 | // | |
3011 | // DSFSR | |
3012 | // tsac 1000 | |
3013 | // tsau 1001 | |
3014 | ||
3015 | assign ta_dec_tid[7:0] = | |
3016 | { asi_tsacu_tid[2] & asi_tsacu_tid[1] & asi_tsacu_tid[0], | |
3017 | asi_tsacu_tid[2] & asi_tsacu_tid[1] & ~asi_tsacu_tid[0], | |
3018 | asi_tsacu_tid[2] & ~asi_tsacu_tid[1] & asi_tsacu_tid[0], | |
3019 | asi_tsacu_tid[2] & ~asi_tsacu_tid[1] & ~asi_tsacu_tid[0], | |
3020 | ~asi_tsacu_tid[2] & asi_tsacu_tid[1] & asi_tsacu_tid[0], | |
3021 | ~asi_tsacu_tid[2] & asi_tsacu_tid[1] & ~asi_tsacu_tid[0], | |
3022 | ~asi_tsacu_tid[2] & ~asi_tsacu_tid[1] & asi_tsacu_tid[0], | |
3023 | ~asi_tsacu_tid[2] & ~asi_tsacu_tid[1] & ~asi_tsacu_tid[0]}; | |
3024 | ||
3025 | assign tsac[7:0] = | |
3026 | tlu_tsac[7:0] | ({8 {asi_tsac}} & ta_dec_tid[7:0]); | |
3027 | ||
3028 | assign tsau[7:0] = | |
3029 | tlu_tsau[7:0] | ({8 {asi_tsau}} & ta_dec_tid[7:0]); | |
3030 | ||
3031 | assign ras_dsfar_sel_tsa[7:0] = | |
3032 | tsac[7:0] | tsau[7:0]; | |
3033 | ||
3034 | assign t_dsfsr_7[3:0] = | |
3035 | ({4 {tsac[7]}} & 4'b1000) | | |
3036 | ({4 {tsau[7]}} & 4'b1001) ; | |
3037 | assign t_dsfsr_6[3:0] = | |
3038 | ({4 {tsac[6]}} & 4'b1000) | | |
3039 | ({4 {tsau[6]}} & 4'b1001) ; | |
3040 | assign t_dsfsr_5[3:0] = | |
3041 | ({4 {tsac[5]}} & 4'b1000) | | |
3042 | ({4 {tsau[5]}} & 4'b1001) ; | |
3043 | assign t_dsfsr_4[3:0] = | |
3044 | ({4 {tsac[4]}} & 4'b1000) | | |
3045 | ({4 {tsau[4]}} & 4'b1001) ; | |
3046 | assign t_dsfsr_3[3:0] = | |
3047 | ({4 {tsac[3]}} & 4'b1000) | | |
3048 | ({4 {tsau[3]}} & 4'b1001) ; | |
3049 | assign t_dsfsr_2[3:0] = | |
3050 | ({4 {tsac[2]}} & 4'b1000) | | |
3051 | ({4 {tsau[2]}} & 4'b1001) ; | |
3052 | assign t_dsfsr_1[3:0] = | |
3053 | ({4 {tsac[1]}} & 4'b1000) | | |
3054 | ({4 {tsau[1]}} & 4'b1001) ; | |
3055 | assign t_dsfsr_0[3:0] = | |
3056 | ({4 {tsac[0]}} & 4'b1000) | | |
3057 | ({4 {tsau[0]}} & 4'b1001) ; | |
3058 | ||
3059 | // DSFAR for TSA errors handled in tlu_dfd_dp | |
3060 | ||
3061 | ||
3062 | ||
3063 | // | |
3064 | // Data cache errors on L2 | |
3065 | // | |
3066 | // DSFSR | |
3067 | // dcl2u 001 | |
3068 | // dcl2nd 010 | |
3069 | // socc 011 | |
3070 | // socu 100 | |
3071 | // | |
3072 | // DESR | |
3073 | // dcl2c 1011 | |
3074 | // This has S = 0 | |
3075 | // dcl2c 100 | |
3076 | // This has S = 1 | |
3077 | ||
3078 | tlu_ras_ctl_msff_ctl_macro__width_9 l_dsfar_lat ( | |
3079 | .scan_in(l_dsfar_lat_scanin), | |
3080 | .scan_out(l_dsfar_lat_scanout), | |
3081 | .din (lsu_dcerr_sfar_g [8:0] ), | |
3082 | .dout (l_dsfar [8:0] ), | |
3083 | .l1clk(l1clk), | |
3084 | .siclk(siclk), | |
3085 | .soclk(soclk) | |
3086 | ); | |
3087 | ||
3088 | tlu_ras_ctl_msff_ctl_macro__width_3 l_tid_lat ( | |
3089 | .scan_in(l_tid_lat_scanin), | |
3090 | .scan_out(l_tid_lat_scanout), | |
3091 | .din (lsu_dcerr_tid_g [2:0] ), | |
3092 | .dout (l_tid [2:0] ), | |
3093 | .l1clk(l1clk), | |
3094 | .siclk(siclk), | |
3095 | .soclk(soclk) | |
3096 | ); | |
3097 | ||
3098 | tlu_ras_ctl_msff_ctl_macro__width_1 dcl2c_lat ( | |
3099 | .scan_in(dcl2c_lat_scanin), | |
3100 | .scan_out(dcl2c_lat_scanout), | |
3101 | .din (lsu_dcl2c_err_g ), | |
3102 | .dout (dcl2c ), | |
3103 | .l1clk(l1clk), | |
3104 | .siclk(siclk), | |
3105 | .soclk(soclk) | |
3106 | ); | |
3107 | ||
3108 | tlu_ras_ctl_msff_ctl_macro__width_1 dcl2u_lat ( | |
3109 | .scan_in(dcl2u_lat_scanin), | |
3110 | .scan_out(dcl2u_lat_scanout), | |
3111 | .din (lsu_dcl2u_err_g ), | |
3112 | .dout (dcl2u ), | |
3113 | .l1clk(l1clk), | |
3114 | .siclk(siclk), | |
3115 | .soclk(soclk) | |
3116 | ); | |
3117 | ||
3118 | tlu_ras_ctl_msff_ctl_macro__width_1 dcl2nd_lat ( | |
3119 | .scan_in(dcl2nd_lat_scanin), | |
3120 | .scan_out(dcl2nd_lat_scanout), | |
3121 | .din (lsu_dcl2nd_err_g ), | |
3122 | .dout (dcl2nd ), | |
3123 | .l1clk(l1clk), | |
3124 | .siclk(siclk), | |
3125 | .soclk(soclk) | |
3126 | ); | |
3127 | ||
3128 | tlu_ras_ctl_msff_ctl_macro__width_1 dcsoc_lat ( | |
3129 | .scan_in(dcsoc_lat_scanin), | |
3130 | .scan_out(dcsoc_lat_scanout), | |
3131 | .din (lsu_dcsoc_err_g ), | |
3132 | .dout (dcsoc ), | |
3133 | .l1clk(l1clk), | |
3134 | .siclk(siclk), | |
3135 | .soclk(soclk) | |
3136 | ); | |
3137 | ||
3138 | assign l_dec_tid[7:0] = | |
3139 | { l_tid[2] & l_tid[1] & l_tid[0], | |
3140 | l_tid[2] & l_tid[1] & ~l_tid[0], | |
3141 | l_tid[2] & ~l_tid[1] & l_tid[0], | |
3142 | l_tid[2] & ~l_tid[1] & ~l_tid[0], | |
3143 | ~l_tid[2] & l_tid[1] & l_tid[0], | |
3144 | ~l_tid[2] & l_tid[1] & ~l_tid[0], | |
3145 | ~l_tid[2] & ~l_tid[1] & l_tid[0], | |
3146 | ~l_tid[2] & ~l_tid[1] & ~l_tid[0]} & {8 {dcl2c | dcl2u | dcl2nd}}; | |
3147 | ||
3148 | assign l_dsfsr[2:0] = | |
3149 | ({3 {dcl2u & ~dcsoc}} & 3'b001) | | |
3150 | ({3 {dcl2nd & ~dcsoc}} & 3'b010) | | |
3151 | ({3 {dcl2u & dcsoc}} & 3'b100) ; | |
3152 | ||
3153 | assign l_dsfsr_7[2:0] = | |
3154 | l_dsfsr[2:0] & {3 {l_dec_tid[7]}}; | |
3155 | assign l_dsfsr_6[2:0] = | |
3156 | l_dsfsr[2:0] & {3 {l_dec_tid[6]}}; | |
3157 | assign l_dsfsr_5[2:0] = | |
3158 | l_dsfsr[2:0] & {3 {l_dec_tid[5]}}; | |
3159 | assign l_dsfsr_4[2:0] = | |
3160 | l_dsfsr[2:0] & {3 {l_dec_tid[4]}}; | |
3161 | assign l_dsfsr_3[2:0] = | |
3162 | l_dsfsr[2:0] & {3 {l_dec_tid[3]}}; | |
3163 | assign l_dsfsr_2[2:0] = | |
3164 | l_dsfsr[2:0] & {3 {l_dec_tid[2]}}; | |
3165 | assign l_dsfsr_1[2:0] = | |
3166 | l_dsfsr[2:0] & {3 {l_dec_tid[1]}}; | |
3167 | assign l_dsfsr_0[2:0] = | |
3168 | l_dsfsr[2:0] & {3 {l_dec_tid[0]}}; | |
3169 | ||
3170 | assign l_dsfar_7[8:0] = | |
3171 | l_dsfar[8:0] & {9 {l_dec_tid[7]}}; | |
3172 | assign l_dsfar_6[8:0] = | |
3173 | l_dsfar[8:0] & {9 {l_dec_tid[6]}}; | |
3174 | assign l_dsfar_5[8:0] = | |
3175 | l_dsfar[8:0] & {9 {l_dec_tid[5]}}; | |
3176 | assign l_dsfar_4[8:0] = | |
3177 | l_dsfar[8:0] & {9 {l_dec_tid[4]}}; | |
3178 | assign l_dsfar_3[8:0] = | |
3179 | l_dsfar[8:0] & {9 {l_dec_tid[3]}}; | |
3180 | assign l_dsfar_2[8:0] = | |
3181 | l_dsfar[8:0] & {9 {l_dec_tid[2]}}; | |
3182 | assign l_dsfar_1[8:0] = | |
3183 | l_dsfar[8:0] & {9 {l_dec_tid[1]}}; | |
3184 | assign l_dsfar_0[8:0] = | |
3185 | l_dsfar[8:0] & {9 {l_dec_tid[0]}}; | |
3186 | ||
3187 | ||
3188 | assign l_desr_et[5:0] = | |
3189 | ({6 {dcl2c & dcsoc}} & 6'b001011) | | |
3190 | ({6 {dcl2c & ~dcsoc}} & 6'b100100) ; | |
3191 | ||
3192 | assign l_desr_et_7[5:0] = | |
3193 | l_desr_et[5:0] & {6 {l_dec_tid[7]}}; | |
3194 | assign l_desr_et_6[5:0] = | |
3195 | l_desr_et[5:0] & {6 {l_dec_tid[6]}}; | |
3196 | assign l_desr_et_5[5:0] = | |
3197 | l_desr_et[5:0] & {6 {l_dec_tid[5]}}; | |
3198 | assign l_desr_et_4[5:0] = | |
3199 | l_desr_et[5:0] & {6 {l_dec_tid[4]}}; | |
3200 | assign l_desr_et_3[5:0] = | |
3201 | l_desr_et[5:0] & {6 {l_dec_tid[3]}}; | |
3202 | assign l_desr_et_2[5:0] = | |
3203 | l_desr_et[5:0] & {6 {l_dec_tid[2]}}; | |
3204 | assign l_desr_et_1[5:0] = | |
3205 | l_desr_et[5:0] & {6 {l_dec_tid[1]}}; | |
3206 | assign l_desr_et_0[5:0] = | |
3207 | l_desr_et[5:0] & {6 {l_dec_tid[0]}}; | |
3208 | ||
3209 | ||
3210 | ||
3211 | // | |
3212 | // Precise but out-of-pipe store buffer errors | |
3213 | // | |
3214 | // DSFSR | |
3215 | // sbdlc 101 | |
3216 | // sbdlu 110 | |
3217 | ||
3218 | tlu_ras_ctl_msff_ctl_macro__width_5 s_dsfar_lat ( | |
3219 | .scan_in(s_dsfar_lat_scanin), | |
3220 | .scan_out(s_dsfar_lat_scanout), | |
3221 | .din ({lsu_stberr_priv_g [1:0], | |
3222 | lsu_stberr_index_g [2:0]}), | |
3223 | .dout ({fesr_priv [1:0], | |
3224 | s_dsfar [2:0]}), | |
3225 | .l1clk(l1clk), | |
3226 | .siclk(siclk), | |
3227 | .soclk(soclk) | |
3228 | ); | |
3229 | ||
3230 | tlu_ras_ctl_msff_ctl_macro__width_3 s_tid_lat ( | |
3231 | .scan_in(s_tid_lat_scanin), | |
3232 | .scan_out(s_tid_lat_scanout), | |
3233 | .din (lsu_stberr_tid_g [2:0] ), | |
3234 | .dout (s_tid [2:0] ), | |
3235 | .l1clk(l1clk), | |
3236 | .siclk(siclk), | |
3237 | .soclk(soclk) | |
3238 | ); | |
3239 | ||
3240 | tlu_ras_ctl_msff_ctl_macro__width_1 stb_flush_lat ( | |
3241 | .scan_in(stb_flush_lat_scanin), | |
3242 | .scan_out(stb_flush_lat_scanout), | |
3243 | .din (lsu_stb_flush_g ), | |
3244 | .dout (stb_flush ), | |
3245 | .l1clk(l1clk), | |
3246 | .siclk(siclk), | |
3247 | .soclk(soclk) | |
3248 | ); | |
3249 | ||
3250 | assign update_priv[7:0] = | |
3251 | {8 {stb_flush}} & s_dsfsr_dec_tid_raw[7:0] & | |
3252 | {(fesr_priv[1] & ~dfd_fesr_priv_7[1] ) | | |
3253 | (fesr_priv[0] & ~dfd_fesr_priv_7[1] & ~dfd_fesr_priv_7[0]), | |
3254 | (fesr_priv[1] & ~dfd_fesr_priv_6[1] ) | | |
3255 | (fesr_priv[0] & ~dfd_fesr_priv_6[1] & ~dfd_fesr_priv_6[0]), | |
3256 | (fesr_priv[1] & ~dfd_fesr_priv_5[1] ) | | |
3257 | (fesr_priv[0] & ~dfd_fesr_priv_5[1] & ~dfd_fesr_priv_5[0]), | |
3258 | (fesr_priv[1] & ~dfd_fesr_priv_4[1] ) | | |
3259 | (fesr_priv[0] & ~dfd_fesr_priv_4[1] & ~dfd_fesr_priv_4[0]), | |
3260 | (fesr_priv[1] & ~dfd_fesr_priv_3[1] ) | | |
3261 | (fesr_priv[0] & ~dfd_fesr_priv_3[1] & ~dfd_fesr_priv_3[0]), | |
3262 | (fesr_priv[1] & ~dfd_fesr_priv_2[1] ) | | |
3263 | (fesr_priv[0] & ~dfd_fesr_priv_2[1] & ~dfd_fesr_priv_2[0]), | |
3264 | (fesr_priv[1] & ~dfd_fesr_priv_1[1] ) | | |
3265 | (fesr_priv[0] & ~dfd_fesr_priv_1[1] & ~dfd_fesr_priv_1[0]), | |
3266 | (fesr_priv[1] & ~dfd_fesr_priv_0[1] ) | | |
3267 | (fesr_priv[0] & ~dfd_fesr_priv_0[1] & ~dfd_fesr_priv_0[0]) }; | |
3268 | ||
3269 | assign ras_update_priv[7:0] = | |
3270 | update_priv[7:0]; | |
3271 | ||
3272 | assign ras_fesr_priv[59:58] = | |
3273 | fesr_priv[1:0]; | |
3274 | ||
3275 | tlu_ras_ctl_msff_ctl_macro__width_1 sbdlc_lat ( | |
3276 | .scan_in(sbdlc_lat_scanin), | |
3277 | .scan_out(sbdlc_lat_scanout), | |
3278 | .din (lsu_sbdlc_err_g ), | |
3279 | .dout (sbdlc ), | |
3280 | .l1clk(l1clk), | |
3281 | .siclk(siclk), | |
3282 | .soclk(soclk) | |
3283 | ); | |
3284 | ||
3285 | tlu_ras_ctl_msff_ctl_macro__width_1 sbdlu_lat ( | |
3286 | .scan_in(sbdlu_lat_scanin), | |
3287 | .scan_out(sbdlu_lat_scanout), | |
3288 | .din (lsu_sbdlu_err_g ), | |
3289 | .dout (sbdlu ), | |
3290 | .l1clk(l1clk), | |
3291 | .siclk(siclk), | |
3292 | .soclk(soclk) | |
3293 | ); | |
3294 | ||
3295 | assign s_dsfsr_dec_tid_raw[7:0] = | |
3296 | { s_tid[2] & s_tid[1] & s_tid[0], | |
3297 | s_tid[2] & s_tid[1] & ~s_tid[0], | |
3298 | s_tid[2] & ~s_tid[1] & s_tid[0], | |
3299 | s_tid[2] & ~s_tid[1] & ~s_tid[0], | |
3300 | ~s_tid[2] & s_tid[1] & s_tid[0], | |
3301 | ~s_tid[2] & s_tid[1] & ~s_tid[0], | |
3302 | ~s_tid[2] & ~s_tid[1] & s_tid[0], | |
3303 | ~s_tid[2] & ~s_tid[1] & ~s_tid[0]} ; | |
3304 | assign s_dsfsr_dec_tid[7:0] = | |
3305 | s_dsfsr_dec_tid_raw[7:0] & | |
3306 | {8 {sbdlc | sbdlu}}; | |
3307 | ||
3308 | assign s_dsfsr[2:0] = | |
3309 | ({3 {sbdlc}} & 3'b101) | | |
3310 | ({3 {sbdlu}} & 3'b110) ; | |
3311 | ||
3312 | assign s_dsfsr_7[2:0] = | |
3313 | s_dsfsr[2:0] & {3 {s_dsfsr_dec_tid[7]}}; | |
3314 | assign s_dsfsr_6[2:0] = | |
3315 | s_dsfsr[2:0] & {3 {s_dsfsr_dec_tid[6]}}; | |
3316 | assign s_dsfsr_5[2:0] = | |
3317 | s_dsfsr[2:0] & {3 {s_dsfsr_dec_tid[5]}}; | |
3318 | assign s_dsfsr_4[2:0] = | |
3319 | s_dsfsr[2:0] & {3 {s_dsfsr_dec_tid[4]}}; | |
3320 | assign s_dsfsr_3[2:0] = | |
3321 | s_dsfsr[2:0] & {3 {s_dsfsr_dec_tid[3]}}; | |
3322 | assign s_dsfsr_2[2:0] = | |
3323 | s_dsfsr[2:0] & {3 {s_dsfsr_dec_tid[2]}}; | |
3324 | assign s_dsfsr_1[2:0] = | |
3325 | s_dsfsr[2:0] & {3 {s_dsfsr_dec_tid[1]}}; | |
3326 | assign s_dsfsr_0[2:0] = | |
3327 | s_dsfsr[2:0] & {3 {s_dsfsr_dec_tid[0]}}; | |
3328 | ||
3329 | assign s_dsfar_7[2:0] = | |
3330 | s_dsfar[2:0] & {3 {s_dsfsr_dec_tid[7]}}; | |
3331 | assign s_dsfar_6[2:0] = | |
3332 | s_dsfar[2:0] & {3 {s_dsfsr_dec_tid[6]}}; | |
3333 | assign s_dsfar_5[2:0] = | |
3334 | s_dsfar[2:0] & {3 {s_dsfsr_dec_tid[5]}}; | |
3335 | assign s_dsfar_4[2:0] = | |
3336 | s_dsfar[2:0] & {3 {s_dsfsr_dec_tid[4]}}; | |
3337 | assign s_dsfar_3[2:0] = | |
3338 | s_dsfar[2:0] & {3 {s_dsfsr_dec_tid[3]}}; | |
3339 | assign s_dsfar_2[2:0] = | |
3340 | s_dsfar[2:0] & {3 {s_dsfsr_dec_tid[2]}}; | |
3341 | assign s_dsfar_1[2:0] = | |
3342 | s_dsfar[2:0] & {3 {s_dsfsr_dec_tid[1]}}; | |
3343 | assign s_dsfar_0[2:0] = | |
3344 | s_dsfar[2:0] & {3 {s_dsfsr_dec_tid[0]}}; | |
3345 | ||
3346 | ||
3347 | ||
3348 | ////////////////////////////////////////////////////////////////////////////// | |
3349 | // | |
3350 | // Instantiate ISFSRs | |
3351 | // | |
3352 | ||
3353 | assign isfsr_7_new_in[2:0] = | |
3354 | pipe_isfsr_7[2:0] | m_isfsr_7[2:0] ; | |
3355 | assign isfsr_6_new_in[2:0] = | |
3356 | pipe_isfsr_6[2:0] | m_isfsr_6[2:0] ; | |
3357 | assign isfsr_5_new_in[2:0] = | |
3358 | pipe_isfsr_5[2:0] | m_isfsr_5[2:0] ; | |
3359 | assign isfsr_4_new_in[2:0] = | |
3360 | pipe_isfsr_4[2:0] | m_isfsr_4[2:0] ; | |
3361 | assign isfsr_3_new_in[2:0] = | |
3362 | pipe_isfsr_3[2:0] | m_isfsr_3[2:0] ; | |
3363 | assign isfsr_2_new_in[2:0] = | |
3364 | pipe_isfsr_2[2:0] | m_isfsr_2[2:0] ; | |
3365 | assign isfsr_1_new_in[2:0] = | |
3366 | pipe_isfsr_1[2:0] | m_isfsr_1[2:0] ; | |
3367 | assign isfsr_0_new_in[2:0] = | |
3368 | pipe_isfsr_0[2:0] | m_isfsr_0[2:0] ; | |
3369 | ||
3370 | assign isfsr_7_in[2:0] = | |
3371 | (isfsr_7_new_in[2:0] & {3 {~asi_wr_isfsr[7]}}) | | |
3372 | (isfsr_7[2:0] & ~{3 {| {asi_wr_isfsr[7], isfsr_7_new_in[2:0]}}}) | | |
3373 | (asi_wr_data[2:0] & {3 { asi_wr_isfsr[7]}}) ; | |
3374 | assign isfsr_6_in[2:0] = | |
3375 | (isfsr_6_new_in[2:0] & {3 {~asi_wr_isfsr[6]}}) | | |
3376 | (isfsr_6[2:0] & ~{3 {| {asi_wr_isfsr[6], isfsr_6_new_in[2:0]}}}) | | |
3377 | (asi_wr_data[2:0] & {3 { asi_wr_isfsr[6]}}) ; | |
3378 | assign isfsr_5_in[2:0] = | |
3379 | (isfsr_5_new_in[2:0] & {3 {~asi_wr_isfsr[5]}}) | | |
3380 | (isfsr_5[2:0] & ~{3 {| {asi_wr_isfsr[5], isfsr_5_new_in[2:0]}}}) | | |
3381 | (asi_wr_data[2:0] & {3 { asi_wr_isfsr[5]}}) ; | |
3382 | assign isfsr_4_in[2:0] = | |
3383 | (isfsr_4_new_in[2:0] & {3 {~asi_wr_isfsr[4]}}) | | |
3384 | (isfsr_4[2:0] & ~{3 {| {asi_wr_isfsr[4], isfsr_4_new_in[2:0]}}}) | | |
3385 | (asi_wr_data[2:0] & {3 { asi_wr_isfsr[4]}}) ; | |
3386 | assign isfsr_3_in[2:0] = | |
3387 | (isfsr_3_new_in[2:0] & {3 {~asi_wr_isfsr[3]}}) | | |
3388 | (isfsr_3[2:0] & ~{3 {| {asi_wr_isfsr[3], isfsr_3_new_in[2:0]}}}) | | |
3389 | (asi_wr_data[2:0] & {3 { asi_wr_isfsr[3]}}) ; | |
3390 | assign isfsr_2_in[2:0] = | |
3391 | (isfsr_2_new_in[2:0] & {3 {~asi_wr_isfsr[2]}}) | | |
3392 | (isfsr_2[2:0] & ~{3 {| {asi_wr_isfsr[2], isfsr_2_new_in[2:0]}}}) | | |
3393 | (asi_wr_data[2:0] & {3 { asi_wr_isfsr[2]}}) ; | |
3394 | assign isfsr_1_in[2:0] = | |
3395 | (isfsr_1_new_in[2:0] & {3 {~asi_wr_isfsr[1]}}) | | |
3396 | (isfsr_1[2:0] & ~{3 {| {asi_wr_isfsr[1], isfsr_1_new_in[2:0]}}}) | | |
3397 | (asi_wr_data[2:0] & {3 { asi_wr_isfsr[1]}}) ; | |
3398 | assign isfsr_0_in[2:0] = | |
3399 | (isfsr_0_new_in[2:0] & {3 {~asi_wr_isfsr[0]}}) | | |
3400 | (isfsr_0[2:0] & ~{3 {| {asi_wr_isfsr[0], isfsr_0_new_in[2:0]}}}) | | |
3401 | (asi_wr_data[2:0] & {3 { asi_wr_isfsr[0]}}) ; | |
3402 | ||
3403 | assign precise_i_error[7:0] = | |
3404 | { | {pipe_isfsr_7[2:0], m_isfsr_7[2:0]}, | |
3405 | | {pipe_isfsr_6[2:0], m_isfsr_6[2:0]}, | |
3406 | | {pipe_isfsr_5[2:0], m_isfsr_5[2:0]}, | |
3407 | | {pipe_isfsr_4[2:0], m_isfsr_4[2:0]}, | |
3408 | | {pipe_isfsr_3[2:0], m_isfsr_3[2:0]}, | |
3409 | | {pipe_isfsr_2[2:0], m_isfsr_2[2:0]}, | |
3410 | | {pipe_isfsr_1[2:0], m_isfsr_1[2:0]}, | |
3411 | | {pipe_isfsr_0[2:0], m_isfsr_0[2:0]} }; | |
3412 | ||
3413 | ||
3414 | tlu_ras_ctl_msff_ctl_macro__width_3 isfsr_7_lat ( | |
3415 | .scan_in(isfsr_7_lat_wmr_scanin), | |
3416 | .scan_out(isfsr_7_lat_wmr_scanout), | |
3417 | .siclk(spc_aclk_wmr), | |
3418 | .din (isfsr_7_in [2:0] ), | |
3419 | .dout (isfsr_7 [2:0] ), | |
3420 | .l1clk(l1clk), | |
3421 | .soclk(soclk) | |
3422 | ); | |
3423 | ||
3424 | tlu_ras_ctl_msff_ctl_macro__width_3 isfsr_6_lat ( | |
3425 | .scan_in(isfsr_6_lat_wmr_scanin), | |
3426 | .scan_out(isfsr_6_lat_wmr_scanout), | |
3427 | .siclk(spc_aclk_wmr), | |
3428 | .din (isfsr_6_in [2:0] ), | |
3429 | .dout (isfsr_6 [2:0] ), | |
3430 | .l1clk(l1clk), | |
3431 | .soclk(soclk) | |
3432 | ); | |
3433 | ||
3434 | tlu_ras_ctl_msff_ctl_macro__width_3 isfsr_5_lat ( | |
3435 | .scan_in(isfsr_5_lat_wmr_scanin), | |
3436 | .scan_out(isfsr_5_lat_wmr_scanout), | |
3437 | .siclk(spc_aclk_wmr), | |
3438 | .din (isfsr_5_in [2:0] ), | |
3439 | .dout (isfsr_5 [2:0] ), | |
3440 | .l1clk(l1clk), | |
3441 | .soclk(soclk) | |
3442 | ); | |
3443 | ||
3444 | tlu_ras_ctl_msff_ctl_macro__width_3 isfsr_4_lat ( | |
3445 | .scan_in(isfsr_4_lat_wmr_scanin), | |
3446 | .scan_out(isfsr_4_lat_wmr_scanout), | |
3447 | .siclk(spc_aclk_wmr), | |
3448 | .din (isfsr_4_in [2:0] ), | |
3449 | .dout (isfsr_4 [2:0] ), | |
3450 | .l1clk(l1clk), | |
3451 | .soclk(soclk) | |
3452 | ); | |
3453 | ||
3454 | tlu_ras_ctl_msff_ctl_macro__width_3 isfsr_3_lat ( | |
3455 | .scan_in(isfsr_3_lat_wmr_scanin), | |
3456 | .scan_out(isfsr_3_lat_wmr_scanout), | |
3457 | .siclk(spc_aclk_wmr), | |
3458 | .din (isfsr_3_in [2:0] ), | |
3459 | .dout (isfsr_3 [2:0] ), | |
3460 | .l1clk(l1clk), | |
3461 | .soclk(soclk) | |
3462 | ); | |
3463 | ||
3464 | tlu_ras_ctl_msff_ctl_macro__width_3 isfsr_2_lat ( | |
3465 | .scan_in(isfsr_2_lat_wmr_scanin), | |
3466 | .scan_out(isfsr_2_lat_wmr_scanout), | |
3467 | .siclk(spc_aclk_wmr), | |
3468 | .din (isfsr_2_in [2:0] ), | |
3469 | .dout (isfsr_2 [2:0] ), | |
3470 | .l1clk(l1clk), | |
3471 | .soclk(soclk) | |
3472 | ); | |
3473 | ||
3474 | tlu_ras_ctl_msff_ctl_macro__width_3 isfsr_1_lat ( | |
3475 | .scan_in(isfsr_1_lat_wmr_scanin), | |
3476 | .scan_out(isfsr_1_lat_wmr_scanout), | |
3477 | .siclk(spc_aclk_wmr), | |
3478 | .din (isfsr_1_in [2:0] ), | |
3479 | .dout (isfsr_1 [2:0] ), | |
3480 | .l1clk(l1clk), | |
3481 | .soclk(soclk) | |
3482 | ); | |
3483 | ||
3484 | tlu_ras_ctl_msff_ctl_macro__width_3 isfsr_0_lat ( | |
3485 | .scan_in(isfsr_0_lat_wmr_scanin), | |
3486 | .scan_out(isfsr_0_lat_wmr_scanout), | |
3487 | .siclk(spc_aclk_wmr), | |
3488 | .din (isfsr_0_in [2:0] ), | |
3489 | .dout (isfsr_0 [2:0] ), | |
3490 | .l1clk(l1clk), | |
3491 | .soclk(soclk) | |
3492 | ); | |
3493 | ||
3494 | ||
3495 | ||
3496 | ////////////////////////////////////////////////////////////////////////////// | |
3497 | // | |
3498 | // Instantiate DSFSRs | |
3499 | // | |
3500 | ||
3501 | assign dsfsr_7_new_in[3:0] = | |
3502 | {1'b0, pipe_dsfsr_7[2:0]} | {1'b0, m_dsfsr_7[2:0]} | | |
3503 | a_dsfsr_7[3:0] | t_dsfsr_7[3:0] | {{1 {1'b0}}, l_dsfsr_7[2:0]} | | |
3504 | {1'b0, s_dsfsr_7[2:0]} ; | |
3505 | assign dsfsr_6_new_in[3:0] = | |
3506 | {1'b0, pipe_dsfsr_6[2:0]} | {1'b0, m_dsfsr_6[2:0]} | | |
3507 | a_dsfsr_6[3:0] | t_dsfsr_6[3:0] | {{1 {1'b0}}, l_dsfsr_6[2:0]} | | |
3508 | {1'b0, s_dsfsr_6[2:0]} ; | |
3509 | assign dsfsr_5_new_in[3:0] = | |
3510 | {1'b0, pipe_dsfsr_5[2:0]} | {1'b0, m_dsfsr_5[2:0]} | | |
3511 | a_dsfsr_5[3:0] | t_dsfsr_5[3:0] | {{1 {1'b0}}, l_dsfsr_5[2:0]} | | |
3512 | {1'b0, s_dsfsr_5[2:0]} ; | |
3513 | assign dsfsr_4_new_in[3:0] = | |
3514 | {1'b0, pipe_dsfsr_4[2:0]} | {1'b0, m_dsfsr_4[2:0]} | | |
3515 | a_dsfsr_4[3:0] | t_dsfsr_4[3:0] | {{1 {1'b0}}, l_dsfsr_4[2:0]} | | |
3516 | {1'b0, s_dsfsr_4[2:0]} ; | |
3517 | assign dsfsr_3_new_in[3:0] = | |
3518 | {1'b0, pipe_dsfsr_3[2:0]} | {1'b0, m_dsfsr_3[2:0]} | | |
3519 | a_dsfsr_3[3:0] | t_dsfsr_3[3:0] | {{1 {1'b0}}, l_dsfsr_3[2:0]} | | |
3520 | {1'b0, s_dsfsr_3[2:0]} ; | |
3521 | assign dsfsr_2_new_in[3:0] = | |
3522 | {1'b0, pipe_dsfsr_2[2:0]} | {1'b0, m_dsfsr_2[2:0]} | | |
3523 | a_dsfsr_2[3:0] | t_dsfsr_2[3:0] | {{1 {1'b0}}, l_dsfsr_2[2:0]} | | |
3524 | {1'b0, s_dsfsr_2[2:0]} ; | |
3525 | assign dsfsr_1_new_in[3:0] = | |
3526 | {1'b0, pipe_dsfsr_1[2:0]} | {1'b0, m_dsfsr_1[2:0]} | | |
3527 | a_dsfsr_1[3:0] | t_dsfsr_1[3:0] | {{1 {1'b0}}, l_dsfsr_1[2:0]} | | |
3528 | {1'b0, s_dsfsr_1[2:0]} ; | |
3529 | assign dsfsr_0_new_in[3:0] = | |
3530 | {1'b0, pipe_dsfsr_0[2:0]} | {1'b0, m_dsfsr_0[2:0]} | | |
3531 | a_dsfsr_0[3:0] | t_dsfsr_0[3:0] | {{1 {1'b0}}, l_dsfsr_0[2:0]} | | |
3532 | {1'b0, s_dsfsr_0[2:0]} ; | |
3533 | ||
3534 | assign dsfsr_7_in[3:0] = | |
3535 | (dsfsr_7_new_in[3:0] & {4 {~asi_wr_dsfsr[7]}}) | | |
3536 | (dsfsr_7[3:0] & ~{4 {| {asi_wr_dsfsr[7], dsfsr_7_new_in[3:0]}}}) | | |
3537 | (asi_wr_data[3:0] & {4 { asi_wr_dsfsr[7]}}) ; | |
3538 | assign dsfsr_6_in[3:0] = | |
3539 | (dsfsr_6_new_in[3:0] & {4 {~asi_wr_dsfsr[6]}}) | | |
3540 | (dsfsr_6[3:0] & ~{4 {| {asi_wr_dsfsr[6], dsfsr_6_new_in[3:0]}}}) | | |
3541 | (asi_wr_data[3:0] & {4 { asi_wr_dsfsr[6]}}) ; | |
3542 | assign dsfsr_5_in[3:0] = | |
3543 | (dsfsr_5_new_in[3:0] & {4 {~asi_wr_dsfsr[5]}}) | | |
3544 | (dsfsr_5[3:0] & ~{4 {| {asi_wr_dsfsr[5], dsfsr_5_new_in[3:0]}}}) | | |
3545 | (asi_wr_data[3:0] & {4 { asi_wr_dsfsr[5]}}) ; | |
3546 | assign dsfsr_4_in[3:0] = | |
3547 | (dsfsr_4_new_in[3:0] & {4 {~asi_wr_dsfsr[4]}}) | | |
3548 | (dsfsr_4[3:0] & ~{4 {| {asi_wr_dsfsr[4], dsfsr_4_new_in[3:0]}}}) | | |
3549 | (asi_wr_data[3:0] & {4 { asi_wr_dsfsr[4]}}) ; | |
3550 | assign dsfsr_3_in[3:0] = | |
3551 | (dsfsr_3_new_in[3:0] & {4 {~asi_wr_dsfsr[3]}}) | | |
3552 | (dsfsr_3[3:0] & ~{4 {| {asi_wr_dsfsr[3], dsfsr_3_new_in[3:0]}}}) | | |
3553 | (asi_wr_data[3:0] & {4 { asi_wr_dsfsr[3]}}) ; | |
3554 | assign dsfsr_2_in[3:0] = | |
3555 | (dsfsr_2_new_in[3:0] & {4 {~asi_wr_dsfsr[2]}}) | | |
3556 | (dsfsr_2[3:0] & ~{4 {| {asi_wr_dsfsr[2], dsfsr_2_new_in[3:0]}}}) | | |
3557 | (asi_wr_data[3:0] & {4 { asi_wr_dsfsr[2]}}) ; | |
3558 | assign dsfsr_1_in[3:0] = | |
3559 | (dsfsr_1_new_in[3:0] & {4 {~asi_wr_dsfsr[1]}}) | | |
3560 | (dsfsr_1[3:0] & ~{4 {| {asi_wr_dsfsr[1], dsfsr_1_new_in[3:0]}}}) | | |
3561 | (asi_wr_data[3:0] & {4 { asi_wr_dsfsr[1]}}) ; | |
3562 | assign dsfsr_0_in[3:0] = | |
3563 | (dsfsr_0_new_in[3:0] & {4 {~asi_wr_dsfsr[0]}}) | | |
3564 | (dsfsr_0[3:0] & ~{4 {| {asi_wr_dsfsr[0], dsfsr_0_new_in[3:0]}}}) | | |
3565 | (asi_wr_data[3:0] & {4 { asi_wr_dsfsr[0]}}) ; | |
3566 | ||
3567 | assign precise_d_error[7:0] = | |
3568 | { | {pipe_dsfsr_7[2:0], m_dsfsr_7[2:0], a_dsfsr_7[3:0], | |
3569 | t_dsfsr_7[3:0], l_dsfsr_7[2:0], s_dsfsr_7[2:0]}, | |
3570 | | {pipe_dsfsr_6[2:0], m_dsfsr_6[2:0], a_dsfsr_6[3:0], | |
3571 | t_dsfsr_6[3:0], l_dsfsr_6[2:0], s_dsfsr_6[2:0]}, | |
3572 | | {pipe_dsfsr_5[2:0], m_dsfsr_5[2:0], a_dsfsr_5[3:0], | |
3573 | t_dsfsr_5[3:0], l_dsfsr_5[2:0], s_dsfsr_5[2:0]}, | |
3574 | | {pipe_dsfsr_4[2:0], m_dsfsr_4[2:0], a_dsfsr_4[3:0], | |
3575 | t_dsfsr_4[3:0], l_dsfsr_4[2:0], s_dsfsr_4[2:0]}, | |
3576 | | {pipe_dsfsr_3[2:0], m_dsfsr_3[2:0], a_dsfsr_3[3:0], | |
3577 | t_dsfsr_3[3:0], l_dsfsr_3[2:0], s_dsfsr_3[2:0]}, | |
3578 | | {pipe_dsfsr_2[2:0], m_dsfsr_2[2:0], a_dsfsr_2[3:0], | |
3579 | t_dsfsr_2[3:0], l_dsfsr_2[2:0], s_dsfsr_2[2:0]}, | |
3580 | | {pipe_dsfsr_1[2:0], m_dsfsr_1[2:0], a_dsfsr_1[3:0], | |
3581 | t_dsfsr_1[3:0], l_dsfsr_1[2:0], s_dsfsr_1[2:0]}, | |
3582 | | {pipe_dsfsr_0[2:0], m_dsfsr_0[2:0], a_dsfsr_0[3:0], | |
3583 | t_dsfsr_0[3:0], l_dsfsr_0[2:0], s_dsfsr_0[2:0]}}; | |
3584 | ||
3585 | tlu_ras_ctl_msff_ctl_macro__width_4 dsfsr_7_lat ( | |
3586 | .scan_in(dsfsr_7_lat_wmr_scanin), | |
3587 | .scan_out(dsfsr_7_lat_wmr_scanout), | |
3588 | .siclk(spc_aclk_wmr), | |
3589 | .din (dsfsr_7_in [3:0] ), | |
3590 | .dout (dsfsr_7 [3:0] ), | |
3591 | .l1clk(l1clk), | |
3592 | .soclk(soclk) | |
3593 | ); | |
3594 | ||
3595 | tlu_ras_ctl_msff_ctl_macro__width_4 dsfsr_6_lat ( | |
3596 | .scan_in(dsfsr_6_lat_wmr_scanin), | |
3597 | .scan_out(dsfsr_6_lat_wmr_scanout), | |
3598 | .siclk(spc_aclk_wmr), | |
3599 | .din (dsfsr_6_in [3:0] ), | |
3600 | .dout (dsfsr_6 [3:0] ), | |
3601 | .l1clk(l1clk), | |
3602 | .soclk(soclk) | |
3603 | ); | |
3604 | ||
3605 | tlu_ras_ctl_msff_ctl_macro__width_4 dsfsr_5_lat ( | |
3606 | .scan_in(dsfsr_5_lat_wmr_scanin), | |
3607 | .scan_out(dsfsr_5_lat_wmr_scanout), | |
3608 | .siclk(spc_aclk_wmr), | |
3609 | .din (dsfsr_5_in [3:0] ), | |
3610 | .dout (dsfsr_5 [3:0] ), | |
3611 | .l1clk(l1clk), | |
3612 | .soclk(soclk) | |
3613 | ); | |
3614 | ||
3615 | tlu_ras_ctl_msff_ctl_macro__width_4 dsfsr_4_lat ( | |
3616 | .scan_in(dsfsr_4_lat_wmr_scanin), | |
3617 | .scan_out(dsfsr_4_lat_wmr_scanout), | |
3618 | .siclk(spc_aclk_wmr), | |
3619 | .din (dsfsr_4_in [3:0] ), | |
3620 | .dout (dsfsr_4 [3:0] ), | |
3621 | .l1clk(l1clk), | |
3622 | .soclk(soclk) | |
3623 | ); | |
3624 | ||
3625 | tlu_ras_ctl_msff_ctl_macro__width_4 dsfsr_3_lat ( | |
3626 | .scan_in(dsfsr_3_lat_wmr_scanin), | |
3627 | .scan_out(dsfsr_3_lat_wmr_scanout), | |
3628 | .siclk(spc_aclk_wmr), | |
3629 | .din (dsfsr_3_in [3:0] ), | |
3630 | .dout (dsfsr_3 [3:0] ), | |
3631 | .l1clk(l1clk), | |
3632 | .soclk(soclk) | |
3633 | ); | |
3634 | ||
3635 | tlu_ras_ctl_msff_ctl_macro__width_4 dsfsr_2_lat ( | |
3636 | .scan_in(dsfsr_2_lat_wmr_scanin), | |
3637 | .scan_out(dsfsr_2_lat_wmr_scanout), | |
3638 | .siclk(spc_aclk_wmr), | |
3639 | .din (dsfsr_2_in [3:0] ), | |
3640 | .dout (dsfsr_2 [3:0] ), | |
3641 | .l1clk(l1clk), | |
3642 | .soclk(soclk) | |
3643 | ); | |
3644 | ||
3645 | tlu_ras_ctl_msff_ctl_macro__width_4 dsfsr_1_lat ( | |
3646 | .scan_in(dsfsr_1_lat_wmr_scanin), | |
3647 | .scan_out(dsfsr_1_lat_wmr_scanout), | |
3648 | .siclk(spc_aclk_wmr), | |
3649 | .din (dsfsr_1_in [3:0] ), | |
3650 | .dout (dsfsr_1 [3:0] ), | |
3651 | .l1clk(l1clk), | |
3652 | .soclk(soclk) | |
3653 | ); | |
3654 | ||
3655 | tlu_ras_ctl_msff_ctl_macro__width_4 dsfsr_0_lat ( | |
3656 | .scan_in(dsfsr_0_lat_wmr_scanin), | |
3657 | .scan_out(dsfsr_0_lat_wmr_scanout), | |
3658 | .siclk(spc_aclk_wmr), | |
3659 | .din (dsfsr_0_in [3:0] ), | |
3660 | .dout (dsfsr_0 [3:0] ), | |
3661 | .l1clk(l1clk), | |
3662 | .soclk(soclk) | |
3663 | ); | |
3664 | ||
3665 | ||
3666 | ||
3667 | ////////////////////////////////////////////////////////////////////////////// | |
3668 | // | |
3669 | // ASI reads | |
3670 | // | |
3671 | ||
3672 | tlu_ras_ctl_msff_ctl_macro__width_8 asi_rd_ctl_lat ( | |
3673 | .scan_in(asi_rd_ctl_lat_scanin), | |
3674 | .scan_out(asi_rd_ctl_lat_scanout), | |
3675 | .din ({asi_rd_isfsr , | |
3676 | asi_rd_dsfsr , | |
3677 | asi_rd_dsfar , | |
3678 | asi_rd_desr , | |
3679 | asi_rd_fesr , | |
3680 | asi_rd_tid [2:0]}), | |
3681 | .dout ({rd_isfsr , | |
3682 | rd_dsfsr , | |
3683 | rd_dsfar , | |
3684 | rd_desr , | |
3685 | rd_fesr , | |
3686 | rd_tid [2:0]}), | |
3687 | .l1clk(l1clk), | |
3688 | .siclk(siclk), | |
3689 | .soclk(soclk) | |
3690 | ); | |
3691 | ||
3692 | assign rd_tid_dec[7:0] = | |
3693 | { rd_tid[2] & rd_tid[1] & rd_tid[0], | |
3694 | rd_tid[2] & rd_tid[1] & ~rd_tid[0], | |
3695 | rd_tid[2] & ~rd_tid[1] & rd_tid[0], | |
3696 | rd_tid[2] & ~rd_tid[1] & ~rd_tid[0], | |
3697 | ~rd_tid[2] & rd_tid[1] & rd_tid[0], | |
3698 | ~rd_tid[2] & rd_tid[1] & ~rd_tid[0], | |
3699 | ~rd_tid[2] & ~rd_tid[1] & rd_tid[0], | |
3700 | ~rd_tid[2] & ~rd_tid[1] & ~rd_tid[0]}; | |
3701 | ||
3702 | assign rd_isfsr_dec[7:0] = | |
3703 | {8 {rd_isfsr}} & rd_tid_dec[7:0]; | |
3704 | ||
3705 | assign rd_dsfsr_dec[7:0] = | |
3706 | {8 {rd_dsfsr}} & rd_tid_dec[7:0]; | |
3707 | ||
3708 | assign rd_desr_dec[7:0] = | |
3709 | {8 {rd_desr}} & rd_tid_dec[7:0]; | |
3710 | ||
3711 | assign ras_rd_dsfar[7:0] = | |
3712 | {8 {rd_dsfar}} & rd_tid_dec[7:0]; | |
3713 | ||
3714 | assign ras_rd_desr[7:0] = | |
3715 | {8 {rd_desr}} & rd_tid_dec[7:0]; | |
3716 | ||
3717 | assign ras_rd_fesr[7:0] = | |
3718 | {8 {rd_fesr}} & rd_tid_dec[7:0]; | |
3719 | ||
3720 | assign ras_asi_data[3:0] = | |
3721 | ({1'b0, isfsr_7[2:0]} & {4 {rd_isfsr_dec[7]}}) | | |
3722 | ({1'b0, isfsr_6[2:0]} & {4 {rd_isfsr_dec[6]}}) | | |
3723 | ({1'b0, isfsr_5[2:0]} & {4 {rd_isfsr_dec[5]}}) | | |
3724 | ({1'b0, isfsr_4[2:0]} & {4 {rd_isfsr_dec[4]}}) | | |
3725 | ({1'b0, isfsr_3[2:0]} & {4 {rd_isfsr_dec[3]}}) | | |
3726 | ({1'b0, isfsr_2[2:0]} & {4 {rd_isfsr_dec[2]}}) | | |
3727 | ({1'b0, isfsr_1[2:0]} & {4 {rd_isfsr_dec[1]}}) | | |
3728 | ({1'b0, isfsr_0[2:0]} & {4 {rd_isfsr_dec[0]}}) | | |
3729 | ( dsfsr_7[3:0] & {4 {rd_dsfsr_dec[7]}}) | | |
3730 | ( dsfsr_6[3:0] & {4 {rd_dsfsr_dec[6]}}) | | |
3731 | ( dsfsr_5[3:0] & {4 {rd_dsfsr_dec[5]}}) | | |
3732 | ( dsfsr_4[3:0] & {4 {rd_dsfsr_dec[4]}}) | | |
3733 | ( dsfsr_3[3:0] & {4 {rd_dsfsr_dec[3]}}) | | |
3734 | ( dsfsr_2[3:0] & {4 {rd_dsfsr_dec[2]}}) | | |
3735 | ( dsfsr_1[3:0] & {4 {rd_dsfsr_dec[1]}}) | | |
3736 | ( dsfsr_0[3:0] & {4 {rd_dsfsr_dec[0]}}) ; | |
3737 | ||
3738 | ||
3739 | ||
3740 | ////////////////////////////////////////////////////////////////////////////// | |
3741 | // | |
3742 | // Prepare DSFAR data | |
3743 | // | |
3744 | ||
3745 | assign ras_dsfar_7[19:0] = | |
3746 | pipe_dsfar_7[19:0] | | |
3747 | {{17 {1'b0}}, m_dsfar_7[2:0]} | | |
3748 | {{ 9 {1'b0}}, a_dsfar_7[10:0]} | | |
3749 | {{11 {1'b0}}, l_dsfar_7[8:0]} | | |
3750 | {{17 {1'b0}}, s_dsfar_7[2:0]} ; | |
3751 | assign ras_dsfar_6[19:0] = | |
3752 | pipe_dsfar_6[19:0] | | |
3753 | {{17 {1'b0}}, m_dsfar_6[2:0]} | | |
3754 | {{ 9 {1'b0}}, a_dsfar_6[10:0]} | | |
3755 | {{11 {1'b0}}, l_dsfar_6[8:0]} | | |
3756 | {{17 {1'b0}}, s_dsfar_6[2:0]} ; | |
3757 | assign ras_dsfar_5[19:0] = | |
3758 | pipe_dsfar_5[19:0] | | |
3759 | {{17 {1'b0}}, m_dsfar_5[2:0]} | | |
3760 | {{ 9 {1'b0}}, a_dsfar_5[10:0]} | | |
3761 | {{11 {1'b0}}, l_dsfar_5[8:0]} | | |
3762 | {{17 {1'b0}}, s_dsfar_5[2:0]} ; | |
3763 | assign ras_dsfar_4[19:0] = | |
3764 | pipe_dsfar_4[19:0] | | |
3765 | {{17 {1'b0}}, m_dsfar_4[2:0]} | | |
3766 | {{ 9 {1'b0}}, a_dsfar_4[10:0]} | | |
3767 | {{11 {1'b0}}, l_dsfar_4[8:0]} | | |
3768 | {{17 {1'b0}}, s_dsfar_4[2:0]} ; | |
3769 | assign ras_dsfar_3[19:0] = | |
3770 | pipe_dsfar_3[19:0] | | |
3771 | {{17 {1'b0}}, m_dsfar_3[2:0]} | | |
3772 | {{ 9 {1'b0}}, a_dsfar_3[10:0]} | | |
3773 | {{11 {1'b0}}, l_dsfar_3[8:0]} | | |
3774 | {{17 {1'b0}}, s_dsfar_3[2:0]} ; | |
3775 | assign ras_dsfar_2[19:0] = | |
3776 | pipe_dsfar_2[19:0] | | |
3777 | {{17 {1'b0}}, m_dsfar_2[2:0]} | | |
3778 | {{ 9 {1'b0}}, a_dsfar_2[10:0]} | | |
3779 | {{11 {1'b0}}, l_dsfar_2[8:0]} | | |
3780 | {{17 {1'b0}}, s_dsfar_2[2:0]} ; | |
3781 | assign ras_dsfar_1[19:0] = | |
3782 | pipe_dsfar_1[19:0] | | |
3783 | {{17 {1'b0}}, m_dsfar_1[2:0]} | | |
3784 | {{ 9 {1'b0}}, a_dsfar_1[10:0]} | | |
3785 | {{11 {1'b0}}, l_dsfar_1[8:0]} | | |
3786 | {{17 {1'b0}}, s_dsfar_1[2:0]} ; | |
3787 | assign ras_dsfar_0[19:0] = | |
3788 | pipe_dsfar_0[19:0] | | |
3789 | {{17 {1'b0}}, m_dsfar_0[2:0]} | | |
3790 | {{ 9 {1'b0}}, a_dsfar_0[10:0]} | | |
3791 | {{11 {1'b0}}, l_dsfar_0[8:0]} | | |
3792 | {{17 {1'b0}}, s_dsfar_0[2:0]} ; | |
3793 | ||
3794 | assign ras_dsfar_sel_ras[7:0] = | |
3795 | {| {dsfsr_7_new_in[3:0], itmu_7, dtmu_7}, | |
3796 | | {dsfsr_6_new_in[3:0], itmu_6, dtmu_6}, | |
3797 | | {dsfsr_5_new_in[3:0], itmu_5, dtmu_5}, | |
3798 | | {dsfsr_4_new_in[3:0], itmu_4, dtmu_4}, | |
3799 | | {dsfsr_3_new_in[3:0], itmu_3, dtmu_3}, | |
3800 | | {dsfsr_2_new_in[3:0], itmu_2, dtmu_2}, | |
3801 | | {dsfsr_1_new_in[3:0], itmu_1, dtmu_1}, | |
3802 | | {dsfsr_0_new_in[3:0], itmu_0, dtmu_0}} & | |
3803 | ~dsfar_sel_lsu_va_for_error[7:0]; | |
3804 | ||
3805 | ||
3806 | ////////////////////////////////////////////////////////////////////////////// | |
3807 | // | |
3808 | // Handle disrupting errors | |
3809 | // | |
3810 | ||
3811 | // Data cache errors -- long latency and implemented as precise but | |
3812 | // technically disrupting | |
3813 | // | |
3814 | // DESR | |
3815 | // dcvp 0101 | |
3816 | // dctp 0110 | |
3817 | // dctm 0111 | |
3818 | // dcdp 1000 | |
3819 | // All these have S = 0 | |
3820 | ||
3821 | tlu_ras_ctl_msff_ctl_macro__width_1 dcvp_lat ( | |
3822 | .scan_in(dcvp_lat_scanin), | |
3823 | .scan_out(dcvp_lat_scanout), | |
3824 | .din (lsu_dcvp_err_g ), | |
3825 | .dout (dcvp ), | |
3826 | .l1clk(l1clk), | |
3827 | .siclk(siclk), | |
3828 | .soclk(soclk) | |
3829 | ); | |
3830 | ||
3831 | tlu_ras_ctl_msff_ctl_macro__width_1 dctp_lat ( | |
3832 | .scan_in(dctp_lat_scanin), | |
3833 | .scan_out(dctp_lat_scanout), | |
3834 | .din (lsu_dctp_err_g ), | |
3835 | .dout (dctp ), | |
3836 | .l1clk(l1clk), | |
3837 | .siclk(siclk), | |
3838 | .soclk(soclk) | |
3839 | ); | |
3840 | ||
3841 | tlu_ras_ctl_msff_ctl_macro__width_1 dctm_lat ( | |
3842 | .scan_in(dctm_lat_scanin), | |
3843 | .scan_out(dctm_lat_scanout), | |
3844 | .din (lsu_dcmh_err_g ), | |
3845 | .dout (dctm ), | |
3846 | .l1clk(l1clk), | |
3847 | .siclk(siclk), | |
3848 | .soclk(soclk) | |
3849 | ); | |
3850 | ||
3851 | tlu_ras_ctl_msff_ctl_macro__width_1 dcdp_lat ( | |
3852 | .scan_in(dcdp_lat_scanin), | |
3853 | .scan_out(dcdp_lat_scanout), | |
3854 | .din (lsu_dcdp_err_g ), | |
3855 | .dout (dcdp ), | |
3856 | .l1clk(l1clk), | |
3857 | .siclk(siclk), | |
3858 | .soclk(soclk) | |
3859 | ); | |
3860 | ||
3861 | assign d_dec_tid[7:0] = | |
3862 | { l_tid[2] & l_tid[1] & l_tid[0], | |
3863 | l_tid[2] & l_tid[1] & ~l_tid[0], | |
3864 | l_tid[2] & ~l_tid[1] & l_tid[0], | |
3865 | l_tid[2] & ~l_tid[1] & ~l_tid[0], | |
3866 | ~l_tid[2] & l_tid[1] & l_tid[0], | |
3867 | ~l_tid[2] & l_tid[1] & ~l_tid[0], | |
3868 | ~l_tid[2] & ~l_tid[1] & l_tid[0], | |
3869 | ~l_tid[2] & ~l_tid[1] & ~l_tid[0]} & {8 {dcvp | dctp | dctm | dcdp}}; | |
3870 | ||
3871 | assign d_desr_et[3:0] = | |
3872 | ({4 {dcvp}} & 4'b0101) | | |
3873 | ({4 {dctp}} & 4'b0110) | | |
3874 | ({4 {dctm}} & 4'b0111) | | |
3875 | ({4 {dcdp}} & 4'b1000) ; | |
3876 | ||
3877 | assign d_desr_et_7[3:0] = | |
3878 | d_desr_et[3:0] & {4 {d_dec_tid[7]}}; | |
3879 | assign d_desr_et_6[3:0] = | |
3880 | d_desr_et[3:0] & {4 {d_dec_tid[6]}}; | |
3881 | assign d_desr_et_5[3:0] = | |
3882 | d_desr_et[3:0] & {4 {d_dec_tid[5]}}; | |
3883 | assign d_desr_et_4[3:0] = | |
3884 | d_desr_et[3:0] & {4 {d_dec_tid[4]}}; | |
3885 | assign d_desr_et_3[3:0] = | |
3886 | d_desr_et[3:0] & {4 {d_dec_tid[3]}}; | |
3887 | assign d_desr_et_2[3:0] = | |
3888 | d_desr_et[3:0] & {4 {d_dec_tid[2]}}; | |
3889 | assign d_desr_et_1[3:0] = | |
3890 | d_desr_et[3:0] & {4 {d_dec_tid[1]}}; | |
3891 | assign d_desr_et_0[3:0] = | |
3892 | d_desr_et[3:0] & {4 {d_dec_tid[0]}}; | |
3893 | ||
3894 | assign d_desr_ea_7[8:0] = | |
3895 | l_dsfar[8:0] & {9 {d_dec_tid[7]}}; | |
3896 | assign d_desr_ea_6[8:0] = | |
3897 | l_dsfar[8:0] & {9 {d_dec_tid[6]}}; | |
3898 | assign d_desr_ea_5[8:0] = | |
3899 | l_dsfar[8:0] & {9 {d_dec_tid[5]}}; | |
3900 | assign d_desr_ea_4[8:0] = | |
3901 | l_dsfar[8:0] & {9 {d_dec_tid[4]}}; | |
3902 | assign d_desr_ea_3[8:0] = | |
3903 | l_dsfar[8:0] & {9 {d_dec_tid[3]}}; | |
3904 | assign d_desr_ea_2[8:0] = | |
3905 | l_dsfar[8:0] & {9 {d_dec_tid[2]}}; | |
3906 | assign d_desr_ea_1[8:0] = | |
3907 | l_dsfar[8:0] & {9 {d_dec_tid[1]}}; | |
3908 | assign d_desr_ea_0[8:0] = | |
3909 | l_dsfar[8:0] & {9 {d_dec_tid[0]}}; | |
3910 | ||
3911 | ||
3912 | // L2 and SOC errors | |
3913 | // | |
3914 | // DESR | |
3915 | // l2ch 01001 | |
3916 | // l2u 10000 | |
3917 | // l2nd 10001 | |
3918 | // soc 01011 | |
3919 | // sou 10011 | |
3920 | // l2cs 10100 | |
3921 | // l2ch and soc has S = 0, others have S = 1 | |
3922 | ||
3923 | tlu_ras_ctl_msff_ctl_macro__width_8 cxi_lat ( | |
3924 | .scan_in(cxi_lat_scanin), | |
3925 | .scan_out(cxi_lat_scanout), | |
3926 | .din ({cxi_l2_err , | |
3927 | cxi_soc_err , | |
3928 | cxi_l2_soc_err_type [1:0], | |
3929 | cxi_l2_soc_tid [2:0], | |
3930 | cxi_l2_soc_sre }), | |
3931 | .dout ({l2_err , | |
3932 | soc_err , | |
3933 | c_l2_soc_err_type [1:0], | |
3934 | c_l2_soc_tid [2:0], | |
3935 | c_l2_soc_sre }), | |
3936 | .l1clk(l1clk), | |
3937 | .siclk(siclk), | |
3938 | .soclk(soclk) | |
3939 | ); | |
3940 | ||
3941 | assign c_l2_soc_dec_tid[7:0] = | |
3942 | { c_l2_soc_tid[2] & c_l2_soc_tid[1] & c_l2_soc_tid[0], | |
3943 | c_l2_soc_tid[2] & c_l2_soc_tid[1] & ~c_l2_soc_tid[0], | |
3944 | c_l2_soc_tid[2] & ~c_l2_soc_tid[1] & c_l2_soc_tid[0], | |
3945 | c_l2_soc_tid[2] & ~c_l2_soc_tid[1] & ~c_l2_soc_tid[0], | |
3946 | ~c_l2_soc_tid[2] & c_l2_soc_tid[1] & c_l2_soc_tid[0], | |
3947 | ~c_l2_soc_tid[2] & c_l2_soc_tid[1] & ~c_l2_soc_tid[0], | |
3948 | ~c_l2_soc_tid[2] & ~c_l2_soc_tid[1] & c_l2_soc_tid[0], | |
3949 | ~c_l2_soc_tid[2] & ~c_l2_soc_tid[1] & ~c_l2_soc_tid[0]}; | |
3950 | ||
3951 | assign c_l2_err[7:0] = | |
3952 | {8 {l2_err}} & c_l2_soc_dec_tid[7:0]; | |
3953 | ||
3954 | assign c_soc_err[7:0] = | |
3955 | {8 {soc_err}} & c_l2_soc_dec_tid[7:0]; | |
3956 | ||
3957 | assign l2_dec_tid[7:0] = | |
3958 | c_l2_err[7:0] | c_soc_err[7:0]; | |
3959 | ||
3960 | assign l2ch = | |
3961 | (c_l2_soc_err_type[1:0] == 2'b01) & l2_err & ~c_l2_soc_sre; | |
3962 | assign l2cs = | |
3963 | (c_l2_soc_err_type[1:0] == 2'b01) & l2_err & c_l2_soc_sre; | |
3964 | assign soc = | |
3965 | (c_l2_soc_err_type[1:0] == 2'b01) & soc_err; | |
3966 | assign l2u = | |
3967 | (c_l2_soc_err_type[1:0] == 2'b10) & l2_err; | |
3968 | assign sou = | |
3969 | (c_l2_soc_err_type[1:0] == 2'b10) & soc_err; | |
3970 | assign l2nd = | |
3971 | (c_l2_soc_err_type[1:0] == 2'b11) & l2_err; | |
3972 | ||
3973 | assign l2_desr_et[5:0] = | |
3974 | ({6 {l2ch}} & 6'b001001) | | |
3975 | ({6 {l2u }} & 6'b110000) | | |
3976 | ({6 {l2nd}} & 6'b110001) | | |
3977 | ({6 {soc }} & 6'b001011) | | |
3978 | ({6 {sou }} & 6'b110011) | | |
3979 | ({6 {l2cs}} & 6'b110100) ; | |
3980 | ||
3981 | assign l2_desr_et_7[5:0] = | |
3982 | l2_desr_et[5:0] & {6 {l2_dec_tid[7]}}; | |
3983 | assign l2_desr_et_6[5:0] = | |
3984 | l2_desr_et[5:0] & {6 {l2_dec_tid[6]}}; | |
3985 | assign l2_desr_et_5[5:0] = | |
3986 | l2_desr_et[5:0] & {6 {l2_dec_tid[5]}}; | |
3987 | assign l2_desr_et_4[5:0] = | |
3988 | l2_desr_et[5:0] & {6 {l2_dec_tid[4]}}; | |
3989 | assign l2_desr_et_3[5:0] = | |
3990 | l2_desr_et[5:0] & {6 {l2_dec_tid[3]}}; | |
3991 | assign l2_desr_et_2[5:0] = | |
3992 | l2_desr_et[5:0] & {6 {l2_dec_tid[2]}}; | |
3993 | assign l2_desr_et_1[5:0] = | |
3994 | l2_desr_et[5:0] & {6 {l2_dec_tid[1]}}; | |
3995 | assign l2_desr_et_0[5:0] = | |
3996 | l2_desr_et[5:0] & {6 {l2_dec_tid[0]}}; | |
3997 | ||
3998 | // No data stored in DESR.EA for L2 or SOC errors | |
3999 | ||
4000 | ||
4001 | ||
4002 | // Store buffer errors | |
4003 | // | |
4004 | // DESR | |
4005 | // sbdpc 01010 | |
4006 | // sbdpu 00110 | |
4007 | // sbdpu has S = 1 | |
4008 | ||
4009 | tlu_ras_ctl_msff_ctl_macro__width_1 sbdpc_lat ( | |
4010 | .scan_in(sbdpc_lat_scanin), | |
4011 | .scan_out(sbdpc_lat_scanout), | |
4012 | .din (lsu_sbdpc_err_g ), | |
4013 | .dout (sbdpc ), | |
4014 | .l1clk(l1clk), | |
4015 | .siclk(siclk), | |
4016 | .soclk(soclk) | |
4017 | ); | |
4018 | ||
4019 | tlu_ras_ctl_msff_ctl_macro__width_1 sbdpu_lat ( | |
4020 | .scan_in(sbdpu_lat_scanin), | |
4021 | .scan_out(sbdpu_lat_scanout), | |
4022 | .din (lsu_sbdpu_err_g ), | |
4023 | .dout (sbdpu ), | |
4024 | .l1clk(l1clk), | |
4025 | .siclk(siclk), | |
4026 | .soclk(soclk) | |
4027 | ); | |
4028 | ||
4029 | assign sb_dec_tid[7:0] = | |
4030 | {s_tid[2:0] == 3'b111, | |
4031 | s_tid[2:0] == 3'b110, | |
4032 | s_tid[2:0] == 3'b101, | |
4033 | s_tid[2:0] == 3'b100, | |
4034 | s_tid[2:0] == 3'b011, | |
4035 | s_tid[2:0] == 3'b010, | |
4036 | s_tid[2:0] == 3'b001, | |
4037 | s_tid[2:0] == 3'b000} & {8 {sbdpc | sbdpu}}; | |
4038 | ||
4039 | assign s_desr_et[5:0] = | |
4040 | {sbdpu, 1'b0, sbdpc, sbdpu, sbdpu | sbdpc, 1'b0}; | |
4041 | ||
4042 | assign s_desr_et_7[5:0] = | |
4043 | s_desr_et[5:0] & {6 {sb_dec_tid[7]}}; | |
4044 | assign s_desr_et_6[5:0] = | |
4045 | s_desr_et[5:0] & {6 {sb_dec_tid[6]}}; | |
4046 | assign s_desr_et_5[5:0] = | |
4047 | s_desr_et[5:0] & {6 {sb_dec_tid[5]}}; | |
4048 | assign s_desr_et_4[5:0] = | |
4049 | s_desr_et[5:0] & {6 {sb_dec_tid[4]}}; | |
4050 | assign s_desr_et_3[5:0] = | |
4051 | s_desr_et[5:0] & {6 {sb_dec_tid[3]}}; | |
4052 | assign s_desr_et_2[5:0] = | |
4053 | s_desr_et[5:0] & {6 {sb_dec_tid[2]}}; | |
4054 | assign s_desr_et_1[5:0] = | |
4055 | s_desr_et[5:0] & {6 {sb_dec_tid[1]}}; | |
4056 | assign s_desr_et_0[5:0] = | |
4057 | s_desr_et[5:0] & {6 {sb_dec_tid[0]}}; | |
4058 | ||
4059 | assign s_desr_ea_7[2:0] = | |
4060 | s_dsfar[2:0] & {3 {sb_dec_tid[7]}}; | |
4061 | assign s_desr_ea_6[2:0] = | |
4062 | s_dsfar[2:0] & {3 {sb_dec_tid[6]}}; | |
4063 | assign s_desr_ea_5[2:0] = | |
4064 | s_dsfar[2:0] & {3 {sb_dec_tid[5]}}; | |
4065 | assign s_desr_ea_4[2:0] = | |
4066 | s_dsfar[2:0] & {3 {sb_dec_tid[4]}}; | |
4067 | assign s_desr_ea_3[2:0] = | |
4068 | s_dsfar[2:0] & {3 {sb_dec_tid[3]}}; | |
4069 | assign s_desr_ea_2[2:0] = | |
4070 | s_dsfar[2:0] & {3 {sb_dec_tid[2]}}; | |
4071 | assign s_desr_ea_1[2:0] = | |
4072 | s_dsfar[2:0] & {3 {sb_dec_tid[1]}}; | |
4073 | assign s_desr_ea_0[2:0] = | |
4074 | s_dsfar[2:0] & {3 {sb_dec_tid[0]}}; | |
4075 | ||
4076 | ||
4077 | ||
4078 | // SPU errors | |
4079 | // | |
4080 | // DESR | |
4081 | // mamu 00111 | |
4082 | // mal2c 01000 | |
4083 | // mal2u 01001 | |
4084 | // mal2nd 01010 | |
4085 | // cwql2c 01011 | |
4086 | // cwql2u 01100 | |
4087 | // cwql2nd 01101 | |
4088 | // All have S = 1 | |
4089 | ||
4090 | // 10 - ma_copy; 9:8 - syndrome; 7:0 - MA index | |
4091 | tlu_ras_ctl_msff_ctl_macro__width_12 mamu_err_lat ( | |
4092 | .scan_in(mamu_err_lat_scanin), | |
4093 | .scan_out(mamu_err_lat_scanout), | |
4094 | .din ({spu_tlu_mamu_err_req_v , | |
4095 | spu_tlu_mamu_err_req [10:0]}), | |
4096 | .dout ({mamu_err_v , | |
4097 | mamu_err [10:0]}), | |
4098 | .l1clk(l1clk), | |
4099 | .siclk(siclk), | |
4100 | .soclk(soclk) | |
4101 | ); | |
4102 | ||
4103 | assign mamu_dec_tid[7:0] = | |
4104 | ma_dec_tid[7:0] & {8 {mamu_err_v}}; | |
4105 | ||
4106 | assign mamu_desr_et[5:0] = | |
4107 | 6'b100111; | |
4108 | ||
4109 | assign mamu_desr_et_7[5:0] = | |
4110 | mamu_desr_et[5:0] & {6 {mamu_dec_tid[7]}}; | |
4111 | assign mamu_desr_et_6[5:0] = | |
4112 | mamu_desr_et[5:0] & {6 {mamu_dec_tid[6]}}; | |
4113 | assign mamu_desr_et_5[5:0] = | |
4114 | mamu_desr_et[5:0] & {6 {mamu_dec_tid[5]}}; | |
4115 | assign mamu_desr_et_4[5:0] = | |
4116 | mamu_desr_et[5:0] & {6 {mamu_dec_tid[4]}}; | |
4117 | assign mamu_desr_et_3[5:0] = | |
4118 | mamu_desr_et[5:0] & {6 {mamu_dec_tid[3]}}; | |
4119 | assign mamu_desr_et_2[5:0] = | |
4120 | mamu_desr_et[5:0] & {6 {mamu_dec_tid[2]}}; | |
4121 | assign mamu_desr_et_1[5:0] = | |
4122 | mamu_desr_et[5:0] & {6 {mamu_dec_tid[1]}}; | |
4123 | assign mamu_desr_et_0[5:0] = | |
4124 | mamu_desr_et[5:0] & {6 {mamu_dec_tid[0]}}; | |
4125 | ||
4126 | assign mamu_desr_ea_7[10:0] = | |
4127 | mamu_err[10:0] & {11 {mamu_dec_tid[7]}}; | |
4128 | assign mamu_desr_ea_6[10:0] = | |
4129 | mamu_err[10:0] & {11 {mamu_dec_tid[6]}}; | |
4130 | assign mamu_desr_ea_5[10:0] = | |
4131 | mamu_err[10:0] & {11 {mamu_dec_tid[5]}}; | |
4132 | assign mamu_desr_ea_4[10:0] = | |
4133 | mamu_err[10:0] & {11 {mamu_dec_tid[4]}}; | |
4134 | assign mamu_desr_ea_3[10:0] = | |
4135 | mamu_err[10:0] & {11 {mamu_dec_tid[3]}}; | |
4136 | assign mamu_desr_ea_2[10:0] = | |
4137 | mamu_err[10:0] & {11 {mamu_dec_tid[2]}}; | |
4138 | assign mamu_desr_ea_1[10:0] = | |
4139 | mamu_err[10:0] & {11 {mamu_dec_tid[1]}}; | |
4140 | assign mamu_desr_ea_0[10:0] = | |
4141 | mamu_err[10:0] & {11 {mamu_dec_tid[0]}}; | |
4142 | ||
4143 | tlu_ras_ctl_msff_ctl_macro__width_3 ma_tid_lat ( | |
4144 | .scan_in(ma_tid_lat_scanin), | |
4145 | .scan_out(ma_tid_lat_scanout), | |
4146 | .din (spu_tlu_ma_int_req [2:0] ), | |
4147 | .dout (ma_tid [2:0] ), | |
4148 | .l1clk(l1clk), | |
4149 | .siclk(siclk), | |
4150 | .soclk(soclk) | |
4151 | ); | |
4152 | ||
4153 | tlu_ras_ctl_msff_ctl_macro__width_3 cwq_tid_lat ( | |
4154 | .scan_in(cwq_tid_lat_scanin), | |
4155 | .scan_out(cwq_tid_lat_scanout), | |
4156 | .din (spu_tlu_cwq_int_req [2:0] ), | |
4157 | .dout (cwq_tid [2:0] ), | |
4158 | .l1clk(l1clk), | |
4159 | .siclk(siclk), | |
4160 | .soclk(soclk) | |
4161 | ); | |
4162 | ||
4163 | tlu_ras_ctl_msff_ctl_macro__width_6 spu_error_lat ( | |
4164 | .scan_in(spu_error_lat_scanin), | |
4165 | .scan_out(spu_error_lat_scanout), | |
4166 | .din (spu_tlu_l2_error [5:0] ), | |
4167 | .dout (spu_error [5:0] ), | |
4168 | .l1clk(l1clk), | |
4169 | .siclk(siclk), | |
4170 | .soclk(soclk) | |
4171 | ); | |
4172 | ||
4173 | assign ma_dec_tid[7:0] = | |
4174 | {ma_tid[2:0] == 3'b111, | |
4175 | ma_tid[2:0] == 3'b110, | |
4176 | ma_tid[2:0] == 3'b101, | |
4177 | ma_tid[2:0] == 3'b100, | |
4178 | ma_tid[2:0] == 3'b011, | |
4179 | ma_tid[2:0] == 3'b010, | |
4180 | ma_tid[2:0] == 3'b001, | |
4181 | ma_tid[2:0] == 3'b000}; | |
4182 | ||
4183 | assign cwq_dec_tid[7:0] = | |
4184 | {cwq_tid[2:0] == 3'b111, | |
4185 | cwq_tid[2:0] == 3'b110, | |
4186 | cwq_tid[2:0] == 3'b101, | |
4187 | cwq_tid[2:0] == 3'b100, | |
4188 | cwq_tid[2:0] == 3'b011, | |
4189 | cwq_tid[2:0] == 3'b010, | |
4190 | cwq_tid[2:0] == 3'b001, | |
4191 | cwq_tid[2:0] == 3'b000}; | |
4192 | ||
4193 | assign mal2c = | |
4194 | spu_error[5]; | |
4195 | assign mal2u = | |
4196 | spu_error[4]; | |
4197 | assign mal2nd = | |
4198 | spu_error[3]; | |
4199 | assign cwql2c = | |
4200 | spu_error[2]; | |
4201 | assign cwql2u = | |
4202 | spu_error[1]; | |
4203 | assign cwql2nd = | |
4204 | spu_error[0]; | |
4205 | ||
4206 | assign ma_desr_et[5:0] = | |
4207 | ({6 {mal2c }} & 6'b101000) | | |
4208 | ({6 {mal2u }} & 6'b101001) | | |
4209 | ({6 {mal2nd }} & 6'b101010) ; | |
4210 | ||
4211 | assign cwq_desr_et[5:0] = | |
4212 | ({6 {cwql2c }} & 6'b101011) | | |
4213 | ({6 {cwql2u }} & 6'b101100) | | |
4214 | ({6 {cwql2nd}} & 6'b101101) ; | |
4215 | ||
4216 | assign ma_desr_et_7[5:0] = | |
4217 | ma_desr_et[5:0] & {6 {ma_dec_tid[7]}}; | |
4218 | assign ma_desr_et_6[5:0] = | |
4219 | ma_desr_et[5:0] & {6 {ma_dec_tid[6]}}; | |
4220 | assign ma_desr_et_5[5:0] = | |
4221 | ma_desr_et[5:0] & {6 {ma_dec_tid[5]}}; | |
4222 | assign ma_desr_et_4[5:0] = | |
4223 | ma_desr_et[5:0] & {6 {ma_dec_tid[4]}}; | |
4224 | assign ma_desr_et_3[5:0] = | |
4225 | ma_desr_et[5:0] & {6 {ma_dec_tid[3]}}; | |
4226 | assign ma_desr_et_2[5:0] = | |
4227 | ma_desr_et[5:0] & {6 {ma_dec_tid[2]}}; | |
4228 | assign ma_desr_et_1[5:0] = | |
4229 | ma_desr_et[5:0] & {6 {ma_dec_tid[1]}}; | |
4230 | assign ma_desr_et_0[5:0] = | |
4231 | ma_desr_et[5:0] & {6 {ma_dec_tid[0]}}; | |
4232 | ||
4233 | assign cwq_desr_et_7[5:0] = | |
4234 | cwq_desr_et[5:0] & {6 {cwq_dec_tid[7]}}; | |
4235 | assign cwq_desr_et_6[5:0] = | |
4236 | cwq_desr_et[5:0] & {6 {cwq_dec_tid[6]}}; | |
4237 | assign cwq_desr_et_5[5:0] = | |
4238 | cwq_desr_et[5:0] & {6 {cwq_dec_tid[5]}}; | |
4239 | assign cwq_desr_et_4[5:0] = | |
4240 | cwq_desr_et[5:0] & {6 {cwq_dec_tid[4]}}; | |
4241 | assign cwq_desr_et_3[5:0] = | |
4242 | cwq_desr_et[5:0] & {6 {cwq_dec_tid[3]}}; | |
4243 | assign cwq_desr_et_2[5:0] = | |
4244 | cwq_desr_et[5:0] & {6 {cwq_dec_tid[2]}}; | |
4245 | assign cwq_desr_et_1[5:0] = | |
4246 | cwq_desr_et[5:0] & {6 {cwq_dec_tid[1]}}; | |
4247 | assign cwq_desr_et_0[5:0] = | |
4248 | cwq_desr_et[5:0] & {6 {cwq_dec_tid[0]}}; | |
4249 | ||
4250 | // ma and cwq are all L2 errors so no DESR.EA for them | |
4251 | ||
4252 | ||
4253 | ||
4254 | // TCA errors | |
4255 | // | |
4256 | // DESR | |
4257 | // tccd 01110 | |
4258 | // tcud 01111 | |
4259 | // Both have S = 1 | |
4260 | ||
4261 | assign t_desr_et_7[5:0] = | |
4262 | ({6 {tlu_tccd[7]}} & 6'b101110) | | |
4263 | ({6 {tlu_tcud[7]}} & 6'b101111) ; | |
4264 | assign t_desr_et_6[5:0] = | |
4265 | ({6 {tlu_tccd[6]}} & 6'b101110) | | |
4266 | ({6 {tlu_tcud[6]}} & 6'b101111) ; | |
4267 | assign t_desr_et_5[5:0] = | |
4268 | ({6 {tlu_tccd[5]}} & 6'b101110) | | |
4269 | ({6 {tlu_tcud[5]}} & 6'b101111) ; | |
4270 | assign t_desr_et_4[5:0] = | |
4271 | ({6 {tlu_tccd[4]}} & 6'b101110) | | |
4272 | ({6 {tlu_tcud[4]}} & 6'b101111) ; | |
4273 | assign t_desr_et_3[5:0] = | |
4274 | ({6 {tlu_tccd[3]}} & 6'b101110) | | |
4275 | ({6 {tlu_tcud[3]}} & 6'b101111) ; | |
4276 | assign t_desr_et_2[5:0] = | |
4277 | ({6 {tlu_tccd[2]}} & 6'b101110) | | |
4278 | ({6 {tlu_tcud[2]}} & 6'b101111) ; | |
4279 | assign t_desr_et_1[5:0] = | |
4280 | ({6 {tlu_tccd[1]}} & 6'b101110) | | |
4281 | ({6 {tlu_tcud[1]}} & 6'b101111) ; | |
4282 | assign t_desr_et_0[5:0] = | |
4283 | ({6 {tlu_tccd[0]}} & 6'b101110) | | |
4284 | ({6 {tlu_tcud[0]}} & 6'b101111) ; | |
4285 | ||
4286 | assign t_desr_ea_7[9:0] = | |
4287 | {10 {tlu_tccd[7] | tlu_tcud[7]}} & | |
4288 | {cel_syndrome[7:0], tlu_tca_index_1[1:0]}; | |
4289 | assign t_desr_ea_6[9:0] = | |
4290 | {10 {tlu_tccd[6] | tlu_tcud[6]}} & | |
4291 | {cel_syndrome[7:0], tlu_tca_index_1[1:0]}; | |
4292 | assign t_desr_ea_5[9:0] = | |
4293 | {10 {tlu_tccd[5] | tlu_tcud[5]}} & | |
4294 | {cel_syndrome[7:0], tlu_tca_index_1[1:0]}; | |
4295 | assign t_desr_ea_4[9:0] = | |
4296 | {10 {tlu_tccd[4] | tlu_tcud[4]}} & | |
4297 | {cel_syndrome[7:0], tlu_tca_index_1[1:0]}; | |
4298 | assign t_desr_ea_3[9:0] = | |
4299 | {10 {tlu_tccd[3] | tlu_tcud[3]}} & | |
4300 | {cel_syndrome[7:0], tlu_tca_index_0[1:0]}; | |
4301 | assign t_desr_ea_2[9:0] = | |
4302 | {10 {tlu_tccd[2] | tlu_tcud[2]}} & | |
4303 | {cel_syndrome[7:0], tlu_tca_index_0[1:0]}; | |
4304 | assign t_desr_ea_1[9:0] = | |
4305 | {10 {tlu_tccd[1] | tlu_tcud[1]}} & | |
4306 | {cel_syndrome[7:0], tlu_tca_index_0[1:0]}; | |
4307 | assign t_desr_ea_0[9:0] = | |
4308 | {10 {tlu_tccd[0] | tlu_tcud[0]}} & | |
4309 | {cel_syndrome[7:0], tlu_tca_index_0[1:0]}; | |
4310 | ||
4311 | ||
4312 | ||
4313 | ||
4314 | // | |
4315 | // DESRs | |
4316 | // | |
4317 | ||
4318 | // Prioritize DESR exceptions | |
4319 | // S = 0, type 1-4, priority 11 | |
4320 | // and S = 1, type 2, priority 6 | |
4321 | assign pipe_desr_exc_7 = (| pipe_desr_et_7[5:0]); | |
4322 | assign pipe_desr_exc_6 = (| pipe_desr_et_6[5:0]); | |
4323 | assign pipe_desr_exc_5 = (| pipe_desr_et_5[5:0]); | |
4324 | assign pipe_desr_exc_4 = (| pipe_desr_et_4[5:0]); | |
4325 | assign pipe_desr_exc_3 = (| pipe_desr_et_3[5:0]); | |
4326 | assign pipe_desr_exc_2 = (| pipe_desr_et_2[5:0]); | |
4327 | assign pipe_desr_exc_1 = (| pipe_desr_et_1[5:0]); | |
4328 | assign pipe_desr_exc_0 = (| pipe_desr_et_0[5:0]); | |
4329 | ||
4330 | // S = 1, type 1&3, priority 6 | |
4331 | assign m_desr_exc_7 = m_desr_et_7[5]; | |
4332 | assign m_desr_exc_6 = m_desr_et_6[5]; | |
4333 | assign m_desr_exc_5 = m_desr_et_5[5]; | |
4334 | assign m_desr_exc_4 = m_desr_et_4[5]; | |
4335 | assign m_desr_exc_3 = m_desr_et_3[5]; | |
4336 | assign m_desr_exc_2 = m_desr_et_2[5]; | |
4337 | assign m_desr_exc_1 = m_desr_et_1[5]; | |
4338 | assign m_desr_exc_0 = m_desr_et_0[5]; | |
4339 | ||
4340 | // S = 1, type 4, priority 6 | |
4341 | // and S = 0, type 11, priority 15 (shared with l2) | |
4342 | assign l_desr_exc_7 = (| l_desr_et_7[5:0]); | |
4343 | assign l_desr_exc_6 = (| l_desr_et_6[5:0]); | |
4344 | assign l_desr_exc_5 = (| l_desr_et_5[5:0]); | |
4345 | assign l_desr_exc_4 = (| l_desr_et_4[5:0]); | |
4346 | assign l_desr_exc_3 = (| l_desr_et_3[5:0]); | |
4347 | assign l_desr_exc_2 = (| l_desr_et_2[5:0]); | |
4348 | assign l_desr_exc_1 = (| l_desr_et_1[5:0]); | |
4349 | assign l_desr_exc_0 = (| l_desr_et_0[5:0]); | |
4350 | ||
4351 | // S = 0, type 5-8, priority 12 | |
4352 | assign d_desr_exc_7 = (| d_desr_et_7[3:0]); | |
4353 | assign d_desr_exc_6 = (| d_desr_et_6[3:0]); | |
4354 | assign d_desr_exc_5 = (| d_desr_et_5[3:0]); | |
4355 | assign d_desr_exc_4 = (| d_desr_et_4[3:0]); | |
4356 | assign d_desr_exc_3 = (| d_desr_et_3[3:0]); | |
4357 | assign d_desr_exc_2 = (| d_desr_et_2[3:0]); | |
4358 | assign d_desr_exc_1 = (| d_desr_et_1[3:0]); | |
4359 | assign d_desr_exc_0 = (| d_desr_et_0[3:0]); | |
4360 | ||
4361 | // S = 0, type 9, priority 13 | |
4362 | // and S = 0, type 11, priority 15 (shared with l) | |
4363 | // and S = 1, type 16-17, priority 5 | |
4364 | // and S = 1, type 18-19, priority 7 | |
4365 | assign l2_desr_exc_7 = (| l2_desr_et_7[5:0]); | |
4366 | assign l2_desr_exc_6 = (| l2_desr_et_6[5:0]); | |
4367 | assign l2_desr_exc_5 = (| l2_desr_et_5[5:0]); | |
4368 | assign l2_desr_exc_4 = (| l2_desr_et_4[5:0]); | |
4369 | assign l2_desr_exc_3 = (| l2_desr_et_3[5:0]); | |
4370 | assign l2_desr_exc_2 = (| l2_desr_et_2[5:0]); | |
4371 | assign l2_desr_exc_1 = (| l2_desr_et_1[5:0]); | |
4372 | assign l2_desr_exc_0 = (| l2_desr_et_0[5:0]); | |
4373 | ||
4374 | // S = 0, type 10, priority 14 | |
4375 | // and S = 1, type 6, priority 1 | |
4376 | assign s_desr_exc_7 = (| s_desr_et_7[5:0]); | |
4377 | assign s_desr_exc_6 = (| s_desr_et_6[5:0]); | |
4378 | assign s_desr_exc_5 = (| s_desr_et_5[5:0]); | |
4379 | assign s_desr_exc_4 = (| s_desr_et_4[5:0]); | |
4380 | assign s_desr_exc_3 = (| s_desr_et_3[5:0]); | |
4381 | assign s_desr_exc_2 = (| s_desr_et_2[5:0]); | |
4382 | assign s_desr_exc_1 = (| s_desr_et_1[5:0]); | |
4383 | assign s_desr_exc_0 = (| s_desr_et_0[5:0]); | |
4384 | ||
4385 | // S = 1, type 7, priority 3 | |
4386 | assign mamu_desr_exc_7 = mamu_desr_et_7[5]; | |
4387 | assign mamu_desr_exc_6 = mamu_desr_et_6[5]; | |
4388 | assign mamu_desr_exc_5 = mamu_desr_et_5[5]; | |
4389 | assign mamu_desr_exc_4 = mamu_desr_et_4[5]; | |
4390 | assign mamu_desr_exc_3 = mamu_desr_et_3[5]; | |
4391 | assign mamu_desr_exc_2 = mamu_desr_et_2[5]; | |
4392 | assign mamu_desr_exc_1 = mamu_desr_et_1[5]; | |
4393 | assign mamu_desr_exc_0 = mamu_desr_et_0[5]; | |
4394 | ||
4395 | // S = 1, type 8-10, priority 3 | |
4396 | assign ma_desr_exc_7 = ma_desr_et_7[5]; | |
4397 | assign ma_desr_exc_6 = ma_desr_et_6[5]; | |
4398 | assign ma_desr_exc_5 = ma_desr_et_5[5]; | |
4399 | assign ma_desr_exc_4 = ma_desr_et_4[5]; | |
4400 | assign ma_desr_exc_3 = ma_desr_et_3[5]; | |
4401 | assign ma_desr_exc_2 = ma_desr_et_2[5]; | |
4402 | assign ma_desr_exc_1 = ma_desr_et_1[5]; | |
4403 | assign ma_desr_exc_0 = ma_desr_et_0[5]; | |
4404 | ||
4405 | // S = 1, type 11-13, priority 4 | |
4406 | assign cwq_desr_exc_7 = cwq_desr_et_7[5]; | |
4407 | assign cwq_desr_exc_6 = cwq_desr_et_6[5]; | |
4408 | assign cwq_desr_exc_5 = cwq_desr_et_5[5]; | |
4409 | assign cwq_desr_exc_4 = cwq_desr_et_4[5]; | |
4410 | assign cwq_desr_exc_3 = cwq_desr_et_3[5]; | |
4411 | assign cwq_desr_exc_2 = cwq_desr_et_2[5]; | |
4412 | assign cwq_desr_exc_1 = cwq_desr_et_1[5]; | |
4413 | assign cwq_desr_exc_0 = cwq_desr_et_0[5]; | |
4414 | ||
4415 | // S = 1, type 14-15, priority 2 | |
4416 | assign t_desr_exc_7 = t_desr_et_7[5]; | |
4417 | assign t_desr_exc_6 = t_desr_et_6[5]; | |
4418 | assign t_desr_exc_5 = t_desr_et_5[5]; | |
4419 | assign t_desr_exc_4 = t_desr_et_4[5]; | |
4420 | assign t_desr_exc_3 = t_desr_et_3[5]; | |
4421 | assign t_desr_exc_2 = t_desr_et_2[5]; | |
4422 | assign t_desr_exc_1 = t_desr_et_1[5]; | |
4423 | assign t_desr_exc_0 = t_desr_et_0[5]; | |
4424 | ||
4425 | assign ras_desr_en[7] = | |
4426 | pipe_desr_exc_7 | m_desr_exc_7 | l_desr_exc_7 | d_desr_exc_7 | | |
4427 | l2_desr_exc_7 | s_desr_exc_7 | mamu_desr_exc_7 | ma_desr_exc_7 | | |
4428 | cwq_desr_exc_7 | t_desr_exc_7 | rd_desr_dec[7]; | |
4429 | assign ras_desr_en[6] = | |
4430 | pipe_desr_exc_6 | m_desr_exc_6 | l_desr_exc_6 | d_desr_exc_6 | | |
4431 | l2_desr_exc_6 | s_desr_exc_6 | mamu_desr_exc_6 | ma_desr_exc_6 | | |
4432 | cwq_desr_exc_6 | t_desr_exc_6 | rd_desr_dec[6]; | |
4433 | assign ras_desr_en[5] = | |
4434 | pipe_desr_exc_5 | m_desr_exc_5 | l_desr_exc_5 | d_desr_exc_5 | | |
4435 | l2_desr_exc_5 | s_desr_exc_5 | mamu_desr_exc_5 | ma_desr_exc_5 | | |
4436 | cwq_desr_exc_5 | t_desr_exc_5 | rd_desr_dec[5]; | |
4437 | assign ras_desr_en[4] = | |
4438 | pipe_desr_exc_4 | m_desr_exc_4 | l_desr_exc_4 | d_desr_exc_4 | | |
4439 | l2_desr_exc_4 | s_desr_exc_4 | mamu_desr_exc_4 | ma_desr_exc_4 | | |
4440 | cwq_desr_exc_4 | t_desr_exc_4 | rd_desr_dec[4]; | |
4441 | assign ras_desr_en[3] = | |
4442 | pipe_desr_exc_3 | m_desr_exc_3 | l_desr_exc_3 | d_desr_exc_3 | | |
4443 | l2_desr_exc_3 | s_desr_exc_3 | mamu_desr_exc_3 | ma_desr_exc_3 | | |
4444 | cwq_desr_exc_3 | t_desr_exc_3 | rd_desr_dec[3]; | |
4445 | assign ras_desr_en[2] = | |
4446 | pipe_desr_exc_2 | m_desr_exc_2 | l_desr_exc_2 | d_desr_exc_2 | | |
4447 | l2_desr_exc_2 | s_desr_exc_2 | mamu_desr_exc_2 | ma_desr_exc_2 | | |
4448 | cwq_desr_exc_2 | t_desr_exc_2 | rd_desr_dec[2]; | |
4449 | assign ras_desr_en[1] = | |
4450 | pipe_desr_exc_1 | m_desr_exc_1 | l_desr_exc_1 | d_desr_exc_1 | | |
4451 | l2_desr_exc_1 | s_desr_exc_1 | mamu_desr_exc_1 | ma_desr_exc_1 | | |
4452 | cwq_desr_exc_1 | t_desr_exc_1 | rd_desr_dec[1]; | |
4453 | assign ras_desr_en[0] = | |
4454 | pipe_desr_exc_0 | m_desr_exc_0 | l_desr_exc_0 | d_desr_exc_0 | | |
4455 | l2_desr_exc_0 | s_desr_exc_0 | mamu_desr_exc_0 | ma_desr_exc_0 | | |
4456 | cwq_desr_exc_0 | t_desr_exc_0 | rd_desr_dec[0]; | |
4457 | ||
4458 | // Third term is to catch the case of simultaneous | |
4459 | // SBDPC (type 10, priority 14) and SOCC (type 11, priority 15) | |
4460 | assign take_s_7 = | |
4461 | s_desr_et_7[5] | | |
4462 | (s_desr_exc_7 & ~l2_desr_exc_7 & ~d_desr_exc_7 & ~pipe_desr_exc_7 & no_desr_s_7) | | |
4463 | (s_desr_exc_7 & l2_desr_et_7[1] & ~d_desr_exc_7 & ~pipe_desr_exc_7 & no_desr_s_7) ; | |
4464 | assign take_s_6 = | |
4465 | s_desr_et_6[5] | | |
4466 | (s_desr_exc_6 & ~l2_desr_exc_6 & ~d_desr_exc_6 & ~pipe_desr_exc_6 & no_desr_s_6) | | |
4467 | (s_desr_exc_6 & l2_desr_et_6[1] & ~d_desr_exc_6 & ~pipe_desr_exc_6 & no_desr_s_6) ; | |
4468 | assign take_s_5 = | |
4469 | s_desr_et_5[5] | | |
4470 | (s_desr_exc_5 & ~l2_desr_exc_5 & ~d_desr_exc_5 & ~pipe_desr_exc_5 & no_desr_s_5) | | |
4471 | (s_desr_exc_5 & l2_desr_et_5[1] & ~d_desr_exc_5 & ~pipe_desr_exc_5 & no_desr_s_5) ; | |
4472 | assign take_s_4 = | |
4473 | s_desr_et_4[5] | | |
4474 | (s_desr_exc_4 & ~l2_desr_exc_4 & ~d_desr_exc_4 & ~pipe_desr_exc_4 & no_desr_s_4) | | |
4475 | (s_desr_exc_4 & l2_desr_et_4[1] & ~d_desr_exc_4 & ~pipe_desr_exc_4 & no_desr_s_4) ; | |
4476 | assign take_s_3 = | |
4477 | s_desr_et_3[5] | | |
4478 | (s_desr_exc_3 & ~l2_desr_exc_3 & ~d_desr_exc_3 & ~pipe_desr_exc_3 & no_desr_s_3) | | |
4479 | (s_desr_exc_3 & l2_desr_et_3[1] & ~d_desr_exc_3 & ~pipe_desr_exc_3 & no_desr_s_3) ; | |
4480 | assign take_s_2 = | |
4481 | s_desr_et_2[5] | | |
4482 | (s_desr_exc_2 & ~l2_desr_exc_2 & ~d_desr_exc_2 & ~pipe_desr_exc_2 & no_desr_s_2) | | |
4483 | (s_desr_exc_2 & l2_desr_et_2[1] & ~d_desr_exc_2 & ~pipe_desr_exc_2 & no_desr_s_2) ; | |
4484 | assign take_s_1 = | |
4485 | s_desr_et_1[5] | | |
4486 | (s_desr_exc_1 & ~l2_desr_exc_1 & ~d_desr_exc_1 & ~pipe_desr_exc_1 & no_desr_s_1) | | |
4487 | (s_desr_exc_1 & l2_desr_et_1[1] & ~d_desr_exc_1 & ~pipe_desr_exc_1 & no_desr_s_1) ; | |
4488 | assign take_s_0 = | |
4489 | s_desr_et_0[5] | | |
4490 | (s_desr_exc_0 & ~l2_desr_exc_0 & ~d_desr_exc_0 & ~pipe_desr_exc_0 & no_desr_s_0) | | |
4491 | (s_desr_exc_0 & l2_desr_et_0[1] & ~d_desr_exc_0 & ~pipe_desr_exc_0 & no_desr_s_0) ; | |
4492 | ||
4493 | assign take_t_7 = t_desr_exc_7 & ~s_desr_et_7[5]; | |
4494 | assign take_t_6 = t_desr_exc_6 & ~s_desr_et_6[5]; | |
4495 | assign take_t_5 = t_desr_exc_5 & ~s_desr_et_5[5]; | |
4496 | assign take_t_4 = t_desr_exc_4 & ~s_desr_et_4[5]; | |
4497 | assign take_t_3 = t_desr_exc_3 & ~s_desr_et_3[5]; | |
4498 | assign take_t_2 = t_desr_exc_2 & ~s_desr_et_2[5]; | |
4499 | assign take_t_1 = t_desr_exc_1 & ~s_desr_et_1[5]; | |
4500 | assign take_t_0 = t_desr_exc_0 & ~s_desr_et_0[5]; | |
4501 | ||
4502 | assign take_ma_7 = ma_desr_exc_7 & ~t_desr_et_7[5] & ~s_desr_et_7[5]; | |
4503 | assign take_ma_6 = ma_desr_exc_6 & ~t_desr_et_6[5] & ~s_desr_et_6[5]; | |
4504 | assign take_ma_5 = ma_desr_exc_5 & ~t_desr_et_5[5] & ~s_desr_et_5[5]; | |
4505 | assign take_ma_4 = ma_desr_exc_4 & ~t_desr_et_4[5] & ~s_desr_et_4[5]; | |
4506 | assign take_ma_3 = ma_desr_exc_3 & ~t_desr_et_3[5] & ~s_desr_et_3[5]; | |
4507 | assign take_ma_2 = ma_desr_exc_2 & ~t_desr_et_2[5] & ~s_desr_et_2[5]; | |
4508 | assign take_ma_1 = ma_desr_exc_1 & ~t_desr_et_1[5] & ~s_desr_et_1[5]; | |
4509 | assign take_ma_0 = ma_desr_exc_0 & ~t_desr_et_0[5] & ~s_desr_et_0[5]; | |
4510 | ||
4511 | assign take_mamu_7 = mamu_desr_exc_7 & ~ma_desr_exc_7 & ~t_desr_et_7[5] & ~s_desr_et_7[5]; | |
4512 | assign take_mamu_6 = mamu_desr_exc_6 & ~ma_desr_exc_6 & ~t_desr_et_6[5] & ~s_desr_et_6[5]; | |
4513 | assign take_mamu_5 = mamu_desr_exc_5 & ~ma_desr_exc_5 & ~t_desr_et_5[5] & ~s_desr_et_5[5]; | |
4514 | assign take_mamu_4 = mamu_desr_exc_4 & ~ma_desr_exc_4 & ~t_desr_et_4[5] & ~s_desr_et_4[5]; | |
4515 | assign take_mamu_3 = mamu_desr_exc_3 & ~ma_desr_exc_3 & ~t_desr_et_3[5] & ~s_desr_et_3[5]; | |
4516 | assign take_mamu_2 = mamu_desr_exc_2 & ~ma_desr_exc_2 & ~t_desr_et_2[5] & ~s_desr_et_2[5]; | |
4517 | assign take_mamu_1 = mamu_desr_exc_1 & ~ma_desr_exc_1 & ~t_desr_et_1[5] & ~s_desr_et_1[5]; | |
4518 | assign take_mamu_0 = mamu_desr_exc_0 & ~ma_desr_exc_0 & ~t_desr_et_0[5] & ~s_desr_et_0[5]; | |
4519 | ||
4520 | assign take_cwq_7 = cwq_desr_exc_7 & ~mamu_desr_et_7[5] & ~ma_desr_et_7[5] & ~t_desr_et_7[5] & ~s_desr_et_7[5]; | |
4521 | assign take_cwq_6 = cwq_desr_exc_6 & ~mamu_desr_et_6[5] & ~ma_desr_et_6[5] & ~t_desr_et_6[5] & ~s_desr_et_6[5]; | |
4522 | assign take_cwq_5 = cwq_desr_exc_5 & ~mamu_desr_et_5[5] & ~ma_desr_et_5[5] & ~t_desr_et_5[5] & ~s_desr_et_5[5]; | |
4523 | assign take_cwq_4 = cwq_desr_exc_4 & ~mamu_desr_et_4[5] & ~ma_desr_et_4[5] & ~t_desr_et_4[5] & ~s_desr_et_4[5]; | |
4524 | assign take_cwq_3 = cwq_desr_exc_3 & ~mamu_desr_et_3[5] & ~ma_desr_et_3[5] & ~t_desr_et_3[5] & ~s_desr_et_3[5]; | |
4525 | assign take_cwq_2 = cwq_desr_exc_2 & ~mamu_desr_et_2[5] & ~ma_desr_et_2[5] & ~t_desr_et_2[5] & ~s_desr_et_2[5]; | |
4526 | assign take_cwq_1 = cwq_desr_exc_1 & ~mamu_desr_et_1[5] & ~ma_desr_et_1[5] & ~t_desr_et_1[5] & ~s_desr_et_1[5]; | |
4527 | assign take_cwq_0 = cwq_desr_exc_0 & ~mamu_desr_et_0[5] & ~ma_desr_et_0[5] & ~t_desr_et_0[5] & ~s_desr_et_0[5]; | |
4528 | ||
4529 | assign take_l2_7 = (l2_desr_et_7[5] & ~l2_desr_et_7[1] & ~cwq_desr_et_7[5] & ~mamu_desr_et_7[5] & ~ma_desr_et_7[5] & ~t_desr_et_7[5] & ~s_desr_et_7[5]) | | |
4530 | (l2_desr_et_7[5] & l2_desr_et_7[1] & ~pipe_desr_et_7[5] & ~m_desr_et_7[5] & ~l_desr_et_7[5] & ~cwq_desr_et_7[5] & ~mamu_desr_et_7[5] & ~ma_desr_et_7[5] & ~t_desr_et_7[5] & ~s_desr_et_7[5]) | | |
4531 | (l2_desr_exc_7 & ~l2_desr_et_7[1] & ~d_desr_exc_7 & ~pipe_desr_exc_7 & no_desr_s_7) | | |
4532 | (l2_desr_exc_7 & l2_desr_et_7[1] & ~s_desr_exc_7 & ~d_desr_exc_7 & ~pipe_desr_exc_7 & no_desr_s_7) ; | |
4533 | assign take_l2_6 = (l2_desr_et_6[5] & ~l2_desr_et_6[1] & ~cwq_desr_et_6[5] & ~mamu_desr_et_6[5] & ~ma_desr_et_6[5] & ~t_desr_et_6[5] & ~s_desr_et_6[5]) | | |
4534 | (l2_desr_et_6[5] & l2_desr_et_6[1] & ~pipe_desr_et_6[5] & ~m_desr_et_6[5] & ~l_desr_et_6[5] & ~cwq_desr_et_6[5] & ~mamu_desr_et_6[5] & ~ma_desr_et_6[5] & ~t_desr_et_6[5] & ~s_desr_et_6[5]) | | |
4535 | (l2_desr_exc_6 & ~l2_desr_et_6[1] & ~d_desr_exc_6 & ~pipe_desr_exc_6 & no_desr_s_6) | | |
4536 | (l2_desr_exc_6 & l2_desr_et_6[1] & ~s_desr_exc_6 & ~d_desr_exc_6 & ~pipe_desr_exc_6 & no_desr_s_6) ; | |
4537 | assign take_l2_5 = (l2_desr_et_5[5] & ~l2_desr_et_5[1] & ~cwq_desr_et_5[5] & ~mamu_desr_et_5[5] & ~ma_desr_et_5[5] & ~t_desr_et_5[5] & ~s_desr_et_5[5]) | | |
4538 | (l2_desr_et_5[5] & l2_desr_et_5[1] & ~pipe_desr_et_5[5] & ~m_desr_et_5[5] & ~l_desr_et_5[5] & ~cwq_desr_et_5[5] & ~mamu_desr_et_5[5] & ~ma_desr_et_5[5] & ~t_desr_et_5[5] & ~s_desr_et_5[5]) | | |
4539 | (l2_desr_exc_5 & ~l2_desr_et_5[1] & ~d_desr_exc_5 & ~pipe_desr_exc_5 & no_desr_s_5) | | |
4540 | (l2_desr_exc_5 & l2_desr_et_5[1] & ~s_desr_exc_5 & ~d_desr_exc_5 & ~pipe_desr_exc_5 & no_desr_s_5) ; | |
4541 | assign take_l2_4 = (l2_desr_et_4[5] & ~l2_desr_et_4[1] & ~cwq_desr_et_4[5] & ~mamu_desr_et_4[5] & ~ma_desr_et_4[5] & ~t_desr_et_4[5] & ~s_desr_et_4[5]) | | |
4542 | (l2_desr_et_4[5] & l2_desr_et_4[1] & ~pipe_desr_et_4[5] & ~m_desr_et_4[5] & ~l_desr_et_4[5] & ~cwq_desr_et_4[5] & ~mamu_desr_et_4[5] & ~ma_desr_et_4[5] & ~t_desr_et_4[5] & ~s_desr_et_4[5]) | | |
4543 | (l2_desr_exc_4 & ~l2_desr_et_4[1] & ~d_desr_exc_4 & ~pipe_desr_exc_4 & no_desr_s_4) | | |
4544 | (l2_desr_exc_4 & l2_desr_et_4[1] & ~s_desr_exc_4 & ~d_desr_exc_4 & ~pipe_desr_exc_4 & no_desr_s_4) ; | |
4545 | assign take_l2_3 = (l2_desr_et_3[5] & ~l2_desr_et_3[1] & ~cwq_desr_et_3[5] & ~mamu_desr_et_3[5] & ~ma_desr_et_3[5] & ~t_desr_et_3[5] & ~s_desr_et_3[5]) | | |
4546 | (l2_desr_et_3[5] & l2_desr_et_3[1] & ~pipe_desr_et_3[5] & ~m_desr_et_3[5] & ~l_desr_et_3[5] & ~cwq_desr_et_3[5] & ~mamu_desr_et_3[5] & ~ma_desr_et_3[5] & ~t_desr_et_3[5] & ~s_desr_et_3[5]) | | |
4547 | (l2_desr_exc_3 & ~l2_desr_et_3[1] & ~d_desr_exc_3 & ~pipe_desr_exc_3 & no_desr_s_3) | | |
4548 | (l2_desr_exc_3 & l2_desr_et_3[1] & ~s_desr_exc_3 & ~d_desr_exc_3 & ~pipe_desr_exc_3 & no_desr_s_3) ; | |
4549 | assign take_l2_2 = (l2_desr_et_2[5] & ~l2_desr_et_2[1] & ~cwq_desr_et_2[5] & ~mamu_desr_et_2[5] & ~ma_desr_et_2[5] & ~t_desr_et_2[5] & ~s_desr_et_2[5]) | | |
4550 | (l2_desr_et_2[5] & l2_desr_et_2[1] & ~pipe_desr_et_2[5] & ~m_desr_et_2[5] & ~l_desr_et_2[5] & ~cwq_desr_et_2[5] & ~mamu_desr_et_2[5] & ~ma_desr_et_2[5] & ~t_desr_et_2[5] & ~s_desr_et_2[5]) | | |
4551 | (l2_desr_exc_2 & ~l2_desr_et_2[1] & ~d_desr_exc_2 & ~pipe_desr_exc_2 & no_desr_s_2) | | |
4552 | (l2_desr_exc_2 & l2_desr_et_2[1] & ~s_desr_exc_2 & ~d_desr_exc_2 & ~pipe_desr_exc_2 & no_desr_s_2) ; | |
4553 | assign take_l2_1 = (l2_desr_et_1[5] & ~l2_desr_et_1[1] & ~cwq_desr_et_1[5] & ~mamu_desr_et_1[5] & ~ma_desr_et_1[5] & ~t_desr_et_1[5] & ~s_desr_et_1[5]) | | |
4554 | (l2_desr_et_1[5] & l2_desr_et_1[1] & ~pipe_desr_et_1[5] & ~m_desr_et_1[5] & ~l_desr_et_1[5] & ~cwq_desr_et_1[5] & ~mamu_desr_et_1[5] & ~ma_desr_et_1[5] & ~t_desr_et_1[5] & ~s_desr_et_1[5]) | | |
4555 | (l2_desr_exc_1 & ~l2_desr_et_1[1] & ~d_desr_exc_1 & ~pipe_desr_exc_1 & no_desr_s_1) | | |
4556 | (l2_desr_exc_1 & l2_desr_et_1[1] & ~s_desr_exc_1 & ~d_desr_exc_1 & ~pipe_desr_exc_1 & no_desr_s_1) ; | |
4557 | assign take_l2_0 = (l2_desr_et_0[5] & ~l2_desr_et_0[1] & ~cwq_desr_et_0[5] & ~mamu_desr_et_0[5] & ~ma_desr_et_0[5] & ~t_desr_et_0[5] & ~s_desr_et_0[5]) | | |
4558 | (l2_desr_et_0[5] & l2_desr_et_0[1] & ~pipe_desr_et_0[5] & ~m_desr_et_0[5] & ~l_desr_et_0[5] & ~cwq_desr_et_0[5] & ~mamu_desr_et_0[5] & ~ma_desr_et_0[5] & ~t_desr_et_0[5] & ~s_desr_et_0[5]) | | |
4559 | (l2_desr_exc_0 & ~l2_desr_et_0[1] & ~d_desr_exc_0 & ~pipe_desr_exc_0 & no_desr_s_0) | | |
4560 | (l2_desr_exc_0 & l2_desr_et_0[1] & ~s_desr_exc_0 & ~d_desr_exc_0 & ~pipe_desr_exc_0 & no_desr_s_0) ; | |
4561 | ||
4562 | assign take_pipe_7 = (pipe_desr_et_7[5] & ~l2_desr_et_7[5] & ~m_desr_et_7[5] & ~l_desr_et_7[5] & ~cwq_desr_et_7[5] & ~mamu_desr_et_7[5] & ~ma_desr_et_7[5] & ~t_desr_et_7[5] & ~s_desr_et_7[5]) | | |
4563 | (pipe_desr_et_7[5] & l2_desr_et_7[1] & ~m_desr_et_7[5] & ~l_desr_et_7[5] & ~cwq_desr_et_7[5] & ~mamu_desr_et_7[5] & ~ma_desr_et_7[5] & ~t_desr_et_7[5] & ~s_desr_et_7[5]) | | |
4564 | (pipe_desr_exc_7 & no_desr_s_7); | |
4565 | assign take_pipe_6 = (pipe_desr_et_6[5] & ~l2_desr_et_6[5] & ~m_desr_et_6[5] & ~l_desr_et_6[5] & ~cwq_desr_et_6[5] & ~mamu_desr_et_6[5] & ~ma_desr_et_6[5] & ~t_desr_et_6[5] & ~s_desr_et_6[5]) | | |
4566 | (pipe_desr_et_6[5] & l2_desr_et_6[1] & ~m_desr_et_6[5] & ~l_desr_et_6[5] & ~cwq_desr_et_6[5] & ~mamu_desr_et_6[5] & ~ma_desr_et_6[5] & ~t_desr_et_6[5] & ~s_desr_et_6[5]) | | |
4567 | (pipe_desr_exc_6 & no_desr_s_6); | |
4568 | assign take_pipe_5 = (pipe_desr_et_5[5] & ~l2_desr_et_5[5] & ~m_desr_et_5[5] & ~l_desr_et_5[5] & ~cwq_desr_et_5[5] & ~mamu_desr_et_5[5] & ~ma_desr_et_5[5] & ~t_desr_et_5[5] & ~s_desr_et_5[5]) | | |
4569 | (pipe_desr_et_5[5] & l2_desr_et_5[1] & ~m_desr_et_5[5] & ~l_desr_et_5[5] & ~cwq_desr_et_5[5] & ~mamu_desr_et_5[5] & ~ma_desr_et_5[5] & ~t_desr_et_5[5] & ~s_desr_et_5[5]) | | |
4570 | (pipe_desr_exc_5 & no_desr_s_5); | |
4571 | assign take_pipe_4 = (pipe_desr_et_4[5] & ~l2_desr_et_4[5] & ~m_desr_et_4[5] & ~l_desr_et_4[5] & ~cwq_desr_et_4[5] & ~mamu_desr_et_4[5] & ~ma_desr_et_4[5] & ~t_desr_et_4[5] & ~s_desr_et_4[5]) | | |
4572 | (pipe_desr_et_4[5] & l2_desr_et_4[1] & ~m_desr_et_4[5] & ~l_desr_et_4[5] & ~cwq_desr_et_4[5] & ~mamu_desr_et_4[5] & ~ma_desr_et_4[5] & ~t_desr_et_4[5] & ~s_desr_et_4[5]) | | |
4573 | (pipe_desr_exc_4 & no_desr_s_4); | |
4574 | assign take_pipe_3 = (pipe_desr_et_3[5] & ~l2_desr_et_3[5] & ~m_desr_et_3[5] & ~l_desr_et_3[5] & ~cwq_desr_et_3[5] & ~mamu_desr_et_3[5] & ~ma_desr_et_3[5] & ~t_desr_et_3[5] & ~s_desr_et_3[5]) | | |
4575 | (pipe_desr_et_3[5] & l2_desr_et_3[1] & ~m_desr_et_3[5] & ~l_desr_et_3[5] & ~cwq_desr_et_3[5] & ~mamu_desr_et_3[5] & ~ma_desr_et_3[5] & ~t_desr_et_3[5] & ~s_desr_et_3[5]) | | |
4576 | (pipe_desr_exc_3 & no_desr_s_3); | |
4577 | assign take_pipe_2 = (pipe_desr_et_2[5] & ~l2_desr_et_2[5] & ~m_desr_et_2[5] & ~l_desr_et_2[5] & ~cwq_desr_et_2[5] & ~mamu_desr_et_2[5] & ~ma_desr_et_2[5] & ~t_desr_et_2[5] & ~s_desr_et_2[5]) | | |
4578 | (pipe_desr_et_2[5] & l2_desr_et_2[1] & ~m_desr_et_2[5] & ~l_desr_et_2[5] & ~cwq_desr_et_2[5] & ~mamu_desr_et_2[5] & ~ma_desr_et_2[5] & ~t_desr_et_2[5] & ~s_desr_et_2[5]) | | |
4579 | (pipe_desr_exc_2 & no_desr_s_2); | |
4580 | assign take_pipe_1 = (pipe_desr_et_1[5] & ~l2_desr_et_1[5] & ~m_desr_et_1[5] & ~l_desr_et_1[5] & ~cwq_desr_et_1[5] & ~mamu_desr_et_1[5] & ~ma_desr_et_1[5] & ~t_desr_et_1[5] & ~s_desr_et_1[5]) | | |
4581 | (pipe_desr_et_1[5] & l2_desr_et_1[1] & ~m_desr_et_1[5] & ~l_desr_et_1[5] & ~cwq_desr_et_1[5] & ~mamu_desr_et_1[5] & ~ma_desr_et_1[5] & ~t_desr_et_1[5] & ~s_desr_et_1[5]) | | |
4582 | (pipe_desr_exc_1 & no_desr_s_1); | |
4583 | assign take_pipe_0 = (pipe_desr_et_0[5] & ~l2_desr_et_0[5] & ~m_desr_et_0[5] & ~l_desr_et_0[5] & ~cwq_desr_et_0[5] & ~mamu_desr_et_0[5] & ~ma_desr_et_0[5] & ~t_desr_et_0[5] & ~s_desr_et_0[5]) | | |
4584 | (pipe_desr_et_0[5] & l2_desr_et_0[1] & ~m_desr_et_0[5] & ~l_desr_et_0[5] & ~cwq_desr_et_0[5] & ~mamu_desr_et_0[5] & ~ma_desr_et_0[5] & ~t_desr_et_0[5] & ~s_desr_et_0[5]) | | |
4585 | (pipe_desr_exc_0 & no_desr_s_0); | |
4586 | ||
4587 | assign take_m_7 = (m_desr_et_7[5] & ~l2_desr_et_7[5] & ~l_desr_et_7[5] & ~cwq_desr_et_7[5] & ~mamu_desr_et_7[5] & ~ma_desr_et_7[5] & ~t_desr_et_7[5] & ~s_desr_et_7[5]) | | |
4588 | (m_desr_et_7[5] & l2_desr_et_7[1] & ~l_desr_et_7[5] & ~cwq_desr_et_7[5] & ~mamu_desr_et_7[5] & ~ma_desr_et_7[5] & ~t_desr_et_7[5] & ~s_desr_et_7[5]) ; | |
4589 | assign take_m_6 = (m_desr_et_6[5] & ~l2_desr_et_6[5] & ~l_desr_et_6[5] & ~cwq_desr_et_6[5] & ~mamu_desr_et_6[5] & ~ma_desr_et_6[5] & ~t_desr_et_6[5] & ~s_desr_et_6[5]) | | |
4590 | (m_desr_et_6[5] & l2_desr_et_6[1] & ~l_desr_et_6[5] & ~cwq_desr_et_6[5] & ~mamu_desr_et_6[5] & ~ma_desr_et_6[5] & ~t_desr_et_6[5] & ~s_desr_et_6[5]) ; | |
4591 | assign take_m_5 = (m_desr_et_5[5] & ~l2_desr_et_5[5] & ~l_desr_et_5[5] & ~cwq_desr_et_5[5] & ~mamu_desr_et_5[5] & ~ma_desr_et_5[5] & ~t_desr_et_5[5] & ~s_desr_et_5[5]) | | |
4592 | (m_desr_et_5[5] & l2_desr_et_5[1] & ~l_desr_et_5[5] & ~cwq_desr_et_5[5] & ~mamu_desr_et_5[5] & ~ma_desr_et_5[5] & ~t_desr_et_5[5] & ~s_desr_et_5[5]) ; | |
4593 | assign take_m_4 = (m_desr_et_4[5] & ~l2_desr_et_4[5] & ~l_desr_et_4[5] & ~cwq_desr_et_4[5] & ~mamu_desr_et_4[5] & ~ma_desr_et_4[5] & ~t_desr_et_4[5] & ~s_desr_et_4[5]) | | |
4594 | (m_desr_et_4[5] & l2_desr_et_4[1] & ~l_desr_et_4[5] & ~cwq_desr_et_4[5] & ~mamu_desr_et_4[5] & ~ma_desr_et_4[5] & ~t_desr_et_4[5] & ~s_desr_et_4[5]) ; | |
4595 | assign take_m_3 = (m_desr_et_3[5] & ~l2_desr_et_3[5] & ~l_desr_et_3[5] & ~cwq_desr_et_3[5] & ~mamu_desr_et_3[5] & ~ma_desr_et_3[5] & ~t_desr_et_3[5] & ~s_desr_et_3[5]) | | |
4596 | (m_desr_et_3[5] & l2_desr_et_3[1] & ~l_desr_et_3[5] & ~cwq_desr_et_3[5] & ~mamu_desr_et_3[5] & ~ma_desr_et_3[5] & ~t_desr_et_3[5] & ~s_desr_et_3[5]) ; | |
4597 | assign take_m_2 = (m_desr_et_2[5] & ~l2_desr_et_2[5] & ~l_desr_et_2[5] & ~cwq_desr_et_2[5] & ~mamu_desr_et_2[5] & ~ma_desr_et_2[5] & ~t_desr_et_2[5] & ~s_desr_et_2[5]) | | |
4598 | (m_desr_et_2[5] & l2_desr_et_2[1] & ~l_desr_et_2[5] & ~cwq_desr_et_2[5] & ~mamu_desr_et_2[5] & ~ma_desr_et_2[5] & ~t_desr_et_2[5] & ~s_desr_et_2[5]) ; | |
4599 | assign take_m_1 = (m_desr_et_1[5] & ~l2_desr_et_1[5] & ~l_desr_et_1[5] & ~cwq_desr_et_1[5] & ~mamu_desr_et_1[5] & ~ma_desr_et_1[5] & ~t_desr_et_1[5] & ~s_desr_et_1[5]) | | |
4600 | (m_desr_et_1[5] & l2_desr_et_1[1] & ~l_desr_et_1[5] & ~cwq_desr_et_1[5] & ~mamu_desr_et_1[5] & ~ma_desr_et_1[5] & ~t_desr_et_1[5] & ~s_desr_et_1[5]) ; | |
4601 | assign take_m_0 = (m_desr_et_0[5] & ~l2_desr_et_0[5] & ~l_desr_et_0[5] & ~cwq_desr_et_0[5] & ~mamu_desr_et_0[5] & ~ma_desr_et_0[5] & ~t_desr_et_0[5] & ~s_desr_et_0[5]) | | |
4602 | (m_desr_et_0[5] & l2_desr_et_0[1] & ~l_desr_et_0[5] & ~cwq_desr_et_0[5] & ~mamu_desr_et_0[5] & ~ma_desr_et_0[5] & ~t_desr_et_0[5] & ~s_desr_et_0[5]) ; | |
4603 | ||
4604 | assign take_l_7 = (l_desr_et_7[5] & ~l2_desr_et_7[5] & ~cwq_desr_et_7[5] & ~mamu_desr_et_7[5] & ~ma_desr_et_7[5] & ~t_desr_et_7[5] & ~s_desr_et_7[5]) | | |
4605 | (l_desr_et_7[5] & l2_desr_et_7[1] & ~cwq_desr_et_7[5] & ~mamu_desr_et_7[5] & ~ma_desr_et_7[5] & ~t_desr_et_7[5] & ~s_desr_et_7[5]) | | |
4606 | (l_desr_exc_7 & ~l2_desr_exc_7 & ~s_desr_exc_7 & ~d_desr_exc_7 & ~pipe_desr_exc_7 & no_desr_s_7); | |
4607 | assign take_l_6 = (l_desr_et_6[5] & ~l2_desr_et_6[5] & ~cwq_desr_et_6[5] & ~mamu_desr_et_6[5] & ~ma_desr_et_6[5] & ~t_desr_et_6[5] & ~s_desr_et_6[5]) | | |
4608 | (l_desr_et_6[5] & l2_desr_et_6[1] & ~cwq_desr_et_6[5] & ~mamu_desr_et_6[5] & ~ma_desr_et_6[5] & ~t_desr_et_6[5] & ~s_desr_et_6[5]) | | |
4609 | (l_desr_exc_6 & ~l2_desr_exc_6 & ~s_desr_exc_6 & ~d_desr_exc_6 & ~pipe_desr_exc_6 & no_desr_s_6); | |
4610 | assign take_l_5 = (l_desr_et_5[5] & ~l2_desr_et_5[5] & ~cwq_desr_et_5[5] & ~mamu_desr_et_5[5] & ~ma_desr_et_5[5] & ~t_desr_et_5[5] & ~s_desr_et_5[5]) | | |
4611 | (l_desr_et_5[5] & l2_desr_et_5[1] & ~cwq_desr_et_5[5] & ~mamu_desr_et_5[5] & ~ma_desr_et_5[5] & ~t_desr_et_5[5] & ~s_desr_et_5[5]) | | |
4612 | (l_desr_exc_5 & ~l2_desr_exc_5 & ~s_desr_exc_5 & ~d_desr_exc_5 & ~pipe_desr_exc_5 & no_desr_s_5); | |
4613 | assign take_l_4 = (l_desr_et_4[5] & ~l2_desr_et_4[5] & ~cwq_desr_et_4[5] & ~mamu_desr_et_4[5] & ~ma_desr_et_4[5] & ~t_desr_et_4[5] & ~s_desr_et_4[5]) | | |
4614 | (l_desr_et_4[5] & l2_desr_et_4[1] & ~cwq_desr_et_4[5] & ~mamu_desr_et_4[5] & ~ma_desr_et_4[5] & ~t_desr_et_4[5] & ~s_desr_et_4[5]) | | |
4615 | (l_desr_exc_4 & ~l2_desr_exc_4 & ~s_desr_exc_4 & ~d_desr_exc_4 & ~pipe_desr_exc_4 & no_desr_s_4); | |
4616 | assign take_l_3 = (l_desr_et_3[5] & ~l2_desr_et_3[5] & ~cwq_desr_et_3[5] & ~mamu_desr_et_3[5] & ~ma_desr_et_3[5] & ~t_desr_et_3[5] & ~s_desr_et_3[5]) | | |
4617 | (l_desr_et_3[5] & l2_desr_et_3[1] & ~cwq_desr_et_3[5] & ~mamu_desr_et_3[5] & ~ma_desr_et_3[5] & ~t_desr_et_3[5] & ~s_desr_et_3[5]) | | |
4618 | (l_desr_exc_3 & ~l2_desr_exc_3 & ~s_desr_exc_3 & ~d_desr_exc_3 & ~pipe_desr_exc_3 & no_desr_s_3); | |
4619 | assign take_l_2 = (l_desr_et_2[5] & ~l2_desr_et_2[5] & ~cwq_desr_et_2[5] & ~mamu_desr_et_2[5] & ~ma_desr_et_2[5] & ~t_desr_et_2[5] & ~s_desr_et_2[5]) | | |
4620 | (l_desr_et_2[5] & l2_desr_et_2[1] & ~cwq_desr_et_2[5] & ~mamu_desr_et_2[5] & ~ma_desr_et_2[5] & ~t_desr_et_2[5] & ~s_desr_et_2[5]) | | |
4621 | (l_desr_exc_2 & ~l2_desr_exc_2 & ~s_desr_exc_2 & ~d_desr_exc_2 & ~pipe_desr_exc_2 & no_desr_s_2); | |
4622 | assign take_l_1 = (l_desr_et_1[5] & ~l2_desr_et_1[5] & ~cwq_desr_et_1[5] & ~mamu_desr_et_1[5] & ~ma_desr_et_1[5] & ~t_desr_et_1[5] & ~s_desr_et_1[5]) | | |
4623 | (l_desr_et_1[5] & l2_desr_et_1[1] & ~cwq_desr_et_1[5] & ~mamu_desr_et_1[5] & ~ma_desr_et_1[5] & ~t_desr_et_1[5] & ~s_desr_et_1[5]) | | |
4624 | (l_desr_exc_1 & ~l2_desr_exc_1 & ~s_desr_exc_1 & ~d_desr_exc_1 & ~pipe_desr_exc_1 & no_desr_s_1); | |
4625 | assign take_l_0 = (l_desr_et_0[5] & ~l2_desr_et_0[5] & ~cwq_desr_et_0[5] & ~mamu_desr_et_0[5] & ~ma_desr_et_0[5] & ~t_desr_et_0[5] & ~s_desr_et_0[5]) | | |
4626 | (l_desr_et_0[5] & l2_desr_et_0[1] & ~cwq_desr_et_0[5] & ~mamu_desr_et_0[5] & ~ma_desr_et_0[5] & ~t_desr_et_0[5] & ~s_desr_et_0[5]) | | |
4627 | (l_desr_exc_0 & ~l2_desr_exc_0 & ~s_desr_exc_0 & ~d_desr_exc_0 & ~pipe_desr_exc_0 & no_desr_s_0); | |
4628 | ||
4629 | assign take_d_7 = d_desr_exc_7 & ~pipe_desr_exc_7 & no_desr_s_7; | |
4630 | assign take_d_6 = d_desr_exc_6 & ~pipe_desr_exc_6 & no_desr_s_6; | |
4631 | assign take_d_5 = d_desr_exc_5 & ~pipe_desr_exc_5 & no_desr_s_5; | |
4632 | assign take_d_4 = d_desr_exc_4 & ~pipe_desr_exc_4 & no_desr_s_4; | |
4633 | assign take_d_3 = d_desr_exc_3 & ~pipe_desr_exc_3 & no_desr_s_3; | |
4634 | assign take_d_2 = d_desr_exc_2 & ~pipe_desr_exc_2 & no_desr_s_2; | |
4635 | assign take_d_1 = d_desr_exc_1 & ~pipe_desr_exc_1 & no_desr_s_1; | |
4636 | assign take_d_0 = d_desr_exc_0 & ~pipe_desr_exc_0 & no_desr_s_0; | |
4637 | ||
4638 | ||
4639 | ||
4640 | assign no_desr_s_7 = | |
4641 | ~(pipe_desr_et_7[5] | m_desr_et_7[5] | l_desr_et_7[5] | | |
4642 | l2_desr_et_7[5] | s_desr_et_7[5] | mamu_desr_et_7[5] | | |
4643 | ma_desr_et_7[5] | cwq_desr_et_7[5] | t_desr_et_7[5]); | |
4644 | assign no_desr_s_6 = | |
4645 | ~(pipe_desr_et_6[5] | m_desr_et_6[5] | l_desr_et_6[5] | | |
4646 | l2_desr_et_6[5] | s_desr_et_6[5] | mamu_desr_et_6[5] | | |
4647 | ma_desr_et_6[5] | cwq_desr_et_6[5] | t_desr_et_6[5]); | |
4648 | assign no_desr_s_5 = | |
4649 | ~(pipe_desr_et_5[5] | m_desr_et_5[5] | l_desr_et_5[5] | | |
4650 | l2_desr_et_5[5] | s_desr_et_5[5] | mamu_desr_et_5[5] | | |
4651 | ma_desr_et_5[5] | cwq_desr_et_5[5] | t_desr_et_5[5]); | |
4652 | assign no_desr_s_4 = | |
4653 | ~(pipe_desr_et_4[5] | m_desr_et_4[5] | l_desr_et_4[5] | | |
4654 | l2_desr_et_4[5] | s_desr_et_4[5] | mamu_desr_et_4[5] | | |
4655 | ma_desr_et_4[5] | cwq_desr_et_4[5] | t_desr_et_4[5]); | |
4656 | assign no_desr_s_3 = | |
4657 | ~(pipe_desr_et_3[5] | m_desr_et_3[5] | l_desr_et_3[5] | | |
4658 | l2_desr_et_3[5] | s_desr_et_3[5] | mamu_desr_et_3[5] | | |
4659 | ma_desr_et_3[5] | cwq_desr_et_3[5] | t_desr_et_3[5]); | |
4660 | assign no_desr_s_2 = | |
4661 | ~(pipe_desr_et_2[5] | m_desr_et_2[5] | l_desr_et_2[5] | | |
4662 | l2_desr_et_2[5] | s_desr_et_2[5] | mamu_desr_et_2[5] | | |
4663 | ma_desr_et_2[5] | cwq_desr_et_2[5] | t_desr_et_2[5]); | |
4664 | assign no_desr_s_1 = | |
4665 | ~(pipe_desr_et_1[5] | m_desr_et_1[5] | l_desr_et_1[5] | | |
4666 | l2_desr_et_1[5] | s_desr_et_1[5] | mamu_desr_et_1[5] | | |
4667 | ma_desr_et_1[5] | cwq_desr_et_1[5] | t_desr_et_1[5]); | |
4668 | assign no_desr_s_0 = | |
4669 | ~(pipe_desr_et_0[5] | m_desr_et_0[5] | l_desr_et_0[5] | | |
4670 | l2_desr_et_0[5] | s_desr_et_0[5] | mamu_desr_et_0[5] | | |
4671 | ma_desr_et_0[5] | cwq_desr_et_0[5] | t_desr_et_0[5]); | |
4672 | ||
4673 | assign ras_desr_et_7[61:56] = | |
4674 | ( pipe_desr_et_7[5:0] & {6 {take_pipe_7}}) | | |
4675 | ( m_desr_et_7[5:0] & {6 { take_m_7}}) | | |
4676 | ( l_desr_et_7[5:0] & {6 { take_l_7}}) | | |
4677 | ({1'b0, {1 {1'b0}}, d_desr_et_7[3:0]} & {6 { take_d_7}}) | | |
4678 | ( l2_desr_et_7[5:0] & {6 { take_l2_7}}) | | |
4679 | ( s_desr_et_7[5:0] & {6 { take_s_7}}) | | |
4680 | ( mamu_desr_et_7[5:0] & {6 {take_mamu_7}}) | | |
4681 | ( ma_desr_et_7[5:0] & {6 { take_ma_7}}) | | |
4682 | ( cwq_desr_et_7[5:0] & {6 { take_cwq_7}}) | | |
4683 | ( t_desr_et_7[5:0] & {6 { take_t_7}}) ; | |
4684 | ||
4685 | assign ras_desr_et_6[61:56] = | |
4686 | ( pipe_desr_et_6[5:0] & {6 {take_pipe_6}}) | | |
4687 | ( m_desr_et_6[5:0] & {6 { take_m_6}}) | | |
4688 | ( l_desr_et_6[5:0] & {6 { take_l_6}}) | | |
4689 | ({1'b0, {1 {1'b0}}, d_desr_et_6[3:0]} & {6 { take_d_6}}) | | |
4690 | ( l2_desr_et_6[5:0] & {6 { take_l2_6}}) | | |
4691 | ( s_desr_et_6[5:0] & {6 { take_s_6}}) | | |
4692 | ( mamu_desr_et_6[5:0] & {6 {take_mamu_6}}) | | |
4693 | ( ma_desr_et_6[5:0] & {6 { take_ma_6}}) | | |
4694 | ( cwq_desr_et_6[5:0] & {6 { take_cwq_6}}) | | |
4695 | ( t_desr_et_6[5:0] & {6 { take_t_6}}) ; | |
4696 | ||
4697 | assign ras_desr_et_5[61:56] = | |
4698 | ( pipe_desr_et_5[5:0] & {6 {take_pipe_5}}) | | |
4699 | ( m_desr_et_5[5:0] & {6 { take_m_5}}) | | |
4700 | ( l_desr_et_5[5:0] & {6 { take_l_5}}) | | |
4701 | ({1'b0, {1 {1'b0}}, d_desr_et_5[3:0]} & {6 { take_d_5}}) | | |
4702 | ( l2_desr_et_5[5:0] & {6 { take_l2_5}}) | | |
4703 | ( s_desr_et_5[5:0] & {6 { take_s_5}}) | | |
4704 | ( mamu_desr_et_5[5:0] & {6 {take_mamu_5}}) | | |
4705 | ( ma_desr_et_5[5:0] & {6 { take_ma_5}}) | | |
4706 | ( cwq_desr_et_5[5:0] & {6 { take_cwq_5}}) | | |
4707 | ( t_desr_et_5[5:0] & {6 { take_t_5}}) ; | |
4708 | ||
4709 | assign ras_desr_et_4[61:56] = | |
4710 | ( pipe_desr_et_4[5:0] & {6 {take_pipe_4}}) | | |
4711 | ( m_desr_et_4[5:0] & {6 { take_m_4}}) | | |
4712 | ( l_desr_et_4[5:0] & {6 { take_l_4}}) | | |
4713 | ({1'b0, {1 {1'b0}}, d_desr_et_4[3:0]} & {6 { take_d_4}}) | | |
4714 | ( l2_desr_et_4[5:0] & {6 { take_l2_4}}) | | |
4715 | ( s_desr_et_4[5:0] & {6 { take_s_4}}) | | |
4716 | ( mamu_desr_et_4[5:0] & {6 {take_mamu_4}}) | | |
4717 | ( ma_desr_et_4[5:0] & {6 { take_ma_4}}) | | |
4718 | ( cwq_desr_et_4[5:0] & {6 { take_cwq_4}}) | | |
4719 | ( t_desr_et_4[5:0] & {6 { take_t_4}}) ; | |
4720 | ||
4721 | assign ras_desr_et_3[61:56] = | |
4722 | ( pipe_desr_et_3[5:0] & {6 {take_pipe_3}}) | | |
4723 | ( m_desr_et_3[5:0] & {6 { take_m_3}}) | | |
4724 | ( l_desr_et_3[5:0] & {6 { take_l_3}}) | | |
4725 | ({1'b0, {1 {1'b0}}, d_desr_et_3[3:0]} & {6 { take_d_3}}) | | |
4726 | ( l2_desr_et_3[5:0] & {6 { take_l2_3}}) | | |
4727 | ( s_desr_et_3[5:0] & {6 { take_s_3}}) | | |
4728 | ( mamu_desr_et_3[5:0] & {6 {take_mamu_3}}) | | |
4729 | ( ma_desr_et_3[5:0] & {6 { take_ma_3}}) | | |
4730 | ( cwq_desr_et_3[5:0] & {6 { take_cwq_3}}) | | |
4731 | ( t_desr_et_3[5:0] & {6 { take_t_3}}) ; | |
4732 | ||
4733 | assign ras_desr_et_2[61:56] = | |
4734 | ( pipe_desr_et_2[5:0] & {6 {take_pipe_2}}) | | |
4735 | ( m_desr_et_2[5:0] & {6 { take_m_2}}) | | |
4736 | ( l_desr_et_2[5:0] & {6 { take_l_2}}) | | |
4737 | ({1'b0, {1 {1'b0}}, d_desr_et_2[3:0]} & {6 { take_d_2}}) | | |
4738 | ( l2_desr_et_2[5:0] & {6 { take_l2_2}}) | | |
4739 | ( s_desr_et_2[5:0] & {6 { take_s_2}}) | | |
4740 | ( mamu_desr_et_2[5:0] & {6 {take_mamu_2}}) | | |
4741 | ( ma_desr_et_2[5:0] & {6 { take_ma_2}}) | | |
4742 | ( cwq_desr_et_2[5:0] & {6 { take_cwq_2}}) | | |
4743 | ( t_desr_et_2[5:0] & {6 { take_t_2}}) ; | |
4744 | ||
4745 | assign ras_desr_et_1[61:56] = | |
4746 | ( pipe_desr_et_1[5:0] & {6 {take_pipe_1}}) | | |
4747 | ( m_desr_et_1[5:0] & {6 { take_m_1}}) | | |
4748 | ( l_desr_et_1[5:0] & {6 { take_l_1}}) | | |
4749 | ({1'b0, {1 {1'b0}}, d_desr_et_1[3:0]} & {6 { take_d_1}}) | | |
4750 | ( l2_desr_et_1[5:0] & {6 { take_l2_1}}) | | |
4751 | ( s_desr_et_1[5:0] & {6 { take_s_1}}) | | |
4752 | ( mamu_desr_et_1[5:0] & {6 {take_mamu_1}}) | | |
4753 | ( ma_desr_et_1[5:0] & {6 { take_ma_1}}) | | |
4754 | ( cwq_desr_et_1[5:0] & {6 { take_cwq_1}}) | | |
4755 | ( t_desr_et_1[5:0] & {6 { take_t_1}}) ; | |
4756 | ||
4757 | assign ras_desr_et_0[61:56] = | |
4758 | ( pipe_desr_et_0[5:0] & {6 {take_pipe_0}}) | | |
4759 | ( m_desr_et_0[5:0] & {6 { take_m_0}}) | | |
4760 | ( l_desr_et_0[5:0] & {6 { take_l_0}}) | | |
4761 | ({1'b0, {1 {1'b0}}, d_desr_et_0[3:0]} & {6 { take_d_0}}) | | |
4762 | ( l2_desr_et_0[5:0] & {6 { take_l2_0}}) | | |
4763 | ( s_desr_et_0[5:0] & {6 { take_s_0}}) | | |
4764 | ( mamu_desr_et_0[5:0] & {6 {take_mamu_0}}) | | |
4765 | ( ma_desr_et_0[5:0] & {6 { take_ma_0}}) | | |
4766 | ( cwq_desr_et_0[5:0] & {6 { take_cwq_0}}) | | |
4767 | ( t_desr_et_0[5:0] & {6 { take_t_0}}) ; | |
4768 | ||
4769 | ||
4770 | assign write_desr[7:0] = | |
4771 | {| ras_desr_et_7[60:56], | |
4772 | | ras_desr_et_6[60:56], | |
4773 | | ras_desr_et_5[60:56], | |
4774 | | ras_desr_et_4[60:56], | |
4775 | | ras_desr_et_3[60:56], | |
4776 | | ras_desr_et_2[60:56], | |
4777 | | ras_desr_et_1[60:56], | |
4778 | | ras_desr_et_0[60:56]}; | |
4779 | ||
4780 | assign write_desr_s[7:0] = | |
4781 | {ras_desr_et_7[61], | |
4782 | ras_desr_et_6[61], | |
4783 | ras_desr_et_5[61], | |
4784 | ras_desr_et_4[61], | |
4785 | ras_desr_et_3[61], | |
4786 | ras_desr_et_2[61], | |
4787 | ras_desr_et_1[61], | |
4788 | ras_desr_et_0[61]}; | |
4789 | ||
4790 | assign ras_write_desr_1st[7:0] = | |
4791 | (write_desr [7:0] & ~dfd_desr_f[7:0]) | | |
4792 | (write_desr_s[7:0] & ~dfd_desr_s[7:0]) | | |
4793 | (write_desr [7:0] & rd_desr_dec[7:0]) ; | |
4794 | ||
4795 | assign ras_write_desr_2nd[7:0] = | |
4796 | (write_desr[7:0] & ~write_desr_s[7:0] & dfd_desr_f[7:0]) | | |
4797 | ( write_desr_s[7:0] & dfd_desr_s[7:0]) ; | |
4798 | ||
4799 | assign ras_desr_me_7 = | |
4800 | (({{3 {1'b0}}, pipe_desr_exc_7} + | |
4801 | {{3 {1'b0}}, m_desr_exc_7} + | |
4802 | {{3 {1'b0}}, l_desr_exc_7} + | |
4803 | {{3 {1'b0}}, d_desr_exc_7} + | |
4804 | {{3 {1'b0}}, l2_desr_exc_7} + | |
4805 | {{3 {1'b0}}, s_desr_exc_7} + | |
4806 | {{3 {1'b0}}, mamu_desr_exc_7} + | |
4807 | {{3 {1'b0}}, ma_desr_exc_7} + | |
4808 | {{3 {1'b0}}, cwq_desr_exc_7} + | |
4809 | {{3 {1'b0}}, t_desr_exc_7}) > 4'b0001) | | |
4810 | (dfd_desr_f[7] & ~rd_desr_dec[7]); | |
4811 | assign ras_desr_me_6 = | |
4812 | (({{3 {1'b0}}, pipe_desr_exc_6} + | |
4813 | {{3 {1'b0}}, m_desr_exc_6} + | |
4814 | {{3 {1'b0}}, l_desr_exc_6} + | |
4815 | {{3 {1'b0}}, d_desr_exc_6} + | |
4816 | {{3 {1'b0}}, l2_desr_exc_6} + | |
4817 | {{3 {1'b0}}, s_desr_exc_6} + | |
4818 | {{3 {1'b0}}, mamu_desr_exc_6} + | |
4819 | {{3 {1'b0}}, ma_desr_exc_6} + | |
4820 | {{3 {1'b0}}, cwq_desr_exc_6} + | |
4821 | {{3 {1'b0}}, t_desr_exc_6}) > 4'b0001) | | |
4822 | (dfd_desr_f[6] & ~rd_desr_dec[6]); | |
4823 | assign ras_desr_me_5 = | |
4824 | (({{3 {1'b0}}, pipe_desr_exc_5} + | |
4825 | {{3 {1'b0}}, m_desr_exc_5} + | |
4826 | {{3 {1'b0}}, l_desr_exc_5} + | |
4827 | {{3 {1'b0}}, d_desr_exc_5} + | |
4828 | {{3 {1'b0}}, l2_desr_exc_5} + | |
4829 | {{3 {1'b0}}, s_desr_exc_5} + | |
4830 | {{3 {1'b0}}, mamu_desr_exc_5} + | |
4831 | {{3 {1'b0}}, ma_desr_exc_5} + | |
4832 | {{3 {1'b0}}, cwq_desr_exc_5} + | |
4833 | {{3 {1'b0}}, t_desr_exc_5}) > 4'b0001) | | |
4834 | (dfd_desr_f[5] & ~rd_desr_dec[5]); | |
4835 | assign ras_desr_me_4 = | |
4836 | (({{3 {1'b0}}, pipe_desr_exc_4} + | |
4837 | {{3 {1'b0}}, m_desr_exc_4} + | |
4838 | {{3 {1'b0}}, l_desr_exc_4} + | |
4839 | {{3 {1'b0}}, d_desr_exc_4} + | |
4840 | {{3 {1'b0}}, l2_desr_exc_4} + | |
4841 | {{3 {1'b0}}, s_desr_exc_4} + | |
4842 | {{3 {1'b0}}, mamu_desr_exc_4} + | |
4843 | {{3 {1'b0}}, ma_desr_exc_4} + | |
4844 | {{3 {1'b0}}, cwq_desr_exc_4} + | |
4845 | {{3 {1'b0}}, t_desr_exc_4}) > 4'b0001) | | |
4846 | (dfd_desr_f[4] & ~rd_desr_dec[4]); | |
4847 | assign ras_desr_me_3 = | |
4848 | (({{3 {1'b0}}, pipe_desr_exc_3} + | |
4849 | {{3 {1'b0}}, m_desr_exc_3} + | |
4850 | {{3 {1'b0}}, l_desr_exc_3} + | |
4851 | {{3 {1'b0}}, d_desr_exc_3} + | |
4852 | {{3 {1'b0}}, l2_desr_exc_3} + | |
4853 | {{3 {1'b0}}, s_desr_exc_3} + | |
4854 | {{3 {1'b0}}, mamu_desr_exc_3} + | |
4855 | {{3 {1'b0}}, ma_desr_exc_3} + | |
4856 | {{3 {1'b0}}, cwq_desr_exc_3} + | |
4857 | {{3 {1'b0}}, t_desr_exc_3}) > 4'b0001) | | |
4858 | (dfd_desr_f[3] & ~rd_desr_dec[3]); | |
4859 | assign ras_desr_me_2 = | |
4860 | (({{3 {1'b0}}, pipe_desr_exc_2} + | |
4861 | {{3 {1'b0}}, m_desr_exc_2} + | |
4862 | {{3 {1'b0}}, l_desr_exc_2} + | |
4863 | {{3 {1'b0}}, d_desr_exc_2} + | |
4864 | {{3 {1'b0}}, l2_desr_exc_2} + | |
4865 | {{3 {1'b0}}, s_desr_exc_2} + | |
4866 | {{3 {1'b0}}, mamu_desr_exc_2} + | |
4867 | {{3 {1'b0}}, ma_desr_exc_2} + | |
4868 | {{3 {1'b0}}, cwq_desr_exc_2} + | |
4869 | {{3 {1'b0}}, t_desr_exc_2}) > 4'b0001) | | |
4870 | (dfd_desr_f[2] & ~rd_desr_dec[2]); | |
4871 | assign ras_desr_me_1 = | |
4872 | (({{3 {1'b0}}, pipe_desr_exc_1} + | |
4873 | {{3 {1'b0}}, m_desr_exc_1} + | |
4874 | {{3 {1'b0}}, l_desr_exc_1} + | |
4875 | {{3 {1'b0}}, d_desr_exc_1} + | |
4876 | {{3 {1'b0}}, l2_desr_exc_1} + | |
4877 | {{3 {1'b0}}, s_desr_exc_1} + | |
4878 | {{3 {1'b0}}, mamu_desr_exc_1} + | |
4879 | {{3 {1'b0}}, ma_desr_exc_1} + | |
4880 | {{3 {1'b0}}, cwq_desr_exc_1} + | |
4881 | {{3 {1'b0}}, t_desr_exc_1}) > 4'b0001) | | |
4882 | (dfd_desr_f[1] & ~rd_desr_dec[1]); | |
4883 | assign ras_desr_me_0 = | |
4884 | (({{3 {1'b0}}, pipe_desr_exc_0} + | |
4885 | {{3 {1'b0}}, m_desr_exc_0} + | |
4886 | {{3 {1'b0}}, l_desr_exc_0} + | |
4887 | {{3 {1'b0}}, d_desr_exc_0} + | |
4888 | {{3 {1'b0}}, l2_desr_exc_0} + | |
4889 | {{3 {1'b0}}, s_desr_exc_0} + | |
4890 | {{3 {1'b0}}, mamu_desr_exc_0} + | |
4891 | {{3 {1'b0}}, ma_desr_exc_0} + | |
4892 | {{3 {1'b0}}, cwq_desr_exc_0} + | |
4893 | {{3 {1'b0}}, t_desr_exc_0}) > 4'b0001) | | |
4894 | (dfd_desr_f[0] & ~rd_desr_dec[0]); | |
4895 | ||
4896 | ||
4897 | assign ras_desr_ea_7[10:0] = | |
4898 | ({{2 {1'b0}}, pipe_desr_ea_7[8:0]} & {11 {take_pipe_7}}) | | |
4899 | ({{2 {1'b0}}, d_desr_ea_7[8:0]} & {11 { take_d_7}}) | | |
4900 | ({{8 {1'b0}}, s_desr_ea_7[2:0]} & {11 { take_s_7}}) | | |
4901 | ( mamu_desr_ea_7[10:0] & {11 {take_mamu_7}}) | | |
4902 | ({{1 {1'b0}}, t_desr_ea_7[9:0]} & {11 { take_t_7}}) ; | |
4903 | assign ras_desr_ea_6[10:0] = | |
4904 | ({{2 {1'b0}}, pipe_desr_ea_6[8:0]} & {11 {take_pipe_6}}) | | |
4905 | ({{2 {1'b0}}, d_desr_ea_6[8:0]} & {11 { take_d_6}}) | | |
4906 | ({{8 {1'b0}}, s_desr_ea_6[2:0]} & {11 { take_s_6}}) | | |
4907 | ( mamu_desr_ea_6[10:0] & {11 {take_mamu_6}}) | | |
4908 | ({{1 {1'b0}}, t_desr_ea_6[9:0]} & {11 { take_t_6}}) ; | |
4909 | assign ras_desr_ea_5[10:0] = | |
4910 | ({{2 {1'b0}}, pipe_desr_ea_5[8:0]} & {11 {take_pipe_5}}) | | |
4911 | ({{2 {1'b0}}, d_desr_ea_5[8:0]} & {11 { take_d_5}}) | | |
4912 | ({{8 {1'b0}}, s_desr_ea_5[2:0]} & {11 { take_s_5}}) | | |
4913 | ( mamu_desr_ea_5[10:0] & {11 {take_mamu_5}}) | | |
4914 | ({{1 {1'b0}}, t_desr_ea_5[9:0]} & {11 { take_t_5}}) ; | |
4915 | assign ras_desr_ea_4[10:0] = | |
4916 | ({{2 {1'b0}}, pipe_desr_ea_4[8:0]} & {11 {take_pipe_4}}) | | |
4917 | ({{2 {1'b0}}, d_desr_ea_4[8:0]} & {11 { take_d_4}}) | | |
4918 | ({{8 {1'b0}}, s_desr_ea_4[2:0]} & {11 { take_s_4}}) | | |
4919 | ( mamu_desr_ea_4[10:0] & {11 {take_mamu_4}}) | | |
4920 | ({{1 {1'b0}}, t_desr_ea_4[9:0]} & {11 { take_t_4}}) ; | |
4921 | assign ras_desr_ea_3[10:0] = | |
4922 | ({{2 {1'b0}}, pipe_desr_ea_3[8:0]} & {11 {take_pipe_3}}) | | |
4923 | ({{2 {1'b0}}, d_desr_ea_3[8:0]} & {11 { take_d_3}}) | | |
4924 | ({{8 {1'b0}}, s_desr_ea_3[2:0]} & {11 { take_s_3}}) | | |
4925 | ( mamu_desr_ea_3[10:0] & {11 {take_mamu_3}}) | | |
4926 | ({{1 {1'b0}}, t_desr_ea_3[9:0]} & {11 { take_t_3}}) ; | |
4927 | assign ras_desr_ea_2[10:0] = | |
4928 | ({{2 {1'b0}}, pipe_desr_ea_2[8:0]} & {11 {take_pipe_2}}) | | |
4929 | ({{2 {1'b0}}, d_desr_ea_2[8:0]} & {11 { take_d_2}}) | | |
4930 | ({{8 {1'b0}}, s_desr_ea_2[2:0]} & {11 { take_s_2}}) | | |
4931 | ( mamu_desr_ea_2[10:0] & {11 {take_mamu_2}}) | | |
4932 | ({{1 {1'b0}}, t_desr_ea_2[9:0]} & {11 { take_t_2}}) ; | |
4933 | assign ras_desr_ea_1[10:0] = | |
4934 | ({{2 {1'b0}}, pipe_desr_ea_1[8:0]} & {11 {take_pipe_1}}) | | |
4935 | ({{2 {1'b0}}, d_desr_ea_1[8:0]} & {11 { take_d_1}}) | | |
4936 | ({{8 {1'b0}}, s_desr_ea_1[2:0]} & {11 { take_s_1}}) | | |
4937 | ( mamu_desr_ea_1[10:0] & {11 {take_mamu_1}}) | | |
4938 | ({{1 {1'b0}}, t_desr_ea_1[9:0]} & {11 { take_t_1}}) ; | |
4939 | assign ras_desr_ea_0[10:0] = | |
4940 | ({{2 {1'b0}}, pipe_desr_ea_0[8:0]} & {11 {take_pipe_0}}) | | |
4941 | ({{2 {1'b0}}, d_desr_ea_0[8:0]} & {11 { take_d_0}}) | | |
4942 | ({{8 {1'b0}}, s_desr_ea_0[2:0]} & {11 { take_s_0}}) | | |
4943 | ( mamu_desr_ea_0[10:0] & {11 {take_mamu_0}}) | | |
4944 | ({{1 {1'b0}}, t_desr_ea_0[9:0]} & {11 { take_t_0}}) ; | |
4945 | ||
4946 | ||
4947 | ||
4948 | ////////////////////////////////////////////////////////////////////////////// | |
4949 | // | |
4950 | // Handle fatal errors | |
4951 | // | |
4952 | // FESR | |
4953 | // sbdiou 01 | |
4954 | // sbapp 10 | |
4955 | ||
4956 | tlu_ras_ctl_msff_ctl_macro__width_1 sbdiou_lat ( | |
4957 | .scan_in(sbdiou_lat_scanin), | |
4958 | .scan_out(sbdiou_lat_scanout), | |
4959 | .din (lsu_sbdiou_err_g ), | |
4960 | .dout (sbdiou ), | |
4961 | .l1clk(l1clk), | |
4962 | .siclk(siclk), | |
4963 | .soclk(soclk) | |
4964 | ); | |
4965 | ||
4966 | tlu_ras_ctl_msff_ctl_macro__width_1 sbapp_lat ( | |
4967 | .scan_in(sbapp_lat_scanin), | |
4968 | .scan_out(sbapp_lat_scanout), | |
4969 | .din (lsu_sbapp_err_g ), | |
4970 | .dout (sbapp ), | |
4971 | .l1clk(l1clk), | |
4972 | .siclk(siclk), | |
4973 | .soclk(soclk) | |
4974 | ); | |
4975 | ||
4976 | assign f_dec_tid[7:0] = | |
4977 | { s_tid[2] & s_tid[1] & s_tid[0], | |
4978 | s_tid[2] & s_tid[1] & ~s_tid[0], | |
4979 | s_tid[2] & ~s_tid[1] & s_tid[0], | |
4980 | s_tid[2] & ~s_tid[1] & ~s_tid[0], | |
4981 | ~s_tid[2] & s_tid[1] & s_tid[0], | |
4982 | ~s_tid[2] & s_tid[1] & ~s_tid[0], | |
4983 | ~s_tid[2] & ~s_tid[1] & s_tid[0], | |
4984 | ~s_tid[2] & ~s_tid[1] & ~s_tid[0]} & | |
4985 | {8 {sbdiou | sbapp}}; | |
4986 | ||
4987 | assign ras_fesr_et_7[61:60] = | |
4988 | {sbapp, sbdiou} & {2 {f_dec_tid[7]}}; | |
4989 | assign ras_fesr_et_6[61:60] = | |
4990 | {sbapp, sbdiou} & {2 {f_dec_tid[6]}}; | |
4991 | assign ras_fesr_et_5[61:60] = | |
4992 | {sbapp, sbdiou} & {2 {f_dec_tid[5]}}; | |
4993 | assign ras_fesr_et_4[61:60] = | |
4994 | {sbapp, sbdiou} & {2 {f_dec_tid[4]}}; | |
4995 | assign ras_fesr_et_3[61:60] = | |
4996 | {sbapp, sbdiou} & {2 {f_dec_tid[3]}}; | |
4997 | assign ras_fesr_et_2[61:60] = | |
4998 | {sbapp, sbdiou} & {2 {f_dec_tid[2]}}; | |
4999 | assign ras_fesr_et_1[61:60] = | |
5000 | {sbapp, sbdiou} & {2 {f_dec_tid[1]}}; | |
5001 | assign ras_fesr_et_0[61:60] = | |
5002 | {sbapp, sbdiou} & {2 {f_dec_tid[0]}}; | |
5003 | ||
5004 | assign write_fesr[7:0] = | |
5005 | f_dec_tid[7:0]; | |
5006 | ||
5007 | assign ras_fesr_en[7:0] = | |
5008 | write_fesr[7:0] | ras_rd_fesr[7:0] | update_priv[7:0]; | |
5009 | ||
5010 | assign ras_write_fesr[7:0] = | |
5011 | write_fesr[7:0] & (~dfd_fesr_f[7:0] | ras_rd_fesr[7:0]); | |
5012 | ||
5013 | assign ras_fesr_ea_7[59:55] = | |
5014 | {fesr_priv[1:0], s_dsfar[2:0]} & {5 {f_dec_tid[7]}}; | |
5015 | assign ras_fesr_ea_6[59:55] = | |
5016 | {fesr_priv[1:0], s_dsfar[2:0]} & {5 {f_dec_tid[6]}}; | |
5017 | assign ras_fesr_ea_5[59:55] = | |
5018 | {fesr_priv[1:0], s_dsfar[2:0]} & {5 {f_dec_tid[5]}}; | |
5019 | assign ras_fesr_ea_4[59:55] = | |
5020 | {fesr_priv[1:0], s_dsfar[2:0]} & {5 {f_dec_tid[4]}}; | |
5021 | assign ras_fesr_ea_3[59:55] = | |
5022 | {fesr_priv[1:0], s_dsfar[2:0]} & {5 {f_dec_tid[3]}}; | |
5023 | assign ras_fesr_ea_2[59:55] = | |
5024 | {fesr_priv[1:0], s_dsfar[2:0]} & {5 {f_dec_tid[2]}}; | |
5025 | assign ras_fesr_ea_1[59:55] = | |
5026 | {fesr_priv[1:0], s_dsfar[2:0]} & {5 {f_dec_tid[1]}}; | |
5027 | assign ras_fesr_ea_0[59:55] = | |
5028 | {fesr_priv[1:0], s_dsfar[2:0]} & {5 {f_dec_tid[0]}}; | |
5029 | ||
5030 | ||
5031 | ||
5032 | ////////////////////////////////////////////////////////////////////////////// | |
5033 | // | |
5034 | // Support debug event control register function | |
5035 | // | |
5036 | // error_event_1 error_event_0 meaning | |
5037 | // 0 0 no event | |
5038 | // 0 1 precise error | |
5039 | // 1 0 disrupting error | |
5040 | // 1 1 deferred error | |
5041 | ||
5042 | assign error_event_1_in[7:0] = | |
5043 | write_desr[7:0] | | |
5044 | write_fesr[7:0]; | |
5045 | ||
5046 | assign error_event_0_in[7:0] = | |
5047 | precise_i_error[7:0] | precise_d_error[7:0] | | |
5048 | write_fesr[7:0]; | |
5049 | ||
5050 | tlu_ras_ctl_msff_ctl_macro__width_8 event_1_lat ( | |
5051 | .scan_in(event_1_lat_scanin), | |
5052 | .scan_out(event_1_lat_scanout), | |
5053 | .din (error_event_1_in [7:0] ), | |
5054 | .dout (error_event_1 [7:0] ), | |
5055 | .l1clk(l1clk), | |
5056 | .siclk(siclk), | |
5057 | .soclk(soclk) | |
5058 | ); | |
5059 | ||
5060 | tlu_ras_ctl_msff_ctl_macro__width_8 event_0_lat ( | |
5061 | .scan_in(event_0_lat_scanin), | |
5062 | .scan_out(event_0_lat_scanout), | |
5063 | .din (error_event_0_in [7:0] ), | |
5064 | .dout (error_event_0 [7:0] ), | |
5065 | .l1clk(l1clk), | |
5066 | .siclk(siclk), | |
5067 | .soclk(soclk) | |
5068 | ); | |
5069 | ||
5070 | assign ras_precise_error[7:0] = | |
5071 | ~error_event_1[7:0] & error_event_0[7:0]; | |
5072 | ||
5073 | assign ras_disrupting_error[7:0] = | |
5074 | error_event_1[7:0] & ~error_event_0[7:0]; | |
5075 | ||
5076 | assign ras_deferred_error[7:0] = | |
5077 | error_event_1[7:0] & error_event_0[7:0]; | |
5078 | ||
5079 | ||
5080 | ||
5081 | ////////////////////////////////////////////////////////////////////////////// | |
5082 | // | |
5083 | // Spares | |
5084 | // | |
5085 | ||
5086 | // Each pack has one flop | |
5087 | tlu_ras_ctl_spare_ctl_macro__num_16 spares ( | |
5088 | .scan_in(spares_scanin), | |
5089 | .scan_out(spares_scanout), | |
5090 | .l1clk (l1clk ), | |
5091 | .siclk(siclk), | |
5092 | .soclk(soclk) | |
5093 | ); | |
5094 | ||
5095 | ||
5096 | // Add some more flops | |
5097 | // sparex_lat gets placed with spare pack x | |
5098 | tlu_ras_ctl_msff_ctl_macro__width_1 spare0_lat ( | |
5099 | .scan_in(spare0_lat_scanin), | |
5100 | .scan_out(spare0_lat_scanout), | |
5101 | .din (1'b0 ), | |
5102 | .dout (spare0_unused ), | |
5103 | .l1clk(l1clk), | |
5104 | .siclk(siclk), | |
5105 | .soclk(soclk) | |
5106 | ); | |
5107 | ||
5108 | tlu_ras_ctl_msff_ctl_macro__width_1 spare1_lat ( | |
5109 | .scan_in(spare1_lat_scanin), | |
5110 | .scan_out(spare1_lat_scanout), | |
5111 | .din (1'b0 ), | |
5112 | .dout (spare1_unused ), | |
5113 | .l1clk(l1clk), | |
5114 | .siclk(siclk), | |
5115 | .soclk(soclk) | |
5116 | ); | |
5117 | ||
5118 | tlu_ras_ctl_msff_ctl_macro__width_1 spare2_lat ( | |
5119 | .scan_in(spare2_lat_scanin), | |
5120 | .scan_out(spare2_lat_scanout), | |
5121 | .din (1'b0 ), | |
5122 | .dout (spare2_unused ), | |
5123 | .l1clk(l1clk), | |
5124 | .siclk(siclk), | |
5125 | .soclk(soclk) | |
5126 | ); | |
5127 | ||
5128 | tlu_ras_ctl_msff_ctl_macro__width_1 spare3_lat ( | |
5129 | .scan_in(spare3_lat_scanin), | |
5130 | .scan_out(spare3_lat_scanout), | |
5131 | .din (1'b0 ), | |
5132 | .dout (spare3_unused ), | |
5133 | .l1clk(l1clk), | |
5134 | .siclk(siclk), | |
5135 | .soclk(soclk) | |
5136 | ); | |
5137 | ||
5138 | tlu_ras_ctl_msff_ctl_macro__width_1 spare4_lat ( | |
5139 | .scan_in(spare4_lat_scanin), | |
5140 | .scan_out(spare4_lat_scanout), | |
5141 | .din (1'b0 ), | |
5142 | .dout (spare4_unused ), | |
5143 | .l1clk(l1clk), | |
5144 | .siclk(siclk), | |
5145 | .soclk(soclk) | |
5146 | ); | |
5147 | ||
5148 | tlu_ras_ctl_msff_ctl_macro__width_1 spare5_lat ( | |
5149 | .scan_in(spare5_lat_scanin), | |
5150 | .scan_out(spare5_lat_scanout), | |
5151 | .din (1'b0 ), | |
5152 | .dout (spare5_unused ), | |
5153 | .l1clk(l1clk), | |
5154 | .siclk(siclk), | |
5155 | .soclk(soclk) | |
5156 | ); | |
5157 | ||
5158 | tlu_ras_ctl_msff_ctl_macro__width_1 spare6_lat ( | |
5159 | .scan_in(spare6_lat_scanin), | |
5160 | .scan_out(spare6_lat_scanout), | |
5161 | .din (1'b0 ), | |
5162 | .dout (spare6_unused ), | |
5163 | .l1clk(l1clk), | |
5164 | .siclk(siclk), | |
5165 | .soclk(soclk) | |
5166 | ); | |
5167 | ||
5168 | tlu_ras_ctl_msff_ctl_macro__width_1 spare7_lat ( | |
5169 | .scan_in(spare7_lat_scanin), | |
5170 | .scan_out(spare7_lat_scanout), | |
5171 | .din (1'b0 ), | |
5172 | .dout (spare7_unused ), | |
5173 | .l1clk(l1clk), | |
5174 | .siclk(siclk), | |
5175 | .soclk(soclk) | |
5176 | ); | |
5177 | ||
5178 | tlu_ras_ctl_msff_ctl_macro__width_1 spare8_lat ( | |
5179 | .scan_in(spare8_lat_scanin), | |
5180 | .scan_out(spare8_lat_scanout), | |
5181 | .din (1'b0 ), | |
5182 | .dout (spare8_unused ), | |
5183 | .l1clk(l1clk), | |
5184 | .siclk(siclk), | |
5185 | .soclk(soclk) | |
5186 | ); | |
5187 | ||
5188 | tlu_ras_ctl_msff_ctl_macro__width_1 spare9_lat ( | |
5189 | .scan_in(spare9_lat_scanin), | |
5190 | .scan_out(spare9_lat_scanout), | |
5191 | .din (1'b0 ), | |
5192 | .dout (spare9_unused ), | |
5193 | .l1clk(l1clk), | |
5194 | .siclk(siclk), | |
5195 | .soclk(soclk) | |
5196 | ); | |
5197 | ||
5198 | tlu_ras_ctl_msff_ctl_macro__width_1 spare10_lat ( | |
5199 | .scan_in(spare10_lat_scanin), | |
5200 | .scan_out(spare10_lat_scanout), | |
5201 | .din (1'b0 ), | |
5202 | .dout (spare10_unused ), | |
5203 | .l1clk(l1clk), | |
5204 | .siclk(siclk), | |
5205 | .soclk(soclk) | |
5206 | ); | |
5207 | ||
5208 | tlu_ras_ctl_msff_ctl_macro__width_1 spare11_lat ( | |
5209 | .scan_in(spare11_lat_scanin), | |
5210 | .scan_out(spare11_lat_scanout), | |
5211 | .din (1'b0 ), | |
5212 | .dout (spare11_unused ), | |
5213 | .l1clk(l1clk), | |
5214 | .siclk(siclk), | |
5215 | .soclk(soclk) | |
5216 | ); | |
5217 | ||
5218 | tlu_ras_ctl_msff_ctl_macro__width_1 spare12_lat ( | |
5219 | .scan_in(spare12_lat_scanin), | |
5220 | .scan_out(spare12_lat_scanout), | |
5221 | .din (1'b0 ), | |
5222 | .dout (spare12_unused ), | |
5223 | .l1clk(l1clk), | |
5224 | .siclk(siclk), | |
5225 | .soclk(soclk) | |
5226 | ); | |
5227 | ||
5228 | tlu_ras_ctl_msff_ctl_macro__width_1 spare13_lat ( | |
5229 | .scan_in(spare13_lat_scanin), | |
5230 | .scan_out(spare13_lat_scanout), | |
5231 | .din (1'b0 ), | |
5232 | .dout (spare13_unused ), | |
5233 | .l1clk(l1clk), | |
5234 | .siclk(siclk), | |
5235 | .soclk(soclk) | |
5236 | ); | |
5237 | ||
5238 | tlu_ras_ctl_msff_ctl_macro__width_1 spare14_lat ( | |
5239 | .scan_in(spare14_lat_scanin), | |
5240 | .scan_out(spare14_lat_scanout), | |
5241 | .din (1'b0 ), | |
5242 | .dout (spare14_unused ), | |
5243 | .l1clk(l1clk), | |
5244 | .siclk(siclk), | |
5245 | .soclk(soclk) | |
5246 | ); | |
5247 | ||
5248 | tlu_ras_ctl_msff_ctl_macro__width_1 spare15_lat ( | |
5249 | .scan_in(spare15_lat_scanin), | |
5250 | .scan_out(spare15_lat_scanout), | |
5251 | .din (1'b0 ), | |
5252 | .dout (spare15_unused ), | |
5253 | .l1clk(l1clk), | |
5254 | .siclk(siclk), | |
5255 | .soclk(soclk) | |
5256 | ); | |
5257 | ||
5258 | ||
5259 | ||
5260 | supply0 vss; // <- port for ground | |
5261 | supply1 vdd; // <- port for power | |
5262 | ||
5263 | // fixscan start: | |
5264 | assign twocycle_inst_b_lat_scanin = scan_in ; | |
5265 | assign inst_valid_b_lat_scanin = twocycle_inst_b_lat_scanout; | |
5266 | assign w_en_lat_scanin = inst_valid_b_lat_scanout ; | |
5267 | assign w1_en_lat_scanin = w_en_lat_scanout ; | |
5268 | assign inst_valid_w_lat_scanin = w1_en_lat_scanout ; | |
5269 | assign block_store_w_lat_scanin = inst_valid_w_lat_scanout ; | |
5270 | assign tid1_b_lat_scanin = block_store_w_lat_scanout; | |
5271 | assign tid0_b_lat_scanin = tid1_b_lat_scanout ; | |
5272 | assign tid1_w_lat_scanin = tid0_b_lat_scanout ; | |
5273 | assign tid0_w_lat_scanin = tid1_w_lat_scanout ; | |
5274 | assign fgu_inst_b_lat_scanin = tid0_w_lat_scanout ; | |
5275 | assign fgu_inst_w_lat_scanin = fgu_inst_b_lat_scanout ; | |
5276 | assign lsu_inst_b_lat_scanin = fgu_inst_w_lat_scanout ; | |
5277 | assign i_isfsr1_b_lat_scanin = lsu_inst_b_lat_scanout ; | |
5278 | assign i_isfsr0_b_lat_scanin = i_isfsr1_b_lat_scanout ; | |
5279 | assign i_desr1_b_lat_scanin = i_isfsr0_b_lat_scanout ; | |
5280 | assign i_desr0_b_lat_scanin = i_desr1_b_lat_scanout ; | |
5281 | assign irf0_ecc_addr_b_lat_scanin = i_desr0_b_lat_scanout ; | |
5282 | assign irf1_ecc_addr_b_lat_scanin = irf0_ecc_addr_b_lat_scanout; | |
5283 | assign irf0_ecc_check_b_lat_scanin = irf1_ecc_addr_b_lat_scanout; | |
5284 | assign irf1_ecc_check_b_lat_scanin = irf0_ecc_check_b_lat_scanout; | |
5285 | assign i_isfsr1_w_lat_scanin = irf1_ecc_check_b_lat_scanout; | |
5286 | assign i_isfsr0_w_lat_scanin = i_isfsr1_w_lat_scanout ; | |
5287 | assign i_desr1_w_lat_scanin = i_isfsr0_w_lat_scanout ; | |
5288 | assign i_desr0_w_lat_scanin = i_desr1_w_lat_scanout ; | |
5289 | assign irfu_w_lat_scanin = i_desr0_w_lat_scanout ; | |
5290 | assign irfc_w_lat_scanin = irfu_w_lat_scanout ; | |
5291 | assign seen_bsee_lat_scanin = irfc_w_lat_scanout ; | |
5292 | assign dttp_w_lat_scanin = seen_bsee_lat_scanout ; | |
5293 | assign dtmh_w_lat_scanin = dttp_w_lat_scanout ; | |
5294 | assign dtdp_w_lat_scanin = dtmh_w_lat_scanout ; | |
5295 | assign irf0_ecc_addr_w_lat_scanin = dtdp_w_lat_scanout ; | |
5296 | assign irf1_ecc_addr_w_lat_scanin = irf0_ecc_addr_w_lat_scanout; | |
5297 | assign irf0_ecc_check_w_lat_scanin = irf1_ecc_addr_w_lat_scanout; | |
5298 | assign irf1_ecc_check_w_lat_scanin = irf0_ecc_check_w_lat_scanout; | |
5299 | assign frf_ecc_addr_w_lat_scanin = irf1_ecc_check_w_lat_scanout; | |
5300 | assign frf_ecc_check_w_lat_scanin = frf_ecc_addr_w_lat_scanout; | |
5301 | assign ecc_w1_lat_scanin = frf_ecc_check_w_lat_scanout; | |
5302 | assign tid1_w1_lat_scanin = ecc_w1_lat_scanout ; | |
5303 | assign tid0_w1_lat_scanin = tid1_w1_lat_scanout ; | |
5304 | assign pipe_dsfsr1_lat_scanin = tid0_w1_lat_scanout ; | |
5305 | assign pipe_dsfsr0_lat_scanin = pipe_dsfsr1_lat_scanout ; | |
5306 | assign pipe_dsfar1_lat_scanin = pipe_dsfsr0_lat_scanout ; | |
5307 | assign pipe_dsfar0_lat_scanin = pipe_dsfar1_lat_scanout ; | |
5308 | assign load_dsfar_lat_scanin = pipe_dsfar0_lat_scanout ; | |
5309 | assign i_desr1_w1_lat_scanin = load_dsfar_lat_scanout ; | |
5310 | assign i_desr0_w1_lat_scanin = i_desr1_w1_lat_scanout ; | |
5311 | assign excp_way_lat_scanin = i_desr0_w1_lat_scanout ; | |
5312 | assign ic_way7_lat_scanin = excp_way_lat_scanout ; | |
5313 | assign ic_way6_lat_scanin = ic_way7_lat_scanout ; | |
5314 | assign ic_way5_lat_scanin = ic_way6_lat_scanout ; | |
5315 | assign ic_way4_lat_scanin = ic_way5_lat_scanout ; | |
5316 | assign ic_way3_lat_scanin = ic_way4_lat_scanout ; | |
5317 | assign ic_way2_lat_scanin = ic_way3_lat_scanout ; | |
5318 | assign ic_way1_lat_scanin = ic_way2_lat_scanout ; | |
5319 | assign ic_way0_lat_scanin = ic_way1_lat_scanout ; | |
5320 | assign pc_1_w1_lat_scanin = ic_way0_lat_scanout ; | |
5321 | assign pc_0_w1_lat_scanin = pc_1_w1_lat_scanout ; | |
5322 | assign it2lc_lat_scanin = pc_0_w1_lat_scanout ; | |
5323 | assign dt2lc_lat_scanin = it2lc_lat_scanout ; | |
5324 | assign tca_error_lat_scanin = dt2lc_lat_scanout ; | |
5325 | assign l_dsfar_lat_scanin = tca_error_lat_scanout ; | |
5326 | assign l_tid_lat_scanin = l_dsfar_lat_scanout ; | |
5327 | assign dcl2c_lat_scanin = l_tid_lat_scanout ; | |
5328 | assign dcl2u_lat_scanin = dcl2c_lat_scanout ; | |
5329 | assign dcl2nd_lat_scanin = dcl2u_lat_scanout ; | |
5330 | assign dcsoc_lat_scanin = dcl2nd_lat_scanout ; | |
5331 | assign s_dsfar_lat_scanin = dcsoc_lat_scanout ; | |
5332 | assign s_tid_lat_scanin = s_dsfar_lat_scanout ; | |
5333 | assign stb_flush_lat_scanin = s_tid_lat_scanout ; | |
5334 | assign sbdlc_lat_scanin = stb_flush_lat_scanout ; | |
5335 | assign sbdlu_lat_scanin = sbdlc_lat_scanout ; | |
5336 | assign asi_rd_ctl_lat_scanin = sbdlu_lat_scanout ; | |
5337 | assign dcvp_lat_scanin = asi_rd_ctl_lat_scanout ; | |
5338 | assign dctp_lat_scanin = dcvp_lat_scanout ; | |
5339 | assign dctm_lat_scanin = dctp_lat_scanout ; | |
5340 | assign dcdp_lat_scanin = dctm_lat_scanout ; | |
5341 | assign cxi_lat_scanin = dcdp_lat_scanout ; | |
5342 | assign sbdpc_lat_scanin = cxi_lat_scanout ; | |
5343 | assign sbdpu_lat_scanin = sbdpc_lat_scanout ; | |
5344 | assign mamu_err_lat_scanin = sbdpu_lat_scanout ; | |
5345 | assign ma_tid_lat_scanin = mamu_err_lat_scanout ; | |
5346 | assign cwq_tid_lat_scanin = ma_tid_lat_scanout ; | |
5347 | assign spu_error_lat_scanin = cwq_tid_lat_scanout ; | |
5348 | assign sbdiou_lat_scanin = spu_error_lat_scanout ; | |
5349 | assign sbapp_lat_scanin = sbdiou_lat_scanout ; | |
5350 | assign event_1_lat_scanin = sbapp_lat_scanout ; | |
5351 | assign event_0_lat_scanin = event_1_lat_scanout ; | |
5352 | assign spares_scanin = event_0_lat_scanout ; | |
5353 | assign spare0_lat_scanin = spares_scanout ; | |
5354 | assign spare1_lat_scanin = spare0_lat_scanout ; | |
5355 | assign spare2_lat_scanin = spare1_lat_scanout ; | |
5356 | assign spare3_lat_scanin = spare2_lat_scanout ; | |
5357 | assign spare4_lat_scanin = spare3_lat_scanout ; | |
5358 | assign spare5_lat_scanin = spare4_lat_scanout ; | |
5359 | assign spare6_lat_scanin = spare5_lat_scanout ; | |
5360 | assign spare7_lat_scanin = spare6_lat_scanout ; | |
5361 | assign spare8_lat_scanin = spare7_lat_scanout ; | |
5362 | assign spare9_lat_scanin = spare8_lat_scanout ; | |
5363 | assign spare10_lat_scanin = spare9_lat_scanout ; | |
5364 | assign spare11_lat_scanin = spare10_lat_scanout ; | |
5365 | assign spare12_lat_scanin = spare11_lat_scanout ; | |
5366 | assign spare13_lat_scanin = spare12_lat_scanout ; | |
5367 | assign spare14_lat_scanin = spare13_lat_scanout ; | |
5368 | assign spare15_lat_scanin = spare14_lat_scanout ; | |
5369 | assign scan_out = spare15_lat_scanout ; | |
5370 | ||
5371 | assign isfsr_7_lat_wmr_scanin = wmr_scan_in ; | |
5372 | assign isfsr_6_lat_wmr_scanin = isfsr_7_lat_wmr_scanout ; | |
5373 | assign isfsr_5_lat_wmr_scanin = isfsr_6_lat_wmr_scanout ; | |
5374 | assign isfsr_4_lat_wmr_scanin = isfsr_5_lat_wmr_scanout ; | |
5375 | assign isfsr_3_lat_wmr_scanin = isfsr_4_lat_wmr_scanout ; | |
5376 | assign isfsr_2_lat_wmr_scanin = isfsr_3_lat_wmr_scanout ; | |
5377 | assign isfsr_1_lat_wmr_scanin = isfsr_2_lat_wmr_scanout ; | |
5378 | assign isfsr_0_lat_wmr_scanin = isfsr_1_lat_wmr_scanout ; | |
5379 | assign dsfsr_7_lat_wmr_scanin = isfsr_0_lat_wmr_scanout ; | |
5380 | assign dsfsr_6_lat_wmr_scanin = dsfsr_7_lat_wmr_scanout ; | |
5381 | assign dsfsr_5_lat_wmr_scanin = dsfsr_6_lat_wmr_scanout ; | |
5382 | assign dsfsr_4_lat_wmr_scanin = dsfsr_5_lat_wmr_scanout ; | |
5383 | assign dsfsr_3_lat_wmr_scanin = dsfsr_4_lat_wmr_scanout ; | |
5384 | assign dsfsr_2_lat_wmr_scanin = dsfsr_3_lat_wmr_scanout ; | |
5385 | assign dsfsr_1_lat_wmr_scanin = dsfsr_2_lat_wmr_scanout ; | |
5386 | assign dsfsr_0_lat_wmr_scanin = dsfsr_1_lat_wmr_scanout ; | |
5387 | assign wmr_scan_out = dsfsr_0_lat_wmr_scanout ; | |
5388 | // fixscan end: | |
5389 | endmodule | |
5390 | ||
5391 | ||
5392 | ||
5393 | ||
5394 | ||
5395 | ||
5396 | ||
5397 | // any PARAMS parms go into naming of macro | |
5398 | ||
5399 | module tlu_ras_ctl_l1clkhdr_ctl_macro ( | |
5400 | l2clk, | |
5401 | l1en, | |
5402 | pce_ov, | |
5403 | stop, | |
5404 | se, | |
5405 | l1clk); | |
5406 | ||
5407 | ||
5408 | input l2clk; | |
5409 | input l1en; | |
5410 | input pce_ov; | |
5411 | input stop; | |
5412 | input se; | |
5413 | output l1clk; | |
5414 | ||
5415 | ||
5416 | ||
5417 | ||
5418 | ||
5419 | cl_sc1_l1hdr_8x c_0 ( | |
5420 | ||
5421 | ||
5422 | .l2clk(l2clk), | |
5423 | .pce(l1en), | |
5424 | .l1clk(l1clk), | |
5425 | .se(se), | |
5426 | .pce_ov(pce_ov), | |
5427 | .stop(stop) | |
5428 | ); | |
5429 | ||
5430 | ||
5431 | ||
5432 | endmodule | |
5433 | ||
5434 | ||
5435 | ||
5436 | ||
5437 | ||
5438 | ||
5439 | ||
5440 | ||
5441 | ||
5442 | ||
5443 | ||
5444 | ||
5445 | ||
5446 | // any PARAMS parms go into naming of macro | |
5447 | ||
5448 | module tlu_ras_ctl_msff_ctl_macro__width_2 ( | |
5449 | din, | |
5450 | l1clk, | |
5451 | scan_in, | |
5452 | siclk, | |
5453 | soclk, | |
5454 | dout, | |
5455 | scan_out); | |
5456 | wire [1:0] fdin; | |
5457 | wire [0:0] so; | |
5458 | ||
5459 | input [1:0] din; | |
5460 | input l1clk; | |
5461 | input scan_in; | |
5462 | ||
5463 | ||
5464 | input siclk; | |
5465 | input soclk; | |
5466 | ||
5467 | output [1:0] dout; | |
5468 | output scan_out; | |
5469 | assign fdin[1:0] = din[1:0]; | |
5470 | ||
5471 | ||
5472 | ||
5473 | ||
5474 | ||
5475 | ||
5476 | dff #(2) d0_0 ( | |
5477 | .l1clk(l1clk), | |
5478 | .siclk(siclk), | |
5479 | .soclk(soclk), | |
5480 | .d(fdin[1:0]), | |
5481 | .si({scan_in,so[0:0]}), | |
5482 | .so({so[0:0],scan_out}), | |
5483 | .q(dout[1:0]) | |
5484 | ); | |
5485 | ||
5486 | ||
5487 | ||
5488 | ||
5489 | ||
5490 | ||
5491 | ||
5492 | ||
5493 | ||
5494 | ||
5495 | ||
5496 | ||
5497 | endmodule | |
5498 | ||
5499 | ||
5500 | ||
5501 | ||
5502 | ||
5503 | ||
5504 | ||
5505 | ||
5506 | ||
5507 | ||
5508 | ||
5509 | ||
5510 | ||
5511 | // any PARAMS parms go into naming of macro | |
5512 | ||
5513 | module tlu_ras_ctl_msff_ctl_macro__width_1 ( | |
5514 | din, | |
5515 | l1clk, | |
5516 | scan_in, | |
5517 | siclk, | |
5518 | soclk, | |
5519 | dout, | |
5520 | scan_out); | |
5521 | wire [0:0] fdin; | |
5522 | ||
5523 | input [0:0] din; | |
5524 | input l1clk; | |
5525 | input scan_in; | |
5526 | ||
5527 | ||
5528 | input siclk; | |
5529 | input soclk; | |
5530 | ||
5531 | output [0:0] dout; | |
5532 | output scan_out; | |
5533 | assign fdin[0:0] = din[0:0]; | |
5534 | ||
5535 | ||
5536 | ||
5537 | ||
5538 | ||
5539 | ||
5540 | dff #(1) d0_0 ( | |
5541 | .l1clk(l1clk), | |
5542 | .siclk(siclk), | |
5543 | .soclk(soclk), | |
5544 | .d(fdin[0:0]), | |
5545 | .si(scan_in), | |
5546 | .so(scan_out), | |
5547 | .q(dout[0:0]) | |
5548 | ); | |
5549 | ||
5550 | ||
5551 | ||
5552 | ||
5553 | ||
5554 | ||
5555 | ||
5556 | ||
5557 | ||
5558 | ||
5559 | ||
5560 | ||
5561 | endmodule | |
5562 | ||
5563 | ||
5564 | ||
5565 | ||
5566 | ||
5567 | ||
5568 | ||
5569 | ||
5570 | ||
5571 | ||
5572 | ||
5573 | ||
5574 | ||
5575 | // any PARAMS parms go into naming of macro | |
5576 | ||
5577 | module tlu_ras_ctl_msff_ctl_macro__width_8 ( | |
5578 | din, | |
5579 | l1clk, | |
5580 | scan_in, | |
5581 | siclk, | |
5582 | soclk, | |
5583 | dout, | |
5584 | scan_out); | |
5585 | wire [7:0] fdin; | |
5586 | wire [6:0] so; | |
5587 | ||
5588 | input [7:0] din; | |
5589 | input l1clk; | |
5590 | input scan_in; | |
5591 | ||
5592 | ||
5593 | input siclk; | |
5594 | input soclk; | |
5595 | ||
5596 | output [7:0] dout; | |
5597 | output scan_out; | |
5598 | assign fdin[7:0] = din[7:0]; | |
5599 | ||
5600 | ||
5601 | ||
5602 | ||
5603 | ||
5604 | ||
5605 | dff #(8) d0_0 ( | |
5606 | .l1clk(l1clk), | |
5607 | .siclk(siclk), | |
5608 | .soclk(soclk), | |
5609 | .d(fdin[7:0]), | |
5610 | .si({scan_in,so[6:0]}), | |
5611 | .so({so[6:0],scan_out}), | |
5612 | .q(dout[7:0]) | |
5613 | ); | |
5614 | ||
5615 | ||
5616 | ||
5617 | ||
5618 | ||
5619 | ||
5620 | ||
5621 | ||
5622 | ||
5623 | ||
5624 | ||
5625 | ||
5626 | endmodule | |
5627 | ||
5628 | ||
5629 | ||
5630 | ||
5631 | ||
5632 | ||
5633 | ||
5634 | ||
5635 | ||
5636 | ||
5637 | ||
5638 | ||
5639 | ||
5640 | // any PARAMS parms go into naming of macro | |
5641 | ||
5642 | module tlu_ras_ctl_msff_ctl_macro__width_3 ( | |
5643 | din, | |
5644 | l1clk, | |
5645 | scan_in, | |
5646 | siclk, | |
5647 | soclk, | |
5648 | dout, | |
5649 | scan_out); | |
5650 | wire [2:0] fdin; | |
5651 | wire [1:0] so; | |
5652 | ||
5653 | input [2:0] din; | |
5654 | input l1clk; | |
5655 | input scan_in; | |
5656 | ||
5657 | ||
5658 | input siclk; | |
5659 | input soclk; | |
5660 | ||
5661 | output [2:0] dout; | |
5662 | output scan_out; | |
5663 | assign fdin[2:0] = din[2:0]; | |
5664 | ||
5665 | ||
5666 | ||
5667 | ||
5668 | ||
5669 | ||
5670 | dff #(3) d0_0 ( | |
5671 | .l1clk(l1clk), | |
5672 | .siclk(siclk), | |
5673 | .soclk(soclk), | |
5674 | .d(fdin[2:0]), | |
5675 | .si({scan_in,so[1:0]}), | |
5676 | .so({so[1:0],scan_out}), | |
5677 | .q(dout[2:0]) | |
5678 | ); | |
5679 | ||
5680 | ||
5681 | ||
5682 | ||
5683 | ||
5684 | ||
5685 | ||
5686 | ||
5687 | ||
5688 | ||
5689 | ||
5690 | ||
5691 | endmodule | |
5692 | ||
5693 | ||
5694 | ||
5695 | ||
5696 | ||
5697 | ||
5698 | ||
5699 | ||
5700 | ||
5701 | ||
5702 | ||
5703 | ||
5704 | ||
5705 | // any PARAMS parms go into naming of macro | |
5706 | ||
5707 | module tlu_ras_ctl_msff_ctl_macro__width_4 ( | |
5708 | din, | |
5709 | l1clk, | |
5710 | scan_in, | |
5711 | siclk, | |
5712 | soclk, | |
5713 | dout, | |
5714 | scan_out); | |
5715 | wire [3:0] fdin; | |
5716 | wire [2:0] so; | |
5717 | ||
5718 | input [3:0] din; | |
5719 | input l1clk; | |
5720 | input scan_in; | |
5721 | ||
5722 | ||
5723 | input siclk; | |
5724 | input soclk; | |
5725 | ||
5726 | output [3:0] dout; | |
5727 | output scan_out; | |
5728 | assign fdin[3:0] = din[3:0]; | |
5729 | ||
5730 | ||
5731 | ||
5732 | ||
5733 | ||
5734 | ||
5735 | dff #(4) d0_0 ( | |
5736 | .l1clk(l1clk), | |
5737 | .siclk(siclk), | |
5738 | .soclk(soclk), | |
5739 | .d(fdin[3:0]), | |
5740 | .si({scan_in,so[2:0]}), | |
5741 | .so({so[2:0],scan_out}), | |
5742 | .q(dout[3:0]) | |
5743 | ); | |
5744 | ||
5745 | ||
5746 | ||
5747 | ||
5748 | ||
5749 | ||
5750 | ||
5751 | ||
5752 | ||
5753 | ||
5754 | ||
5755 | ||
5756 | endmodule | |
5757 | ||
5758 | ||
5759 | ||
5760 | ||
5761 | ||
5762 | ||
5763 | ||
5764 | ||
5765 | ||
5766 | ||
5767 | ||
5768 | ||
5769 | ||
5770 | // any PARAMS parms go into naming of macro | |
5771 | ||
5772 | module tlu_ras_ctl_msff_ctl_macro__width_5 ( | |
5773 | din, | |
5774 | l1clk, | |
5775 | scan_in, | |
5776 | siclk, | |
5777 | soclk, | |
5778 | dout, | |
5779 | scan_out); | |
5780 | wire [4:0] fdin; | |
5781 | wire [3:0] so; | |
5782 | ||
5783 | input [4:0] din; | |
5784 | input l1clk; | |
5785 | input scan_in; | |
5786 | ||
5787 | ||
5788 | input siclk; | |
5789 | input soclk; | |
5790 | ||
5791 | output [4:0] dout; | |
5792 | output scan_out; | |
5793 | assign fdin[4:0] = din[4:0]; | |
5794 | ||
5795 | ||
5796 | ||
5797 | ||
5798 | ||
5799 | ||
5800 | dff #(5) d0_0 ( | |
5801 | .l1clk(l1clk), | |
5802 | .siclk(siclk), | |
5803 | .soclk(soclk), | |
5804 | .d(fdin[4:0]), | |
5805 | .si({scan_in,so[3:0]}), | |
5806 | .so({so[3:0],scan_out}), | |
5807 | .q(dout[4:0]) | |
5808 | ); | |
5809 | ||
5810 | ||
5811 | ||
5812 | ||
5813 | ||
5814 | ||
5815 | ||
5816 | ||
5817 | ||
5818 | ||
5819 | ||
5820 | ||
5821 | endmodule | |
5822 | ||
5823 | ||
5824 | ||
5825 | ||
5826 | ||
5827 | ||
5828 | ||
5829 | ||
5830 | ||
5831 | ||
5832 | ||
5833 | ||
5834 | ||
5835 | // any PARAMS parms go into naming of macro | |
5836 | ||
5837 | module tlu_ras_ctl_msff_ctl_macro__width_6 ( | |
5838 | din, | |
5839 | l1clk, | |
5840 | scan_in, | |
5841 | siclk, | |
5842 | soclk, | |
5843 | dout, | |
5844 | scan_out); | |
5845 | wire [5:0] fdin; | |
5846 | wire [4:0] so; | |
5847 | ||
5848 | input [5:0] din; | |
5849 | input l1clk; | |
5850 | input scan_in; | |
5851 | ||
5852 | ||
5853 | input siclk; | |
5854 | input soclk; | |
5855 | ||
5856 | output [5:0] dout; | |
5857 | output scan_out; | |
5858 | assign fdin[5:0] = din[5:0]; | |
5859 | ||
5860 | ||
5861 | ||
5862 | ||
5863 | ||
5864 | ||
5865 | dff #(6) d0_0 ( | |
5866 | .l1clk(l1clk), | |
5867 | .siclk(siclk), | |
5868 | .soclk(soclk), | |
5869 | .d(fdin[5:0]), | |
5870 | .si({scan_in,so[4:0]}), | |
5871 | .so({so[4:0],scan_out}), | |
5872 | .q(dout[5:0]) | |
5873 | ); | |
5874 | ||
5875 | ||
5876 | ||
5877 | ||
5878 | ||
5879 | ||
5880 | ||
5881 | ||
5882 | ||
5883 | ||
5884 | ||
5885 | ||
5886 | endmodule | |
5887 | ||
5888 | ||
5889 | ||
5890 | ||
5891 | ||
5892 | ||
5893 | ||
5894 | ||
5895 | ||
5896 | ||
5897 | ||
5898 | ||
5899 | ||
5900 | // any PARAMS parms go into naming of macro | |
5901 | ||
5902 | module tlu_ras_ctl_msff_ctl_macro__width_14 ( | |
5903 | din, | |
5904 | l1clk, | |
5905 | scan_in, | |
5906 | siclk, | |
5907 | soclk, | |
5908 | dout, | |
5909 | scan_out); | |
5910 | wire [13:0] fdin; | |
5911 | wire [12:0] so; | |
5912 | ||
5913 | input [13:0] din; | |
5914 | input l1clk; | |
5915 | input scan_in; | |
5916 | ||
5917 | ||
5918 | input siclk; | |
5919 | input soclk; | |
5920 | ||
5921 | output [13:0] dout; | |
5922 | output scan_out; | |
5923 | assign fdin[13:0] = din[13:0]; | |
5924 | ||
5925 | ||
5926 | ||
5927 | ||
5928 | ||
5929 | ||
5930 | dff #(14) d0_0 ( | |
5931 | .l1clk(l1clk), | |
5932 | .siclk(siclk), | |
5933 | .soclk(soclk), | |
5934 | .d(fdin[13:0]), | |
5935 | .si({scan_in,so[12:0]}), | |
5936 | .so({so[12:0],scan_out}), | |
5937 | .q(dout[13:0]) | |
5938 | ); | |
5939 | ||
5940 | ||
5941 | ||
5942 | ||
5943 | ||
5944 | ||
5945 | ||
5946 | ||
5947 | ||
5948 | ||
5949 | ||
5950 | ||
5951 | endmodule | |
5952 | ||
5953 | ||
5954 | ||
5955 | ||
5956 | ||
5957 | ||
5958 | ||
5959 | ||
5960 | ||
5961 | ||
5962 | ||
5963 | ||
5964 | ||
5965 | // any PARAMS parms go into naming of macro | |
5966 | ||
5967 | module tlu_ras_ctl_msff_ctl_macro__width_20 ( | |
5968 | din, | |
5969 | l1clk, | |
5970 | scan_in, | |
5971 | siclk, | |
5972 | soclk, | |
5973 | dout, | |
5974 | scan_out); | |
5975 | wire [19:0] fdin; | |
5976 | wire [18:0] so; | |
5977 | ||
5978 | input [19:0] din; | |
5979 | input l1clk; | |
5980 | input scan_in; | |
5981 | ||
5982 | ||
5983 | input siclk; | |
5984 | input soclk; | |
5985 | ||
5986 | output [19:0] dout; | |
5987 | output scan_out; | |
5988 | assign fdin[19:0] = din[19:0]; | |
5989 | ||
5990 | ||
5991 | ||
5992 | ||
5993 | ||
5994 | ||
5995 | dff #(20) d0_0 ( | |
5996 | .l1clk(l1clk), | |
5997 | .siclk(siclk), | |
5998 | .soclk(soclk), | |
5999 | .d(fdin[19:0]), | |
6000 | .si({scan_in,so[18:0]}), | |
6001 | .so({so[18:0],scan_out}), | |
6002 | .q(dout[19:0]) | |
6003 | ); | |
6004 | ||
6005 | ||
6006 | ||
6007 | ||
6008 | ||
6009 | ||
6010 | ||
6011 | ||
6012 | ||
6013 | ||
6014 | ||
6015 | ||
6016 | endmodule | |
6017 | ||
6018 | ||
6019 | ||
6020 | ||
6021 | ||
6022 | ||
6023 | ||
6024 | ||
6025 | ||
6026 | ||
6027 | ||
6028 | ||
6029 | ||
6030 | // any PARAMS parms go into naming of macro | |
6031 | ||
6032 | module tlu_ras_ctl_msff_ctl_macro__width_7 ( | |
6033 | din, | |
6034 | l1clk, | |
6035 | scan_in, | |
6036 | siclk, | |
6037 | soclk, | |
6038 | dout, | |
6039 | scan_out); | |
6040 | wire [6:0] fdin; | |
6041 | wire [5:0] so; | |
6042 | ||
6043 | input [6:0] din; | |
6044 | input l1clk; | |
6045 | input scan_in; | |
6046 | ||
6047 | ||
6048 | input siclk; | |
6049 | input soclk; | |
6050 | ||
6051 | output [6:0] dout; | |
6052 | output scan_out; | |
6053 | assign fdin[6:0] = din[6:0]; | |
6054 | ||
6055 | ||
6056 | ||
6057 | ||
6058 | ||
6059 | ||
6060 | dff #(7) d0_0 ( | |
6061 | .l1clk(l1clk), | |
6062 | .siclk(siclk), | |
6063 | .soclk(soclk), | |
6064 | .d(fdin[6:0]), | |
6065 | .si({scan_in,so[5:0]}), | |
6066 | .so({so[5:0],scan_out}), | |
6067 | .q(dout[6:0]) | |
6068 | ); | |
6069 | ||
6070 | ||
6071 | ||
6072 | ||
6073 | ||
6074 | ||
6075 | ||
6076 | ||
6077 | ||
6078 | ||
6079 | ||
6080 | ||
6081 | endmodule | |
6082 | ||
6083 | ||
6084 | ||
6085 | ||
6086 | ||
6087 | ||
6088 | ||
6089 | ||
6090 | ||
6091 | ||
6092 | ||
6093 | ||
6094 | ||
6095 | // any PARAMS parms go into naming of macro | |
6096 | ||
6097 | module tlu_ras_ctl_msff_ctl_macro__width_9 ( | |
6098 | din, | |
6099 | l1clk, | |
6100 | scan_in, | |
6101 | siclk, | |
6102 | soclk, | |
6103 | dout, | |
6104 | scan_out); | |
6105 | wire [8:0] fdin; | |
6106 | wire [7:0] so; | |
6107 | ||
6108 | input [8:0] din; | |
6109 | input l1clk; | |
6110 | input scan_in; | |
6111 | ||
6112 | ||
6113 | input siclk; | |
6114 | input soclk; | |
6115 | ||
6116 | output [8:0] dout; | |
6117 | output scan_out; | |
6118 | assign fdin[8:0] = din[8:0]; | |
6119 | ||
6120 | ||
6121 | ||
6122 | ||
6123 | ||
6124 | ||
6125 | dff #(9) d0_0 ( | |
6126 | .l1clk(l1clk), | |
6127 | .siclk(siclk), | |
6128 | .soclk(soclk), | |
6129 | .d(fdin[8:0]), | |
6130 | .si({scan_in,so[7:0]}), | |
6131 | .so({so[7:0],scan_out}), | |
6132 | .q(dout[8:0]) | |
6133 | ); | |
6134 | ||
6135 | ||
6136 | ||
6137 | ||
6138 | ||
6139 | ||
6140 | ||
6141 | ||
6142 | ||
6143 | ||
6144 | ||
6145 | ||
6146 | endmodule | |
6147 | ||
6148 | ||
6149 | ||
6150 | ||
6151 | ||
6152 | ||
6153 | ||
6154 | ||
6155 | ||
6156 | ||
6157 | ||
6158 | ||
6159 | ||
6160 | // any PARAMS parms go into naming of macro | |
6161 | ||
6162 | module tlu_ras_ctl_msff_ctl_macro__width_12 ( | |
6163 | din, | |
6164 | l1clk, | |
6165 | scan_in, | |
6166 | siclk, | |
6167 | soclk, | |
6168 | dout, | |
6169 | scan_out); | |
6170 | wire [11:0] fdin; | |
6171 | wire [10:0] so; | |
6172 | ||
6173 | input [11:0] din; | |
6174 | input l1clk; | |
6175 | input scan_in; | |
6176 | ||
6177 | ||
6178 | input siclk; | |
6179 | input soclk; | |
6180 | ||
6181 | output [11:0] dout; | |
6182 | output scan_out; | |
6183 | assign fdin[11:0] = din[11:0]; | |
6184 | ||
6185 | ||
6186 | ||
6187 | ||
6188 | ||
6189 | ||
6190 | dff #(12) d0_0 ( | |
6191 | .l1clk(l1clk), | |
6192 | .siclk(siclk), | |
6193 | .soclk(soclk), | |
6194 | .d(fdin[11:0]), | |
6195 | .si({scan_in,so[10:0]}), | |
6196 | .so({so[10:0],scan_out}), | |
6197 | .q(dout[11:0]) | |
6198 | ); | |
6199 | ||
6200 | ||
6201 | ||
6202 | ||
6203 | ||
6204 | ||
6205 | ||
6206 | ||
6207 | ||
6208 | ||
6209 | ||
6210 | ||
6211 | endmodule | |
6212 | ||
6213 | ||
6214 | ||
6215 | ||
6216 | ||
6217 | ||
6218 | ||
6219 | ||
6220 | ||
6221 | // Description: Spare gate macro for control blocks | |
6222 | // | |
6223 | // Param num controls the number of times the macro is added | |
6224 | // flops=0 can be used to use only combination spare logic | |
6225 | ||
6226 | ||
6227 | module tlu_ras_ctl_spare_ctl_macro__num_16 ( | |
6228 | l1clk, | |
6229 | scan_in, | |
6230 | siclk, | |
6231 | soclk, | |
6232 | scan_out); | |
6233 | wire si_0; | |
6234 | wire so_0; | |
6235 | wire spare0_flop_unused; | |
6236 | wire spare0_buf_32x_unused; | |
6237 | wire spare0_nand3_8x_unused; | |
6238 | wire spare0_inv_8x_unused; | |
6239 | wire spare0_aoi22_4x_unused; | |
6240 | wire spare0_buf_8x_unused; | |
6241 | wire spare0_oai22_4x_unused; | |
6242 | wire spare0_inv_16x_unused; | |
6243 | wire spare0_nand2_16x_unused; | |
6244 | wire spare0_nor3_4x_unused; | |
6245 | wire spare0_nand2_8x_unused; | |
6246 | wire spare0_buf_16x_unused; | |
6247 | wire spare0_nor2_16x_unused; | |
6248 | wire spare0_inv_32x_unused; | |
6249 | wire si_1; | |
6250 | wire so_1; | |
6251 | wire spare1_flop_unused; | |
6252 | wire spare1_buf_32x_unused; | |
6253 | wire spare1_nand3_8x_unused; | |
6254 | wire spare1_inv_8x_unused; | |
6255 | wire spare1_aoi22_4x_unused; | |
6256 | wire spare1_buf_8x_unused; | |
6257 | wire spare1_oai22_4x_unused; | |
6258 | wire spare1_inv_16x_unused; | |
6259 | wire spare1_nand2_16x_unused; | |
6260 | wire spare1_nor3_4x_unused; | |
6261 | wire spare1_nand2_8x_unused; | |
6262 | wire spare1_buf_16x_unused; | |
6263 | wire spare1_nor2_16x_unused; | |
6264 | wire spare1_inv_32x_unused; | |
6265 | wire si_2; | |
6266 | wire so_2; | |
6267 | wire spare2_flop_unused; | |
6268 | wire spare2_buf_32x_unused; | |
6269 | wire spare2_nand3_8x_unused; | |
6270 | wire spare2_inv_8x_unused; | |
6271 | wire spare2_aoi22_4x_unused; | |
6272 | wire spare2_buf_8x_unused; | |
6273 | wire spare2_oai22_4x_unused; | |
6274 | wire spare2_inv_16x_unused; | |
6275 | wire spare2_nand2_16x_unused; | |
6276 | wire spare2_nor3_4x_unused; | |
6277 | wire spare2_nand2_8x_unused; | |
6278 | wire spare2_buf_16x_unused; | |
6279 | wire spare2_nor2_16x_unused; | |
6280 | wire spare2_inv_32x_unused; | |
6281 | wire si_3; | |
6282 | wire so_3; | |
6283 | wire spare3_flop_unused; | |
6284 | wire spare3_buf_32x_unused; | |
6285 | wire spare3_nand3_8x_unused; | |
6286 | wire spare3_inv_8x_unused; | |
6287 | wire spare3_aoi22_4x_unused; | |
6288 | wire spare3_buf_8x_unused; | |
6289 | wire spare3_oai22_4x_unused; | |
6290 | wire spare3_inv_16x_unused; | |
6291 | wire spare3_nand2_16x_unused; | |
6292 | wire spare3_nor3_4x_unused; | |
6293 | wire spare3_nand2_8x_unused; | |
6294 | wire spare3_buf_16x_unused; | |
6295 | wire spare3_nor2_16x_unused; | |
6296 | wire spare3_inv_32x_unused; | |
6297 | wire si_4; | |
6298 | wire so_4; | |
6299 | wire spare4_flop_unused; | |
6300 | wire spare4_buf_32x_unused; | |
6301 | wire spare4_nand3_8x_unused; | |
6302 | wire spare4_inv_8x_unused; | |
6303 | wire spare4_aoi22_4x_unused; | |
6304 | wire spare4_buf_8x_unused; | |
6305 | wire spare4_oai22_4x_unused; | |
6306 | wire spare4_inv_16x_unused; | |
6307 | wire spare4_nand2_16x_unused; | |
6308 | wire spare4_nor3_4x_unused; | |
6309 | wire spare4_nand2_8x_unused; | |
6310 | wire spare4_buf_16x_unused; | |
6311 | wire spare4_nor2_16x_unused; | |
6312 | wire spare4_inv_32x_unused; | |
6313 | wire si_5; | |
6314 | wire so_5; | |
6315 | wire spare5_flop_unused; | |
6316 | wire spare5_buf_32x_unused; | |
6317 | wire spare5_nand3_8x_unused; | |
6318 | wire spare5_inv_8x_unused; | |
6319 | wire spare5_aoi22_4x_unused; | |
6320 | wire spare5_buf_8x_unused; | |
6321 | wire spare5_oai22_4x_unused; | |
6322 | wire spare5_inv_16x_unused; | |
6323 | wire spare5_nand2_16x_unused; | |
6324 | wire spare5_nor3_4x_unused; | |
6325 | wire spare5_nand2_8x_unused; | |
6326 | wire spare5_buf_16x_unused; | |
6327 | wire spare5_nor2_16x_unused; | |
6328 | wire spare5_inv_32x_unused; | |
6329 | wire si_6; | |
6330 | wire so_6; | |
6331 | wire spare6_flop_unused; | |
6332 | wire spare6_buf_32x_unused; | |
6333 | wire spare6_nand3_8x_unused; | |
6334 | wire spare6_inv_8x_unused; | |
6335 | wire spare6_aoi22_4x_unused; | |
6336 | wire spare6_buf_8x_unused; | |
6337 | wire spare6_oai22_4x_unused; | |
6338 | wire spare6_inv_16x_unused; | |
6339 | wire spare6_nand2_16x_unused; | |
6340 | wire spare6_nor3_4x_unused; | |
6341 | wire spare6_nand2_8x_unused; | |
6342 | wire spare6_buf_16x_unused; | |
6343 | wire spare6_nor2_16x_unused; | |
6344 | wire spare6_inv_32x_unused; | |
6345 | wire si_7; | |
6346 | wire so_7; | |
6347 | wire spare7_flop_unused; | |
6348 | wire spare7_buf_32x_unused; | |
6349 | wire spare7_nand3_8x_unused; | |
6350 | wire spare7_inv_8x_unused; | |
6351 | wire spare7_aoi22_4x_unused; | |
6352 | wire spare7_buf_8x_unused; | |
6353 | wire spare7_oai22_4x_unused; | |
6354 | wire spare7_inv_16x_unused; | |
6355 | wire spare7_nand2_16x_unused; | |
6356 | wire spare7_nor3_4x_unused; | |
6357 | wire spare7_nand2_8x_unused; | |
6358 | wire spare7_buf_16x_unused; | |
6359 | wire spare7_nor2_16x_unused; | |
6360 | wire spare7_inv_32x_unused; | |
6361 | wire si_8; | |
6362 | wire so_8; | |
6363 | wire spare8_flop_unused; | |
6364 | wire spare8_buf_32x_unused; | |
6365 | wire spare8_nand3_8x_unused; | |
6366 | wire spare8_inv_8x_unused; | |
6367 | wire spare8_aoi22_4x_unused; | |
6368 | wire spare8_buf_8x_unused; | |
6369 | wire spare8_oai22_4x_unused; | |
6370 | wire spare8_inv_16x_unused; | |
6371 | wire spare8_nand2_16x_unused; | |
6372 | wire spare8_nor3_4x_unused; | |
6373 | wire spare8_nand2_8x_unused; | |
6374 | wire spare8_buf_16x_unused; | |
6375 | wire spare8_nor2_16x_unused; | |
6376 | wire spare8_inv_32x_unused; | |
6377 | wire si_9; | |
6378 | wire so_9; | |
6379 | wire spare9_flop_unused; | |
6380 | wire spare9_buf_32x_unused; | |
6381 | wire spare9_nand3_8x_unused; | |
6382 | wire spare9_inv_8x_unused; | |
6383 | wire spare9_aoi22_4x_unused; | |
6384 | wire spare9_buf_8x_unused; | |
6385 | wire spare9_oai22_4x_unused; | |
6386 | wire spare9_inv_16x_unused; | |
6387 | wire spare9_nand2_16x_unused; | |
6388 | wire spare9_nor3_4x_unused; | |
6389 | wire spare9_nand2_8x_unused; | |
6390 | wire spare9_buf_16x_unused; | |
6391 | wire spare9_nor2_16x_unused; | |
6392 | wire spare9_inv_32x_unused; | |
6393 | wire si_10; | |
6394 | wire so_10; | |
6395 | wire spare10_flop_unused; | |
6396 | wire spare10_buf_32x_unused; | |
6397 | wire spare10_nand3_8x_unused; | |
6398 | wire spare10_inv_8x_unused; | |
6399 | wire spare10_aoi22_4x_unused; | |
6400 | wire spare10_buf_8x_unused; | |
6401 | wire spare10_oai22_4x_unused; | |
6402 | wire spare10_inv_16x_unused; | |
6403 | wire spare10_nand2_16x_unused; | |
6404 | wire spare10_nor3_4x_unused; | |
6405 | wire spare10_nand2_8x_unused; | |
6406 | wire spare10_buf_16x_unused; | |
6407 | wire spare10_nor2_16x_unused; | |
6408 | wire spare10_inv_32x_unused; | |
6409 | wire si_11; | |
6410 | wire so_11; | |
6411 | wire spare11_flop_unused; | |
6412 | wire spare11_buf_32x_unused; | |
6413 | wire spare11_nand3_8x_unused; | |
6414 | wire spare11_inv_8x_unused; | |
6415 | wire spare11_aoi22_4x_unused; | |
6416 | wire spare11_buf_8x_unused; | |
6417 | wire spare11_oai22_4x_unused; | |
6418 | wire spare11_inv_16x_unused; | |
6419 | wire spare11_nand2_16x_unused; | |
6420 | wire spare11_nor3_4x_unused; | |
6421 | wire spare11_nand2_8x_unused; | |
6422 | wire spare11_buf_16x_unused; | |
6423 | wire spare11_nor2_16x_unused; | |
6424 | wire spare11_inv_32x_unused; | |
6425 | wire si_12; | |
6426 | wire so_12; | |
6427 | wire spare12_flop_unused; | |
6428 | wire spare12_buf_32x_unused; | |
6429 | wire spare12_nand3_8x_unused; | |
6430 | wire spare12_inv_8x_unused; | |
6431 | wire spare12_aoi22_4x_unused; | |
6432 | wire spare12_buf_8x_unused; | |
6433 | wire spare12_oai22_4x_unused; | |
6434 | wire spare12_inv_16x_unused; | |
6435 | wire spare12_nand2_16x_unused; | |
6436 | wire spare12_nor3_4x_unused; | |
6437 | wire spare12_nand2_8x_unused; | |
6438 | wire spare12_buf_16x_unused; | |
6439 | wire spare12_nor2_16x_unused; | |
6440 | wire spare12_inv_32x_unused; | |
6441 | wire si_13; | |
6442 | wire so_13; | |
6443 | wire spare13_flop_unused; | |
6444 | wire spare13_buf_32x_unused; | |
6445 | wire spare13_nand3_8x_unused; | |
6446 | wire spare13_inv_8x_unused; | |
6447 | wire spare13_aoi22_4x_unused; | |
6448 | wire spare13_buf_8x_unused; | |
6449 | wire spare13_oai22_4x_unused; | |
6450 | wire spare13_inv_16x_unused; | |
6451 | wire spare13_nand2_16x_unused; | |
6452 | wire spare13_nor3_4x_unused; | |
6453 | wire spare13_nand2_8x_unused; | |
6454 | wire spare13_buf_16x_unused; | |
6455 | wire spare13_nor2_16x_unused; | |
6456 | wire spare13_inv_32x_unused; | |
6457 | wire si_14; | |
6458 | wire so_14; | |
6459 | wire spare14_flop_unused; | |
6460 | wire spare14_buf_32x_unused; | |
6461 | wire spare14_nand3_8x_unused; | |
6462 | wire spare14_inv_8x_unused; | |
6463 | wire spare14_aoi22_4x_unused; | |
6464 | wire spare14_buf_8x_unused; | |
6465 | wire spare14_oai22_4x_unused; | |
6466 | wire spare14_inv_16x_unused; | |
6467 | wire spare14_nand2_16x_unused; | |
6468 | wire spare14_nor3_4x_unused; | |
6469 | wire spare14_nand2_8x_unused; | |
6470 | wire spare14_buf_16x_unused; | |
6471 | wire spare14_nor2_16x_unused; | |
6472 | wire spare14_inv_32x_unused; | |
6473 | wire si_15; | |
6474 | wire so_15; | |
6475 | wire spare15_flop_unused; | |
6476 | wire spare15_buf_32x_unused; | |
6477 | wire spare15_nand3_8x_unused; | |
6478 | wire spare15_inv_8x_unused; | |
6479 | wire spare15_aoi22_4x_unused; | |
6480 | wire spare15_buf_8x_unused; | |
6481 | wire spare15_oai22_4x_unused; | |
6482 | wire spare15_inv_16x_unused; | |
6483 | wire spare15_nand2_16x_unused; | |
6484 | wire spare15_nor3_4x_unused; | |
6485 | wire spare15_nand2_8x_unused; | |
6486 | wire spare15_buf_16x_unused; | |
6487 | wire spare15_nor2_16x_unused; | |
6488 | wire spare15_inv_32x_unused; | |
6489 | ||
6490 | ||
6491 | input l1clk; | |
6492 | input scan_in; | |
6493 | input siclk; | |
6494 | input soclk; | |
6495 | output scan_out; | |
6496 | ||
6497 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
6498 | .siclk(siclk), | |
6499 | .soclk(soclk), | |
6500 | .si(si_0), | |
6501 | .so(so_0), | |
6502 | .d(1'b0), | |
6503 | .q(spare0_flop_unused)); | |
6504 | assign si_0 = scan_in; | |
6505 | ||
6506 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
6507 | .out(spare0_buf_32x_unused)); | |
6508 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
6509 | .in1(1'b1), | |
6510 | .in2(1'b1), | |
6511 | .out(spare0_nand3_8x_unused)); | |
6512 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
6513 | .out(spare0_inv_8x_unused)); | |
6514 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
6515 | .in01(1'b1), | |
6516 | .in10(1'b1), | |
6517 | .in11(1'b1), | |
6518 | .out(spare0_aoi22_4x_unused)); | |
6519 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
6520 | .out(spare0_buf_8x_unused)); | |
6521 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
6522 | .in01(1'b1), | |
6523 | .in10(1'b1), | |
6524 | .in11(1'b1), | |
6525 | .out(spare0_oai22_4x_unused)); | |
6526 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
6527 | .out(spare0_inv_16x_unused)); | |
6528 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
6529 | .in1(1'b1), | |
6530 | .out(spare0_nand2_16x_unused)); | |
6531 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
6532 | .in1(1'b0), | |
6533 | .in2(1'b0), | |
6534 | .out(spare0_nor3_4x_unused)); | |
6535 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
6536 | .in1(1'b1), | |
6537 | .out(spare0_nand2_8x_unused)); | |
6538 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
6539 | .out(spare0_buf_16x_unused)); | |
6540 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
6541 | .in1(1'b0), | |
6542 | .out(spare0_nor2_16x_unused)); | |
6543 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
6544 | .out(spare0_inv_32x_unused)); | |
6545 | ||
6546 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), | |
6547 | .siclk(siclk), | |
6548 | .soclk(soclk), | |
6549 | .si(si_1), | |
6550 | .so(so_1), | |
6551 | .d(1'b0), | |
6552 | .q(spare1_flop_unused)); | |
6553 | assign si_1 = so_0; | |
6554 | ||
6555 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
6556 | .out(spare1_buf_32x_unused)); | |
6557 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
6558 | .in1(1'b1), | |
6559 | .in2(1'b1), | |
6560 | .out(spare1_nand3_8x_unused)); | |
6561 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
6562 | .out(spare1_inv_8x_unused)); | |
6563 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
6564 | .in01(1'b1), | |
6565 | .in10(1'b1), | |
6566 | .in11(1'b1), | |
6567 | .out(spare1_aoi22_4x_unused)); | |
6568 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
6569 | .out(spare1_buf_8x_unused)); | |
6570 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
6571 | .in01(1'b1), | |
6572 | .in10(1'b1), | |
6573 | .in11(1'b1), | |
6574 | .out(spare1_oai22_4x_unused)); | |
6575 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
6576 | .out(spare1_inv_16x_unused)); | |
6577 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
6578 | .in1(1'b1), | |
6579 | .out(spare1_nand2_16x_unused)); | |
6580 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
6581 | .in1(1'b0), | |
6582 | .in2(1'b0), | |
6583 | .out(spare1_nor3_4x_unused)); | |
6584 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
6585 | .in1(1'b1), | |
6586 | .out(spare1_nand2_8x_unused)); | |
6587 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
6588 | .out(spare1_buf_16x_unused)); | |
6589 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
6590 | .in1(1'b0), | |
6591 | .out(spare1_nor2_16x_unused)); | |
6592 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
6593 | .out(spare1_inv_32x_unused)); | |
6594 | ||
6595 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), | |
6596 | .siclk(siclk), | |
6597 | .soclk(soclk), | |
6598 | .si(si_2), | |
6599 | .so(so_2), | |
6600 | .d(1'b0), | |
6601 | .q(spare2_flop_unused)); | |
6602 | assign si_2 = so_1; | |
6603 | ||
6604 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), | |
6605 | .out(spare2_buf_32x_unused)); | |
6606 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), | |
6607 | .in1(1'b1), | |
6608 | .in2(1'b1), | |
6609 | .out(spare2_nand3_8x_unused)); | |
6610 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), | |
6611 | .out(spare2_inv_8x_unused)); | |
6612 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), | |
6613 | .in01(1'b1), | |
6614 | .in10(1'b1), | |
6615 | .in11(1'b1), | |
6616 | .out(spare2_aoi22_4x_unused)); | |
6617 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), | |
6618 | .out(spare2_buf_8x_unused)); | |
6619 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), | |
6620 | .in01(1'b1), | |
6621 | .in10(1'b1), | |
6622 | .in11(1'b1), | |
6623 | .out(spare2_oai22_4x_unused)); | |
6624 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), | |
6625 | .out(spare2_inv_16x_unused)); | |
6626 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), | |
6627 | .in1(1'b1), | |
6628 | .out(spare2_nand2_16x_unused)); | |
6629 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), | |
6630 | .in1(1'b0), | |
6631 | .in2(1'b0), | |
6632 | .out(spare2_nor3_4x_unused)); | |
6633 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), | |
6634 | .in1(1'b1), | |
6635 | .out(spare2_nand2_8x_unused)); | |
6636 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), | |
6637 | .out(spare2_buf_16x_unused)); | |
6638 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), | |
6639 | .in1(1'b0), | |
6640 | .out(spare2_nor2_16x_unused)); | |
6641 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), | |
6642 | .out(spare2_inv_32x_unused)); | |
6643 | ||
6644 | cl_sc1_msff_8x spare3_flop (.l1clk(l1clk), | |
6645 | .siclk(siclk), | |
6646 | .soclk(soclk), | |
6647 | .si(si_3), | |
6648 | .so(so_3), | |
6649 | .d(1'b0), | |
6650 | .q(spare3_flop_unused)); | |
6651 | assign si_3 = so_2; | |
6652 | ||
6653 | cl_u1_buf_32x spare3_buf_32x (.in(1'b1), | |
6654 | .out(spare3_buf_32x_unused)); | |
6655 | cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1), | |
6656 | .in1(1'b1), | |
6657 | .in2(1'b1), | |
6658 | .out(spare3_nand3_8x_unused)); | |
6659 | cl_u1_inv_8x spare3_inv_8x (.in(1'b1), | |
6660 | .out(spare3_inv_8x_unused)); | |
6661 | cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1), | |
6662 | .in01(1'b1), | |
6663 | .in10(1'b1), | |
6664 | .in11(1'b1), | |
6665 | .out(spare3_aoi22_4x_unused)); | |
6666 | cl_u1_buf_8x spare3_buf_8x (.in(1'b1), | |
6667 | .out(spare3_buf_8x_unused)); | |
6668 | cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1), | |
6669 | .in01(1'b1), | |
6670 | .in10(1'b1), | |
6671 | .in11(1'b1), | |
6672 | .out(spare3_oai22_4x_unused)); | |
6673 | cl_u1_inv_16x spare3_inv_16x (.in(1'b1), | |
6674 | .out(spare3_inv_16x_unused)); | |
6675 | cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1), | |
6676 | .in1(1'b1), | |
6677 | .out(spare3_nand2_16x_unused)); | |
6678 | cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0), | |
6679 | .in1(1'b0), | |
6680 | .in2(1'b0), | |
6681 | .out(spare3_nor3_4x_unused)); | |
6682 | cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1), | |
6683 | .in1(1'b1), | |
6684 | .out(spare3_nand2_8x_unused)); | |
6685 | cl_u1_buf_16x spare3_buf_16x (.in(1'b1), | |
6686 | .out(spare3_buf_16x_unused)); | |
6687 | cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0), | |
6688 | .in1(1'b0), | |
6689 | .out(spare3_nor2_16x_unused)); | |
6690 | cl_u1_inv_32x spare3_inv_32x (.in(1'b1), | |
6691 | .out(spare3_inv_32x_unused)); | |
6692 | ||
6693 | cl_sc1_msff_8x spare4_flop (.l1clk(l1clk), | |
6694 | .siclk(siclk), | |
6695 | .soclk(soclk), | |
6696 | .si(si_4), | |
6697 | .so(so_4), | |
6698 | .d(1'b0), | |
6699 | .q(spare4_flop_unused)); | |
6700 | assign si_4 = so_3; | |
6701 | ||
6702 | cl_u1_buf_32x spare4_buf_32x (.in(1'b1), | |
6703 | .out(spare4_buf_32x_unused)); | |
6704 | cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1), | |
6705 | .in1(1'b1), | |
6706 | .in2(1'b1), | |
6707 | .out(spare4_nand3_8x_unused)); | |
6708 | cl_u1_inv_8x spare4_inv_8x (.in(1'b1), | |
6709 | .out(spare4_inv_8x_unused)); | |
6710 | cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1), | |
6711 | .in01(1'b1), | |
6712 | .in10(1'b1), | |
6713 | .in11(1'b1), | |
6714 | .out(spare4_aoi22_4x_unused)); | |
6715 | cl_u1_buf_8x spare4_buf_8x (.in(1'b1), | |
6716 | .out(spare4_buf_8x_unused)); | |
6717 | cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1), | |
6718 | .in01(1'b1), | |
6719 | .in10(1'b1), | |
6720 | .in11(1'b1), | |
6721 | .out(spare4_oai22_4x_unused)); | |
6722 | cl_u1_inv_16x spare4_inv_16x (.in(1'b1), | |
6723 | .out(spare4_inv_16x_unused)); | |
6724 | cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1), | |
6725 | .in1(1'b1), | |
6726 | .out(spare4_nand2_16x_unused)); | |
6727 | cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0), | |
6728 | .in1(1'b0), | |
6729 | .in2(1'b0), | |
6730 | .out(spare4_nor3_4x_unused)); | |
6731 | cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1), | |
6732 | .in1(1'b1), | |
6733 | .out(spare4_nand2_8x_unused)); | |
6734 | cl_u1_buf_16x spare4_buf_16x (.in(1'b1), | |
6735 | .out(spare4_buf_16x_unused)); | |
6736 | cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0), | |
6737 | .in1(1'b0), | |
6738 | .out(spare4_nor2_16x_unused)); | |
6739 | cl_u1_inv_32x spare4_inv_32x (.in(1'b1), | |
6740 | .out(spare4_inv_32x_unused)); | |
6741 | ||
6742 | cl_sc1_msff_8x spare5_flop (.l1clk(l1clk), | |
6743 | .siclk(siclk), | |
6744 | .soclk(soclk), | |
6745 | .si(si_5), | |
6746 | .so(so_5), | |
6747 | .d(1'b0), | |
6748 | .q(spare5_flop_unused)); | |
6749 | assign si_5 = so_4; | |
6750 | ||
6751 | cl_u1_buf_32x spare5_buf_32x (.in(1'b1), | |
6752 | .out(spare5_buf_32x_unused)); | |
6753 | cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1), | |
6754 | .in1(1'b1), | |
6755 | .in2(1'b1), | |
6756 | .out(spare5_nand3_8x_unused)); | |
6757 | cl_u1_inv_8x spare5_inv_8x (.in(1'b1), | |
6758 | .out(spare5_inv_8x_unused)); | |
6759 | cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1), | |
6760 | .in01(1'b1), | |
6761 | .in10(1'b1), | |
6762 | .in11(1'b1), | |
6763 | .out(spare5_aoi22_4x_unused)); | |
6764 | cl_u1_buf_8x spare5_buf_8x (.in(1'b1), | |
6765 | .out(spare5_buf_8x_unused)); | |
6766 | cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1), | |
6767 | .in01(1'b1), | |
6768 | .in10(1'b1), | |
6769 | .in11(1'b1), | |
6770 | .out(spare5_oai22_4x_unused)); | |
6771 | cl_u1_inv_16x spare5_inv_16x (.in(1'b1), | |
6772 | .out(spare5_inv_16x_unused)); | |
6773 | cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1), | |
6774 | .in1(1'b1), | |
6775 | .out(spare5_nand2_16x_unused)); | |
6776 | cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0), | |
6777 | .in1(1'b0), | |
6778 | .in2(1'b0), | |
6779 | .out(spare5_nor3_4x_unused)); | |
6780 | cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1), | |
6781 | .in1(1'b1), | |
6782 | .out(spare5_nand2_8x_unused)); | |
6783 | cl_u1_buf_16x spare5_buf_16x (.in(1'b1), | |
6784 | .out(spare5_buf_16x_unused)); | |
6785 | cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0), | |
6786 | .in1(1'b0), | |
6787 | .out(spare5_nor2_16x_unused)); | |
6788 | cl_u1_inv_32x spare5_inv_32x (.in(1'b1), | |
6789 | .out(spare5_inv_32x_unused)); | |
6790 | ||
6791 | cl_sc1_msff_8x spare6_flop (.l1clk(l1clk), | |
6792 | .siclk(siclk), | |
6793 | .soclk(soclk), | |
6794 | .si(si_6), | |
6795 | .so(so_6), | |
6796 | .d(1'b0), | |
6797 | .q(spare6_flop_unused)); | |
6798 | assign si_6 = so_5; | |
6799 | ||
6800 | cl_u1_buf_32x spare6_buf_32x (.in(1'b1), | |
6801 | .out(spare6_buf_32x_unused)); | |
6802 | cl_u1_nand3_8x spare6_nand3_8x (.in0(1'b1), | |
6803 | .in1(1'b1), | |
6804 | .in2(1'b1), | |
6805 | .out(spare6_nand3_8x_unused)); | |
6806 | cl_u1_inv_8x spare6_inv_8x (.in(1'b1), | |
6807 | .out(spare6_inv_8x_unused)); | |
6808 | cl_u1_aoi22_4x spare6_aoi22_4x (.in00(1'b1), | |
6809 | .in01(1'b1), | |
6810 | .in10(1'b1), | |
6811 | .in11(1'b1), | |
6812 | .out(spare6_aoi22_4x_unused)); | |
6813 | cl_u1_buf_8x spare6_buf_8x (.in(1'b1), | |
6814 | .out(spare6_buf_8x_unused)); | |
6815 | cl_u1_oai22_4x spare6_oai22_4x (.in00(1'b1), | |
6816 | .in01(1'b1), | |
6817 | .in10(1'b1), | |
6818 | .in11(1'b1), | |
6819 | .out(spare6_oai22_4x_unused)); | |
6820 | cl_u1_inv_16x spare6_inv_16x (.in(1'b1), | |
6821 | .out(spare6_inv_16x_unused)); | |
6822 | cl_u1_nand2_16x spare6_nand2_16x (.in0(1'b1), | |
6823 | .in1(1'b1), | |
6824 | .out(spare6_nand2_16x_unused)); | |
6825 | cl_u1_nor3_4x spare6_nor3_4x (.in0(1'b0), | |
6826 | .in1(1'b0), | |
6827 | .in2(1'b0), | |
6828 | .out(spare6_nor3_4x_unused)); | |
6829 | cl_u1_nand2_8x spare6_nand2_8x (.in0(1'b1), | |
6830 | .in1(1'b1), | |
6831 | .out(spare6_nand2_8x_unused)); | |
6832 | cl_u1_buf_16x spare6_buf_16x (.in(1'b1), | |
6833 | .out(spare6_buf_16x_unused)); | |
6834 | cl_u1_nor2_16x spare6_nor2_16x (.in0(1'b0), | |
6835 | .in1(1'b0), | |
6836 | .out(spare6_nor2_16x_unused)); | |
6837 | cl_u1_inv_32x spare6_inv_32x (.in(1'b1), | |
6838 | .out(spare6_inv_32x_unused)); | |
6839 | ||
6840 | cl_sc1_msff_8x spare7_flop (.l1clk(l1clk), | |
6841 | .siclk(siclk), | |
6842 | .soclk(soclk), | |
6843 | .si(si_7), | |
6844 | .so(so_7), | |
6845 | .d(1'b0), | |
6846 | .q(spare7_flop_unused)); | |
6847 | assign si_7 = so_6; | |
6848 | ||
6849 | cl_u1_buf_32x spare7_buf_32x (.in(1'b1), | |
6850 | .out(spare7_buf_32x_unused)); | |
6851 | cl_u1_nand3_8x spare7_nand3_8x (.in0(1'b1), | |
6852 | .in1(1'b1), | |
6853 | .in2(1'b1), | |
6854 | .out(spare7_nand3_8x_unused)); | |
6855 | cl_u1_inv_8x spare7_inv_8x (.in(1'b1), | |
6856 | .out(spare7_inv_8x_unused)); | |
6857 | cl_u1_aoi22_4x spare7_aoi22_4x (.in00(1'b1), | |
6858 | .in01(1'b1), | |
6859 | .in10(1'b1), | |
6860 | .in11(1'b1), | |
6861 | .out(spare7_aoi22_4x_unused)); | |
6862 | cl_u1_buf_8x spare7_buf_8x (.in(1'b1), | |
6863 | .out(spare7_buf_8x_unused)); | |
6864 | cl_u1_oai22_4x spare7_oai22_4x (.in00(1'b1), | |
6865 | .in01(1'b1), | |
6866 | .in10(1'b1), | |
6867 | .in11(1'b1), | |
6868 | .out(spare7_oai22_4x_unused)); | |
6869 | cl_u1_inv_16x spare7_inv_16x (.in(1'b1), | |
6870 | .out(spare7_inv_16x_unused)); | |
6871 | cl_u1_nand2_16x spare7_nand2_16x (.in0(1'b1), | |
6872 | .in1(1'b1), | |
6873 | .out(spare7_nand2_16x_unused)); | |
6874 | cl_u1_nor3_4x spare7_nor3_4x (.in0(1'b0), | |
6875 | .in1(1'b0), | |
6876 | .in2(1'b0), | |
6877 | .out(spare7_nor3_4x_unused)); | |
6878 | cl_u1_nand2_8x spare7_nand2_8x (.in0(1'b1), | |
6879 | .in1(1'b1), | |
6880 | .out(spare7_nand2_8x_unused)); | |
6881 | cl_u1_buf_16x spare7_buf_16x (.in(1'b1), | |
6882 | .out(spare7_buf_16x_unused)); | |
6883 | cl_u1_nor2_16x spare7_nor2_16x (.in0(1'b0), | |
6884 | .in1(1'b0), | |
6885 | .out(spare7_nor2_16x_unused)); | |
6886 | cl_u1_inv_32x spare7_inv_32x (.in(1'b1), | |
6887 | .out(spare7_inv_32x_unused)); | |
6888 | ||
6889 | cl_sc1_msff_8x spare8_flop (.l1clk(l1clk), | |
6890 | .siclk(siclk), | |
6891 | .soclk(soclk), | |
6892 | .si(si_8), | |
6893 | .so(so_8), | |
6894 | .d(1'b0), | |
6895 | .q(spare8_flop_unused)); | |
6896 | assign si_8 = so_7; | |
6897 | ||
6898 | cl_u1_buf_32x spare8_buf_32x (.in(1'b1), | |
6899 | .out(spare8_buf_32x_unused)); | |
6900 | cl_u1_nand3_8x spare8_nand3_8x (.in0(1'b1), | |
6901 | .in1(1'b1), | |
6902 | .in2(1'b1), | |
6903 | .out(spare8_nand3_8x_unused)); | |
6904 | cl_u1_inv_8x spare8_inv_8x (.in(1'b1), | |
6905 | .out(spare8_inv_8x_unused)); | |
6906 | cl_u1_aoi22_4x spare8_aoi22_4x (.in00(1'b1), | |
6907 | .in01(1'b1), | |
6908 | .in10(1'b1), | |
6909 | .in11(1'b1), | |
6910 | .out(spare8_aoi22_4x_unused)); | |
6911 | cl_u1_buf_8x spare8_buf_8x (.in(1'b1), | |
6912 | .out(spare8_buf_8x_unused)); | |
6913 | cl_u1_oai22_4x spare8_oai22_4x (.in00(1'b1), | |
6914 | .in01(1'b1), | |
6915 | .in10(1'b1), | |
6916 | .in11(1'b1), | |
6917 | .out(spare8_oai22_4x_unused)); | |
6918 | cl_u1_inv_16x spare8_inv_16x (.in(1'b1), | |
6919 | .out(spare8_inv_16x_unused)); | |
6920 | cl_u1_nand2_16x spare8_nand2_16x (.in0(1'b1), | |
6921 | .in1(1'b1), | |
6922 | .out(spare8_nand2_16x_unused)); | |
6923 | cl_u1_nor3_4x spare8_nor3_4x (.in0(1'b0), | |
6924 | .in1(1'b0), | |
6925 | .in2(1'b0), | |
6926 | .out(spare8_nor3_4x_unused)); | |
6927 | cl_u1_nand2_8x spare8_nand2_8x (.in0(1'b1), | |
6928 | .in1(1'b1), | |
6929 | .out(spare8_nand2_8x_unused)); | |
6930 | cl_u1_buf_16x spare8_buf_16x (.in(1'b1), | |
6931 | .out(spare8_buf_16x_unused)); | |
6932 | cl_u1_nor2_16x spare8_nor2_16x (.in0(1'b0), | |
6933 | .in1(1'b0), | |
6934 | .out(spare8_nor2_16x_unused)); | |
6935 | cl_u1_inv_32x spare8_inv_32x (.in(1'b1), | |
6936 | .out(spare8_inv_32x_unused)); | |
6937 | ||
6938 | cl_sc1_msff_8x spare9_flop (.l1clk(l1clk), | |
6939 | .siclk(siclk), | |
6940 | .soclk(soclk), | |
6941 | .si(si_9), | |
6942 | .so(so_9), | |
6943 | .d(1'b0), | |
6944 | .q(spare9_flop_unused)); | |
6945 | assign si_9 = so_8; | |
6946 | ||
6947 | cl_u1_buf_32x spare9_buf_32x (.in(1'b1), | |
6948 | .out(spare9_buf_32x_unused)); | |
6949 | cl_u1_nand3_8x spare9_nand3_8x (.in0(1'b1), | |
6950 | .in1(1'b1), | |
6951 | .in2(1'b1), | |
6952 | .out(spare9_nand3_8x_unused)); | |
6953 | cl_u1_inv_8x spare9_inv_8x (.in(1'b1), | |
6954 | .out(spare9_inv_8x_unused)); | |
6955 | cl_u1_aoi22_4x spare9_aoi22_4x (.in00(1'b1), | |
6956 | .in01(1'b1), | |
6957 | .in10(1'b1), | |
6958 | .in11(1'b1), | |
6959 | .out(spare9_aoi22_4x_unused)); | |
6960 | cl_u1_buf_8x spare9_buf_8x (.in(1'b1), | |
6961 | .out(spare9_buf_8x_unused)); | |
6962 | cl_u1_oai22_4x spare9_oai22_4x (.in00(1'b1), | |
6963 | .in01(1'b1), | |
6964 | .in10(1'b1), | |
6965 | .in11(1'b1), | |
6966 | .out(spare9_oai22_4x_unused)); | |
6967 | cl_u1_inv_16x spare9_inv_16x (.in(1'b1), | |
6968 | .out(spare9_inv_16x_unused)); | |
6969 | cl_u1_nand2_16x spare9_nand2_16x (.in0(1'b1), | |
6970 | .in1(1'b1), | |
6971 | .out(spare9_nand2_16x_unused)); | |
6972 | cl_u1_nor3_4x spare9_nor3_4x (.in0(1'b0), | |
6973 | .in1(1'b0), | |
6974 | .in2(1'b0), | |
6975 | .out(spare9_nor3_4x_unused)); | |
6976 | cl_u1_nand2_8x spare9_nand2_8x (.in0(1'b1), | |
6977 | .in1(1'b1), | |
6978 | .out(spare9_nand2_8x_unused)); | |
6979 | cl_u1_buf_16x spare9_buf_16x (.in(1'b1), | |
6980 | .out(spare9_buf_16x_unused)); | |
6981 | cl_u1_nor2_16x spare9_nor2_16x (.in0(1'b0), | |
6982 | .in1(1'b0), | |
6983 | .out(spare9_nor2_16x_unused)); | |
6984 | cl_u1_inv_32x spare9_inv_32x (.in(1'b1), | |
6985 | .out(spare9_inv_32x_unused)); | |
6986 | ||
6987 | cl_sc1_msff_8x spare10_flop (.l1clk(l1clk), | |
6988 | .siclk(siclk), | |
6989 | .soclk(soclk), | |
6990 | .si(si_10), | |
6991 | .so(so_10), | |
6992 | .d(1'b0), | |
6993 | .q(spare10_flop_unused)); | |
6994 | assign si_10 = so_9; | |
6995 | ||
6996 | cl_u1_buf_32x spare10_buf_32x (.in(1'b1), | |
6997 | .out(spare10_buf_32x_unused)); | |
6998 | cl_u1_nand3_8x spare10_nand3_8x (.in0(1'b1), | |
6999 | .in1(1'b1), | |
7000 | .in2(1'b1), | |
7001 | .out(spare10_nand3_8x_unused)); | |
7002 | cl_u1_inv_8x spare10_inv_8x (.in(1'b1), | |
7003 | .out(spare10_inv_8x_unused)); | |
7004 | cl_u1_aoi22_4x spare10_aoi22_4x (.in00(1'b1), | |
7005 | .in01(1'b1), | |
7006 | .in10(1'b1), | |
7007 | .in11(1'b1), | |
7008 | .out(spare10_aoi22_4x_unused)); | |
7009 | cl_u1_buf_8x spare10_buf_8x (.in(1'b1), | |
7010 | .out(spare10_buf_8x_unused)); | |
7011 | cl_u1_oai22_4x spare10_oai22_4x (.in00(1'b1), | |
7012 | .in01(1'b1), | |
7013 | .in10(1'b1), | |
7014 | .in11(1'b1), | |
7015 | .out(spare10_oai22_4x_unused)); | |
7016 | cl_u1_inv_16x spare10_inv_16x (.in(1'b1), | |
7017 | .out(spare10_inv_16x_unused)); | |
7018 | cl_u1_nand2_16x spare10_nand2_16x (.in0(1'b1), | |
7019 | .in1(1'b1), | |
7020 | .out(spare10_nand2_16x_unused)); | |
7021 | cl_u1_nor3_4x spare10_nor3_4x (.in0(1'b0), | |
7022 | .in1(1'b0), | |
7023 | .in2(1'b0), | |
7024 | .out(spare10_nor3_4x_unused)); | |
7025 | cl_u1_nand2_8x spare10_nand2_8x (.in0(1'b1), | |
7026 | .in1(1'b1), | |
7027 | .out(spare10_nand2_8x_unused)); | |
7028 | cl_u1_buf_16x spare10_buf_16x (.in(1'b1), | |
7029 | .out(spare10_buf_16x_unused)); | |
7030 | cl_u1_nor2_16x spare10_nor2_16x (.in0(1'b0), | |
7031 | .in1(1'b0), | |
7032 | .out(spare10_nor2_16x_unused)); | |
7033 | cl_u1_inv_32x spare10_inv_32x (.in(1'b1), | |
7034 | .out(spare10_inv_32x_unused)); | |
7035 | ||
7036 | cl_sc1_msff_8x spare11_flop (.l1clk(l1clk), | |
7037 | .siclk(siclk), | |
7038 | .soclk(soclk), | |
7039 | .si(si_11), | |
7040 | .so(so_11), | |
7041 | .d(1'b0), | |
7042 | .q(spare11_flop_unused)); | |
7043 | assign si_11 = so_10; | |
7044 | ||
7045 | cl_u1_buf_32x spare11_buf_32x (.in(1'b1), | |
7046 | .out(spare11_buf_32x_unused)); | |
7047 | cl_u1_nand3_8x spare11_nand3_8x (.in0(1'b1), | |
7048 | .in1(1'b1), | |
7049 | .in2(1'b1), | |
7050 | .out(spare11_nand3_8x_unused)); | |
7051 | cl_u1_inv_8x spare11_inv_8x (.in(1'b1), | |
7052 | .out(spare11_inv_8x_unused)); | |
7053 | cl_u1_aoi22_4x spare11_aoi22_4x (.in00(1'b1), | |
7054 | .in01(1'b1), | |
7055 | .in10(1'b1), | |
7056 | .in11(1'b1), | |
7057 | .out(spare11_aoi22_4x_unused)); | |
7058 | cl_u1_buf_8x spare11_buf_8x (.in(1'b1), | |
7059 | .out(spare11_buf_8x_unused)); | |
7060 | cl_u1_oai22_4x spare11_oai22_4x (.in00(1'b1), | |
7061 | .in01(1'b1), | |
7062 | .in10(1'b1), | |
7063 | .in11(1'b1), | |
7064 | .out(spare11_oai22_4x_unused)); | |
7065 | cl_u1_inv_16x spare11_inv_16x (.in(1'b1), | |
7066 | .out(spare11_inv_16x_unused)); | |
7067 | cl_u1_nand2_16x spare11_nand2_16x (.in0(1'b1), | |
7068 | .in1(1'b1), | |
7069 | .out(spare11_nand2_16x_unused)); | |
7070 | cl_u1_nor3_4x spare11_nor3_4x (.in0(1'b0), | |
7071 | .in1(1'b0), | |
7072 | .in2(1'b0), | |
7073 | .out(spare11_nor3_4x_unused)); | |
7074 | cl_u1_nand2_8x spare11_nand2_8x (.in0(1'b1), | |
7075 | .in1(1'b1), | |
7076 | .out(spare11_nand2_8x_unused)); | |
7077 | cl_u1_buf_16x spare11_buf_16x (.in(1'b1), | |
7078 | .out(spare11_buf_16x_unused)); | |
7079 | cl_u1_nor2_16x spare11_nor2_16x (.in0(1'b0), | |
7080 | .in1(1'b0), | |
7081 | .out(spare11_nor2_16x_unused)); | |
7082 | cl_u1_inv_32x spare11_inv_32x (.in(1'b1), | |
7083 | .out(spare11_inv_32x_unused)); | |
7084 | ||
7085 | cl_sc1_msff_8x spare12_flop (.l1clk(l1clk), | |
7086 | .siclk(siclk), | |
7087 | .soclk(soclk), | |
7088 | .si(si_12), | |
7089 | .so(so_12), | |
7090 | .d(1'b0), | |
7091 | .q(spare12_flop_unused)); | |
7092 | assign si_12 = so_11; | |
7093 | ||
7094 | cl_u1_buf_32x spare12_buf_32x (.in(1'b1), | |
7095 | .out(spare12_buf_32x_unused)); | |
7096 | cl_u1_nand3_8x spare12_nand3_8x (.in0(1'b1), | |
7097 | .in1(1'b1), | |
7098 | .in2(1'b1), | |
7099 | .out(spare12_nand3_8x_unused)); | |
7100 | cl_u1_inv_8x spare12_inv_8x (.in(1'b1), | |
7101 | .out(spare12_inv_8x_unused)); | |
7102 | cl_u1_aoi22_4x spare12_aoi22_4x (.in00(1'b1), | |
7103 | .in01(1'b1), | |
7104 | .in10(1'b1), | |
7105 | .in11(1'b1), | |
7106 | .out(spare12_aoi22_4x_unused)); | |
7107 | cl_u1_buf_8x spare12_buf_8x (.in(1'b1), | |
7108 | .out(spare12_buf_8x_unused)); | |
7109 | cl_u1_oai22_4x spare12_oai22_4x (.in00(1'b1), | |
7110 | .in01(1'b1), | |
7111 | .in10(1'b1), | |
7112 | .in11(1'b1), | |
7113 | .out(spare12_oai22_4x_unused)); | |
7114 | cl_u1_inv_16x spare12_inv_16x (.in(1'b1), | |
7115 | .out(spare12_inv_16x_unused)); | |
7116 | cl_u1_nand2_16x spare12_nand2_16x (.in0(1'b1), | |
7117 | .in1(1'b1), | |
7118 | .out(spare12_nand2_16x_unused)); | |
7119 | cl_u1_nor3_4x spare12_nor3_4x (.in0(1'b0), | |
7120 | .in1(1'b0), | |
7121 | .in2(1'b0), | |
7122 | .out(spare12_nor3_4x_unused)); | |
7123 | cl_u1_nand2_8x spare12_nand2_8x (.in0(1'b1), | |
7124 | .in1(1'b1), | |
7125 | .out(spare12_nand2_8x_unused)); | |
7126 | cl_u1_buf_16x spare12_buf_16x (.in(1'b1), | |
7127 | .out(spare12_buf_16x_unused)); | |
7128 | cl_u1_nor2_16x spare12_nor2_16x (.in0(1'b0), | |
7129 | .in1(1'b0), | |
7130 | .out(spare12_nor2_16x_unused)); | |
7131 | cl_u1_inv_32x spare12_inv_32x (.in(1'b1), | |
7132 | .out(spare12_inv_32x_unused)); | |
7133 | ||
7134 | cl_sc1_msff_8x spare13_flop (.l1clk(l1clk), | |
7135 | .siclk(siclk), | |
7136 | .soclk(soclk), | |
7137 | .si(si_13), | |
7138 | .so(so_13), | |
7139 | .d(1'b0), | |
7140 | .q(spare13_flop_unused)); | |
7141 | assign si_13 = so_12; | |
7142 | ||
7143 | cl_u1_buf_32x spare13_buf_32x (.in(1'b1), | |
7144 | .out(spare13_buf_32x_unused)); | |
7145 | cl_u1_nand3_8x spare13_nand3_8x (.in0(1'b1), | |
7146 | .in1(1'b1), | |
7147 | .in2(1'b1), | |
7148 | .out(spare13_nand3_8x_unused)); | |
7149 | cl_u1_inv_8x spare13_inv_8x (.in(1'b1), | |
7150 | .out(spare13_inv_8x_unused)); | |
7151 | cl_u1_aoi22_4x spare13_aoi22_4x (.in00(1'b1), | |
7152 | .in01(1'b1), | |
7153 | .in10(1'b1), | |
7154 | .in11(1'b1), | |
7155 | .out(spare13_aoi22_4x_unused)); | |
7156 | cl_u1_buf_8x spare13_buf_8x (.in(1'b1), | |
7157 | .out(spare13_buf_8x_unused)); | |
7158 | cl_u1_oai22_4x spare13_oai22_4x (.in00(1'b1), | |
7159 | .in01(1'b1), | |
7160 | .in10(1'b1), | |
7161 | .in11(1'b1), | |
7162 | .out(spare13_oai22_4x_unused)); | |
7163 | cl_u1_inv_16x spare13_inv_16x (.in(1'b1), | |
7164 | .out(spare13_inv_16x_unused)); | |
7165 | cl_u1_nand2_16x spare13_nand2_16x (.in0(1'b1), | |
7166 | .in1(1'b1), | |
7167 | .out(spare13_nand2_16x_unused)); | |
7168 | cl_u1_nor3_4x spare13_nor3_4x (.in0(1'b0), | |
7169 | .in1(1'b0), | |
7170 | .in2(1'b0), | |
7171 | .out(spare13_nor3_4x_unused)); | |
7172 | cl_u1_nand2_8x spare13_nand2_8x (.in0(1'b1), | |
7173 | .in1(1'b1), | |
7174 | .out(spare13_nand2_8x_unused)); | |
7175 | cl_u1_buf_16x spare13_buf_16x (.in(1'b1), | |
7176 | .out(spare13_buf_16x_unused)); | |
7177 | cl_u1_nor2_16x spare13_nor2_16x (.in0(1'b0), | |
7178 | .in1(1'b0), | |
7179 | .out(spare13_nor2_16x_unused)); | |
7180 | cl_u1_inv_32x spare13_inv_32x (.in(1'b1), | |
7181 | .out(spare13_inv_32x_unused)); | |
7182 | ||
7183 | cl_sc1_msff_8x spare14_flop (.l1clk(l1clk), | |
7184 | .siclk(siclk), | |
7185 | .soclk(soclk), | |
7186 | .si(si_14), | |
7187 | .so(so_14), | |
7188 | .d(1'b0), | |
7189 | .q(spare14_flop_unused)); | |
7190 | assign si_14 = so_13; | |
7191 | ||
7192 | cl_u1_buf_32x spare14_buf_32x (.in(1'b1), | |
7193 | .out(spare14_buf_32x_unused)); | |
7194 | cl_u1_nand3_8x spare14_nand3_8x (.in0(1'b1), | |
7195 | .in1(1'b1), | |
7196 | .in2(1'b1), | |
7197 | .out(spare14_nand3_8x_unused)); | |
7198 | cl_u1_inv_8x spare14_inv_8x (.in(1'b1), | |
7199 | .out(spare14_inv_8x_unused)); | |
7200 | cl_u1_aoi22_4x spare14_aoi22_4x (.in00(1'b1), | |
7201 | .in01(1'b1), | |
7202 | .in10(1'b1), | |
7203 | .in11(1'b1), | |
7204 | .out(spare14_aoi22_4x_unused)); | |
7205 | cl_u1_buf_8x spare14_buf_8x (.in(1'b1), | |
7206 | .out(spare14_buf_8x_unused)); | |
7207 | cl_u1_oai22_4x spare14_oai22_4x (.in00(1'b1), | |
7208 | .in01(1'b1), | |
7209 | .in10(1'b1), | |
7210 | .in11(1'b1), | |
7211 | .out(spare14_oai22_4x_unused)); | |
7212 | cl_u1_inv_16x spare14_inv_16x (.in(1'b1), | |
7213 | .out(spare14_inv_16x_unused)); | |
7214 | cl_u1_nand2_16x spare14_nand2_16x (.in0(1'b1), | |
7215 | .in1(1'b1), | |
7216 | .out(spare14_nand2_16x_unused)); | |
7217 | cl_u1_nor3_4x spare14_nor3_4x (.in0(1'b0), | |
7218 | .in1(1'b0), | |
7219 | .in2(1'b0), | |
7220 | .out(spare14_nor3_4x_unused)); | |
7221 | cl_u1_nand2_8x spare14_nand2_8x (.in0(1'b1), | |
7222 | .in1(1'b1), | |
7223 | .out(spare14_nand2_8x_unused)); | |
7224 | cl_u1_buf_16x spare14_buf_16x (.in(1'b1), | |
7225 | .out(spare14_buf_16x_unused)); | |
7226 | cl_u1_nor2_16x spare14_nor2_16x (.in0(1'b0), | |
7227 | .in1(1'b0), | |
7228 | .out(spare14_nor2_16x_unused)); | |
7229 | cl_u1_inv_32x spare14_inv_32x (.in(1'b1), | |
7230 | .out(spare14_inv_32x_unused)); | |
7231 | ||
7232 | cl_sc1_msff_8x spare15_flop (.l1clk(l1clk), | |
7233 | .siclk(siclk), | |
7234 | .soclk(soclk), | |
7235 | .si(si_15), | |
7236 | .so(so_15), | |
7237 | .d(1'b0), | |
7238 | .q(spare15_flop_unused)); | |
7239 | assign si_15 = so_14; | |
7240 | ||
7241 | cl_u1_buf_32x spare15_buf_32x (.in(1'b1), | |
7242 | .out(spare15_buf_32x_unused)); | |
7243 | cl_u1_nand3_8x spare15_nand3_8x (.in0(1'b1), | |
7244 | .in1(1'b1), | |
7245 | .in2(1'b1), | |
7246 | .out(spare15_nand3_8x_unused)); | |
7247 | cl_u1_inv_8x spare15_inv_8x (.in(1'b1), | |
7248 | .out(spare15_inv_8x_unused)); | |
7249 | cl_u1_aoi22_4x spare15_aoi22_4x (.in00(1'b1), | |
7250 | .in01(1'b1), | |
7251 | .in10(1'b1), | |
7252 | .in11(1'b1), | |
7253 | .out(spare15_aoi22_4x_unused)); | |
7254 | cl_u1_buf_8x spare15_buf_8x (.in(1'b1), | |
7255 | .out(spare15_buf_8x_unused)); | |
7256 | cl_u1_oai22_4x spare15_oai22_4x (.in00(1'b1), | |
7257 | .in01(1'b1), | |
7258 | .in10(1'b1), | |
7259 | .in11(1'b1), | |
7260 | .out(spare15_oai22_4x_unused)); | |
7261 | cl_u1_inv_16x spare15_inv_16x (.in(1'b1), | |
7262 | .out(spare15_inv_16x_unused)); | |
7263 | cl_u1_nand2_16x spare15_nand2_16x (.in0(1'b1), | |
7264 | .in1(1'b1), | |
7265 | .out(spare15_nand2_16x_unused)); | |
7266 | cl_u1_nor3_4x spare15_nor3_4x (.in0(1'b0), | |
7267 | .in1(1'b0), | |
7268 | .in2(1'b0), | |
7269 | .out(spare15_nor3_4x_unused)); | |
7270 | cl_u1_nand2_8x spare15_nand2_8x (.in0(1'b1), | |
7271 | .in1(1'b1), | |
7272 | .out(spare15_nand2_8x_unused)); | |
7273 | cl_u1_buf_16x spare15_buf_16x (.in(1'b1), | |
7274 | .out(spare15_buf_16x_unused)); | |
7275 | cl_u1_nor2_16x spare15_nor2_16x (.in0(1'b0), | |
7276 | .in1(1'b0), | |
7277 | .out(spare15_nor2_16x_unused)); | |
7278 | cl_u1_inv_32x spare15_inv_32x (.in(1'b1), | |
7279 | .out(spare15_inv_32x_unused)); | |
7280 | assign scan_out = so_15; | |
7281 | ||
7282 | ||
7283 | ||
7284 | endmodule | |
7285 |