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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: n2_clk_clstr_hdr1_cust.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `timescale 1 ns/1 ns | |
36 | ||
37 | module n2_clk_clstr_hdr1_cust ( | |
38 | gclk, | |
39 | l2clk, | |
40 | cluster_arst_l, | |
41 | ccu_div_ph, | |
42 | cluster_div_en, | |
43 | tcu_div_bypass, | |
44 | scan_in, | |
45 | scan_en, | |
46 | tcu_aclk, | |
47 | tcu_bclk, | |
48 | ccu_cmp_slow_sync_en, | |
49 | ccu_slow_cmp_sync_en, | |
50 | ccu_io2x_sync_en, | |
51 | ccu_dr_sync_en, | |
52 | tcu_pce_ov, | |
53 | tcu_clk_stop, | |
54 | rst_por_, | |
55 | rst_wmr_, | |
56 | rst_wmr_protect, | |
57 | tcu_wr_inhibit, | |
58 | tcu_atpg_mode, | |
59 | array_wr_inhibit, | |
60 | aclk_wmr, | |
61 | aclk, | |
62 | bclk, | |
63 | cmp_slow_sync_en, | |
64 | slow_cmp_sync_en, | |
65 | io2x_sync_en, | |
66 | dr_sync_en, | |
67 | pce_ov, | |
68 | por_, | |
69 | wmr_, | |
70 | wmr_protect, | |
71 | scan_out, | |
72 | cclk | |
73 | ); | |
74 | ||
75 | // ******************************* | |
76 | // port declaration | |
77 | // ******************************* | |
78 | ||
79 | input gclk; | |
80 | input l2clk; | |
81 | input cluster_arst_l; | |
82 | input ccu_div_ph; | |
83 | input cluster_div_en; | |
84 | input tcu_div_bypass; | |
85 | input scan_in; | |
86 | input scan_en; | |
87 | input tcu_aclk; | |
88 | input tcu_bclk; | |
89 | input ccu_cmp_slow_sync_en; | |
90 | input ccu_slow_cmp_sync_en; | |
91 | input ccu_io2x_sync_en; | |
92 | input ccu_dr_sync_en; | |
93 | input tcu_pce_ov; | |
94 | input tcu_clk_stop; | |
95 | input rst_por_; | |
96 | input rst_wmr_; | |
97 | input rst_wmr_protect; | |
98 | input tcu_wr_inhibit; | |
99 | input tcu_atpg_mode; | |
100 | output array_wr_inhibit; | |
101 | output aclk_wmr; | |
102 | output aclk; | |
103 | output bclk; | |
104 | output cmp_slow_sync_en; | |
105 | output slow_cmp_sync_en; | |
106 | output io2x_sync_en; | |
107 | output dr_sync_en; | |
108 | output pce_ov; | |
109 | output por_; | |
110 | output wmr_; | |
111 | output wmr_protect; | |
112 | output scan_out; | |
113 | output cclk; | |
114 | ||
115 | ||
116 | // ******************************* | |
117 | // wire declaration | |
118 | // ******************************* | |
119 | ||
120 | wire gclk; | |
121 | wire l2clk; | |
122 | wire cluster_arst_l; | |
123 | wire ccu_div_ph; | |
124 | wire cluster_div_en; | |
125 | wire tcu_div_bypass; | |
126 | wire scan_in; | |
127 | wire scan_en; | |
128 | wire tcu_aclk; | |
129 | wire tcu_bclk; | |
130 | wire ccu_cmp_slow_sync_en; | |
131 | wire ccu_slow_cmp_sync_en; | |
132 | wire ccu_io2x_sync_en; | |
133 | wire ccu_dr_sync_en; | |
134 | wire tcu_pce_ov; | |
135 | wire tcu_clk_stop; | |
136 | wire rst_por_; | |
137 | wire rst_wmr_; | |
138 | wire rst_wmr_protect; | |
139 | wire tcu_wr_inhibit; // to be made input | |
140 | wire tcu_atpg_mode; // to be made input | |
141 | wire array_wr_inhibit; // to be made output | |
142 | wire aclk_wmr; | |
143 | wire aclk; | |
144 | wire bclk; | |
145 | wire cmp_slow_sync_en; | |
146 | wire slow_cmp_sync_en; | |
147 | wire io2x_sync_en; | |
148 | wire dr_sync_en; | |
149 | wire pce_ov; | |
150 | wire por_; | |
151 | wire wmr_; | |
152 | wire wmr_protect; | |
153 | wire scan_out; | |
154 | wire cclk; | |
155 | ||
156 | ||
157 | // additional internal nets | |
158 | wire div_r; | |
159 | // wire div_f; // vlint | |
160 | ||
161 | wire cluster_div_en_n; | |
162 | wire tcu_div_bypass_n; | |
163 | ||
164 | ||
165 | wire sel0; | |
166 | wire sel1; | |
167 | // wire sel2; // vlint | |
168 | ||
169 | wire div_out; | |
170 | // wire div_r_n; // vlint | |
171 | // wire div_f_n; // vlint | |
172 | ||
173 | // wire gclk_n; // vlint | |
174 | wire array_wr_inhibit_n; | |
175 | ||
176 | ||
177 | wire cclk_n; | |
178 | wire pre_cclk; | |
179 | wire div_clk; | |
180 | ||
181 | wire l1clk; | |
182 | wire l1gclk; | |
183 | ||
184 | wire aclk_gated; | |
185 | wire bclk_gated; | |
186 | wire scan_en_gated; | |
187 | wire scan_out_pre_mux; | |
188 | ||
189 | wire aclk_gated_n; | |
190 | wire bclk_gated_n; | |
191 | wire scan_en_gated_n; | |
192 | wire tcu_atpg_mode_n; | |
193 | ||
194 | wire scan_ch; | |
195 | ||
196 | // wire clk_stop_muxed; // vlint | |
197 | // wire clk_stop_q; // vlint | |
198 | wire clk_stop_synced; | |
199 | ||
200 | wire rst_wmr_protect_n; | |
201 | wire aclk_wmr_n; | |
202 | wire div_r_sync; | |
203 | wire sel0_n; | |
204 | wire sel1_n; | |
205 | wire div_ph_blatch; | |
206 | wire div_r_sync_n; | |
207 | wire div_mux; | |
208 | ||
209 | // ********************************************************** | |
210 | // buffered & gated stuff | |
211 | // ********************************************************** | |
212 | ||
213 | cl_u1_buf_1x aclk_buf ( .in( tcu_aclk ), .out ( aclk ) ); | |
214 | cl_u1_buf_1x bclk_buf ( .in( tcu_bclk ), .out ( bclk ) ); | |
215 | cl_u1_buf_1x pce_ov_buf ( .in( tcu_pce_ov ), .out ( pce_ov ) ); | |
216 | cl_u1_buf_1x wmr_protect_buf ( .in( rst_wmr_protect ), .out ( wmr_protect ) ); | |
217 | ||
218 | // assign aclk_gated = aclk & tcu_atpg_mode; | |
219 | // assign bclk_gated = bclk & tcu_atpg_mode; | |
220 | // assign scan_en_gated = scan_en & tcu_atpg_mode; | |
221 | // implemented right here | |
222 | cl_u1_nand2_1x aclk_gated_nand ( .in0 (aclk), .in1 (tcu_atpg_mode), .out (aclk_gated_n) ); | |
223 | cl_u1_nand2_1x bclk_gated_nand ( .in0 (bclk), .in1 (tcu_atpg_mode), .out (bclk_gated_n) ); | |
224 | cl_u1_nand2_1x scan_en_gated_nand ( .in0 (scan_en), .in1 (tcu_atpg_mode), .out (scan_en_gated_n) ); | |
225 | cl_u1_inv_1x aclk_gated_inv ( .in (aclk_gated_n), .out (aclk_gated) ); | |
226 | cl_u1_inv_1x bclk_gated_inv ( .in (bclk_gated_n), .out (bclk_gated) ); | |
227 | cl_u1_inv_1x scan_en_gated_inv ( .in (scan_en_gated_n), .out (scan_en_gated) ); | |
228 | ||
229 | // assign scan_out = tcu_atpg_mode ? scan_out_pre_mux : scan_in ; | |
230 | // implemented below, and as instance "scan_chain_mux" | |
231 | cl_u1_inv_1x tcu_atpg_mode_inv ( .in (tcu_atpg_mode) , .out (tcu_atpg_mode_n) ); | |
232 | ||
233 | ||
234 | // assign aclk_wmr = ~rst_wmr_protect & tcu_aclk; | |
235 | ||
236 | ||
237 | cl_u1_inv_1x wmr_protect_inv ( .in (rst_wmr_protect) , .out (rst_wmr_protect_n) ); | |
238 | ||
239 | cl_u1_nand2_1x aclk_wmr_gate ( | |
240 | .in0 (aclk), | |
241 | .in1 (rst_wmr_protect_n), | |
242 | .out (aclk_wmr_n) | |
243 | ); | |
244 | ||
245 | cl_u1_inv_1x aclk_wmr_inv ( .in (aclk_wmr_n) , .out (aclk_wmr) ); | |
246 | ||
247 | // cl_u1_inv_1x gclk_inv ( .in (gclk) , .out (gclk_n) ); // vlint | |
248 | ||
249 | // ********************************************************** | |
250 | // l1hdr for scan | |
251 | // ********************************************************** | |
252 | ||
253 | n2_clk_clstr_hdr1_l1hdr gclk_header ( | |
254 | .l2clk(gclk), | |
255 | .l1clk(l1gclk), | |
256 | .pce(1'b1), | |
257 | .se(scan_en_gated), | |
258 | .pce_ov(1'b1), | |
259 | .stop(1'b0) // ECO1.2 - not allowed to stop local clocks | |
260 | ); | |
261 | ||
262 | n2_clk_clstr_hdr1_l1hdr l1_header ( | |
263 | .l2clk(l2clk), | |
264 | .l1clk(l1clk), | |
265 | .pce(1'b1), | |
266 | .se(scan_en_gated), | |
267 | .pce_ov(1'b1), | |
268 | .stop(1'b0) // ECO1.3 - false info; no action needed | |
269 | ); | |
270 | ||
271 | // ********************************************************** | |
272 | // make observe flops part of scan chain (observe only) | |
273 | // ********************************************************** | |
274 | ||
275 | n2_clk_clstr_hdr1_obs_flops observe_flops ( | |
276 | .tcu_clk_stop (tcu_clk_stop), | |
277 | .ccu_div_ph (ccu_div_ph), | |
278 | .array_wr_inhibit (array_wr_inhibit), | |
279 | .l1clk (l1gclk), | |
280 | .aclk (aclk_gated), | |
281 | .bclk (bclk_gated), | |
282 | .scan_in (scan_in), | |
283 | .scan_out (scan_ch) | |
284 | ); | |
285 | ||
286 | cl_sc1_aomux2_1x scan_chain_mux ( | |
287 | .sel0 ( tcu_atpg_mode ), | |
288 | .sel1 ( tcu_atpg_mode_n ), | |
289 | .in0 ( scan_out_pre_mux ), | |
290 | .in1 ( scan_in ), | |
291 | .out ( scan_out ) | |
292 | ); | |
293 | ||
294 | ||
295 | // ********************************************************** | |
296 | // synchronize the control signals | |
297 | // ********************************************************** | |
298 | ||
299 | n2_clk_clstr_hdr1_sync control_sig_sync ( | |
300 | .div_r ( div_r_sync ), | |
301 | .gclk ( l1gclk ), | |
302 | .l1clk ( l1clk ), | |
303 | .ccu_slow_cmp_sync_en ( ccu_slow_cmp_sync_en), | |
304 | .ccu_cmp_slow_sync_en ( ccu_cmp_slow_sync_en), | |
305 | .ccu_dr_sync_en ( ccu_dr_sync_en), | |
306 | .ccu_io2x_sync_en ( ccu_io2x_sync_en), | |
307 | .rst_por_ ( rst_por_), | |
308 | .rst_wmr_ ( rst_wmr_), | |
309 | .scan_in ( scan_ch ), | |
310 | .aclk ( aclk_gated ), | |
311 | .bclk ( bclk_gated ), | |
312 | .slow_cmp_sync_en ( slow_cmp_sync_en ), | |
313 | .cmp_slow_sync_en ( cmp_slow_sync_en ), | |
314 | .dr_sync_en ( dr_sync_en), | |
315 | .io2x_sync_en ( io2x_sync_en), | |
316 | .por_ ( por_ ), | |
317 | .wmr_ ( wmr_ ), | |
318 | .scan_out ( scan_out_pre_mux ) | |
319 | ); | |
320 | ||
321 | ||
322 | // ********************************************************** | |
323 | // divider & mux model | |
324 | // ********************************************************** | |
325 | ||
326 | wire ccu_div_ph_ff; | |
327 | wire ccu_div_ph_flop_unused; | |
328 | ||
329 | // first flop ccu_div_ph | |
330 | cl_sc1_msff_1x ccu_div_ph_flop ( | |
331 | .d ( ccu_div_ph ), | |
332 | .l1clk ( gclk ), | |
333 | .si ( 1'b0 ), | |
334 | .siclk ( 1'b0 ), | |
335 | .soclk ( 1'b0 ), | |
336 | .q ( ccu_div_ph_ff ), | |
337 | .so (ccu_div_ph_flop_unused) | |
338 | ); | |
339 | ||
340 | // div_r = sel1 (ie, ~div_en | tcu_div_bypass ) | div_ph | |
341 | // div_f = sel0 (ie, div_en & ~tcu_div_bypass ) | |
342 | // | |
343 | ||
344 | // sel0 = ~div_bypass & div_en // div_ph select | |
345 | // sel1 = div_bypass | ~div_en // gclk select | |
346 | ||
347 | cl_u1_inv_1x div_bypass_inv ( .in (tcu_div_bypass), .out (tcu_div_bypass_n) ); | |
348 | cl_u1_inv_1x cluster_div_inv ( .in (cluster_div_en), .out (cluster_div_en_n) ); | |
349 | ||
350 | // | |
351 | // generate sel0 - div_ph sel | |
352 | // | |
353 | ||
354 | cl_u1_nand2_1x sel0_n_gen ( | |
355 | .in0 (tcu_div_bypass_n), | |
356 | .in1 (cluster_div_en), | |
357 | .out (sel0_n) | |
358 | ); | |
359 | ||
360 | cl_u1_inv_1x sel0_gen ( .in (sel0_n), .out (sel0) ); | |
361 | ||
362 | ||
363 | // | |
364 | // generate sel1 - gclk sel | |
365 | // | |
366 | ||
367 | cl_u1_nor2_1x sel2_n_gen ( | |
368 | .in0 (cluster_div_en_n), | |
369 | .in1 (tcu_div_bypass), | |
370 | .out (sel1_n) | |
371 | ); | |
372 | ||
373 | cl_u1_inv_1x sel1_gen ( .in (sel1_n), .out (sel1) ); | |
374 | ||
375 | ||
376 | // gate off div_r | |
377 | //cl_u1_nor2_1x div_r_gate ( | |
378 | // .in0 (sel1), | |
379 | // .in1 (div_ph_blatch), | |
380 | // .out (div_r_n) | |
381 | //); | |
382 | wire blatch_divr_unused; | |
383 | cl_sc1_blatch_4x blatch_divr ( | |
384 | .latout(div_ph_blatch), .d(ccu_div_ph_ff), .l1clk (gclk), | |
385 | .so (blatch_divr_unused), .si (1'b0), .siclk(1'b0), .soclk(1'b0) ); | |
386 | ||
387 | //cl_u1_nor2_1x div_r_gate ( | |
388 | // .in0 (sel1), | |
389 | // .in1 (div_ph_blatch), | |
390 | // .out (div_r_n) | |
391 | //); | |
392 | ||
393 | cl_u1_buf_1x div_r_buf ( .in (div_ph_blatch), .out (div_r ) ); | |
394 | ||
395 | ||
396 | // | |
397 | // divider model | |
398 | // | |
399 | ||
400 | // creating the div_r_to_syncronizer to mimic generation of | |
401 | //div_r in schematic. | |
402 | ||
403 | cl_u1_nor2_1x div_r_sync_gen_nor ( | |
404 | .in0 (sel0_n), | |
405 | .in1 (ccu_div_ph_ff), | |
406 | .out (div_r_sync_n) | |
407 | ); | |
408 | ||
409 | cl_u1_inv_1x div_r_sync_gen_inv ( .in (div_r_sync_n), .out (div_r_sync) ); | |
410 | ||
411 | cl_sc1_aomux2_1x alatch_in ( | |
412 | .sel0 (~sel1 ), | |
413 | .sel1 ( sel1 ), | |
414 | .in0 ( div_r ), | |
415 | .in1 ( div_clk ), | |
416 | .out ( div_mux ) | |
417 | ); | |
418 | ||
419 | wire gclk_reset; | |
420 | wire gclk_reset_n; | |
421 | cl_u1_nor2_1x nor_gclk_reset ( .in0 (sel1), .in1 (gclk), .out (gclk_reset_n)); | |
422 | cl_u1_inv_1x inv_gclk_reset ( .in (gclk_reset_n), .out (gclk_reset)); | |
423 | ||
424 | ||
425 | wire alatch_unused; | |
426 | cl_sc1_alatch_4x alatch ( | |
427 | .q(div_out), .d(div_mux), .l1clk (gclk_reset), | |
428 | .so (alatch_unused), .si (1'b0), .siclk(1'b0), .soclk(1'b0), .se(1'b0) ); | |
429 | ||
430 | // muxed clock out | |
431 | cl_sc1_aomux2_1x final_mux ( | |
432 | .sel0 ( sel0 ), | |
433 | .sel1 ( sel1 ), | |
434 | .in0 ( div_out ), | |
435 | .in1 ( gclk ), | |
436 | .out ( div_clk ) | |
437 | ); | |
438 | ||
439 | // ********************************************************** | |
440 | // clkstop for l2clk (via control of cclk) | |
441 | // ********************************************************** | |
442 | ||
443 | // 1. sync up clock stop (these are non-scanned) | |
444 | n2_clk_clstr_hdr1_clk_stop_syncff clk_stop_syncff ( | |
445 | .din ( tcu_clk_stop ), | |
446 | .synced ( clk_stop_synced ), | |
447 | .clkin ( gclk ), | |
448 | .sync_clk ( div_clk ), | |
449 | .sel ( div_r_sync ) | |
450 | ||
451 | ); | |
452 | ||
453 | wire clk_stop_synced_stg1; | |
454 | wire clk_stop_synced_stg2; | |
455 | wire clk_stop_del_stg1_unused; | |
456 | wire clk_stop_del_stg2_unused; | |
457 | // 2. now delay sync'd up clock stop (these are non-scanned) | |
458 | cl_sc1_msff_1x clk_stop_del_stg1 ( | |
459 | .d (clk_stop_synced), .q (clk_stop_synced_stg1), .l1clk (div_clk), | |
460 | .siclk (1'b0), .soclk (1'b0), .si (1'b0), .so (clk_stop_del_stg1_unused) | |
461 | ); | |
462 | ||
463 | cl_sc1_msff_1x clk_stop_del_stg2 ( | |
464 | .d (clk_stop_synced_stg1), .q (clk_stop_synced_stg2), .l1clk (div_clk), | |
465 | .siclk (1'b0), .soclk (1'b0), .si (1'b0), .so (clk_stop_del_stg2_unused) | |
466 | ); | |
467 | ||
468 | wire clk_stop_synced_stg2_gated; | |
469 | wire clk_stop_synced_stg2_n; | |
470 | ||
471 | cl_u1_inv_1x clk_stop_stg2_inv ( .in (clk_stop_synced_stg2), .out (clk_stop_synced_stg2_n) ); | |
472 | ||
473 | // ECO1.5 - pushed the gate after the latch in the clk-stop instance "clk_stopper" | |
474 | // cl_u1_nor2_1x clk_stop_stg2_nor ( .in0 (clk_stop_synced_stg2_n), .in1 (tcu_atpg_mode), .out (clk_stop_synced_stg2_gated) ); | |
475 | // | |
476 | // 3. use blatch & and-gate for controlling clock | |
477 | n2_clk_clstr_hdr1_clkgate clk_stopper ( | |
478 | .l2clk(div_clk), | |
479 | .l1clk(pre_cclk), | |
480 | .atpg_mode(tcu_atpg_mode), | |
481 | .clken(clk_stop_synced_stg2_n) | |
482 | ); | |
483 | ||
484 | // 4. finally gate-off with async reset | |
485 | // assign cclk = pre_cclk & cluster_arst_l; | |
486 | ||
487 | // wire cclk_tmp; | |
488 | cl_u1_nand2_1x cclk_nand ( .in0 (pre_cclk), .in1 (cluster_arst_l), .out (cclk_n) ); | |
489 | cl_u1_inv_1x cclk_inv ( .in (cclk_n), .out (cclk) ); // cclk_tmp | |
490 | // assign cclk = cclk_tmp | scan_en; | |
491 | ||
492 | ||
493 | // ********************************************************** | |
494 | // array write inhibit operation | |
495 | // ********************************************************** | |
496 | ||
497 | wire clk_stop_synced_n; | |
498 | ||
499 | wire clk_stop_synced_stg3; | |
500 | wire clk_stop_synced_stg4; | |
501 | wire clk_stop_synced_stg5; | |
502 | ||
503 | wire array_wr_inhibit1; | |
504 | wire array_wr_inhibit2; | |
505 | ||
506 | wire array_wr_inhibit1_n; | |
507 | wire array_wr_inhibit2_n; | |
508 | wire cluster_arst; | |
509 | wire clk_stop_del_stg3_unused; | |
510 | wire clk_stop_del_stg4_unused; | |
511 | wire clk_stop_del_stg5_unused; | |
512 | ||
513 | cl_sc1_msff_1x clk_stop_del_stg3 ( | |
514 | .d (clk_stop_synced_stg2), .q (clk_stop_synced_stg3), .l1clk (div_clk), | |
515 | .siclk (1'b0), .soclk (1'b0), .si (1'b0), .so (clk_stop_del_stg3_unused) | |
516 | ); | |
517 | ||
518 | cl_sc1_msff_1x clk_stop_del_stg4 ( | |
519 | .d (clk_stop_synced_stg3), .q (clk_stop_synced_stg4), .l1clk (div_clk), | |
520 | .siclk (1'b0), .soclk (1'b0), .si (1'b0), .so (clk_stop_del_stg4_unused) | |
521 | ); | |
522 | ||
523 | cl_sc1_msff_1x clk_stop_del_stg5 ( | |
524 | .d (clk_stop_synced_stg4), .q (clk_stop_synced_stg5), .l1clk (div_clk), | |
525 | .siclk (1'b0), .soclk (1'b0), .si (1'b0), .so (clk_stop_del_stg5_unused) | |
526 | ); | |
527 | ||
528 | ||
529 | // assign array_wr_inhibit1 = clk_stop_synced & clk_stop_synced_stg5; | |
530 | ||
531 | cl_u1_nand3_1x clk_stop_and_delayed ( // ECO1.4 - changed cl_u1_nand2_1x | |
532 | .in0 (clk_stop_synced), | |
533 | .in1 (clk_stop_synced_stg5), | |
534 | .in2 (tcu_atpg_mode_n), | |
535 | .out (array_wr_inhibit1_n) | |
536 | ); | |
537 | ||
538 | cl_u1_inv_1x array_wr_inhibit1_inv ( .in(array_wr_inhibit1_n), .out(array_wr_inhibit1) ); | |
539 | ||
540 | ||
541 | // assign array_wr_inhibit2 = (~clk_stop_synced) & wr_inhibit_q2; | |
542 | cl_u1_inv_1x clk_stop_synced_inv ( .in(clk_stop_synced), .out(clk_stop_synced_n) ); | |
543 | ||
544 | // ECO1.1 - removed nand gate from path of tcu_wr_inhibit | |
545 | // and replaced with buffer | |
546 | // | |
547 | // cl_u1_nand2_1x clk_stop_synced_and_wr_inhibit_q2 ( | |
548 | // .in0 (clk_stop_synced_n), | |
549 | // .in1 (tcu_wr_inhibit), // (wr_inhibit_q2), | |
550 | // .out (array_wr_inhibit2_n) | |
551 | // ); | |
552 | // | |
553 | // cl_u1_inv_1x array_wr_inhibit2_inv ( .in(array_wr_inhibit2_n), .out(array_wr_inhibit2) ); | |
554 | cl_u1_buf_1x array_wr_inhibit2_buf ( .in(tcu_wr_inhibit), .out(array_wr_inhibit2) ); | |
555 | ||
556 | ||
557 | // assign array_wr_inhibit = array_wr_inhibit1 | array_wr_inhibit2 | (~cluster_arst_l); | |
558 | ||
559 | cl_u1_inv_1x cluster_arst_inv (.in (cluster_arst_l), .out (cluster_arst)); | |
560 | ||
561 | cl_u1_nor3_1x array_wr_inhibit_nor ( | |
562 | .in0 (array_wr_inhibit1), | |
563 | .in1 (array_wr_inhibit2), | |
564 | .in2 (cluster_arst), | |
565 | .out (array_wr_inhibit_n) | |
566 | ); | |
567 | ||
568 | cl_u1_inv_1x array_wr_inhibit_inv (.in (array_wr_inhibit_n), .out (array_wr_inhibit)); | |
569 | ||
570 | endmodule // n2_clk_clstr_hdr1_cust | |
571 | ||
572 | ||
573 | ||
574 | ||
575 | // ********************************************************** | |
576 | // (fictitous) observe flop module for ATPG purposes | |
577 | // ********************************************************** | |
578 | ||
579 | module n2_clk_clstr_hdr1_obs_flops ( | |
580 | tcu_clk_stop, | |
581 | ccu_div_ph, | |
582 | array_wr_inhibit, | |
583 | l1clk, | |
584 | aclk, | |
585 | bclk, | |
586 | scan_in, | |
587 | scan_out | |
588 | ); | |
589 | ||
590 | input tcu_clk_stop; | |
591 | input ccu_div_ph; | |
592 | input array_wr_inhibit; | |
593 | input l1clk; | |
594 | input aclk; | |
595 | input bclk; | |
596 | input scan_in; | |
597 | output scan_out; | |
598 | ||
599 | wire tcu_clk_stop; | |
600 | wire ccu_div_ph; | |
601 | wire array_wr_inhibit; | |
602 | wire l1clk; | |
603 | wire aclk; | |
604 | wire bclk; | |
605 | wire scan_in; | |
606 | wire scan_out; | |
607 | ||
608 | wire scan_ch1; | |
609 | wire scan_ch2; | |
610 | wire obs_ff1_unused; | |
611 | wire obs_ff2_unused; | |
612 | wire obs_ff3_unused; | |
613 | ||
614 | cl_sc1_msff_1x obs_ff1 ( | |
615 | .d ( tcu_clk_stop ), | |
616 | .l1clk ( l1clk ), | |
617 | .si ( scan_in ), | |
618 | .siclk ( aclk ), | |
619 | .soclk ( bclk ), | |
620 | .q (obs_ff1_unused ), | |
621 | .so ( scan_ch1 ) | |
622 | ); | |
623 | ||
624 | cl_sc1_msff_1x obs_ff2 ( | |
625 | .d ( ccu_div_ph ), | |
626 | .l1clk ( l1clk ), | |
627 | .si ( scan_ch1 ), | |
628 | .siclk ( aclk ), | |
629 | .soclk ( bclk ), | |
630 | .q (obs_ff2_unused ), | |
631 | .so ( scan_ch2 ) | |
632 | ); | |
633 | ||
634 | cl_sc1_msff_1x obs_ff3 ( | |
635 | .d ( array_wr_inhibit ), | |
636 | .l1clk ( l1clk ), | |
637 | .si ( scan_ch2 ), | |
638 | .siclk ( aclk ), | |
639 | .soclk ( bclk ), | |
640 | .q (obs_ff3_unused ), | |
641 | .so ( scan_out ) | |
642 | ); | |
643 | endmodule // n2_clk_clstr_hdr1_obs_flops | |
644 | ||
645 | ||
646 | // ********************************************************** | |
647 | // (fictitous) synchronizer module for ATPG purposes | |
648 | // ********************************************************** | |
649 | ||
650 | module n2_clk_clstr_hdr1_sync ( | |
651 | div_r, | |
652 | gclk, | |
653 | l1clk, | |
654 | ccu_slow_cmp_sync_en , | |
655 | ccu_cmp_slow_sync_en , | |
656 | ccu_dr_sync_en, | |
657 | ccu_io2x_sync_en, | |
658 | rst_por_ , | |
659 | rst_wmr_ , | |
660 | scan_in, | |
661 | aclk, | |
662 | bclk, | |
663 | slow_cmp_sync_en, | |
664 | cmp_slow_sync_en, | |
665 | dr_sync_en, | |
666 | io2x_sync_en, | |
667 | por_, | |
668 | wmr_, | |
669 | scan_out | |
670 | ); | |
671 | ||
672 | ||
673 | input div_r; | |
674 | input gclk; | |
675 | input l1clk; | |
676 | input ccu_slow_cmp_sync_en ; | |
677 | input ccu_cmp_slow_sync_en ; | |
678 | input ccu_dr_sync_en; | |
679 | input ccu_io2x_sync_en; | |
680 | input rst_por_ ; | |
681 | input rst_wmr_ ; | |
682 | input scan_in; | |
683 | input aclk; | |
684 | input bclk; | |
685 | ||
686 | output slow_cmp_sync_en; | |
687 | output cmp_slow_sync_en; | |
688 | output dr_sync_en; | |
689 | output io2x_sync_en; | |
690 | output por_; | |
691 | output wmr_; | |
692 | output scan_out; | |
693 | ||
694 | wire div_r; | |
695 | // wire div_r_n; // vlint | |
696 | wire gclk; | |
697 | // wire gclk_n; // vlint | |
698 | wire l1clk; | |
699 | ||
700 | wire ccu_slow_cmp_sync_en ; | |
701 | wire slow_cmp_sync_en; | |
702 | wire ccu_cmp_slow_sync_en ; | |
703 | wire cmp_slow_sync_en; | |
704 | wire rst_por_ ; | |
705 | wire por_; | |
706 | ||
707 | wire rst_wmr_ ; | |
708 | wire wmr_; | |
709 | ||
710 | wire scan_in; | |
711 | wire scan_out; | |
712 | wire aclk; | |
713 | wire bclk; | |
714 | ||
715 | wire scan_ch1; | |
716 | wire scan_ch2; | |
717 | wire scan_ch3; | |
718 | wire scan_ch4; | |
719 | wire scan_ch5; | |
720 | ||
721 | ||
722 | // slow_cmp_sync_en | |
723 | n2_clk_clstr_hdr1_sync_ff slow_cmp_sync_en_syncff ( | |
724 | .din ( ccu_slow_cmp_sync_en ), | |
725 | .synced ( slow_cmp_sync_en ), | |
726 | .clkin ( gclk ), | |
727 | .sync_clk ( l1clk ), | |
728 | .sel ( div_r ), | |
729 | .siclk ( aclk ), | |
730 | .soclk ( bclk ), | |
731 | .si ( scan_in ), | |
732 | .so ( scan_ch1 ) | |
733 | ); | |
734 | ||
735 | // cmp_slow_sync_en | |
736 | n2_clk_clstr_hdr1_sync_ff cmp_slow_sync_en_syncff ( | |
737 | .din ( ccu_cmp_slow_sync_en ), | |
738 | .synced ( cmp_slow_sync_en ), | |
739 | .clkin ( gclk ), | |
740 | .sync_clk ( l1clk ), | |
741 | .sel ( div_r ), | |
742 | .siclk ( aclk ), | |
743 | .soclk ( bclk ), | |
744 | .si ( scan_ch1 ), | |
745 | .so ( scan_ch2 ) | |
746 | ); | |
747 | ||
748 | // por_ | |
749 | n2_clk_clstr_hdr1_sync_ff por_syncff ( | |
750 | .din ( rst_por_ ), | |
751 | .synced ( por_ ), | |
752 | .clkin ( gclk ), | |
753 | .sync_clk ( l1clk ), | |
754 | .sel ( div_r ), | |
755 | .siclk ( aclk ), | |
756 | .soclk ( bclk ), | |
757 | .si ( scan_ch2 ), | |
758 | .so ( scan_ch3 ) | |
759 | ); | |
760 | ||
761 | // wmr_ | |
762 | n2_clk_clstr_hdr1_sync_ff wmr_syncff ( | |
763 | .din ( rst_wmr_ ), | |
764 | .synced ( wmr_ ), | |
765 | .clkin ( gclk ), | |
766 | .sync_clk ( l1clk ), | |
767 | .sel ( div_r ), | |
768 | .siclk ( aclk ), | |
769 | .soclk ( bclk ), | |
770 | .si ( scan_ch3 ), | |
771 | .so ( scan_ch4 ) | |
772 | ); | |
773 | ||
774 | // dr_sync_en; | |
775 | n2_clk_clstr_hdr1_sync_ff dr_sync_en_syncff ( | |
776 | .din ( ccu_dr_sync_en ), | |
777 | .synced ( dr_sync_en ), | |
778 | .clkin ( gclk ), | |
779 | .sync_clk ( l1clk ), | |
780 | .sel ( div_r ), | |
781 | .siclk ( aclk ), | |
782 | .soclk ( bclk ), | |
783 | .si ( scan_ch4 ), | |
784 | .so ( scan_ch5 ) | |
785 | ); | |
786 | ||
787 | // io2x_sync_en; | |
788 | n2_clk_clstr_hdr1_sync_ff io2x_sync_en_syncff ( | |
789 | .din ( ccu_io2x_sync_en ), | |
790 | .synced ( io2x_sync_en ), | |
791 | .clkin ( gclk ), | |
792 | .sync_clk ( l1clk ), | |
793 | .sel ( div_r ), | |
794 | .siclk ( aclk ), | |
795 | .soclk ( bclk ), | |
796 | .si ( scan_ch5 ), | |
797 | .so ( scan_out ) | |
798 | ); | |
799 | ||
800 | endmodule // n2_clk_clstr_hdr1_sync | |
801 | ||
802 | ||
803 | // ********************************************************** | |
804 | // (fictitous) 1-bit synchronizer for ATPG purposes | |
805 | // ********************************************************** | |
806 | ||
807 | module n2_clk_clstr_hdr1_sync_ff ( | |
808 | din, | |
809 | synced, | |
810 | clkin, | |
811 | sync_clk, | |
812 | sel, | |
813 | siclk, | |
814 | soclk, | |
815 | si, | |
816 | so | |
817 | ); | |
818 | ||
819 | input din; | |
820 | output synced; | |
821 | input clkin; | |
822 | input sync_clk; | |
823 | input siclk; | |
824 | input soclk; | |
825 | input si; | |
826 | output so; | |
827 | input sel; | |
828 | ||
829 | wire din; | |
830 | wire synced; | |
831 | wire clkin; | |
832 | wire sync_clk; | |
833 | wire siclk; | |
834 | wire soclk; | |
835 | wire si; | |
836 | wire so; | |
837 | wire sel; | |
838 | ||
839 | wire so_tmp; | |
840 | wire sel_n; | |
841 | wire din_q1; | |
842 | wire din_muxed; | |
843 | ||
844 | cl_u1_inv_1x sel_inv ( .in ( sel ), .out ( sel_n ) ); | |
845 | ||
846 | cl_sc1_aomux2_1x sync_mux1 ( | |
847 | .sel0 ( sel_n ), | |
848 | .sel1 ( sel ), | |
849 | .in0 ( din_q1 ), | |
850 | .in1 ( din ), | |
851 | .out ( din_muxed ) | |
852 | ); | |
853 | ||
854 | cl_sc1_msff_1x din_stg1 ( | |
855 | .d ( din_muxed ), | |
856 | .l1clk ( clkin ), | |
857 | .si ( si ), | |
858 | .siclk ( siclk ), | |
859 | .soclk ( soclk ), | |
860 | .q ( din_q1 ), | |
861 | .so ( so_tmp ) | |
862 | ); | |
863 | ||
864 | cl_sc1_msff_1x din_stg2 ( | |
865 | .d ( din_q1 ), | |
866 | .l1clk ( sync_clk ), | |
867 | .si ( so_tmp ), | |
868 | .siclk ( siclk ), | |
869 | .soclk ( soclk ), | |
870 | .q ( synced ), | |
871 | .so ( so ) | |
872 | ); | |
873 | endmodule // n2_clk_clstr_hdr1_sync_ff | |
874 | ||
875 | ||
876 | // ********************************************************** | |
877 | // (fictitous) module for clock stop sync. | |
878 | // ********************************************************** | |
879 | module n2_clk_clstr_hdr1_clk_stop_syncff ( | |
880 | din, | |
881 | synced, | |
882 | clkin, | |
883 | sync_clk, | |
884 | sel | |
885 | ); | |
886 | ||
887 | input din; | |
888 | output synced; | |
889 | input clkin; | |
890 | input sync_clk; | |
891 | input sel; | |
892 | ||
893 | wire din; | |
894 | wire synced; | |
895 | wire clkin; | |
896 | wire sync_clk; | |
897 | wire sel; | |
898 | ||
899 | wire [2:0] so_unused; | |
900 | ||
901 | wire sel_n; | |
902 | wire din_q1_lat; | |
903 | wire din_q1; | |
904 | wire din_muxed; | |
905 | ||
906 | cl_u1_inv_1x sel_inv ( .in(sel), .out(sel_n) ); | |
907 | ||
908 | cl_sc1_aomux2_1x sync_mux1 ( | |
909 | .sel0 ( sel_n ), .sel1 ( sel ), | |
910 | .in0 ( din_q1 ), .in1 ( din ), | |
911 | .out ( din_muxed ) | |
912 | ); | |
913 | ||
914 | cl_sc1_msff_1x din_stg1 ( | |
915 | .d ( din_muxed ), .l1clk ( clkin ), .q ( din_q1 ), | |
916 | .si ( 1'b0 ), .siclk ( 1'b0 ), .soclk ( 1'b0 ), | |
917 | .so (so_unused[0])); | |
918 | ||
919 | cl_sc1_blatch_4x blatch ( | |
920 | .latout(din_q1_lat), .d(din_q1), .l1clk (clkin), | |
921 | .so (so_unused[1]), .si (1'b0), .siclk(1'b0), .soclk(1'b0) ); | |
922 | ||
923 | cl_sc1_msff_1x din_stg2 ( | |
924 | .d ( din_q1_lat ), .l1clk ( sync_clk ), .q ( synced ), | |
925 | .siclk ( 1'b0 ), .soclk ( 1'b0 ), .si ( 1'b0 ), .so (so_unused[2] ) ); | |
926 | ||
927 | endmodule // n2_clk_clstr_hdr1_clk_stop_sync_ff | |
928 | ||
929 | ||
930 | ||
931 | module n2_clk_clstr_hdr1_clkgate ( | |
932 | atpg_mode, | |
933 | clken, | |
934 | l2clk, | |
935 | l1clk | |
936 | ); | |
937 | ||
938 | input atpg_mode; | |
939 | input clken; // clken, active high | |
940 | input l2clk; // level 2 clock, from clock grid | |
941 | output l1clk; | |
942 | ||
943 | wire atpg_mode, clken, l2clk, l1clk; | |
944 | ||
945 | wire clken_gated; | |
946 | wire clken_gated_n; | |
947 | wire l1clk_n; | |
948 | wire clken_lat; | |
949 | wire so_unused; | |
950 | ||
951 | cl_sc1_blatch_4x blatch ( | |
952 | .latout(clken_lat), .d(clken), .l1clk (l2clk), | |
953 | .so (so_unused), .si (1'b0), .siclk(1'b0), .soclk(1'b0) ); | |
954 | ||
955 | cl_u1_nor2_1x clken_nor ( .in0(clken_lat), .in1(atpg_mode), .out(clken_gated_n) ); | |
956 | cl_u1_inv_1x clken_gated_inv ( .in(clken_gated_n), .out(clken_gated) ); | |
957 | ||
958 | cl_u1_nand2_1x clk_nand ( .in0(clken_gated), .in1(l2clk), .out(l1clk_n) ); | |
959 | cl_u1_inv_1x clk_inv ( .in(l1clk_n), .out(l1clk) ); | |
960 | ||
961 | endmodule // n2_clk_clstr_hdr1_clkgate | |
962 | ||
963 | module n2_clk_clstr_hdr1_l1hdr ( | |
964 | l2clk, | |
965 | se, | |
966 | pce, | |
967 | pce_ov, | |
968 | stop, | |
969 | l1clk | |
970 | ); | |
971 | ||
972 | input l2clk; // level 2 clock, from clock grid | |
973 | input se; // Scan Enable | |
974 | input pce; // Clock enable for local power savings | |
975 | input pce_ov; // TCU sourced clock enable override for testing | |
976 | input stop; // TCU/CCU sourced clock stop for debug | |
977 | output l1clk; | |
978 | ||
979 | reg l1en; | |
980 | ||
981 | always @ (l2clk or stop or pce or pce_ov ) begin // vlint fix - latch model | |
982 | if (!l2clk) | |
983 | l1en = (~stop & ( pce | pce_ov )); // vlint fix - replaced w/blocking | |
984 | end | |
985 | ||
986 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority | |
987 | ||
988 | endmodule // n2_clk_clstr_hdr1_l1hdr | |
989 | ||
990 |