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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: clkgen_rtx_io2x.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module clkgen_rtx_io2x ( | |
36 | array_wr_inhibit, | |
37 | tcu_atpg_mode, | |
38 | tcu_wr_inhibit, | |
39 | l2clk, | |
40 | aclk, | |
41 | bclk, | |
42 | scan_out, | |
43 | pce_ov, | |
44 | aclk_wmr, | |
45 | wmr_protect, | |
46 | wmr_, | |
47 | por_, | |
48 | cmp_slow_sync_en, | |
49 | slow_cmp_sync_en, | |
50 | tcu_clk_stop, | |
51 | tcu_pce_ov, | |
52 | rst_wmr_protect, | |
53 | rst_wmr_, | |
54 | rst_por_, | |
55 | ccu_cmp_slow_sync_en, | |
56 | ccu_slow_cmp_sync_en, | |
57 | tcu_div_bypass, | |
58 | ccu_div_ph, | |
59 | cluster_div_en, | |
60 | gclk, | |
61 | cluster_arst_l, | |
62 | clk_ext, | |
63 | ccu_serdes_dtm, | |
64 | tcu_aclk, | |
65 | tcu_bclk, | |
66 | scan_en, | |
67 | scan_in | |
68 | ); | |
69 | ||
70 | ||
71 | // ************************** | |
72 | // port declaration | |
73 | // ************************** | |
74 | ||
75 | // clock & test out | |
76 | output l2clk; // assume we do not need aclk, bclk outputs | |
77 | output aclk; // buffered version of aclk | |
78 | output bclk; // buffered version of bclk | |
79 | output scan_out; // unused as of today - feb 10, 05 | |
80 | output aclk_wmr; | |
81 | ||
82 | // pipelined out | |
83 | output pce_ov; // pce override to l1 header | |
84 | output wmr_protect; // warm reset protect | |
85 | output wmr_; // warm reset (active low) | |
86 | output por_; // power-on-reset | |
87 | output cmp_slow_sync_en; // cmp->slow clk sync pulse | |
88 | output slow_cmp_sync_en; // slow->cmp clk sync pulse | |
89 | // output io2x_sync_en; // cmp<->io2x clk sync pulse | |
90 | // output dr_sync_en; // cmp<->dr clk sync pulse | |
91 | ||
92 | // ctrl in (for pipelining) | |
93 | output array_wr_inhibit; | |
94 | input tcu_atpg_mode; | |
95 | input tcu_wr_inhibit; | |
96 | input tcu_clk_stop; | |
97 | input tcu_pce_ov; | |
98 | input rst_wmr_protect; | |
99 | input rst_wmr_; | |
100 | input rst_por_; | |
101 | input ccu_cmp_slow_sync_en; | |
102 | input ccu_slow_cmp_sync_en; | |
103 | // input ccu_io2x_sync_en; | |
104 | // input ccu_dr_sync_en; | |
105 | ||
106 | // ctrl in (for clock gen) | |
107 | input tcu_div_bypass; // bypasses clk divider to mux in ext clk | |
108 | input ccu_div_ph; // phase signal from ccu (div/4 or div/2) | |
109 | input cluster_div_en; // if enabled, l2clk is divided down | |
110 | ||
111 | // clock & test in | |
112 | input gclk; // global clk - this is either cmp or dr | |
113 | input cluster_arst_l; | |
114 | input ccu_serdes_dtm; | |
115 | input clk_ext; // external clk muxed in for ioclk bypass | |
116 | input scan_en; // unused as of today - feb 10, 05 | |
117 | input scan_in; // unused as of today - feb 10, 05 | |
118 | input tcu_aclk; | |
119 | input tcu_bclk; | |
120 | ||
121 | // ************************** | |
122 | // wire declaration | |
123 | // ************************** | |
124 | wire array_wr_inhibit; | |
125 | wire tcu_atpg_mode; | |
126 | wire tcu_wr_inhibit; | |
127 | wire l2clk; | |
128 | wire aclk; | |
129 | wire bclk; | |
130 | wire scan_out; | |
131 | wire aclk_wmr; | |
132 | wire pce_ov; | |
133 | wire wmr_protect; | |
134 | wire wmr_; | |
135 | wire por_; | |
136 | wire cmp_slow_sync_en; | |
137 | wire slow_cmp_sync_en; | |
138 | // wire io2x_sync_en; | |
139 | // wire dr_sync_en; | |
140 | wire tcu_clk_stop; | |
141 | wire tcu_pce_ov; | |
142 | wire rst_wmr_protect; | |
143 | wire rst_wmr_; | |
144 | wire rst_por_; | |
145 | wire ccu_cmp_slow_sync_en; | |
146 | wire ccu_slow_cmp_sync_en; | |
147 | // wire ccu_io2x_sync_en; | |
148 | // wire ccu_dr_sync_en; | |
149 | wire tcu_div_bypass; | |
150 | wire ccu_div_ph; | |
151 | wire cluster_div_en; | |
152 | wire gclk; | |
153 | wire cluster_arst_l; | |
154 | wire clk_ext; | |
155 | wire ccu_serdes_dtm; | |
156 | wire scan_en; | |
157 | wire scan_in; | |
158 | wire tcu_aclk; | |
159 | wire tcu_bclk; | |
160 | ||
161 | wire cclk; | |
162 | ||
163 | ||
164 | // ************************** | |
165 | // instantiations | |
166 | // ************************** | |
167 | ||
168 | // needs a few edits to cluster header def - mahmud.hassan | |
169 | // modified custom cell name for avoiding | |
170 | // collision with sparc core and other clusters - mhassan | |
171 | n2_clk_clstr_hdr_cust xcluster_header ( | |
172 | .gclk (gclk), | |
173 | .l2clk (l2clk), | |
174 | .cluster_arst_l (cluster_arst_l), | |
175 | .ccu_div_ph (ccu_div_ph), | |
176 | .cluster_div_en (cluster_div_en), | |
177 | .tcu_div_bypass (tcu_div_bypass), | |
178 | // .clk_ext (clk_ext), | |
179 | // .ccu_serdes_dtm (ccu_serdes_dtm), | |
180 | .scan_in (scan_in), | |
181 | .scan_en (scan_en), | |
182 | .tcu_aclk (tcu_aclk), | |
183 | .tcu_bclk (tcu_bclk), | |
184 | .ccu_cmp_slow_sync_en (ccu_cmp_slow_sync_en), | |
185 | .ccu_slow_cmp_sync_en (ccu_slow_cmp_sync_en), | |
186 | // .ccu_io2x_sync_en (ccu_io2x_sync_en ), | |
187 | // .ccu_dr_sync_en (ccu_dr_sync_en ), | |
188 | .tcu_pce_ov (tcu_pce_ov), | |
189 | .tcu_clk_stop (tcu_clk_stop), | |
190 | .rst_por_ (rst_por_), | |
191 | .rst_wmr_ (rst_wmr_), | |
192 | .rst_wmr_protect (rst_wmr_protect), | |
193 | .aclk_wmr (aclk_wmr), | |
194 | .aclk (aclk), | |
195 | .bclk (bclk), | |
196 | .cmp_slow_sync_en (cmp_slow_sync_en), | |
197 | .slow_cmp_sync_en (slow_cmp_sync_en), | |
198 | // .io2x_sync_en (io2x_sync_en ), | |
199 | // .dr_sync_en (dr_sync_en ), | |
200 | .pce_ov (pce_ov), | |
201 | .por_ (por_), | |
202 | .wmr_ (wmr_), | |
203 | .wmr_protect (wmr_protect), | |
204 | .scan_out (scan_out), | |
205 | .array_wr_inhibit (array_wr_inhibit), | |
206 | .tcu_atpg_mode (tcu_atpg_mode), | |
207 | .tcu_wr_inhibit (tcu_wr_inhibit), | |
208 | .cclk (cclk) | |
209 | ); | |
210 | ||
211 | ||
212 | ||
213 | // cclk -> l2clk from right | |
214 | n2_clk_rtx_io2x_cust xright ( | |
215 | .l2clk (l2clk), | |
216 | .cclk (cclk) | |
217 | ); | |
218 | ||
219 | ||
220 | ||
221 | // cclk -> l2clk from left | |
222 | n2_clk_rtx_io2x_cust xleft ( | |
223 | .l2clk (l2clk), | |
224 | .cclk (cclk) | |
225 | ); | |
226 | ||
227 | endmodule | |
228 |