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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_err_adv_piu_int_ejr.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap | |
39 | #define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap | |
40 | ||
41 | #define MAIN_PAGE_HV_ALSO | |
42 | ||
43 | #define H_HT0_Interrupt_0x60 | |
44 | #define My_HT0_Interrupt_0x60 \ | |
45 | call my_trap_code; \ | |
46 | nop; \ | |
47 | retry; \ | |
48 | nop; | |
49 | ||
50 | #include "hboot.s" | |
51 | #include "peu_defines.h" | |
52 | #include "ncu_defines.h" | |
53 | ||
54 | ||
55 | /************************************************************************ | |
56 | Test case code start | |
57 | ************************************************************************/ | |
58 | .text | |
59 | .global main | |
60 | .global My_Recoverable_Sw_error_trap | |
61 | .global My_Corrected_ECC_error_trap | |
62 | ||
63 | ||
64 | main: | |
65 | ta T_CHANGE_HPRIV | |
66 | nop | |
67 | ||
68 | lear_esr_first: | |
69 | setx SOC_ESR_REG, %l7, %i0 | |
70 | stx %g0, [%i0] | |
71 | ||
72 | set_ejr: | |
73 | set 0x1, %i1 | |
74 | sllx %i1, ERR_FIELD, %i2 | |
75 | setx SOC_EJR_REG, %l7, %i3 | |
76 | stx %i2, [%i3] | |
77 | membar 0x40 | |
78 | ||
79 | ||
80 | /* Initialize the NCU for the interrupt. */ | |
81 | ||
82 | ! Disable interrupts | |
83 | ||
84 | ||
85 | no_intr: | |
86 | rdpr %pstate, %g7 | |
87 | xor %g7, 0x2, %g7 ! Reset interrupt enable | |
88 | wrpr %g7, %pstate | |
89 | ||
90 | ! Initialize NCU's Mondo Interrupt Vector Register | |
91 | ! VECTOR = 63 | |
92 | ||
93 | ncu_mondo_int_vec: | |
94 | set 63, %g1 | |
95 | setx MONDO_INT_VEC, %g2, %g3 | |
96 | stx %g1, [%g3] | |
97 | ||
98 | ! Clear NCU's Mondo Interrupt Busy registers. | |
99 | ||
100 | ncu_mondo_int_busy: | |
101 | setx MONDO_INT_ABUSY, %g1, %g2 | |
102 | stx %g0, [%g2] | |
103 | ||
104 | ! Enable in MMU, TTE_INV_P, primary TTE valid bit not set error. | |
105 | ||
106 | mmu_intr_enable_reg_init: | |
107 | setx PCI_E_MMU_INT_ENB_ADDR, %g1, %g2 | |
108 | set PCI_E_MMU_INT_EN_TTE_INV_P_SHIFT, %g3 | |
109 | set 1, %g4 | |
110 | sllx %g4, %g3, %g4 | |
111 | stx %g4, [%g2] | |
112 | ||
113 | ! Enable in IMU, MSI_MAL_ERR_P, malformed MSI message error. | |
114 | ||
115 | imu_intr_enable_reg_init: | |
116 | setx PCI_E_IMU_INT_ENB_ADDR, %g1, %g2 | |
117 | set PCI_E_IMU_INT_EN_MSI_MAL_ERR_P_SHIFT, %g3 | |
118 | set 1, %g4 | |
119 | sllx %g4, %g3, %g4 | |
120 | stx %g4, [%g2] | |
121 | ||
122 | ! Initialize Interrupt Mapping register | |
123 | ! Valid, thread ID 0, no interrupt controller | |
124 | ||
125 | pci_intr_map_reg_init: | |
126 | setx PCI_E_INT_MAP_ADDR, %g1, %g7 | |
127 | setx PCI_E_INT_MAP_MONDO_62_OFFSET, %g1, %g3 | |
128 | add %g7, %g3, %g7 | |
129 | setx 0x80000040, %g1, %g6 ! valid = 1, thread id = 0 | |
130 | stx %g6, [%g7] ! interrupt controller = 1 | |
131 | ||
132 | yes_intr: | |
133 | rdpr %pstate, %g7 | |
134 | or %g7, 0x2, %g7 ! Set interrupt enable | |
135 | wrpr %g7, %pstate | |
136 | ||
137 | ! Enable IMU, MMU interrupts in the DMU Core and Block | |
138 | ! Interrupt Enable register. | |
139 | ||
140 | dmu_core_block_enable: | |
141 | setx PCI_E_DMU_CORE_BLK_INT_ENB_ADDR, %g1, %g2 | |
142 | setx PCI_E_DMU_CORE_BLK_INT_EN_DMC_MASK, %g1, %g3 | |
143 | setx PCI_E_DMU_CORE_BLK_INT_EN_MMU_MASK, %g1, %g4 | |
144 | or %g3, %g4, %g4 | |
145 | setx PCI_E_DMU_CORE_BLK_INT_EN_IMU_MASK, %g1, %g3 | |
146 | or %g3, %g4, %g4 | |
147 | stx %g4, [%g2] | |
148 | membar #Sync | |
149 | ||
150 | ! Generate an interrupt from the IMU block. | |
151 | ||
152 | gen_imu_intr: | |
153 | setx PCI_E_IMU_ERR_STAT_SET_ADDR, %g1, %g2 | |
154 | set 1, %g6 | |
155 | setx PCI_E_IMU_INT_EN_MSI_MAL_ERR_P_SHIFT, %g1, %g3 | |
156 | sllx %g6, %g3, %g6 | |
157 | stx %g6, [%g2] | |
158 | membar #Sync | |
159 | ||
160 | ! Wait for the interrupt trap | |
161 | ||
162 | intr_wait1: | |
163 | setx 0x400, %g1, %g2 ! timeout count | |
164 | setx user_data_start, %g1, %g7 | |
165 | ||
166 | intr_wait_loop1: | |
167 | ld [%g7], %g5 | |
168 | cmp %g5, 1 | |
169 | be read_esr | |
170 | nop | |
171 | ||
172 | cmp %g2, 0 | |
173 | be test_failed ! time out | |
174 | nop | |
175 | ba intr_wait_loop1 | |
176 | dec %g2 | |
177 | ||
178 | ||
179 | /****************************** | |
180 | Error Check | |
181 | ******************************/ | |
182 | read_esr: | |
183 | setx SOC_ESR_REG, %l7, %i0 | |
184 | ldx [%i0], %i1 | |
185 | nop | |
186 | ||
187 | setx 0x8000000000000000, %l7, %o3 !valid bit | |
188 | set 0x1, %i2 | |
189 | sllx %i2, ERR_FIELD, %i3 | |
190 | or %i3, %o3, %i4 | |
191 | sub %i1, %i4, %i5 | |
192 | brnz %i5, test_failed | |
193 | nop | |
194 | ||
195 | eie_reg_ones: | |
196 | setx SOC_EIE_REG, %g3, %g2 | |
197 | set 0x1, %i1 | |
198 | sllx %i1, ERR_FIELD, %g1 | |
199 | stx %g1, [%g2] | |
200 | membar 0x40 | |
201 | ||
202 | setx 0x40, %g7, %g6 | |
203 | set 0x1, %g1 ! 1 Trap | |
204 | err_trap_loop: | |
205 | cmp %g6, %g0 | |
206 | be %xcc, test_failed | |
207 | nop | |
208 | ||
209 | cmp %g1, %i7 | |
210 | be %xcc, check_tt | |
211 | nop | |
212 | ||
213 | ba err_trap_loop | |
214 | nop | |
215 | ||
216 | check_tt: | |
217 | mov TT, %l0 | |
218 | cmp %o7, %l0 | |
219 | bne %xcc, test_failed | |
220 | nop | |
221 | ||
222 | ||
223 | /********************************/ | |
224 | ||
225 | ||
226 | test_passed: | |
227 | EXIT_GOOD | |
228 | ||
229 | test_failed: | |
230 | EXIT_BAD | |
231 | ||
232 | ||
233 | /********************************************************************** | |
234 | Interrupt trap handler. | |
235 | **********************************************************************/ | |
236 | ||
237 | .global my_trap_code | |
238 | ||
239 | my_trap_code: | |
240 | ||
241 | ! Record interrupt occured. | |
242 | ||
243 | trap_intr_flag: | |
244 | setx user_data_start, %l1, %l3 | |
245 | set 1, %l1 | |
246 | st %l1, [%l3] | |
247 | ||
248 | ! Check Mondo Interrupt Busy reg. | |
249 | ||
250 | trap_mondo_busy: | |
251 | ta T_RD_THID ! thread id into %o1 | |
252 | setx MONDO_INT_BUSY, %l1, %l2 | |
253 | setx MONDO_INT_BUSY_STEP, %l1, %l3 | |
254 | mulx %l3, %o1, %l3 | |
255 | add %l3, %l2, %l2 | |
256 | ldx [%l2], %l4 | |
257 | and %l4, 0x40, %l5 ! Is busy bit set? | |
258 | cmp %l5, 0 | |
259 | be test_failed | |
260 | nop | |
261 | ||
262 | ! Clear the mondo interrupt in the PIU. | |
263 | ||
264 | ! MMU Error Status Set reg. | |
265 | ||
266 | trap_clear_mmu_err_set: | |
267 | setx PCI_E_MMU_ERR_STAT_SET_ADDR, %l1, %l2 | |
268 | stx %g0, [%l2] ! removes setting of the error | |
269 | ||
270 | ! MMU Error Status Clear reg. | |
271 | ||
272 | trap_mmu_err_clear: | |
273 | setx PCI_E_MMU_ERR_STAT_CL_ADDR, %l1, %l2 | |
274 | sub %g0, 1, %l0 ! a W1C register | |
275 | stx %l0, [%l2] ! clears the error flag | |
276 | ||
277 | ! IMU Error Status Set reg. | |
278 | ||
279 | trap_clear_imu_err_set: | |
280 | setx PCI_E_IMU_ERR_STAT_SET_ADDR, %l1, %l2 | |
281 | stx %g0, [%l2] ! removes setting of the error | |
282 | ||
283 | ! IMU Error Status Clear reg. | |
284 | ||
285 | trap_imu_err_clear: | |
286 | setx PCI_E_IMU_ERR_STAT_CLR_ADDR, %l1, %l2 | |
287 | sub %g0, 1, %l0 ! a W1C register | |
288 | stx %l0, [%l2] ! clears the error flag | |
289 | ||
290 | ! Interrupt Clear reg. | |
291 | ||
292 | trap_intr_clear: | |
293 | setx PCI_E_INT_CLEAR_ADDR, %l1, %l2 | |
294 | setx PCI_E_INT_CLEAR_MONDO_62_OFFSET, %l1, %l3 | |
295 | add %l2, %l3, %l2 | |
296 | stx %g0, [%l2] | |
297 | ||
298 | ! Clear the mondo interrupt in the NCU | |
299 | ||
300 | trap_mondo_intr_clear: | |
301 | setx MONDO_INT_ABUSY, %l0, %l1 | |
302 | stx %g0, [%l1] | |
303 | membar #Sync | |
304 | ||
305 | ldx [%l1], %l2 | |
306 | and %l2, 0x40, %l2 | |
307 | cmp %l2, 0 ! Busy should be cleared | |
308 | bne test_failed | |
309 | nop | |
310 | ||
311 | ! Clear the interrupt in the core. | |
312 | ||
313 | trap_clear_asi_intr_r: | |
314 | ldxa [%g0]ASI_SWVR_INTR_R, %l5 | |
315 | cmp %l5, 63 ! check for correct vector number | |
316 | bne test_failed | |
317 | nop | |
318 | ||
319 | ! Done. | |
320 | ||
321 | trap_done: | |
322 | jmpl %o7+0x8, %g0 | |
323 | nop | |
324 | ||
325 | ||
326 | ||
327 | ||
328 | /************************************************************************ | |
329 | RAS | |
330 | Trap Handlers | |
331 | ************************************************************************/ | |
332 | My_Recoverable_Sw_error_trap: | |
333 | ! Signal trap taken | |
334 | setx EXECUTED, %l0, %o6 | |
335 | ! save trap type value | |
336 | rdpr %tt, %o7 | |
337 | ||
338 | inc %i7 | |
339 | ||
340 | check_desr_tt40: | |
341 | ldxa [%g0]0x4c, %g2 | |
342 | nop | |
343 | setx 0xb300000000000000, %l0, %g3 | |
344 | subcc %g2, %g3, %g4 | |
345 | brnz %g4, test_failed | |
346 | nop | |
347 | ||
348 | check_DSFSR_tt32: | |
349 | set 0x18, %g1 | |
350 | ldxa [%g1]0x58, %g2 | |
351 | nop | |
352 | /* | |
353 | set 0x4, %g3 | |
354 | subcc %g2, %g3, %g4 | |
355 | brnz %g4, test_failed | |
356 | nop | |
357 | */ | |
358 | ||
359 | ||
360 | check_per_tt40: | |
361 | setx SOC_PER_REG, %l7, %g1 | |
362 | ldx [%g1], %g2 | |
363 | setx 0x8000000000000000, %g7, %g1 | |
364 | set 0x1, %g3 | |
365 | sllx %g3, ERR_FIELD, %g4 | |
366 | or %g1, %g4, %g3 | |
367 | sub %g2, %g3, %g5 | |
368 | brnz %g5, test_failed | |
369 | nop | |
370 | ||
371 | clear_per_tt40: | |
372 | setx SOC_PER_REG, %l7, %g1 | |
373 | stx %g0, [%g1] | |
374 | nop | |
375 | ||
376 | clear_ejr_tt40: | |
377 | setx SOC_EJR_REG, %l7, %g1 | |
378 | stx %g0, [%g1] | |
379 | nop | |
380 | ||
381 | clear_eie_tt40: | |
382 | setx SOC_EIE_REG, %l7, %g1 | |
383 | stx %g0, [%g1] | |
384 | nop | |
385 | ||
386 | trap_done_tt40: | |
387 | done | |
388 | nop | |
389 | ||
390 | ||
391 | My_Corrected_ECC_error_trap: | |
392 | ! Signal trap taken | |
393 | setx EXECUTED, %l0, %o6 | |
394 | ! save trap type value | |
395 | rdpr %tt, %o7 | |
396 | ||
397 | inc %i7 | |
398 | ||
399 | check_desr_tt63: | |
400 | ldxa [%g0]0x4c, %g2 | |
401 | nop | |
402 | setx 0x8b00000000000000, %l0, %g3 | |
403 | subcc %g2, %g3, %g4 | |
404 | brnz %g4, test_failed | |
405 | ||
406 | check_per_tt63: | |
407 | setx SOC_PER_REG, %l7, %i0 | |
408 | ldx [%i0], %i1 | |
409 | setx 0x8000000000000000, %l7, %o3 !valid bit | |
410 | set 0x1, %i2 | |
411 | sllx %i2, ERR_FIELD, %i3 | |
412 | or %i3, %o3, %i4 | |
413 | sub %i1, %i4, %i5 | |
414 | brnz %i5, test_failed | |
415 | nop | |
416 | ||
417 | clear_per_tt63: | |
418 | setx SOC_PER_REG, %l7, %i0 | |
419 | stx %g0, [%i0] | |
420 | nop | |
421 | done | |
422 | nop | |
423 | ||
424 | check_DSFSR_tt63: | |
425 | set 0x18, %g1 | |
426 | ldxa [%g1]0x58, %g5 | |
427 | ||
428 | trap_done_tt63: | |
429 | done | |
430 | nop | |
431 | ||
432 | ||
433 | ||
434 | /************************************************************************ | |
435 | Test case data start | |
436 | ************************************************************************/ | |
437 | ||
438 | .align 1024 | |
439 | .data | |
440 | user_data_start: | |
441 | .word 0x0 | |
442 | .word 0x0 | |
443 | .word 0x0 | |
444 | .word 0x0 | |
445 | user_data_end: | |
446 | .end | |
447 |