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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_err_l2_LDRU_cecc_trap.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define ENABLE_PCIE_LINK_TRAINING | |
39 | #define MAIN_PAGE_HV_ALSO | |
40 | ||
41 | ||
42 | #define L2_ENTRY_PA 0xa000000000 | |
43 | #define TEST_DATA1 0x5555555555555555 | |
44 | #define L2_ENTRY_PA0 0x30000008 | |
45 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 | |
46 | #define SPARC_ES_W1C_VALUE 0xefffffff | |
47 | #define TT_SW_Error 0x40 | |
48 | #define DMA_DATA_BYP_ADDR1 0xfffc000030aa0000 | |
49 | ||
50 | ||
51 | #include "hboot.s" | |
52 | #include "asi_s.h" | |
53 | #include "err_defines.h" | |
54 | #include "peu_defines.h" | |
55 | ||
56 | ||
57 | .text | |
58 | .global main | |
59 | ||
60 | main: | |
61 | ||
62 | ||
63 | ! Boot code does not provide TLB translation for IO address space | |
64 | ta T_CHANGE_HPRIV | |
65 | ||
66 | ||
67 | disable_l1_DCache: | |
68 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
69 | ! Remove bit 2 | |
70 | andn %l0, 0x2, %l0 | |
71 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
72 | ||
73 | enable_err_reporting: | |
74 | setx L2EE_PA0, %l0, %l1 | |
75 | ldx [%l1], %l2 | |
76 | mov 0x3, %l0 | |
77 | or %l2, %l0, %l2 | |
78 | ! stx %l2, [%l1] | |
79 | ||
80 | ||
81 | ||
82 | clear_l2_ESR: | |
83 | setx L2_ES_W1C_VALUE, %l0, %l1 | |
84 | setx L2ES_PA0, %l6, %g1 | |
85 | stx %l1, [%g1] | |
86 | ||
87 | ||
88 | set_L2_Directly_Mapped_Mode: | |
89 | setx L2CS_PA0, %l6, %g1 ! Bit 1 in L2 Control Status Register | |
90 | mov 0x2, %l0 | |
91 | stx %l0, [%g1] | |
92 | ||
93 | setx TEST_DATA1, %l0, %g5 | |
94 | store_to_L2_way0: | |
95 | set 0x30aa0000, %g2 ! bits [21:18] select way | |
96 | stx %g5, [%g2] | |
97 | membar #Sync | |
98 | ||
99 | ||
100 | set 0x8,%l1 | |
101 | clr %l2 | |
102 | loop: | |
103 | inc %l2 | |
104 | cmp %l1,%l2 | |
105 | bne loop | |
106 | nop | |
107 | ||
108 | L2_diag_load: | |
109 | setx 0x3ffff8, %l0, %l2 ! Mask for extracting [21:3] | |
110 | setx L2_ENTRY_PA, %l0, %g4 | |
111 | and %g2, %l2, %g5 !g2 has L2 PA, | |
112 | or %g5, %g4, %g5 !g5 now has Diagnostic Data Array address | |
113 | ldx [%g5], %g6 | |
114 | membar #Sync | |
115 | ||
116 | set 0x8,%l1 | |
117 | clr %l2 | |
118 | loop1: | |
119 | inc %l2 | |
120 | cmp %l1,%l2 | |
121 | bne loop1 | |
122 | nop | |
123 | ||
124 | flip_one_bit: | |
125 | ! Flip two bits to inject error | |
126 | xor %g6, 0x220, %g6 | |
127 | stx %g6, [%g5] | |
128 | membar #Sync | |
129 | ||
130 | set 0x8,%l1 | |
131 | clr %l2 | |
132 | loop3: | |
133 | inc %l2 | |
134 | cmp %l1,%l2 | |
135 | bne loop3 | |
136 | nop | |
137 | ||
138 | PIO2_noexp: nop; | |
139 | ! $EV trig_pc_d(1, @VA(.MAIN.PIO2_noexp)) -> EnablePCIeIgCmd ("PIO_NOEXP",0,0,0,1) | |
140 | ||
141 | PIO2: nop; nop; nop; nop; nop; nop; nop; nop; | |
142 | ||
143 | ||
144 | Wr_Evnt: nop; | |
145 | ! $EV trig_pc_d(1, @VA(.MAIN.Wr_Evnt) -> EnablePCIeIgCmd ("DMARD_UE", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h40", 1 ) | |
146 | ||
147 | clr %l7 | |
148 | set 0x20, %i7 | |
149 | wr_evnt_loop: | |
150 | inc %l7 | |
151 | cmp %l7,%i7 | |
152 | bne wr_evnt_loop | |
153 | nop | |
154 | ||
155 | PIO3_noexp: nop; | |
156 | ! $EV trig_pc_d(1, @VA(.MAIN.PIO3_noexp)) -> EnablePCIeIgCmd ("PIO_NOEXP",0,0,0,1) | |
157 | ||
158 | PIO3: nop; nop; nop; nop; nop; nop; nop; nop; | |
159 | ||
160 | ||
161 | Wr_Evnt_mec: nop; | |
162 | ! $EV trig_pc_d(1, @VA(.MAIN.Wr_Evnt_mec) -> EnablePCIeIgCmd ("DMARD_UE", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h40", 1 ) | |
163 | clr %l7 | |
164 | set 0x20, %i7 | |
165 | wr_evnt_loop_mec: | |
166 | inc %l7 | |
167 | cmp %l7,%i7 | |
168 | bne wr_evnt_loop_mec | |
169 | nop | |
170 | ||
171 | check_l2_ESR_mec: | |
172 | setx L2ES_PA0, %l6, %g1 | |
173 | ldx [%g1], %l4 | |
174 | membar #Sync | |
175 | ||
176 | ||
177 | compute_error_mec: | |
178 | mov 0x1, %l1 | |
179 | sllx %l1, L2ES_LDRU, %l7 | |
180 | sllx %l1, L2ES_VEU, %l3 | |
181 | or %l7, %l3, %l7 | |
182 | sllx %l1, L2ES_MEU, %l3 | |
183 | or %l7, %l3, %l7 | |
184 | ! mov 0x1, %l1 | |
185 | ! sllx %g4, L2ES_TID, %l3 ! ID of thread that encountered error | |
186 | ! or %l7, %l3, %l7 ! %l7 has expected value | |
187 | ! membar #Sync | |
188 | ||
189 | verify_ESR_mec: | |
190 | cmp %l7, %l4 ! l7 has expected value l4 has actula value | |
191 | bne test_fail | |
192 | ||
193 | check_l2_EAR_mec: | |
194 | setx L2EA_PA0, %l6, %l3 | |
195 | ldx [%l3], %l4 | |
196 | membar #Sync | |
197 | ||
198 | ||
199 | ||
200 | enable_l1_DCache: | |
201 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
202 | or %l0, 0x2, %l0 | |
203 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
204 | ||
205 | ||
206 | ba test_pass | |
207 | nop | |
208 | ||
209 | ||
210 | ||
211 | /******************************************************* | |
212 | * Exit code | |
213 | *******************************************************/ | |
214 | ||
215 | test_pass: | |
216 | ta T_GOOD_TRAP | |
217 | ||
218 | test_fail: | |
219 | ta T_BAD_TRAP | |
220 |