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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: tcu_regs_dram_2.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define MAIN_PAGE_NUCLEUS_ALSO | |
39 | #define MAIN_PAGE_HV_ALSO | |
40 | ||
41 | #define TEST_DATA0 0x4c3fdead4c3fbeef | |
42 | #define tmp1 %l2 | |
43 | #define tmp2 %l3 | |
44 | #define tmp3 %l4 | |
45 | #define tmp4 %l5 | |
46 | ||
47 | ||
48 | #include "asi_s.h" | |
49 | #include "mcu_defines.h" | |
50 | #include "tcu_defines.h" | |
51 | ||
52 | /************************************************************************ | |
53 | Test case code start | |
54 | ************************************************************************/ | |
55 | ||
56 | #ifdef FAST_BOOT | |
57 | #define RESET_VEC 0x0000000000000000 | |
58 | #else | |
59 | #define RESET_VEC 0xfffffffff0000000 | |
60 | #endif | |
61 | ||
62 | SECTION .RED_SEC TEXT_VA = RESET_VEC | |
63 | attr_text { | |
64 | Name=.RED_SEC, | |
65 | hypervisor | |
66 | } | |
67 | ||
68 | .text | |
69 | nop | |
70 | nop | |
71 | nop | |
72 | nop | |
73 | nop | |
74 | nop | |
75 | nop | |
76 | nop | |
77 | ||
78 | .global main | |
79 | ||
80 | ||
81 | ! DRAM PRECHARGE COMMAND PERIOD | |
82 | L1: | |
83 | set 0x3, %i3 | |
84 | setx 0x8400000000, %l5, %l6 | |
85 | add %l6, 0xb8, %g7 | |
86 | ldx [%g7], %g3 | |
87 | cmp %g3, %i3 | |
88 | bne bad_trap | |
89 | membar #Sync | |
90 | ||
91 | ! DRAM WRITE RECOVER PERIOD | |
92 | L2: | |
93 | set 0x3, %i3 | |
94 | setx 0x8400000000, %l5, %l6 | |
95 | add %l6, 0xc0, %g7 | |
96 | ldx [%g7], %g3 | |
97 | cmp %g3, %i3 | |
98 | bne bad_trap | |
99 | membar #Sync | |
100 | ||
101 | ! DRAM AUTOREFRESH TO ACTIVE PERIOD | |
102 | L3: | |
103 | set 0x27, %i3 | |
104 | setx 0x8400000000, %l5, %l6 | |
105 | add %l6, 0xc8, %g7 | |
106 | ldx [%g7], %g3 | |
107 | cmp %g3, %i3 | |
108 | bne bad_trap | |
109 | membar #Sync | |
110 | ||
111 | ! DRAM MODE REG SET COMMAND PERIOD | |
112 | L4: | |
113 | set 0x2, %i3 | |
114 | setx 0x8400000000, %l5, %l6 | |
115 | add %l6, 0xd0, %g7 | |
116 | ldx [%g7], %g3 | |
117 | cmp %g3, %i3 | |
118 | bne bad_trap | |
119 | membar #Sync | |
120 | ||
121 | ! DRAM FOUR ACTIVE WINDOW | |
122 | L5: | |
123 | set 0xa, %i3 | |
124 | setx 0x8400000000, %l5, %l6 | |
125 | add %l6, 0xd8, %g7 | |
126 | ldx [%g7], %g3 | |
127 | cmp %g3, %i3 | |
128 | bne bad_trap | |
129 | membar #Sync | |
130 | ||
131 | ! DRAM INTERNAL WRITE TO READ COMMAND DELAY | |
132 | L6: | |
133 | set 0x2, %i3 | |
134 | setx 0x8400000000, %l5, %l6 | |
135 | add %l6, 0xe0, %g7 | |
136 | ldx [%g7], %g3 | |
137 | cmp %g3, %i3 | |
138 | bne bad_trap | |
139 | membar #Sync | |
140 | ||
141 | ! DRAM PRECHARGE WAIT DURING POWER UP | |
142 | L7: | |
143 | set 0x55, %i3 | |
144 | setx 0x8400000000, %l5, %l6 | |
145 | add %l6, 0xe8, %g7 | |
146 | ldx [%g7], %g3 | |
147 | cmp %g3, %i3 | |
148 | bne bad_trap | |
149 | membar #Sync | |
150 | ||
151 | ! DRAM DIMM STACKED | |
152 | L8: | |
153 | setx 0x8400000000, %l5, %l6 | |
154 | add %l6, 0x108, %g7 | |
155 | ldx [%g7], %g3 | |
156 | cmp %g3, %g0 | |
157 | bne bad_trap | |
158 | membar #Sync | |
159 | ||
160 | ! DRAM EXTENDED MODE (2) | |
161 | L9: | |
162 | setx 0x8400000000, %l5, %l6 | |
163 | add %l6, 0x110, %g7 | |
164 | ldx [%g7], %g3 | |
165 | cmp %g3, %g0 | |
166 | bne bad_trap | |
167 | membar #Sync | |
168 | ||
169 | ! DRAM EXTENDED MODE (1) | |
170 | L10: | |
171 | set 0x18, %i3 | |
172 | setx 0x8400000000, %l5, %l6 | |
173 | add %l6, 0x118, %g7 | |
174 | ldx [%g7], %g3 | |
175 | cmp %g3, %i3 | |
176 | bne bad_trap | |
177 | membar #Sync | |
178 | ||
179 | ! DRAM EXTENDED MODE (3) | |
180 | L11: | |
181 | setx 0x8400000000, %l5, %l6 | |
182 | add %l6, 0x120, %g7 | |
183 | ldx [%g7], %g3 | |
184 | cmp %g3, %g0 | |
185 | bne bad_trap | |
186 | membar #Sync | |
187 | ||
188 | ! DRAM 8 BANK MODE | |
189 | L12: | |
190 | set 0x1, %i3 | |
191 | setx 0x8400000000, %l5, %l6 | |
192 | add %l6, 0x128, %g7 | |
193 | ldx [%g7], %g3 | |
194 | cmp %g3, %i3 | |
195 | bne bad_trap | |
196 | membar #Sync | |
197 | ||
198 | ! DRAM BRANCH DISABLED | |
199 | L13: | |
200 | setx 0x8400000000, %l5, %l6 | |
201 | add %l6, 0x138, %g7 | |
202 | ldx [%g7], %g3 | |
203 | cmp %g3, %g0 | |
204 | bne bad_trap | |
205 | membar #Sync | |
206 | ||
207 | ! DRAM SELECT LOW ORDER ADDRESS BITS | |
208 | L14: | |
209 | setx 0x8400000000, %l5, %l6 | |
210 | add %l6, 0x140, %g7 | |
211 | ldx [%g7], %g3 | |
212 | cmp %g3, %g0 | |
213 | bne bad_trap | |
214 | membar #Sync | |
215 | ||
216 | ! DRAM SINGLE CHANNEL MODE | |
217 | L15: | |
218 | setx 0x8400000000, %l5, %l6 | |
219 | add %l6, 0x148, %g7 | |
220 | ldx [%g7], %g3 | |
221 | cmp %g3, %g0 | |
222 | bne bad_trap | |
223 | membar #Sync | |
224 | ||
225 | ! DRAM DIMMs PRESENT | |
226 | L16: | |
227 | set 0x1, %i3 | |
228 | setx 0x8400000000, %l5, %l6 | |
229 | add %l6, 0x1a0, %g7 | |
230 | ldx [%g7], %g3 | |
231 | cmp %g3, %i3 | |
232 | bne bad_trap | |
233 | membar #Sync | |
234 | ||
235 | ! DRAM FAIL-OVER STATUS | |
236 | L17: | |
237 | setx 0x8400000000, %l5, %l6 | |
238 | add %l6, 0x220, %g7 | |
239 | ldx [%g7], %g3 | |
240 | cmp %g3, %g0 | |
241 | bne bad_trap | |
242 | membar #Sync | |
243 | ||
244 | ! DRAM FAIL-OVER MASK | |
245 | L18: | |
246 | setx 0x8400000000, %l5, %l6 | |
247 | add %l6, 0x228, %g7 | |
248 | ldx [%g7], %g3 | |
249 | cmp %g3, %g0 | |
250 | bne bad_trap | |
251 | membar #Sync | |
252 | ||
253 | ! FBD CHANNEL STATE | |
254 | L19: | |
255 | setx 0x8400000000, %l5, %l6 | |
256 | add %l6, 0x800, %g7 | |
257 | ldx [%g7], %g3 | |
258 | cmp %g3, %g0 | |
259 | bne bad_trap | |
260 | membar #Sync | |
261 | ||
262 | ! FBD FAST RESET FLAG (Bug filed 117094) | |
263 | ! Wait for JC to update the Riesling 6/22/06 | |
264 | ! L20: | |
265 | ! setx 0x8400000000, %l5, %l6 | |
266 | ! add %l6, 0x808, %g7 | |
267 | ! ldx [%g7], %g3 | |
268 | ! cmp %g3, %g0 | |
269 | ! bne bad_trap | |
270 | ! membar #Sync | |
271 | ||
272 | ! FBD CHANNEL RESET | |
273 | L21: | |
274 | setx 0x8400000000, %l5, %l6 | |
275 | add %l6, 0x810, %g7 | |
276 | ldx [%g7], %g3 | |
277 | cmp %g3, %g0 | |
278 | bne bad_trap | |
279 | membar #Sync | |
280 | ||
281 | ! TS1 SOUTHBOUND TO NORTHBOUND MAPPING | |
282 | L22: | |
283 | setx 0x8400000000, %l5, %l6 | |
284 | add %l6, 0x818, %g7 | |
285 | ldx [%g7], %g3 | |
286 | cmp %g3, %g0 | |
287 | bne bad_trap | |
288 | membar #Sync | |
289 | ||
290 | ! TS1 TEST PARAMETER | |
291 | L23: | |
292 | setx 0x8400000000, %l5, %l6 | |
293 | add %l6, 0x820, %g7 | |
294 | ldx [%g7], %g3 | |
295 | cmp %g3, %g0 | |
296 | bne bad_trap | |
297 | membar #Sync | |
298 | ||
299 | ! TS3 FAILOVER CONFIGURATION | |
300 | ||
301 | L24: | |
302 | set 0xffff, %i3 | |
303 | setx 0x8400000000, %l5, %l6 | |
304 | add %l6, 0x828, %g7 | |
305 | ldx [%g7], %g3 | |
306 | cmp %g3, %i3 | |
307 | bne bad_trap | |
308 | membar #Sync | |
309 | ||
310 | good_trap: | |
311 | ba good_trap | |
312 | nop | |
313 | nop | |
314 | bad_trap: | |
315 | ba bad_trap | |
316 | nop | |
317 | ||
318 | ||
319 | /************************************************************************ | |
320 | Test case data start | |
321 | ************************************************************************/ | |
322 | .data | |
323 | .word 0x0 | |
324 | user_data_start: | |
325 | .end | |
326 |