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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: pcg_ports.vri | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | #define PCG_MII_IN_TIMING PSAMPLE | |
36 | #define PCG_MII_OUT_TIMING PHOLD #0 | |
37 | #define PCG_MII_CLK_TIMING CLOCK | |
38 | ||
39 | #define PCG_GMII_IN_TIMING PSAMPLE | |
40 | #define PCG_GMII_OUT_TIMING PHOLD #0 | |
41 | #define PCG_GMII_CLK_TIMING CLOCK | |
42 | ||
43 | #define PCG_XGMII_IN_TIMING PSAMPLE | |
44 | #define PCG_XGMII_OUT_TIMING PHOLD #0 | |
45 | #define PCG_XGMII_CLK_TIMING CLOCK | |
46 | ||
47 | interface m0_rx { | |
48 | output [7:0] data PCG_MII_OUT_TIMING; | |
49 | output crs PCG_MII_OUT_TIMING; | |
50 | output col PCG_MII_OUT_TIMING; | |
51 | output dv PCG_MII_OUT_TIMING; | |
52 | output [3:0] config PCG_MII_OUT_TIMING; | |
53 | output err PCG_MII_OUT_TIMING; | |
54 | input clk PCG_MII_CLK_TIMING; | |
55 | } | |
56 | ||
57 | interface m0_tx { | |
58 | input [7:0] data PCG_MII_IN_TIMING; | |
59 | input en PCG_MII_IN_TIMING; | |
60 | output [3:0] config PCG_MII_OUT_TIMING; | |
61 | input err PCG_MII_IN_TIMING; | |
62 | input clk PCG_MII_CLK_TIMING; | |
63 | } | |
64 | ||
65 | interface m1_rx { | |
66 | output [7:0] data PCG_MII_OUT_TIMING; | |
67 | output crs PCG_MII_OUT_TIMING; | |
68 | output col PCG_MII_OUT_TIMING; | |
69 | output dv PCG_MII_OUT_TIMING; | |
70 | output [3:0] config PCG_MII_OUT_TIMING; | |
71 | output err PCG_MII_OUT_TIMING; | |
72 | input clk PCG_MII_CLK_TIMING; | |
73 | } | |
74 | ||
75 | interface m1_tx { | |
76 | input [7:0] data PCG_MII_IN_TIMING; | |
77 | input en PCG_MII_IN_TIMING; | |
78 | output [3:0] config PCG_MII_OUT_TIMING; | |
79 | input err PCG_MII_IN_TIMING; | |
80 | input clk PCG_MII_CLK_TIMING; | |
81 | } | |
82 | ||
83 | interface m2_rx { | |
84 | output [7:0] data PCG_MII_OUT_TIMING; | |
85 | output crs PCG_MII_OUT_TIMING; | |
86 | output col PCG_MII_OUT_TIMING; | |
87 | output dv PCG_MII_OUT_TIMING; | |
88 | output [3:0] config PCG_MII_OUT_TIMING; | |
89 | output err PCG_MII_OUT_TIMING; | |
90 | input clk PCG_MII_CLK_TIMING; | |
91 | } | |
92 | ||
93 | interface m2_tx { | |
94 | input [7:0] data PCG_MII_IN_TIMING; | |
95 | input en PCG_MII_IN_TIMING; | |
96 | output [3:0] config PCG_MII_OUT_TIMING; | |
97 | input err PCG_MII_IN_TIMING; | |
98 | input clk PCG_MII_CLK_TIMING; | |
99 | } | |
100 | ||
101 | interface m3_rx { | |
102 | output [7:0] data PCG_MII_OUT_TIMING; | |
103 | output crs PCG_MII_OUT_TIMING; | |
104 | output col PCG_MII_OUT_TIMING; | |
105 | output dv PCG_MII_OUT_TIMING; | |
106 | output [3:0] config PCG_MII_OUT_TIMING; | |
107 | output err PCG_MII_OUT_TIMING; | |
108 | input clk PCG_MII_CLK_TIMING; | |
109 | } | |
110 | ||
111 | interface m3_tx { | |
112 | input [7:0] data PCG_MII_IN_TIMING; | |
113 | input en PCG_MII_IN_TIMING; | |
114 | output [3:0] config PCG_MII_OUT_TIMING; | |
115 | input err PCG_MII_IN_TIMING; | |
116 | input clk PCG_MII_CLK_TIMING; | |
117 | } | |
118 | ||
119 | ||
120 | port xgmii_def { | |
121 | rxd; | |
122 | rxcrs; | |
123 | rxcol; | |
124 | rxdv; | |
125 | rxerr; | |
126 | rxclk_int; | |
127 | txd; | |
128 | txen; | |
129 | txerr; | |
130 | txclk_int; | |
131 | rx_config; | |
132 | tx_config; | |
133 | ||
134 | } | |
135 | ||
136 | port gmii_def { | |
137 | rxd; | |
138 | rxcrs; | |
139 | rxcol; | |
140 | rxdv; | |
141 | rxerr; | |
142 | rxclk; | |
143 | txd; | |
144 | txen; | |
145 | txerr; | |
146 | txclk; | |
147 | rx_config; | |
148 | tx_config; | |
149 | } | |
150 | ||
151 | ||
152 | port mii_def { | |
153 | rxd; | |
154 | rxcrs; | |
155 | rxcol; | |
156 | rxdv; | |
157 | rxerr; | |
158 | rxclk; | |
159 | txd; | |
160 | txen; | |
161 | txerr; | |
162 | txclk; | |
163 | rx_config; | |
164 | tx_config; | |
165 | } | |
166 | ||
167 | ||
168 | ||
169 | bind mii_def m0 { | |
170 | rxd m0_rx.data; | |
171 | rxcrs m0_rx.crs; | |
172 | rxcol m0_rx.col; | |
173 | rxdv m0_rx.dv; | |
174 | rxerr m0_rx.err; | |
175 | rxclk m0_rx.clk; | |
176 | txd m0_tx.data; | |
177 | txen m0_tx.en; | |
178 | txerr m0_tx.err; | |
179 | txclk m0_tx.clk; | |
180 | rx_config m0_rx.config; | |
181 | tx_config m0_tx.config; | |
182 | } | |
183 | ||
184 | bind mii_def m1 { | |
185 | rxd m1_rx.data; | |
186 | rxcrs m1_rx.crs; | |
187 | rxcol m1_rx.col; | |
188 | rxdv m1_rx.dv; | |
189 | rxerr m1_rx.err; | |
190 | rxclk m1_rx.clk; | |
191 | txd m1_tx.data; | |
192 | txen m1_tx.en; | |
193 | txerr m1_tx.err; | |
194 | txclk m1_tx.clk; | |
195 | rx_config m1_rx.config; | |
196 | tx_config m1_tx.config; | |
197 | } | |
198 | ||
199 | bind mii_def m2 { | |
200 | rxd m2_rx.data; | |
201 | rxcrs m2_rx.crs; | |
202 | rxcol m2_rx.col; | |
203 | rxdv m2_rx.dv; | |
204 | rxerr m2_rx.err; | |
205 | rxclk m2_rx.clk; | |
206 | txd m2_tx.data; | |
207 | txen m2_tx.en; | |
208 | txerr m2_tx.err; | |
209 | txclk m2_tx.clk; | |
210 | rx_config m2_rx.config; | |
211 | tx_config m2_tx.config; | |
212 | } | |
213 | ||
214 | ||
215 | bind mii_def m3 { | |
216 | rxd m3_rx.data; | |
217 | rxcrs m3_rx.crs; | |
218 | rxcol m3_rx.col; | |
219 | rxdv m3_rx.dv; | |
220 | rxerr m3_rx.err; | |
221 | rxclk m3_rx.clk; | |
222 | txd m3_tx.data; | |
223 | txen m3_tx.en; | |
224 | txerr m3_tx.err; | |
225 | txclk m3_tx.clk; | |
226 | rx_config m3_rx.config; | |
227 | tx_config m3_tx.config; | |
228 | } | |
229 | ||
230 | ||
231 | ||
232 | ||
233 | bind gmii_def gm0 { | |
234 | rxd m0_rx.data; | |
235 | rxcrs m0_rx.crs; | |
236 | rxcol m0_rx.col; | |
237 | rxdv m0_rx.dv; | |
238 | rxerr m0_rx.err; | |
239 | rxclk m0_rx.clk; | |
240 | txd m0_tx.data; | |
241 | txen m0_tx.en; | |
242 | txerr m0_tx.err; | |
243 | txclk m0_tx.clk; | |
244 | rx_config m0_rx.config; | |
245 | tx_config m0_tx.config; | |
246 | } | |
247 | ||
248 | bind gmii_def gm1 { | |
249 | rxd m1_rx.data; | |
250 | rxcrs m1_rx.crs; | |
251 | rxcol m1_rx.col; | |
252 | rxdv m1_rx.dv; | |
253 | rxerr m1_rx.err; | |
254 | rxclk m1_rx.clk; | |
255 | txd m1_tx.data; | |
256 | txen m1_tx.en; | |
257 | txerr m1_tx.err; | |
258 | txclk m1_tx.clk; | |
259 | rx_config m1_rx.config; | |
260 | tx_config m1_tx.config; | |
261 | } | |
262 | ||
263 | ||
264 | bind gmii_def gm2 { | |
265 | rxd m2_rx.data; | |
266 | rxcrs m2_rx.crs; | |
267 | rxcol m2_rx.col; | |
268 | rxdv m2_rx.dv; | |
269 | rxerr m2_rx.err; | |
270 | rxclk m2_rx.clk; | |
271 | txd m2_tx.data; | |
272 | txen m2_tx.en; | |
273 | txerr m2_tx.err; | |
274 | txclk m2_tx.clk; | |
275 | rx_config m2_rx.config; | |
276 | tx_config m2_tx.config; | |
277 | } | |
278 | ||
279 | ||
280 | bind gmii_def gm3 { | |
281 | rxd m3_rx.data; | |
282 | rxcrs m3_rx.crs; | |
283 | rxcol m3_rx.col; | |
284 | rxdv m3_rx.dv; | |
285 | rxerr m3_rx.err; | |
286 | rxclk m3_rx.clk; | |
287 | txd m3_tx.data; | |
288 | txen m3_tx.en; | |
289 | txerr m3_tx.err; | |
290 | txclk m3_tx.clk; | |
291 | rx_config m3_rx.config; | |
292 | tx_config m3_tx.config; | |
293 | } | |
294 | ||
295 | ||
296 | bind xgmii_def xgm0 { | |
297 | rxd m0_rx.data; | |
298 | rxcrs m0_rx.crs; | |
299 | rxcol m0_rx.col; | |
300 | rxdv m0_rx.dv; | |
301 | rxerr m0_rx.err; | |
302 | rxclk_int m0_rx.clk; | |
303 | txd m0_tx.data; | |
304 | txen m0_tx.en; | |
305 | txerr m0_tx.err; | |
306 | txclk_int m0_tx.clk; | |
307 | rx_config m0_rx.config; | |
308 | tx_config m0_tx.config; | |
309 | } | |
310 | ||
311 | ||
312 | bind xgmii_def xgm1 { | |
313 | rxd m1_rx.data; | |
314 | rxcrs m1_rx.crs; | |
315 | rxcol m1_rx.col; | |
316 | rxdv m1_rx.dv; | |
317 | rxerr m1_rx.err; | |
318 | rxclk_int m1_rx.clk; | |
319 | txd m1_tx.data; | |
320 | txen m1_tx.en; | |
321 | txerr m1_tx.err; | |
322 | txclk_int m1_tx.clk; | |
323 | rx_config m1_rx.config; | |
324 | tx_config m1_tx.config; | |
325 | } | |
326 | ||
327 |