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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / verilog / err_sync / err.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: err.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35`ifdef CORE_0
36
37
38
39module err_c0t0 ();
40`ifndef GATESIM
41
42`include "defines.vh"
43
44wire [2:0] mycid;
45wire [2:0] mytid;
46wire [5:0] mytnum;
47
48integer junk;
49reg ready;
50reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
51reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
52
53reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
54reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
55
56reg update_dfesr_w;
57
58reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
59reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
60
61reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
62reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
63
64reg sync_asi;
65reg chk_if_asi_ld;
66reg [63:0] ld_data_w;
67
68reg desr_asi_rd, desr_wr, desr_pend_wr;
69
70assign mycid = 0;
71assign mytid = 0;
72assign mytnum = 0*8 + 0;
73
74initial begin //{
75 desr_asi_rd = 1'b0;
76 desr_pend_wr = 1'b0;
77 ready = 0;
78 @(posedge `SPC0.l2clk) ;
79 @(posedge `SPC0.l2clk) ;
80 ready = `PARGS.err_sync_on;
81end //}
82
83`define DSFSR_NEW_IN_0 `SPC0.tlu.ras.dsfsr_0_new_in
84`define ISFSR_NEW_IN_0 `SPC0.tlu.ras.isfsr_0_new_in
85
86`define DSFSR_0 `SPC0.tlu.ras.dsfsr_0
87`define ISFSR_0 `SPC0.tlu.ras.isfsr_0
88`define DSFAR_0 `SPC0.tlu.dfd.dsfar_0
89
90`define ASI_WR_DSFSR_0 `SPC0.tlu.ras.asi_wr_dsfsr[0]
91`define ASI_WR_ISFSR_0 `SPC0.tlu.ras.asi_wr_isfsr[0]
92
93`define RAS_WRITE_DESR_1st_0 `SPC0.tlu.dfd.ras_write_desr_1st[0]
94`define RAS_WRITE_DESR_2nd_0 `SPC0.tlu.dfd.ras_write_desr_2nd[0]
95`define DESR_asi_rd_0 `SPC0.tlu.ras_rd_desr[0]
96`define DESR_0 `SPC0.tlu.dfd.desr_0
97
98`define RAS_WRITE_FESR_0 `SPC0.tlu.ras.write_fesr[0]
99`define FESR_0 `SPC0.tlu.dfd.fesr_0
100
101`define ST_ERR_0 `SPC0.tlu.trl0.take_ftt & `SPC0.tlu.trl0.trap[0]
102`define SW_REC_ERR_0 `SPC0.tlu.trl0.take_ade & `SPC0.tlu.trl0.trap[0]
103`define DATA_ACC_ERR_0 `SPC0.tlu.trl0.take_dae & `SPC0.tlu.trl0.trap[0]
104`define INST_ACC_ERR_0 `SPC0.tlu.trl0.take_iae & `SPC0.tlu.trl0.trap[0]
105`define INT_PROC_ERR_0 `SPC0.tlu.trl0.take_ipe & `SPC0.tlu.trl0.trap[0]
106`define HW_CORR_ERR_0 `SPC0.tlu.trl0.take_eer & `SPC0.tlu.trl0.trap[0]
107`define INST_ACC_MMU_ERR_0 `SPC0.tlu.trl0.take_ime & `SPC0.tlu.trl0.trap[0]
108`define DATA_ACC_MMU_ERR_0 `SPC0.tlu.trl0.take_dme & `SPC0.tlu.trl0.trap[0]
109
110`define LSU_LD_VALID_B `PROBES0.lsu_ld_valid
111`define LSU_TID_DEC_B_0 `PROBES0.lsu_tid_dec_b[0]
112`define ASI_LD_0 `SPC0.lsu.lmd.lmq0_pkt[60] & (`SPC0.lsu.lmd.lmq0_pkt[49:48] == 2'b0)
113`define ASI_0 `SPC0.lsu.lmd.lmq0_pkt[47:40]
114`define ASI_ADDR_0 `SPC0.lsu.lmd.lmq0_pkt[39:0]
115`define ASI_LD_DATA_0 `SPC0.lsu_exu_ld_data_b[63:0]
116`define ASI_LD_COMP_0 tb_top.nas_top.c0.t0.complete_fw2
117
118//SPU specific - only one SPU per core
119`define SPU_MA_BUSY_0 `SPC0.spu.spu_pmu_ma_busy[3]
120`define SPU_MA_TID_0 `SPC0.spu.spu_pmu_ma_busy[2:0]
121
122////////////////////////////////////////////////////////////////////////////////
123//Capture the status register data from rtl. For disrupting traps,
124//rtl can modify the contents of the status register before the
125//trap is taken and intp message is sent to Riesling.
126//For precise traps, once the status register is updated rtl can't
127//change the register again before jumping to the trap handler.
128//So, for deferred and disrupting traps, inform Riesling when the
129//register is modified while for precise traps wait until Fw2 before
130//telling Riesling.
131
132//TLU asserts the flush and input signals in W stage. I latch them at the
133//+ve edge of FX4.
134
135always @(negedge (`SPC0.l2clk & ready))
136begin // {
137 if (`DESR_asi_rd_0)
138 desr_asi_rd <= 1'b1;
139 if (desr_asi_rd)
140 begin
141 if (desr_wr)
142 desr_pend_wr <= 1'b1;
143 if (`ASI_LD_COMP_0[2])
144 desr_asi_rd <= 1'b0;
145 end
146
147 update_dsfsr_w <= (`DSFSR_NEW_IN_0 != 4'b0) && ~`ASI_WR_DSFSR_0;
148 update_isfsr_w <= (`ISFSR_NEW_IN_0 != 3'b0) && ~`ASI_WR_ISFSR_0;
149 desr_wr <= (`RAS_WRITE_DESR_1st_0 || `RAS_WRITE_DESR_2nd_0);
150 update_dfesr_w <= `RAS_WRITE_FESR_0;
151 take_err_trap_fx4 <= `ST_ERR_0 | `SW_REC_ERR_0 | `DATA_ACC_ERR_0
152 | `INST_ACC_ERR_0 | `INT_PROC_ERR_0
153 | `HW_CORR_ERR_0 | `INST_ACC_MMU_ERR_0
154 | `DATA_ACC_MMU_ERR_0 ;
155
156
157 if (`ST_ERR_0) int_num_fx4 <= 8'h07;
158 if (`SW_REC_ERR_0) int_num_fx4 <= 8'h40;
159 if (`DATA_ACC_ERR_0) int_num_fx4 <= 8'h32;
160 if (`INST_ACC_ERR_0) int_num_fx4 <= 8'h0A;
161 if (`INT_PROC_ERR_0) int_num_fx4 <= 8'h29;
162 if (`HW_CORR_ERR_0) int_num_fx4 <= 8'h63;
163 if (`INST_ACC_MMU_ERR_0) int_num_fx4 <= 8'h71;
164 if (`DATA_ACC_MMU_ERR_0) int_num_fx4 <= 8'h72;
165
166 update_dsfsr_fx4 <= update_dsfsr_w;
167 update_dsfsr_fx5 <= update_dsfsr_fx4;
168 update_dsfsr_fb <= update_dsfsr_fx5;
169 update_dsfsr_fw <= update_dsfsr_fb;
170 update_dsfsr_fw1 <= update_dsfsr_fw;
171 update_dsfsr_fw2 <= update_dsfsr_fw1;
172
173 update_isfsr_fx4 <= update_isfsr_w;
174 update_isfsr_fx5 <= update_isfsr_fx4;
175 update_isfsr_fb <= update_isfsr_fx5;
176 update_isfsr_fw <= update_isfsr_fb;
177 update_isfsr_fw1 <= update_isfsr_fw;
178 update_isfsr_fw2 <= update_isfsr_fw1;
179
180 take_err_trap_fx5 <= take_err_trap_fx4;
181 take_err_trap_fb <= take_err_trap_fx5;
182 take_err_trap_fw <= take_err_trap_fb;
183 take_err_trap_fw1 <= take_err_trap_fw;
184 take_err_trap_fw2 <= take_err_trap_fw1;
185
186 int_num_fx5 <= int_num_fx4;
187 int_num_fb <= int_num_fx5;
188 int_num_fw <= int_num_fb;
189 int_num_fw1 <= int_num_fw;
190 int_num_fw2 <= int_num_fw1;
191
192 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
193 begin // {
194 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
195 begin //{
196 desr_pend_wr <= 1'b0;
197 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_0[63:56], 45'b0, `DESR_0[10:0]});
198 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_0[63:56], 45'b0, `DESR_0[10:0]});
199 end //}
200 //if (update_dfesr_w)
201 if (`ST_ERR_0)
202 begin //{
203 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_0[61:55], 55'b0});
204 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_0[61:55], 55'b0});
205 end //}
206 if (update_dsfsr_fw2)
207 begin //{
208 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
209 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_0[3:0]});
210 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_0[47:0]});
211
212 end //}
213 if (update_isfsr_fw2)
214 begin //{
215 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
216 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_0[2:0]});
217 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_0[47:0]});
218
219 end //}
220 if (take_err_trap_fw2)
221 begin //{
222 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
223 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
224 end // }
225 end // }
226
227end //}
228
229//removing the addr check as the LSU doesn't flag an invalid_asi_exception
230//if the addr of diagnostic accesses is not in the valid range. The inst.
231//still executes. LSU expects that HP won't use addresses in invalid range.
232
233always @(negedge (`SPC0.l2clk & ready))
234begin // {
235 sync_asi = 1'b0;
236 ld_data_w <= `ASI_LD_DATA_0;
237
238 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_0)
239 chk_if_asi_ld <= 1'b1;
240 else
241 chk_if_asi_ld <= 1'b0;
242
243 if (chk_if_asi_ld & `ASI_LD_0)
244 begin
245 case (`ASI_0)
246 8'h66: //ASI_IC_INSTR
247 begin
248 //if ((`ASI_ADDR_0 >= 0) & (`ASI_ADDR_0 <= 40'h7ff8))
249 sync_asi = 1'b1;
250 end
251 8'h67: //ASI_IC_TAG
252 begin
253 //if ((`ASI_ADDR_0 >= 0) & (`ASI_ADDR_0 <= 40'h7fe0))
254 sync_asi = 1'b1;
255 end
256 8'h46: //ASI_DC_DATA
257 begin
258 sync_asi = 1'b1;
259 end
260 8'h47: //ASI_DC_TAG
261 begin
262 //if ((`ASI_ADDR_0 >= 0) & (`ASI_ADDR_0 <= 40'h7ff0))
263 sync_asi = 1'b1;
264 end
265 8'h48://IRF ECC
266 begin
267 //if ((`ASI_ADDR_0 >= 0) & (`ASI_ADDR_0 <= 40'hF8))
268 sync_asi = 1'b1;
269 end
270 8'h49://FRF ECC
271 begin
272 //if ((`ASI_ADDR_0 >= 0) & (`ASI_ADDR_0 <= 40'hF8))
273 sync_asi = 1'b1;
274 end
275 8'h4A://STB access, stb ptr can be read also
276 begin
277 //if ((`ASI_ADDR_0 >= 0) & (`ASI_ADDR_0 <= 40'h100))
278 sync_asi = 1'b1;
279 end
280 8'h5A://Tick compare reg
281 begin
282 //if ((`ASI_ADDR_0 >= 0) & (`ASI_ADDR_0 <= 40'h38))
283 sync_asi = 1'b1;
284 end
285 8'h5B://TSA
286 begin
287 //if ((`ASI_ADDR_0 >= 0) & (`ASI_ADDR_0 <= 40'h38))
288 sync_asi = 1'b1;
289 end
290 8'h51://MRA
291 begin
292 //if ((`ASI_ADDR_0 >= 0) & (`ASI_ADDR_0 <= 40'h38))
293 sync_asi = 1'b1;
294 end
295 8'h59://scratchpad ecc data read
296 begin
297 //if ((`ASI_ADDR_0 >= 0) & (`ASI_ADDR_0 <= 40'h38))
298 //syncup the ecc data only. For ecc bit 6 is 0.
299 if (~`SPC0.lsu.lmd.lmq0_pkt[6])
300 sync_asi = 1'b1;
301 end
302 8'h40://cwqcsr,ma_sync access
303 begin
304 if ((`ASI_ADDR_0 == 40'h20) || (`ASI_ADDR_0 == 40'h30)
305 || (`ASI_ADDR_0 == 40'h80)
306 || ((`ASI_ADDR_0 == 40'ha0) & (`SPU_MA_BUSY_0 == 0) & (`SPU_MA_TID_0 == 0))
307 )
308 sync_asi = 1'b1;
309 end
310 8'h4C://CLESR, CLFESR access
311 begin
312 if ((`ASI_ADDR_0 == 40'h20) || (`ASI_ADDR_0 == 40'h28))
313 sync_asi = 1'b1;
314 end
315 endcase
316 end
317
318 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
319 begin
320 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_0, `ASI_ADDR_0, ld_data_w);
321 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_0, {24'b0, `ASI_ADDR_0}, ld_data_w[63:0]);
322 end
323end //}
324`endif
325endmodule
326
327
328
329module err_c0t1 ();
330`ifndef GATESIM
331
332`include "defines.vh"
333
334wire [2:0] mycid;
335wire [2:0] mytid;
336wire [5:0] mytnum;
337
338integer junk;
339reg ready;
340reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
341reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
342
343reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
344reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
345
346reg update_dfesr_w;
347
348reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
349reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
350
351reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
352reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
353
354reg sync_asi;
355reg chk_if_asi_ld;
356reg [63:0] ld_data_w;
357
358reg desr_asi_rd, desr_wr, desr_pend_wr;
359
360assign mycid = 0;
361assign mytid = 1;
362assign mytnum = 0*8 + 1;
363
364initial begin //{
365 desr_asi_rd = 1'b0;
366 desr_pend_wr = 1'b0;
367 ready = 0;
368 @(posedge `SPC0.l2clk) ;
369 @(posedge `SPC0.l2clk) ;
370 ready = `PARGS.err_sync_on;
371end //}
372
373`define DSFSR_NEW_IN_1 `SPC0.tlu.ras.dsfsr_1_new_in
374`define ISFSR_NEW_IN_1 `SPC0.tlu.ras.isfsr_1_new_in
375
376`define DSFSR_1 `SPC0.tlu.ras.dsfsr_1
377`define ISFSR_1 `SPC0.tlu.ras.isfsr_1
378`define DSFAR_1 `SPC0.tlu.dfd.dsfar_1
379
380`define ASI_WR_DSFSR_1 `SPC0.tlu.ras.asi_wr_dsfsr[1]
381`define ASI_WR_ISFSR_1 `SPC0.tlu.ras.asi_wr_isfsr[1]
382
383`define RAS_WRITE_DESR_1st_1 `SPC0.tlu.dfd.ras_write_desr_1st[1]
384`define RAS_WRITE_DESR_2nd_1 `SPC0.tlu.dfd.ras_write_desr_2nd[1]
385`define DESR_asi_rd_1 `SPC0.tlu.ras_rd_desr[1]
386`define DESR_1 `SPC0.tlu.dfd.desr_1
387
388`define RAS_WRITE_FESR_1 `SPC0.tlu.ras.write_fesr[1]
389`define FESR_1 `SPC0.tlu.dfd.fesr_1
390
391`define ST_ERR_1 `SPC0.tlu.trl0.take_ftt & `SPC0.tlu.trl0.trap[1]
392`define SW_REC_ERR_1 `SPC0.tlu.trl0.take_ade & `SPC0.tlu.trl0.trap[1]
393`define DATA_ACC_ERR_1 `SPC0.tlu.trl0.take_dae & `SPC0.tlu.trl0.trap[1]
394`define INST_ACC_ERR_1 `SPC0.tlu.trl0.take_iae & `SPC0.tlu.trl0.trap[1]
395`define INT_PROC_ERR_1 `SPC0.tlu.trl0.take_ipe & `SPC0.tlu.trl0.trap[1]
396`define HW_CORR_ERR_1 `SPC0.tlu.trl0.take_eer & `SPC0.tlu.trl0.trap[1]
397`define INST_ACC_MMU_ERR_1 `SPC0.tlu.trl0.take_ime & `SPC0.tlu.trl0.trap[1]
398`define DATA_ACC_MMU_ERR_1 `SPC0.tlu.trl0.take_dme & `SPC0.tlu.trl0.trap[1]
399
400`define LSU_LD_VALID_B `PROBES0.lsu_ld_valid
401`define LSU_TID_DEC_B_1 `PROBES0.lsu_tid_dec_b[1]
402`define ASI_LD_1 `SPC0.lsu.lmd.lmq1_pkt[60] & (`SPC0.lsu.lmd.lmq1_pkt[49:48] == 2'b0)
403`define ASI_1 `SPC0.lsu.lmd.lmq1_pkt[47:40]
404`define ASI_ADDR_1 `SPC0.lsu.lmd.lmq1_pkt[39:0]
405`define ASI_LD_DATA_1 `SPC0.lsu_exu_ld_data_b[63:0]
406`define ASI_LD_COMP_1 tb_top.nas_top.c0.t1.complete_fw2
407
408//SPU specific - only one SPU per core
409`define SPU_MA_BUSY_0 `SPC0.spu.spu_pmu_ma_busy[3]
410`define SPU_MA_TID_0 `SPC0.spu.spu_pmu_ma_busy[2:0]
411
412////////////////////////////////////////////////////////////////////////////////
413//Capture the status register data from rtl. For disrupting traps,
414//rtl can modify the contents of the status register before the
415//trap is taken and intp message is sent to Riesling.
416//For precise traps, once the status register is updated rtl can't
417//change the register again before jumping to the trap handler.
418//So, for deferred and disrupting traps, inform Riesling when the
419//register is modified while for precise traps wait until Fw2 before
420//telling Riesling.
421
422//TLU asserts the flush and input signals in W stage. I latch them at the
423//+ve edge of FX4.
424
425always @(negedge (`SPC0.l2clk & ready))
426begin // {
427 if (`DESR_asi_rd_1)
428 desr_asi_rd <= 1'b1;
429 if (desr_asi_rd)
430 begin
431 if (desr_wr)
432 desr_pend_wr <= 1'b1;
433 if (`ASI_LD_COMP_1[2])
434 desr_asi_rd <= 1'b0;
435 end
436
437 update_dsfsr_w <= (`DSFSR_NEW_IN_1 != 4'b0) && ~`ASI_WR_DSFSR_1;
438 update_isfsr_w <= (`ISFSR_NEW_IN_1 != 3'b0) && ~`ASI_WR_ISFSR_1;
439 desr_wr <= (`RAS_WRITE_DESR_1st_1 || `RAS_WRITE_DESR_2nd_1);
440 update_dfesr_w <= `RAS_WRITE_FESR_1;
441 take_err_trap_fx4 <= `ST_ERR_1 | `SW_REC_ERR_1 | `DATA_ACC_ERR_1
442 | `INST_ACC_ERR_1 | `INT_PROC_ERR_1
443 | `HW_CORR_ERR_1 | `INST_ACC_MMU_ERR_1
444 | `DATA_ACC_MMU_ERR_1 ;
445
446
447 if (`ST_ERR_1) int_num_fx4 <= 8'h07;
448 if (`SW_REC_ERR_1) int_num_fx4 <= 8'h40;
449 if (`DATA_ACC_ERR_1) int_num_fx4 <= 8'h32;
450 if (`INST_ACC_ERR_1) int_num_fx4 <= 8'h0A;
451 if (`INT_PROC_ERR_1) int_num_fx4 <= 8'h29;
452 if (`HW_CORR_ERR_1) int_num_fx4 <= 8'h63;
453 if (`INST_ACC_MMU_ERR_1) int_num_fx4 <= 8'h71;
454 if (`DATA_ACC_MMU_ERR_1) int_num_fx4 <= 8'h72;
455
456 update_dsfsr_fx4 <= update_dsfsr_w;
457 update_dsfsr_fx5 <= update_dsfsr_fx4;
458 update_dsfsr_fb <= update_dsfsr_fx5;
459 update_dsfsr_fw <= update_dsfsr_fb;
460 update_dsfsr_fw1 <= update_dsfsr_fw;
461 update_dsfsr_fw2 <= update_dsfsr_fw1;
462
463 update_isfsr_fx4 <= update_isfsr_w;
464 update_isfsr_fx5 <= update_isfsr_fx4;
465 update_isfsr_fb <= update_isfsr_fx5;
466 update_isfsr_fw <= update_isfsr_fb;
467 update_isfsr_fw1 <= update_isfsr_fw;
468 update_isfsr_fw2 <= update_isfsr_fw1;
469
470 take_err_trap_fx5 <= take_err_trap_fx4;
471 take_err_trap_fb <= take_err_trap_fx5;
472 take_err_trap_fw <= take_err_trap_fb;
473 take_err_trap_fw1 <= take_err_trap_fw;
474 take_err_trap_fw2 <= take_err_trap_fw1;
475
476 int_num_fx5 <= int_num_fx4;
477 int_num_fb <= int_num_fx5;
478 int_num_fw <= int_num_fb;
479 int_num_fw1 <= int_num_fw;
480 int_num_fw2 <= int_num_fw1;
481
482 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
483 begin // {
484 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
485 begin //{
486 desr_pend_wr <= 1'b0;
487 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_1[63:56], 45'b0, `DESR_1[10:0]});
488 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_1[63:56], 45'b0, `DESR_1[10:0]});
489 end //}
490 //if (update_dfesr_w)
491 if (`ST_ERR_1)
492 begin //{
493 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_1[61:55], 55'b0});
494 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_1[61:55], 55'b0});
495 end //}
496 if (update_dsfsr_fw2)
497 begin //{
498 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
499 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_1[3:0]});
500 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_1[47:0]});
501
502 end //}
503 if (update_isfsr_fw2)
504 begin //{
505 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
506 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_1[2:0]});
507 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_1[47:0]});
508
509 end //}
510 if (take_err_trap_fw2)
511 begin //{
512 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
513 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
514 end // }
515 end // }
516
517end //}
518
519//removing the addr check as the LSU doesn't flag an invalid_asi_exception
520//if the addr of diagnostic accesses is not in the valid range. The inst.
521//still executes. LSU expects that HP won't use addresses in invalid range.
522
523always @(negedge (`SPC0.l2clk & ready))
524begin // {
525 sync_asi = 1'b0;
526 ld_data_w <= `ASI_LD_DATA_1;
527
528 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_1)
529 chk_if_asi_ld <= 1'b1;
530 else
531 chk_if_asi_ld <= 1'b0;
532
533 if (chk_if_asi_ld & `ASI_LD_1)
534 begin
535 case (`ASI_1)
536 8'h66: //ASI_IC_INSTR
537 begin
538 //if ((`ASI_ADDR_1 >= 0) & (`ASI_ADDR_1 <= 40'h7ff8))
539 sync_asi = 1'b1;
540 end
541 8'h67: //ASI_IC_TAG
542 begin
543 //if ((`ASI_ADDR_1 >= 0) & (`ASI_ADDR_1 <= 40'h7fe0))
544 sync_asi = 1'b1;
545 end
546 8'h46: //ASI_DC_DATA
547 begin
548 sync_asi = 1'b1;
549 end
550 8'h47: //ASI_DC_TAG
551 begin
552 //if ((`ASI_ADDR_1 >= 0) & (`ASI_ADDR_1 <= 40'h7ff0))
553 sync_asi = 1'b1;
554 end
555 8'h48://IRF ECC
556 begin
557 //if ((`ASI_ADDR_1 >= 0) & (`ASI_ADDR_1 <= 40'hF8))
558 sync_asi = 1'b1;
559 end
560 8'h49://FRF ECC
561 begin
562 //if ((`ASI_ADDR_1 >= 0) & (`ASI_ADDR_1 <= 40'hF8))
563 sync_asi = 1'b1;
564 end
565 8'h4A://STB access, stb ptr can be read also
566 begin
567 //if ((`ASI_ADDR_1 >= 0) & (`ASI_ADDR_1 <= 40'h100))
568 sync_asi = 1'b1;
569 end
570 8'h5A://Tick compare reg
571 begin
572 //if ((`ASI_ADDR_1 >= 0) & (`ASI_ADDR_1 <= 40'h38))
573 sync_asi = 1'b1;
574 end
575 8'h5B://TSA
576 begin
577 //if ((`ASI_ADDR_1 >= 0) & (`ASI_ADDR_1 <= 40'h38))
578 sync_asi = 1'b1;
579 end
580 8'h51://MRA
581 begin
582 //if ((`ASI_ADDR_1 >= 0) & (`ASI_ADDR_1 <= 40'h38))
583 sync_asi = 1'b1;
584 end
585 8'h59://scratchpad ecc data read
586 begin
587 //if ((`ASI_ADDR_1 >= 0) & (`ASI_ADDR_1 <= 40'h38))
588 //syncup the ecc data only. For ecc bit 6 is 0.
589 if (~`SPC0.lsu.lmd.lmq1_pkt[6])
590 sync_asi = 1'b1;
591 end
592 8'h40://cwqcsr,ma_sync access
593 begin
594 if ((`ASI_ADDR_1 == 40'h20) || (`ASI_ADDR_1 == 40'h30)
595 || (`ASI_ADDR_1 == 40'h80)
596 || ((`ASI_ADDR_1 == 40'ha0) & (`SPU_MA_BUSY_0 == 0) & (`SPU_MA_TID_0 == 1))
597 )
598 sync_asi = 1'b1;
599 end
600 8'h4C://CLESR, CLFESR access
601 begin
602 if ((`ASI_ADDR_1 == 40'h20) || (`ASI_ADDR_1 == 40'h28))
603 sync_asi = 1'b1;
604 end
605 endcase
606 end
607
608 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
609 begin
610 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_1, `ASI_ADDR_1, ld_data_w);
611 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_1, {24'b0, `ASI_ADDR_1}, ld_data_w[63:0]);
612 end
613end //}
614`endif
615endmodule
616
617
618
619module err_c0t2 ();
620`ifndef GATESIM
621
622`include "defines.vh"
623
624wire [2:0] mycid;
625wire [2:0] mytid;
626wire [5:0] mytnum;
627
628integer junk;
629reg ready;
630reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
631reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
632
633reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
634reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
635
636reg update_dfesr_w;
637
638reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
639reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
640
641reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
642reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
643
644reg sync_asi;
645reg chk_if_asi_ld;
646reg [63:0] ld_data_w;
647
648reg desr_asi_rd, desr_wr, desr_pend_wr;
649
650assign mycid = 0;
651assign mytid = 2;
652assign mytnum = 0*8 + 2;
653
654initial begin //{
655 desr_asi_rd = 1'b0;
656 desr_pend_wr = 1'b0;
657 ready = 0;
658 @(posedge `SPC0.l2clk) ;
659 @(posedge `SPC0.l2clk) ;
660 ready = `PARGS.err_sync_on;
661end //}
662
663`define DSFSR_NEW_IN_2 `SPC0.tlu.ras.dsfsr_2_new_in
664`define ISFSR_NEW_IN_2 `SPC0.tlu.ras.isfsr_2_new_in
665
666`define DSFSR_2 `SPC0.tlu.ras.dsfsr_2
667`define ISFSR_2 `SPC0.tlu.ras.isfsr_2
668`define DSFAR_2 `SPC0.tlu.dfd.dsfar_2
669
670`define ASI_WR_DSFSR_2 `SPC0.tlu.ras.asi_wr_dsfsr[2]
671`define ASI_WR_ISFSR_2 `SPC0.tlu.ras.asi_wr_isfsr[2]
672
673`define RAS_WRITE_DESR_1st_2 `SPC0.tlu.dfd.ras_write_desr_1st[2]
674`define RAS_WRITE_DESR_2nd_2 `SPC0.tlu.dfd.ras_write_desr_2nd[2]
675`define DESR_asi_rd_2 `SPC0.tlu.ras_rd_desr[2]
676`define DESR_2 `SPC0.tlu.dfd.desr_2
677
678`define RAS_WRITE_FESR_2 `SPC0.tlu.ras.write_fesr[2]
679`define FESR_2 `SPC0.tlu.dfd.fesr_2
680
681`define ST_ERR_2 `SPC0.tlu.trl0.take_ftt & `SPC0.tlu.trl0.trap[2]
682`define SW_REC_ERR_2 `SPC0.tlu.trl0.take_ade & `SPC0.tlu.trl0.trap[2]
683`define DATA_ACC_ERR_2 `SPC0.tlu.trl0.take_dae & `SPC0.tlu.trl0.trap[2]
684`define INST_ACC_ERR_2 `SPC0.tlu.trl0.take_iae & `SPC0.tlu.trl0.trap[2]
685`define INT_PROC_ERR_2 `SPC0.tlu.trl0.take_ipe & `SPC0.tlu.trl0.trap[2]
686`define HW_CORR_ERR_2 `SPC0.tlu.trl0.take_eer & `SPC0.tlu.trl0.trap[2]
687`define INST_ACC_MMU_ERR_2 `SPC0.tlu.trl0.take_ime & `SPC0.tlu.trl0.trap[2]
688`define DATA_ACC_MMU_ERR_2 `SPC0.tlu.trl0.take_dme & `SPC0.tlu.trl0.trap[2]
689
690`define LSU_LD_VALID_B `PROBES0.lsu_ld_valid
691`define LSU_TID_DEC_B_2 `PROBES0.lsu_tid_dec_b[2]
692`define ASI_LD_2 `SPC0.lsu.lmd.lmq2_pkt[60] & (`SPC0.lsu.lmd.lmq2_pkt[49:48] == 2'b0)
693`define ASI_2 `SPC0.lsu.lmd.lmq2_pkt[47:40]
694`define ASI_ADDR_2 `SPC0.lsu.lmd.lmq2_pkt[39:0]
695`define ASI_LD_DATA_2 `SPC0.lsu_exu_ld_data_b[63:0]
696`define ASI_LD_COMP_2 tb_top.nas_top.c0.t2.complete_fw2
697
698//SPU specific - only one SPU per core
699`define SPU_MA_BUSY_0 `SPC0.spu.spu_pmu_ma_busy[3]
700`define SPU_MA_TID_0 `SPC0.spu.spu_pmu_ma_busy[2:0]
701
702////////////////////////////////////////////////////////////////////////////////
703//Capture the status register data from rtl. For disrupting traps,
704//rtl can modify the contents of the status register before the
705//trap is taken and intp message is sent to Riesling.
706//For precise traps, once the status register is updated rtl can't
707//change the register again before jumping to the trap handler.
708//So, for deferred and disrupting traps, inform Riesling when the
709//register is modified while for precise traps wait until Fw2 before
710//telling Riesling.
711
712//TLU asserts the flush and input signals in W stage. I latch them at the
713//+ve edge of FX4.
714
715always @(negedge (`SPC0.l2clk & ready))
716begin // {
717 if (`DESR_asi_rd_2)
718 desr_asi_rd <= 1'b1;
719 if (desr_asi_rd)
720 begin
721 if (desr_wr)
722 desr_pend_wr <= 1'b1;
723 if (`ASI_LD_COMP_2[2])
724 desr_asi_rd <= 1'b0;
725 end
726
727 update_dsfsr_w <= (`DSFSR_NEW_IN_2 != 4'b0) && ~`ASI_WR_DSFSR_2;
728 update_isfsr_w <= (`ISFSR_NEW_IN_2 != 3'b0) && ~`ASI_WR_ISFSR_2;
729 desr_wr <= (`RAS_WRITE_DESR_1st_2 || `RAS_WRITE_DESR_2nd_2);
730 update_dfesr_w <= `RAS_WRITE_FESR_2;
731 take_err_trap_fx4 <= `ST_ERR_2 | `SW_REC_ERR_2 | `DATA_ACC_ERR_2
732 | `INST_ACC_ERR_2 | `INT_PROC_ERR_2
733 | `HW_CORR_ERR_2 | `INST_ACC_MMU_ERR_2
734 | `DATA_ACC_MMU_ERR_2 ;
735
736
737 if (`ST_ERR_2) int_num_fx4 <= 8'h07;
738 if (`SW_REC_ERR_2) int_num_fx4 <= 8'h40;
739 if (`DATA_ACC_ERR_2) int_num_fx4 <= 8'h32;
740 if (`INST_ACC_ERR_2) int_num_fx4 <= 8'h0A;
741 if (`INT_PROC_ERR_2) int_num_fx4 <= 8'h29;
742 if (`HW_CORR_ERR_2) int_num_fx4 <= 8'h63;
743 if (`INST_ACC_MMU_ERR_2) int_num_fx4 <= 8'h71;
744 if (`DATA_ACC_MMU_ERR_2) int_num_fx4 <= 8'h72;
745
746 update_dsfsr_fx4 <= update_dsfsr_w;
747 update_dsfsr_fx5 <= update_dsfsr_fx4;
748 update_dsfsr_fb <= update_dsfsr_fx5;
749 update_dsfsr_fw <= update_dsfsr_fb;
750 update_dsfsr_fw1 <= update_dsfsr_fw;
751 update_dsfsr_fw2 <= update_dsfsr_fw1;
752
753 update_isfsr_fx4 <= update_isfsr_w;
754 update_isfsr_fx5 <= update_isfsr_fx4;
755 update_isfsr_fb <= update_isfsr_fx5;
756 update_isfsr_fw <= update_isfsr_fb;
757 update_isfsr_fw1 <= update_isfsr_fw;
758 update_isfsr_fw2 <= update_isfsr_fw1;
759
760 take_err_trap_fx5 <= take_err_trap_fx4;
761 take_err_trap_fb <= take_err_trap_fx5;
762 take_err_trap_fw <= take_err_trap_fb;
763 take_err_trap_fw1 <= take_err_trap_fw;
764 take_err_trap_fw2 <= take_err_trap_fw1;
765
766 int_num_fx5 <= int_num_fx4;
767 int_num_fb <= int_num_fx5;
768 int_num_fw <= int_num_fb;
769 int_num_fw1 <= int_num_fw;
770 int_num_fw2 <= int_num_fw1;
771
772 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
773 begin // {
774 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
775 begin //{
776 desr_pend_wr <= 1'b0;
777 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_2[63:56], 45'b0, `DESR_2[10:0]});
778 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_2[63:56], 45'b0, `DESR_2[10:0]});
779 end //}
780 //if (update_dfesr_w)
781 if (`ST_ERR_2)
782 begin //{
783 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_2[61:55], 55'b0});
784 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_2[61:55], 55'b0});
785 end //}
786 if (update_dsfsr_fw2)
787 begin //{
788 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
789 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_2[3:0]});
790 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_2[47:0]});
791
792 end //}
793 if (update_isfsr_fw2)
794 begin //{
795 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
796 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_2[2:0]});
797 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_2[47:0]});
798
799 end //}
800 if (take_err_trap_fw2)
801 begin //{
802 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
803 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
804 end // }
805 end // }
806
807end //}
808
809//removing the addr check as the LSU doesn't flag an invalid_asi_exception
810//if the addr of diagnostic accesses is not in the valid range. The inst.
811//still executes. LSU expects that HP won't use addresses in invalid range.
812
813always @(negedge (`SPC0.l2clk & ready))
814begin // {
815 sync_asi = 1'b0;
816 ld_data_w <= `ASI_LD_DATA_2;
817
818 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_2)
819 chk_if_asi_ld <= 1'b1;
820 else
821 chk_if_asi_ld <= 1'b0;
822
823 if (chk_if_asi_ld & `ASI_LD_2)
824 begin
825 case (`ASI_2)
826 8'h66: //ASI_IC_INSTR
827 begin
828 //if ((`ASI_ADDR_2 >= 0) & (`ASI_ADDR_2 <= 40'h7ff8))
829 sync_asi = 1'b1;
830 end
831 8'h67: //ASI_IC_TAG
832 begin
833 //if ((`ASI_ADDR_2 >= 0) & (`ASI_ADDR_2 <= 40'h7fe0))
834 sync_asi = 1'b1;
835 end
836 8'h46: //ASI_DC_DATA
837 begin
838 sync_asi = 1'b1;
839 end
840 8'h47: //ASI_DC_TAG
841 begin
842 //if ((`ASI_ADDR_2 >= 0) & (`ASI_ADDR_2 <= 40'h7ff0))
843 sync_asi = 1'b1;
844 end
845 8'h48://IRF ECC
846 begin
847 //if ((`ASI_ADDR_2 >= 0) & (`ASI_ADDR_2 <= 40'hF8))
848 sync_asi = 1'b1;
849 end
850 8'h49://FRF ECC
851 begin
852 //if ((`ASI_ADDR_2 >= 0) & (`ASI_ADDR_2 <= 40'hF8))
853 sync_asi = 1'b1;
854 end
855 8'h4A://STB access, stb ptr can be read also
856 begin
857 //if ((`ASI_ADDR_2 >= 0) & (`ASI_ADDR_2 <= 40'h100))
858 sync_asi = 1'b1;
859 end
860 8'h5A://Tick compare reg
861 begin
862 //if ((`ASI_ADDR_2 >= 0) & (`ASI_ADDR_2 <= 40'h38))
863 sync_asi = 1'b1;
864 end
865 8'h5B://TSA
866 begin
867 //if ((`ASI_ADDR_2 >= 0) & (`ASI_ADDR_2 <= 40'h38))
868 sync_asi = 1'b1;
869 end
870 8'h51://MRA
871 begin
872 //if ((`ASI_ADDR_2 >= 0) & (`ASI_ADDR_2 <= 40'h38))
873 sync_asi = 1'b1;
874 end
875 8'h59://scratchpad ecc data read
876 begin
877 //if ((`ASI_ADDR_2 >= 0) & (`ASI_ADDR_2 <= 40'h38))
878 //syncup the ecc data only. For ecc bit 6 is 0.
879 if (~`SPC0.lsu.lmd.lmq2_pkt[6])
880 sync_asi = 1'b1;
881 end
882 8'h40://cwqcsr,ma_sync access
883 begin
884 if ((`ASI_ADDR_2 == 40'h20) || (`ASI_ADDR_2 == 40'h30)
885 || (`ASI_ADDR_2 == 40'h80)
886 || ((`ASI_ADDR_2 == 40'ha0) & (`SPU_MA_BUSY_0 == 0) & (`SPU_MA_TID_0 == 2))
887 )
888 sync_asi = 1'b1;
889 end
890 8'h4C://CLESR, CLFESR access
891 begin
892 if ((`ASI_ADDR_2 == 40'h20) || (`ASI_ADDR_2 == 40'h28))
893 sync_asi = 1'b1;
894 end
895 endcase
896 end
897
898 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
899 begin
900 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_2, `ASI_ADDR_2, ld_data_w);
901 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_2, {24'b0, `ASI_ADDR_2}, ld_data_w[63:0]);
902 end
903end //}
904`endif
905endmodule
906
907
908
909module err_c0t3 ();
910`ifndef GATESIM
911
912`include "defines.vh"
913
914wire [2:0] mycid;
915wire [2:0] mytid;
916wire [5:0] mytnum;
917
918integer junk;
919reg ready;
920reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
921reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
922
923reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
924reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
925
926reg update_dfesr_w;
927
928reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
929reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
930
931reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
932reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
933
934reg sync_asi;
935reg chk_if_asi_ld;
936reg [63:0] ld_data_w;
937
938reg desr_asi_rd, desr_wr, desr_pend_wr;
939
940assign mycid = 0;
941assign mytid = 3;
942assign mytnum = 0*8 + 3;
943
944initial begin //{
945 desr_asi_rd = 1'b0;
946 desr_pend_wr = 1'b0;
947 ready = 0;
948 @(posedge `SPC0.l2clk) ;
949 @(posedge `SPC0.l2clk) ;
950 ready = `PARGS.err_sync_on;
951end //}
952
953`define DSFSR_NEW_IN_3 `SPC0.tlu.ras.dsfsr_3_new_in
954`define ISFSR_NEW_IN_3 `SPC0.tlu.ras.isfsr_3_new_in
955
956`define DSFSR_3 `SPC0.tlu.ras.dsfsr_3
957`define ISFSR_3 `SPC0.tlu.ras.isfsr_3
958`define DSFAR_3 `SPC0.tlu.dfd.dsfar_3
959
960`define ASI_WR_DSFSR_3 `SPC0.tlu.ras.asi_wr_dsfsr[3]
961`define ASI_WR_ISFSR_3 `SPC0.tlu.ras.asi_wr_isfsr[3]
962
963`define RAS_WRITE_DESR_1st_3 `SPC0.tlu.dfd.ras_write_desr_1st[3]
964`define RAS_WRITE_DESR_2nd_3 `SPC0.tlu.dfd.ras_write_desr_2nd[3]
965`define DESR_asi_rd_3 `SPC0.tlu.ras_rd_desr[3]
966`define DESR_3 `SPC0.tlu.dfd.desr_3
967
968`define RAS_WRITE_FESR_3 `SPC0.tlu.ras.write_fesr[3]
969`define FESR_3 `SPC0.tlu.dfd.fesr_3
970
971`define ST_ERR_3 `SPC0.tlu.trl0.take_ftt & `SPC0.tlu.trl0.trap[3]
972`define SW_REC_ERR_3 `SPC0.tlu.trl0.take_ade & `SPC0.tlu.trl0.trap[3]
973`define DATA_ACC_ERR_3 `SPC0.tlu.trl0.take_dae & `SPC0.tlu.trl0.trap[3]
974`define INST_ACC_ERR_3 `SPC0.tlu.trl0.take_iae & `SPC0.tlu.trl0.trap[3]
975`define INT_PROC_ERR_3 `SPC0.tlu.trl0.take_ipe & `SPC0.tlu.trl0.trap[3]
976`define HW_CORR_ERR_3 `SPC0.tlu.trl0.take_eer & `SPC0.tlu.trl0.trap[3]
977`define INST_ACC_MMU_ERR_3 `SPC0.tlu.trl0.take_ime & `SPC0.tlu.trl0.trap[3]
978`define DATA_ACC_MMU_ERR_3 `SPC0.tlu.trl0.take_dme & `SPC0.tlu.trl0.trap[3]
979
980`define LSU_LD_VALID_B `PROBES0.lsu_ld_valid
981`define LSU_TID_DEC_B_3 `PROBES0.lsu_tid_dec_b[3]
982`define ASI_LD_3 `SPC0.lsu.lmd.lmq3_pkt[60] & (`SPC0.lsu.lmd.lmq3_pkt[49:48] == 2'b0)
983`define ASI_3 `SPC0.lsu.lmd.lmq3_pkt[47:40]
984`define ASI_ADDR_3 `SPC0.lsu.lmd.lmq3_pkt[39:0]
985`define ASI_LD_DATA_3 `SPC0.lsu_exu_ld_data_b[63:0]
986`define ASI_LD_COMP_3 tb_top.nas_top.c0.t3.complete_fw2
987
988//SPU specific - only one SPU per core
989`define SPU_MA_BUSY_0 `SPC0.spu.spu_pmu_ma_busy[3]
990`define SPU_MA_TID_0 `SPC0.spu.spu_pmu_ma_busy[2:0]
991
992////////////////////////////////////////////////////////////////////////////////
993//Capture the status register data from rtl. For disrupting traps,
994//rtl can modify the contents of the status register before the
995//trap is taken and intp message is sent to Riesling.
996//For precise traps, once the status register is updated rtl can't
997//change the register again before jumping to the trap handler.
998//So, for deferred and disrupting traps, inform Riesling when the
999//register is modified while for precise traps wait until Fw2 before
1000//telling Riesling.
1001
1002//TLU asserts the flush and input signals in W stage. I latch them at the
1003//+ve edge of FX4.
1004
1005always @(negedge (`SPC0.l2clk & ready))
1006begin // {
1007 if (`DESR_asi_rd_3)
1008 desr_asi_rd <= 1'b1;
1009 if (desr_asi_rd)
1010 begin
1011 if (desr_wr)
1012 desr_pend_wr <= 1'b1;
1013 if (`ASI_LD_COMP_3[2])
1014 desr_asi_rd <= 1'b0;
1015 end
1016
1017 update_dsfsr_w <= (`DSFSR_NEW_IN_3 != 4'b0) && ~`ASI_WR_DSFSR_3;
1018 update_isfsr_w <= (`ISFSR_NEW_IN_3 != 3'b0) && ~`ASI_WR_ISFSR_3;
1019 desr_wr <= (`RAS_WRITE_DESR_1st_3 || `RAS_WRITE_DESR_2nd_3);
1020 update_dfesr_w <= `RAS_WRITE_FESR_3;
1021 take_err_trap_fx4 <= `ST_ERR_3 | `SW_REC_ERR_3 | `DATA_ACC_ERR_3
1022 | `INST_ACC_ERR_3 | `INT_PROC_ERR_3
1023 | `HW_CORR_ERR_3 | `INST_ACC_MMU_ERR_3
1024 | `DATA_ACC_MMU_ERR_3 ;
1025
1026
1027 if (`ST_ERR_3) int_num_fx4 <= 8'h07;
1028 if (`SW_REC_ERR_3) int_num_fx4 <= 8'h40;
1029 if (`DATA_ACC_ERR_3) int_num_fx4 <= 8'h32;
1030 if (`INST_ACC_ERR_3) int_num_fx4 <= 8'h0A;
1031 if (`INT_PROC_ERR_3) int_num_fx4 <= 8'h29;
1032 if (`HW_CORR_ERR_3) int_num_fx4 <= 8'h63;
1033 if (`INST_ACC_MMU_ERR_3) int_num_fx4 <= 8'h71;
1034 if (`DATA_ACC_MMU_ERR_3) int_num_fx4 <= 8'h72;
1035
1036 update_dsfsr_fx4 <= update_dsfsr_w;
1037 update_dsfsr_fx5 <= update_dsfsr_fx4;
1038 update_dsfsr_fb <= update_dsfsr_fx5;
1039 update_dsfsr_fw <= update_dsfsr_fb;
1040 update_dsfsr_fw1 <= update_dsfsr_fw;
1041 update_dsfsr_fw2 <= update_dsfsr_fw1;
1042
1043 update_isfsr_fx4 <= update_isfsr_w;
1044 update_isfsr_fx5 <= update_isfsr_fx4;
1045 update_isfsr_fb <= update_isfsr_fx5;
1046 update_isfsr_fw <= update_isfsr_fb;
1047 update_isfsr_fw1 <= update_isfsr_fw;
1048 update_isfsr_fw2 <= update_isfsr_fw1;
1049
1050 take_err_trap_fx5 <= take_err_trap_fx4;
1051 take_err_trap_fb <= take_err_trap_fx5;
1052 take_err_trap_fw <= take_err_trap_fb;
1053 take_err_trap_fw1 <= take_err_trap_fw;
1054 take_err_trap_fw2 <= take_err_trap_fw1;
1055
1056 int_num_fx5 <= int_num_fx4;
1057 int_num_fb <= int_num_fx5;
1058 int_num_fw <= int_num_fb;
1059 int_num_fw1 <= int_num_fw;
1060 int_num_fw2 <= int_num_fw1;
1061
1062 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
1063 begin // {
1064 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
1065 begin //{
1066 desr_pend_wr <= 1'b0;
1067 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_3[63:56], 45'b0, `DESR_3[10:0]});
1068 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_3[63:56], 45'b0, `DESR_3[10:0]});
1069 end //}
1070 //if (update_dfesr_w)
1071 if (`ST_ERR_3)
1072 begin //{
1073 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_3[61:55], 55'b0});
1074 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_3[61:55], 55'b0});
1075 end //}
1076 if (update_dsfsr_fw2)
1077 begin //{
1078 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
1079 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_3[3:0]});
1080 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_3[47:0]});
1081
1082 end //}
1083 if (update_isfsr_fw2)
1084 begin //{
1085 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
1086 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_3[2:0]});
1087 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_3[47:0]});
1088
1089 end //}
1090 if (take_err_trap_fw2)
1091 begin //{
1092 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
1093 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
1094 end // }
1095 end // }
1096
1097end //}
1098
1099//removing the addr check as the LSU doesn't flag an invalid_asi_exception
1100//if the addr of diagnostic accesses is not in the valid range. The inst.
1101//still executes. LSU expects that HP won't use addresses in invalid range.
1102
1103always @(negedge (`SPC0.l2clk & ready))
1104begin // {
1105 sync_asi = 1'b0;
1106 ld_data_w <= `ASI_LD_DATA_3;
1107
1108 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_3)
1109 chk_if_asi_ld <= 1'b1;
1110 else
1111 chk_if_asi_ld <= 1'b0;
1112
1113 if (chk_if_asi_ld & `ASI_LD_3)
1114 begin
1115 case (`ASI_3)
1116 8'h66: //ASI_IC_INSTR
1117 begin
1118 //if ((`ASI_ADDR_3 >= 0) & (`ASI_ADDR_3 <= 40'h7ff8))
1119 sync_asi = 1'b1;
1120 end
1121 8'h67: //ASI_IC_TAG
1122 begin
1123 //if ((`ASI_ADDR_3 >= 0) & (`ASI_ADDR_3 <= 40'h7fe0))
1124 sync_asi = 1'b1;
1125 end
1126 8'h46: //ASI_DC_DATA
1127 begin
1128 sync_asi = 1'b1;
1129 end
1130 8'h47: //ASI_DC_TAG
1131 begin
1132 //if ((`ASI_ADDR_3 >= 0) & (`ASI_ADDR_3 <= 40'h7ff0))
1133 sync_asi = 1'b1;
1134 end
1135 8'h48://IRF ECC
1136 begin
1137 //if ((`ASI_ADDR_3 >= 0) & (`ASI_ADDR_3 <= 40'hF8))
1138 sync_asi = 1'b1;
1139 end
1140 8'h49://FRF ECC
1141 begin
1142 //if ((`ASI_ADDR_3 >= 0) & (`ASI_ADDR_3 <= 40'hF8))
1143 sync_asi = 1'b1;
1144 end
1145 8'h4A://STB access, stb ptr can be read also
1146 begin
1147 //if ((`ASI_ADDR_3 >= 0) & (`ASI_ADDR_3 <= 40'h100))
1148 sync_asi = 1'b1;
1149 end
1150 8'h5A://Tick compare reg
1151 begin
1152 //if ((`ASI_ADDR_3 >= 0) & (`ASI_ADDR_3 <= 40'h38))
1153 sync_asi = 1'b1;
1154 end
1155 8'h5B://TSA
1156 begin
1157 //if ((`ASI_ADDR_3 >= 0) & (`ASI_ADDR_3 <= 40'h38))
1158 sync_asi = 1'b1;
1159 end
1160 8'h51://MRA
1161 begin
1162 //if ((`ASI_ADDR_3 >= 0) & (`ASI_ADDR_3 <= 40'h38))
1163 sync_asi = 1'b1;
1164 end
1165 8'h59://scratchpad ecc data read
1166 begin
1167 //if ((`ASI_ADDR_3 >= 0) & (`ASI_ADDR_3 <= 40'h38))
1168 //syncup the ecc data only. For ecc bit 6 is 0.
1169 if (~`SPC0.lsu.lmd.lmq3_pkt[6])
1170 sync_asi = 1'b1;
1171 end
1172 8'h40://cwqcsr,ma_sync access
1173 begin
1174 if ((`ASI_ADDR_3 == 40'h20) || (`ASI_ADDR_3 == 40'h30)
1175 || (`ASI_ADDR_3 == 40'h80)
1176 || ((`ASI_ADDR_3 == 40'ha0) & (`SPU_MA_BUSY_0 == 0) & (`SPU_MA_TID_0 == 3))
1177 )
1178 sync_asi = 1'b1;
1179 end
1180 8'h4C://CLESR, CLFESR access
1181 begin
1182 if ((`ASI_ADDR_3 == 40'h20) || (`ASI_ADDR_3 == 40'h28))
1183 sync_asi = 1'b1;
1184 end
1185 endcase
1186 end
1187
1188 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
1189 begin
1190 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_3, `ASI_ADDR_3, ld_data_w);
1191 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_3, {24'b0, `ASI_ADDR_3}, ld_data_w[63:0]);
1192 end
1193end //}
1194`endif
1195endmodule
1196
1197
1198
1199module err_c0t4 ();
1200`ifndef GATESIM
1201
1202`include "defines.vh"
1203
1204wire [2:0] mycid;
1205wire [2:0] mytid;
1206wire [5:0] mytnum;
1207
1208integer junk;
1209reg ready;
1210reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
1211reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
1212
1213reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
1214reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
1215
1216reg update_dfesr_w;
1217
1218reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
1219reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
1220
1221reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
1222reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
1223
1224reg sync_asi;
1225reg chk_if_asi_ld;
1226reg [63:0] ld_data_w;
1227
1228reg desr_asi_rd, desr_wr, desr_pend_wr;
1229
1230assign mycid = 0;
1231assign mytid = 4;
1232assign mytnum = 0*8 + 4;
1233
1234initial begin //{
1235 desr_asi_rd = 1'b0;
1236 desr_pend_wr = 1'b0;
1237 ready = 0;
1238 @(posedge `SPC0.l2clk) ;
1239 @(posedge `SPC0.l2clk) ;
1240 ready = `PARGS.err_sync_on;
1241end //}
1242
1243`define DSFSR_NEW_IN_4 `SPC0.tlu.ras.dsfsr_4_new_in
1244`define ISFSR_NEW_IN_4 `SPC0.tlu.ras.isfsr_4_new_in
1245
1246`define DSFSR_4 `SPC0.tlu.ras.dsfsr_4
1247`define ISFSR_4 `SPC0.tlu.ras.isfsr_4
1248`define DSFAR_4 `SPC0.tlu.dfd.dsfar_4
1249
1250`define ASI_WR_DSFSR_4 `SPC0.tlu.ras.asi_wr_dsfsr[4]
1251`define ASI_WR_ISFSR_4 `SPC0.tlu.ras.asi_wr_isfsr[4]
1252
1253`define RAS_WRITE_DESR_1st_4 `SPC0.tlu.dfd.ras_write_desr_1st[4]
1254`define RAS_WRITE_DESR_2nd_4 `SPC0.tlu.dfd.ras_write_desr_2nd[4]
1255`define DESR_asi_rd_4 `SPC0.tlu.ras_rd_desr[4]
1256`define DESR_4 `SPC0.tlu.dfd.desr_4
1257
1258`define RAS_WRITE_FESR_4 `SPC0.tlu.ras.write_fesr[4]
1259`define FESR_4 `SPC0.tlu.dfd.fesr_4
1260
1261`define ST_ERR_4 `SPC0.tlu.trl1.take_ftt & `SPC0.tlu.trl1.trap[0]
1262`define SW_REC_ERR_4 `SPC0.tlu.trl1.take_ade & `SPC0.tlu.trl1.trap[0]
1263`define DATA_ACC_ERR_4 `SPC0.tlu.trl1.take_dae & `SPC0.tlu.trl1.trap[0]
1264`define INST_ACC_ERR_4 `SPC0.tlu.trl1.take_iae & `SPC0.tlu.trl1.trap[0]
1265`define INT_PROC_ERR_4 `SPC0.tlu.trl1.take_ipe & `SPC0.tlu.trl1.trap[0]
1266`define HW_CORR_ERR_4 `SPC0.tlu.trl1.take_eer & `SPC0.tlu.trl1.trap[0]
1267`define INST_ACC_MMU_ERR_4 `SPC0.tlu.trl1.take_ime & `SPC0.tlu.trl1.trap[0]
1268`define DATA_ACC_MMU_ERR_4 `SPC0.tlu.trl1.take_dme & `SPC0.tlu.trl1.trap[0]
1269
1270`define LSU_LD_VALID_B `PROBES0.lsu_ld_valid
1271`define LSU_TID_DEC_B_4 `PROBES0.lsu_tid_dec_b[4]
1272`define ASI_LD_4 `SPC0.lsu.lmd.lmq4_pkt[60] & (`SPC0.lsu.lmd.lmq4_pkt[49:48] == 2'b0)
1273`define ASI_4 `SPC0.lsu.lmd.lmq4_pkt[47:40]
1274`define ASI_ADDR_4 `SPC0.lsu.lmd.lmq4_pkt[39:0]
1275`define ASI_LD_DATA_4 `SPC0.lsu_exu_ld_data_b[63:0]
1276`define ASI_LD_COMP_4 tb_top.nas_top.c0.t4.complete_fw2
1277
1278//SPU specific - only one SPU per core
1279`define SPU_MA_BUSY_0 `SPC0.spu.spu_pmu_ma_busy[3]
1280`define SPU_MA_TID_0 `SPC0.spu.spu_pmu_ma_busy[2:0]
1281
1282////////////////////////////////////////////////////////////////////////////////
1283//Capture the status register data from rtl. For disrupting traps,
1284//rtl can modify the contents of the status register before the
1285//trap is taken and intp message is sent to Riesling.
1286//For precise traps, once the status register is updated rtl can't
1287//change the register again before jumping to the trap handler.
1288//So, for deferred and disrupting traps, inform Riesling when the
1289//register is modified while for precise traps wait until Fw2 before
1290//telling Riesling.
1291
1292//TLU asserts the flush and input signals in W stage. I latch them at the
1293//+ve edge of FX4.
1294
1295always @(negedge (`SPC0.l2clk & ready))
1296begin // {
1297 if (`DESR_asi_rd_4)
1298 desr_asi_rd <= 1'b1;
1299 if (desr_asi_rd)
1300 begin
1301 if (desr_wr)
1302 desr_pend_wr <= 1'b1;
1303 if (`ASI_LD_COMP_4[2])
1304 desr_asi_rd <= 1'b0;
1305 end
1306
1307 update_dsfsr_w <= (`DSFSR_NEW_IN_4 != 4'b0) && ~`ASI_WR_DSFSR_4;
1308 update_isfsr_w <= (`ISFSR_NEW_IN_4 != 3'b0) && ~`ASI_WR_ISFSR_4;
1309 desr_wr <= (`RAS_WRITE_DESR_1st_4 || `RAS_WRITE_DESR_2nd_4);
1310 update_dfesr_w <= `RAS_WRITE_FESR_4;
1311 take_err_trap_fx4 <= `ST_ERR_4 | `SW_REC_ERR_4 | `DATA_ACC_ERR_4
1312 | `INST_ACC_ERR_4 | `INT_PROC_ERR_4
1313 | `HW_CORR_ERR_4 | `INST_ACC_MMU_ERR_4
1314 | `DATA_ACC_MMU_ERR_4 ;
1315
1316
1317 if (`ST_ERR_4) int_num_fx4 <= 8'h07;
1318 if (`SW_REC_ERR_4) int_num_fx4 <= 8'h40;
1319 if (`DATA_ACC_ERR_4) int_num_fx4 <= 8'h32;
1320 if (`INST_ACC_ERR_4) int_num_fx4 <= 8'h0A;
1321 if (`INT_PROC_ERR_4) int_num_fx4 <= 8'h29;
1322 if (`HW_CORR_ERR_4) int_num_fx4 <= 8'h63;
1323 if (`INST_ACC_MMU_ERR_4) int_num_fx4 <= 8'h71;
1324 if (`DATA_ACC_MMU_ERR_4) int_num_fx4 <= 8'h72;
1325
1326 update_dsfsr_fx4 <= update_dsfsr_w;
1327 update_dsfsr_fx5 <= update_dsfsr_fx4;
1328 update_dsfsr_fb <= update_dsfsr_fx5;
1329 update_dsfsr_fw <= update_dsfsr_fb;
1330 update_dsfsr_fw1 <= update_dsfsr_fw;
1331 update_dsfsr_fw2 <= update_dsfsr_fw1;
1332
1333 update_isfsr_fx4 <= update_isfsr_w;
1334 update_isfsr_fx5 <= update_isfsr_fx4;
1335 update_isfsr_fb <= update_isfsr_fx5;
1336 update_isfsr_fw <= update_isfsr_fb;
1337 update_isfsr_fw1 <= update_isfsr_fw;
1338 update_isfsr_fw2 <= update_isfsr_fw1;
1339
1340 take_err_trap_fx5 <= take_err_trap_fx4;
1341 take_err_trap_fb <= take_err_trap_fx5;
1342 take_err_trap_fw <= take_err_trap_fb;
1343 take_err_trap_fw1 <= take_err_trap_fw;
1344 take_err_trap_fw2 <= take_err_trap_fw1;
1345
1346 int_num_fx5 <= int_num_fx4;
1347 int_num_fb <= int_num_fx5;
1348 int_num_fw <= int_num_fb;
1349 int_num_fw1 <= int_num_fw;
1350 int_num_fw2 <= int_num_fw1;
1351
1352 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
1353 begin // {
1354 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
1355 begin //{
1356 desr_pend_wr <= 1'b0;
1357 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_4[63:56], 45'b0, `DESR_4[10:0]});
1358 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_4[63:56], 45'b0, `DESR_4[10:0]});
1359 end //}
1360 //if (update_dfesr_w)
1361 if (`ST_ERR_4)
1362 begin //{
1363 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_4[61:55], 55'b0});
1364 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_4[61:55], 55'b0});
1365 end //}
1366 if (update_dsfsr_fw2)
1367 begin //{
1368 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
1369 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_4[3:0]});
1370 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_4[47:0]});
1371
1372 end //}
1373 if (update_isfsr_fw2)
1374 begin //{
1375 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
1376 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_4[2:0]});
1377 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_4[47:0]});
1378
1379 end //}
1380 if (take_err_trap_fw2)
1381 begin //{
1382 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
1383 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
1384 end // }
1385 end // }
1386
1387end //}
1388
1389//removing the addr check as the LSU doesn't flag an invalid_asi_exception
1390//if the addr of diagnostic accesses is not in the valid range. The inst.
1391//still executes. LSU expects that HP won't use addresses in invalid range.
1392
1393always @(negedge (`SPC0.l2clk & ready))
1394begin // {
1395 sync_asi = 1'b0;
1396 ld_data_w <= `ASI_LD_DATA_4;
1397
1398 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_4)
1399 chk_if_asi_ld <= 1'b1;
1400 else
1401 chk_if_asi_ld <= 1'b0;
1402
1403 if (chk_if_asi_ld & `ASI_LD_4)
1404 begin
1405 case (`ASI_4)
1406 8'h66: //ASI_IC_INSTR
1407 begin
1408 //if ((`ASI_ADDR_4 >= 0) & (`ASI_ADDR_4 <= 40'h7ff8))
1409 sync_asi = 1'b1;
1410 end
1411 8'h67: //ASI_IC_TAG
1412 begin
1413 //if ((`ASI_ADDR_4 >= 0) & (`ASI_ADDR_4 <= 40'h7fe0))
1414 sync_asi = 1'b1;
1415 end
1416 8'h46: //ASI_DC_DATA
1417 begin
1418 sync_asi = 1'b1;
1419 end
1420 8'h47: //ASI_DC_TAG
1421 begin
1422 //if ((`ASI_ADDR_4 >= 0) & (`ASI_ADDR_4 <= 40'h7ff0))
1423 sync_asi = 1'b1;
1424 end
1425 8'h48://IRF ECC
1426 begin
1427 //if ((`ASI_ADDR_4 >= 0) & (`ASI_ADDR_4 <= 40'hF8))
1428 sync_asi = 1'b1;
1429 end
1430 8'h49://FRF ECC
1431 begin
1432 //if ((`ASI_ADDR_4 >= 0) & (`ASI_ADDR_4 <= 40'hF8))
1433 sync_asi = 1'b1;
1434 end
1435 8'h4A://STB access, stb ptr can be read also
1436 begin
1437 //if ((`ASI_ADDR_4 >= 0) & (`ASI_ADDR_4 <= 40'h100))
1438 sync_asi = 1'b1;
1439 end
1440 8'h5A://Tick compare reg
1441 begin
1442 //if ((`ASI_ADDR_4 >= 0) & (`ASI_ADDR_4 <= 40'h38))
1443 sync_asi = 1'b1;
1444 end
1445 8'h5B://TSA
1446 begin
1447 //if ((`ASI_ADDR_4 >= 0) & (`ASI_ADDR_4 <= 40'h38))
1448 sync_asi = 1'b1;
1449 end
1450 8'h51://MRA
1451 begin
1452 //if ((`ASI_ADDR_4 >= 0) & (`ASI_ADDR_4 <= 40'h38))
1453 sync_asi = 1'b1;
1454 end
1455 8'h59://scratchpad ecc data read
1456 begin
1457 //if ((`ASI_ADDR_4 >= 0) & (`ASI_ADDR_4 <= 40'h38))
1458 //syncup the ecc data only. For ecc bit 6 is 0.
1459 if (~`SPC0.lsu.lmd.lmq4_pkt[6])
1460 sync_asi = 1'b1;
1461 end
1462 8'h40://cwqcsr,ma_sync access
1463 begin
1464 if ((`ASI_ADDR_4 == 40'h20) || (`ASI_ADDR_4 == 40'h30)
1465 || (`ASI_ADDR_4 == 40'h80)
1466 || ((`ASI_ADDR_4 == 40'ha0) & (`SPU_MA_BUSY_0 == 0) & (`SPU_MA_TID_0 == 4))
1467 )
1468 sync_asi = 1'b1;
1469 end
1470 8'h4C://CLESR, CLFESR access
1471 begin
1472 if ((`ASI_ADDR_4 == 40'h20) || (`ASI_ADDR_4 == 40'h28))
1473 sync_asi = 1'b1;
1474 end
1475 endcase
1476 end
1477
1478 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
1479 begin
1480 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_4, `ASI_ADDR_4, ld_data_w);
1481 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_4, {24'b0, `ASI_ADDR_4}, ld_data_w[63:0]);
1482 end
1483end //}
1484`endif
1485endmodule
1486
1487
1488
1489module err_c0t5 ();
1490`ifndef GATESIM
1491
1492`include "defines.vh"
1493
1494wire [2:0] mycid;
1495wire [2:0] mytid;
1496wire [5:0] mytnum;
1497
1498integer junk;
1499reg ready;
1500reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
1501reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
1502
1503reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
1504reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
1505
1506reg update_dfesr_w;
1507
1508reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
1509reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
1510
1511reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
1512reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
1513
1514reg sync_asi;
1515reg chk_if_asi_ld;
1516reg [63:0] ld_data_w;
1517
1518reg desr_asi_rd, desr_wr, desr_pend_wr;
1519
1520assign mycid = 0;
1521assign mytid = 5;
1522assign mytnum = 0*8 + 5;
1523
1524initial begin //{
1525 desr_asi_rd = 1'b0;
1526 desr_pend_wr = 1'b0;
1527 ready = 0;
1528 @(posedge `SPC0.l2clk) ;
1529 @(posedge `SPC0.l2clk) ;
1530 ready = `PARGS.err_sync_on;
1531end //}
1532
1533`define DSFSR_NEW_IN_5 `SPC0.tlu.ras.dsfsr_5_new_in
1534`define ISFSR_NEW_IN_5 `SPC0.tlu.ras.isfsr_5_new_in
1535
1536`define DSFSR_5 `SPC0.tlu.ras.dsfsr_5
1537`define ISFSR_5 `SPC0.tlu.ras.isfsr_5
1538`define DSFAR_5 `SPC0.tlu.dfd.dsfar_5
1539
1540`define ASI_WR_DSFSR_5 `SPC0.tlu.ras.asi_wr_dsfsr[5]
1541`define ASI_WR_ISFSR_5 `SPC0.tlu.ras.asi_wr_isfsr[5]
1542
1543`define RAS_WRITE_DESR_1st_5 `SPC0.tlu.dfd.ras_write_desr_1st[5]
1544`define RAS_WRITE_DESR_2nd_5 `SPC0.tlu.dfd.ras_write_desr_2nd[5]
1545`define DESR_asi_rd_5 `SPC0.tlu.ras_rd_desr[5]
1546`define DESR_5 `SPC0.tlu.dfd.desr_5
1547
1548`define RAS_WRITE_FESR_5 `SPC0.tlu.ras.write_fesr[5]
1549`define FESR_5 `SPC0.tlu.dfd.fesr_5
1550
1551`define ST_ERR_5 `SPC0.tlu.trl1.take_ftt & `SPC0.tlu.trl1.trap[1]
1552`define SW_REC_ERR_5 `SPC0.tlu.trl1.take_ade & `SPC0.tlu.trl1.trap[1]
1553`define DATA_ACC_ERR_5 `SPC0.tlu.trl1.take_dae & `SPC0.tlu.trl1.trap[1]
1554`define INST_ACC_ERR_5 `SPC0.tlu.trl1.take_iae & `SPC0.tlu.trl1.trap[1]
1555`define INT_PROC_ERR_5 `SPC0.tlu.trl1.take_ipe & `SPC0.tlu.trl1.trap[1]
1556`define HW_CORR_ERR_5 `SPC0.tlu.trl1.take_eer & `SPC0.tlu.trl1.trap[1]
1557`define INST_ACC_MMU_ERR_5 `SPC0.tlu.trl1.take_ime & `SPC0.tlu.trl1.trap[1]
1558`define DATA_ACC_MMU_ERR_5 `SPC0.tlu.trl1.take_dme & `SPC0.tlu.trl1.trap[1]
1559
1560`define LSU_LD_VALID_B `PROBES0.lsu_ld_valid
1561`define LSU_TID_DEC_B_5 `PROBES0.lsu_tid_dec_b[5]
1562`define ASI_LD_5 `SPC0.lsu.lmd.lmq5_pkt[60] & (`SPC0.lsu.lmd.lmq5_pkt[49:48] == 2'b0)
1563`define ASI_5 `SPC0.lsu.lmd.lmq5_pkt[47:40]
1564`define ASI_ADDR_5 `SPC0.lsu.lmd.lmq5_pkt[39:0]
1565`define ASI_LD_DATA_5 `SPC0.lsu_exu_ld_data_b[63:0]
1566`define ASI_LD_COMP_5 tb_top.nas_top.c0.t5.complete_fw2
1567
1568//SPU specific - only one SPU per core
1569`define SPU_MA_BUSY_0 `SPC0.spu.spu_pmu_ma_busy[3]
1570`define SPU_MA_TID_0 `SPC0.spu.spu_pmu_ma_busy[2:0]
1571
1572////////////////////////////////////////////////////////////////////////////////
1573//Capture the status register data from rtl. For disrupting traps,
1574//rtl can modify the contents of the status register before the
1575//trap is taken and intp message is sent to Riesling.
1576//For precise traps, once the status register is updated rtl can't
1577//change the register again before jumping to the trap handler.
1578//So, for deferred and disrupting traps, inform Riesling when the
1579//register is modified while for precise traps wait until Fw2 before
1580//telling Riesling.
1581
1582//TLU asserts the flush and input signals in W stage. I latch them at the
1583//+ve edge of FX4.
1584
1585always @(negedge (`SPC0.l2clk & ready))
1586begin // {
1587 if (`DESR_asi_rd_5)
1588 desr_asi_rd <= 1'b1;
1589 if (desr_asi_rd)
1590 begin
1591 if (desr_wr)
1592 desr_pend_wr <= 1'b1;
1593 if (`ASI_LD_COMP_5[2])
1594 desr_asi_rd <= 1'b0;
1595 end
1596
1597 update_dsfsr_w <= (`DSFSR_NEW_IN_5 != 4'b0) && ~`ASI_WR_DSFSR_5;
1598 update_isfsr_w <= (`ISFSR_NEW_IN_5 != 3'b0) && ~`ASI_WR_ISFSR_5;
1599 desr_wr <= (`RAS_WRITE_DESR_1st_5 || `RAS_WRITE_DESR_2nd_5);
1600 update_dfesr_w <= `RAS_WRITE_FESR_5;
1601 take_err_trap_fx4 <= `ST_ERR_5 | `SW_REC_ERR_5 | `DATA_ACC_ERR_5
1602 | `INST_ACC_ERR_5 | `INT_PROC_ERR_5
1603 | `HW_CORR_ERR_5 | `INST_ACC_MMU_ERR_5
1604 | `DATA_ACC_MMU_ERR_5 ;
1605
1606
1607 if (`ST_ERR_5) int_num_fx4 <= 8'h07;
1608 if (`SW_REC_ERR_5) int_num_fx4 <= 8'h40;
1609 if (`DATA_ACC_ERR_5) int_num_fx4 <= 8'h32;
1610 if (`INST_ACC_ERR_5) int_num_fx4 <= 8'h0A;
1611 if (`INT_PROC_ERR_5) int_num_fx4 <= 8'h29;
1612 if (`HW_CORR_ERR_5) int_num_fx4 <= 8'h63;
1613 if (`INST_ACC_MMU_ERR_5) int_num_fx4 <= 8'h71;
1614 if (`DATA_ACC_MMU_ERR_5) int_num_fx4 <= 8'h72;
1615
1616 update_dsfsr_fx4 <= update_dsfsr_w;
1617 update_dsfsr_fx5 <= update_dsfsr_fx4;
1618 update_dsfsr_fb <= update_dsfsr_fx5;
1619 update_dsfsr_fw <= update_dsfsr_fb;
1620 update_dsfsr_fw1 <= update_dsfsr_fw;
1621 update_dsfsr_fw2 <= update_dsfsr_fw1;
1622
1623 update_isfsr_fx4 <= update_isfsr_w;
1624 update_isfsr_fx5 <= update_isfsr_fx4;
1625 update_isfsr_fb <= update_isfsr_fx5;
1626 update_isfsr_fw <= update_isfsr_fb;
1627 update_isfsr_fw1 <= update_isfsr_fw;
1628 update_isfsr_fw2 <= update_isfsr_fw1;
1629
1630 take_err_trap_fx5 <= take_err_trap_fx4;
1631 take_err_trap_fb <= take_err_trap_fx5;
1632 take_err_trap_fw <= take_err_trap_fb;
1633 take_err_trap_fw1 <= take_err_trap_fw;
1634 take_err_trap_fw2 <= take_err_trap_fw1;
1635
1636 int_num_fx5 <= int_num_fx4;
1637 int_num_fb <= int_num_fx5;
1638 int_num_fw <= int_num_fb;
1639 int_num_fw1 <= int_num_fw;
1640 int_num_fw2 <= int_num_fw1;
1641
1642 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
1643 begin // {
1644 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
1645 begin //{
1646 desr_pend_wr <= 1'b0;
1647 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_5[63:56], 45'b0, `DESR_5[10:0]});
1648 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_5[63:56], 45'b0, `DESR_5[10:0]});
1649 end //}
1650 //if (update_dfesr_w)
1651 if (`ST_ERR_5)
1652 begin //{
1653 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_5[61:55], 55'b0});
1654 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_5[61:55], 55'b0});
1655 end //}
1656 if (update_dsfsr_fw2)
1657 begin //{
1658 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
1659 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_5[3:0]});
1660 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_5[47:0]});
1661
1662 end //}
1663 if (update_isfsr_fw2)
1664 begin //{
1665 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
1666 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_5[2:0]});
1667 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_5[47:0]});
1668
1669 end //}
1670 if (take_err_trap_fw2)
1671 begin //{
1672 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
1673 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
1674 end // }
1675 end // }
1676
1677end //}
1678
1679//removing the addr check as the LSU doesn't flag an invalid_asi_exception
1680//if the addr of diagnostic accesses is not in the valid range. The inst.
1681//still executes. LSU expects that HP won't use addresses in invalid range.
1682
1683always @(negedge (`SPC0.l2clk & ready))
1684begin // {
1685 sync_asi = 1'b0;
1686 ld_data_w <= `ASI_LD_DATA_5;
1687
1688 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_5)
1689 chk_if_asi_ld <= 1'b1;
1690 else
1691 chk_if_asi_ld <= 1'b0;
1692
1693 if (chk_if_asi_ld & `ASI_LD_5)
1694 begin
1695 case (`ASI_5)
1696 8'h66: //ASI_IC_INSTR
1697 begin
1698 //if ((`ASI_ADDR_5 >= 0) & (`ASI_ADDR_5 <= 40'h7ff8))
1699 sync_asi = 1'b1;
1700 end
1701 8'h67: //ASI_IC_TAG
1702 begin
1703 //if ((`ASI_ADDR_5 >= 0) & (`ASI_ADDR_5 <= 40'h7fe0))
1704 sync_asi = 1'b1;
1705 end
1706 8'h46: //ASI_DC_DATA
1707 begin
1708 sync_asi = 1'b1;
1709 end
1710 8'h47: //ASI_DC_TAG
1711 begin
1712 //if ((`ASI_ADDR_5 >= 0) & (`ASI_ADDR_5 <= 40'h7ff0))
1713 sync_asi = 1'b1;
1714 end
1715 8'h48://IRF ECC
1716 begin
1717 //if ((`ASI_ADDR_5 >= 0) & (`ASI_ADDR_5 <= 40'hF8))
1718 sync_asi = 1'b1;
1719 end
1720 8'h49://FRF ECC
1721 begin
1722 //if ((`ASI_ADDR_5 >= 0) & (`ASI_ADDR_5 <= 40'hF8))
1723 sync_asi = 1'b1;
1724 end
1725 8'h4A://STB access, stb ptr can be read also
1726 begin
1727 //if ((`ASI_ADDR_5 >= 0) & (`ASI_ADDR_5 <= 40'h100))
1728 sync_asi = 1'b1;
1729 end
1730 8'h5A://Tick compare reg
1731 begin
1732 //if ((`ASI_ADDR_5 >= 0) & (`ASI_ADDR_5 <= 40'h38))
1733 sync_asi = 1'b1;
1734 end
1735 8'h5B://TSA
1736 begin
1737 //if ((`ASI_ADDR_5 >= 0) & (`ASI_ADDR_5 <= 40'h38))
1738 sync_asi = 1'b1;
1739 end
1740 8'h51://MRA
1741 begin
1742 //if ((`ASI_ADDR_5 >= 0) & (`ASI_ADDR_5 <= 40'h38))
1743 sync_asi = 1'b1;
1744 end
1745 8'h59://scratchpad ecc data read
1746 begin
1747 //if ((`ASI_ADDR_5 >= 0) & (`ASI_ADDR_5 <= 40'h38))
1748 //syncup the ecc data only. For ecc bit 6 is 0.
1749 if (~`SPC0.lsu.lmd.lmq5_pkt[6])
1750 sync_asi = 1'b1;
1751 end
1752 8'h40://cwqcsr,ma_sync access
1753 begin
1754 if ((`ASI_ADDR_5 == 40'h20) || (`ASI_ADDR_5 == 40'h30)
1755 || (`ASI_ADDR_5 == 40'h80)
1756 || ((`ASI_ADDR_5 == 40'ha0) & (`SPU_MA_BUSY_0 == 0) & (`SPU_MA_TID_0 == 5))
1757 )
1758 sync_asi = 1'b1;
1759 end
1760 8'h4C://CLESR, CLFESR access
1761 begin
1762 if ((`ASI_ADDR_5 == 40'h20) || (`ASI_ADDR_5 == 40'h28))
1763 sync_asi = 1'b1;
1764 end
1765 endcase
1766 end
1767
1768 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
1769 begin
1770 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_5, `ASI_ADDR_5, ld_data_w);
1771 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_5, {24'b0, `ASI_ADDR_5}, ld_data_w[63:0]);
1772 end
1773end //}
1774`endif
1775endmodule
1776
1777
1778
1779module err_c0t6 ();
1780`ifndef GATESIM
1781
1782`include "defines.vh"
1783
1784wire [2:0] mycid;
1785wire [2:0] mytid;
1786wire [5:0] mytnum;
1787
1788integer junk;
1789reg ready;
1790reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
1791reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
1792
1793reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
1794reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
1795
1796reg update_dfesr_w;
1797
1798reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
1799reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
1800
1801reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
1802reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
1803
1804reg sync_asi;
1805reg chk_if_asi_ld;
1806reg [63:0] ld_data_w;
1807
1808reg desr_asi_rd, desr_wr, desr_pend_wr;
1809
1810assign mycid = 0;
1811assign mytid = 6;
1812assign mytnum = 0*8 + 6;
1813
1814initial begin //{
1815 desr_asi_rd = 1'b0;
1816 desr_pend_wr = 1'b0;
1817 ready = 0;
1818 @(posedge `SPC0.l2clk) ;
1819 @(posedge `SPC0.l2clk) ;
1820 ready = `PARGS.err_sync_on;
1821end //}
1822
1823`define DSFSR_NEW_IN_6 `SPC0.tlu.ras.dsfsr_6_new_in
1824`define ISFSR_NEW_IN_6 `SPC0.tlu.ras.isfsr_6_new_in
1825
1826`define DSFSR_6 `SPC0.tlu.ras.dsfsr_6
1827`define ISFSR_6 `SPC0.tlu.ras.isfsr_6
1828`define DSFAR_6 `SPC0.tlu.dfd.dsfar_6
1829
1830`define ASI_WR_DSFSR_6 `SPC0.tlu.ras.asi_wr_dsfsr[6]
1831`define ASI_WR_ISFSR_6 `SPC0.tlu.ras.asi_wr_isfsr[6]
1832
1833`define RAS_WRITE_DESR_1st_6 `SPC0.tlu.dfd.ras_write_desr_1st[6]
1834`define RAS_WRITE_DESR_2nd_6 `SPC0.tlu.dfd.ras_write_desr_2nd[6]
1835`define DESR_asi_rd_6 `SPC0.tlu.ras_rd_desr[6]
1836`define DESR_6 `SPC0.tlu.dfd.desr_6
1837
1838`define RAS_WRITE_FESR_6 `SPC0.tlu.ras.write_fesr[6]
1839`define FESR_6 `SPC0.tlu.dfd.fesr_6
1840
1841`define ST_ERR_6 `SPC0.tlu.trl1.take_ftt & `SPC0.tlu.trl1.trap[2]
1842`define SW_REC_ERR_6 `SPC0.tlu.trl1.take_ade & `SPC0.tlu.trl1.trap[2]
1843`define DATA_ACC_ERR_6 `SPC0.tlu.trl1.take_dae & `SPC0.tlu.trl1.trap[2]
1844`define INST_ACC_ERR_6 `SPC0.tlu.trl1.take_iae & `SPC0.tlu.trl1.trap[2]
1845`define INT_PROC_ERR_6 `SPC0.tlu.trl1.take_ipe & `SPC0.tlu.trl1.trap[2]
1846`define HW_CORR_ERR_6 `SPC0.tlu.trl1.take_eer & `SPC0.tlu.trl1.trap[2]
1847`define INST_ACC_MMU_ERR_6 `SPC0.tlu.trl1.take_ime & `SPC0.tlu.trl1.trap[2]
1848`define DATA_ACC_MMU_ERR_6 `SPC0.tlu.trl1.take_dme & `SPC0.tlu.trl1.trap[2]
1849
1850`define LSU_LD_VALID_B `PROBES0.lsu_ld_valid
1851`define LSU_TID_DEC_B_6 `PROBES0.lsu_tid_dec_b[6]
1852`define ASI_LD_6 `SPC0.lsu.lmd.lmq6_pkt[60] & (`SPC0.lsu.lmd.lmq6_pkt[49:48] == 2'b0)
1853`define ASI_6 `SPC0.lsu.lmd.lmq6_pkt[47:40]
1854`define ASI_ADDR_6 `SPC0.lsu.lmd.lmq6_pkt[39:0]
1855`define ASI_LD_DATA_6 `SPC0.lsu_exu_ld_data_b[63:0]
1856`define ASI_LD_COMP_6 tb_top.nas_top.c0.t6.complete_fw2
1857
1858//SPU specific - only one SPU per core
1859`define SPU_MA_BUSY_0 `SPC0.spu.spu_pmu_ma_busy[3]
1860`define SPU_MA_TID_0 `SPC0.spu.spu_pmu_ma_busy[2:0]
1861
1862////////////////////////////////////////////////////////////////////////////////
1863//Capture the status register data from rtl. For disrupting traps,
1864//rtl can modify the contents of the status register before the
1865//trap is taken and intp message is sent to Riesling.
1866//For precise traps, once the status register is updated rtl can't
1867//change the register again before jumping to the trap handler.
1868//So, for deferred and disrupting traps, inform Riesling when the
1869//register is modified while for precise traps wait until Fw2 before
1870//telling Riesling.
1871
1872//TLU asserts the flush and input signals in W stage. I latch them at the
1873//+ve edge of FX4.
1874
1875always @(negedge (`SPC0.l2clk & ready))
1876begin // {
1877 if (`DESR_asi_rd_6)
1878 desr_asi_rd <= 1'b1;
1879 if (desr_asi_rd)
1880 begin
1881 if (desr_wr)
1882 desr_pend_wr <= 1'b1;
1883 if (`ASI_LD_COMP_6[2])
1884 desr_asi_rd <= 1'b0;
1885 end
1886
1887 update_dsfsr_w <= (`DSFSR_NEW_IN_6 != 4'b0) && ~`ASI_WR_DSFSR_6;
1888 update_isfsr_w <= (`ISFSR_NEW_IN_6 != 3'b0) && ~`ASI_WR_ISFSR_6;
1889 desr_wr <= (`RAS_WRITE_DESR_1st_6 || `RAS_WRITE_DESR_2nd_6);
1890 update_dfesr_w <= `RAS_WRITE_FESR_6;
1891 take_err_trap_fx4 <= `ST_ERR_6 | `SW_REC_ERR_6 | `DATA_ACC_ERR_6
1892 | `INST_ACC_ERR_6 | `INT_PROC_ERR_6
1893 | `HW_CORR_ERR_6 | `INST_ACC_MMU_ERR_6
1894 | `DATA_ACC_MMU_ERR_6 ;
1895
1896
1897 if (`ST_ERR_6) int_num_fx4 <= 8'h07;
1898 if (`SW_REC_ERR_6) int_num_fx4 <= 8'h40;
1899 if (`DATA_ACC_ERR_6) int_num_fx4 <= 8'h32;
1900 if (`INST_ACC_ERR_6) int_num_fx4 <= 8'h0A;
1901 if (`INT_PROC_ERR_6) int_num_fx4 <= 8'h29;
1902 if (`HW_CORR_ERR_6) int_num_fx4 <= 8'h63;
1903 if (`INST_ACC_MMU_ERR_6) int_num_fx4 <= 8'h71;
1904 if (`DATA_ACC_MMU_ERR_6) int_num_fx4 <= 8'h72;
1905
1906 update_dsfsr_fx4 <= update_dsfsr_w;
1907 update_dsfsr_fx5 <= update_dsfsr_fx4;
1908 update_dsfsr_fb <= update_dsfsr_fx5;
1909 update_dsfsr_fw <= update_dsfsr_fb;
1910 update_dsfsr_fw1 <= update_dsfsr_fw;
1911 update_dsfsr_fw2 <= update_dsfsr_fw1;
1912
1913 update_isfsr_fx4 <= update_isfsr_w;
1914 update_isfsr_fx5 <= update_isfsr_fx4;
1915 update_isfsr_fb <= update_isfsr_fx5;
1916 update_isfsr_fw <= update_isfsr_fb;
1917 update_isfsr_fw1 <= update_isfsr_fw;
1918 update_isfsr_fw2 <= update_isfsr_fw1;
1919
1920 take_err_trap_fx5 <= take_err_trap_fx4;
1921 take_err_trap_fb <= take_err_trap_fx5;
1922 take_err_trap_fw <= take_err_trap_fb;
1923 take_err_trap_fw1 <= take_err_trap_fw;
1924 take_err_trap_fw2 <= take_err_trap_fw1;
1925
1926 int_num_fx5 <= int_num_fx4;
1927 int_num_fb <= int_num_fx5;
1928 int_num_fw <= int_num_fb;
1929 int_num_fw1 <= int_num_fw;
1930 int_num_fw2 <= int_num_fw1;
1931
1932 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
1933 begin // {
1934 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
1935 begin //{
1936 desr_pend_wr <= 1'b0;
1937 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_6[63:56], 45'b0, `DESR_6[10:0]});
1938 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_6[63:56], 45'b0, `DESR_6[10:0]});
1939 end //}
1940 //if (update_dfesr_w)
1941 if (`ST_ERR_6)
1942 begin //{
1943 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_6[61:55], 55'b0});
1944 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_6[61:55], 55'b0});
1945 end //}
1946 if (update_dsfsr_fw2)
1947 begin //{
1948 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
1949 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_6[3:0]});
1950 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_6[47:0]});
1951
1952 end //}
1953 if (update_isfsr_fw2)
1954 begin //{
1955 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
1956 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_6[2:0]});
1957 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_6[47:0]});
1958
1959 end //}
1960 if (take_err_trap_fw2)
1961 begin //{
1962 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
1963 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
1964 end // }
1965 end // }
1966
1967end //}
1968
1969//removing the addr check as the LSU doesn't flag an invalid_asi_exception
1970//if the addr of diagnostic accesses is not in the valid range. The inst.
1971//still executes. LSU expects that HP won't use addresses in invalid range.
1972
1973always @(negedge (`SPC0.l2clk & ready))
1974begin // {
1975 sync_asi = 1'b0;
1976 ld_data_w <= `ASI_LD_DATA_6;
1977
1978 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_6)
1979 chk_if_asi_ld <= 1'b1;
1980 else
1981 chk_if_asi_ld <= 1'b0;
1982
1983 if (chk_if_asi_ld & `ASI_LD_6)
1984 begin
1985 case (`ASI_6)
1986 8'h66: //ASI_IC_INSTR
1987 begin
1988 //if ((`ASI_ADDR_6 >= 0) & (`ASI_ADDR_6 <= 40'h7ff8))
1989 sync_asi = 1'b1;
1990 end
1991 8'h67: //ASI_IC_TAG
1992 begin
1993 //if ((`ASI_ADDR_6 >= 0) & (`ASI_ADDR_6 <= 40'h7fe0))
1994 sync_asi = 1'b1;
1995 end
1996 8'h46: //ASI_DC_DATA
1997 begin
1998 sync_asi = 1'b1;
1999 end
2000 8'h47: //ASI_DC_TAG
2001 begin
2002 //if ((`ASI_ADDR_6 >= 0) & (`ASI_ADDR_6 <= 40'h7ff0))
2003 sync_asi = 1'b1;
2004 end
2005 8'h48://IRF ECC
2006 begin
2007 //if ((`ASI_ADDR_6 >= 0) & (`ASI_ADDR_6 <= 40'hF8))
2008 sync_asi = 1'b1;
2009 end
2010 8'h49://FRF ECC
2011 begin
2012 //if ((`ASI_ADDR_6 >= 0) & (`ASI_ADDR_6 <= 40'hF8))
2013 sync_asi = 1'b1;
2014 end
2015 8'h4A://STB access, stb ptr can be read also
2016 begin
2017 //if ((`ASI_ADDR_6 >= 0) & (`ASI_ADDR_6 <= 40'h100))
2018 sync_asi = 1'b1;
2019 end
2020 8'h5A://Tick compare reg
2021 begin
2022 //if ((`ASI_ADDR_6 >= 0) & (`ASI_ADDR_6 <= 40'h38))
2023 sync_asi = 1'b1;
2024 end
2025 8'h5B://TSA
2026 begin
2027 //if ((`ASI_ADDR_6 >= 0) & (`ASI_ADDR_6 <= 40'h38))
2028 sync_asi = 1'b1;
2029 end
2030 8'h51://MRA
2031 begin
2032 //if ((`ASI_ADDR_6 >= 0) & (`ASI_ADDR_6 <= 40'h38))
2033 sync_asi = 1'b1;
2034 end
2035 8'h59://scratchpad ecc data read
2036 begin
2037 //if ((`ASI_ADDR_6 >= 0) & (`ASI_ADDR_6 <= 40'h38))
2038 //syncup the ecc data only. For ecc bit 6 is 0.
2039 if (~`SPC0.lsu.lmd.lmq6_pkt[6])
2040 sync_asi = 1'b1;
2041 end
2042 8'h40://cwqcsr,ma_sync access
2043 begin
2044 if ((`ASI_ADDR_6 == 40'h20) || (`ASI_ADDR_6 == 40'h30)
2045 || (`ASI_ADDR_6 == 40'h80)
2046 || ((`ASI_ADDR_6 == 40'ha0) & (`SPU_MA_BUSY_0 == 0) & (`SPU_MA_TID_0 == 6))
2047 )
2048 sync_asi = 1'b1;
2049 end
2050 8'h4C://CLESR, CLFESR access
2051 begin
2052 if ((`ASI_ADDR_6 == 40'h20) || (`ASI_ADDR_6 == 40'h28))
2053 sync_asi = 1'b1;
2054 end
2055 endcase
2056 end
2057
2058 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
2059 begin
2060 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_6, `ASI_ADDR_6, ld_data_w);
2061 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_6, {24'b0, `ASI_ADDR_6}, ld_data_w[63:0]);
2062 end
2063end //}
2064`endif
2065endmodule
2066
2067
2068
2069module err_c0t7 ();
2070`ifndef GATESIM
2071
2072`include "defines.vh"
2073
2074wire [2:0] mycid;
2075wire [2:0] mytid;
2076wire [5:0] mytnum;
2077
2078integer junk;
2079reg ready;
2080reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
2081reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
2082
2083reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
2084reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
2085
2086reg update_dfesr_w;
2087
2088reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
2089reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
2090
2091reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
2092reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
2093
2094reg sync_asi;
2095reg chk_if_asi_ld;
2096reg [63:0] ld_data_w;
2097
2098reg desr_asi_rd, desr_wr, desr_pend_wr;
2099
2100assign mycid = 0;
2101assign mytid = 7;
2102assign mytnum = 0*8 + 7;
2103
2104initial begin //{
2105 desr_asi_rd = 1'b0;
2106 desr_pend_wr = 1'b0;
2107 ready = 0;
2108 @(posedge `SPC0.l2clk) ;
2109 @(posedge `SPC0.l2clk) ;
2110 ready = `PARGS.err_sync_on;
2111end //}
2112
2113`define DSFSR_NEW_IN_7 `SPC0.tlu.ras.dsfsr_7_new_in
2114`define ISFSR_NEW_IN_7 `SPC0.tlu.ras.isfsr_7_new_in
2115
2116`define DSFSR_7 `SPC0.tlu.ras.dsfsr_7
2117`define ISFSR_7 `SPC0.tlu.ras.isfsr_7
2118`define DSFAR_7 `SPC0.tlu.dfd.dsfar_7
2119
2120`define ASI_WR_DSFSR_7 `SPC0.tlu.ras.asi_wr_dsfsr[7]
2121`define ASI_WR_ISFSR_7 `SPC0.tlu.ras.asi_wr_isfsr[7]
2122
2123`define RAS_WRITE_DESR_1st_7 `SPC0.tlu.dfd.ras_write_desr_1st[7]
2124`define RAS_WRITE_DESR_2nd_7 `SPC0.tlu.dfd.ras_write_desr_2nd[7]
2125`define DESR_asi_rd_7 `SPC0.tlu.ras_rd_desr[7]
2126`define DESR_7 `SPC0.tlu.dfd.desr_7
2127
2128`define RAS_WRITE_FESR_7 `SPC0.tlu.ras.write_fesr[7]
2129`define FESR_7 `SPC0.tlu.dfd.fesr_7
2130
2131`define ST_ERR_7 `SPC0.tlu.trl1.take_ftt & `SPC0.tlu.trl1.trap[3]
2132`define SW_REC_ERR_7 `SPC0.tlu.trl1.take_ade & `SPC0.tlu.trl1.trap[3]
2133`define DATA_ACC_ERR_7 `SPC0.tlu.trl1.take_dae & `SPC0.tlu.trl1.trap[3]
2134`define INST_ACC_ERR_7 `SPC0.tlu.trl1.take_iae & `SPC0.tlu.trl1.trap[3]
2135`define INT_PROC_ERR_7 `SPC0.tlu.trl1.take_ipe & `SPC0.tlu.trl1.trap[3]
2136`define HW_CORR_ERR_7 `SPC0.tlu.trl1.take_eer & `SPC0.tlu.trl1.trap[3]
2137`define INST_ACC_MMU_ERR_7 `SPC0.tlu.trl1.take_ime & `SPC0.tlu.trl1.trap[3]
2138`define DATA_ACC_MMU_ERR_7 `SPC0.tlu.trl1.take_dme & `SPC0.tlu.trl1.trap[3]
2139
2140`define LSU_LD_VALID_B `PROBES0.lsu_ld_valid
2141`define LSU_TID_DEC_B_7 `PROBES0.lsu_tid_dec_b[7]
2142`define ASI_LD_7 `SPC0.lsu.lmd.lmq7_pkt[60] & (`SPC0.lsu.lmd.lmq7_pkt[49:48] == 2'b0)
2143`define ASI_7 `SPC0.lsu.lmd.lmq7_pkt[47:40]
2144`define ASI_ADDR_7 `SPC0.lsu.lmd.lmq7_pkt[39:0]
2145`define ASI_LD_DATA_7 `SPC0.lsu_exu_ld_data_b[63:0]
2146`define ASI_LD_COMP_7 tb_top.nas_top.c0.t7.complete_fw2
2147
2148//SPU specific - only one SPU per core
2149`define SPU_MA_BUSY_0 `SPC0.spu.spu_pmu_ma_busy[3]
2150`define SPU_MA_TID_0 `SPC0.spu.spu_pmu_ma_busy[2:0]
2151
2152////////////////////////////////////////////////////////////////////////////////
2153//Capture the status register data from rtl. For disrupting traps,
2154//rtl can modify the contents of the status register before the
2155//trap is taken and intp message is sent to Riesling.
2156//For precise traps, once the status register is updated rtl can't
2157//change the register again before jumping to the trap handler.
2158//So, for deferred and disrupting traps, inform Riesling when the
2159//register is modified while for precise traps wait until Fw2 before
2160//telling Riesling.
2161
2162//TLU asserts the flush and input signals in W stage. I latch them at the
2163//+ve edge of FX4.
2164
2165always @(negedge (`SPC0.l2clk & ready))
2166begin // {
2167 if (`DESR_asi_rd_7)
2168 desr_asi_rd <= 1'b1;
2169 if (desr_asi_rd)
2170 begin
2171 if (desr_wr)
2172 desr_pend_wr <= 1'b1;
2173 if (`ASI_LD_COMP_7[2])
2174 desr_asi_rd <= 1'b0;
2175 end
2176
2177 update_dsfsr_w <= (`DSFSR_NEW_IN_7 != 4'b0) && ~`ASI_WR_DSFSR_7;
2178 update_isfsr_w <= (`ISFSR_NEW_IN_7 != 3'b0) && ~`ASI_WR_ISFSR_7;
2179 desr_wr <= (`RAS_WRITE_DESR_1st_7 || `RAS_WRITE_DESR_2nd_7);
2180 update_dfesr_w <= `RAS_WRITE_FESR_7;
2181 take_err_trap_fx4 <= `ST_ERR_7 | `SW_REC_ERR_7 | `DATA_ACC_ERR_7
2182 | `INST_ACC_ERR_7 | `INT_PROC_ERR_7
2183 | `HW_CORR_ERR_7 | `INST_ACC_MMU_ERR_7
2184 | `DATA_ACC_MMU_ERR_7 ;
2185
2186
2187 if (`ST_ERR_7) int_num_fx4 <= 8'h07;
2188 if (`SW_REC_ERR_7) int_num_fx4 <= 8'h40;
2189 if (`DATA_ACC_ERR_7) int_num_fx4 <= 8'h32;
2190 if (`INST_ACC_ERR_7) int_num_fx4 <= 8'h0A;
2191 if (`INT_PROC_ERR_7) int_num_fx4 <= 8'h29;
2192 if (`HW_CORR_ERR_7) int_num_fx4 <= 8'h63;
2193 if (`INST_ACC_MMU_ERR_7) int_num_fx4 <= 8'h71;
2194 if (`DATA_ACC_MMU_ERR_7) int_num_fx4 <= 8'h72;
2195
2196 update_dsfsr_fx4 <= update_dsfsr_w;
2197 update_dsfsr_fx5 <= update_dsfsr_fx4;
2198 update_dsfsr_fb <= update_dsfsr_fx5;
2199 update_dsfsr_fw <= update_dsfsr_fb;
2200 update_dsfsr_fw1 <= update_dsfsr_fw;
2201 update_dsfsr_fw2 <= update_dsfsr_fw1;
2202
2203 update_isfsr_fx4 <= update_isfsr_w;
2204 update_isfsr_fx5 <= update_isfsr_fx4;
2205 update_isfsr_fb <= update_isfsr_fx5;
2206 update_isfsr_fw <= update_isfsr_fb;
2207 update_isfsr_fw1 <= update_isfsr_fw;
2208 update_isfsr_fw2 <= update_isfsr_fw1;
2209
2210 take_err_trap_fx5 <= take_err_trap_fx4;
2211 take_err_trap_fb <= take_err_trap_fx5;
2212 take_err_trap_fw <= take_err_trap_fb;
2213 take_err_trap_fw1 <= take_err_trap_fw;
2214 take_err_trap_fw2 <= take_err_trap_fw1;
2215
2216 int_num_fx5 <= int_num_fx4;
2217 int_num_fb <= int_num_fx5;
2218 int_num_fw <= int_num_fb;
2219 int_num_fw1 <= int_num_fw;
2220 int_num_fw2 <= int_num_fw1;
2221
2222 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
2223 begin // {
2224 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
2225 begin //{
2226 desr_pend_wr <= 1'b0;
2227 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_7[63:56], 45'b0, `DESR_7[10:0]});
2228 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_7[63:56], 45'b0, `DESR_7[10:0]});
2229 end //}
2230 //if (update_dfesr_w)
2231 if (`ST_ERR_7)
2232 begin //{
2233 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_7[61:55], 55'b0});
2234 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_7[61:55], 55'b0});
2235 end //}
2236 if (update_dsfsr_fw2)
2237 begin //{
2238 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
2239 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_7[3:0]});
2240 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_7[47:0]});
2241
2242 end //}
2243 if (update_isfsr_fw2)
2244 begin //{
2245 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
2246 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_7[2:0]});
2247 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_7[47:0]});
2248
2249 end //}
2250 if (take_err_trap_fw2)
2251 begin //{
2252 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
2253 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
2254 end // }
2255 end // }
2256
2257end //}
2258
2259//removing the addr check as the LSU doesn't flag an invalid_asi_exception
2260//if the addr of diagnostic accesses is not in the valid range. The inst.
2261//still executes. LSU expects that HP won't use addresses in invalid range.
2262
2263always @(negedge (`SPC0.l2clk & ready))
2264begin // {
2265 sync_asi = 1'b0;
2266 ld_data_w <= `ASI_LD_DATA_7;
2267
2268 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_7)
2269 chk_if_asi_ld <= 1'b1;
2270 else
2271 chk_if_asi_ld <= 1'b0;
2272
2273 if (chk_if_asi_ld & `ASI_LD_7)
2274 begin
2275 case (`ASI_7)
2276 8'h66: //ASI_IC_INSTR
2277 begin
2278 //if ((`ASI_ADDR_7 >= 0) & (`ASI_ADDR_7 <= 40'h7ff8))
2279 sync_asi = 1'b1;
2280 end
2281 8'h67: //ASI_IC_TAG
2282 begin
2283 //if ((`ASI_ADDR_7 >= 0) & (`ASI_ADDR_7 <= 40'h7fe0))
2284 sync_asi = 1'b1;
2285 end
2286 8'h46: //ASI_DC_DATA
2287 begin
2288 sync_asi = 1'b1;
2289 end
2290 8'h47: //ASI_DC_TAG
2291 begin
2292 //if ((`ASI_ADDR_7 >= 0) & (`ASI_ADDR_7 <= 40'h7ff0))
2293 sync_asi = 1'b1;
2294 end
2295 8'h48://IRF ECC
2296 begin
2297 //if ((`ASI_ADDR_7 >= 0) & (`ASI_ADDR_7 <= 40'hF8))
2298 sync_asi = 1'b1;
2299 end
2300 8'h49://FRF ECC
2301 begin
2302 //if ((`ASI_ADDR_7 >= 0) & (`ASI_ADDR_7 <= 40'hF8))
2303 sync_asi = 1'b1;
2304 end
2305 8'h4A://STB access, stb ptr can be read also
2306 begin
2307 //if ((`ASI_ADDR_7 >= 0) & (`ASI_ADDR_7 <= 40'h100))
2308 sync_asi = 1'b1;
2309 end
2310 8'h5A://Tick compare reg
2311 begin
2312 //if ((`ASI_ADDR_7 >= 0) & (`ASI_ADDR_7 <= 40'h38))
2313 sync_asi = 1'b1;
2314 end
2315 8'h5B://TSA
2316 begin
2317 //if ((`ASI_ADDR_7 >= 0) & (`ASI_ADDR_7 <= 40'h38))
2318 sync_asi = 1'b1;
2319 end
2320 8'h51://MRA
2321 begin
2322 //if ((`ASI_ADDR_7 >= 0) & (`ASI_ADDR_7 <= 40'h38))
2323 sync_asi = 1'b1;
2324 end
2325 8'h59://scratchpad ecc data read
2326 begin
2327 //if ((`ASI_ADDR_7 >= 0) & (`ASI_ADDR_7 <= 40'h38))
2328 //syncup the ecc data only. For ecc bit 6 is 0.
2329 if (~`SPC0.lsu.lmd.lmq7_pkt[6])
2330 sync_asi = 1'b1;
2331 end
2332 8'h40://cwqcsr,ma_sync access
2333 begin
2334 if ((`ASI_ADDR_7 == 40'h20) || (`ASI_ADDR_7 == 40'h30)
2335 || (`ASI_ADDR_7 == 40'h80)
2336 || ((`ASI_ADDR_7 == 40'ha0) & (`SPU_MA_BUSY_0 == 0) & (`SPU_MA_TID_0 == 7))
2337 )
2338 sync_asi = 1'b1;
2339 end
2340 8'h4C://CLESR, CLFESR access
2341 begin
2342 if ((`ASI_ADDR_7 == 40'h20) || (`ASI_ADDR_7 == 40'h28))
2343 sync_asi = 1'b1;
2344 end
2345 endcase
2346 end
2347
2348 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
2349 begin
2350 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_7, `ASI_ADDR_7, ld_data_w);
2351 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_7, {24'b0, `ASI_ADDR_7}, ld_data_w[63:0]);
2352 end
2353end //}
2354`endif
2355endmodule
2356
2357`endif
2358
2359`ifdef CORE_1
2360
2361
2362
2363module err_c1t0 ();
2364`ifndef GATESIM
2365
2366`include "defines.vh"
2367
2368wire [2:0] mycid;
2369wire [2:0] mytid;
2370wire [5:0] mytnum;
2371
2372integer junk;
2373reg ready;
2374reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
2375reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
2376
2377reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
2378reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
2379
2380reg update_dfesr_w;
2381
2382reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
2383reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
2384
2385reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
2386reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
2387
2388reg sync_asi;
2389reg chk_if_asi_ld;
2390reg [63:0] ld_data_w;
2391
2392reg desr_asi_rd, desr_wr, desr_pend_wr;
2393
2394assign mycid = 1;
2395assign mytid = 0;
2396assign mytnum = 1*8 + 0;
2397
2398initial begin //{
2399 desr_asi_rd = 1'b0;
2400 desr_pend_wr = 1'b0;
2401 ready = 0;
2402 @(posedge `SPC1.l2clk) ;
2403 @(posedge `SPC1.l2clk) ;
2404 ready = `PARGS.err_sync_on;
2405end //}
2406
2407`define DSFSR_NEW_IN_8 `SPC1.tlu.ras.dsfsr_0_new_in
2408`define ISFSR_NEW_IN_8 `SPC1.tlu.ras.isfsr_0_new_in
2409
2410`define DSFSR_8 `SPC1.tlu.ras.dsfsr_0
2411`define ISFSR_8 `SPC1.tlu.ras.isfsr_0
2412`define DSFAR_8 `SPC1.tlu.dfd.dsfar_0
2413
2414`define ASI_WR_DSFSR_8 `SPC1.tlu.ras.asi_wr_dsfsr[0]
2415`define ASI_WR_ISFSR_8 `SPC1.tlu.ras.asi_wr_isfsr[0]
2416
2417`define RAS_WRITE_DESR_1st_8 `SPC1.tlu.dfd.ras_write_desr_1st[0]
2418`define RAS_WRITE_DESR_2nd_8 `SPC1.tlu.dfd.ras_write_desr_2nd[0]
2419`define DESR_asi_rd_8 `SPC1.tlu.ras_rd_desr[0]
2420`define DESR_8 `SPC1.tlu.dfd.desr_0
2421
2422`define RAS_WRITE_FESR_8 `SPC1.tlu.ras.write_fesr[0]
2423`define FESR_8 `SPC1.tlu.dfd.fesr_0
2424
2425`define ST_ERR_8 `SPC1.tlu.trl0.take_ftt & `SPC1.tlu.trl0.trap[0]
2426`define SW_REC_ERR_8 `SPC1.tlu.trl0.take_ade & `SPC1.tlu.trl0.trap[0]
2427`define DATA_ACC_ERR_8 `SPC1.tlu.trl0.take_dae & `SPC1.tlu.trl0.trap[0]
2428`define INST_ACC_ERR_8 `SPC1.tlu.trl0.take_iae & `SPC1.tlu.trl0.trap[0]
2429`define INT_PROC_ERR_8 `SPC1.tlu.trl0.take_ipe & `SPC1.tlu.trl0.trap[0]
2430`define HW_CORR_ERR_8 `SPC1.tlu.trl0.take_eer & `SPC1.tlu.trl0.trap[0]
2431`define INST_ACC_MMU_ERR_8 `SPC1.tlu.trl0.take_ime & `SPC1.tlu.trl0.trap[0]
2432`define DATA_ACC_MMU_ERR_8 `SPC1.tlu.trl0.take_dme & `SPC1.tlu.trl0.trap[0]
2433
2434`define LSU_LD_VALID_B `PROBES1.lsu_ld_valid
2435`define LSU_TID_DEC_B_8 `PROBES1.lsu_tid_dec_b[0]
2436`define ASI_LD_8 `SPC1.lsu.lmd.lmq0_pkt[60] & (`SPC1.lsu.lmd.lmq0_pkt[49:48] == 2'b0)
2437`define ASI_8 `SPC1.lsu.lmd.lmq0_pkt[47:40]
2438`define ASI_ADDR_8 `SPC1.lsu.lmd.lmq0_pkt[39:0]
2439`define ASI_LD_DATA_8 `SPC1.lsu_exu_ld_data_b[63:0]
2440`define ASI_LD_COMP_8 tb_top.nas_top.c1.t0.complete_fw2
2441
2442//SPU specific - only one SPU per core
2443`define SPU_MA_BUSY_1 `SPC1.spu.spu_pmu_ma_busy[3]
2444`define SPU_MA_TID_1 `SPC1.spu.spu_pmu_ma_busy[2:0]
2445
2446////////////////////////////////////////////////////////////////////////////////
2447//Capture the status register data from rtl. For disrupting traps,
2448//rtl can modify the contents of the status register before the
2449//trap is taken and intp message is sent to Riesling.
2450//For precise traps, once the status register is updated rtl can't
2451//change the register again before jumping to the trap handler.
2452//So, for deferred and disrupting traps, inform Riesling when the
2453//register is modified while for precise traps wait until Fw2 before
2454//telling Riesling.
2455
2456//TLU asserts the flush and input signals in W stage. I latch them at the
2457//+ve edge of FX4.
2458
2459always @(negedge (`SPC1.l2clk & ready))
2460begin // {
2461 if (`DESR_asi_rd_8)
2462 desr_asi_rd <= 1'b1;
2463 if (desr_asi_rd)
2464 begin
2465 if (desr_wr)
2466 desr_pend_wr <= 1'b1;
2467 if (`ASI_LD_COMP_8[2])
2468 desr_asi_rd <= 1'b0;
2469 end
2470
2471 update_dsfsr_w <= (`DSFSR_NEW_IN_8 != 4'b0) && ~`ASI_WR_DSFSR_8;
2472 update_isfsr_w <= (`ISFSR_NEW_IN_8 != 3'b0) && ~`ASI_WR_ISFSR_8;
2473 desr_wr <= (`RAS_WRITE_DESR_1st_8 || `RAS_WRITE_DESR_2nd_8);
2474 update_dfesr_w <= `RAS_WRITE_FESR_8;
2475 take_err_trap_fx4 <= `ST_ERR_8 | `SW_REC_ERR_8 | `DATA_ACC_ERR_8
2476 | `INST_ACC_ERR_8 | `INT_PROC_ERR_8
2477 | `HW_CORR_ERR_8 | `INST_ACC_MMU_ERR_8
2478 | `DATA_ACC_MMU_ERR_8 ;
2479
2480
2481 if (`ST_ERR_8) int_num_fx4 <= 8'h07;
2482 if (`SW_REC_ERR_8) int_num_fx4 <= 8'h40;
2483 if (`DATA_ACC_ERR_8) int_num_fx4 <= 8'h32;
2484 if (`INST_ACC_ERR_8) int_num_fx4 <= 8'h0A;
2485 if (`INT_PROC_ERR_8) int_num_fx4 <= 8'h29;
2486 if (`HW_CORR_ERR_8) int_num_fx4 <= 8'h63;
2487 if (`INST_ACC_MMU_ERR_8) int_num_fx4 <= 8'h71;
2488 if (`DATA_ACC_MMU_ERR_8) int_num_fx4 <= 8'h72;
2489
2490 update_dsfsr_fx4 <= update_dsfsr_w;
2491 update_dsfsr_fx5 <= update_dsfsr_fx4;
2492 update_dsfsr_fb <= update_dsfsr_fx5;
2493 update_dsfsr_fw <= update_dsfsr_fb;
2494 update_dsfsr_fw1 <= update_dsfsr_fw;
2495 update_dsfsr_fw2 <= update_dsfsr_fw1;
2496
2497 update_isfsr_fx4 <= update_isfsr_w;
2498 update_isfsr_fx5 <= update_isfsr_fx4;
2499 update_isfsr_fb <= update_isfsr_fx5;
2500 update_isfsr_fw <= update_isfsr_fb;
2501 update_isfsr_fw1 <= update_isfsr_fw;
2502 update_isfsr_fw2 <= update_isfsr_fw1;
2503
2504 take_err_trap_fx5 <= take_err_trap_fx4;
2505 take_err_trap_fb <= take_err_trap_fx5;
2506 take_err_trap_fw <= take_err_trap_fb;
2507 take_err_trap_fw1 <= take_err_trap_fw;
2508 take_err_trap_fw2 <= take_err_trap_fw1;
2509
2510 int_num_fx5 <= int_num_fx4;
2511 int_num_fb <= int_num_fx5;
2512 int_num_fw <= int_num_fb;
2513 int_num_fw1 <= int_num_fw;
2514 int_num_fw2 <= int_num_fw1;
2515
2516 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
2517 begin // {
2518 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
2519 begin //{
2520 desr_pend_wr <= 1'b0;
2521 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_8[63:56], 45'b0, `DESR_8[10:0]});
2522 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_8[63:56], 45'b0, `DESR_8[10:0]});
2523 end //}
2524 //if (update_dfesr_w)
2525 if (`ST_ERR_8)
2526 begin //{
2527 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_8[61:55], 55'b0});
2528 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_8[61:55], 55'b0});
2529 end //}
2530 if (update_dsfsr_fw2)
2531 begin //{
2532 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
2533 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_8[3:0]});
2534 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_8[47:0]});
2535
2536 end //}
2537 if (update_isfsr_fw2)
2538 begin //{
2539 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
2540 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_8[2:0]});
2541 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_8[47:0]});
2542
2543 end //}
2544 if (take_err_trap_fw2)
2545 begin //{
2546 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
2547 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
2548 end // }
2549 end // }
2550
2551end //}
2552
2553//removing the addr check as the LSU doesn't flag an invalid_asi_exception
2554//if the addr of diagnostic accesses is not in the valid range. The inst.
2555//still executes. LSU expects that HP won't use addresses in invalid range.
2556
2557always @(negedge (`SPC1.l2clk & ready))
2558begin // {
2559 sync_asi = 1'b0;
2560 ld_data_w <= `ASI_LD_DATA_8;
2561
2562 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_8)
2563 chk_if_asi_ld <= 1'b1;
2564 else
2565 chk_if_asi_ld <= 1'b0;
2566
2567 if (chk_if_asi_ld & `ASI_LD_8)
2568 begin
2569 case (`ASI_8)
2570 8'h66: //ASI_IC_INSTR
2571 begin
2572 //if ((`ASI_ADDR_8 >= 0) & (`ASI_ADDR_8 <= 40'h7ff8))
2573 sync_asi = 1'b1;
2574 end
2575 8'h67: //ASI_IC_TAG
2576 begin
2577 //if ((`ASI_ADDR_8 >= 0) & (`ASI_ADDR_8 <= 40'h7fe0))
2578 sync_asi = 1'b1;
2579 end
2580 8'h46: //ASI_DC_DATA
2581 begin
2582 sync_asi = 1'b1;
2583 end
2584 8'h47: //ASI_DC_TAG
2585 begin
2586 //if ((`ASI_ADDR_8 >= 0) & (`ASI_ADDR_8 <= 40'h7ff0))
2587 sync_asi = 1'b1;
2588 end
2589 8'h48://IRF ECC
2590 begin
2591 //if ((`ASI_ADDR_8 >= 0) & (`ASI_ADDR_8 <= 40'hF8))
2592 sync_asi = 1'b1;
2593 end
2594 8'h49://FRF ECC
2595 begin
2596 //if ((`ASI_ADDR_8 >= 0) & (`ASI_ADDR_8 <= 40'hF8))
2597 sync_asi = 1'b1;
2598 end
2599 8'h4A://STB access, stb ptr can be read also
2600 begin
2601 //if ((`ASI_ADDR_8 >= 0) & (`ASI_ADDR_8 <= 40'h100))
2602 sync_asi = 1'b1;
2603 end
2604 8'h5A://Tick compare reg
2605 begin
2606 //if ((`ASI_ADDR_8 >= 0) & (`ASI_ADDR_8 <= 40'h38))
2607 sync_asi = 1'b1;
2608 end
2609 8'h5B://TSA
2610 begin
2611 //if ((`ASI_ADDR_8 >= 0) & (`ASI_ADDR_8 <= 40'h38))
2612 sync_asi = 1'b1;
2613 end
2614 8'h51://MRA
2615 begin
2616 //if ((`ASI_ADDR_8 >= 0) & (`ASI_ADDR_8 <= 40'h38))
2617 sync_asi = 1'b1;
2618 end
2619 8'h59://scratchpad ecc data read
2620 begin
2621 //if ((`ASI_ADDR_8 >= 0) & (`ASI_ADDR_8 <= 40'h38))
2622 //syncup the ecc data only. For ecc bit 6 is 0.
2623 if (~`SPC1.lsu.lmd.lmq0_pkt[6])
2624 sync_asi = 1'b1;
2625 end
2626 8'h40://cwqcsr,ma_sync access
2627 begin
2628 if ((`ASI_ADDR_8 == 40'h20) || (`ASI_ADDR_8 == 40'h30)
2629 || (`ASI_ADDR_8 == 40'h80)
2630 || ((`ASI_ADDR_8 == 40'ha0) & (`SPU_MA_BUSY_1 == 0) & (`SPU_MA_TID_1 == 0))
2631 )
2632 sync_asi = 1'b1;
2633 end
2634 8'h4C://CLESR, CLFESR access
2635 begin
2636 if ((`ASI_ADDR_8 == 40'h20) || (`ASI_ADDR_8 == 40'h28))
2637 sync_asi = 1'b1;
2638 end
2639 endcase
2640 end
2641
2642 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
2643 begin
2644 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_8, `ASI_ADDR_8, ld_data_w);
2645 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_8, {24'b0, `ASI_ADDR_8}, ld_data_w[63:0]);
2646 end
2647end //}
2648`endif
2649endmodule
2650
2651
2652
2653module err_c1t1 ();
2654`ifndef GATESIM
2655
2656`include "defines.vh"
2657
2658wire [2:0] mycid;
2659wire [2:0] mytid;
2660wire [5:0] mytnum;
2661
2662integer junk;
2663reg ready;
2664reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
2665reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
2666
2667reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
2668reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
2669
2670reg update_dfesr_w;
2671
2672reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
2673reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
2674
2675reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
2676reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
2677
2678reg sync_asi;
2679reg chk_if_asi_ld;
2680reg [63:0] ld_data_w;
2681
2682reg desr_asi_rd, desr_wr, desr_pend_wr;
2683
2684assign mycid = 1;
2685assign mytid = 1;
2686assign mytnum = 1*8 + 1;
2687
2688initial begin //{
2689 desr_asi_rd = 1'b0;
2690 desr_pend_wr = 1'b0;
2691 ready = 0;
2692 @(posedge `SPC1.l2clk) ;
2693 @(posedge `SPC1.l2clk) ;
2694 ready = `PARGS.err_sync_on;
2695end //}
2696
2697`define DSFSR_NEW_IN_9 `SPC1.tlu.ras.dsfsr_1_new_in
2698`define ISFSR_NEW_IN_9 `SPC1.tlu.ras.isfsr_1_new_in
2699
2700`define DSFSR_9 `SPC1.tlu.ras.dsfsr_1
2701`define ISFSR_9 `SPC1.tlu.ras.isfsr_1
2702`define DSFAR_9 `SPC1.tlu.dfd.dsfar_1
2703
2704`define ASI_WR_DSFSR_9 `SPC1.tlu.ras.asi_wr_dsfsr[1]
2705`define ASI_WR_ISFSR_9 `SPC1.tlu.ras.asi_wr_isfsr[1]
2706
2707`define RAS_WRITE_DESR_1st_9 `SPC1.tlu.dfd.ras_write_desr_1st[1]
2708`define RAS_WRITE_DESR_2nd_9 `SPC1.tlu.dfd.ras_write_desr_2nd[1]
2709`define DESR_asi_rd_9 `SPC1.tlu.ras_rd_desr[1]
2710`define DESR_9 `SPC1.tlu.dfd.desr_1
2711
2712`define RAS_WRITE_FESR_9 `SPC1.tlu.ras.write_fesr[1]
2713`define FESR_9 `SPC1.tlu.dfd.fesr_1
2714
2715`define ST_ERR_9 `SPC1.tlu.trl0.take_ftt & `SPC1.tlu.trl0.trap[1]
2716`define SW_REC_ERR_9 `SPC1.tlu.trl0.take_ade & `SPC1.tlu.trl0.trap[1]
2717`define DATA_ACC_ERR_9 `SPC1.tlu.trl0.take_dae & `SPC1.tlu.trl0.trap[1]
2718`define INST_ACC_ERR_9 `SPC1.tlu.trl0.take_iae & `SPC1.tlu.trl0.trap[1]
2719`define INT_PROC_ERR_9 `SPC1.tlu.trl0.take_ipe & `SPC1.tlu.trl0.trap[1]
2720`define HW_CORR_ERR_9 `SPC1.tlu.trl0.take_eer & `SPC1.tlu.trl0.trap[1]
2721`define INST_ACC_MMU_ERR_9 `SPC1.tlu.trl0.take_ime & `SPC1.tlu.trl0.trap[1]
2722`define DATA_ACC_MMU_ERR_9 `SPC1.tlu.trl0.take_dme & `SPC1.tlu.trl0.trap[1]
2723
2724`define LSU_LD_VALID_B `PROBES1.lsu_ld_valid
2725`define LSU_TID_DEC_B_9 `PROBES1.lsu_tid_dec_b[1]
2726`define ASI_LD_9 `SPC1.lsu.lmd.lmq1_pkt[60] & (`SPC1.lsu.lmd.lmq1_pkt[49:48] == 2'b0)
2727`define ASI_9 `SPC1.lsu.lmd.lmq1_pkt[47:40]
2728`define ASI_ADDR_9 `SPC1.lsu.lmd.lmq1_pkt[39:0]
2729`define ASI_LD_DATA_9 `SPC1.lsu_exu_ld_data_b[63:0]
2730`define ASI_LD_COMP_9 tb_top.nas_top.c1.t1.complete_fw2
2731
2732//SPU specific - only one SPU per core
2733`define SPU_MA_BUSY_1 `SPC1.spu.spu_pmu_ma_busy[3]
2734`define SPU_MA_TID_1 `SPC1.spu.spu_pmu_ma_busy[2:0]
2735
2736////////////////////////////////////////////////////////////////////////////////
2737//Capture the status register data from rtl. For disrupting traps,
2738//rtl can modify the contents of the status register before the
2739//trap is taken and intp message is sent to Riesling.
2740//For precise traps, once the status register is updated rtl can't
2741//change the register again before jumping to the trap handler.
2742//So, for deferred and disrupting traps, inform Riesling when the
2743//register is modified while for precise traps wait until Fw2 before
2744//telling Riesling.
2745
2746//TLU asserts the flush and input signals in W stage. I latch them at the
2747//+ve edge of FX4.
2748
2749always @(negedge (`SPC1.l2clk & ready))
2750begin // {
2751 if (`DESR_asi_rd_9)
2752 desr_asi_rd <= 1'b1;
2753 if (desr_asi_rd)
2754 begin
2755 if (desr_wr)
2756 desr_pend_wr <= 1'b1;
2757 if (`ASI_LD_COMP_9[2])
2758 desr_asi_rd <= 1'b0;
2759 end
2760
2761 update_dsfsr_w <= (`DSFSR_NEW_IN_9 != 4'b0) && ~`ASI_WR_DSFSR_9;
2762 update_isfsr_w <= (`ISFSR_NEW_IN_9 != 3'b0) && ~`ASI_WR_ISFSR_9;
2763 desr_wr <= (`RAS_WRITE_DESR_1st_9 || `RAS_WRITE_DESR_2nd_9);
2764 update_dfesr_w <= `RAS_WRITE_FESR_9;
2765 take_err_trap_fx4 <= `ST_ERR_9 | `SW_REC_ERR_9 | `DATA_ACC_ERR_9
2766 | `INST_ACC_ERR_9 | `INT_PROC_ERR_9
2767 | `HW_CORR_ERR_9 | `INST_ACC_MMU_ERR_9
2768 | `DATA_ACC_MMU_ERR_9 ;
2769
2770
2771 if (`ST_ERR_9) int_num_fx4 <= 8'h07;
2772 if (`SW_REC_ERR_9) int_num_fx4 <= 8'h40;
2773 if (`DATA_ACC_ERR_9) int_num_fx4 <= 8'h32;
2774 if (`INST_ACC_ERR_9) int_num_fx4 <= 8'h0A;
2775 if (`INT_PROC_ERR_9) int_num_fx4 <= 8'h29;
2776 if (`HW_CORR_ERR_9) int_num_fx4 <= 8'h63;
2777 if (`INST_ACC_MMU_ERR_9) int_num_fx4 <= 8'h71;
2778 if (`DATA_ACC_MMU_ERR_9) int_num_fx4 <= 8'h72;
2779
2780 update_dsfsr_fx4 <= update_dsfsr_w;
2781 update_dsfsr_fx5 <= update_dsfsr_fx4;
2782 update_dsfsr_fb <= update_dsfsr_fx5;
2783 update_dsfsr_fw <= update_dsfsr_fb;
2784 update_dsfsr_fw1 <= update_dsfsr_fw;
2785 update_dsfsr_fw2 <= update_dsfsr_fw1;
2786
2787 update_isfsr_fx4 <= update_isfsr_w;
2788 update_isfsr_fx5 <= update_isfsr_fx4;
2789 update_isfsr_fb <= update_isfsr_fx5;
2790 update_isfsr_fw <= update_isfsr_fb;
2791 update_isfsr_fw1 <= update_isfsr_fw;
2792 update_isfsr_fw2 <= update_isfsr_fw1;
2793
2794 take_err_trap_fx5 <= take_err_trap_fx4;
2795 take_err_trap_fb <= take_err_trap_fx5;
2796 take_err_trap_fw <= take_err_trap_fb;
2797 take_err_trap_fw1 <= take_err_trap_fw;
2798 take_err_trap_fw2 <= take_err_trap_fw1;
2799
2800 int_num_fx5 <= int_num_fx4;
2801 int_num_fb <= int_num_fx5;
2802 int_num_fw <= int_num_fb;
2803 int_num_fw1 <= int_num_fw;
2804 int_num_fw2 <= int_num_fw1;
2805
2806 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
2807 begin // {
2808 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
2809 begin //{
2810 desr_pend_wr <= 1'b0;
2811 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_9[63:56], 45'b0, `DESR_9[10:0]});
2812 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_9[63:56], 45'b0, `DESR_9[10:0]});
2813 end //}
2814 //if (update_dfesr_w)
2815 if (`ST_ERR_9)
2816 begin //{
2817 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_9[61:55], 55'b0});
2818 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_9[61:55], 55'b0});
2819 end //}
2820 if (update_dsfsr_fw2)
2821 begin //{
2822 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
2823 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_9[3:0]});
2824 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_9[47:0]});
2825
2826 end //}
2827 if (update_isfsr_fw2)
2828 begin //{
2829 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
2830 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_9[2:0]});
2831 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_9[47:0]});
2832
2833 end //}
2834 if (take_err_trap_fw2)
2835 begin //{
2836 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
2837 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
2838 end // }
2839 end // }
2840
2841end //}
2842
2843//removing the addr check as the LSU doesn't flag an invalid_asi_exception
2844//if the addr of diagnostic accesses is not in the valid range. The inst.
2845//still executes. LSU expects that HP won't use addresses in invalid range.
2846
2847always @(negedge (`SPC1.l2clk & ready))
2848begin // {
2849 sync_asi = 1'b0;
2850 ld_data_w <= `ASI_LD_DATA_9;
2851
2852 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_9)
2853 chk_if_asi_ld <= 1'b1;
2854 else
2855 chk_if_asi_ld <= 1'b0;
2856
2857 if (chk_if_asi_ld & `ASI_LD_9)
2858 begin
2859 case (`ASI_9)
2860 8'h66: //ASI_IC_INSTR
2861 begin
2862 //if ((`ASI_ADDR_9 >= 0) & (`ASI_ADDR_9 <= 40'h7ff8))
2863 sync_asi = 1'b1;
2864 end
2865 8'h67: //ASI_IC_TAG
2866 begin
2867 //if ((`ASI_ADDR_9 >= 0) & (`ASI_ADDR_9 <= 40'h7fe0))
2868 sync_asi = 1'b1;
2869 end
2870 8'h46: //ASI_DC_DATA
2871 begin
2872 sync_asi = 1'b1;
2873 end
2874 8'h47: //ASI_DC_TAG
2875 begin
2876 //if ((`ASI_ADDR_9 >= 0) & (`ASI_ADDR_9 <= 40'h7ff0))
2877 sync_asi = 1'b1;
2878 end
2879 8'h48://IRF ECC
2880 begin
2881 //if ((`ASI_ADDR_9 >= 0) & (`ASI_ADDR_9 <= 40'hF8))
2882 sync_asi = 1'b1;
2883 end
2884 8'h49://FRF ECC
2885 begin
2886 //if ((`ASI_ADDR_9 >= 0) & (`ASI_ADDR_9 <= 40'hF8))
2887 sync_asi = 1'b1;
2888 end
2889 8'h4A://STB access, stb ptr can be read also
2890 begin
2891 //if ((`ASI_ADDR_9 >= 0) & (`ASI_ADDR_9 <= 40'h100))
2892 sync_asi = 1'b1;
2893 end
2894 8'h5A://Tick compare reg
2895 begin
2896 //if ((`ASI_ADDR_9 >= 0) & (`ASI_ADDR_9 <= 40'h38))
2897 sync_asi = 1'b1;
2898 end
2899 8'h5B://TSA
2900 begin
2901 //if ((`ASI_ADDR_9 >= 0) & (`ASI_ADDR_9 <= 40'h38))
2902 sync_asi = 1'b1;
2903 end
2904 8'h51://MRA
2905 begin
2906 //if ((`ASI_ADDR_9 >= 0) & (`ASI_ADDR_9 <= 40'h38))
2907 sync_asi = 1'b1;
2908 end
2909 8'h59://scratchpad ecc data read
2910 begin
2911 //if ((`ASI_ADDR_9 >= 0) & (`ASI_ADDR_9 <= 40'h38))
2912 //syncup the ecc data only. For ecc bit 6 is 0.
2913 if (~`SPC1.lsu.lmd.lmq1_pkt[6])
2914 sync_asi = 1'b1;
2915 end
2916 8'h40://cwqcsr,ma_sync access
2917 begin
2918 if ((`ASI_ADDR_9 == 40'h20) || (`ASI_ADDR_9 == 40'h30)
2919 || (`ASI_ADDR_9 == 40'h80)
2920 || ((`ASI_ADDR_9 == 40'ha0) & (`SPU_MA_BUSY_1 == 0) & (`SPU_MA_TID_1 == 1))
2921 )
2922 sync_asi = 1'b1;
2923 end
2924 8'h4C://CLESR, CLFESR access
2925 begin
2926 if ((`ASI_ADDR_9 == 40'h20) || (`ASI_ADDR_9 == 40'h28))
2927 sync_asi = 1'b1;
2928 end
2929 endcase
2930 end
2931
2932 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
2933 begin
2934 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_9, `ASI_ADDR_9, ld_data_w);
2935 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_9, {24'b0, `ASI_ADDR_9}, ld_data_w[63:0]);
2936 end
2937end //}
2938`endif
2939endmodule
2940
2941
2942
2943module err_c1t2 ();
2944`ifndef GATESIM
2945
2946`include "defines.vh"
2947
2948wire [2:0] mycid;
2949wire [2:0] mytid;
2950wire [5:0] mytnum;
2951
2952integer junk;
2953reg ready;
2954reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
2955reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
2956
2957reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
2958reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
2959
2960reg update_dfesr_w;
2961
2962reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
2963reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
2964
2965reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
2966reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
2967
2968reg sync_asi;
2969reg chk_if_asi_ld;
2970reg [63:0] ld_data_w;
2971
2972reg desr_asi_rd, desr_wr, desr_pend_wr;
2973
2974assign mycid = 1;
2975assign mytid = 2;
2976assign mytnum = 1*8 + 2;
2977
2978initial begin //{
2979 desr_asi_rd = 1'b0;
2980 desr_pend_wr = 1'b0;
2981 ready = 0;
2982 @(posedge `SPC1.l2clk) ;
2983 @(posedge `SPC1.l2clk) ;
2984 ready = `PARGS.err_sync_on;
2985end //}
2986
2987`define DSFSR_NEW_IN_10 `SPC1.tlu.ras.dsfsr_2_new_in
2988`define ISFSR_NEW_IN_10 `SPC1.tlu.ras.isfsr_2_new_in
2989
2990`define DSFSR_10 `SPC1.tlu.ras.dsfsr_2
2991`define ISFSR_10 `SPC1.tlu.ras.isfsr_2
2992`define DSFAR_10 `SPC1.tlu.dfd.dsfar_2
2993
2994`define ASI_WR_DSFSR_10 `SPC1.tlu.ras.asi_wr_dsfsr[2]
2995`define ASI_WR_ISFSR_10 `SPC1.tlu.ras.asi_wr_isfsr[2]
2996
2997`define RAS_WRITE_DESR_1st_10 `SPC1.tlu.dfd.ras_write_desr_1st[2]
2998`define RAS_WRITE_DESR_2nd_10 `SPC1.tlu.dfd.ras_write_desr_2nd[2]
2999`define DESR_asi_rd_10 `SPC1.tlu.ras_rd_desr[2]
3000`define DESR_10 `SPC1.tlu.dfd.desr_2
3001
3002`define RAS_WRITE_FESR_10 `SPC1.tlu.ras.write_fesr[2]
3003`define FESR_10 `SPC1.tlu.dfd.fesr_2
3004
3005`define ST_ERR_10 `SPC1.tlu.trl0.take_ftt & `SPC1.tlu.trl0.trap[2]
3006`define SW_REC_ERR_10 `SPC1.tlu.trl0.take_ade & `SPC1.tlu.trl0.trap[2]
3007`define DATA_ACC_ERR_10 `SPC1.tlu.trl0.take_dae & `SPC1.tlu.trl0.trap[2]
3008`define INST_ACC_ERR_10 `SPC1.tlu.trl0.take_iae & `SPC1.tlu.trl0.trap[2]
3009`define INT_PROC_ERR_10 `SPC1.tlu.trl0.take_ipe & `SPC1.tlu.trl0.trap[2]
3010`define HW_CORR_ERR_10 `SPC1.tlu.trl0.take_eer & `SPC1.tlu.trl0.trap[2]
3011`define INST_ACC_MMU_ERR_10 `SPC1.tlu.trl0.take_ime & `SPC1.tlu.trl0.trap[2]
3012`define DATA_ACC_MMU_ERR_10 `SPC1.tlu.trl0.take_dme & `SPC1.tlu.trl0.trap[2]
3013
3014`define LSU_LD_VALID_B `PROBES1.lsu_ld_valid
3015`define LSU_TID_DEC_B_10 `PROBES1.lsu_tid_dec_b[2]
3016`define ASI_LD_10 `SPC1.lsu.lmd.lmq2_pkt[60] & (`SPC1.lsu.lmd.lmq2_pkt[49:48] == 2'b0)
3017`define ASI_10 `SPC1.lsu.lmd.lmq2_pkt[47:40]
3018`define ASI_ADDR_10 `SPC1.lsu.lmd.lmq2_pkt[39:0]
3019`define ASI_LD_DATA_10 `SPC1.lsu_exu_ld_data_b[63:0]
3020`define ASI_LD_COMP_10 tb_top.nas_top.c1.t2.complete_fw2
3021
3022//SPU specific - only one SPU per core
3023`define SPU_MA_BUSY_1 `SPC1.spu.spu_pmu_ma_busy[3]
3024`define SPU_MA_TID_1 `SPC1.spu.spu_pmu_ma_busy[2:0]
3025
3026////////////////////////////////////////////////////////////////////////////////
3027//Capture the status register data from rtl. For disrupting traps,
3028//rtl can modify the contents of the status register before the
3029//trap is taken and intp message is sent to Riesling.
3030//For precise traps, once the status register is updated rtl can't
3031//change the register again before jumping to the trap handler.
3032//So, for deferred and disrupting traps, inform Riesling when the
3033//register is modified while for precise traps wait until Fw2 before
3034//telling Riesling.
3035
3036//TLU asserts the flush and input signals in W stage. I latch them at the
3037//+ve edge of FX4.
3038
3039always @(negedge (`SPC1.l2clk & ready))
3040begin // {
3041 if (`DESR_asi_rd_10)
3042 desr_asi_rd <= 1'b1;
3043 if (desr_asi_rd)
3044 begin
3045 if (desr_wr)
3046 desr_pend_wr <= 1'b1;
3047 if (`ASI_LD_COMP_10[2])
3048 desr_asi_rd <= 1'b0;
3049 end
3050
3051 update_dsfsr_w <= (`DSFSR_NEW_IN_10 != 4'b0) && ~`ASI_WR_DSFSR_10;
3052 update_isfsr_w <= (`ISFSR_NEW_IN_10 != 3'b0) && ~`ASI_WR_ISFSR_10;
3053 desr_wr <= (`RAS_WRITE_DESR_1st_10 || `RAS_WRITE_DESR_2nd_10);
3054 update_dfesr_w <= `RAS_WRITE_FESR_10;
3055 take_err_trap_fx4 <= `ST_ERR_10 | `SW_REC_ERR_10 | `DATA_ACC_ERR_10
3056 | `INST_ACC_ERR_10 | `INT_PROC_ERR_10
3057 | `HW_CORR_ERR_10 | `INST_ACC_MMU_ERR_10
3058 | `DATA_ACC_MMU_ERR_10 ;
3059
3060
3061 if (`ST_ERR_10) int_num_fx4 <= 8'h07;
3062 if (`SW_REC_ERR_10) int_num_fx4 <= 8'h40;
3063 if (`DATA_ACC_ERR_10) int_num_fx4 <= 8'h32;
3064 if (`INST_ACC_ERR_10) int_num_fx4 <= 8'h0A;
3065 if (`INT_PROC_ERR_10) int_num_fx4 <= 8'h29;
3066 if (`HW_CORR_ERR_10) int_num_fx4 <= 8'h63;
3067 if (`INST_ACC_MMU_ERR_10) int_num_fx4 <= 8'h71;
3068 if (`DATA_ACC_MMU_ERR_10) int_num_fx4 <= 8'h72;
3069
3070 update_dsfsr_fx4 <= update_dsfsr_w;
3071 update_dsfsr_fx5 <= update_dsfsr_fx4;
3072 update_dsfsr_fb <= update_dsfsr_fx5;
3073 update_dsfsr_fw <= update_dsfsr_fb;
3074 update_dsfsr_fw1 <= update_dsfsr_fw;
3075 update_dsfsr_fw2 <= update_dsfsr_fw1;
3076
3077 update_isfsr_fx4 <= update_isfsr_w;
3078 update_isfsr_fx5 <= update_isfsr_fx4;
3079 update_isfsr_fb <= update_isfsr_fx5;
3080 update_isfsr_fw <= update_isfsr_fb;
3081 update_isfsr_fw1 <= update_isfsr_fw;
3082 update_isfsr_fw2 <= update_isfsr_fw1;
3083
3084 take_err_trap_fx5 <= take_err_trap_fx4;
3085 take_err_trap_fb <= take_err_trap_fx5;
3086 take_err_trap_fw <= take_err_trap_fb;
3087 take_err_trap_fw1 <= take_err_trap_fw;
3088 take_err_trap_fw2 <= take_err_trap_fw1;
3089
3090 int_num_fx5 <= int_num_fx4;
3091 int_num_fb <= int_num_fx5;
3092 int_num_fw <= int_num_fb;
3093 int_num_fw1 <= int_num_fw;
3094 int_num_fw2 <= int_num_fw1;
3095
3096 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
3097 begin // {
3098 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
3099 begin //{
3100 desr_pend_wr <= 1'b0;
3101 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_10[63:56], 45'b0, `DESR_10[10:0]});
3102 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_10[63:56], 45'b0, `DESR_10[10:0]});
3103 end //}
3104 //if (update_dfesr_w)
3105 if (`ST_ERR_10)
3106 begin //{
3107 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_10[61:55], 55'b0});
3108 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_10[61:55], 55'b0});
3109 end //}
3110 if (update_dsfsr_fw2)
3111 begin //{
3112 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
3113 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_10[3:0]});
3114 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_10[47:0]});
3115
3116 end //}
3117 if (update_isfsr_fw2)
3118 begin //{
3119 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
3120 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_10[2:0]});
3121 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_10[47:0]});
3122
3123 end //}
3124 if (take_err_trap_fw2)
3125 begin //{
3126 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
3127 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
3128 end // }
3129 end // }
3130
3131end //}
3132
3133//removing the addr check as the LSU doesn't flag an invalid_asi_exception
3134//if the addr of diagnostic accesses is not in the valid range. The inst.
3135//still executes. LSU expects that HP won't use addresses in invalid range.
3136
3137always @(negedge (`SPC1.l2clk & ready))
3138begin // {
3139 sync_asi = 1'b0;
3140 ld_data_w <= `ASI_LD_DATA_10;
3141
3142 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_10)
3143 chk_if_asi_ld <= 1'b1;
3144 else
3145 chk_if_asi_ld <= 1'b0;
3146
3147 if (chk_if_asi_ld & `ASI_LD_10)
3148 begin
3149 case (`ASI_10)
3150 8'h66: //ASI_IC_INSTR
3151 begin
3152 //if ((`ASI_ADDR_10 >= 0) & (`ASI_ADDR_10 <= 40'h7ff8))
3153 sync_asi = 1'b1;
3154 end
3155 8'h67: //ASI_IC_TAG
3156 begin
3157 //if ((`ASI_ADDR_10 >= 0) & (`ASI_ADDR_10 <= 40'h7fe0))
3158 sync_asi = 1'b1;
3159 end
3160 8'h46: //ASI_DC_DATA
3161 begin
3162 sync_asi = 1'b1;
3163 end
3164 8'h47: //ASI_DC_TAG
3165 begin
3166 //if ((`ASI_ADDR_10 >= 0) & (`ASI_ADDR_10 <= 40'h7ff0))
3167 sync_asi = 1'b1;
3168 end
3169 8'h48://IRF ECC
3170 begin
3171 //if ((`ASI_ADDR_10 >= 0) & (`ASI_ADDR_10 <= 40'hF8))
3172 sync_asi = 1'b1;
3173 end
3174 8'h49://FRF ECC
3175 begin
3176 //if ((`ASI_ADDR_10 >= 0) & (`ASI_ADDR_10 <= 40'hF8))
3177 sync_asi = 1'b1;
3178 end
3179 8'h4A://STB access, stb ptr can be read also
3180 begin
3181 //if ((`ASI_ADDR_10 >= 0) & (`ASI_ADDR_10 <= 40'h100))
3182 sync_asi = 1'b1;
3183 end
3184 8'h5A://Tick compare reg
3185 begin
3186 //if ((`ASI_ADDR_10 >= 0) & (`ASI_ADDR_10 <= 40'h38))
3187 sync_asi = 1'b1;
3188 end
3189 8'h5B://TSA
3190 begin
3191 //if ((`ASI_ADDR_10 >= 0) & (`ASI_ADDR_10 <= 40'h38))
3192 sync_asi = 1'b1;
3193 end
3194 8'h51://MRA
3195 begin
3196 //if ((`ASI_ADDR_10 >= 0) & (`ASI_ADDR_10 <= 40'h38))
3197 sync_asi = 1'b1;
3198 end
3199 8'h59://scratchpad ecc data read
3200 begin
3201 //if ((`ASI_ADDR_10 >= 0) & (`ASI_ADDR_10 <= 40'h38))
3202 //syncup the ecc data only. For ecc bit 6 is 0.
3203 if (~`SPC1.lsu.lmd.lmq2_pkt[6])
3204 sync_asi = 1'b1;
3205 end
3206 8'h40://cwqcsr,ma_sync access
3207 begin
3208 if ((`ASI_ADDR_10 == 40'h20) || (`ASI_ADDR_10 == 40'h30)
3209 || (`ASI_ADDR_10 == 40'h80)
3210 || ((`ASI_ADDR_10 == 40'ha0) & (`SPU_MA_BUSY_1 == 0) & (`SPU_MA_TID_1 == 2))
3211 )
3212 sync_asi = 1'b1;
3213 end
3214 8'h4C://CLESR, CLFESR access
3215 begin
3216 if ((`ASI_ADDR_10 == 40'h20) || (`ASI_ADDR_10 == 40'h28))
3217 sync_asi = 1'b1;
3218 end
3219 endcase
3220 end
3221
3222 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
3223 begin
3224 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_10, `ASI_ADDR_10, ld_data_w);
3225 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_10, {24'b0, `ASI_ADDR_10}, ld_data_w[63:0]);
3226 end
3227end //}
3228`endif
3229endmodule
3230
3231
3232
3233module err_c1t3 ();
3234`ifndef GATESIM
3235
3236`include "defines.vh"
3237
3238wire [2:0] mycid;
3239wire [2:0] mytid;
3240wire [5:0] mytnum;
3241
3242integer junk;
3243reg ready;
3244reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
3245reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
3246
3247reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
3248reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
3249
3250reg update_dfesr_w;
3251
3252reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
3253reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
3254
3255reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
3256reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
3257
3258reg sync_asi;
3259reg chk_if_asi_ld;
3260reg [63:0] ld_data_w;
3261
3262reg desr_asi_rd, desr_wr, desr_pend_wr;
3263
3264assign mycid = 1;
3265assign mytid = 3;
3266assign mytnum = 1*8 + 3;
3267
3268initial begin //{
3269 desr_asi_rd = 1'b0;
3270 desr_pend_wr = 1'b0;
3271 ready = 0;
3272 @(posedge `SPC1.l2clk) ;
3273 @(posedge `SPC1.l2clk) ;
3274 ready = `PARGS.err_sync_on;
3275end //}
3276
3277`define DSFSR_NEW_IN_11 `SPC1.tlu.ras.dsfsr_3_new_in
3278`define ISFSR_NEW_IN_11 `SPC1.tlu.ras.isfsr_3_new_in
3279
3280`define DSFSR_11 `SPC1.tlu.ras.dsfsr_3
3281`define ISFSR_11 `SPC1.tlu.ras.isfsr_3
3282`define DSFAR_11 `SPC1.tlu.dfd.dsfar_3
3283
3284`define ASI_WR_DSFSR_11 `SPC1.tlu.ras.asi_wr_dsfsr[3]
3285`define ASI_WR_ISFSR_11 `SPC1.tlu.ras.asi_wr_isfsr[3]
3286
3287`define RAS_WRITE_DESR_1st_11 `SPC1.tlu.dfd.ras_write_desr_1st[3]
3288`define RAS_WRITE_DESR_2nd_11 `SPC1.tlu.dfd.ras_write_desr_2nd[3]
3289`define DESR_asi_rd_11 `SPC1.tlu.ras_rd_desr[3]
3290`define DESR_11 `SPC1.tlu.dfd.desr_3
3291
3292`define RAS_WRITE_FESR_11 `SPC1.tlu.ras.write_fesr[3]
3293`define FESR_11 `SPC1.tlu.dfd.fesr_3
3294
3295`define ST_ERR_11 `SPC1.tlu.trl0.take_ftt & `SPC1.tlu.trl0.trap[3]
3296`define SW_REC_ERR_11 `SPC1.tlu.trl0.take_ade & `SPC1.tlu.trl0.trap[3]
3297`define DATA_ACC_ERR_11 `SPC1.tlu.trl0.take_dae & `SPC1.tlu.trl0.trap[3]
3298`define INST_ACC_ERR_11 `SPC1.tlu.trl0.take_iae & `SPC1.tlu.trl0.trap[3]
3299`define INT_PROC_ERR_11 `SPC1.tlu.trl0.take_ipe & `SPC1.tlu.trl0.trap[3]
3300`define HW_CORR_ERR_11 `SPC1.tlu.trl0.take_eer & `SPC1.tlu.trl0.trap[3]
3301`define INST_ACC_MMU_ERR_11 `SPC1.tlu.trl0.take_ime & `SPC1.tlu.trl0.trap[3]
3302`define DATA_ACC_MMU_ERR_11 `SPC1.tlu.trl0.take_dme & `SPC1.tlu.trl0.trap[3]
3303
3304`define LSU_LD_VALID_B `PROBES1.lsu_ld_valid
3305`define LSU_TID_DEC_B_11 `PROBES1.lsu_tid_dec_b[3]
3306`define ASI_LD_11 `SPC1.lsu.lmd.lmq3_pkt[60] & (`SPC1.lsu.lmd.lmq3_pkt[49:48] == 2'b0)
3307`define ASI_11 `SPC1.lsu.lmd.lmq3_pkt[47:40]
3308`define ASI_ADDR_11 `SPC1.lsu.lmd.lmq3_pkt[39:0]
3309`define ASI_LD_DATA_11 `SPC1.lsu_exu_ld_data_b[63:0]
3310`define ASI_LD_COMP_11 tb_top.nas_top.c1.t3.complete_fw2
3311
3312//SPU specific - only one SPU per core
3313`define SPU_MA_BUSY_1 `SPC1.spu.spu_pmu_ma_busy[3]
3314`define SPU_MA_TID_1 `SPC1.spu.spu_pmu_ma_busy[2:0]
3315
3316////////////////////////////////////////////////////////////////////////////////
3317//Capture the status register data from rtl. For disrupting traps,
3318//rtl can modify the contents of the status register before the
3319//trap is taken and intp message is sent to Riesling.
3320//For precise traps, once the status register is updated rtl can't
3321//change the register again before jumping to the trap handler.
3322//So, for deferred and disrupting traps, inform Riesling when the
3323//register is modified while for precise traps wait until Fw2 before
3324//telling Riesling.
3325
3326//TLU asserts the flush and input signals in W stage. I latch them at the
3327//+ve edge of FX4.
3328
3329always @(negedge (`SPC1.l2clk & ready))
3330begin // {
3331 if (`DESR_asi_rd_11)
3332 desr_asi_rd <= 1'b1;
3333 if (desr_asi_rd)
3334 begin
3335 if (desr_wr)
3336 desr_pend_wr <= 1'b1;
3337 if (`ASI_LD_COMP_11[2])
3338 desr_asi_rd <= 1'b0;
3339 end
3340
3341 update_dsfsr_w <= (`DSFSR_NEW_IN_11 != 4'b0) && ~`ASI_WR_DSFSR_11;
3342 update_isfsr_w <= (`ISFSR_NEW_IN_11 != 3'b0) && ~`ASI_WR_ISFSR_11;
3343 desr_wr <= (`RAS_WRITE_DESR_1st_11 || `RAS_WRITE_DESR_2nd_11);
3344 update_dfesr_w <= `RAS_WRITE_FESR_11;
3345 take_err_trap_fx4 <= `ST_ERR_11 | `SW_REC_ERR_11 | `DATA_ACC_ERR_11
3346 | `INST_ACC_ERR_11 | `INT_PROC_ERR_11
3347 | `HW_CORR_ERR_11 | `INST_ACC_MMU_ERR_11
3348 | `DATA_ACC_MMU_ERR_11 ;
3349
3350
3351 if (`ST_ERR_11) int_num_fx4 <= 8'h07;
3352 if (`SW_REC_ERR_11) int_num_fx4 <= 8'h40;
3353 if (`DATA_ACC_ERR_11) int_num_fx4 <= 8'h32;
3354 if (`INST_ACC_ERR_11) int_num_fx4 <= 8'h0A;
3355 if (`INT_PROC_ERR_11) int_num_fx4 <= 8'h29;
3356 if (`HW_CORR_ERR_11) int_num_fx4 <= 8'h63;
3357 if (`INST_ACC_MMU_ERR_11) int_num_fx4 <= 8'h71;
3358 if (`DATA_ACC_MMU_ERR_11) int_num_fx4 <= 8'h72;
3359
3360 update_dsfsr_fx4 <= update_dsfsr_w;
3361 update_dsfsr_fx5 <= update_dsfsr_fx4;
3362 update_dsfsr_fb <= update_dsfsr_fx5;
3363 update_dsfsr_fw <= update_dsfsr_fb;
3364 update_dsfsr_fw1 <= update_dsfsr_fw;
3365 update_dsfsr_fw2 <= update_dsfsr_fw1;
3366
3367 update_isfsr_fx4 <= update_isfsr_w;
3368 update_isfsr_fx5 <= update_isfsr_fx4;
3369 update_isfsr_fb <= update_isfsr_fx5;
3370 update_isfsr_fw <= update_isfsr_fb;
3371 update_isfsr_fw1 <= update_isfsr_fw;
3372 update_isfsr_fw2 <= update_isfsr_fw1;
3373
3374 take_err_trap_fx5 <= take_err_trap_fx4;
3375 take_err_trap_fb <= take_err_trap_fx5;
3376 take_err_trap_fw <= take_err_trap_fb;
3377 take_err_trap_fw1 <= take_err_trap_fw;
3378 take_err_trap_fw2 <= take_err_trap_fw1;
3379
3380 int_num_fx5 <= int_num_fx4;
3381 int_num_fb <= int_num_fx5;
3382 int_num_fw <= int_num_fb;
3383 int_num_fw1 <= int_num_fw;
3384 int_num_fw2 <= int_num_fw1;
3385
3386 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
3387 begin // {
3388 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
3389 begin //{
3390 desr_pend_wr <= 1'b0;
3391 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_11[63:56], 45'b0, `DESR_11[10:0]});
3392 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_11[63:56], 45'b0, `DESR_11[10:0]});
3393 end //}
3394 //if (update_dfesr_w)
3395 if (`ST_ERR_11)
3396 begin //{
3397 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_11[61:55], 55'b0});
3398 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_11[61:55], 55'b0});
3399 end //}
3400 if (update_dsfsr_fw2)
3401 begin //{
3402 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
3403 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_11[3:0]});
3404 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_11[47:0]});
3405
3406 end //}
3407 if (update_isfsr_fw2)
3408 begin //{
3409 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
3410 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_11[2:0]});
3411 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_11[47:0]});
3412
3413 end //}
3414 if (take_err_trap_fw2)
3415 begin //{
3416 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
3417 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
3418 end // }
3419 end // }
3420
3421end //}
3422
3423//removing the addr check as the LSU doesn't flag an invalid_asi_exception
3424//if the addr of diagnostic accesses is not in the valid range. The inst.
3425//still executes. LSU expects that HP won't use addresses in invalid range.
3426
3427always @(negedge (`SPC1.l2clk & ready))
3428begin // {
3429 sync_asi = 1'b0;
3430 ld_data_w <= `ASI_LD_DATA_11;
3431
3432 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_11)
3433 chk_if_asi_ld <= 1'b1;
3434 else
3435 chk_if_asi_ld <= 1'b0;
3436
3437 if (chk_if_asi_ld & `ASI_LD_11)
3438 begin
3439 case (`ASI_11)
3440 8'h66: //ASI_IC_INSTR
3441 begin
3442 //if ((`ASI_ADDR_11 >= 0) & (`ASI_ADDR_11 <= 40'h7ff8))
3443 sync_asi = 1'b1;
3444 end
3445 8'h67: //ASI_IC_TAG
3446 begin
3447 //if ((`ASI_ADDR_11 >= 0) & (`ASI_ADDR_11 <= 40'h7fe0))
3448 sync_asi = 1'b1;
3449 end
3450 8'h46: //ASI_DC_DATA
3451 begin
3452 sync_asi = 1'b1;
3453 end
3454 8'h47: //ASI_DC_TAG
3455 begin
3456 //if ((`ASI_ADDR_11 >= 0) & (`ASI_ADDR_11 <= 40'h7ff0))
3457 sync_asi = 1'b1;
3458 end
3459 8'h48://IRF ECC
3460 begin
3461 //if ((`ASI_ADDR_11 >= 0) & (`ASI_ADDR_11 <= 40'hF8))
3462 sync_asi = 1'b1;
3463 end
3464 8'h49://FRF ECC
3465 begin
3466 //if ((`ASI_ADDR_11 >= 0) & (`ASI_ADDR_11 <= 40'hF8))
3467 sync_asi = 1'b1;
3468 end
3469 8'h4A://STB access, stb ptr can be read also
3470 begin
3471 //if ((`ASI_ADDR_11 >= 0) & (`ASI_ADDR_11 <= 40'h100))
3472 sync_asi = 1'b1;
3473 end
3474 8'h5A://Tick compare reg
3475 begin
3476 //if ((`ASI_ADDR_11 >= 0) & (`ASI_ADDR_11 <= 40'h38))
3477 sync_asi = 1'b1;
3478 end
3479 8'h5B://TSA
3480 begin
3481 //if ((`ASI_ADDR_11 >= 0) & (`ASI_ADDR_11 <= 40'h38))
3482 sync_asi = 1'b1;
3483 end
3484 8'h51://MRA
3485 begin
3486 //if ((`ASI_ADDR_11 >= 0) & (`ASI_ADDR_11 <= 40'h38))
3487 sync_asi = 1'b1;
3488 end
3489 8'h59://scratchpad ecc data read
3490 begin
3491 //if ((`ASI_ADDR_11 >= 0) & (`ASI_ADDR_11 <= 40'h38))
3492 //syncup the ecc data only. For ecc bit 6 is 0.
3493 if (~`SPC1.lsu.lmd.lmq3_pkt[6])
3494 sync_asi = 1'b1;
3495 end
3496 8'h40://cwqcsr,ma_sync access
3497 begin
3498 if ((`ASI_ADDR_11 == 40'h20) || (`ASI_ADDR_11 == 40'h30)
3499 || (`ASI_ADDR_11 == 40'h80)
3500 || ((`ASI_ADDR_11 == 40'ha0) & (`SPU_MA_BUSY_1 == 0) & (`SPU_MA_TID_1 == 3))
3501 )
3502 sync_asi = 1'b1;
3503 end
3504 8'h4C://CLESR, CLFESR access
3505 begin
3506 if ((`ASI_ADDR_11 == 40'h20) || (`ASI_ADDR_11 == 40'h28))
3507 sync_asi = 1'b1;
3508 end
3509 endcase
3510 end
3511
3512 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
3513 begin
3514 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_11, `ASI_ADDR_11, ld_data_w);
3515 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_11, {24'b0, `ASI_ADDR_11}, ld_data_w[63:0]);
3516 end
3517end //}
3518`endif
3519endmodule
3520
3521
3522
3523module err_c1t4 ();
3524`ifndef GATESIM
3525
3526`include "defines.vh"
3527
3528wire [2:0] mycid;
3529wire [2:0] mytid;
3530wire [5:0] mytnum;
3531
3532integer junk;
3533reg ready;
3534reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
3535reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
3536
3537reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
3538reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
3539
3540reg update_dfesr_w;
3541
3542reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
3543reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
3544
3545reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
3546reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
3547
3548reg sync_asi;
3549reg chk_if_asi_ld;
3550reg [63:0] ld_data_w;
3551
3552reg desr_asi_rd, desr_wr, desr_pend_wr;
3553
3554assign mycid = 1;
3555assign mytid = 4;
3556assign mytnum = 1*8 + 4;
3557
3558initial begin //{
3559 desr_asi_rd = 1'b0;
3560 desr_pend_wr = 1'b0;
3561 ready = 0;
3562 @(posedge `SPC1.l2clk) ;
3563 @(posedge `SPC1.l2clk) ;
3564 ready = `PARGS.err_sync_on;
3565end //}
3566
3567`define DSFSR_NEW_IN_12 `SPC1.tlu.ras.dsfsr_4_new_in
3568`define ISFSR_NEW_IN_12 `SPC1.tlu.ras.isfsr_4_new_in
3569
3570`define DSFSR_12 `SPC1.tlu.ras.dsfsr_4
3571`define ISFSR_12 `SPC1.tlu.ras.isfsr_4
3572`define DSFAR_12 `SPC1.tlu.dfd.dsfar_4
3573
3574`define ASI_WR_DSFSR_12 `SPC1.tlu.ras.asi_wr_dsfsr[4]
3575`define ASI_WR_ISFSR_12 `SPC1.tlu.ras.asi_wr_isfsr[4]
3576
3577`define RAS_WRITE_DESR_1st_12 `SPC1.tlu.dfd.ras_write_desr_1st[4]
3578`define RAS_WRITE_DESR_2nd_12 `SPC1.tlu.dfd.ras_write_desr_2nd[4]
3579`define DESR_asi_rd_12 `SPC1.tlu.ras_rd_desr[4]
3580`define DESR_12 `SPC1.tlu.dfd.desr_4
3581
3582`define RAS_WRITE_FESR_12 `SPC1.tlu.ras.write_fesr[4]
3583`define FESR_12 `SPC1.tlu.dfd.fesr_4
3584
3585`define ST_ERR_12 `SPC1.tlu.trl1.take_ftt & `SPC1.tlu.trl1.trap[0]
3586`define SW_REC_ERR_12 `SPC1.tlu.trl1.take_ade & `SPC1.tlu.trl1.trap[0]
3587`define DATA_ACC_ERR_12 `SPC1.tlu.trl1.take_dae & `SPC1.tlu.trl1.trap[0]
3588`define INST_ACC_ERR_12 `SPC1.tlu.trl1.take_iae & `SPC1.tlu.trl1.trap[0]
3589`define INT_PROC_ERR_12 `SPC1.tlu.trl1.take_ipe & `SPC1.tlu.trl1.trap[0]
3590`define HW_CORR_ERR_12 `SPC1.tlu.trl1.take_eer & `SPC1.tlu.trl1.trap[0]
3591`define INST_ACC_MMU_ERR_12 `SPC1.tlu.trl1.take_ime & `SPC1.tlu.trl1.trap[0]
3592`define DATA_ACC_MMU_ERR_12 `SPC1.tlu.trl1.take_dme & `SPC1.tlu.trl1.trap[0]
3593
3594`define LSU_LD_VALID_B `PROBES1.lsu_ld_valid
3595`define LSU_TID_DEC_B_12 `PROBES1.lsu_tid_dec_b[4]
3596`define ASI_LD_12 `SPC1.lsu.lmd.lmq4_pkt[60] & (`SPC1.lsu.lmd.lmq4_pkt[49:48] == 2'b0)
3597`define ASI_12 `SPC1.lsu.lmd.lmq4_pkt[47:40]
3598`define ASI_ADDR_12 `SPC1.lsu.lmd.lmq4_pkt[39:0]
3599`define ASI_LD_DATA_12 `SPC1.lsu_exu_ld_data_b[63:0]
3600`define ASI_LD_COMP_12 tb_top.nas_top.c1.t4.complete_fw2
3601
3602//SPU specific - only one SPU per core
3603`define SPU_MA_BUSY_1 `SPC1.spu.spu_pmu_ma_busy[3]
3604`define SPU_MA_TID_1 `SPC1.spu.spu_pmu_ma_busy[2:0]
3605
3606////////////////////////////////////////////////////////////////////////////////
3607//Capture the status register data from rtl. For disrupting traps,
3608//rtl can modify the contents of the status register before the
3609//trap is taken and intp message is sent to Riesling.
3610//For precise traps, once the status register is updated rtl can't
3611//change the register again before jumping to the trap handler.
3612//So, for deferred and disrupting traps, inform Riesling when the
3613//register is modified while for precise traps wait until Fw2 before
3614//telling Riesling.
3615
3616//TLU asserts the flush and input signals in W stage. I latch them at the
3617//+ve edge of FX4.
3618
3619always @(negedge (`SPC1.l2clk & ready))
3620begin // {
3621 if (`DESR_asi_rd_12)
3622 desr_asi_rd <= 1'b1;
3623 if (desr_asi_rd)
3624 begin
3625 if (desr_wr)
3626 desr_pend_wr <= 1'b1;
3627 if (`ASI_LD_COMP_12[2])
3628 desr_asi_rd <= 1'b0;
3629 end
3630
3631 update_dsfsr_w <= (`DSFSR_NEW_IN_12 != 4'b0) && ~`ASI_WR_DSFSR_12;
3632 update_isfsr_w <= (`ISFSR_NEW_IN_12 != 3'b0) && ~`ASI_WR_ISFSR_12;
3633 desr_wr <= (`RAS_WRITE_DESR_1st_12 || `RAS_WRITE_DESR_2nd_12);
3634 update_dfesr_w <= `RAS_WRITE_FESR_12;
3635 take_err_trap_fx4 <= `ST_ERR_12 | `SW_REC_ERR_12 | `DATA_ACC_ERR_12
3636 | `INST_ACC_ERR_12 | `INT_PROC_ERR_12
3637 | `HW_CORR_ERR_12 | `INST_ACC_MMU_ERR_12
3638 | `DATA_ACC_MMU_ERR_12 ;
3639
3640
3641 if (`ST_ERR_12) int_num_fx4 <= 8'h07;
3642 if (`SW_REC_ERR_12) int_num_fx4 <= 8'h40;
3643 if (`DATA_ACC_ERR_12) int_num_fx4 <= 8'h32;
3644 if (`INST_ACC_ERR_12) int_num_fx4 <= 8'h0A;
3645 if (`INT_PROC_ERR_12) int_num_fx4 <= 8'h29;
3646 if (`HW_CORR_ERR_12) int_num_fx4 <= 8'h63;
3647 if (`INST_ACC_MMU_ERR_12) int_num_fx4 <= 8'h71;
3648 if (`DATA_ACC_MMU_ERR_12) int_num_fx4 <= 8'h72;
3649
3650 update_dsfsr_fx4 <= update_dsfsr_w;
3651 update_dsfsr_fx5 <= update_dsfsr_fx4;
3652 update_dsfsr_fb <= update_dsfsr_fx5;
3653 update_dsfsr_fw <= update_dsfsr_fb;
3654 update_dsfsr_fw1 <= update_dsfsr_fw;
3655 update_dsfsr_fw2 <= update_dsfsr_fw1;
3656
3657 update_isfsr_fx4 <= update_isfsr_w;
3658 update_isfsr_fx5 <= update_isfsr_fx4;
3659 update_isfsr_fb <= update_isfsr_fx5;
3660 update_isfsr_fw <= update_isfsr_fb;
3661 update_isfsr_fw1 <= update_isfsr_fw;
3662 update_isfsr_fw2 <= update_isfsr_fw1;
3663
3664 take_err_trap_fx5 <= take_err_trap_fx4;
3665 take_err_trap_fb <= take_err_trap_fx5;
3666 take_err_trap_fw <= take_err_trap_fb;
3667 take_err_trap_fw1 <= take_err_trap_fw;
3668 take_err_trap_fw2 <= take_err_trap_fw1;
3669
3670 int_num_fx5 <= int_num_fx4;
3671 int_num_fb <= int_num_fx5;
3672 int_num_fw <= int_num_fb;
3673 int_num_fw1 <= int_num_fw;
3674 int_num_fw2 <= int_num_fw1;
3675
3676 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
3677 begin // {
3678 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
3679 begin //{
3680 desr_pend_wr <= 1'b0;
3681 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_12[63:56], 45'b0, `DESR_12[10:0]});
3682 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_12[63:56], 45'b0, `DESR_12[10:0]});
3683 end //}
3684 //if (update_dfesr_w)
3685 if (`ST_ERR_12)
3686 begin //{
3687 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_12[61:55], 55'b0});
3688 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_12[61:55], 55'b0});
3689 end //}
3690 if (update_dsfsr_fw2)
3691 begin //{
3692 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
3693 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_12[3:0]});
3694 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_12[47:0]});
3695
3696 end //}
3697 if (update_isfsr_fw2)
3698 begin //{
3699 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
3700 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_12[2:0]});
3701 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_12[47:0]});
3702
3703 end //}
3704 if (take_err_trap_fw2)
3705 begin //{
3706 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
3707 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
3708 end // }
3709 end // }
3710
3711end //}
3712
3713//removing the addr check as the LSU doesn't flag an invalid_asi_exception
3714//if the addr of diagnostic accesses is not in the valid range. The inst.
3715//still executes. LSU expects that HP won't use addresses in invalid range.
3716
3717always @(negedge (`SPC1.l2clk & ready))
3718begin // {
3719 sync_asi = 1'b0;
3720 ld_data_w <= `ASI_LD_DATA_12;
3721
3722 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_12)
3723 chk_if_asi_ld <= 1'b1;
3724 else
3725 chk_if_asi_ld <= 1'b0;
3726
3727 if (chk_if_asi_ld & `ASI_LD_12)
3728 begin
3729 case (`ASI_12)
3730 8'h66: //ASI_IC_INSTR
3731 begin
3732 //if ((`ASI_ADDR_12 >= 0) & (`ASI_ADDR_12 <= 40'h7ff8))
3733 sync_asi = 1'b1;
3734 end
3735 8'h67: //ASI_IC_TAG
3736 begin
3737 //if ((`ASI_ADDR_12 >= 0) & (`ASI_ADDR_12 <= 40'h7fe0))
3738 sync_asi = 1'b1;
3739 end
3740 8'h46: //ASI_DC_DATA
3741 begin
3742 sync_asi = 1'b1;
3743 end
3744 8'h47: //ASI_DC_TAG
3745 begin
3746 //if ((`ASI_ADDR_12 >= 0) & (`ASI_ADDR_12 <= 40'h7ff0))
3747 sync_asi = 1'b1;
3748 end
3749 8'h48://IRF ECC
3750 begin
3751 //if ((`ASI_ADDR_12 >= 0) & (`ASI_ADDR_12 <= 40'hF8))
3752 sync_asi = 1'b1;
3753 end
3754 8'h49://FRF ECC
3755 begin
3756 //if ((`ASI_ADDR_12 >= 0) & (`ASI_ADDR_12 <= 40'hF8))
3757 sync_asi = 1'b1;
3758 end
3759 8'h4A://STB access, stb ptr can be read also
3760 begin
3761 //if ((`ASI_ADDR_12 >= 0) & (`ASI_ADDR_12 <= 40'h100))
3762 sync_asi = 1'b1;
3763 end
3764 8'h5A://Tick compare reg
3765 begin
3766 //if ((`ASI_ADDR_12 >= 0) & (`ASI_ADDR_12 <= 40'h38))
3767 sync_asi = 1'b1;
3768 end
3769 8'h5B://TSA
3770 begin
3771 //if ((`ASI_ADDR_12 >= 0) & (`ASI_ADDR_12 <= 40'h38))
3772 sync_asi = 1'b1;
3773 end
3774 8'h51://MRA
3775 begin
3776 //if ((`ASI_ADDR_12 >= 0) & (`ASI_ADDR_12 <= 40'h38))
3777 sync_asi = 1'b1;
3778 end
3779 8'h59://scratchpad ecc data read
3780 begin
3781 //if ((`ASI_ADDR_12 >= 0) & (`ASI_ADDR_12 <= 40'h38))
3782 //syncup the ecc data only. For ecc bit 6 is 0.
3783 if (~`SPC1.lsu.lmd.lmq4_pkt[6])
3784 sync_asi = 1'b1;
3785 end
3786 8'h40://cwqcsr,ma_sync access
3787 begin
3788 if ((`ASI_ADDR_12 == 40'h20) || (`ASI_ADDR_12 == 40'h30)
3789 || (`ASI_ADDR_12 == 40'h80)
3790 || ((`ASI_ADDR_12 == 40'ha0) & (`SPU_MA_BUSY_1 == 0) & (`SPU_MA_TID_1 == 4))
3791 )
3792 sync_asi = 1'b1;
3793 end
3794 8'h4C://CLESR, CLFESR access
3795 begin
3796 if ((`ASI_ADDR_12 == 40'h20) || (`ASI_ADDR_12 == 40'h28))
3797 sync_asi = 1'b1;
3798 end
3799 endcase
3800 end
3801
3802 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
3803 begin
3804 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_12, `ASI_ADDR_12, ld_data_w);
3805 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_12, {24'b0, `ASI_ADDR_12}, ld_data_w[63:0]);
3806 end
3807end //}
3808`endif
3809endmodule
3810
3811
3812
3813module err_c1t5 ();
3814`ifndef GATESIM
3815
3816`include "defines.vh"
3817
3818wire [2:0] mycid;
3819wire [2:0] mytid;
3820wire [5:0] mytnum;
3821
3822integer junk;
3823reg ready;
3824reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
3825reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
3826
3827reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
3828reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
3829
3830reg update_dfesr_w;
3831
3832reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
3833reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
3834
3835reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
3836reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
3837
3838reg sync_asi;
3839reg chk_if_asi_ld;
3840reg [63:0] ld_data_w;
3841
3842reg desr_asi_rd, desr_wr, desr_pend_wr;
3843
3844assign mycid = 1;
3845assign mytid = 5;
3846assign mytnum = 1*8 + 5;
3847
3848initial begin //{
3849 desr_asi_rd = 1'b0;
3850 desr_pend_wr = 1'b0;
3851 ready = 0;
3852 @(posedge `SPC1.l2clk) ;
3853 @(posedge `SPC1.l2clk) ;
3854 ready = `PARGS.err_sync_on;
3855end //}
3856
3857`define DSFSR_NEW_IN_13 `SPC1.tlu.ras.dsfsr_5_new_in
3858`define ISFSR_NEW_IN_13 `SPC1.tlu.ras.isfsr_5_new_in
3859
3860`define DSFSR_13 `SPC1.tlu.ras.dsfsr_5
3861`define ISFSR_13 `SPC1.tlu.ras.isfsr_5
3862`define DSFAR_13 `SPC1.tlu.dfd.dsfar_5
3863
3864`define ASI_WR_DSFSR_13 `SPC1.tlu.ras.asi_wr_dsfsr[5]
3865`define ASI_WR_ISFSR_13 `SPC1.tlu.ras.asi_wr_isfsr[5]
3866
3867`define RAS_WRITE_DESR_1st_13 `SPC1.tlu.dfd.ras_write_desr_1st[5]
3868`define RAS_WRITE_DESR_2nd_13 `SPC1.tlu.dfd.ras_write_desr_2nd[5]
3869`define DESR_asi_rd_13 `SPC1.tlu.ras_rd_desr[5]
3870`define DESR_13 `SPC1.tlu.dfd.desr_5
3871
3872`define RAS_WRITE_FESR_13 `SPC1.tlu.ras.write_fesr[5]
3873`define FESR_13 `SPC1.tlu.dfd.fesr_5
3874
3875`define ST_ERR_13 `SPC1.tlu.trl1.take_ftt & `SPC1.tlu.trl1.trap[1]
3876`define SW_REC_ERR_13 `SPC1.tlu.trl1.take_ade & `SPC1.tlu.trl1.trap[1]
3877`define DATA_ACC_ERR_13 `SPC1.tlu.trl1.take_dae & `SPC1.tlu.trl1.trap[1]
3878`define INST_ACC_ERR_13 `SPC1.tlu.trl1.take_iae & `SPC1.tlu.trl1.trap[1]
3879`define INT_PROC_ERR_13 `SPC1.tlu.trl1.take_ipe & `SPC1.tlu.trl1.trap[1]
3880`define HW_CORR_ERR_13 `SPC1.tlu.trl1.take_eer & `SPC1.tlu.trl1.trap[1]
3881`define INST_ACC_MMU_ERR_13 `SPC1.tlu.trl1.take_ime & `SPC1.tlu.trl1.trap[1]
3882`define DATA_ACC_MMU_ERR_13 `SPC1.tlu.trl1.take_dme & `SPC1.tlu.trl1.trap[1]
3883
3884`define LSU_LD_VALID_B `PROBES1.lsu_ld_valid
3885`define LSU_TID_DEC_B_13 `PROBES1.lsu_tid_dec_b[5]
3886`define ASI_LD_13 `SPC1.lsu.lmd.lmq5_pkt[60] & (`SPC1.lsu.lmd.lmq5_pkt[49:48] == 2'b0)
3887`define ASI_13 `SPC1.lsu.lmd.lmq5_pkt[47:40]
3888`define ASI_ADDR_13 `SPC1.lsu.lmd.lmq5_pkt[39:0]
3889`define ASI_LD_DATA_13 `SPC1.lsu_exu_ld_data_b[63:0]
3890`define ASI_LD_COMP_13 tb_top.nas_top.c1.t5.complete_fw2
3891
3892//SPU specific - only one SPU per core
3893`define SPU_MA_BUSY_1 `SPC1.spu.spu_pmu_ma_busy[3]
3894`define SPU_MA_TID_1 `SPC1.spu.spu_pmu_ma_busy[2:0]
3895
3896////////////////////////////////////////////////////////////////////////////////
3897//Capture the status register data from rtl. For disrupting traps,
3898//rtl can modify the contents of the status register before the
3899//trap is taken and intp message is sent to Riesling.
3900//For precise traps, once the status register is updated rtl can't
3901//change the register again before jumping to the trap handler.
3902//So, for deferred and disrupting traps, inform Riesling when the
3903//register is modified while for precise traps wait until Fw2 before
3904//telling Riesling.
3905
3906//TLU asserts the flush and input signals in W stage. I latch them at the
3907//+ve edge of FX4.
3908
3909always @(negedge (`SPC1.l2clk & ready))
3910begin // {
3911 if (`DESR_asi_rd_13)
3912 desr_asi_rd <= 1'b1;
3913 if (desr_asi_rd)
3914 begin
3915 if (desr_wr)
3916 desr_pend_wr <= 1'b1;
3917 if (`ASI_LD_COMP_13[2])
3918 desr_asi_rd <= 1'b0;
3919 end
3920
3921 update_dsfsr_w <= (`DSFSR_NEW_IN_13 != 4'b0) && ~`ASI_WR_DSFSR_13;
3922 update_isfsr_w <= (`ISFSR_NEW_IN_13 != 3'b0) && ~`ASI_WR_ISFSR_13;
3923 desr_wr <= (`RAS_WRITE_DESR_1st_13 || `RAS_WRITE_DESR_2nd_13);
3924 update_dfesr_w <= `RAS_WRITE_FESR_13;
3925 take_err_trap_fx4 <= `ST_ERR_13 | `SW_REC_ERR_13 | `DATA_ACC_ERR_13
3926 | `INST_ACC_ERR_13 | `INT_PROC_ERR_13
3927 | `HW_CORR_ERR_13 | `INST_ACC_MMU_ERR_13
3928 | `DATA_ACC_MMU_ERR_13 ;
3929
3930
3931 if (`ST_ERR_13) int_num_fx4 <= 8'h07;
3932 if (`SW_REC_ERR_13) int_num_fx4 <= 8'h40;
3933 if (`DATA_ACC_ERR_13) int_num_fx4 <= 8'h32;
3934 if (`INST_ACC_ERR_13) int_num_fx4 <= 8'h0A;
3935 if (`INT_PROC_ERR_13) int_num_fx4 <= 8'h29;
3936 if (`HW_CORR_ERR_13) int_num_fx4 <= 8'h63;
3937 if (`INST_ACC_MMU_ERR_13) int_num_fx4 <= 8'h71;
3938 if (`DATA_ACC_MMU_ERR_13) int_num_fx4 <= 8'h72;
3939
3940 update_dsfsr_fx4 <= update_dsfsr_w;
3941 update_dsfsr_fx5 <= update_dsfsr_fx4;
3942 update_dsfsr_fb <= update_dsfsr_fx5;
3943 update_dsfsr_fw <= update_dsfsr_fb;
3944 update_dsfsr_fw1 <= update_dsfsr_fw;
3945 update_dsfsr_fw2 <= update_dsfsr_fw1;
3946
3947 update_isfsr_fx4 <= update_isfsr_w;
3948 update_isfsr_fx5 <= update_isfsr_fx4;
3949 update_isfsr_fb <= update_isfsr_fx5;
3950 update_isfsr_fw <= update_isfsr_fb;
3951 update_isfsr_fw1 <= update_isfsr_fw;
3952 update_isfsr_fw2 <= update_isfsr_fw1;
3953
3954 take_err_trap_fx5 <= take_err_trap_fx4;
3955 take_err_trap_fb <= take_err_trap_fx5;
3956 take_err_trap_fw <= take_err_trap_fb;
3957 take_err_trap_fw1 <= take_err_trap_fw;
3958 take_err_trap_fw2 <= take_err_trap_fw1;
3959
3960 int_num_fx5 <= int_num_fx4;
3961 int_num_fb <= int_num_fx5;
3962 int_num_fw <= int_num_fb;
3963 int_num_fw1 <= int_num_fw;
3964 int_num_fw2 <= int_num_fw1;
3965
3966 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
3967 begin // {
3968 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
3969 begin //{
3970 desr_pend_wr <= 1'b0;
3971 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_13[63:56], 45'b0, `DESR_13[10:0]});
3972 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_13[63:56], 45'b0, `DESR_13[10:0]});
3973 end //}
3974 //if (update_dfesr_w)
3975 if (`ST_ERR_13)
3976 begin //{
3977 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_13[61:55], 55'b0});
3978 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_13[61:55], 55'b0});
3979 end //}
3980 if (update_dsfsr_fw2)
3981 begin //{
3982 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
3983 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_13[3:0]});
3984 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_13[47:0]});
3985
3986 end //}
3987 if (update_isfsr_fw2)
3988 begin //{
3989 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
3990 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_13[2:0]});
3991 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_13[47:0]});
3992
3993 end //}
3994 if (take_err_trap_fw2)
3995 begin //{
3996 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
3997 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
3998 end // }
3999 end // }
4000
4001end //}
4002
4003//removing the addr check as the LSU doesn't flag an invalid_asi_exception
4004//if the addr of diagnostic accesses is not in the valid range. The inst.
4005//still executes. LSU expects that HP won't use addresses in invalid range.
4006
4007always @(negedge (`SPC1.l2clk & ready))
4008begin // {
4009 sync_asi = 1'b0;
4010 ld_data_w <= `ASI_LD_DATA_13;
4011
4012 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_13)
4013 chk_if_asi_ld <= 1'b1;
4014 else
4015 chk_if_asi_ld <= 1'b0;
4016
4017 if (chk_if_asi_ld & `ASI_LD_13)
4018 begin
4019 case (`ASI_13)
4020 8'h66: //ASI_IC_INSTR
4021 begin
4022 //if ((`ASI_ADDR_13 >= 0) & (`ASI_ADDR_13 <= 40'h7ff8))
4023 sync_asi = 1'b1;
4024 end
4025 8'h67: //ASI_IC_TAG
4026 begin
4027 //if ((`ASI_ADDR_13 >= 0) & (`ASI_ADDR_13 <= 40'h7fe0))
4028 sync_asi = 1'b1;
4029 end
4030 8'h46: //ASI_DC_DATA
4031 begin
4032 sync_asi = 1'b1;
4033 end
4034 8'h47: //ASI_DC_TAG
4035 begin
4036 //if ((`ASI_ADDR_13 >= 0) & (`ASI_ADDR_13 <= 40'h7ff0))
4037 sync_asi = 1'b1;
4038 end
4039 8'h48://IRF ECC
4040 begin
4041 //if ((`ASI_ADDR_13 >= 0) & (`ASI_ADDR_13 <= 40'hF8))
4042 sync_asi = 1'b1;
4043 end
4044 8'h49://FRF ECC
4045 begin
4046 //if ((`ASI_ADDR_13 >= 0) & (`ASI_ADDR_13 <= 40'hF8))
4047 sync_asi = 1'b1;
4048 end
4049 8'h4A://STB access, stb ptr can be read also
4050 begin
4051 //if ((`ASI_ADDR_13 >= 0) & (`ASI_ADDR_13 <= 40'h100))
4052 sync_asi = 1'b1;
4053 end
4054 8'h5A://Tick compare reg
4055 begin
4056 //if ((`ASI_ADDR_13 >= 0) & (`ASI_ADDR_13 <= 40'h38))
4057 sync_asi = 1'b1;
4058 end
4059 8'h5B://TSA
4060 begin
4061 //if ((`ASI_ADDR_13 >= 0) & (`ASI_ADDR_13 <= 40'h38))
4062 sync_asi = 1'b1;
4063 end
4064 8'h51://MRA
4065 begin
4066 //if ((`ASI_ADDR_13 >= 0) & (`ASI_ADDR_13 <= 40'h38))
4067 sync_asi = 1'b1;
4068 end
4069 8'h59://scratchpad ecc data read
4070 begin
4071 //if ((`ASI_ADDR_13 >= 0) & (`ASI_ADDR_13 <= 40'h38))
4072 //syncup the ecc data only. For ecc bit 6 is 0.
4073 if (~`SPC1.lsu.lmd.lmq5_pkt[6])
4074 sync_asi = 1'b1;
4075 end
4076 8'h40://cwqcsr,ma_sync access
4077 begin
4078 if ((`ASI_ADDR_13 == 40'h20) || (`ASI_ADDR_13 == 40'h30)
4079 || (`ASI_ADDR_13 == 40'h80)
4080 || ((`ASI_ADDR_13 == 40'ha0) & (`SPU_MA_BUSY_1 == 0) & (`SPU_MA_TID_1 == 5))
4081 )
4082 sync_asi = 1'b1;
4083 end
4084 8'h4C://CLESR, CLFESR access
4085 begin
4086 if ((`ASI_ADDR_13 == 40'h20) || (`ASI_ADDR_13 == 40'h28))
4087 sync_asi = 1'b1;
4088 end
4089 endcase
4090 end
4091
4092 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
4093 begin
4094 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_13, `ASI_ADDR_13, ld_data_w);
4095 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_13, {24'b0, `ASI_ADDR_13}, ld_data_w[63:0]);
4096 end
4097end //}
4098`endif
4099endmodule
4100
4101
4102
4103module err_c1t6 ();
4104`ifndef GATESIM
4105
4106`include "defines.vh"
4107
4108wire [2:0] mycid;
4109wire [2:0] mytid;
4110wire [5:0] mytnum;
4111
4112integer junk;
4113reg ready;
4114reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
4115reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
4116
4117reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
4118reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
4119
4120reg update_dfesr_w;
4121
4122reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
4123reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
4124
4125reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
4126reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
4127
4128reg sync_asi;
4129reg chk_if_asi_ld;
4130reg [63:0] ld_data_w;
4131
4132reg desr_asi_rd, desr_wr, desr_pend_wr;
4133
4134assign mycid = 1;
4135assign mytid = 6;
4136assign mytnum = 1*8 + 6;
4137
4138initial begin //{
4139 desr_asi_rd = 1'b0;
4140 desr_pend_wr = 1'b0;
4141 ready = 0;
4142 @(posedge `SPC1.l2clk) ;
4143 @(posedge `SPC1.l2clk) ;
4144 ready = `PARGS.err_sync_on;
4145end //}
4146
4147`define DSFSR_NEW_IN_14 `SPC1.tlu.ras.dsfsr_6_new_in
4148`define ISFSR_NEW_IN_14 `SPC1.tlu.ras.isfsr_6_new_in
4149
4150`define DSFSR_14 `SPC1.tlu.ras.dsfsr_6
4151`define ISFSR_14 `SPC1.tlu.ras.isfsr_6
4152`define DSFAR_14 `SPC1.tlu.dfd.dsfar_6
4153
4154`define ASI_WR_DSFSR_14 `SPC1.tlu.ras.asi_wr_dsfsr[6]
4155`define ASI_WR_ISFSR_14 `SPC1.tlu.ras.asi_wr_isfsr[6]
4156
4157`define RAS_WRITE_DESR_1st_14 `SPC1.tlu.dfd.ras_write_desr_1st[6]
4158`define RAS_WRITE_DESR_2nd_14 `SPC1.tlu.dfd.ras_write_desr_2nd[6]
4159`define DESR_asi_rd_14 `SPC1.tlu.ras_rd_desr[6]
4160`define DESR_14 `SPC1.tlu.dfd.desr_6
4161
4162`define RAS_WRITE_FESR_14 `SPC1.tlu.ras.write_fesr[6]
4163`define FESR_14 `SPC1.tlu.dfd.fesr_6
4164
4165`define ST_ERR_14 `SPC1.tlu.trl1.take_ftt & `SPC1.tlu.trl1.trap[2]
4166`define SW_REC_ERR_14 `SPC1.tlu.trl1.take_ade & `SPC1.tlu.trl1.trap[2]
4167`define DATA_ACC_ERR_14 `SPC1.tlu.trl1.take_dae & `SPC1.tlu.trl1.trap[2]
4168`define INST_ACC_ERR_14 `SPC1.tlu.trl1.take_iae & `SPC1.tlu.trl1.trap[2]
4169`define INT_PROC_ERR_14 `SPC1.tlu.trl1.take_ipe & `SPC1.tlu.trl1.trap[2]
4170`define HW_CORR_ERR_14 `SPC1.tlu.trl1.take_eer & `SPC1.tlu.trl1.trap[2]
4171`define INST_ACC_MMU_ERR_14 `SPC1.tlu.trl1.take_ime & `SPC1.tlu.trl1.trap[2]
4172`define DATA_ACC_MMU_ERR_14 `SPC1.tlu.trl1.take_dme & `SPC1.tlu.trl1.trap[2]
4173
4174`define LSU_LD_VALID_B `PROBES1.lsu_ld_valid
4175`define LSU_TID_DEC_B_14 `PROBES1.lsu_tid_dec_b[6]
4176`define ASI_LD_14 `SPC1.lsu.lmd.lmq6_pkt[60] & (`SPC1.lsu.lmd.lmq6_pkt[49:48] == 2'b0)
4177`define ASI_14 `SPC1.lsu.lmd.lmq6_pkt[47:40]
4178`define ASI_ADDR_14 `SPC1.lsu.lmd.lmq6_pkt[39:0]
4179`define ASI_LD_DATA_14 `SPC1.lsu_exu_ld_data_b[63:0]
4180`define ASI_LD_COMP_14 tb_top.nas_top.c1.t6.complete_fw2
4181
4182//SPU specific - only one SPU per core
4183`define SPU_MA_BUSY_1 `SPC1.spu.spu_pmu_ma_busy[3]
4184`define SPU_MA_TID_1 `SPC1.spu.spu_pmu_ma_busy[2:0]
4185
4186////////////////////////////////////////////////////////////////////////////////
4187//Capture the status register data from rtl. For disrupting traps,
4188//rtl can modify the contents of the status register before the
4189//trap is taken and intp message is sent to Riesling.
4190//For precise traps, once the status register is updated rtl can't
4191//change the register again before jumping to the trap handler.
4192//So, for deferred and disrupting traps, inform Riesling when the
4193//register is modified while for precise traps wait until Fw2 before
4194//telling Riesling.
4195
4196//TLU asserts the flush and input signals in W stage. I latch them at the
4197//+ve edge of FX4.
4198
4199always @(negedge (`SPC1.l2clk & ready))
4200begin // {
4201 if (`DESR_asi_rd_14)
4202 desr_asi_rd <= 1'b1;
4203 if (desr_asi_rd)
4204 begin
4205 if (desr_wr)
4206 desr_pend_wr <= 1'b1;
4207 if (`ASI_LD_COMP_14[2])
4208 desr_asi_rd <= 1'b0;
4209 end
4210
4211 update_dsfsr_w <= (`DSFSR_NEW_IN_14 != 4'b0) && ~`ASI_WR_DSFSR_14;
4212 update_isfsr_w <= (`ISFSR_NEW_IN_14 != 3'b0) && ~`ASI_WR_ISFSR_14;
4213 desr_wr <= (`RAS_WRITE_DESR_1st_14 || `RAS_WRITE_DESR_2nd_14);
4214 update_dfesr_w <= `RAS_WRITE_FESR_14;
4215 take_err_trap_fx4 <= `ST_ERR_14 | `SW_REC_ERR_14 | `DATA_ACC_ERR_14
4216 | `INST_ACC_ERR_14 | `INT_PROC_ERR_14
4217 | `HW_CORR_ERR_14 | `INST_ACC_MMU_ERR_14
4218 | `DATA_ACC_MMU_ERR_14 ;
4219
4220
4221 if (`ST_ERR_14) int_num_fx4 <= 8'h07;
4222 if (`SW_REC_ERR_14) int_num_fx4 <= 8'h40;
4223 if (`DATA_ACC_ERR_14) int_num_fx4 <= 8'h32;
4224 if (`INST_ACC_ERR_14) int_num_fx4 <= 8'h0A;
4225 if (`INT_PROC_ERR_14) int_num_fx4 <= 8'h29;
4226 if (`HW_CORR_ERR_14) int_num_fx4 <= 8'h63;
4227 if (`INST_ACC_MMU_ERR_14) int_num_fx4 <= 8'h71;
4228 if (`DATA_ACC_MMU_ERR_14) int_num_fx4 <= 8'h72;
4229
4230 update_dsfsr_fx4 <= update_dsfsr_w;
4231 update_dsfsr_fx5 <= update_dsfsr_fx4;
4232 update_dsfsr_fb <= update_dsfsr_fx5;
4233 update_dsfsr_fw <= update_dsfsr_fb;
4234 update_dsfsr_fw1 <= update_dsfsr_fw;
4235 update_dsfsr_fw2 <= update_dsfsr_fw1;
4236
4237 update_isfsr_fx4 <= update_isfsr_w;
4238 update_isfsr_fx5 <= update_isfsr_fx4;
4239 update_isfsr_fb <= update_isfsr_fx5;
4240 update_isfsr_fw <= update_isfsr_fb;
4241 update_isfsr_fw1 <= update_isfsr_fw;
4242 update_isfsr_fw2 <= update_isfsr_fw1;
4243
4244 take_err_trap_fx5 <= take_err_trap_fx4;
4245 take_err_trap_fb <= take_err_trap_fx5;
4246 take_err_trap_fw <= take_err_trap_fb;
4247 take_err_trap_fw1 <= take_err_trap_fw;
4248 take_err_trap_fw2 <= take_err_trap_fw1;
4249
4250 int_num_fx5 <= int_num_fx4;
4251 int_num_fb <= int_num_fx5;
4252 int_num_fw <= int_num_fb;
4253 int_num_fw1 <= int_num_fw;
4254 int_num_fw2 <= int_num_fw1;
4255
4256 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
4257 begin // {
4258 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
4259 begin //{
4260 desr_pend_wr <= 1'b0;
4261 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_14[63:56], 45'b0, `DESR_14[10:0]});
4262 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_14[63:56], 45'b0, `DESR_14[10:0]});
4263 end //}
4264 //if (update_dfesr_w)
4265 if (`ST_ERR_14)
4266 begin //{
4267 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_14[61:55], 55'b0});
4268 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_14[61:55], 55'b0});
4269 end //}
4270 if (update_dsfsr_fw2)
4271 begin //{
4272 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
4273 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_14[3:0]});
4274 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_14[47:0]});
4275
4276 end //}
4277 if (update_isfsr_fw2)
4278 begin //{
4279 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
4280 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_14[2:0]});
4281 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_14[47:0]});
4282
4283 end //}
4284 if (take_err_trap_fw2)
4285 begin //{
4286 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
4287 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
4288 end // }
4289 end // }
4290
4291end //}
4292
4293//removing the addr check as the LSU doesn't flag an invalid_asi_exception
4294//if the addr of diagnostic accesses is not in the valid range. The inst.
4295//still executes. LSU expects that HP won't use addresses in invalid range.
4296
4297always @(negedge (`SPC1.l2clk & ready))
4298begin // {
4299 sync_asi = 1'b0;
4300 ld_data_w <= `ASI_LD_DATA_14;
4301
4302 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_14)
4303 chk_if_asi_ld <= 1'b1;
4304 else
4305 chk_if_asi_ld <= 1'b0;
4306
4307 if (chk_if_asi_ld & `ASI_LD_14)
4308 begin
4309 case (`ASI_14)
4310 8'h66: //ASI_IC_INSTR
4311 begin
4312 //if ((`ASI_ADDR_14 >= 0) & (`ASI_ADDR_14 <= 40'h7ff8))
4313 sync_asi = 1'b1;
4314 end
4315 8'h67: //ASI_IC_TAG
4316 begin
4317 //if ((`ASI_ADDR_14 >= 0) & (`ASI_ADDR_14 <= 40'h7fe0))
4318 sync_asi = 1'b1;
4319 end
4320 8'h46: //ASI_DC_DATA
4321 begin
4322 sync_asi = 1'b1;
4323 end
4324 8'h47: //ASI_DC_TAG
4325 begin
4326 //if ((`ASI_ADDR_14 >= 0) & (`ASI_ADDR_14 <= 40'h7ff0))
4327 sync_asi = 1'b1;
4328 end
4329 8'h48://IRF ECC
4330 begin
4331 //if ((`ASI_ADDR_14 >= 0) & (`ASI_ADDR_14 <= 40'hF8))
4332 sync_asi = 1'b1;
4333 end
4334 8'h49://FRF ECC
4335 begin
4336 //if ((`ASI_ADDR_14 >= 0) & (`ASI_ADDR_14 <= 40'hF8))
4337 sync_asi = 1'b1;
4338 end
4339 8'h4A://STB access, stb ptr can be read also
4340 begin
4341 //if ((`ASI_ADDR_14 >= 0) & (`ASI_ADDR_14 <= 40'h100))
4342 sync_asi = 1'b1;
4343 end
4344 8'h5A://Tick compare reg
4345 begin
4346 //if ((`ASI_ADDR_14 >= 0) & (`ASI_ADDR_14 <= 40'h38))
4347 sync_asi = 1'b1;
4348 end
4349 8'h5B://TSA
4350 begin
4351 //if ((`ASI_ADDR_14 >= 0) & (`ASI_ADDR_14 <= 40'h38))
4352 sync_asi = 1'b1;
4353 end
4354 8'h51://MRA
4355 begin
4356 //if ((`ASI_ADDR_14 >= 0) & (`ASI_ADDR_14 <= 40'h38))
4357 sync_asi = 1'b1;
4358 end
4359 8'h59://scratchpad ecc data read
4360 begin
4361 //if ((`ASI_ADDR_14 >= 0) & (`ASI_ADDR_14 <= 40'h38))
4362 //syncup the ecc data only. For ecc bit 6 is 0.
4363 if (~`SPC1.lsu.lmd.lmq6_pkt[6])
4364 sync_asi = 1'b1;
4365 end
4366 8'h40://cwqcsr,ma_sync access
4367 begin
4368 if ((`ASI_ADDR_14 == 40'h20) || (`ASI_ADDR_14 == 40'h30)
4369 || (`ASI_ADDR_14 == 40'h80)
4370 || ((`ASI_ADDR_14 == 40'ha0) & (`SPU_MA_BUSY_1 == 0) & (`SPU_MA_TID_1 == 6))
4371 )
4372 sync_asi = 1'b1;
4373 end
4374 8'h4C://CLESR, CLFESR access
4375 begin
4376 if ((`ASI_ADDR_14 == 40'h20) || (`ASI_ADDR_14 == 40'h28))
4377 sync_asi = 1'b1;
4378 end
4379 endcase
4380 end
4381
4382 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
4383 begin
4384 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_14, `ASI_ADDR_14, ld_data_w);
4385 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_14, {24'b0, `ASI_ADDR_14}, ld_data_w[63:0]);
4386 end
4387end //}
4388`endif
4389endmodule
4390
4391
4392
4393module err_c1t7 ();
4394`ifndef GATESIM
4395
4396`include "defines.vh"
4397
4398wire [2:0] mycid;
4399wire [2:0] mytid;
4400wire [5:0] mytnum;
4401
4402integer junk;
4403reg ready;
4404reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
4405reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
4406
4407reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
4408reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
4409
4410reg update_dfesr_w;
4411
4412reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
4413reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
4414
4415reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
4416reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
4417
4418reg sync_asi;
4419reg chk_if_asi_ld;
4420reg [63:0] ld_data_w;
4421
4422reg desr_asi_rd, desr_wr, desr_pend_wr;
4423
4424assign mycid = 1;
4425assign mytid = 7;
4426assign mytnum = 1*8 + 7;
4427
4428initial begin //{
4429 desr_asi_rd = 1'b0;
4430 desr_pend_wr = 1'b0;
4431 ready = 0;
4432 @(posedge `SPC1.l2clk) ;
4433 @(posedge `SPC1.l2clk) ;
4434 ready = `PARGS.err_sync_on;
4435end //}
4436
4437`define DSFSR_NEW_IN_15 `SPC1.tlu.ras.dsfsr_7_new_in
4438`define ISFSR_NEW_IN_15 `SPC1.tlu.ras.isfsr_7_new_in
4439
4440`define DSFSR_15 `SPC1.tlu.ras.dsfsr_7
4441`define ISFSR_15 `SPC1.tlu.ras.isfsr_7
4442`define DSFAR_15 `SPC1.tlu.dfd.dsfar_7
4443
4444`define ASI_WR_DSFSR_15 `SPC1.tlu.ras.asi_wr_dsfsr[7]
4445`define ASI_WR_ISFSR_15 `SPC1.tlu.ras.asi_wr_isfsr[7]
4446
4447`define RAS_WRITE_DESR_1st_15 `SPC1.tlu.dfd.ras_write_desr_1st[7]
4448`define RAS_WRITE_DESR_2nd_15 `SPC1.tlu.dfd.ras_write_desr_2nd[7]
4449`define DESR_asi_rd_15 `SPC1.tlu.ras_rd_desr[7]
4450`define DESR_15 `SPC1.tlu.dfd.desr_7
4451
4452`define RAS_WRITE_FESR_15 `SPC1.tlu.ras.write_fesr[7]
4453`define FESR_15 `SPC1.tlu.dfd.fesr_7
4454
4455`define ST_ERR_15 `SPC1.tlu.trl1.take_ftt & `SPC1.tlu.trl1.trap[3]
4456`define SW_REC_ERR_15 `SPC1.tlu.trl1.take_ade & `SPC1.tlu.trl1.trap[3]
4457`define DATA_ACC_ERR_15 `SPC1.tlu.trl1.take_dae & `SPC1.tlu.trl1.trap[3]
4458`define INST_ACC_ERR_15 `SPC1.tlu.trl1.take_iae & `SPC1.tlu.trl1.trap[3]
4459`define INT_PROC_ERR_15 `SPC1.tlu.trl1.take_ipe & `SPC1.tlu.trl1.trap[3]
4460`define HW_CORR_ERR_15 `SPC1.tlu.trl1.take_eer & `SPC1.tlu.trl1.trap[3]
4461`define INST_ACC_MMU_ERR_15 `SPC1.tlu.trl1.take_ime & `SPC1.tlu.trl1.trap[3]
4462`define DATA_ACC_MMU_ERR_15 `SPC1.tlu.trl1.take_dme & `SPC1.tlu.trl1.trap[3]
4463
4464`define LSU_LD_VALID_B `PROBES1.lsu_ld_valid
4465`define LSU_TID_DEC_B_15 `PROBES1.lsu_tid_dec_b[7]
4466`define ASI_LD_15 `SPC1.lsu.lmd.lmq7_pkt[60] & (`SPC1.lsu.lmd.lmq7_pkt[49:48] == 2'b0)
4467`define ASI_15 `SPC1.lsu.lmd.lmq7_pkt[47:40]
4468`define ASI_ADDR_15 `SPC1.lsu.lmd.lmq7_pkt[39:0]
4469`define ASI_LD_DATA_15 `SPC1.lsu_exu_ld_data_b[63:0]
4470`define ASI_LD_COMP_15 tb_top.nas_top.c1.t7.complete_fw2
4471
4472//SPU specific - only one SPU per core
4473`define SPU_MA_BUSY_1 `SPC1.spu.spu_pmu_ma_busy[3]
4474`define SPU_MA_TID_1 `SPC1.spu.spu_pmu_ma_busy[2:0]
4475
4476////////////////////////////////////////////////////////////////////////////////
4477//Capture the status register data from rtl. For disrupting traps,
4478//rtl can modify the contents of the status register before the
4479//trap is taken and intp message is sent to Riesling.
4480//For precise traps, once the status register is updated rtl can't
4481//change the register again before jumping to the trap handler.
4482//So, for deferred and disrupting traps, inform Riesling when the
4483//register is modified while for precise traps wait until Fw2 before
4484//telling Riesling.
4485
4486//TLU asserts the flush and input signals in W stage. I latch them at the
4487//+ve edge of FX4.
4488
4489always @(negedge (`SPC1.l2clk & ready))
4490begin // {
4491 if (`DESR_asi_rd_15)
4492 desr_asi_rd <= 1'b1;
4493 if (desr_asi_rd)
4494 begin
4495 if (desr_wr)
4496 desr_pend_wr <= 1'b1;
4497 if (`ASI_LD_COMP_15[2])
4498 desr_asi_rd <= 1'b0;
4499 end
4500
4501 update_dsfsr_w <= (`DSFSR_NEW_IN_15 != 4'b0) && ~`ASI_WR_DSFSR_15;
4502 update_isfsr_w <= (`ISFSR_NEW_IN_15 != 3'b0) && ~`ASI_WR_ISFSR_15;
4503 desr_wr <= (`RAS_WRITE_DESR_1st_15 || `RAS_WRITE_DESR_2nd_15);
4504 update_dfesr_w <= `RAS_WRITE_FESR_15;
4505 take_err_trap_fx4 <= `ST_ERR_15 | `SW_REC_ERR_15 | `DATA_ACC_ERR_15
4506 | `INST_ACC_ERR_15 | `INT_PROC_ERR_15
4507 | `HW_CORR_ERR_15 | `INST_ACC_MMU_ERR_15
4508 | `DATA_ACC_MMU_ERR_15 ;
4509
4510
4511 if (`ST_ERR_15) int_num_fx4 <= 8'h07;
4512 if (`SW_REC_ERR_15) int_num_fx4 <= 8'h40;
4513 if (`DATA_ACC_ERR_15) int_num_fx4 <= 8'h32;
4514 if (`INST_ACC_ERR_15) int_num_fx4 <= 8'h0A;
4515 if (`INT_PROC_ERR_15) int_num_fx4 <= 8'h29;
4516 if (`HW_CORR_ERR_15) int_num_fx4 <= 8'h63;
4517 if (`INST_ACC_MMU_ERR_15) int_num_fx4 <= 8'h71;
4518 if (`DATA_ACC_MMU_ERR_15) int_num_fx4 <= 8'h72;
4519
4520 update_dsfsr_fx4 <= update_dsfsr_w;
4521 update_dsfsr_fx5 <= update_dsfsr_fx4;
4522 update_dsfsr_fb <= update_dsfsr_fx5;
4523 update_dsfsr_fw <= update_dsfsr_fb;
4524 update_dsfsr_fw1 <= update_dsfsr_fw;
4525 update_dsfsr_fw2 <= update_dsfsr_fw1;
4526
4527 update_isfsr_fx4 <= update_isfsr_w;
4528 update_isfsr_fx5 <= update_isfsr_fx4;
4529 update_isfsr_fb <= update_isfsr_fx5;
4530 update_isfsr_fw <= update_isfsr_fb;
4531 update_isfsr_fw1 <= update_isfsr_fw;
4532 update_isfsr_fw2 <= update_isfsr_fw1;
4533
4534 take_err_trap_fx5 <= take_err_trap_fx4;
4535 take_err_trap_fb <= take_err_trap_fx5;
4536 take_err_trap_fw <= take_err_trap_fb;
4537 take_err_trap_fw1 <= take_err_trap_fw;
4538 take_err_trap_fw2 <= take_err_trap_fw1;
4539
4540 int_num_fx5 <= int_num_fx4;
4541 int_num_fb <= int_num_fx5;
4542 int_num_fw <= int_num_fb;
4543 int_num_fw1 <= int_num_fw;
4544 int_num_fw2 <= int_num_fw1;
4545
4546 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
4547 begin // {
4548 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
4549 begin //{
4550 desr_pend_wr <= 1'b0;
4551 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_15[63:56], 45'b0, `DESR_15[10:0]});
4552 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_15[63:56], 45'b0, `DESR_15[10:0]});
4553 end //}
4554 //if (update_dfesr_w)
4555 if (`ST_ERR_15)
4556 begin //{
4557 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_15[61:55], 55'b0});
4558 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_15[61:55], 55'b0});
4559 end //}
4560 if (update_dsfsr_fw2)
4561 begin //{
4562 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
4563 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_15[3:0]});
4564 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_15[47:0]});
4565
4566 end //}
4567 if (update_isfsr_fw2)
4568 begin //{
4569 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
4570 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_15[2:0]});
4571 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_15[47:0]});
4572
4573 end //}
4574 if (take_err_trap_fw2)
4575 begin //{
4576 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
4577 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
4578 end // }
4579 end // }
4580
4581end //}
4582
4583//removing the addr check as the LSU doesn't flag an invalid_asi_exception
4584//if the addr of diagnostic accesses is not in the valid range. The inst.
4585//still executes. LSU expects that HP won't use addresses in invalid range.
4586
4587always @(negedge (`SPC1.l2clk & ready))
4588begin // {
4589 sync_asi = 1'b0;
4590 ld_data_w <= `ASI_LD_DATA_15;
4591
4592 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_15)
4593 chk_if_asi_ld <= 1'b1;
4594 else
4595 chk_if_asi_ld <= 1'b0;
4596
4597 if (chk_if_asi_ld & `ASI_LD_15)
4598 begin
4599 case (`ASI_15)
4600 8'h66: //ASI_IC_INSTR
4601 begin
4602 //if ((`ASI_ADDR_15 >= 0) & (`ASI_ADDR_15 <= 40'h7ff8))
4603 sync_asi = 1'b1;
4604 end
4605 8'h67: //ASI_IC_TAG
4606 begin
4607 //if ((`ASI_ADDR_15 >= 0) & (`ASI_ADDR_15 <= 40'h7fe0))
4608 sync_asi = 1'b1;
4609 end
4610 8'h46: //ASI_DC_DATA
4611 begin
4612 sync_asi = 1'b1;
4613 end
4614 8'h47: //ASI_DC_TAG
4615 begin
4616 //if ((`ASI_ADDR_15 >= 0) & (`ASI_ADDR_15 <= 40'h7ff0))
4617 sync_asi = 1'b1;
4618 end
4619 8'h48://IRF ECC
4620 begin
4621 //if ((`ASI_ADDR_15 >= 0) & (`ASI_ADDR_15 <= 40'hF8))
4622 sync_asi = 1'b1;
4623 end
4624 8'h49://FRF ECC
4625 begin
4626 //if ((`ASI_ADDR_15 >= 0) & (`ASI_ADDR_15 <= 40'hF8))
4627 sync_asi = 1'b1;
4628 end
4629 8'h4A://STB access, stb ptr can be read also
4630 begin
4631 //if ((`ASI_ADDR_15 >= 0) & (`ASI_ADDR_15 <= 40'h100))
4632 sync_asi = 1'b1;
4633 end
4634 8'h5A://Tick compare reg
4635 begin
4636 //if ((`ASI_ADDR_15 >= 0) & (`ASI_ADDR_15 <= 40'h38))
4637 sync_asi = 1'b1;
4638 end
4639 8'h5B://TSA
4640 begin
4641 //if ((`ASI_ADDR_15 >= 0) & (`ASI_ADDR_15 <= 40'h38))
4642 sync_asi = 1'b1;
4643 end
4644 8'h51://MRA
4645 begin
4646 //if ((`ASI_ADDR_15 >= 0) & (`ASI_ADDR_15 <= 40'h38))
4647 sync_asi = 1'b1;
4648 end
4649 8'h59://scratchpad ecc data read
4650 begin
4651 //if ((`ASI_ADDR_15 >= 0) & (`ASI_ADDR_15 <= 40'h38))
4652 //syncup the ecc data only. For ecc bit 6 is 0.
4653 if (~`SPC1.lsu.lmd.lmq7_pkt[6])
4654 sync_asi = 1'b1;
4655 end
4656 8'h40://cwqcsr,ma_sync access
4657 begin
4658 if ((`ASI_ADDR_15 == 40'h20) || (`ASI_ADDR_15 == 40'h30)
4659 || (`ASI_ADDR_15 == 40'h80)
4660 || ((`ASI_ADDR_15 == 40'ha0) & (`SPU_MA_BUSY_1 == 0) & (`SPU_MA_TID_1 == 7))
4661 )
4662 sync_asi = 1'b1;
4663 end
4664 8'h4C://CLESR, CLFESR access
4665 begin
4666 if ((`ASI_ADDR_15 == 40'h20) || (`ASI_ADDR_15 == 40'h28))
4667 sync_asi = 1'b1;
4668 end
4669 endcase
4670 end
4671
4672 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
4673 begin
4674 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_15, `ASI_ADDR_15, ld_data_w);
4675 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_15, {24'b0, `ASI_ADDR_15}, ld_data_w[63:0]);
4676 end
4677end //}
4678`endif
4679endmodule
4680
4681`endif
4682
4683`ifdef CORE_2
4684
4685
4686
4687module err_c2t0 ();
4688`ifndef GATESIM
4689
4690`include "defines.vh"
4691
4692wire [2:0] mycid;
4693wire [2:0] mytid;
4694wire [5:0] mytnum;
4695
4696integer junk;
4697reg ready;
4698reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
4699reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
4700
4701reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
4702reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
4703
4704reg update_dfesr_w;
4705
4706reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
4707reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
4708
4709reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
4710reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
4711
4712reg sync_asi;
4713reg chk_if_asi_ld;
4714reg [63:0] ld_data_w;
4715
4716reg desr_asi_rd, desr_wr, desr_pend_wr;
4717
4718assign mycid = 2;
4719assign mytid = 0;
4720assign mytnum = 2*8 + 0;
4721
4722initial begin //{
4723 desr_asi_rd = 1'b0;
4724 desr_pend_wr = 1'b0;
4725 ready = 0;
4726 @(posedge `SPC2.l2clk) ;
4727 @(posedge `SPC2.l2clk) ;
4728 ready = `PARGS.err_sync_on;
4729end //}
4730
4731`define DSFSR_NEW_IN_16 `SPC2.tlu.ras.dsfsr_0_new_in
4732`define ISFSR_NEW_IN_16 `SPC2.tlu.ras.isfsr_0_new_in
4733
4734`define DSFSR_16 `SPC2.tlu.ras.dsfsr_0
4735`define ISFSR_16 `SPC2.tlu.ras.isfsr_0
4736`define DSFAR_16 `SPC2.tlu.dfd.dsfar_0
4737
4738`define ASI_WR_DSFSR_16 `SPC2.tlu.ras.asi_wr_dsfsr[0]
4739`define ASI_WR_ISFSR_16 `SPC2.tlu.ras.asi_wr_isfsr[0]
4740
4741`define RAS_WRITE_DESR_1st_16 `SPC2.tlu.dfd.ras_write_desr_1st[0]
4742`define RAS_WRITE_DESR_2nd_16 `SPC2.tlu.dfd.ras_write_desr_2nd[0]
4743`define DESR_asi_rd_16 `SPC2.tlu.ras_rd_desr[0]
4744`define DESR_16 `SPC2.tlu.dfd.desr_0
4745
4746`define RAS_WRITE_FESR_16 `SPC2.tlu.ras.write_fesr[0]
4747`define FESR_16 `SPC2.tlu.dfd.fesr_0
4748
4749`define ST_ERR_16 `SPC2.tlu.trl0.take_ftt & `SPC2.tlu.trl0.trap[0]
4750`define SW_REC_ERR_16 `SPC2.tlu.trl0.take_ade & `SPC2.tlu.trl0.trap[0]
4751`define DATA_ACC_ERR_16 `SPC2.tlu.trl0.take_dae & `SPC2.tlu.trl0.trap[0]
4752`define INST_ACC_ERR_16 `SPC2.tlu.trl0.take_iae & `SPC2.tlu.trl0.trap[0]
4753`define INT_PROC_ERR_16 `SPC2.tlu.trl0.take_ipe & `SPC2.tlu.trl0.trap[0]
4754`define HW_CORR_ERR_16 `SPC2.tlu.trl0.take_eer & `SPC2.tlu.trl0.trap[0]
4755`define INST_ACC_MMU_ERR_16 `SPC2.tlu.trl0.take_ime & `SPC2.tlu.trl0.trap[0]
4756`define DATA_ACC_MMU_ERR_16 `SPC2.tlu.trl0.take_dme & `SPC2.tlu.trl0.trap[0]
4757
4758`define LSU_LD_VALID_B `PROBES2.lsu_ld_valid
4759`define LSU_TID_DEC_B_16 `PROBES2.lsu_tid_dec_b[0]
4760`define ASI_LD_16 `SPC2.lsu.lmd.lmq0_pkt[60] & (`SPC2.lsu.lmd.lmq0_pkt[49:48] == 2'b0)
4761`define ASI_16 `SPC2.lsu.lmd.lmq0_pkt[47:40]
4762`define ASI_ADDR_16 `SPC2.lsu.lmd.lmq0_pkt[39:0]
4763`define ASI_LD_DATA_16 `SPC2.lsu_exu_ld_data_b[63:0]
4764`define ASI_LD_COMP_16 tb_top.nas_top.c2.t0.complete_fw2
4765
4766//SPU specific - only one SPU per core
4767`define SPU_MA_BUSY_2 `SPC2.spu.spu_pmu_ma_busy[3]
4768`define SPU_MA_TID_2 `SPC2.spu.spu_pmu_ma_busy[2:0]
4769
4770////////////////////////////////////////////////////////////////////////////////
4771//Capture the status register data from rtl. For disrupting traps,
4772//rtl can modify the contents of the status register before the
4773//trap is taken and intp message is sent to Riesling.
4774//For precise traps, once the status register is updated rtl can't
4775//change the register again before jumping to the trap handler.
4776//So, for deferred and disrupting traps, inform Riesling when the
4777//register is modified while for precise traps wait until Fw2 before
4778//telling Riesling.
4779
4780//TLU asserts the flush and input signals in W stage. I latch them at the
4781//+ve edge of FX4.
4782
4783always @(negedge (`SPC2.l2clk & ready))
4784begin // {
4785 if (`DESR_asi_rd_16)
4786 desr_asi_rd <= 1'b1;
4787 if (desr_asi_rd)
4788 begin
4789 if (desr_wr)
4790 desr_pend_wr <= 1'b1;
4791 if (`ASI_LD_COMP_16[2])
4792 desr_asi_rd <= 1'b0;
4793 end
4794
4795 update_dsfsr_w <= (`DSFSR_NEW_IN_16 != 4'b0) && ~`ASI_WR_DSFSR_16;
4796 update_isfsr_w <= (`ISFSR_NEW_IN_16 != 3'b0) && ~`ASI_WR_ISFSR_16;
4797 desr_wr <= (`RAS_WRITE_DESR_1st_16 || `RAS_WRITE_DESR_2nd_16);
4798 update_dfesr_w <= `RAS_WRITE_FESR_16;
4799 take_err_trap_fx4 <= `ST_ERR_16 | `SW_REC_ERR_16 | `DATA_ACC_ERR_16
4800 | `INST_ACC_ERR_16 | `INT_PROC_ERR_16
4801 | `HW_CORR_ERR_16 | `INST_ACC_MMU_ERR_16
4802 | `DATA_ACC_MMU_ERR_16 ;
4803
4804
4805 if (`ST_ERR_16) int_num_fx4 <= 8'h07;
4806 if (`SW_REC_ERR_16) int_num_fx4 <= 8'h40;
4807 if (`DATA_ACC_ERR_16) int_num_fx4 <= 8'h32;
4808 if (`INST_ACC_ERR_16) int_num_fx4 <= 8'h0A;
4809 if (`INT_PROC_ERR_16) int_num_fx4 <= 8'h29;
4810 if (`HW_CORR_ERR_16) int_num_fx4 <= 8'h63;
4811 if (`INST_ACC_MMU_ERR_16) int_num_fx4 <= 8'h71;
4812 if (`DATA_ACC_MMU_ERR_16) int_num_fx4 <= 8'h72;
4813
4814 update_dsfsr_fx4 <= update_dsfsr_w;
4815 update_dsfsr_fx5 <= update_dsfsr_fx4;
4816 update_dsfsr_fb <= update_dsfsr_fx5;
4817 update_dsfsr_fw <= update_dsfsr_fb;
4818 update_dsfsr_fw1 <= update_dsfsr_fw;
4819 update_dsfsr_fw2 <= update_dsfsr_fw1;
4820
4821 update_isfsr_fx4 <= update_isfsr_w;
4822 update_isfsr_fx5 <= update_isfsr_fx4;
4823 update_isfsr_fb <= update_isfsr_fx5;
4824 update_isfsr_fw <= update_isfsr_fb;
4825 update_isfsr_fw1 <= update_isfsr_fw;
4826 update_isfsr_fw2 <= update_isfsr_fw1;
4827
4828 take_err_trap_fx5 <= take_err_trap_fx4;
4829 take_err_trap_fb <= take_err_trap_fx5;
4830 take_err_trap_fw <= take_err_trap_fb;
4831 take_err_trap_fw1 <= take_err_trap_fw;
4832 take_err_trap_fw2 <= take_err_trap_fw1;
4833
4834 int_num_fx5 <= int_num_fx4;
4835 int_num_fb <= int_num_fx5;
4836 int_num_fw <= int_num_fb;
4837 int_num_fw1 <= int_num_fw;
4838 int_num_fw2 <= int_num_fw1;
4839
4840 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
4841 begin // {
4842 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
4843 begin //{
4844 desr_pend_wr <= 1'b0;
4845 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_16[63:56], 45'b0, `DESR_16[10:0]});
4846 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_16[63:56], 45'b0, `DESR_16[10:0]});
4847 end //}
4848 //if (update_dfesr_w)
4849 if (`ST_ERR_16)
4850 begin //{
4851 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_16[61:55], 55'b0});
4852 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_16[61:55], 55'b0});
4853 end //}
4854 if (update_dsfsr_fw2)
4855 begin //{
4856 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
4857 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_16[3:0]});
4858 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_16[47:0]});
4859
4860 end //}
4861 if (update_isfsr_fw2)
4862 begin //{
4863 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
4864 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_16[2:0]});
4865 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_16[47:0]});
4866
4867 end //}
4868 if (take_err_trap_fw2)
4869 begin //{
4870 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
4871 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
4872 end // }
4873 end // }
4874
4875end //}
4876
4877//removing the addr check as the LSU doesn't flag an invalid_asi_exception
4878//if the addr of diagnostic accesses is not in the valid range. The inst.
4879//still executes. LSU expects that HP won't use addresses in invalid range.
4880
4881always @(negedge (`SPC2.l2clk & ready))
4882begin // {
4883 sync_asi = 1'b0;
4884 ld_data_w <= `ASI_LD_DATA_16;
4885
4886 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_16)
4887 chk_if_asi_ld <= 1'b1;
4888 else
4889 chk_if_asi_ld <= 1'b0;
4890
4891 if (chk_if_asi_ld & `ASI_LD_16)
4892 begin
4893 case (`ASI_16)
4894 8'h66: //ASI_IC_INSTR
4895 begin
4896 //if ((`ASI_ADDR_16 >= 0) & (`ASI_ADDR_16 <= 40'h7ff8))
4897 sync_asi = 1'b1;
4898 end
4899 8'h67: //ASI_IC_TAG
4900 begin
4901 //if ((`ASI_ADDR_16 >= 0) & (`ASI_ADDR_16 <= 40'h7fe0))
4902 sync_asi = 1'b1;
4903 end
4904 8'h46: //ASI_DC_DATA
4905 begin
4906 sync_asi = 1'b1;
4907 end
4908 8'h47: //ASI_DC_TAG
4909 begin
4910 //if ((`ASI_ADDR_16 >= 0) & (`ASI_ADDR_16 <= 40'h7ff0))
4911 sync_asi = 1'b1;
4912 end
4913 8'h48://IRF ECC
4914 begin
4915 //if ((`ASI_ADDR_16 >= 0) & (`ASI_ADDR_16 <= 40'hF8))
4916 sync_asi = 1'b1;
4917 end
4918 8'h49://FRF ECC
4919 begin
4920 //if ((`ASI_ADDR_16 >= 0) & (`ASI_ADDR_16 <= 40'hF8))
4921 sync_asi = 1'b1;
4922 end
4923 8'h4A://STB access, stb ptr can be read also
4924 begin
4925 //if ((`ASI_ADDR_16 >= 0) & (`ASI_ADDR_16 <= 40'h100))
4926 sync_asi = 1'b1;
4927 end
4928 8'h5A://Tick compare reg
4929 begin
4930 //if ((`ASI_ADDR_16 >= 0) & (`ASI_ADDR_16 <= 40'h38))
4931 sync_asi = 1'b1;
4932 end
4933 8'h5B://TSA
4934 begin
4935 //if ((`ASI_ADDR_16 >= 0) & (`ASI_ADDR_16 <= 40'h38))
4936 sync_asi = 1'b1;
4937 end
4938 8'h51://MRA
4939 begin
4940 //if ((`ASI_ADDR_16 >= 0) & (`ASI_ADDR_16 <= 40'h38))
4941 sync_asi = 1'b1;
4942 end
4943 8'h59://scratchpad ecc data read
4944 begin
4945 //if ((`ASI_ADDR_16 >= 0) & (`ASI_ADDR_16 <= 40'h38))
4946 //syncup the ecc data only. For ecc bit 6 is 0.
4947 if (~`SPC2.lsu.lmd.lmq0_pkt[6])
4948 sync_asi = 1'b1;
4949 end
4950 8'h40://cwqcsr,ma_sync access
4951 begin
4952 if ((`ASI_ADDR_16 == 40'h20) || (`ASI_ADDR_16 == 40'h30)
4953 || (`ASI_ADDR_16 == 40'h80)
4954 || ((`ASI_ADDR_16 == 40'ha0) & (`SPU_MA_BUSY_2 == 0) & (`SPU_MA_TID_2 == 0))
4955 )
4956 sync_asi = 1'b1;
4957 end
4958 8'h4C://CLESR, CLFESR access
4959 begin
4960 if ((`ASI_ADDR_16 == 40'h20) || (`ASI_ADDR_16 == 40'h28))
4961 sync_asi = 1'b1;
4962 end
4963 endcase
4964 end
4965
4966 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
4967 begin
4968 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_16, `ASI_ADDR_16, ld_data_w);
4969 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_16, {24'b0, `ASI_ADDR_16}, ld_data_w[63:0]);
4970 end
4971end //}
4972`endif
4973endmodule
4974
4975
4976
4977module err_c2t1 ();
4978`ifndef GATESIM
4979
4980`include "defines.vh"
4981
4982wire [2:0] mycid;
4983wire [2:0] mytid;
4984wire [5:0] mytnum;
4985
4986integer junk;
4987reg ready;
4988reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
4989reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
4990
4991reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
4992reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
4993
4994reg update_dfesr_w;
4995
4996reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
4997reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
4998
4999reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
5000reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
5001
5002reg sync_asi;
5003reg chk_if_asi_ld;
5004reg [63:0] ld_data_w;
5005
5006reg desr_asi_rd, desr_wr, desr_pend_wr;
5007
5008assign mycid = 2;
5009assign mytid = 1;
5010assign mytnum = 2*8 + 1;
5011
5012initial begin //{
5013 desr_asi_rd = 1'b0;
5014 desr_pend_wr = 1'b0;
5015 ready = 0;
5016 @(posedge `SPC2.l2clk) ;
5017 @(posedge `SPC2.l2clk) ;
5018 ready = `PARGS.err_sync_on;
5019end //}
5020
5021`define DSFSR_NEW_IN_17 `SPC2.tlu.ras.dsfsr_1_new_in
5022`define ISFSR_NEW_IN_17 `SPC2.tlu.ras.isfsr_1_new_in
5023
5024`define DSFSR_17 `SPC2.tlu.ras.dsfsr_1
5025`define ISFSR_17 `SPC2.tlu.ras.isfsr_1
5026`define DSFAR_17 `SPC2.tlu.dfd.dsfar_1
5027
5028`define ASI_WR_DSFSR_17 `SPC2.tlu.ras.asi_wr_dsfsr[1]
5029`define ASI_WR_ISFSR_17 `SPC2.tlu.ras.asi_wr_isfsr[1]
5030
5031`define RAS_WRITE_DESR_1st_17 `SPC2.tlu.dfd.ras_write_desr_1st[1]
5032`define RAS_WRITE_DESR_2nd_17 `SPC2.tlu.dfd.ras_write_desr_2nd[1]
5033`define DESR_asi_rd_17 `SPC2.tlu.ras_rd_desr[1]
5034`define DESR_17 `SPC2.tlu.dfd.desr_1
5035
5036`define RAS_WRITE_FESR_17 `SPC2.tlu.ras.write_fesr[1]
5037`define FESR_17 `SPC2.tlu.dfd.fesr_1
5038
5039`define ST_ERR_17 `SPC2.tlu.trl0.take_ftt & `SPC2.tlu.trl0.trap[1]
5040`define SW_REC_ERR_17 `SPC2.tlu.trl0.take_ade & `SPC2.tlu.trl0.trap[1]
5041`define DATA_ACC_ERR_17 `SPC2.tlu.trl0.take_dae & `SPC2.tlu.trl0.trap[1]
5042`define INST_ACC_ERR_17 `SPC2.tlu.trl0.take_iae & `SPC2.tlu.trl0.trap[1]
5043`define INT_PROC_ERR_17 `SPC2.tlu.trl0.take_ipe & `SPC2.tlu.trl0.trap[1]
5044`define HW_CORR_ERR_17 `SPC2.tlu.trl0.take_eer & `SPC2.tlu.trl0.trap[1]
5045`define INST_ACC_MMU_ERR_17 `SPC2.tlu.trl0.take_ime & `SPC2.tlu.trl0.trap[1]
5046`define DATA_ACC_MMU_ERR_17 `SPC2.tlu.trl0.take_dme & `SPC2.tlu.trl0.trap[1]
5047
5048`define LSU_LD_VALID_B `PROBES2.lsu_ld_valid
5049`define LSU_TID_DEC_B_17 `PROBES2.lsu_tid_dec_b[1]
5050`define ASI_LD_17 `SPC2.lsu.lmd.lmq1_pkt[60] & (`SPC2.lsu.lmd.lmq1_pkt[49:48] == 2'b0)
5051`define ASI_17 `SPC2.lsu.lmd.lmq1_pkt[47:40]
5052`define ASI_ADDR_17 `SPC2.lsu.lmd.lmq1_pkt[39:0]
5053`define ASI_LD_DATA_17 `SPC2.lsu_exu_ld_data_b[63:0]
5054`define ASI_LD_COMP_17 tb_top.nas_top.c2.t1.complete_fw2
5055
5056//SPU specific - only one SPU per core
5057`define SPU_MA_BUSY_2 `SPC2.spu.spu_pmu_ma_busy[3]
5058`define SPU_MA_TID_2 `SPC2.spu.spu_pmu_ma_busy[2:0]
5059
5060////////////////////////////////////////////////////////////////////////////////
5061//Capture the status register data from rtl. For disrupting traps,
5062//rtl can modify the contents of the status register before the
5063//trap is taken and intp message is sent to Riesling.
5064//For precise traps, once the status register is updated rtl can't
5065//change the register again before jumping to the trap handler.
5066//So, for deferred and disrupting traps, inform Riesling when the
5067//register is modified while for precise traps wait until Fw2 before
5068//telling Riesling.
5069
5070//TLU asserts the flush and input signals in W stage. I latch them at the
5071//+ve edge of FX4.
5072
5073always @(negedge (`SPC2.l2clk & ready))
5074begin // {
5075 if (`DESR_asi_rd_17)
5076 desr_asi_rd <= 1'b1;
5077 if (desr_asi_rd)
5078 begin
5079 if (desr_wr)
5080 desr_pend_wr <= 1'b1;
5081 if (`ASI_LD_COMP_17[2])
5082 desr_asi_rd <= 1'b0;
5083 end
5084
5085 update_dsfsr_w <= (`DSFSR_NEW_IN_17 != 4'b0) && ~`ASI_WR_DSFSR_17;
5086 update_isfsr_w <= (`ISFSR_NEW_IN_17 != 3'b0) && ~`ASI_WR_ISFSR_17;
5087 desr_wr <= (`RAS_WRITE_DESR_1st_17 || `RAS_WRITE_DESR_2nd_17);
5088 update_dfesr_w <= `RAS_WRITE_FESR_17;
5089 take_err_trap_fx4 <= `ST_ERR_17 | `SW_REC_ERR_17 | `DATA_ACC_ERR_17
5090 | `INST_ACC_ERR_17 | `INT_PROC_ERR_17
5091 | `HW_CORR_ERR_17 | `INST_ACC_MMU_ERR_17
5092 | `DATA_ACC_MMU_ERR_17 ;
5093
5094
5095 if (`ST_ERR_17) int_num_fx4 <= 8'h07;
5096 if (`SW_REC_ERR_17) int_num_fx4 <= 8'h40;
5097 if (`DATA_ACC_ERR_17) int_num_fx4 <= 8'h32;
5098 if (`INST_ACC_ERR_17) int_num_fx4 <= 8'h0A;
5099 if (`INT_PROC_ERR_17) int_num_fx4 <= 8'h29;
5100 if (`HW_CORR_ERR_17) int_num_fx4 <= 8'h63;
5101 if (`INST_ACC_MMU_ERR_17) int_num_fx4 <= 8'h71;
5102 if (`DATA_ACC_MMU_ERR_17) int_num_fx4 <= 8'h72;
5103
5104 update_dsfsr_fx4 <= update_dsfsr_w;
5105 update_dsfsr_fx5 <= update_dsfsr_fx4;
5106 update_dsfsr_fb <= update_dsfsr_fx5;
5107 update_dsfsr_fw <= update_dsfsr_fb;
5108 update_dsfsr_fw1 <= update_dsfsr_fw;
5109 update_dsfsr_fw2 <= update_dsfsr_fw1;
5110
5111 update_isfsr_fx4 <= update_isfsr_w;
5112 update_isfsr_fx5 <= update_isfsr_fx4;
5113 update_isfsr_fb <= update_isfsr_fx5;
5114 update_isfsr_fw <= update_isfsr_fb;
5115 update_isfsr_fw1 <= update_isfsr_fw;
5116 update_isfsr_fw2 <= update_isfsr_fw1;
5117
5118 take_err_trap_fx5 <= take_err_trap_fx4;
5119 take_err_trap_fb <= take_err_trap_fx5;
5120 take_err_trap_fw <= take_err_trap_fb;
5121 take_err_trap_fw1 <= take_err_trap_fw;
5122 take_err_trap_fw2 <= take_err_trap_fw1;
5123
5124 int_num_fx5 <= int_num_fx4;
5125 int_num_fb <= int_num_fx5;
5126 int_num_fw <= int_num_fb;
5127 int_num_fw1 <= int_num_fw;
5128 int_num_fw2 <= int_num_fw1;
5129
5130 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
5131 begin // {
5132 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
5133 begin //{
5134 desr_pend_wr <= 1'b0;
5135 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_17[63:56], 45'b0, `DESR_17[10:0]});
5136 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_17[63:56], 45'b0, `DESR_17[10:0]});
5137 end //}
5138 //if (update_dfesr_w)
5139 if (`ST_ERR_17)
5140 begin //{
5141 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_17[61:55], 55'b0});
5142 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_17[61:55], 55'b0});
5143 end //}
5144 if (update_dsfsr_fw2)
5145 begin //{
5146 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
5147 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_17[3:0]});
5148 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_17[47:0]});
5149
5150 end //}
5151 if (update_isfsr_fw2)
5152 begin //{
5153 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
5154 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_17[2:0]});
5155 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_17[47:0]});
5156
5157 end //}
5158 if (take_err_trap_fw2)
5159 begin //{
5160 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
5161 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
5162 end // }
5163 end // }
5164
5165end //}
5166
5167//removing the addr check as the LSU doesn't flag an invalid_asi_exception
5168//if the addr of diagnostic accesses is not in the valid range. The inst.
5169//still executes. LSU expects that HP won't use addresses in invalid range.
5170
5171always @(negedge (`SPC2.l2clk & ready))
5172begin // {
5173 sync_asi = 1'b0;
5174 ld_data_w <= `ASI_LD_DATA_17;
5175
5176 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_17)
5177 chk_if_asi_ld <= 1'b1;
5178 else
5179 chk_if_asi_ld <= 1'b0;
5180
5181 if (chk_if_asi_ld & `ASI_LD_17)
5182 begin
5183 case (`ASI_17)
5184 8'h66: //ASI_IC_INSTR
5185 begin
5186 //if ((`ASI_ADDR_17 >= 0) & (`ASI_ADDR_17 <= 40'h7ff8))
5187 sync_asi = 1'b1;
5188 end
5189 8'h67: //ASI_IC_TAG
5190 begin
5191 //if ((`ASI_ADDR_17 >= 0) & (`ASI_ADDR_17 <= 40'h7fe0))
5192 sync_asi = 1'b1;
5193 end
5194 8'h46: //ASI_DC_DATA
5195 begin
5196 sync_asi = 1'b1;
5197 end
5198 8'h47: //ASI_DC_TAG
5199 begin
5200 //if ((`ASI_ADDR_17 >= 0) & (`ASI_ADDR_17 <= 40'h7ff0))
5201 sync_asi = 1'b1;
5202 end
5203 8'h48://IRF ECC
5204 begin
5205 //if ((`ASI_ADDR_17 >= 0) & (`ASI_ADDR_17 <= 40'hF8))
5206 sync_asi = 1'b1;
5207 end
5208 8'h49://FRF ECC
5209 begin
5210 //if ((`ASI_ADDR_17 >= 0) & (`ASI_ADDR_17 <= 40'hF8))
5211 sync_asi = 1'b1;
5212 end
5213 8'h4A://STB access, stb ptr can be read also
5214 begin
5215 //if ((`ASI_ADDR_17 >= 0) & (`ASI_ADDR_17 <= 40'h100))
5216 sync_asi = 1'b1;
5217 end
5218 8'h5A://Tick compare reg
5219 begin
5220 //if ((`ASI_ADDR_17 >= 0) & (`ASI_ADDR_17 <= 40'h38))
5221 sync_asi = 1'b1;
5222 end
5223 8'h5B://TSA
5224 begin
5225 //if ((`ASI_ADDR_17 >= 0) & (`ASI_ADDR_17 <= 40'h38))
5226 sync_asi = 1'b1;
5227 end
5228 8'h51://MRA
5229 begin
5230 //if ((`ASI_ADDR_17 >= 0) & (`ASI_ADDR_17 <= 40'h38))
5231 sync_asi = 1'b1;
5232 end
5233 8'h59://scratchpad ecc data read
5234 begin
5235 //if ((`ASI_ADDR_17 >= 0) & (`ASI_ADDR_17 <= 40'h38))
5236 //syncup the ecc data only. For ecc bit 6 is 0.
5237 if (~`SPC2.lsu.lmd.lmq1_pkt[6])
5238 sync_asi = 1'b1;
5239 end
5240 8'h40://cwqcsr,ma_sync access
5241 begin
5242 if ((`ASI_ADDR_17 == 40'h20) || (`ASI_ADDR_17 == 40'h30)
5243 || (`ASI_ADDR_17 == 40'h80)
5244 || ((`ASI_ADDR_17 == 40'ha0) & (`SPU_MA_BUSY_2 == 0) & (`SPU_MA_TID_2 == 1))
5245 )
5246 sync_asi = 1'b1;
5247 end
5248 8'h4C://CLESR, CLFESR access
5249 begin
5250 if ((`ASI_ADDR_17 == 40'h20) || (`ASI_ADDR_17 == 40'h28))
5251 sync_asi = 1'b1;
5252 end
5253 endcase
5254 end
5255
5256 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
5257 begin
5258 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_17, `ASI_ADDR_17, ld_data_w);
5259 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_17, {24'b0, `ASI_ADDR_17}, ld_data_w[63:0]);
5260 end
5261end //}
5262`endif
5263endmodule
5264
5265
5266
5267module err_c2t2 ();
5268`ifndef GATESIM
5269
5270`include "defines.vh"
5271
5272wire [2:0] mycid;
5273wire [2:0] mytid;
5274wire [5:0] mytnum;
5275
5276integer junk;
5277reg ready;
5278reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
5279reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
5280
5281reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
5282reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
5283
5284reg update_dfesr_w;
5285
5286reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
5287reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
5288
5289reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
5290reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
5291
5292reg sync_asi;
5293reg chk_if_asi_ld;
5294reg [63:0] ld_data_w;
5295
5296reg desr_asi_rd, desr_wr, desr_pend_wr;
5297
5298assign mycid = 2;
5299assign mytid = 2;
5300assign mytnum = 2*8 + 2;
5301
5302initial begin //{
5303 desr_asi_rd = 1'b0;
5304 desr_pend_wr = 1'b0;
5305 ready = 0;
5306 @(posedge `SPC2.l2clk) ;
5307 @(posedge `SPC2.l2clk) ;
5308 ready = `PARGS.err_sync_on;
5309end //}
5310
5311`define DSFSR_NEW_IN_18 `SPC2.tlu.ras.dsfsr_2_new_in
5312`define ISFSR_NEW_IN_18 `SPC2.tlu.ras.isfsr_2_new_in
5313
5314`define DSFSR_18 `SPC2.tlu.ras.dsfsr_2
5315`define ISFSR_18 `SPC2.tlu.ras.isfsr_2
5316`define DSFAR_18 `SPC2.tlu.dfd.dsfar_2
5317
5318`define ASI_WR_DSFSR_18 `SPC2.tlu.ras.asi_wr_dsfsr[2]
5319`define ASI_WR_ISFSR_18 `SPC2.tlu.ras.asi_wr_isfsr[2]
5320
5321`define RAS_WRITE_DESR_1st_18 `SPC2.tlu.dfd.ras_write_desr_1st[2]
5322`define RAS_WRITE_DESR_2nd_18 `SPC2.tlu.dfd.ras_write_desr_2nd[2]
5323`define DESR_asi_rd_18 `SPC2.tlu.ras_rd_desr[2]
5324`define DESR_18 `SPC2.tlu.dfd.desr_2
5325
5326`define RAS_WRITE_FESR_18 `SPC2.tlu.ras.write_fesr[2]
5327`define FESR_18 `SPC2.tlu.dfd.fesr_2
5328
5329`define ST_ERR_18 `SPC2.tlu.trl0.take_ftt & `SPC2.tlu.trl0.trap[2]
5330`define SW_REC_ERR_18 `SPC2.tlu.trl0.take_ade & `SPC2.tlu.trl0.trap[2]
5331`define DATA_ACC_ERR_18 `SPC2.tlu.trl0.take_dae & `SPC2.tlu.trl0.trap[2]
5332`define INST_ACC_ERR_18 `SPC2.tlu.trl0.take_iae & `SPC2.tlu.trl0.trap[2]
5333`define INT_PROC_ERR_18 `SPC2.tlu.trl0.take_ipe & `SPC2.tlu.trl0.trap[2]
5334`define HW_CORR_ERR_18 `SPC2.tlu.trl0.take_eer & `SPC2.tlu.trl0.trap[2]
5335`define INST_ACC_MMU_ERR_18 `SPC2.tlu.trl0.take_ime & `SPC2.tlu.trl0.trap[2]
5336`define DATA_ACC_MMU_ERR_18 `SPC2.tlu.trl0.take_dme & `SPC2.tlu.trl0.trap[2]
5337
5338`define LSU_LD_VALID_B `PROBES2.lsu_ld_valid
5339`define LSU_TID_DEC_B_18 `PROBES2.lsu_tid_dec_b[2]
5340`define ASI_LD_18 `SPC2.lsu.lmd.lmq2_pkt[60] & (`SPC2.lsu.lmd.lmq2_pkt[49:48] == 2'b0)
5341`define ASI_18 `SPC2.lsu.lmd.lmq2_pkt[47:40]
5342`define ASI_ADDR_18 `SPC2.lsu.lmd.lmq2_pkt[39:0]
5343`define ASI_LD_DATA_18 `SPC2.lsu_exu_ld_data_b[63:0]
5344`define ASI_LD_COMP_18 tb_top.nas_top.c2.t2.complete_fw2
5345
5346//SPU specific - only one SPU per core
5347`define SPU_MA_BUSY_2 `SPC2.spu.spu_pmu_ma_busy[3]
5348`define SPU_MA_TID_2 `SPC2.spu.spu_pmu_ma_busy[2:0]
5349
5350////////////////////////////////////////////////////////////////////////////////
5351//Capture the status register data from rtl. For disrupting traps,
5352//rtl can modify the contents of the status register before the
5353//trap is taken and intp message is sent to Riesling.
5354//For precise traps, once the status register is updated rtl can't
5355//change the register again before jumping to the trap handler.
5356//So, for deferred and disrupting traps, inform Riesling when the
5357//register is modified while for precise traps wait until Fw2 before
5358//telling Riesling.
5359
5360//TLU asserts the flush and input signals in W stage. I latch them at the
5361//+ve edge of FX4.
5362
5363always @(negedge (`SPC2.l2clk & ready))
5364begin // {
5365 if (`DESR_asi_rd_18)
5366 desr_asi_rd <= 1'b1;
5367 if (desr_asi_rd)
5368 begin
5369 if (desr_wr)
5370 desr_pend_wr <= 1'b1;
5371 if (`ASI_LD_COMP_18[2])
5372 desr_asi_rd <= 1'b0;
5373 end
5374
5375 update_dsfsr_w <= (`DSFSR_NEW_IN_18 != 4'b0) && ~`ASI_WR_DSFSR_18;
5376 update_isfsr_w <= (`ISFSR_NEW_IN_18 != 3'b0) && ~`ASI_WR_ISFSR_18;
5377 desr_wr <= (`RAS_WRITE_DESR_1st_18 || `RAS_WRITE_DESR_2nd_18);
5378 update_dfesr_w <= `RAS_WRITE_FESR_18;
5379 take_err_trap_fx4 <= `ST_ERR_18 | `SW_REC_ERR_18 | `DATA_ACC_ERR_18
5380 | `INST_ACC_ERR_18 | `INT_PROC_ERR_18
5381 | `HW_CORR_ERR_18 | `INST_ACC_MMU_ERR_18
5382 | `DATA_ACC_MMU_ERR_18 ;
5383
5384
5385 if (`ST_ERR_18) int_num_fx4 <= 8'h07;
5386 if (`SW_REC_ERR_18) int_num_fx4 <= 8'h40;
5387 if (`DATA_ACC_ERR_18) int_num_fx4 <= 8'h32;
5388 if (`INST_ACC_ERR_18) int_num_fx4 <= 8'h0A;
5389 if (`INT_PROC_ERR_18) int_num_fx4 <= 8'h29;
5390 if (`HW_CORR_ERR_18) int_num_fx4 <= 8'h63;
5391 if (`INST_ACC_MMU_ERR_18) int_num_fx4 <= 8'h71;
5392 if (`DATA_ACC_MMU_ERR_18) int_num_fx4 <= 8'h72;
5393
5394 update_dsfsr_fx4 <= update_dsfsr_w;
5395 update_dsfsr_fx5 <= update_dsfsr_fx4;
5396 update_dsfsr_fb <= update_dsfsr_fx5;
5397 update_dsfsr_fw <= update_dsfsr_fb;
5398 update_dsfsr_fw1 <= update_dsfsr_fw;
5399 update_dsfsr_fw2 <= update_dsfsr_fw1;
5400
5401 update_isfsr_fx4 <= update_isfsr_w;
5402 update_isfsr_fx5 <= update_isfsr_fx4;
5403 update_isfsr_fb <= update_isfsr_fx5;
5404 update_isfsr_fw <= update_isfsr_fb;
5405 update_isfsr_fw1 <= update_isfsr_fw;
5406 update_isfsr_fw2 <= update_isfsr_fw1;
5407
5408 take_err_trap_fx5 <= take_err_trap_fx4;
5409 take_err_trap_fb <= take_err_trap_fx5;
5410 take_err_trap_fw <= take_err_trap_fb;
5411 take_err_trap_fw1 <= take_err_trap_fw;
5412 take_err_trap_fw2 <= take_err_trap_fw1;
5413
5414 int_num_fx5 <= int_num_fx4;
5415 int_num_fb <= int_num_fx5;
5416 int_num_fw <= int_num_fb;
5417 int_num_fw1 <= int_num_fw;
5418 int_num_fw2 <= int_num_fw1;
5419
5420 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
5421 begin // {
5422 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
5423 begin //{
5424 desr_pend_wr <= 1'b0;
5425 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_18[63:56], 45'b0, `DESR_18[10:0]});
5426 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_18[63:56], 45'b0, `DESR_18[10:0]});
5427 end //}
5428 //if (update_dfesr_w)
5429 if (`ST_ERR_18)
5430 begin //{
5431 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_18[61:55], 55'b0});
5432 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_18[61:55], 55'b0});
5433 end //}
5434 if (update_dsfsr_fw2)
5435 begin //{
5436 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
5437 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_18[3:0]});
5438 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_18[47:0]});
5439
5440 end //}
5441 if (update_isfsr_fw2)
5442 begin //{
5443 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
5444 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_18[2:0]});
5445 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_18[47:0]});
5446
5447 end //}
5448 if (take_err_trap_fw2)
5449 begin //{
5450 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
5451 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
5452 end // }
5453 end // }
5454
5455end //}
5456
5457//removing the addr check as the LSU doesn't flag an invalid_asi_exception
5458//if the addr of diagnostic accesses is not in the valid range. The inst.
5459//still executes. LSU expects that HP won't use addresses in invalid range.
5460
5461always @(negedge (`SPC2.l2clk & ready))
5462begin // {
5463 sync_asi = 1'b0;
5464 ld_data_w <= `ASI_LD_DATA_18;
5465
5466 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_18)
5467 chk_if_asi_ld <= 1'b1;
5468 else
5469 chk_if_asi_ld <= 1'b0;
5470
5471 if (chk_if_asi_ld & `ASI_LD_18)
5472 begin
5473 case (`ASI_18)
5474 8'h66: //ASI_IC_INSTR
5475 begin
5476 //if ((`ASI_ADDR_18 >= 0) & (`ASI_ADDR_18 <= 40'h7ff8))
5477 sync_asi = 1'b1;
5478 end
5479 8'h67: //ASI_IC_TAG
5480 begin
5481 //if ((`ASI_ADDR_18 >= 0) & (`ASI_ADDR_18 <= 40'h7fe0))
5482 sync_asi = 1'b1;
5483 end
5484 8'h46: //ASI_DC_DATA
5485 begin
5486 sync_asi = 1'b1;
5487 end
5488 8'h47: //ASI_DC_TAG
5489 begin
5490 //if ((`ASI_ADDR_18 >= 0) & (`ASI_ADDR_18 <= 40'h7ff0))
5491 sync_asi = 1'b1;
5492 end
5493 8'h48://IRF ECC
5494 begin
5495 //if ((`ASI_ADDR_18 >= 0) & (`ASI_ADDR_18 <= 40'hF8))
5496 sync_asi = 1'b1;
5497 end
5498 8'h49://FRF ECC
5499 begin
5500 //if ((`ASI_ADDR_18 >= 0) & (`ASI_ADDR_18 <= 40'hF8))
5501 sync_asi = 1'b1;
5502 end
5503 8'h4A://STB access, stb ptr can be read also
5504 begin
5505 //if ((`ASI_ADDR_18 >= 0) & (`ASI_ADDR_18 <= 40'h100))
5506 sync_asi = 1'b1;
5507 end
5508 8'h5A://Tick compare reg
5509 begin
5510 //if ((`ASI_ADDR_18 >= 0) & (`ASI_ADDR_18 <= 40'h38))
5511 sync_asi = 1'b1;
5512 end
5513 8'h5B://TSA
5514 begin
5515 //if ((`ASI_ADDR_18 >= 0) & (`ASI_ADDR_18 <= 40'h38))
5516 sync_asi = 1'b1;
5517 end
5518 8'h51://MRA
5519 begin
5520 //if ((`ASI_ADDR_18 >= 0) & (`ASI_ADDR_18 <= 40'h38))
5521 sync_asi = 1'b1;
5522 end
5523 8'h59://scratchpad ecc data read
5524 begin
5525 //if ((`ASI_ADDR_18 >= 0) & (`ASI_ADDR_18 <= 40'h38))
5526 //syncup the ecc data only. For ecc bit 6 is 0.
5527 if (~`SPC2.lsu.lmd.lmq2_pkt[6])
5528 sync_asi = 1'b1;
5529 end
5530 8'h40://cwqcsr,ma_sync access
5531 begin
5532 if ((`ASI_ADDR_18 == 40'h20) || (`ASI_ADDR_18 == 40'h30)
5533 || (`ASI_ADDR_18 == 40'h80)
5534 || ((`ASI_ADDR_18 == 40'ha0) & (`SPU_MA_BUSY_2 == 0) & (`SPU_MA_TID_2 == 2))
5535 )
5536 sync_asi = 1'b1;
5537 end
5538 8'h4C://CLESR, CLFESR access
5539 begin
5540 if ((`ASI_ADDR_18 == 40'h20) || (`ASI_ADDR_18 == 40'h28))
5541 sync_asi = 1'b1;
5542 end
5543 endcase
5544 end
5545
5546 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
5547 begin
5548 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_18, `ASI_ADDR_18, ld_data_w);
5549 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_18, {24'b0, `ASI_ADDR_18}, ld_data_w[63:0]);
5550 end
5551end //}
5552`endif
5553endmodule
5554
5555
5556
5557module err_c2t3 ();
5558`ifndef GATESIM
5559
5560`include "defines.vh"
5561
5562wire [2:0] mycid;
5563wire [2:0] mytid;
5564wire [5:0] mytnum;
5565
5566integer junk;
5567reg ready;
5568reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
5569reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
5570
5571reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
5572reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
5573
5574reg update_dfesr_w;
5575
5576reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
5577reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
5578
5579reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
5580reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
5581
5582reg sync_asi;
5583reg chk_if_asi_ld;
5584reg [63:0] ld_data_w;
5585
5586reg desr_asi_rd, desr_wr, desr_pend_wr;
5587
5588assign mycid = 2;
5589assign mytid = 3;
5590assign mytnum = 2*8 + 3;
5591
5592initial begin //{
5593 desr_asi_rd = 1'b0;
5594 desr_pend_wr = 1'b0;
5595 ready = 0;
5596 @(posedge `SPC2.l2clk) ;
5597 @(posedge `SPC2.l2clk) ;
5598 ready = `PARGS.err_sync_on;
5599end //}
5600
5601`define DSFSR_NEW_IN_19 `SPC2.tlu.ras.dsfsr_3_new_in
5602`define ISFSR_NEW_IN_19 `SPC2.tlu.ras.isfsr_3_new_in
5603
5604`define DSFSR_19 `SPC2.tlu.ras.dsfsr_3
5605`define ISFSR_19 `SPC2.tlu.ras.isfsr_3
5606`define DSFAR_19 `SPC2.tlu.dfd.dsfar_3
5607
5608`define ASI_WR_DSFSR_19 `SPC2.tlu.ras.asi_wr_dsfsr[3]
5609`define ASI_WR_ISFSR_19 `SPC2.tlu.ras.asi_wr_isfsr[3]
5610
5611`define RAS_WRITE_DESR_1st_19 `SPC2.tlu.dfd.ras_write_desr_1st[3]
5612`define RAS_WRITE_DESR_2nd_19 `SPC2.tlu.dfd.ras_write_desr_2nd[3]
5613`define DESR_asi_rd_19 `SPC2.tlu.ras_rd_desr[3]
5614`define DESR_19 `SPC2.tlu.dfd.desr_3
5615
5616`define RAS_WRITE_FESR_19 `SPC2.tlu.ras.write_fesr[3]
5617`define FESR_19 `SPC2.tlu.dfd.fesr_3
5618
5619`define ST_ERR_19 `SPC2.tlu.trl0.take_ftt & `SPC2.tlu.trl0.trap[3]
5620`define SW_REC_ERR_19 `SPC2.tlu.trl0.take_ade & `SPC2.tlu.trl0.trap[3]
5621`define DATA_ACC_ERR_19 `SPC2.tlu.trl0.take_dae & `SPC2.tlu.trl0.trap[3]
5622`define INST_ACC_ERR_19 `SPC2.tlu.trl0.take_iae & `SPC2.tlu.trl0.trap[3]
5623`define INT_PROC_ERR_19 `SPC2.tlu.trl0.take_ipe & `SPC2.tlu.trl0.trap[3]
5624`define HW_CORR_ERR_19 `SPC2.tlu.trl0.take_eer & `SPC2.tlu.trl0.trap[3]
5625`define INST_ACC_MMU_ERR_19 `SPC2.tlu.trl0.take_ime & `SPC2.tlu.trl0.trap[3]
5626`define DATA_ACC_MMU_ERR_19 `SPC2.tlu.trl0.take_dme & `SPC2.tlu.trl0.trap[3]
5627
5628`define LSU_LD_VALID_B `PROBES2.lsu_ld_valid
5629`define LSU_TID_DEC_B_19 `PROBES2.lsu_tid_dec_b[3]
5630`define ASI_LD_19 `SPC2.lsu.lmd.lmq3_pkt[60] & (`SPC2.lsu.lmd.lmq3_pkt[49:48] == 2'b0)
5631`define ASI_19 `SPC2.lsu.lmd.lmq3_pkt[47:40]
5632`define ASI_ADDR_19 `SPC2.lsu.lmd.lmq3_pkt[39:0]
5633`define ASI_LD_DATA_19 `SPC2.lsu_exu_ld_data_b[63:0]
5634`define ASI_LD_COMP_19 tb_top.nas_top.c2.t3.complete_fw2
5635
5636//SPU specific - only one SPU per core
5637`define SPU_MA_BUSY_2 `SPC2.spu.spu_pmu_ma_busy[3]
5638`define SPU_MA_TID_2 `SPC2.spu.spu_pmu_ma_busy[2:0]
5639
5640////////////////////////////////////////////////////////////////////////////////
5641//Capture the status register data from rtl. For disrupting traps,
5642//rtl can modify the contents of the status register before the
5643//trap is taken and intp message is sent to Riesling.
5644//For precise traps, once the status register is updated rtl can't
5645//change the register again before jumping to the trap handler.
5646//So, for deferred and disrupting traps, inform Riesling when the
5647//register is modified while for precise traps wait until Fw2 before
5648//telling Riesling.
5649
5650//TLU asserts the flush and input signals in W stage. I latch them at the
5651//+ve edge of FX4.
5652
5653always @(negedge (`SPC2.l2clk & ready))
5654begin // {
5655 if (`DESR_asi_rd_19)
5656 desr_asi_rd <= 1'b1;
5657 if (desr_asi_rd)
5658 begin
5659 if (desr_wr)
5660 desr_pend_wr <= 1'b1;
5661 if (`ASI_LD_COMP_19[2])
5662 desr_asi_rd <= 1'b0;
5663 end
5664
5665 update_dsfsr_w <= (`DSFSR_NEW_IN_19 != 4'b0) && ~`ASI_WR_DSFSR_19;
5666 update_isfsr_w <= (`ISFSR_NEW_IN_19 != 3'b0) && ~`ASI_WR_ISFSR_19;
5667 desr_wr <= (`RAS_WRITE_DESR_1st_19 || `RAS_WRITE_DESR_2nd_19);
5668 update_dfesr_w <= `RAS_WRITE_FESR_19;
5669 take_err_trap_fx4 <= `ST_ERR_19 | `SW_REC_ERR_19 | `DATA_ACC_ERR_19
5670 | `INST_ACC_ERR_19 | `INT_PROC_ERR_19
5671 | `HW_CORR_ERR_19 | `INST_ACC_MMU_ERR_19
5672 | `DATA_ACC_MMU_ERR_19 ;
5673
5674
5675 if (`ST_ERR_19) int_num_fx4 <= 8'h07;
5676 if (`SW_REC_ERR_19) int_num_fx4 <= 8'h40;
5677 if (`DATA_ACC_ERR_19) int_num_fx4 <= 8'h32;
5678 if (`INST_ACC_ERR_19) int_num_fx4 <= 8'h0A;
5679 if (`INT_PROC_ERR_19) int_num_fx4 <= 8'h29;
5680 if (`HW_CORR_ERR_19) int_num_fx4 <= 8'h63;
5681 if (`INST_ACC_MMU_ERR_19) int_num_fx4 <= 8'h71;
5682 if (`DATA_ACC_MMU_ERR_19) int_num_fx4 <= 8'h72;
5683
5684 update_dsfsr_fx4 <= update_dsfsr_w;
5685 update_dsfsr_fx5 <= update_dsfsr_fx4;
5686 update_dsfsr_fb <= update_dsfsr_fx5;
5687 update_dsfsr_fw <= update_dsfsr_fb;
5688 update_dsfsr_fw1 <= update_dsfsr_fw;
5689 update_dsfsr_fw2 <= update_dsfsr_fw1;
5690
5691 update_isfsr_fx4 <= update_isfsr_w;
5692 update_isfsr_fx5 <= update_isfsr_fx4;
5693 update_isfsr_fb <= update_isfsr_fx5;
5694 update_isfsr_fw <= update_isfsr_fb;
5695 update_isfsr_fw1 <= update_isfsr_fw;
5696 update_isfsr_fw2 <= update_isfsr_fw1;
5697
5698 take_err_trap_fx5 <= take_err_trap_fx4;
5699 take_err_trap_fb <= take_err_trap_fx5;
5700 take_err_trap_fw <= take_err_trap_fb;
5701 take_err_trap_fw1 <= take_err_trap_fw;
5702 take_err_trap_fw2 <= take_err_trap_fw1;
5703
5704 int_num_fx5 <= int_num_fx4;
5705 int_num_fb <= int_num_fx5;
5706 int_num_fw <= int_num_fb;
5707 int_num_fw1 <= int_num_fw;
5708 int_num_fw2 <= int_num_fw1;
5709
5710 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
5711 begin // {
5712 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
5713 begin //{
5714 desr_pend_wr <= 1'b0;
5715 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_19[63:56], 45'b0, `DESR_19[10:0]});
5716 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_19[63:56], 45'b0, `DESR_19[10:0]});
5717 end //}
5718 //if (update_dfesr_w)
5719 if (`ST_ERR_19)
5720 begin //{
5721 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_19[61:55], 55'b0});
5722 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_19[61:55], 55'b0});
5723 end //}
5724 if (update_dsfsr_fw2)
5725 begin //{
5726 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
5727 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_19[3:0]});
5728 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_19[47:0]});
5729
5730 end //}
5731 if (update_isfsr_fw2)
5732 begin //{
5733 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
5734 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_19[2:0]});
5735 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_19[47:0]});
5736
5737 end //}
5738 if (take_err_trap_fw2)
5739 begin //{
5740 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
5741 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
5742 end // }
5743 end // }
5744
5745end //}
5746
5747//removing the addr check as the LSU doesn't flag an invalid_asi_exception
5748//if the addr of diagnostic accesses is not in the valid range. The inst.
5749//still executes. LSU expects that HP won't use addresses in invalid range.
5750
5751always @(negedge (`SPC2.l2clk & ready))
5752begin // {
5753 sync_asi = 1'b0;
5754 ld_data_w <= `ASI_LD_DATA_19;
5755
5756 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_19)
5757 chk_if_asi_ld <= 1'b1;
5758 else
5759 chk_if_asi_ld <= 1'b0;
5760
5761 if (chk_if_asi_ld & `ASI_LD_19)
5762 begin
5763 case (`ASI_19)
5764 8'h66: //ASI_IC_INSTR
5765 begin
5766 //if ((`ASI_ADDR_19 >= 0) & (`ASI_ADDR_19 <= 40'h7ff8))
5767 sync_asi = 1'b1;
5768 end
5769 8'h67: //ASI_IC_TAG
5770 begin
5771 //if ((`ASI_ADDR_19 >= 0) & (`ASI_ADDR_19 <= 40'h7fe0))
5772 sync_asi = 1'b1;
5773 end
5774 8'h46: //ASI_DC_DATA
5775 begin
5776 sync_asi = 1'b1;
5777 end
5778 8'h47: //ASI_DC_TAG
5779 begin
5780 //if ((`ASI_ADDR_19 >= 0) & (`ASI_ADDR_19 <= 40'h7ff0))
5781 sync_asi = 1'b1;
5782 end
5783 8'h48://IRF ECC
5784 begin
5785 //if ((`ASI_ADDR_19 >= 0) & (`ASI_ADDR_19 <= 40'hF8))
5786 sync_asi = 1'b1;
5787 end
5788 8'h49://FRF ECC
5789 begin
5790 //if ((`ASI_ADDR_19 >= 0) & (`ASI_ADDR_19 <= 40'hF8))
5791 sync_asi = 1'b1;
5792 end
5793 8'h4A://STB access, stb ptr can be read also
5794 begin
5795 //if ((`ASI_ADDR_19 >= 0) & (`ASI_ADDR_19 <= 40'h100))
5796 sync_asi = 1'b1;
5797 end
5798 8'h5A://Tick compare reg
5799 begin
5800 //if ((`ASI_ADDR_19 >= 0) & (`ASI_ADDR_19 <= 40'h38))
5801 sync_asi = 1'b1;
5802 end
5803 8'h5B://TSA
5804 begin
5805 //if ((`ASI_ADDR_19 >= 0) & (`ASI_ADDR_19 <= 40'h38))
5806 sync_asi = 1'b1;
5807 end
5808 8'h51://MRA
5809 begin
5810 //if ((`ASI_ADDR_19 >= 0) & (`ASI_ADDR_19 <= 40'h38))
5811 sync_asi = 1'b1;
5812 end
5813 8'h59://scratchpad ecc data read
5814 begin
5815 //if ((`ASI_ADDR_19 >= 0) & (`ASI_ADDR_19 <= 40'h38))
5816 //syncup the ecc data only. For ecc bit 6 is 0.
5817 if (~`SPC2.lsu.lmd.lmq3_pkt[6])
5818 sync_asi = 1'b1;
5819 end
5820 8'h40://cwqcsr,ma_sync access
5821 begin
5822 if ((`ASI_ADDR_19 == 40'h20) || (`ASI_ADDR_19 == 40'h30)
5823 || (`ASI_ADDR_19 == 40'h80)
5824 || ((`ASI_ADDR_19 == 40'ha0) & (`SPU_MA_BUSY_2 == 0) & (`SPU_MA_TID_2 == 3))
5825 )
5826 sync_asi = 1'b1;
5827 end
5828 8'h4C://CLESR, CLFESR access
5829 begin
5830 if ((`ASI_ADDR_19 == 40'h20) || (`ASI_ADDR_19 == 40'h28))
5831 sync_asi = 1'b1;
5832 end
5833 endcase
5834 end
5835
5836 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
5837 begin
5838 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_19, `ASI_ADDR_19, ld_data_w);
5839 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_19, {24'b0, `ASI_ADDR_19}, ld_data_w[63:0]);
5840 end
5841end //}
5842`endif
5843endmodule
5844
5845
5846
5847module err_c2t4 ();
5848`ifndef GATESIM
5849
5850`include "defines.vh"
5851
5852wire [2:0] mycid;
5853wire [2:0] mytid;
5854wire [5:0] mytnum;
5855
5856integer junk;
5857reg ready;
5858reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
5859reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
5860
5861reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
5862reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
5863
5864reg update_dfesr_w;
5865
5866reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
5867reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
5868
5869reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
5870reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
5871
5872reg sync_asi;
5873reg chk_if_asi_ld;
5874reg [63:0] ld_data_w;
5875
5876reg desr_asi_rd, desr_wr, desr_pend_wr;
5877
5878assign mycid = 2;
5879assign mytid = 4;
5880assign mytnum = 2*8 + 4;
5881
5882initial begin //{
5883 desr_asi_rd = 1'b0;
5884 desr_pend_wr = 1'b0;
5885 ready = 0;
5886 @(posedge `SPC2.l2clk) ;
5887 @(posedge `SPC2.l2clk) ;
5888 ready = `PARGS.err_sync_on;
5889end //}
5890
5891`define DSFSR_NEW_IN_20 `SPC2.tlu.ras.dsfsr_4_new_in
5892`define ISFSR_NEW_IN_20 `SPC2.tlu.ras.isfsr_4_new_in
5893
5894`define DSFSR_20 `SPC2.tlu.ras.dsfsr_4
5895`define ISFSR_20 `SPC2.tlu.ras.isfsr_4
5896`define DSFAR_20 `SPC2.tlu.dfd.dsfar_4
5897
5898`define ASI_WR_DSFSR_20 `SPC2.tlu.ras.asi_wr_dsfsr[4]
5899`define ASI_WR_ISFSR_20 `SPC2.tlu.ras.asi_wr_isfsr[4]
5900
5901`define RAS_WRITE_DESR_1st_20 `SPC2.tlu.dfd.ras_write_desr_1st[4]
5902`define RAS_WRITE_DESR_2nd_20 `SPC2.tlu.dfd.ras_write_desr_2nd[4]
5903`define DESR_asi_rd_20 `SPC2.tlu.ras_rd_desr[4]
5904`define DESR_20 `SPC2.tlu.dfd.desr_4
5905
5906`define RAS_WRITE_FESR_20 `SPC2.tlu.ras.write_fesr[4]
5907`define FESR_20 `SPC2.tlu.dfd.fesr_4
5908
5909`define ST_ERR_20 `SPC2.tlu.trl1.take_ftt & `SPC2.tlu.trl1.trap[0]
5910`define SW_REC_ERR_20 `SPC2.tlu.trl1.take_ade & `SPC2.tlu.trl1.trap[0]
5911`define DATA_ACC_ERR_20 `SPC2.tlu.trl1.take_dae & `SPC2.tlu.trl1.trap[0]
5912`define INST_ACC_ERR_20 `SPC2.tlu.trl1.take_iae & `SPC2.tlu.trl1.trap[0]
5913`define INT_PROC_ERR_20 `SPC2.tlu.trl1.take_ipe & `SPC2.tlu.trl1.trap[0]
5914`define HW_CORR_ERR_20 `SPC2.tlu.trl1.take_eer & `SPC2.tlu.trl1.trap[0]
5915`define INST_ACC_MMU_ERR_20 `SPC2.tlu.trl1.take_ime & `SPC2.tlu.trl1.trap[0]
5916`define DATA_ACC_MMU_ERR_20 `SPC2.tlu.trl1.take_dme & `SPC2.tlu.trl1.trap[0]
5917
5918`define LSU_LD_VALID_B `PROBES2.lsu_ld_valid
5919`define LSU_TID_DEC_B_20 `PROBES2.lsu_tid_dec_b[4]
5920`define ASI_LD_20 `SPC2.lsu.lmd.lmq4_pkt[60] & (`SPC2.lsu.lmd.lmq4_pkt[49:48] == 2'b0)
5921`define ASI_20 `SPC2.lsu.lmd.lmq4_pkt[47:40]
5922`define ASI_ADDR_20 `SPC2.lsu.lmd.lmq4_pkt[39:0]
5923`define ASI_LD_DATA_20 `SPC2.lsu_exu_ld_data_b[63:0]
5924`define ASI_LD_COMP_20 tb_top.nas_top.c2.t4.complete_fw2
5925
5926//SPU specific - only one SPU per core
5927`define SPU_MA_BUSY_2 `SPC2.spu.spu_pmu_ma_busy[3]
5928`define SPU_MA_TID_2 `SPC2.spu.spu_pmu_ma_busy[2:0]
5929
5930////////////////////////////////////////////////////////////////////////////////
5931//Capture the status register data from rtl. For disrupting traps,
5932//rtl can modify the contents of the status register before the
5933//trap is taken and intp message is sent to Riesling.
5934//For precise traps, once the status register is updated rtl can't
5935//change the register again before jumping to the trap handler.
5936//So, for deferred and disrupting traps, inform Riesling when the
5937//register is modified while for precise traps wait until Fw2 before
5938//telling Riesling.
5939
5940//TLU asserts the flush and input signals in W stage. I latch them at the
5941//+ve edge of FX4.
5942
5943always @(negedge (`SPC2.l2clk & ready))
5944begin // {
5945 if (`DESR_asi_rd_20)
5946 desr_asi_rd <= 1'b1;
5947 if (desr_asi_rd)
5948 begin
5949 if (desr_wr)
5950 desr_pend_wr <= 1'b1;
5951 if (`ASI_LD_COMP_20[2])
5952 desr_asi_rd <= 1'b0;
5953 end
5954
5955 update_dsfsr_w <= (`DSFSR_NEW_IN_20 != 4'b0) && ~`ASI_WR_DSFSR_20;
5956 update_isfsr_w <= (`ISFSR_NEW_IN_20 != 3'b0) && ~`ASI_WR_ISFSR_20;
5957 desr_wr <= (`RAS_WRITE_DESR_1st_20 || `RAS_WRITE_DESR_2nd_20);
5958 update_dfesr_w <= `RAS_WRITE_FESR_20;
5959 take_err_trap_fx4 <= `ST_ERR_20 | `SW_REC_ERR_20 | `DATA_ACC_ERR_20
5960 | `INST_ACC_ERR_20 | `INT_PROC_ERR_20
5961 | `HW_CORR_ERR_20 | `INST_ACC_MMU_ERR_20
5962 | `DATA_ACC_MMU_ERR_20 ;
5963
5964
5965 if (`ST_ERR_20) int_num_fx4 <= 8'h07;
5966 if (`SW_REC_ERR_20) int_num_fx4 <= 8'h40;
5967 if (`DATA_ACC_ERR_20) int_num_fx4 <= 8'h32;
5968 if (`INST_ACC_ERR_20) int_num_fx4 <= 8'h0A;
5969 if (`INT_PROC_ERR_20) int_num_fx4 <= 8'h29;
5970 if (`HW_CORR_ERR_20) int_num_fx4 <= 8'h63;
5971 if (`INST_ACC_MMU_ERR_20) int_num_fx4 <= 8'h71;
5972 if (`DATA_ACC_MMU_ERR_20) int_num_fx4 <= 8'h72;
5973
5974 update_dsfsr_fx4 <= update_dsfsr_w;
5975 update_dsfsr_fx5 <= update_dsfsr_fx4;
5976 update_dsfsr_fb <= update_dsfsr_fx5;
5977 update_dsfsr_fw <= update_dsfsr_fb;
5978 update_dsfsr_fw1 <= update_dsfsr_fw;
5979 update_dsfsr_fw2 <= update_dsfsr_fw1;
5980
5981 update_isfsr_fx4 <= update_isfsr_w;
5982 update_isfsr_fx5 <= update_isfsr_fx4;
5983 update_isfsr_fb <= update_isfsr_fx5;
5984 update_isfsr_fw <= update_isfsr_fb;
5985 update_isfsr_fw1 <= update_isfsr_fw;
5986 update_isfsr_fw2 <= update_isfsr_fw1;
5987
5988 take_err_trap_fx5 <= take_err_trap_fx4;
5989 take_err_trap_fb <= take_err_trap_fx5;
5990 take_err_trap_fw <= take_err_trap_fb;
5991 take_err_trap_fw1 <= take_err_trap_fw;
5992 take_err_trap_fw2 <= take_err_trap_fw1;
5993
5994 int_num_fx5 <= int_num_fx4;
5995 int_num_fb <= int_num_fx5;
5996 int_num_fw <= int_num_fb;
5997 int_num_fw1 <= int_num_fw;
5998 int_num_fw2 <= int_num_fw1;
5999
6000 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
6001 begin // {
6002 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
6003 begin //{
6004 desr_pend_wr <= 1'b0;
6005 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_20[63:56], 45'b0, `DESR_20[10:0]});
6006 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_20[63:56], 45'b0, `DESR_20[10:0]});
6007 end //}
6008 //if (update_dfesr_w)
6009 if (`ST_ERR_20)
6010 begin //{
6011 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_20[61:55], 55'b0});
6012 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_20[61:55], 55'b0});
6013 end //}
6014 if (update_dsfsr_fw2)
6015 begin //{
6016 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
6017 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_20[3:0]});
6018 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_20[47:0]});
6019
6020 end //}
6021 if (update_isfsr_fw2)
6022 begin //{
6023 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
6024 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_20[2:0]});
6025 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_20[47:0]});
6026
6027 end //}
6028 if (take_err_trap_fw2)
6029 begin //{
6030 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
6031 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
6032 end // }
6033 end // }
6034
6035end //}
6036
6037//removing the addr check as the LSU doesn't flag an invalid_asi_exception
6038//if the addr of diagnostic accesses is not in the valid range. The inst.
6039//still executes. LSU expects that HP won't use addresses in invalid range.
6040
6041always @(negedge (`SPC2.l2clk & ready))
6042begin // {
6043 sync_asi = 1'b0;
6044 ld_data_w <= `ASI_LD_DATA_20;
6045
6046 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_20)
6047 chk_if_asi_ld <= 1'b1;
6048 else
6049 chk_if_asi_ld <= 1'b0;
6050
6051 if (chk_if_asi_ld & `ASI_LD_20)
6052 begin
6053 case (`ASI_20)
6054 8'h66: //ASI_IC_INSTR
6055 begin
6056 //if ((`ASI_ADDR_20 >= 0) & (`ASI_ADDR_20 <= 40'h7ff8))
6057 sync_asi = 1'b1;
6058 end
6059 8'h67: //ASI_IC_TAG
6060 begin
6061 //if ((`ASI_ADDR_20 >= 0) & (`ASI_ADDR_20 <= 40'h7fe0))
6062 sync_asi = 1'b1;
6063 end
6064 8'h46: //ASI_DC_DATA
6065 begin
6066 sync_asi = 1'b1;
6067 end
6068 8'h47: //ASI_DC_TAG
6069 begin
6070 //if ((`ASI_ADDR_20 >= 0) & (`ASI_ADDR_20 <= 40'h7ff0))
6071 sync_asi = 1'b1;
6072 end
6073 8'h48://IRF ECC
6074 begin
6075 //if ((`ASI_ADDR_20 >= 0) & (`ASI_ADDR_20 <= 40'hF8))
6076 sync_asi = 1'b1;
6077 end
6078 8'h49://FRF ECC
6079 begin
6080 //if ((`ASI_ADDR_20 >= 0) & (`ASI_ADDR_20 <= 40'hF8))
6081 sync_asi = 1'b1;
6082 end
6083 8'h4A://STB access, stb ptr can be read also
6084 begin
6085 //if ((`ASI_ADDR_20 >= 0) & (`ASI_ADDR_20 <= 40'h100))
6086 sync_asi = 1'b1;
6087 end
6088 8'h5A://Tick compare reg
6089 begin
6090 //if ((`ASI_ADDR_20 >= 0) & (`ASI_ADDR_20 <= 40'h38))
6091 sync_asi = 1'b1;
6092 end
6093 8'h5B://TSA
6094 begin
6095 //if ((`ASI_ADDR_20 >= 0) & (`ASI_ADDR_20 <= 40'h38))
6096 sync_asi = 1'b1;
6097 end
6098 8'h51://MRA
6099 begin
6100 //if ((`ASI_ADDR_20 >= 0) & (`ASI_ADDR_20 <= 40'h38))
6101 sync_asi = 1'b1;
6102 end
6103 8'h59://scratchpad ecc data read
6104 begin
6105 //if ((`ASI_ADDR_20 >= 0) & (`ASI_ADDR_20 <= 40'h38))
6106 //syncup the ecc data only. For ecc bit 6 is 0.
6107 if (~`SPC2.lsu.lmd.lmq4_pkt[6])
6108 sync_asi = 1'b1;
6109 end
6110 8'h40://cwqcsr,ma_sync access
6111 begin
6112 if ((`ASI_ADDR_20 == 40'h20) || (`ASI_ADDR_20 == 40'h30)
6113 || (`ASI_ADDR_20 == 40'h80)
6114 || ((`ASI_ADDR_20 == 40'ha0) & (`SPU_MA_BUSY_2 == 0) & (`SPU_MA_TID_2 == 4))
6115 )
6116 sync_asi = 1'b1;
6117 end
6118 8'h4C://CLESR, CLFESR access
6119 begin
6120 if ((`ASI_ADDR_20 == 40'h20) || (`ASI_ADDR_20 == 40'h28))
6121 sync_asi = 1'b1;
6122 end
6123 endcase
6124 end
6125
6126 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
6127 begin
6128 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_20, `ASI_ADDR_20, ld_data_w);
6129 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_20, {24'b0, `ASI_ADDR_20}, ld_data_w[63:0]);
6130 end
6131end //}
6132`endif
6133endmodule
6134
6135
6136
6137module err_c2t5 ();
6138`ifndef GATESIM
6139
6140`include "defines.vh"
6141
6142wire [2:0] mycid;
6143wire [2:0] mytid;
6144wire [5:0] mytnum;
6145
6146integer junk;
6147reg ready;
6148reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
6149reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
6150
6151reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
6152reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
6153
6154reg update_dfesr_w;
6155
6156reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
6157reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
6158
6159reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
6160reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
6161
6162reg sync_asi;
6163reg chk_if_asi_ld;
6164reg [63:0] ld_data_w;
6165
6166reg desr_asi_rd, desr_wr, desr_pend_wr;
6167
6168assign mycid = 2;
6169assign mytid = 5;
6170assign mytnum = 2*8 + 5;
6171
6172initial begin //{
6173 desr_asi_rd = 1'b0;
6174 desr_pend_wr = 1'b0;
6175 ready = 0;
6176 @(posedge `SPC2.l2clk) ;
6177 @(posedge `SPC2.l2clk) ;
6178 ready = `PARGS.err_sync_on;
6179end //}
6180
6181`define DSFSR_NEW_IN_21 `SPC2.tlu.ras.dsfsr_5_new_in
6182`define ISFSR_NEW_IN_21 `SPC2.tlu.ras.isfsr_5_new_in
6183
6184`define DSFSR_21 `SPC2.tlu.ras.dsfsr_5
6185`define ISFSR_21 `SPC2.tlu.ras.isfsr_5
6186`define DSFAR_21 `SPC2.tlu.dfd.dsfar_5
6187
6188`define ASI_WR_DSFSR_21 `SPC2.tlu.ras.asi_wr_dsfsr[5]
6189`define ASI_WR_ISFSR_21 `SPC2.tlu.ras.asi_wr_isfsr[5]
6190
6191`define RAS_WRITE_DESR_1st_21 `SPC2.tlu.dfd.ras_write_desr_1st[5]
6192`define RAS_WRITE_DESR_2nd_21 `SPC2.tlu.dfd.ras_write_desr_2nd[5]
6193`define DESR_asi_rd_21 `SPC2.tlu.ras_rd_desr[5]
6194`define DESR_21 `SPC2.tlu.dfd.desr_5
6195
6196`define RAS_WRITE_FESR_21 `SPC2.tlu.ras.write_fesr[5]
6197`define FESR_21 `SPC2.tlu.dfd.fesr_5
6198
6199`define ST_ERR_21 `SPC2.tlu.trl1.take_ftt & `SPC2.tlu.trl1.trap[1]
6200`define SW_REC_ERR_21 `SPC2.tlu.trl1.take_ade & `SPC2.tlu.trl1.trap[1]
6201`define DATA_ACC_ERR_21 `SPC2.tlu.trl1.take_dae & `SPC2.tlu.trl1.trap[1]
6202`define INST_ACC_ERR_21 `SPC2.tlu.trl1.take_iae & `SPC2.tlu.trl1.trap[1]
6203`define INT_PROC_ERR_21 `SPC2.tlu.trl1.take_ipe & `SPC2.tlu.trl1.trap[1]
6204`define HW_CORR_ERR_21 `SPC2.tlu.trl1.take_eer & `SPC2.tlu.trl1.trap[1]
6205`define INST_ACC_MMU_ERR_21 `SPC2.tlu.trl1.take_ime & `SPC2.tlu.trl1.trap[1]
6206`define DATA_ACC_MMU_ERR_21 `SPC2.tlu.trl1.take_dme & `SPC2.tlu.trl1.trap[1]
6207
6208`define LSU_LD_VALID_B `PROBES2.lsu_ld_valid
6209`define LSU_TID_DEC_B_21 `PROBES2.lsu_tid_dec_b[5]
6210`define ASI_LD_21 `SPC2.lsu.lmd.lmq5_pkt[60] & (`SPC2.lsu.lmd.lmq5_pkt[49:48] == 2'b0)
6211`define ASI_21 `SPC2.lsu.lmd.lmq5_pkt[47:40]
6212`define ASI_ADDR_21 `SPC2.lsu.lmd.lmq5_pkt[39:0]
6213`define ASI_LD_DATA_21 `SPC2.lsu_exu_ld_data_b[63:0]
6214`define ASI_LD_COMP_21 tb_top.nas_top.c2.t5.complete_fw2
6215
6216//SPU specific - only one SPU per core
6217`define SPU_MA_BUSY_2 `SPC2.spu.spu_pmu_ma_busy[3]
6218`define SPU_MA_TID_2 `SPC2.spu.spu_pmu_ma_busy[2:0]
6219
6220////////////////////////////////////////////////////////////////////////////////
6221//Capture the status register data from rtl. For disrupting traps,
6222//rtl can modify the contents of the status register before the
6223//trap is taken and intp message is sent to Riesling.
6224//For precise traps, once the status register is updated rtl can't
6225//change the register again before jumping to the trap handler.
6226//So, for deferred and disrupting traps, inform Riesling when the
6227//register is modified while for precise traps wait until Fw2 before
6228//telling Riesling.
6229
6230//TLU asserts the flush and input signals in W stage. I latch them at the
6231//+ve edge of FX4.
6232
6233always @(negedge (`SPC2.l2clk & ready))
6234begin // {
6235 if (`DESR_asi_rd_21)
6236 desr_asi_rd <= 1'b1;
6237 if (desr_asi_rd)
6238 begin
6239 if (desr_wr)
6240 desr_pend_wr <= 1'b1;
6241 if (`ASI_LD_COMP_21[2])
6242 desr_asi_rd <= 1'b0;
6243 end
6244
6245 update_dsfsr_w <= (`DSFSR_NEW_IN_21 != 4'b0) && ~`ASI_WR_DSFSR_21;
6246 update_isfsr_w <= (`ISFSR_NEW_IN_21 != 3'b0) && ~`ASI_WR_ISFSR_21;
6247 desr_wr <= (`RAS_WRITE_DESR_1st_21 || `RAS_WRITE_DESR_2nd_21);
6248 update_dfesr_w <= `RAS_WRITE_FESR_21;
6249 take_err_trap_fx4 <= `ST_ERR_21 | `SW_REC_ERR_21 | `DATA_ACC_ERR_21
6250 | `INST_ACC_ERR_21 | `INT_PROC_ERR_21
6251 | `HW_CORR_ERR_21 | `INST_ACC_MMU_ERR_21
6252 | `DATA_ACC_MMU_ERR_21 ;
6253
6254
6255 if (`ST_ERR_21) int_num_fx4 <= 8'h07;
6256 if (`SW_REC_ERR_21) int_num_fx4 <= 8'h40;
6257 if (`DATA_ACC_ERR_21) int_num_fx4 <= 8'h32;
6258 if (`INST_ACC_ERR_21) int_num_fx4 <= 8'h0A;
6259 if (`INT_PROC_ERR_21) int_num_fx4 <= 8'h29;
6260 if (`HW_CORR_ERR_21) int_num_fx4 <= 8'h63;
6261 if (`INST_ACC_MMU_ERR_21) int_num_fx4 <= 8'h71;
6262 if (`DATA_ACC_MMU_ERR_21) int_num_fx4 <= 8'h72;
6263
6264 update_dsfsr_fx4 <= update_dsfsr_w;
6265 update_dsfsr_fx5 <= update_dsfsr_fx4;
6266 update_dsfsr_fb <= update_dsfsr_fx5;
6267 update_dsfsr_fw <= update_dsfsr_fb;
6268 update_dsfsr_fw1 <= update_dsfsr_fw;
6269 update_dsfsr_fw2 <= update_dsfsr_fw1;
6270
6271 update_isfsr_fx4 <= update_isfsr_w;
6272 update_isfsr_fx5 <= update_isfsr_fx4;
6273 update_isfsr_fb <= update_isfsr_fx5;
6274 update_isfsr_fw <= update_isfsr_fb;
6275 update_isfsr_fw1 <= update_isfsr_fw;
6276 update_isfsr_fw2 <= update_isfsr_fw1;
6277
6278 take_err_trap_fx5 <= take_err_trap_fx4;
6279 take_err_trap_fb <= take_err_trap_fx5;
6280 take_err_trap_fw <= take_err_trap_fb;
6281 take_err_trap_fw1 <= take_err_trap_fw;
6282 take_err_trap_fw2 <= take_err_trap_fw1;
6283
6284 int_num_fx5 <= int_num_fx4;
6285 int_num_fb <= int_num_fx5;
6286 int_num_fw <= int_num_fb;
6287 int_num_fw1 <= int_num_fw;
6288 int_num_fw2 <= int_num_fw1;
6289
6290 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
6291 begin // {
6292 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
6293 begin //{
6294 desr_pend_wr <= 1'b0;
6295 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_21[63:56], 45'b0, `DESR_21[10:0]});
6296 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_21[63:56], 45'b0, `DESR_21[10:0]});
6297 end //}
6298 //if (update_dfesr_w)
6299 if (`ST_ERR_21)
6300 begin //{
6301 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_21[61:55], 55'b0});
6302 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_21[61:55], 55'b0});
6303 end //}
6304 if (update_dsfsr_fw2)
6305 begin //{
6306 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
6307 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_21[3:0]});
6308 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_21[47:0]});
6309
6310 end //}
6311 if (update_isfsr_fw2)
6312 begin //{
6313 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
6314 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_21[2:0]});
6315 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_21[47:0]});
6316
6317 end //}
6318 if (take_err_trap_fw2)
6319 begin //{
6320 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
6321 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
6322 end // }
6323 end // }
6324
6325end //}
6326
6327//removing the addr check as the LSU doesn't flag an invalid_asi_exception
6328//if the addr of diagnostic accesses is not in the valid range. The inst.
6329//still executes. LSU expects that HP won't use addresses in invalid range.
6330
6331always @(negedge (`SPC2.l2clk & ready))
6332begin // {
6333 sync_asi = 1'b0;
6334 ld_data_w <= `ASI_LD_DATA_21;
6335
6336 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_21)
6337 chk_if_asi_ld <= 1'b1;
6338 else
6339 chk_if_asi_ld <= 1'b0;
6340
6341 if (chk_if_asi_ld & `ASI_LD_21)
6342 begin
6343 case (`ASI_21)
6344 8'h66: //ASI_IC_INSTR
6345 begin
6346 //if ((`ASI_ADDR_21 >= 0) & (`ASI_ADDR_21 <= 40'h7ff8))
6347 sync_asi = 1'b1;
6348 end
6349 8'h67: //ASI_IC_TAG
6350 begin
6351 //if ((`ASI_ADDR_21 >= 0) & (`ASI_ADDR_21 <= 40'h7fe0))
6352 sync_asi = 1'b1;
6353 end
6354 8'h46: //ASI_DC_DATA
6355 begin
6356 sync_asi = 1'b1;
6357 end
6358 8'h47: //ASI_DC_TAG
6359 begin
6360 //if ((`ASI_ADDR_21 >= 0) & (`ASI_ADDR_21 <= 40'h7ff0))
6361 sync_asi = 1'b1;
6362 end
6363 8'h48://IRF ECC
6364 begin
6365 //if ((`ASI_ADDR_21 >= 0) & (`ASI_ADDR_21 <= 40'hF8))
6366 sync_asi = 1'b1;
6367 end
6368 8'h49://FRF ECC
6369 begin
6370 //if ((`ASI_ADDR_21 >= 0) & (`ASI_ADDR_21 <= 40'hF8))
6371 sync_asi = 1'b1;
6372 end
6373 8'h4A://STB access, stb ptr can be read also
6374 begin
6375 //if ((`ASI_ADDR_21 >= 0) & (`ASI_ADDR_21 <= 40'h100))
6376 sync_asi = 1'b1;
6377 end
6378 8'h5A://Tick compare reg
6379 begin
6380 //if ((`ASI_ADDR_21 >= 0) & (`ASI_ADDR_21 <= 40'h38))
6381 sync_asi = 1'b1;
6382 end
6383 8'h5B://TSA
6384 begin
6385 //if ((`ASI_ADDR_21 >= 0) & (`ASI_ADDR_21 <= 40'h38))
6386 sync_asi = 1'b1;
6387 end
6388 8'h51://MRA
6389 begin
6390 //if ((`ASI_ADDR_21 >= 0) & (`ASI_ADDR_21 <= 40'h38))
6391 sync_asi = 1'b1;
6392 end
6393 8'h59://scratchpad ecc data read
6394 begin
6395 //if ((`ASI_ADDR_21 >= 0) & (`ASI_ADDR_21 <= 40'h38))
6396 //syncup the ecc data only. For ecc bit 6 is 0.
6397 if (~`SPC2.lsu.lmd.lmq5_pkt[6])
6398 sync_asi = 1'b1;
6399 end
6400 8'h40://cwqcsr,ma_sync access
6401 begin
6402 if ((`ASI_ADDR_21 == 40'h20) || (`ASI_ADDR_21 == 40'h30)
6403 || (`ASI_ADDR_21 == 40'h80)
6404 || ((`ASI_ADDR_21 == 40'ha0) & (`SPU_MA_BUSY_2 == 0) & (`SPU_MA_TID_2 == 5))
6405 )
6406 sync_asi = 1'b1;
6407 end
6408 8'h4C://CLESR, CLFESR access
6409 begin
6410 if ((`ASI_ADDR_21 == 40'h20) || (`ASI_ADDR_21 == 40'h28))
6411 sync_asi = 1'b1;
6412 end
6413 endcase
6414 end
6415
6416 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
6417 begin
6418 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_21, `ASI_ADDR_21, ld_data_w);
6419 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_21, {24'b0, `ASI_ADDR_21}, ld_data_w[63:0]);
6420 end
6421end //}
6422`endif
6423endmodule
6424
6425
6426
6427module err_c2t6 ();
6428`ifndef GATESIM
6429
6430`include "defines.vh"
6431
6432wire [2:0] mycid;
6433wire [2:0] mytid;
6434wire [5:0] mytnum;
6435
6436integer junk;
6437reg ready;
6438reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
6439reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
6440
6441reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
6442reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
6443
6444reg update_dfesr_w;
6445
6446reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
6447reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
6448
6449reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
6450reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
6451
6452reg sync_asi;
6453reg chk_if_asi_ld;
6454reg [63:0] ld_data_w;
6455
6456reg desr_asi_rd, desr_wr, desr_pend_wr;
6457
6458assign mycid = 2;
6459assign mytid = 6;
6460assign mytnum = 2*8 + 6;
6461
6462initial begin //{
6463 desr_asi_rd = 1'b0;
6464 desr_pend_wr = 1'b0;
6465 ready = 0;
6466 @(posedge `SPC2.l2clk) ;
6467 @(posedge `SPC2.l2clk) ;
6468 ready = `PARGS.err_sync_on;
6469end //}
6470
6471`define DSFSR_NEW_IN_22 `SPC2.tlu.ras.dsfsr_6_new_in
6472`define ISFSR_NEW_IN_22 `SPC2.tlu.ras.isfsr_6_new_in
6473
6474`define DSFSR_22 `SPC2.tlu.ras.dsfsr_6
6475`define ISFSR_22 `SPC2.tlu.ras.isfsr_6
6476`define DSFAR_22 `SPC2.tlu.dfd.dsfar_6
6477
6478`define ASI_WR_DSFSR_22 `SPC2.tlu.ras.asi_wr_dsfsr[6]
6479`define ASI_WR_ISFSR_22 `SPC2.tlu.ras.asi_wr_isfsr[6]
6480
6481`define RAS_WRITE_DESR_1st_22 `SPC2.tlu.dfd.ras_write_desr_1st[6]
6482`define RAS_WRITE_DESR_2nd_22 `SPC2.tlu.dfd.ras_write_desr_2nd[6]
6483`define DESR_asi_rd_22 `SPC2.tlu.ras_rd_desr[6]
6484`define DESR_22 `SPC2.tlu.dfd.desr_6
6485
6486`define RAS_WRITE_FESR_22 `SPC2.tlu.ras.write_fesr[6]
6487`define FESR_22 `SPC2.tlu.dfd.fesr_6
6488
6489`define ST_ERR_22 `SPC2.tlu.trl1.take_ftt & `SPC2.tlu.trl1.trap[2]
6490`define SW_REC_ERR_22 `SPC2.tlu.trl1.take_ade & `SPC2.tlu.trl1.trap[2]
6491`define DATA_ACC_ERR_22 `SPC2.tlu.trl1.take_dae & `SPC2.tlu.trl1.trap[2]
6492`define INST_ACC_ERR_22 `SPC2.tlu.trl1.take_iae & `SPC2.tlu.trl1.trap[2]
6493`define INT_PROC_ERR_22 `SPC2.tlu.trl1.take_ipe & `SPC2.tlu.trl1.trap[2]
6494`define HW_CORR_ERR_22 `SPC2.tlu.trl1.take_eer & `SPC2.tlu.trl1.trap[2]
6495`define INST_ACC_MMU_ERR_22 `SPC2.tlu.trl1.take_ime & `SPC2.tlu.trl1.trap[2]
6496`define DATA_ACC_MMU_ERR_22 `SPC2.tlu.trl1.take_dme & `SPC2.tlu.trl1.trap[2]
6497
6498`define LSU_LD_VALID_B `PROBES2.lsu_ld_valid
6499`define LSU_TID_DEC_B_22 `PROBES2.lsu_tid_dec_b[6]
6500`define ASI_LD_22 `SPC2.lsu.lmd.lmq6_pkt[60] & (`SPC2.lsu.lmd.lmq6_pkt[49:48] == 2'b0)
6501`define ASI_22 `SPC2.lsu.lmd.lmq6_pkt[47:40]
6502`define ASI_ADDR_22 `SPC2.lsu.lmd.lmq6_pkt[39:0]
6503`define ASI_LD_DATA_22 `SPC2.lsu_exu_ld_data_b[63:0]
6504`define ASI_LD_COMP_22 tb_top.nas_top.c2.t6.complete_fw2
6505
6506//SPU specific - only one SPU per core
6507`define SPU_MA_BUSY_2 `SPC2.spu.spu_pmu_ma_busy[3]
6508`define SPU_MA_TID_2 `SPC2.spu.spu_pmu_ma_busy[2:0]
6509
6510////////////////////////////////////////////////////////////////////////////////
6511//Capture the status register data from rtl. For disrupting traps,
6512//rtl can modify the contents of the status register before the
6513//trap is taken and intp message is sent to Riesling.
6514//For precise traps, once the status register is updated rtl can't
6515//change the register again before jumping to the trap handler.
6516//So, for deferred and disrupting traps, inform Riesling when the
6517//register is modified while for precise traps wait until Fw2 before
6518//telling Riesling.
6519
6520//TLU asserts the flush and input signals in W stage. I latch them at the
6521//+ve edge of FX4.
6522
6523always @(negedge (`SPC2.l2clk & ready))
6524begin // {
6525 if (`DESR_asi_rd_22)
6526 desr_asi_rd <= 1'b1;
6527 if (desr_asi_rd)
6528 begin
6529 if (desr_wr)
6530 desr_pend_wr <= 1'b1;
6531 if (`ASI_LD_COMP_22[2])
6532 desr_asi_rd <= 1'b0;
6533 end
6534
6535 update_dsfsr_w <= (`DSFSR_NEW_IN_22 != 4'b0) && ~`ASI_WR_DSFSR_22;
6536 update_isfsr_w <= (`ISFSR_NEW_IN_22 != 3'b0) && ~`ASI_WR_ISFSR_22;
6537 desr_wr <= (`RAS_WRITE_DESR_1st_22 || `RAS_WRITE_DESR_2nd_22);
6538 update_dfesr_w <= `RAS_WRITE_FESR_22;
6539 take_err_trap_fx4 <= `ST_ERR_22 | `SW_REC_ERR_22 | `DATA_ACC_ERR_22
6540 | `INST_ACC_ERR_22 | `INT_PROC_ERR_22
6541 | `HW_CORR_ERR_22 | `INST_ACC_MMU_ERR_22
6542 | `DATA_ACC_MMU_ERR_22 ;
6543
6544
6545 if (`ST_ERR_22) int_num_fx4 <= 8'h07;
6546 if (`SW_REC_ERR_22) int_num_fx4 <= 8'h40;
6547 if (`DATA_ACC_ERR_22) int_num_fx4 <= 8'h32;
6548 if (`INST_ACC_ERR_22) int_num_fx4 <= 8'h0A;
6549 if (`INT_PROC_ERR_22) int_num_fx4 <= 8'h29;
6550 if (`HW_CORR_ERR_22) int_num_fx4 <= 8'h63;
6551 if (`INST_ACC_MMU_ERR_22) int_num_fx4 <= 8'h71;
6552 if (`DATA_ACC_MMU_ERR_22) int_num_fx4 <= 8'h72;
6553
6554 update_dsfsr_fx4 <= update_dsfsr_w;
6555 update_dsfsr_fx5 <= update_dsfsr_fx4;
6556 update_dsfsr_fb <= update_dsfsr_fx5;
6557 update_dsfsr_fw <= update_dsfsr_fb;
6558 update_dsfsr_fw1 <= update_dsfsr_fw;
6559 update_dsfsr_fw2 <= update_dsfsr_fw1;
6560
6561 update_isfsr_fx4 <= update_isfsr_w;
6562 update_isfsr_fx5 <= update_isfsr_fx4;
6563 update_isfsr_fb <= update_isfsr_fx5;
6564 update_isfsr_fw <= update_isfsr_fb;
6565 update_isfsr_fw1 <= update_isfsr_fw;
6566 update_isfsr_fw2 <= update_isfsr_fw1;
6567
6568 take_err_trap_fx5 <= take_err_trap_fx4;
6569 take_err_trap_fb <= take_err_trap_fx5;
6570 take_err_trap_fw <= take_err_trap_fb;
6571 take_err_trap_fw1 <= take_err_trap_fw;
6572 take_err_trap_fw2 <= take_err_trap_fw1;
6573
6574 int_num_fx5 <= int_num_fx4;
6575 int_num_fb <= int_num_fx5;
6576 int_num_fw <= int_num_fb;
6577 int_num_fw1 <= int_num_fw;
6578 int_num_fw2 <= int_num_fw1;
6579
6580 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
6581 begin // {
6582 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
6583 begin //{
6584 desr_pend_wr <= 1'b0;
6585 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_22[63:56], 45'b0, `DESR_22[10:0]});
6586 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_22[63:56], 45'b0, `DESR_22[10:0]});
6587 end //}
6588 //if (update_dfesr_w)
6589 if (`ST_ERR_22)
6590 begin //{
6591 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_22[61:55], 55'b0});
6592 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_22[61:55], 55'b0});
6593 end //}
6594 if (update_dsfsr_fw2)
6595 begin //{
6596 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
6597 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_22[3:0]});
6598 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_22[47:0]});
6599
6600 end //}
6601 if (update_isfsr_fw2)
6602 begin //{
6603 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
6604 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_22[2:0]});
6605 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_22[47:0]});
6606
6607 end //}
6608 if (take_err_trap_fw2)
6609 begin //{
6610 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
6611 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
6612 end // }
6613 end // }
6614
6615end //}
6616
6617//removing the addr check as the LSU doesn't flag an invalid_asi_exception
6618//if the addr of diagnostic accesses is not in the valid range. The inst.
6619//still executes. LSU expects that HP won't use addresses in invalid range.
6620
6621always @(negedge (`SPC2.l2clk & ready))
6622begin // {
6623 sync_asi = 1'b0;
6624 ld_data_w <= `ASI_LD_DATA_22;
6625
6626 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_22)
6627 chk_if_asi_ld <= 1'b1;
6628 else
6629 chk_if_asi_ld <= 1'b0;
6630
6631 if (chk_if_asi_ld & `ASI_LD_22)
6632 begin
6633 case (`ASI_22)
6634 8'h66: //ASI_IC_INSTR
6635 begin
6636 //if ((`ASI_ADDR_22 >= 0) & (`ASI_ADDR_22 <= 40'h7ff8))
6637 sync_asi = 1'b1;
6638 end
6639 8'h67: //ASI_IC_TAG
6640 begin
6641 //if ((`ASI_ADDR_22 >= 0) & (`ASI_ADDR_22 <= 40'h7fe0))
6642 sync_asi = 1'b1;
6643 end
6644 8'h46: //ASI_DC_DATA
6645 begin
6646 sync_asi = 1'b1;
6647 end
6648 8'h47: //ASI_DC_TAG
6649 begin
6650 //if ((`ASI_ADDR_22 >= 0) & (`ASI_ADDR_22 <= 40'h7ff0))
6651 sync_asi = 1'b1;
6652 end
6653 8'h48://IRF ECC
6654 begin
6655 //if ((`ASI_ADDR_22 >= 0) & (`ASI_ADDR_22 <= 40'hF8))
6656 sync_asi = 1'b1;
6657 end
6658 8'h49://FRF ECC
6659 begin
6660 //if ((`ASI_ADDR_22 >= 0) & (`ASI_ADDR_22 <= 40'hF8))
6661 sync_asi = 1'b1;
6662 end
6663 8'h4A://STB access, stb ptr can be read also
6664 begin
6665 //if ((`ASI_ADDR_22 >= 0) & (`ASI_ADDR_22 <= 40'h100))
6666 sync_asi = 1'b1;
6667 end
6668 8'h5A://Tick compare reg
6669 begin
6670 //if ((`ASI_ADDR_22 >= 0) & (`ASI_ADDR_22 <= 40'h38))
6671 sync_asi = 1'b1;
6672 end
6673 8'h5B://TSA
6674 begin
6675 //if ((`ASI_ADDR_22 >= 0) & (`ASI_ADDR_22 <= 40'h38))
6676 sync_asi = 1'b1;
6677 end
6678 8'h51://MRA
6679 begin
6680 //if ((`ASI_ADDR_22 >= 0) & (`ASI_ADDR_22 <= 40'h38))
6681 sync_asi = 1'b1;
6682 end
6683 8'h59://scratchpad ecc data read
6684 begin
6685 //if ((`ASI_ADDR_22 >= 0) & (`ASI_ADDR_22 <= 40'h38))
6686 //syncup the ecc data only. For ecc bit 6 is 0.
6687 if (~`SPC2.lsu.lmd.lmq6_pkt[6])
6688 sync_asi = 1'b1;
6689 end
6690 8'h40://cwqcsr,ma_sync access
6691 begin
6692 if ((`ASI_ADDR_22 == 40'h20) || (`ASI_ADDR_22 == 40'h30)
6693 || (`ASI_ADDR_22 == 40'h80)
6694 || ((`ASI_ADDR_22 == 40'ha0) & (`SPU_MA_BUSY_2 == 0) & (`SPU_MA_TID_2 == 6))
6695 )
6696 sync_asi = 1'b1;
6697 end
6698 8'h4C://CLESR, CLFESR access
6699 begin
6700 if ((`ASI_ADDR_22 == 40'h20) || (`ASI_ADDR_22 == 40'h28))
6701 sync_asi = 1'b1;
6702 end
6703 endcase
6704 end
6705
6706 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
6707 begin
6708 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_22, `ASI_ADDR_22, ld_data_w);
6709 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_22, {24'b0, `ASI_ADDR_22}, ld_data_w[63:0]);
6710 end
6711end //}
6712`endif
6713endmodule
6714
6715
6716
6717module err_c2t7 ();
6718`ifndef GATESIM
6719
6720`include "defines.vh"
6721
6722wire [2:0] mycid;
6723wire [2:0] mytid;
6724wire [5:0] mytnum;
6725
6726integer junk;
6727reg ready;
6728reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
6729reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
6730
6731reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
6732reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
6733
6734reg update_dfesr_w;
6735
6736reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
6737reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
6738
6739reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
6740reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
6741
6742reg sync_asi;
6743reg chk_if_asi_ld;
6744reg [63:0] ld_data_w;
6745
6746reg desr_asi_rd, desr_wr, desr_pend_wr;
6747
6748assign mycid = 2;
6749assign mytid = 7;
6750assign mytnum = 2*8 + 7;
6751
6752initial begin //{
6753 desr_asi_rd = 1'b0;
6754 desr_pend_wr = 1'b0;
6755 ready = 0;
6756 @(posedge `SPC2.l2clk) ;
6757 @(posedge `SPC2.l2clk) ;
6758 ready = `PARGS.err_sync_on;
6759end //}
6760
6761`define DSFSR_NEW_IN_23 `SPC2.tlu.ras.dsfsr_7_new_in
6762`define ISFSR_NEW_IN_23 `SPC2.tlu.ras.isfsr_7_new_in
6763
6764`define DSFSR_23 `SPC2.tlu.ras.dsfsr_7
6765`define ISFSR_23 `SPC2.tlu.ras.isfsr_7
6766`define DSFAR_23 `SPC2.tlu.dfd.dsfar_7
6767
6768`define ASI_WR_DSFSR_23 `SPC2.tlu.ras.asi_wr_dsfsr[7]
6769`define ASI_WR_ISFSR_23 `SPC2.tlu.ras.asi_wr_isfsr[7]
6770
6771`define RAS_WRITE_DESR_1st_23 `SPC2.tlu.dfd.ras_write_desr_1st[7]
6772`define RAS_WRITE_DESR_2nd_23 `SPC2.tlu.dfd.ras_write_desr_2nd[7]
6773`define DESR_asi_rd_23 `SPC2.tlu.ras_rd_desr[7]
6774`define DESR_23 `SPC2.tlu.dfd.desr_7
6775
6776`define RAS_WRITE_FESR_23 `SPC2.tlu.ras.write_fesr[7]
6777`define FESR_23 `SPC2.tlu.dfd.fesr_7
6778
6779`define ST_ERR_23 `SPC2.tlu.trl1.take_ftt & `SPC2.tlu.trl1.trap[3]
6780`define SW_REC_ERR_23 `SPC2.tlu.trl1.take_ade & `SPC2.tlu.trl1.trap[3]
6781`define DATA_ACC_ERR_23 `SPC2.tlu.trl1.take_dae & `SPC2.tlu.trl1.trap[3]
6782`define INST_ACC_ERR_23 `SPC2.tlu.trl1.take_iae & `SPC2.tlu.trl1.trap[3]
6783`define INT_PROC_ERR_23 `SPC2.tlu.trl1.take_ipe & `SPC2.tlu.trl1.trap[3]
6784`define HW_CORR_ERR_23 `SPC2.tlu.trl1.take_eer & `SPC2.tlu.trl1.trap[3]
6785`define INST_ACC_MMU_ERR_23 `SPC2.tlu.trl1.take_ime & `SPC2.tlu.trl1.trap[3]
6786`define DATA_ACC_MMU_ERR_23 `SPC2.tlu.trl1.take_dme & `SPC2.tlu.trl1.trap[3]
6787
6788`define LSU_LD_VALID_B `PROBES2.lsu_ld_valid
6789`define LSU_TID_DEC_B_23 `PROBES2.lsu_tid_dec_b[7]
6790`define ASI_LD_23 `SPC2.lsu.lmd.lmq7_pkt[60] & (`SPC2.lsu.lmd.lmq7_pkt[49:48] == 2'b0)
6791`define ASI_23 `SPC2.lsu.lmd.lmq7_pkt[47:40]
6792`define ASI_ADDR_23 `SPC2.lsu.lmd.lmq7_pkt[39:0]
6793`define ASI_LD_DATA_23 `SPC2.lsu_exu_ld_data_b[63:0]
6794`define ASI_LD_COMP_23 tb_top.nas_top.c2.t7.complete_fw2
6795
6796//SPU specific - only one SPU per core
6797`define SPU_MA_BUSY_2 `SPC2.spu.spu_pmu_ma_busy[3]
6798`define SPU_MA_TID_2 `SPC2.spu.spu_pmu_ma_busy[2:0]
6799
6800////////////////////////////////////////////////////////////////////////////////
6801//Capture the status register data from rtl. For disrupting traps,
6802//rtl can modify the contents of the status register before the
6803//trap is taken and intp message is sent to Riesling.
6804//For precise traps, once the status register is updated rtl can't
6805//change the register again before jumping to the trap handler.
6806//So, for deferred and disrupting traps, inform Riesling when the
6807//register is modified while for precise traps wait until Fw2 before
6808//telling Riesling.
6809
6810//TLU asserts the flush and input signals in W stage. I latch them at the
6811//+ve edge of FX4.
6812
6813always @(negedge (`SPC2.l2clk & ready))
6814begin // {
6815 if (`DESR_asi_rd_23)
6816 desr_asi_rd <= 1'b1;
6817 if (desr_asi_rd)
6818 begin
6819 if (desr_wr)
6820 desr_pend_wr <= 1'b1;
6821 if (`ASI_LD_COMP_23[2])
6822 desr_asi_rd <= 1'b0;
6823 end
6824
6825 update_dsfsr_w <= (`DSFSR_NEW_IN_23 != 4'b0) && ~`ASI_WR_DSFSR_23;
6826 update_isfsr_w <= (`ISFSR_NEW_IN_23 != 3'b0) && ~`ASI_WR_ISFSR_23;
6827 desr_wr <= (`RAS_WRITE_DESR_1st_23 || `RAS_WRITE_DESR_2nd_23);
6828 update_dfesr_w <= `RAS_WRITE_FESR_23;
6829 take_err_trap_fx4 <= `ST_ERR_23 | `SW_REC_ERR_23 | `DATA_ACC_ERR_23
6830 | `INST_ACC_ERR_23 | `INT_PROC_ERR_23
6831 | `HW_CORR_ERR_23 | `INST_ACC_MMU_ERR_23
6832 | `DATA_ACC_MMU_ERR_23 ;
6833
6834
6835 if (`ST_ERR_23) int_num_fx4 <= 8'h07;
6836 if (`SW_REC_ERR_23) int_num_fx4 <= 8'h40;
6837 if (`DATA_ACC_ERR_23) int_num_fx4 <= 8'h32;
6838 if (`INST_ACC_ERR_23) int_num_fx4 <= 8'h0A;
6839 if (`INT_PROC_ERR_23) int_num_fx4 <= 8'h29;
6840 if (`HW_CORR_ERR_23) int_num_fx4 <= 8'h63;
6841 if (`INST_ACC_MMU_ERR_23) int_num_fx4 <= 8'h71;
6842 if (`DATA_ACC_MMU_ERR_23) int_num_fx4 <= 8'h72;
6843
6844 update_dsfsr_fx4 <= update_dsfsr_w;
6845 update_dsfsr_fx5 <= update_dsfsr_fx4;
6846 update_dsfsr_fb <= update_dsfsr_fx5;
6847 update_dsfsr_fw <= update_dsfsr_fb;
6848 update_dsfsr_fw1 <= update_dsfsr_fw;
6849 update_dsfsr_fw2 <= update_dsfsr_fw1;
6850
6851 update_isfsr_fx4 <= update_isfsr_w;
6852 update_isfsr_fx5 <= update_isfsr_fx4;
6853 update_isfsr_fb <= update_isfsr_fx5;
6854 update_isfsr_fw <= update_isfsr_fb;
6855 update_isfsr_fw1 <= update_isfsr_fw;
6856 update_isfsr_fw2 <= update_isfsr_fw1;
6857
6858 take_err_trap_fx5 <= take_err_trap_fx4;
6859 take_err_trap_fb <= take_err_trap_fx5;
6860 take_err_trap_fw <= take_err_trap_fb;
6861 take_err_trap_fw1 <= take_err_trap_fw;
6862 take_err_trap_fw2 <= take_err_trap_fw1;
6863
6864 int_num_fx5 <= int_num_fx4;
6865 int_num_fb <= int_num_fx5;
6866 int_num_fw <= int_num_fb;
6867 int_num_fw1 <= int_num_fw;
6868 int_num_fw2 <= int_num_fw1;
6869
6870 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
6871 begin // {
6872 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
6873 begin //{
6874 desr_pend_wr <= 1'b0;
6875 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_23[63:56], 45'b0, `DESR_23[10:0]});
6876 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_23[63:56], 45'b0, `DESR_23[10:0]});
6877 end //}
6878 //if (update_dfesr_w)
6879 if (`ST_ERR_23)
6880 begin //{
6881 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_23[61:55], 55'b0});
6882 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_23[61:55], 55'b0});
6883 end //}
6884 if (update_dsfsr_fw2)
6885 begin //{
6886 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
6887 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_23[3:0]});
6888 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_23[47:0]});
6889
6890 end //}
6891 if (update_isfsr_fw2)
6892 begin //{
6893 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
6894 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_23[2:0]});
6895 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_23[47:0]});
6896
6897 end //}
6898 if (take_err_trap_fw2)
6899 begin //{
6900 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
6901 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
6902 end // }
6903 end // }
6904
6905end //}
6906
6907//removing the addr check as the LSU doesn't flag an invalid_asi_exception
6908//if the addr of diagnostic accesses is not in the valid range. The inst.
6909//still executes. LSU expects that HP won't use addresses in invalid range.
6910
6911always @(negedge (`SPC2.l2clk & ready))
6912begin // {
6913 sync_asi = 1'b0;
6914 ld_data_w <= `ASI_LD_DATA_23;
6915
6916 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_23)
6917 chk_if_asi_ld <= 1'b1;
6918 else
6919 chk_if_asi_ld <= 1'b0;
6920
6921 if (chk_if_asi_ld & `ASI_LD_23)
6922 begin
6923 case (`ASI_23)
6924 8'h66: //ASI_IC_INSTR
6925 begin
6926 //if ((`ASI_ADDR_23 >= 0) & (`ASI_ADDR_23 <= 40'h7ff8))
6927 sync_asi = 1'b1;
6928 end
6929 8'h67: //ASI_IC_TAG
6930 begin
6931 //if ((`ASI_ADDR_23 >= 0) & (`ASI_ADDR_23 <= 40'h7fe0))
6932 sync_asi = 1'b1;
6933 end
6934 8'h46: //ASI_DC_DATA
6935 begin
6936 sync_asi = 1'b1;
6937 end
6938 8'h47: //ASI_DC_TAG
6939 begin
6940 //if ((`ASI_ADDR_23 >= 0) & (`ASI_ADDR_23 <= 40'h7ff0))
6941 sync_asi = 1'b1;
6942 end
6943 8'h48://IRF ECC
6944 begin
6945 //if ((`ASI_ADDR_23 >= 0) & (`ASI_ADDR_23 <= 40'hF8))
6946 sync_asi = 1'b1;
6947 end
6948 8'h49://FRF ECC
6949 begin
6950 //if ((`ASI_ADDR_23 >= 0) & (`ASI_ADDR_23 <= 40'hF8))
6951 sync_asi = 1'b1;
6952 end
6953 8'h4A://STB access, stb ptr can be read also
6954 begin
6955 //if ((`ASI_ADDR_23 >= 0) & (`ASI_ADDR_23 <= 40'h100))
6956 sync_asi = 1'b1;
6957 end
6958 8'h5A://Tick compare reg
6959 begin
6960 //if ((`ASI_ADDR_23 >= 0) & (`ASI_ADDR_23 <= 40'h38))
6961 sync_asi = 1'b1;
6962 end
6963 8'h5B://TSA
6964 begin
6965 //if ((`ASI_ADDR_23 >= 0) & (`ASI_ADDR_23 <= 40'h38))
6966 sync_asi = 1'b1;
6967 end
6968 8'h51://MRA
6969 begin
6970 //if ((`ASI_ADDR_23 >= 0) & (`ASI_ADDR_23 <= 40'h38))
6971 sync_asi = 1'b1;
6972 end
6973 8'h59://scratchpad ecc data read
6974 begin
6975 //if ((`ASI_ADDR_23 >= 0) & (`ASI_ADDR_23 <= 40'h38))
6976 //syncup the ecc data only. For ecc bit 6 is 0.
6977 if (~`SPC2.lsu.lmd.lmq7_pkt[6])
6978 sync_asi = 1'b1;
6979 end
6980 8'h40://cwqcsr,ma_sync access
6981 begin
6982 if ((`ASI_ADDR_23 == 40'h20) || (`ASI_ADDR_23 == 40'h30)
6983 || (`ASI_ADDR_23 == 40'h80)
6984 || ((`ASI_ADDR_23 == 40'ha0) & (`SPU_MA_BUSY_2 == 0) & (`SPU_MA_TID_2 == 7))
6985 )
6986 sync_asi = 1'b1;
6987 end
6988 8'h4C://CLESR, CLFESR access
6989 begin
6990 if ((`ASI_ADDR_23 == 40'h20) || (`ASI_ADDR_23 == 40'h28))
6991 sync_asi = 1'b1;
6992 end
6993 endcase
6994 end
6995
6996 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
6997 begin
6998 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_23, `ASI_ADDR_23, ld_data_w);
6999 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_23, {24'b0, `ASI_ADDR_23}, ld_data_w[63:0]);
7000 end
7001end //}
7002`endif
7003endmodule
7004
7005`endif
7006
7007`ifdef CORE_3
7008
7009
7010
7011module err_c3t0 ();
7012`ifndef GATESIM
7013
7014`include "defines.vh"
7015
7016wire [2:0] mycid;
7017wire [2:0] mytid;
7018wire [5:0] mytnum;
7019
7020integer junk;
7021reg ready;
7022reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
7023reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
7024
7025reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
7026reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
7027
7028reg update_dfesr_w;
7029
7030reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
7031reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
7032
7033reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
7034reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
7035
7036reg sync_asi;
7037reg chk_if_asi_ld;
7038reg [63:0] ld_data_w;
7039
7040reg desr_asi_rd, desr_wr, desr_pend_wr;
7041
7042assign mycid = 3;
7043assign mytid = 0;
7044assign mytnum = 3*8 + 0;
7045
7046initial begin //{
7047 desr_asi_rd = 1'b0;
7048 desr_pend_wr = 1'b0;
7049 ready = 0;
7050 @(posedge `SPC3.l2clk) ;
7051 @(posedge `SPC3.l2clk) ;
7052 ready = `PARGS.err_sync_on;
7053end //}
7054
7055`define DSFSR_NEW_IN_24 `SPC3.tlu.ras.dsfsr_0_new_in
7056`define ISFSR_NEW_IN_24 `SPC3.tlu.ras.isfsr_0_new_in
7057
7058`define DSFSR_24 `SPC3.tlu.ras.dsfsr_0
7059`define ISFSR_24 `SPC3.tlu.ras.isfsr_0
7060`define DSFAR_24 `SPC3.tlu.dfd.dsfar_0
7061
7062`define ASI_WR_DSFSR_24 `SPC3.tlu.ras.asi_wr_dsfsr[0]
7063`define ASI_WR_ISFSR_24 `SPC3.tlu.ras.asi_wr_isfsr[0]
7064
7065`define RAS_WRITE_DESR_1st_24 `SPC3.tlu.dfd.ras_write_desr_1st[0]
7066`define RAS_WRITE_DESR_2nd_24 `SPC3.tlu.dfd.ras_write_desr_2nd[0]
7067`define DESR_asi_rd_24 `SPC3.tlu.ras_rd_desr[0]
7068`define DESR_24 `SPC3.tlu.dfd.desr_0
7069
7070`define RAS_WRITE_FESR_24 `SPC3.tlu.ras.write_fesr[0]
7071`define FESR_24 `SPC3.tlu.dfd.fesr_0
7072
7073`define ST_ERR_24 `SPC3.tlu.trl0.take_ftt & `SPC3.tlu.trl0.trap[0]
7074`define SW_REC_ERR_24 `SPC3.tlu.trl0.take_ade & `SPC3.tlu.trl0.trap[0]
7075`define DATA_ACC_ERR_24 `SPC3.tlu.trl0.take_dae & `SPC3.tlu.trl0.trap[0]
7076`define INST_ACC_ERR_24 `SPC3.tlu.trl0.take_iae & `SPC3.tlu.trl0.trap[0]
7077`define INT_PROC_ERR_24 `SPC3.tlu.trl0.take_ipe & `SPC3.tlu.trl0.trap[0]
7078`define HW_CORR_ERR_24 `SPC3.tlu.trl0.take_eer & `SPC3.tlu.trl0.trap[0]
7079`define INST_ACC_MMU_ERR_24 `SPC3.tlu.trl0.take_ime & `SPC3.tlu.trl0.trap[0]
7080`define DATA_ACC_MMU_ERR_24 `SPC3.tlu.trl0.take_dme & `SPC3.tlu.trl0.trap[0]
7081
7082`define LSU_LD_VALID_B `PROBES3.lsu_ld_valid
7083`define LSU_TID_DEC_B_24 `PROBES3.lsu_tid_dec_b[0]
7084`define ASI_LD_24 `SPC3.lsu.lmd.lmq0_pkt[60] & (`SPC3.lsu.lmd.lmq0_pkt[49:48] == 2'b0)
7085`define ASI_24 `SPC3.lsu.lmd.lmq0_pkt[47:40]
7086`define ASI_ADDR_24 `SPC3.lsu.lmd.lmq0_pkt[39:0]
7087`define ASI_LD_DATA_24 `SPC3.lsu_exu_ld_data_b[63:0]
7088`define ASI_LD_COMP_24 tb_top.nas_top.c3.t0.complete_fw2
7089
7090//SPU specific - only one SPU per core
7091`define SPU_MA_BUSY_3 `SPC3.spu.spu_pmu_ma_busy[3]
7092`define SPU_MA_TID_3 `SPC3.spu.spu_pmu_ma_busy[2:0]
7093
7094////////////////////////////////////////////////////////////////////////////////
7095//Capture the status register data from rtl. For disrupting traps,
7096//rtl can modify the contents of the status register before the
7097//trap is taken and intp message is sent to Riesling.
7098//For precise traps, once the status register is updated rtl can't
7099//change the register again before jumping to the trap handler.
7100//So, for deferred and disrupting traps, inform Riesling when the
7101//register is modified while for precise traps wait until Fw2 before
7102//telling Riesling.
7103
7104//TLU asserts the flush and input signals in W stage. I latch them at the
7105//+ve edge of FX4.
7106
7107always @(negedge (`SPC3.l2clk & ready))
7108begin // {
7109 if (`DESR_asi_rd_24)
7110 desr_asi_rd <= 1'b1;
7111 if (desr_asi_rd)
7112 begin
7113 if (desr_wr)
7114 desr_pend_wr <= 1'b1;
7115 if (`ASI_LD_COMP_24[2])
7116 desr_asi_rd <= 1'b0;
7117 end
7118
7119 update_dsfsr_w <= (`DSFSR_NEW_IN_24 != 4'b0) && ~`ASI_WR_DSFSR_24;
7120 update_isfsr_w <= (`ISFSR_NEW_IN_24 != 3'b0) && ~`ASI_WR_ISFSR_24;
7121 desr_wr <= (`RAS_WRITE_DESR_1st_24 || `RAS_WRITE_DESR_2nd_24);
7122 update_dfesr_w <= `RAS_WRITE_FESR_24;
7123 take_err_trap_fx4 <= `ST_ERR_24 | `SW_REC_ERR_24 | `DATA_ACC_ERR_24
7124 | `INST_ACC_ERR_24 | `INT_PROC_ERR_24
7125 | `HW_CORR_ERR_24 | `INST_ACC_MMU_ERR_24
7126 | `DATA_ACC_MMU_ERR_24 ;
7127
7128
7129 if (`ST_ERR_24) int_num_fx4 <= 8'h07;
7130 if (`SW_REC_ERR_24) int_num_fx4 <= 8'h40;
7131 if (`DATA_ACC_ERR_24) int_num_fx4 <= 8'h32;
7132 if (`INST_ACC_ERR_24) int_num_fx4 <= 8'h0A;
7133 if (`INT_PROC_ERR_24) int_num_fx4 <= 8'h29;
7134 if (`HW_CORR_ERR_24) int_num_fx4 <= 8'h63;
7135 if (`INST_ACC_MMU_ERR_24) int_num_fx4 <= 8'h71;
7136 if (`DATA_ACC_MMU_ERR_24) int_num_fx4 <= 8'h72;
7137
7138 update_dsfsr_fx4 <= update_dsfsr_w;
7139 update_dsfsr_fx5 <= update_dsfsr_fx4;
7140 update_dsfsr_fb <= update_dsfsr_fx5;
7141 update_dsfsr_fw <= update_dsfsr_fb;
7142 update_dsfsr_fw1 <= update_dsfsr_fw;
7143 update_dsfsr_fw2 <= update_dsfsr_fw1;
7144
7145 update_isfsr_fx4 <= update_isfsr_w;
7146 update_isfsr_fx5 <= update_isfsr_fx4;
7147 update_isfsr_fb <= update_isfsr_fx5;
7148 update_isfsr_fw <= update_isfsr_fb;
7149 update_isfsr_fw1 <= update_isfsr_fw;
7150 update_isfsr_fw2 <= update_isfsr_fw1;
7151
7152 take_err_trap_fx5 <= take_err_trap_fx4;
7153 take_err_trap_fb <= take_err_trap_fx5;
7154 take_err_trap_fw <= take_err_trap_fb;
7155 take_err_trap_fw1 <= take_err_trap_fw;
7156 take_err_trap_fw2 <= take_err_trap_fw1;
7157
7158 int_num_fx5 <= int_num_fx4;
7159 int_num_fb <= int_num_fx5;
7160 int_num_fw <= int_num_fb;
7161 int_num_fw1 <= int_num_fw;
7162 int_num_fw2 <= int_num_fw1;
7163
7164 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
7165 begin // {
7166 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
7167 begin //{
7168 desr_pend_wr <= 1'b0;
7169 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_24[63:56], 45'b0, `DESR_24[10:0]});
7170 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_24[63:56], 45'b0, `DESR_24[10:0]});
7171 end //}
7172 //if (update_dfesr_w)
7173 if (`ST_ERR_24)
7174 begin //{
7175 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_24[61:55], 55'b0});
7176 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_24[61:55], 55'b0});
7177 end //}
7178 if (update_dsfsr_fw2)
7179 begin //{
7180 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
7181 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_24[3:0]});
7182 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_24[47:0]});
7183
7184 end //}
7185 if (update_isfsr_fw2)
7186 begin //{
7187 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
7188 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_24[2:0]});
7189 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_24[47:0]});
7190
7191 end //}
7192 if (take_err_trap_fw2)
7193 begin //{
7194 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
7195 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
7196 end // }
7197 end // }
7198
7199end //}
7200
7201//removing the addr check as the LSU doesn't flag an invalid_asi_exception
7202//if the addr of diagnostic accesses is not in the valid range. The inst.
7203//still executes. LSU expects that HP won't use addresses in invalid range.
7204
7205always @(negedge (`SPC3.l2clk & ready))
7206begin // {
7207 sync_asi = 1'b0;
7208 ld_data_w <= `ASI_LD_DATA_24;
7209
7210 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_24)
7211 chk_if_asi_ld <= 1'b1;
7212 else
7213 chk_if_asi_ld <= 1'b0;
7214
7215 if (chk_if_asi_ld & `ASI_LD_24)
7216 begin
7217 case (`ASI_24)
7218 8'h66: //ASI_IC_INSTR
7219 begin
7220 //if ((`ASI_ADDR_24 >= 0) & (`ASI_ADDR_24 <= 40'h7ff8))
7221 sync_asi = 1'b1;
7222 end
7223 8'h67: //ASI_IC_TAG
7224 begin
7225 //if ((`ASI_ADDR_24 >= 0) & (`ASI_ADDR_24 <= 40'h7fe0))
7226 sync_asi = 1'b1;
7227 end
7228 8'h46: //ASI_DC_DATA
7229 begin
7230 sync_asi = 1'b1;
7231 end
7232 8'h47: //ASI_DC_TAG
7233 begin
7234 //if ((`ASI_ADDR_24 >= 0) & (`ASI_ADDR_24 <= 40'h7ff0))
7235 sync_asi = 1'b1;
7236 end
7237 8'h48://IRF ECC
7238 begin
7239 //if ((`ASI_ADDR_24 >= 0) & (`ASI_ADDR_24 <= 40'hF8))
7240 sync_asi = 1'b1;
7241 end
7242 8'h49://FRF ECC
7243 begin
7244 //if ((`ASI_ADDR_24 >= 0) & (`ASI_ADDR_24 <= 40'hF8))
7245 sync_asi = 1'b1;
7246 end
7247 8'h4A://STB access, stb ptr can be read also
7248 begin
7249 //if ((`ASI_ADDR_24 >= 0) & (`ASI_ADDR_24 <= 40'h100))
7250 sync_asi = 1'b1;
7251 end
7252 8'h5A://Tick compare reg
7253 begin
7254 //if ((`ASI_ADDR_24 >= 0) & (`ASI_ADDR_24 <= 40'h38))
7255 sync_asi = 1'b1;
7256 end
7257 8'h5B://TSA
7258 begin
7259 //if ((`ASI_ADDR_24 >= 0) & (`ASI_ADDR_24 <= 40'h38))
7260 sync_asi = 1'b1;
7261 end
7262 8'h51://MRA
7263 begin
7264 //if ((`ASI_ADDR_24 >= 0) & (`ASI_ADDR_24 <= 40'h38))
7265 sync_asi = 1'b1;
7266 end
7267 8'h59://scratchpad ecc data read
7268 begin
7269 //if ((`ASI_ADDR_24 >= 0) & (`ASI_ADDR_24 <= 40'h38))
7270 //syncup the ecc data only. For ecc bit 6 is 0.
7271 if (~`SPC3.lsu.lmd.lmq0_pkt[6])
7272 sync_asi = 1'b1;
7273 end
7274 8'h40://cwqcsr,ma_sync access
7275 begin
7276 if ((`ASI_ADDR_24 == 40'h20) || (`ASI_ADDR_24 == 40'h30)
7277 || (`ASI_ADDR_24 == 40'h80)
7278 || ((`ASI_ADDR_24 == 40'ha0) & (`SPU_MA_BUSY_3 == 0) & (`SPU_MA_TID_3 == 0))
7279 )
7280 sync_asi = 1'b1;
7281 end
7282 8'h4C://CLESR, CLFESR access
7283 begin
7284 if ((`ASI_ADDR_24 == 40'h20) || (`ASI_ADDR_24 == 40'h28))
7285 sync_asi = 1'b1;
7286 end
7287 endcase
7288 end
7289
7290 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
7291 begin
7292 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_24, `ASI_ADDR_24, ld_data_w);
7293 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_24, {24'b0, `ASI_ADDR_24}, ld_data_w[63:0]);
7294 end
7295end //}
7296`endif
7297endmodule
7298
7299
7300
7301module err_c3t1 ();
7302`ifndef GATESIM
7303
7304`include "defines.vh"
7305
7306wire [2:0] mycid;
7307wire [2:0] mytid;
7308wire [5:0] mytnum;
7309
7310integer junk;
7311reg ready;
7312reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
7313reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
7314
7315reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
7316reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
7317
7318reg update_dfesr_w;
7319
7320reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
7321reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
7322
7323reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
7324reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
7325
7326reg sync_asi;
7327reg chk_if_asi_ld;
7328reg [63:0] ld_data_w;
7329
7330reg desr_asi_rd, desr_wr, desr_pend_wr;
7331
7332assign mycid = 3;
7333assign mytid = 1;
7334assign mytnum = 3*8 + 1;
7335
7336initial begin //{
7337 desr_asi_rd = 1'b0;
7338 desr_pend_wr = 1'b0;
7339 ready = 0;
7340 @(posedge `SPC3.l2clk) ;
7341 @(posedge `SPC3.l2clk) ;
7342 ready = `PARGS.err_sync_on;
7343end //}
7344
7345`define DSFSR_NEW_IN_25 `SPC3.tlu.ras.dsfsr_1_new_in
7346`define ISFSR_NEW_IN_25 `SPC3.tlu.ras.isfsr_1_new_in
7347
7348`define DSFSR_25 `SPC3.tlu.ras.dsfsr_1
7349`define ISFSR_25 `SPC3.tlu.ras.isfsr_1
7350`define DSFAR_25 `SPC3.tlu.dfd.dsfar_1
7351
7352`define ASI_WR_DSFSR_25 `SPC3.tlu.ras.asi_wr_dsfsr[1]
7353`define ASI_WR_ISFSR_25 `SPC3.tlu.ras.asi_wr_isfsr[1]
7354
7355`define RAS_WRITE_DESR_1st_25 `SPC3.tlu.dfd.ras_write_desr_1st[1]
7356`define RAS_WRITE_DESR_2nd_25 `SPC3.tlu.dfd.ras_write_desr_2nd[1]
7357`define DESR_asi_rd_25 `SPC3.tlu.ras_rd_desr[1]
7358`define DESR_25 `SPC3.tlu.dfd.desr_1
7359
7360`define RAS_WRITE_FESR_25 `SPC3.tlu.ras.write_fesr[1]
7361`define FESR_25 `SPC3.tlu.dfd.fesr_1
7362
7363`define ST_ERR_25 `SPC3.tlu.trl0.take_ftt & `SPC3.tlu.trl0.trap[1]
7364`define SW_REC_ERR_25 `SPC3.tlu.trl0.take_ade & `SPC3.tlu.trl0.trap[1]
7365`define DATA_ACC_ERR_25 `SPC3.tlu.trl0.take_dae & `SPC3.tlu.trl0.trap[1]
7366`define INST_ACC_ERR_25 `SPC3.tlu.trl0.take_iae & `SPC3.tlu.trl0.trap[1]
7367`define INT_PROC_ERR_25 `SPC3.tlu.trl0.take_ipe & `SPC3.tlu.trl0.trap[1]
7368`define HW_CORR_ERR_25 `SPC3.tlu.trl0.take_eer & `SPC3.tlu.trl0.trap[1]
7369`define INST_ACC_MMU_ERR_25 `SPC3.tlu.trl0.take_ime & `SPC3.tlu.trl0.trap[1]
7370`define DATA_ACC_MMU_ERR_25 `SPC3.tlu.trl0.take_dme & `SPC3.tlu.trl0.trap[1]
7371
7372`define LSU_LD_VALID_B `PROBES3.lsu_ld_valid
7373`define LSU_TID_DEC_B_25 `PROBES3.lsu_tid_dec_b[1]
7374`define ASI_LD_25 `SPC3.lsu.lmd.lmq1_pkt[60] & (`SPC3.lsu.lmd.lmq1_pkt[49:48] == 2'b0)
7375`define ASI_25 `SPC3.lsu.lmd.lmq1_pkt[47:40]
7376`define ASI_ADDR_25 `SPC3.lsu.lmd.lmq1_pkt[39:0]
7377`define ASI_LD_DATA_25 `SPC3.lsu_exu_ld_data_b[63:0]
7378`define ASI_LD_COMP_25 tb_top.nas_top.c3.t1.complete_fw2
7379
7380//SPU specific - only one SPU per core
7381`define SPU_MA_BUSY_3 `SPC3.spu.spu_pmu_ma_busy[3]
7382`define SPU_MA_TID_3 `SPC3.spu.spu_pmu_ma_busy[2:0]
7383
7384////////////////////////////////////////////////////////////////////////////////
7385//Capture the status register data from rtl. For disrupting traps,
7386//rtl can modify the contents of the status register before the
7387//trap is taken and intp message is sent to Riesling.
7388//For precise traps, once the status register is updated rtl can't
7389//change the register again before jumping to the trap handler.
7390//So, for deferred and disrupting traps, inform Riesling when the
7391//register is modified while for precise traps wait until Fw2 before
7392//telling Riesling.
7393
7394//TLU asserts the flush and input signals in W stage. I latch them at the
7395//+ve edge of FX4.
7396
7397always @(negedge (`SPC3.l2clk & ready))
7398begin // {
7399 if (`DESR_asi_rd_25)
7400 desr_asi_rd <= 1'b1;
7401 if (desr_asi_rd)
7402 begin
7403 if (desr_wr)
7404 desr_pend_wr <= 1'b1;
7405 if (`ASI_LD_COMP_25[2])
7406 desr_asi_rd <= 1'b0;
7407 end
7408
7409 update_dsfsr_w <= (`DSFSR_NEW_IN_25 != 4'b0) && ~`ASI_WR_DSFSR_25;
7410 update_isfsr_w <= (`ISFSR_NEW_IN_25 != 3'b0) && ~`ASI_WR_ISFSR_25;
7411 desr_wr <= (`RAS_WRITE_DESR_1st_25 || `RAS_WRITE_DESR_2nd_25);
7412 update_dfesr_w <= `RAS_WRITE_FESR_25;
7413 take_err_trap_fx4 <= `ST_ERR_25 | `SW_REC_ERR_25 | `DATA_ACC_ERR_25
7414 | `INST_ACC_ERR_25 | `INT_PROC_ERR_25
7415 | `HW_CORR_ERR_25 | `INST_ACC_MMU_ERR_25
7416 | `DATA_ACC_MMU_ERR_25 ;
7417
7418
7419 if (`ST_ERR_25) int_num_fx4 <= 8'h07;
7420 if (`SW_REC_ERR_25) int_num_fx4 <= 8'h40;
7421 if (`DATA_ACC_ERR_25) int_num_fx4 <= 8'h32;
7422 if (`INST_ACC_ERR_25) int_num_fx4 <= 8'h0A;
7423 if (`INT_PROC_ERR_25) int_num_fx4 <= 8'h29;
7424 if (`HW_CORR_ERR_25) int_num_fx4 <= 8'h63;
7425 if (`INST_ACC_MMU_ERR_25) int_num_fx4 <= 8'h71;
7426 if (`DATA_ACC_MMU_ERR_25) int_num_fx4 <= 8'h72;
7427
7428 update_dsfsr_fx4 <= update_dsfsr_w;
7429 update_dsfsr_fx5 <= update_dsfsr_fx4;
7430 update_dsfsr_fb <= update_dsfsr_fx5;
7431 update_dsfsr_fw <= update_dsfsr_fb;
7432 update_dsfsr_fw1 <= update_dsfsr_fw;
7433 update_dsfsr_fw2 <= update_dsfsr_fw1;
7434
7435 update_isfsr_fx4 <= update_isfsr_w;
7436 update_isfsr_fx5 <= update_isfsr_fx4;
7437 update_isfsr_fb <= update_isfsr_fx5;
7438 update_isfsr_fw <= update_isfsr_fb;
7439 update_isfsr_fw1 <= update_isfsr_fw;
7440 update_isfsr_fw2 <= update_isfsr_fw1;
7441
7442 take_err_trap_fx5 <= take_err_trap_fx4;
7443 take_err_trap_fb <= take_err_trap_fx5;
7444 take_err_trap_fw <= take_err_trap_fb;
7445 take_err_trap_fw1 <= take_err_trap_fw;
7446 take_err_trap_fw2 <= take_err_trap_fw1;
7447
7448 int_num_fx5 <= int_num_fx4;
7449 int_num_fb <= int_num_fx5;
7450 int_num_fw <= int_num_fb;
7451 int_num_fw1 <= int_num_fw;
7452 int_num_fw2 <= int_num_fw1;
7453
7454 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
7455 begin // {
7456 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
7457 begin //{
7458 desr_pend_wr <= 1'b0;
7459 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_25[63:56], 45'b0, `DESR_25[10:0]});
7460 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_25[63:56], 45'b0, `DESR_25[10:0]});
7461 end //}
7462 //if (update_dfesr_w)
7463 if (`ST_ERR_25)
7464 begin //{
7465 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_25[61:55], 55'b0});
7466 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_25[61:55], 55'b0});
7467 end //}
7468 if (update_dsfsr_fw2)
7469 begin //{
7470 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
7471 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_25[3:0]});
7472 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_25[47:0]});
7473
7474 end //}
7475 if (update_isfsr_fw2)
7476 begin //{
7477 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
7478 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_25[2:0]});
7479 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_25[47:0]});
7480
7481 end //}
7482 if (take_err_trap_fw2)
7483 begin //{
7484 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
7485 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
7486 end // }
7487 end // }
7488
7489end //}
7490
7491//removing the addr check as the LSU doesn't flag an invalid_asi_exception
7492//if the addr of diagnostic accesses is not in the valid range. The inst.
7493//still executes. LSU expects that HP won't use addresses in invalid range.
7494
7495always @(negedge (`SPC3.l2clk & ready))
7496begin // {
7497 sync_asi = 1'b0;
7498 ld_data_w <= `ASI_LD_DATA_25;
7499
7500 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_25)
7501 chk_if_asi_ld <= 1'b1;
7502 else
7503 chk_if_asi_ld <= 1'b0;
7504
7505 if (chk_if_asi_ld & `ASI_LD_25)
7506 begin
7507 case (`ASI_25)
7508 8'h66: //ASI_IC_INSTR
7509 begin
7510 //if ((`ASI_ADDR_25 >= 0) & (`ASI_ADDR_25 <= 40'h7ff8))
7511 sync_asi = 1'b1;
7512 end
7513 8'h67: //ASI_IC_TAG
7514 begin
7515 //if ((`ASI_ADDR_25 >= 0) & (`ASI_ADDR_25 <= 40'h7fe0))
7516 sync_asi = 1'b1;
7517 end
7518 8'h46: //ASI_DC_DATA
7519 begin
7520 sync_asi = 1'b1;
7521 end
7522 8'h47: //ASI_DC_TAG
7523 begin
7524 //if ((`ASI_ADDR_25 >= 0) & (`ASI_ADDR_25 <= 40'h7ff0))
7525 sync_asi = 1'b1;
7526 end
7527 8'h48://IRF ECC
7528 begin
7529 //if ((`ASI_ADDR_25 >= 0) & (`ASI_ADDR_25 <= 40'hF8))
7530 sync_asi = 1'b1;
7531 end
7532 8'h49://FRF ECC
7533 begin
7534 //if ((`ASI_ADDR_25 >= 0) & (`ASI_ADDR_25 <= 40'hF8))
7535 sync_asi = 1'b1;
7536 end
7537 8'h4A://STB access, stb ptr can be read also
7538 begin
7539 //if ((`ASI_ADDR_25 >= 0) & (`ASI_ADDR_25 <= 40'h100))
7540 sync_asi = 1'b1;
7541 end
7542 8'h5A://Tick compare reg
7543 begin
7544 //if ((`ASI_ADDR_25 >= 0) & (`ASI_ADDR_25 <= 40'h38))
7545 sync_asi = 1'b1;
7546 end
7547 8'h5B://TSA
7548 begin
7549 //if ((`ASI_ADDR_25 >= 0) & (`ASI_ADDR_25 <= 40'h38))
7550 sync_asi = 1'b1;
7551 end
7552 8'h51://MRA
7553 begin
7554 //if ((`ASI_ADDR_25 >= 0) & (`ASI_ADDR_25 <= 40'h38))
7555 sync_asi = 1'b1;
7556 end
7557 8'h59://scratchpad ecc data read
7558 begin
7559 //if ((`ASI_ADDR_25 >= 0) & (`ASI_ADDR_25 <= 40'h38))
7560 //syncup the ecc data only. For ecc bit 6 is 0.
7561 if (~`SPC3.lsu.lmd.lmq1_pkt[6])
7562 sync_asi = 1'b1;
7563 end
7564 8'h40://cwqcsr,ma_sync access
7565 begin
7566 if ((`ASI_ADDR_25 == 40'h20) || (`ASI_ADDR_25 == 40'h30)
7567 || (`ASI_ADDR_25 == 40'h80)
7568 || ((`ASI_ADDR_25 == 40'ha0) & (`SPU_MA_BUSY_3 == 0) & (`SPU_MA_TID_3 == 1))
7569 )
7570 sync_asi = 1'b1;
7571 end
7572 8'h4C://CLESR, CLFESR access
7573 begin
7574 if ((`ASI_ADDR_25 == 40'h20) || (`ASI_ADDR_25 == 40'h28))
7575 sync_asi = 1'b1;
7576 end
7577 endcase
7578 end
7579
7580 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
7581 begin
7582 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_25, `ASI_ADDR_25, ld_data_w);
7583 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_25, {24'b0, `ASI_ADDR_25}, ld_data_w[63:0]);
7584 end
7585end //}
7586`endif
7587endmodule
7588
7589
7590
7591module err_c3t2 ();
7592`ifndef GATESIM
7593
7594`include "defines.vh"
7595
7596wire [2:0] mycid;
7597wire [2:0] mytid;
7598wire [5:0] mytnum;
7599
7600integer junk;
7601reg ready;
7602reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
7603reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
7604
7605reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
7606reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
7607
7608reg update_dfesr_w;
7609
7610reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
7611reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
7612
7613reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
7614reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
7615
7616reg sync_asi;
7617reg chk_if_asi_ld;
7618reg [63:0] ld_data_w;
7619
7620reg desr_asi_rd, desr_wr, desr_pend_wr;
7621
7622assign mycid = 3;
7623assign mytid = 2;
7624assign mytnum = 3*8 + 2;
7625
7626initial begin //{
7627 desr_asi_rd = 1'b0;
7628 desr_pend_wr = 1'b0;
7629 ready = 0;
7630 @(posedge `SPC3.l2clk) ;
7631 @(posedge `SPC3.l2clk) ;
7632 ready = `PARGS.err_sync_on;
7633end //}
7634
7635`define DSFSR_NEW_IN_26 `SPC3.tlu.ras.dsfsr_2_new_in
7636`define ISFSR_NEW_IN_26 `SPC3.tlu.ras.isfsr_2_new_in
7637
7638`define DSFSR_26 `SPC3.tlu.ras.dsfsr_2
7639`define ISFSR_26 `SPC3.tlu.ras.isfsr_2
7640`define DSFAR_26 `SPC3.tlu.dfd.dsfar_2
7641
7642`define ASI_WR_DSFSR_26 `SPC3.tlu.ras.asi_wr_dsfsr[2]
7643`define ASI_WR_ISFSR_26 `SPC3.tlu.ras.asi_wr_isfsr[2]
7644
7645`define RAS_WRITE_DESR_1st_26 `SPC3.tlu.dfd.ras_write_desr_1st[2]
7646`define RAS_WRITE_DESR_2nd_26 `SPC3.tlu.dfd.ras_write_desr_2nd[2]
7647`define DESR_asi_rd_26 `SPC3.tlu.ras_rd_desr[2]
7648`define DESR_26 `SPC3.tlu.dfd.desr_2
7649
7650`define RAS_WRITE_FESR_26 `SPC3.tlu.ras.write_fesr[2]
7651`define FESR_26 `SPC3.tlu.dfd.fesr_2
7652
7653`define ST_ERR_26 `SPC3.tlu.trl0.take_ftt & `SPC3.tlu.trl0.trap[2]
7654`define SW_REC_ERR_26 `SPC3.tlu.trl0.take_ade & `SPC3.tlu.trl0.trap[2]
7655`define DATA_ACC_ERR_26 `SPC3.tlu.trl0.take_dae & `SPC3.tlu.trl0.trap[2]
7656`define INST_ACC_ERR_26 `SPC3.tlu.trl0.take_iae & `SPC3.tlu.trl0.trap[2]
7657`define INT_PROC_ERR_26 `SPC3.tlu.trl0.take_ipe & `SPC3.tlu.trl0.trap[2]
7658`define HW_CORR_ERR_26 `SPC3.tlu.trl0.take_eer & `SPC3.tlu.trl0.trap[2]
7659`define INST_ACC_MMU_ERR_26 `SPC3.tlu.trl0.take_ime & `SPC3.tlu.trl0.trap[2]
7660`define DATA_ACC_MMU_ERR_26 `SPC3.tlu.trl0.take_dme & `SPC3.tlu.trl0.trap[2]
7661
7662`define LSU_LD_VALID_B `PROBES3.lsu_ld_valid
7663`define LSU_TID_DEC_B_26 `PROBES3.lsu_tid_dec_b[2]
7664`define ASI_LD_26 `SPC3.lsu.lmd.lmq2_pkt[60] & (`SPC3.lsu.lmd.lmq2_pkt[49:48] == 2'b0)
7665`define ASI_26 `SPC3.lsu.lmd.lmq2_pkt[47:40]
7666`define ASI_ADDR_26 `SPC3.lsu.lmd.lmq2_pkt[39:0]
7667`define ASI_LD_DATA_26 `SPC3.lsu_exu_ld_data_b[63:0]
7668`define ASI_LD_COMP_26 tb_top.nas_top.c3.t2.complete_fw2
7669
7670//SPU specific - only one SPU per core
7671`define SPU_MA_BUSY_3 `SPC3.spu.spu_pmu_ma_busy[3]
7672`define SPU_MA_TID_3 `SPC3.spu.spu_pmu_ma_busy[2:0]
7673
7674////////////////////////////////////////////////////////////////////////////////
7675//Capture the status register data from rtl. For disrupting traps,
7676//rtl can modify the contents of the status register before the
7677//trap is taken and intp message is sent to Riesling.
7678//For precise traps, once the status register is updated rtl can't
7679//change the register again before jumping to the trap handler.
7680//So, for deferred and disrupting traps, inform Riesling when the
7681//register is modified while for precise traps wait until Fw2 before
7682//telling Riesling.
7683
7684//TLU asserts the flush and input signals in W stage. I latch them at the
7685//+ve edge of FX4.
7686
7687always @(negedge (`SPC3.l2clk & ready))
7688begin // {
7689 if (`DESR_asi_rd_26)
7690 desr_asi_rd <= 1'b1;
7691 if (desr_asi_rd)
7692 begin
7693 if (desr_wr)
7694 desr_pend_wr <= 1'b1;
7695 if (`ASI_LD_COMP_26[2])
7696 desr_asi_rd <= 1'b0;
7697 end
7698
7699 update_dsfsr_w <= (`DSFSR_NEW_IN_26 != 4'b0) && ~`ASI_WR_DSFSR_26;
7700 update_isfsr_w <= (`ISFSR_NEW_IN_26 != 3'b0) && ~`ASI_WR_ISFSR_26;
7701 desr_wr <= (`RAS_WRITE_DESR_1st_26 || `RAS_WRITE_DESR_2nd_26);
7702 update_dfesr_w <= `RAS_WRITE_FESR_26;
7703 take_err_trap_fx4 <= `ST_ERR_26 | `SW_REC_ERR_26 | `DATA_ACC_ERR_26
7704 | `INST_ACC_ERR_26 | `INT_PROC_ERR_26
7705 | `HW_CORR_ERR_26 | `INST_ACC_MMU_ERR_26
7706 | `DATA_ACC_MMU_ERR_26 ;
7707
7708
7709 if (`ST_ERR_26) int_num_fx4 <= 8'h07;
7710 if (`SW_REC_ERR_26) int_num_fx4 <= 8'h40;
7711 if (`DATA_ACC_ERR_26) int_num_fx4 <= 8'h32;
7712 if (`INST_ACC_ERR_26) int_num_fx4 <= 8'h0A;
7713 if (`INT_PROC_ERR_26) int_num_fx4 <= 8'h29;
7714 if (`HW_CORR_ERR_26) int_num_fx4 <= 8'h63;
7715 if (`INST_ACC_MMU_ERR_26) int_num_fx4 <= 8'h71;
7716 if (`DATA_ACC_MMU_ERR_26) int_num_fx4 <= 8'h72;
7717
7718 update_dsfsr_fx4 <= update_dsfsr_w;
7719 update_dsfsr_fx5 <= update_dsfsr_fx4;
7720 update_dsfsr_fb <= update_dsfsr_fx5;
7721 update_dsfsr_fw <= update_dsfsr_fb;
7722 update_dsfsr_fw1 <= update_dsfsr_fw;
7723 update_dsfsr_fw2 <= update_dsfsr_fw1;
7724
7725 update_isfsr_fx4 <= update_isfsr_w;
7726 update_isfsr_fx5 <= update_isfsr_fx4;
7727 update_isfsr_fb <= update_isfsr_fx5;
7728 update_isfsr_fw <= update_isfsr_fb;
7729 update_isfsr_fw1 <= update_isfsr_fw;
7730 update_isfsr_fw2 <= update_isfsr_fw1;
7731
7732 take_err_trap_fx5 <= take_err_trap_fx4;
7733 take_err_trap_fb <= take_err_trap_fx5;
7734 take_err_trap_fw <= take_err_trap_fb;
7735 take_err_trap_fw1 <= take_err_trap_fw;
7736 take_err_trap_fw2 <= take_err_trap_fw1;
7737
7738 int_num_fx5 <= int_num_fx4;
7739 int_num_fb <= int_num_fx5;
7740 int_num_fw <= int_num_fb;
7741 int_num_fw1 <= int_num_fw;
7742 int_num_fw2 <= int_num_fw1;
7743
7744 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
7745 begin // {
7746 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
7747 begin //{
7748 desr_pend_wr <= 1'b0;
7749 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_26[63:56], 45'b0, `DESR_26[10:0]});
7750 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_26[63:56], 45'b0, `DESR_26[10:0]});
7751 end //}
7752 //if (update_dfesr_w)
7753 if (`ST_ERR_26)
7754 begin //{
7755 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_26[61:55], 55'b0});
7756 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_26[61:55], 55'b0});
7757 end //}
7758 if (update_dsfsr_fw2)
7759 begin //{
7760 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
7761 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_26[3:0]});
7762 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_26[47:0]});
7763
7764 end //}
7765 if (update_isfsr_fw2)
7766 begin //{
7767 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
7768 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_26[2:0]});
7769 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_26[47:0]});
7770
7771 end //}
7772 if (take_err_trap_fw2)
7773 begin //{
7774 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
7775 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
7776 end // }
7777 end // }
7778
7779end //}
7780
7781//removing the addr check as the LSU doesn't flag an invalid_asi_exception
7782//if the addr of diagnostic accesses is not in the valid range. The inst.
7783//still executes. LSU expects that HP won't use addresses in invalid range.
7784
7785always @(negedge (`SPC3.l2clk & ready))
7786begin // {
7787 sync_asi = 1'b0;
7788 ld_data_w <= `ASI_LD_DATA_26;
7789
7790 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_26)
7791 chk_if_asi_ld <= 1'b1;
7792 else
7793 chk_if_asi_ld <= 1'b0;
7794
7795 if (chk_if_asi_ld & `ASI_LD_26)
7796 begin
7797 case (`ASI_26)
7798 8'h66: //ASI_IC_INSTR
7799 begin
7800 //if ((`ASI_ADDR_26 >= 0) & (`ASI_ADDR_26 <= 40'h7ff8))
7801 sync_asi = 1'b1;
7802 end
7803 8'h67: //ASI_IC_TAG
7804 begin
7805 //if ((`ASI_ADDR_26 >= 0) & (`ASI_ADDR_26 <= 40'h7fe0))
7806 sync_asi = 1'b1;
7807 end
7808 8'h46: //ASI_DC_DATA
7809 begin
7810 sync_asi = 1'b1;
7811 end
7812 8'h47: //ASI_DC_TAG
7813 begin
7814 //if ((`ASI_ADDR_26 >= 0) & (`ASI_ADDR_26 <= 40'h7ff0))
7815 sync_asi = 1'b1;
7816 end
7817 8'h48://IRF ECC
7818 begin
7819 //if ((`ASI_ADDR_26 >= 0) & (`ASI_ADDR_26 <= 40'hF8))
7820 sync_asi = 1'b1;
7821 end
7822 8'h49://FRF ECC
7823 begin
7824 //if ((`ASI_ADDR_26 >= 0) & (`ASI_ADDR_26 <= 40'hF8))
7825 sync_asi = 1'b1;
7826 end
7827 8'h4A://STB access, stb ptr can be read also
7828 begin
7829 //if ((`ASI_ADDR_26 >= 0) & (`ASI_ADDR_26 <= 40'h100))
7830 sync_asi = 1'b1;
7831 end
7832 8'h5A://Tick compare reg
7833 begin
7834 //if ((`ASI_ADDR_26 >= 0) & (`ASI_ADDR_26 <= 40'h38))
7835 sync_asi = 1'b1;
7836 end
7837 8'h5B://TSA
7838 begin
7839 //if ((`ASI_ADDR_26 >= 0) & (`ASI_ADDR_26 <= 40'h38))
7840 sync_asi = 1'b1;
7841 end
7842 8'h51://MRA
7843 begin
7844 //if ((`ASI_ADDR_26 >= 0) & (`ASI_ADDR_26 <= 40'h38))
7845 sync_asi = 1'b1;
7846 end
7847 8'h59://scratchpad ecc data read
7848 begin
7849 //if ((`ASI_ADDR_26 >= 0) & (`ASI_ADDR_26 <= 40'h38))
7850 //syncup the ecc data only. For ecc bit 6 is 0.
7851 if (~`SPC3.lsu.lmd.lmq2_pkt[6])
7852 sync_asi = 1'b1;
7853 end
7854 8'h40://cwqcsr,ma_sync access
7855 begin
7856 if ((`ASI_ADDR_26 == 40'h20) || (`ASI_ADDR_26 == 40'h30)
7857 || (`ASI_ADDR_26 == 40'h80)
7858 || ((`ASI_ADDR_26 == 40'ha0) & (`SPU_MA_BUSY_3 == 0) & (`SPU_MA_TID_3 == 2))
7859 )
7860 sync_asi = 1'b1;
7861 end
7862 8'h4C://CLESR, CLFESR access
7863 begin
7864 if ((`ASI_ADDR_26 == 40'h20) || (`ASI_ADDR_26 == 40'h28))
7865 sync_asi = 1'b1;
7866 end
7867 endcase
7868 end
7869
7870 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
7871 begin
7872 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_26, `ASI_ADDR_26, ld_data_w);
7873 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_26, {24'b0, `ASI_ADDR_26}, ld_data_w[63:0]);
7874 end
7875end //}
7876`endif
7877endmodule
7878
7879
7880
7881module err_c3t3 ();
7882`ifndef GATESIM
7883
7884`include "defines.vh"
7885
7886wire [2:0] mycid;
7887wire [2:0] mytid;
7888wire [5:0] mytnum;
7889
7890integer junk;
7891reg ready;
7892reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
7893reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
7894
7895reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
7896reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
7897
7898reg update_dfesr_w;
7899
7900reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
7901reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
7902
7903reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
7904reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
7905
7906reg sync_asi;
7907reg chk_if_asi_ld;
7908reg [63:0] ld_data_w;
7909
7910reg desr_asi_rd, desr_wr, desr_pend_wr;
7911
7912assign mycid = 3;
7913assign mytid = 3;
7914assign mytnum = 3*8 + 3;
7915
7916initial begin //{
7917 desr_asi_rd = 1'b0;
7918 desr_pend_wr = 1'b0;
7919 ready = 0;
7920 @(posedge `SPC3.l2clk) ;
7921 @(posedge `SPC3.l2clk) ;
7922 ready = `PARGS.err_sync_on;
7923end //}
7924
7925`define DSFSR_NEW_IN_27 `SPC3.tlu.ras.dsfsr_3_new_in
7926`define ISFSR_NEW_IN_27 `SPC3.tlu.ras.isfsr_3_new_in
7927
7928`define DSFSR_27 `SPC3.tlu.ras.dsfsr_3
7929`define ISFSR_27 `SPC3.tlu.ras.isfsr_3
7930`define DSFAR_27 `SPC3.tlu.dfd.dsfar_3
7931
7932`define ASI_WR_DSFSR_27 `SPC3.tlu.ras.asi_wr_dsfsr[3]
7933`define ASI_WR_ISFSR_27 `SPC3.tlu.ras.asi_wr_isfsr[3]
7934
7935`define RAS_WRITE_DESR_1st_27 `SPC3.tlu.dfd.ras_write_desr_1st[3]
7936`define RAS_WRITE_DESR_2nd_27 `SPC3.tlu.dfd.ras_write_desr_2nd[3]
7937`define DESR_asi_rd_27 `SPC3.tlu.ras_rd_desr[3]
7938`define DESR_27 `SPC3.tlu.dfd.desr_3
7939
7940`define RAS_WRITE_FESR_27 `SPC3.tlu.ras.write_fesr[3]
7941`define FESR_27 `SPC3.tlu.dfd.fesr_3
7942
7943`define ST_ERR_27 `SPC3.tlu.trl0.take_ftt & `SPC3.tlu.trl0.trap[3]
7944`define SW_REC_ERR_27 `SPC3.tlu.trl0.take_ade & `SPC3.tlu.trl0.trap[3]
7945`define DATA_ACC_ERR_27 `SPC3.tlu.trl0.take_dae & `SPC3.tlu.trl0.trap[3]
7946`define INST_ACC_ERR_27 `SPC3.tlu.trl0.take_iae & `SPC3.tlu.trl0.trap[3]
7947`define INT_PROC_ERR_27 `SPC3.tlu.trl0.take_ipe & `SPC3.tlu.trl0.trap[3]
7948`define HW_CORR_ERR_27 `SPC3.tlu.trl0.take_eer & `SPC3.tlu.trl0.trap[3]
7949`define INST_ACC_MMU_ERR_27 `SPC3.tlu.trl0.take_ime & `SPC3.tlu.trl0.trap[3]
7950`define DATA_ACC_MMU_ERR_27 `SPC3.tlu.trl0.take_dme & `SPC3.tlu.trl0.trap[3]
7951
7952`define LSU_LD_VALID_B `PROBES3.lsu_ld_valid
7953`define LSU_TID_DEC_B_27 `PROBES3.lsu_tid_dec_b[3]
7954`define ASI_LD_27 `SPC3.lsu.lmd.lmq3_pkt[60] & (`SPC3.lsu.lmd.lmq3_pkt[49:48] == 2'b0)
7955`define ASI_27 `SPC3.lsu.lmd.lmq3_pkt[47:40]
7956`define ASI_ADDR_27 `SPC3.lsu.lmd.lmq3_pkt[39:0]
7957`define ASI_LD_DATA_27 `SPC3.lsu_exu_ld_data_b[63:0]
7958`define ASI_LD_COMP_27 tb_top.nas_top.c3.t3.complete_fw2
7959
7960//SPU specific - only one SPU per core
7961`define SPU_MA_BUSY_3 `SPC3.spu.spu_pmu_ma_busy[3]
7962`define SPU_MA_TID_3 `SPC3.spu.spu_pmu_ma_busy[2:0]
7963
7964////////////////////////////////////////////////////////////////////////////////
7965//Capture the status register data from rtl. For disrupting traps,
7966//rtl can modify the contents of the status register before the
7967//trap is taken and intp message is sent to Riesling.
7968//For precise traps, once the status register is updated rtl can't
7969//change the register again before jumping to the trap handler.
7970//So, for deferred and disrupting traps, inform Riesling when the
7971//register is modified while for precise traps wait until Fw2 before
7972//telling Riesling.
7973
7974//TLU asserts the flush and input signals in W stage. I latch them at the
7975//+ve edge of FX4.
7976
7977always @(negedge (`SPC3.l2clk & ready))
7978begin // {
7979 if (`DESR_asi_rd_27)
7980 desr_asi_rd <= 1'b1;
7981 if (desr_asi_rd)
7982 begin
7983 if (desr_wr)
7984 desr_pend_wr <= 1'b1;
7985 if (`ASI_LD_COMP_27[2])
7986 desr_asi_rd <= 1'b0;
7987 end
7988
7989 update_dsfsr_w <= (`DSFSR_NEW_IN_27 != 4'b0) && ~`ASI_WR_DSFSR_27;
7990 update_isfsr_w <= (`ISFSR_NEW_IN_27 != 3'b0) && ~`ASI_WR_ISFSR_27;
7991 desr_wr <= (`RAS_WRITE_DESR_1st_27 || `RAS_WRITE_DESR_2nd_27);
7992 update_dfesr_w <= `RAS_WRITE_FESR_27;
7993 take_err_trap_fx4 <= `ST_ERR_27 | `SW_REC_ERR_27 | `DATA_ACC_ERR_27
7994 | `INST_ACC_ERR_27 | `INT_PROC_ERR_27
7995 | `HW_CORR_ERR_27 | `INST_ACC_MMU_ERR_27
7996 | `DATA_ACC_MMU_ERR_27 ;
7997
7998
7999 if (`ST_ERR_27) int_num_fx4 <= 8'h07;
8000 if (`SW_REC_ERR_27) int_num_fx4 <= 8'h40;
8001 if (`DATA_ACC_ERR_27) int_num_fx4 <= 8'h32;
8002 if (`INST_ACC_ERR_27) int_num_fx4 <= 8'h0A;
8003 if (`INT_PROC_ERR_27) int_num_fx4 <= 8'h29;
8004 if (`HW_CORR_ERR_27) int_num_fx4 <= 8'h63;
8005 if (`INST_ACC_MMU_ERR_27) int_num_fx4 <= 8'h71;
8006 if (`DATA_ACC_MMU_ERR_27) int_num_fx4 <= 8'h72;
8007
8008 update_dsfsr_fx4 <= update_dsfsr_w;
8009 update_dsfsr_fx5 <= update_dsfsr_fx4;
8010 update_dsfsr_fb <= update_dsfsr_fx5;
8011 update_dsfsr_fw <= update_dsfsr_fb;
8012 update_dsfsr_fw1 <= update_dsfsr_fw;
8013 update_dsfsr_fw2 <= update_dsfsr_fw1;
8014
8015 update_isfsr_fx4 <= update_isfsr_w;
8016 update_isfsr_fx5 <= update_isfsr_fx4;
8017 update_isfsr_fb <= update_isfsr_fx5;
8018 update_isfsr_fw <= update_isfsr_fb;
8019 update_isfsr_fw1 <= update_isfsr_fw;
8020 update_isfsr_fw2 <= update_isfsr_fw1;
8021
8022 take_err_trap_fx5 <= take_err_trap_fx4;
8023 take_err_trap_fb <= take_err_trap_fx5;
8024 take_err_trap_fw <= take_err_trap_fb;
8025 take_err_trap_fw1 <= take_err_trap_fw;
8026 take_err_trap_fw2 <= take_err_trap_fw1;
8027
8028 int_num_fx5 <= int_num_fx4;
8029 int_num_fb <= int_num_fx5;
8030 int_num_fw <= int_num_fb;
8031 int_num_fw1 <= int_num_fw;
8032 int_num_fw2 <= int_num_fw1;
8033
8034 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
8035 begin // {
8036 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
8037 begin //{
8038 desr_pend_wr <= 1'b0;
8039 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_27[63:56], 45'b0, `DESR_27[10:0]});
8040 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_27[63:56], 45'b0, `DESR_27[10:0]});
8041 end //}
8042 //if (update_dfesr_w)
8043 if (`ST_ERR_27)
8044 begin //{
8045 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_27[61:55], 55'b0});
8046 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_27[61:55], 55'b0});
8047 end //}
8048 if (update_dsfsr_fw2)
8049 begin //{
8050 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
8051 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_27[3:0]});
8052 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_27[47:0]});
8053
8054 end //}
8055 if (update_isfsr_fw2)
8056 begin //{
8057 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
8058 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_27[2:0]});
8059 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_27[47:0]});
8060
8061 end //}
8062 if (take_err_trap_fw2)
8063 begin //{
8064 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
8065 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
8066 end // }
8067 end // }
8068
8069end //}
8070
8071//removing the addr check as the LSU doesn't flag an invalid_asi_exception
8072//if the addr of diagnostic accesses is not in the valid range. The inst.
8073//still executes. LSU expects that HP won't use addresses in invalid range.
8074
8075always @(negedge (`SPC3.l2clk & ready))
8076begin // {
8077 sync_asi = 1'b0;
8078 ld_data_w <= `ASI_LD_DATA_27;
8079
8080 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_27)
8081 chk_if_asi_ld <= 1'b1;
8082 else
8083 chk_if_asi_ld <= 1'b0;
8084
8085 if (chk_if_asi_ld & `ASI_LD_27)
8086 begin
8087 case (`ASI_27)
8088 8'h66: //ASI_IC_INSTR
8089 begin
8090 //if ((`ASI_ADDR_27 >= 0) & (`ASI_ADDR_27 <= 40'h7ff8))
8091 sync_asi = 1'b1;
8092 end
8093 8'h67: //ASI_IC_TAG
8094 begin
8095 //if ((`ASI_ADDR_27 >= 0) & (`ASI_ADDR_27 <= 40'h7fe0))
8096 sync_asi = 1'b1;
8097 end
8098 8'h46: //ASI_DC_DATA
8099 begin
8100 sync_asi = 1'b1;
8101 end
8102 8'h47: //ASI_DC_TAG
8103 begin
8104 //if ((`ASI_ADDR_27 >= 0) & (`ASI_ADDR_27 <= 40'h7ff0))
8105 sync_asi = 1'b1;
8106 end
8107 8'h48://IRF ECC
8108 begin
8109 //if ((`ASI_ADDR_27 >= 0) & (`ASI_ADDR_27 <= 40'hF8))
8110 sync_asi = 1'b1;
8111 end
8112 8'h49://FRF ECC
8113 begin
8114 //if ((`ASI_ADDR_27 >= 0) & (`ASI_ADDR_27 <= 40'hF8))
8115 sync_asi = 1'b1;
8116 end
8117 8'h4A://STB access, stb ptr can be read also
8118 begin
8119 //if ((`ASI_ADDR_27 >= 0) & (`ASI_ADDR_27 <= 40'h100))
8120 sync_asi = 1'b1;
8121 end
8122 8'h5A://Tick compare reg
8123 begin
8124 //if ((`ASI_ADDR_27 >= 0) & (`ASI_ADDR_27 <= 40'h38))
8125 sync_asi = 1'b1;
8126 end
8127 8'h5B://TSA
8128 begin
8129 //if ((`ASI_ADDR_27 >= 0) & (`ASI_ADDR_27 <= 40'h38))
8130 sync_asi = 1'b1;
8131 end
8132 8'h51://MRA
8133 begin
8134 //if ((`ASI_ADDR_27 >= 0) & (`ASI_ADDR_27 <= 40'h38))
8135 sync_asi = 1'b1;
8136 end
8137 8'h59://scratchpad ecc data read
8138 begin
8139 //if ((`ASI_ADDR_27 >= 0) & (`ASI_ADDR_27 <= 40'h38))
8140 //syncup the ecc data only. For ecc bit 6 is 0.
8141 if (~`SPC3.lsu.lmd.lmq3_pkt[6])
8142 sync_asi = 1'b1;
8143 end
8144 8'h40://cwqcsr,ma_sync access
8145 begin
8146 if ((`ASI_ADDR_27 == 40'h20) || (`ASI_ADDR_27 == 40'h30)
8147 || (`ASI_ADDR_27 == 40'h80)
8148 || ((`ASI_ADDR_27 == 40'ha0) & (`SPU_MA_BUSY_3 == 0) & (`SPU_MA_TID_3 == 3))
8149 )
8150 sync_asi = 1'b1;
8151 end
8152 8'h4C://CLESR, CLFESR access
8153 begin
8154 if ((`ASI_ADDR_27 == 40'h20) || (`ASI_ADDR_27 == 40'h28))
8155 sync_asi = 1'b1;
8156 end
8157 endcase
8158 end
8159
8160 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
8161 begin
8162 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_27, `ASI_ADDR_27, ld_data_w);
8163 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_27, {24'b0, `ASI_ADDR_27}, ld_data_w[63:0]);
8164 end
8165end //}
8166`endif
8167endmodule
8168
8169
8170
8171module err_c3t4 ();
8172`ifndef GATESIM
8173
8174`include "defines.vh"
8175
8176wire [2:0] mycid;
8177wire [2:0] mytid;
8178wire [5:0] mytnum;
8179
8180integer junk;
8181reg ready;
8182reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
8183reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
8184
8185reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
8186reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
8187
8188reg update_dfesr_w;
8189
8190reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
8191reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
8192
8193reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
8194reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
8195
8196reg sync_asi;
8197reg chk_if_asi_ld;
8198reg [63:0] ld_data_w;
8199
8200reg desr_asi_rd, desr_wr, desr_pend_wr;
8201
8202assign mycid = 3;
8203assign mytid = 4;
8204assign mytnum = 3*8 + 4;
8205
8206initial begin //{
8207 desr_asi_rd = 1'b0;
8208 desr_pend_wr = 1'b0;
8209 ready = 0;
8210 @(posedge `SPC3.l2clk) ;
8211 @(posedge `SPC3.l2clk) ;
8212 ready = `PARGS.err_sync_on;
8213end //}
8214
8215`define DSFSR_NEW_IN_28 `SPC3.tlu.ras.dsfsr_4_new_in
8216`define ISFSR_NEW_IN_28 `SPC3.tlu.ras.isfsr_4_new_in
8217
8218`define DSFSR_28 `SPC3.tlu.ras.dsfsr_4
8219`define ISFSR_28 `SPC3.tlu.ras.isfsr_4
8220`define DSFAR_28 `SPC3.tlu.dfd.dsfar_4
8221
8222`define ASI_WR_DSFSR_28 `SPC3.tlu.ras.asi_wr_dsfsr[4]
8223`define ASI_WR_ISFSR_28 `SPC3.tlu.ras.asi_wr_isfsr[4]
8224
8225`define RAS_WRITE_DESR_1st_28 `SPC3.tlu.dfd.ras_write_desr_1st[4]
8226`define RAS_WRITE_DESR_2nd_28 `SPC3.tlu.dfd.ras_write_desr_2nd[4]
8227`define DESR_asi_rd_28 `SPC3.tlu.ras_rd_desr[4]
8228`define DESR_28 `SPC3.tlu.dfd.desr_4
8229
8230`define RAS_WRITE_FESR_28 `SPC3.tlu.ras.write_fesr[4]
8231`define FESR_28 `SPC3.tlu.dfd.fesr_4
8232
8233`define ST_ERR_28 `SPC3.tlu.trl1.take_ftt & `SPC3.tlu.trl1.trap[0]
8234`define SW_REC_ERR_28 `SPC3.tlu.trl1.take_ade & `SPC3.tlu.trl1.trap[0]
8235`define DATA_ACC_ERR_28 `SPC3.tlu.trl1.take_dae & `SPC3.tlu.trl1.trap[0]
8236`define INST_ACC_ERR_28 `SPC3.tlu.trl1.take_iae & `SPC3.tlu.trl1.trap[0]
8237`define INT_PROC_ERR_28 `SPC3.tlu.trl1.take_ipe & `SPC3.tlu.trl1.trap[0]
8238`define HW_CORR_ERR_28 `SPC3.tlu.trl1.take_eer & `SPC3.tlu.trl1.trap[0]
8239`define INST_ACC_MMU_ERR_28 `SPC3.tlu.trl1.take_ime & `SPC3.tlu.trl1.trap[0]
8240`define DATA_ACC_MMU_ERR_28 `SPC3.tlu.trl1.take_dme & `SPC3.tlu.trl1.trap[0]
8241
8242`define LSU_LD_VALID_B `PROBES3.lsu_ld_valid
8243`define LSU_TID_DEC_B_28 `PROBES3.lsu_tid_dec_b[4]
8244`define ASI_LD_28 `SPC3.lsu.lmd.lmq4_pkt[60] & (`SPC3.lsu.lmd.lmq4_pkt[49:48] == 2'b0)
8245`define ASI_28 `SPC3.lsu.lmd.lmq4_pkt[47:40]
8246`define ASI_ADDR_28 `SPC3.lsu.lmd.lmq4_pkt[39:0]
8247`define ASI_LD_DATA_28 `SPC3.lsu_exu_ld_data_b[63:0]
8248`define ASI_LD_COMP_28 tb_top.nas_top.c3.t4.complete_fw2
8249
8250//SPU specific - only one SPU per core
8251`define SPU_MA_BUSY_3 `SPC3.spu.spu_pmu_ma_busy[3]
8252`define SPU_MA_TID_3 `SPC3.spu.spu_pmu_ma_busy[2:0]
8253
8254////////////////////////////////////////////////////////////////////////////////
8255//Capture the status register data from rtl. For disrupting traps,
8256//rtl can modify the contents of the status register before the
8257//trap is taken and intp message is sent to Riesling.
8258//For precise traps, once the status register is updated rtl can't
8259//change the register again before jumping to the trap handler.
8260//So, for deferred and disrupting traps, inform Riesling when the
8261//register is modified while for precise traps wait until Fw2 before
8262//telling Riesling.
8263
8264//TLU asserts the flush and input signals in W stage. I latch them at the
8265//+ve edge of FX4.
8266
8267always @(negedge (`SPC3.l2clk & ready))
8268begin // {
8269 if (`DESR_asi_rd_28)
8270 desr_asi_rd <= 1'b1;
8271 if (desr_asi_rd)
8272 begin
8273 if (desr_wr)
8274 desr_pend_wr <= 1'b1;
8275 if (`ASI_LD_COMP_28[2])
8276 desr_asi_rd <= 1'b0;
8277 end
8278
8279 update_dsfsr_w <= (`DSFSR_NEW_IN_28 != 4'b0) && ~`ASI_WR_DSFSR_28;
8280 update_isfsr_w <= (`ISFSR_NEW_IN_28 != 3'b0) && ~`ASI_WR_ISFSR_28;
8281 desr_wr <= (`RAS_WRITE_DESR_1st_28 || `RAS_WRITE_DESR_2nd_28);
8282 update_dfesr_w <= `RAS_WRITE_FESR_28;
8283 take_err_trap_fx4 <= `ST_ERR_28 | `SW_REC_ERR_28 | `DATA_ACC_ERR_28
8284 | `INST_ACC_ERR_28 | `INT_PROC_ERR_28
8285 | `HW_CORR_ERR_28 | `INST_ACC_MMU_ERR_28
8286 | `DATA_ACC_MMU_ERR_28 ;
8287
8288
8289 if (`ST_ERR_28) int_num_fx4 <= 8'h07;
8290 if (`SW_REC_ERR_28) int_num_fx4 <= 8'h40;
8291 if (`DATA_ACC_ERR_28) int_num_fx4 <= 8'h32;
8292 if (`INST_ACC_ERR_28) int_num_fx4 <= 8'h0A;
8293 if (`INT_PROC_ERR_28) int_num_fx4 <= 8'h29;
8294 if (`HW_CORR_ERR_28) int_num_fx4 <= 8'h63;
8295 if (`INST_ACC_MMU_ERR_28) int_num_fx4 <= 8'h71;
8296 if (`DATA_ACC_MMU_ERR_28) int_num_fx4 <= 8'h72;
8297
8298 update_dsfsr_fx4 <= update_dsfsr_w;
8299 update_dsfsr_fx5 <= update_dsfsr_fx4;
8300 update_dsfsr_fb <= update_dsfsr_fx5;
8301 update_dsfsr_fw <= update_dsfsr_fb;
8302 update_dsfsr_fw1 <= update_dsfsr_fw;
8303 update_dsfsr_fw2 <= update_dsfsr_fw1;
8304
8305 update_isfsr_fx4 <= update_isfsr_w;
8306 update_isfsr_fx5 <= update_isfsr_fx4;
8307 update_isfsr_fb <= update_isfsr_fx5;
8308 update_isfsr_fw <= update_isfsr_fb;
8309 update_isfsr_fw1 <= update_isfsr_fw;
8310 update_isfsr_fw2 <= update_isfsr_fw1;
8311
8312 take_err_trap_fx5 <= take_err_trap_fx4;
8313 take_err_trap_fb <= take_err_trap_fx5;
8314 take_err_trap_fw <= take_err_trap_fb;
8315 take_err_trap_fw1 <= take_err_trap_fw;
8316 take_err_trap_fw2 <= take_err_trap_fw1;
8317
8318 int_num_fx5 <= int_num_fx4;
8319 int_num_fb <= int_num_fx5;
8320 int_num_fw <= int_num_fb;
8321 int_num_fw1 <= int_num_fw;
8322 int_num_fw2 <= int_num_fw1;
8323
8324 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
8325 begin // {
8326 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
8327 begin //{
8328 desr_pend_wr <= 1'b0;
8329 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_28[63:56], 45'b0, `DESR_28[10:0]});
8330 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_28[63:56], 45'b0, `DESR_28[10:0]});
8331 end //}
8332 //if (update_dfesr_w)
8333 if (`ST_ERR_28)
8334 begin //{
8335 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_28[61:55], 55'b0});
8336 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_28[61:55], 55'b0});
8337 end //}
8338 if (update_dsfsr_fw2)
8339 begin //{
8340 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
8341 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_28[3:0]});
8342 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_28[47:0]});
8343
8344 end //}
8345 if (update_isfsr_fw2)
8346 begin //{
8347 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
8348 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_28[2:0]});
8349 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_28[47:0]});
8350
8351 end //}
8352 if (take_err_trap_fw2)
8353 begin //{
8354 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
8355 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
8356 end // }
8357 end // }
8358
8359end //}
8360
8361//removing the addr check as the LSU doesn't flag an invalid_asi_exception
8362//if the addr of diagnostic accesses is not in the valid range. The inst.
8363//still executes. LSU expects that HP won't use addresses in invalid range.
8364
8365always @(negedge (`SPC3.l2clk & ready))
8366begin // {
8367 sync_asi = 1'b0;
8368 ld_data_w <= `ASI_LD_DATA_28;
8369
8370 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_28)
8371 chk_if_asi_ld <= 1'b1;
8372 else
8373 chk_if_asi_ld <= 1'b0;
8374
8375 if (chk_if_asi_ld & `ASI_LD_28)
8376 begin
8377 case (`ASI_28)
8378 8'h66: //ASI_IC_INSTR
8379 begin
8380 //if ((`ASI_ADDR_28 >= 0) & (`ASI_ADDR_28 <= 40'h7ff8))
8381 sync_asi = 1'b1;
8382 end
8383 8'h67: //ASI_IC_TAG
8384 begin
8385 //if ((`ASI_ADDR_28 >= 0) & (`ASI_ADDR_28 <= 40'h7fe0))
8386 sync_asi = 1'b1;
8387 end
8388 8'h46: //ASI_DC_DATA
8389 begin
8390 sync_asi = 1'b1;
8391 end
8392 8'h47: //ASI_DC_TAG
8393 begin
8394 //if ((`ASI_ADDR_28 >= 0) & (`ASI_ADDR_28 <= 40'h7ff0))
8395 sync_asi = 1'b1;
8396 end
8397 8'h48://IRF ECC
8398 begin
8399 //if ((`ASI_ADDR_28 >= 0) & (`ASI_ADDR_28 <= 40'hF8))
8400 sync_asi = 1'b1;
8401 end
8402 8'h49://FRF ECC
8403 begin
8404 //if ((`ASI_ADDR_28 >= 0) & (`ASI_ADDR_28 <= 40'hF8))
8405 sync_asi = 1'b1;
8406 end
8407 8'h4A://STB access, stb ptr can be read also
8408 begin
8409 //if ((`ASI_ADDR_28 >= 0) & (`ASI_ADDR_28 <= 40'h100))
8410 sync_asi = 1'b1;
8411 end
8412 8'h5A://Tick compare reg
8413 begin
8414 //if ((`ASI_ADDR_28 >= 0) & (`ASI_ADDR_28 <= 40'h38))
8415 sync_asi = 1'b1;
8416 end
8417 8'h5B://TSA
8418 begin
8419 //if ((`ASI_ADDR_28 >= 0) & (`ASI_ADDR_28 <= 40'h38))
8420 sync_asi = 1'b1;
8421 end
8422 8'h51://MRA
8423 begin
8424 //if ((`ASI_ADDR_28 >= 0) & (`ASI_ADDR_28 <= 40'h38))
8425 sync_asi = 1'b1;
8426 end
8427 8'h59://scratchpad ecc data read
8428 begin
8429 //if ((`ASI_ADDR_28 >= 0) & (`ASI_ADDR_28 <= 40'h38))
8430 //syncup the ecc data only. For ecc bit 6 is 0.
8431 if (~`SPC3.lsu.lmd.lmq4_pkt[6])
8432 sync_asi = 1'b1;
8433 end
8434 8'h40://cwqcsr,ma_sync access
8435 begin
8436 if ((`ASI_ADDR_28 == 40'h20) || (`ASI_ADDR_28 == 40'h30)
8437 || (`ASI_ADDR_28 == 40'h80)
8438 || ((`ASI_ADDR_28 == 40'ha0) & (`SPU_MA_BUSY_3 == 0) & (`SPU_MA_TID_3 == 4))
8439 )
8440 sync_asi = 1'b1;
8441 end
8442 8'h4C://CLESR, CLFESR access
8443 begin
8444 if ((`ASI_ADDR_28 == 40'h20) || (`ASI_ADDR_28 == 40'h28))
8445 sync_asi = 1'b1;
8446 end
8447 endcase
8448 end
8449
8450 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
8451 begin
8452 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_28, `ASI_ADDR_28, ld_data_w);
8453 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_28, {24'b0, `ASI_ADDR_28}, ld_data_w[63:0]);
8454 end
8455end //}
8456`endif
8457endmodule
8458
8459
8460
8461module err_c3t5 ();
8462`ifndef GATESIM
8463
8464`include "defines.vh"
8465
8466wire [2:0] mycid;
8467wire [2:0] mytid;
8468wire [5:0] mytnum;
8469
8470integer junk;
8471reg ready;
8472reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
8473reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
8474
8475reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
8476reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
8477
8478reg update_dfesr_w;
8479
8480reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
8481reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
8482
8483reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
8484reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
8485
8486reg sync_asi;
8487reg chk_if_asi_ld;
8488reg [63:0] ld_data_w;
8489
8490reg desr_asi_rd, desr_wr, desr_pend_wr;
8491
8492assign mycid = 3;
8493assign mytid = 5;
8494assign mytnum = 3*8 + 5;
8495
8496initial begin //{
8497 desr_asi_rd = 1'b0;
8498 desr_pend_wr = 1'b0;
8499 ready = 0;
8500 @(posedge `SPC3.l2clk) ;
8501 @(posedge `SPC3.l2clk) ;
8502 ready = `PARGS.err_sync_on;
8503end //}
8504
8505`define DSFSR_NEW_IN_29 `SPC3.tlu.ras.dsfsr_5_new_in
8506`define ISFSR_NEW_IN_29 `SPC3.tlu.ras.isfsr_5_new_in
8507
8508`define DSFSR_29 `SPC3.tlu.ras.dsfsr_5
8509`define ISFSR_29 `SPC3.tlu.ras.isfsr_5
8510`define DSFAR_29 `SPC3.tlu.dfd.dsfar_5
8511
8512`define ASI_WR_DSFSR_29 `SPC3.tlu.ras.asi_wr_dsfsr[5]
8513`define ASI_WR_ISFSR_29 `SPC3.tlu.ras.asi_wr_isfsr[5]
8514
8515`define RAS_WRITE_DESR_1st_29 `SPC3.tlu.dfd.ras_write_desr_1st[5]
8516`define RAS_WRITE_DESR_2nd_29 `SPC3.tlu.dfd.ras_write_desr_2nd[5]
8517`define DESR_asi_rd_29 `SPC3.tlu.ras_rd_desr[5]
8518`define DESR_29 `SPC3.tlu.dfd.desr_5
8519
8520`define RAS_WRITE_FESR_29 `SPC3.tlu.ras.write_fesr[5]
8521`define FESR_29 `SPC3.tlu.dfd.fesr_5
8522
8523`define ST_ERR_29 `SPC3.tlu.trl1.take_ftt & `SPC3.tlu.trl1.trap[1]
8524`define SW_REC_ERR_29 `SPC3.tlu.trl1.take_ade & `SPC3.tlu.trl1.trap[1]
8525`define DATA_ACC_ERR_29 `SPC3.tlu.trl1.take_dae & `SPC3.tlu.trl1.trap[1]
8526`define INST_ACC_ERR_29 `SPC3.tlu.trl1.take_iae & `SPC3.tlu.trl1.trap[1]
8527`define INT_PROC_ERR_29 `SPC3.tlu.trl1.take_ipe & `SPC3.tlu.trl1.trap[1]
8528`define HW_CORR_ERR_29 `SPC3.tlu.trl1.take_eer & `SPC3.tlu.trl1.trap[1]
8529`define INST_ACC_MMU_ERR_29 `SPC3.tlu.trl1.take_ime & `SPC3.tlu.trl1.trap[1]
8530`define DATA_ACC_MMU_ERR_29 `SPC3.tlu.trl1.take_dme & `SPC3.tlu.trl1.trap[1]
8531
8532`define LSU_LD_VALID_B `PROBES3.lsu_ld_valid
8533`define LSU_TID_DEC_B_29 `PROBES3.lsu_tid_dec_b[5]
8534`define ASI_LD_29 `SPC3.lsu.lmd.lmq5_pkt[60] & (`SPC3.lsu.lmd.lmq5_pkt[49:48] == 2'b0)
8535`define ASI_29 `SPC3.lsu.lmd.lmq5_pkt[47:40]
8536`define ASI_ADDR_29 `SPC3.lsu.lmd.lmq5_pkt[39:0]
8537`define ASI_LD_DATA_29 `SPC3.lsu_exu_ld_data_b[63:0]
8538`define ASI_LD_COMP_29 tb_top.nas_top.c3.t5.complete_fw2
8539
8540//SPU specific - only one SPU per core
8541`define SPU_MA_BUSY_3 `SPC3.spu.spu_pmu_ma_busy[3]
8542`define SPU_MA_TID_3 `SPC3.spu.spu_pmu_ma_busy[2:0]
8543
8544////////////////////////////////////////////////////////////////////////////////
8545//Capture the status register data from rtl. For disrupting traps,
8546//rtl can modify the contents of the status register before the
8547//trap is taken and intp message is sent to Riesling.
8548//For precise traps, once the status register is updated rtl can't
8549//change the register again before jumping to the trap handler.
8550//So, for deferred and disrupting traps, inform Riesling when the
8551//register is modified while for precise traps wait until Fw2 before
8552//telling Riesling.
8553
8554//TLU asserts the flush and input signals in W stage. I latch them at the
8555//+ve edge of FX4.
8556
8557always @(negedge (`SPC3.l2clk & ready))
8558begin // {
8559 if (`DESR_asi_rd_29)
8560 desr_asi_rd <= 1'b1;
8561 if (desr_asi_rd)
8562 begin
8563 if (desr_wr)
8564 desr_pend_wr <= 1'b1;
8565 if (`ASI_LD_COMP_29[2])
8566 desr_asi_rd <= 1'b0;
8567 end
8568
8569 update_dsfsr_w <= (`DSFSR_NEW_IN_29 != 4'b0) && ~`ASI_WR_DSFSR_29;
8570 update_isfsr_w <= (`ISFSR_NEW_IN_29 != 3'b0) && ~`ASI_WR_ISFSR_29;
8571 desr_wr <= (`RAS_WRITE_DESR_1st_29 || `RAS_WRITE_DESR_2nd_29);
8572 update_dfesr_w <= `RAS_WRITE_FESR_29;
8573 take_err_trap_fx4 <= `ST_ERR_29 | `SW_REC_ERR_29 | `DATA_ACC_ERR_29
8574 | `INST_ACC_ERR_29 | `INT_PROC_ERR_29
8575 | `HW_CORR_ERR_29 | `INST_ACC_MMU_ERR_29
8576 | `DATA_ACC_MMU_ERR_29 ;
8577
8578
8579 if (`ST_ERR_29) int_num_fx4 <= 8'h07;
8580 if (`SW_REC_ERR_29) int_num_fx4 <= 8'h40;
8581 if (`DATA_ACC_ERR_29) int_num_fx4 <= 8'h32;
8582 if (`INST_ACC_ERR_29) int_num_fx4 <= 8'h0A;
8583 if (`INT_PROC_ERR_29) int_num_fx4 <= 8'h29;
8584 if (`HW_CORR_ERR_29) int_num_fx4 <= 8'h63;
8585 if (`INST_ACC_MMU_ERR_29) int_num_fx4 <= 8'h71;
8586 if (`DATA_ACC_MMU_ERR_29) int_num_fx4 <= 8'h72;
8587
8588 update_dsfsr_fx4 <= update_dsfsr_w;
8589 update_dsfsr_fx5 <= update_dsfsr_fx4;
8590 update_dsfsr_fb <= update_dsfsr_fx5;
8591 update_dsfsr_fw <= update_dsfsr_fb;
8592 update_dsfsr_fw1 <= update_dsfsr_fw;
8593 update_dsfsr_fw2 <= update_dsfsr_fw1;
8594
8595 update_isfsr_fx4 <= update_isfsr_w;
8596 update_isfsr_fx5 <= update_isfsr_fx4;
8597 update_isfsr_fb <= update_isfsr_fx5;
8598 update_isfsr_fw <= update_isfsr_fb;
8599 update_isfsr_fw1 <= update_isfsr_fw;
8600 update_isfsr_fw2 <= update_isfsr_fw1;
8601
8602 take_err_trap_fx5 <= take_err_trap_fx4;
8603 take_err_trap_fb <= take_err_trap_fx5;
8604 take_err_trap_fw <= take_err_trap_fb;
8605 take_err_trap_fw1 <= take_err_trap_fw;
8606 take_err_trap_fw2 <= take_err_trap_fw1;
8607
8608 int_num_fx5 <= int_num_fx4;
8609 int_num_fb <= int_num_fx5;
8610 int_num_fw <= int_num_fb;
8611 int_num_fw1 <= int_num_fw;
8612 int_num_fw2 <= int_num_fw1;
8613
8614 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
8615 begin // {
8616 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
8617 begin //{
8618 desr_pend_wr <= 1'b0;
8619 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_29[63:56], 45'b0, `DESR_29[10:0]});
8620 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_29[63:56], 45'b0, `DESR_29[10:0]});
8621 end //}
8622 //if (update_dfesr_w)
8623 if (`ST_ERR_29)
8624 begin //{
8625 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_29[61:55], 55'b0});
8626 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_29[61:55], 55'b0});
8627 end //}
8628 if (update_dsfsr_fw2)
8629 begin //{
8630 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
8631 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_29[3:0]});
8632 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_29[47:0]});
8633
8634 end //}
8635 if (update_isfsr_fw2)
8636 begin //{
8637 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
8638 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_29[2:0]});
8639 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_29[47:0]});
8640
8641 end //}
8642 if (take_err_trap_fw2)
8643 begin //{
8644 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
8645 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
8646 end // }
8647 end // }
8648
8649end //}
8650
8651//removing the addr check as the LSU doesn't flag an invalid_asi_exception
8652//if the addr of diagnostic accesses is not in the valid range. The inst.
8653//still executes. LSU expects that HP won't use addresses in invalid range.
8654
8655always @(negedge (`SPC3.l2clk & ready))
8656begin // {
8657 sync_asi = 1'b0;
8658 ld_data_w <= `ASI_LD_DATA_29;
8659
8660 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_29)
8661 chk_if_asi_ld <= 1'b1;
8662 else
8663 chk_if_asi_ld <= 1'b0;
8664
8665 if (chk_if_asi_ld & `ASI_LD_29)
8666 begin
8667 case (`ASI_29)
8668 8'h66: //ASI_IC_INSTR
8669 begin
8670 //if ((`ASI_ADDR_29 >= 0) & (`ASI_ADDR_29 <= 40'h7ff8))
8671 sync_asi = 1'b1;
8672 end
8673 8'h67: //ASI_IC_TAG
8674 begin
8675 //if ((`ASI_ADDR_29 >= 0) & (`ASI_ADDR_29 <= 40'h7fe0))
8676 sync_asi = 1'b1;
8677 end
8678 8'h46: //ASI_DC_DATA
8679 begin
8680 sync_asi = 1'b1;
8681 end
8682 8'h47: //ASI_DC_TAG
8683 begin
8684 //if ((`ASI_ADDR_29 >= 0) & (`ASI_ADDR_29 <= 40'h7ff0))
8685 sync_asi = 1'b1;
8686 end
8687 8'h48://IRF ECC
8688 begin
8689 //if ((`ASI_ADDR_29 >= 0) & (`ASI_ADDR_29 <= 40'hF8))
8690 sync_asi = 1'b1;
8691 end
8692 8'h49://FRF ECC
8693 begin
8694 //if ((`ASI_ADDR_29 >= 0) & (`ASI_ADDR_29 <= 40'hF8))
8695 sync_asi = 1'b1;
8696 end
8697 8'h4A://STB access, stb ptr can be read also
8698 begin
8699 //if ((`ASI_ADDR_29 >= 0) & (`ASI_ADDR_29 <= 40'h100))
8700 sync_asi = 1'b1;
8701 end
8702 8'h5A://Tick compare reg
8703 begin
8704 //if ((`ASI_ADDR_29 >= 0) & (`ASI_ADDR_29 <= 40'h38))
8705 sync_asi = 1'b1;
8706 end
8707 8'h5B://TSA
8708 begin
8709 //if ((`ASI_ADDR_29 >= 0) & (`ASI_ADDR_29 <= 40'h38))
8710 sync_asi = 1'b1;
8711 end
8712 8'h51://MRA
8713 begin
8714 //if ((`ASI_ADDR_29 >= 0) & (`ASI_ADDR_29 <= 40'h38))
8715 sync_asi = 1'b1;
8716 end
8717 8'h59://scratchpad ecc data read
8718 begin
8719 //if ((`ASI_ADDR_29 >= 0) & (`ASI_ADDR_29 <= 40'h38))
8720 //syncup the ecc data only. For ecc bit 6 is 0.
8721 if (~`SPC3.lsu.lmd.lmq5_pkt[6])
8722 sync_asi = 1'b1;
8723 end
8724 8'h40://cwqcsr,ma_sync access
8725 begin
8726 if ((`ASI_ADDR_29 == 40'h20) || (`ASI_ADDR_29 == 40'h30)
8727 || (`ASI_ADDR_29 == 40'h80)
8728 || ((`ASI_ADDR_29 == 40'ha0) & (`SPU_MA_BUSY_3 == 0) & (`SPU_MA_TID_3 == 5))
8729 )
8730 sync_asi = 1'b1;
8731 end
8732 8'h4C://CLESR, CLFESR access
8733 begin
8734 if ((`ASI_ADDR_29 == 40'h20) || (`ASI_ADDR_29 == 40'h28))
8735 sync_asi = 1'b1;
8736 end
8737 endcase
8738 end
8739
8740 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
8741 begin
8742 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_29, `ASI_ADDR_29, ld_data_w);
8743 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_29, {24'b0, `ASI_ADDR_29}, ld_data_w[63:0]);
8744 end
8745end //}
8746`endif
8747endmodule
8748
8749
8750
8751module err_c3t6 ();
8752`ifndef GATESIM
8753
8754`include "defines.vh"
8755
8756wire [2:0] mycid;
8757wire [2:0] mytid;
8758wire [5:0] mytnum;
8759
8760integer junk;
8761reg ready;
8762reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
8763reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
8764
8765reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
8766reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
8767
8768reg update_dfesr_w;
8769
8770reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
8771reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
8772
8773reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
8774reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
8775
8776reg sync_asi;
8777reg chk_if_asi_ld;
8778reg [63:0] ld_data_w;
8779
8780reg desr_asi_rd, desr_wr, desr_pend_wr;
8781
8782assign mycid = 3;
8783assign mytid = 6;
8784assign mytnum = 3*8 + 6;
8785
8786initial begin //{
8787 desr_asi_rd = 1'b0;
8788 desr_pend_wr = 1'b0;
8789 ready = 0;
8790 @(posedge `SPC3.l2clk) ;
8791 @(posedge `SPC3.l2clk) ;
8792 ready = `PARGS.err_sync_on;
8793end //}
8794
8795`define DSFSR_NEW_IN_30 `SPC3.tlu.ras.dsfsr_6_new_in
8796`define ISFSR_NEW_IN_30 `SPC3.tlu.ras.isfsr_6_new_in
8797
8798`define DSFSR_30 `SPC3.tlu.ras.dsfsr_6
8799`define ISFSR_30 `SPC3.tlu.ras.isfsr_6
8800`define DSFAR_30 `SPC3.tlu.dfd.dsfar_6
8801
8802`define ASI_WR_DSFSR_30 `SPC3.tlu.ras.asi_wr_dsfsr[6]
8803`define ASI_WR_ISFSR_30 `SPC3.tlu.ras.asi_wr_isfsr[6]
8804
8805`define RAS_WRITE_DESR_1st_30 `SPC3.tlu.dfd.ras_write_desr_1st[6]
8806`define RAS_WRITE_DESR_2nd_30 `SPC3.tlu.dfd.ras_write_desr_2nd[6]
8807`define DESR_asi_rd_30 `SPC3.tlu.ras_rd_desr[6]
8808`define DESR_30 `SPC3.tlu.dfd.desr_6
8809
8810`define RAS_WRITE_FESR_30 `SPC3.tlu.ras.write_fesr[6]
8811`define FESR_30 `SPC3.tlu.dfd.fesr_6
8812
8813`define ST_ERR_30 `SPC3.tlu.trl1.take_ftt & `SPC3.tlu.trl1.trap[2]
8814`define SW_REC_ERR_30 `SPC3.tlu.trl1.take_ade & `SPC3.tlu.trl1.trap[2]
8815`define DATA_ACC_ERR_30 `SPC3.tlu.trl1.take_dae & `SPC3.tlu.trl1.trap[2]
8816`define INST_ACC_ERR_30 `SPC3.tlu.trl1.take_iae & `SPC3.tlu.trl1.trap[2]
8817`define INT_PROC_ERR_30 `SPC3.tlu.trl1.take_ipe & `SPC3.tlu.trl1.trap[2]
8818`define HW_CORR_ERR_30 `SPC3.tlu.trl1.take_eer & `SPC3.tlu.trl1.trap[2]
8819`define INST_ACC_MMU_ERR_30 `SPC3.tlu.trl1.take_ime & `SPC3.tlu.trl1.trap[2]
8820`define DATA_ACC_MMU_ERR_30 `SPC3.tlu.trl1.take_dme & `SPC3.tlu.trl1.trap[2]
8821
8822`define LSU_LD_VALID_B `PROBES3.lsu_ld_valid
8823`define LSU_TID_DEC_B_30 `PROBES3.lsu_tid_dec_b[6]
8824`define ASI_LD_30 `SPC3.lsu.lmd.lmq6_pkt[60] & (`SPC3.lsu.lmd.lmq6_pkt[49:48] == 2'b0)
8825`define ASI_30 `SPC3.lsu.lmd.lmq6_pkt[47:40]
8826`define ASI_ADDR_30 `SPC3.lsu.lmd.lmq6_pkt[39:0]
8827`define ASI_LD_DATA_30 `SPC3.lsu_exu_ld_data_b[63:0]
8828`define ASI_LD_COMP_30 tb_top.nas_top.c3.t6.complete_fw2
8829
8830//SPU specific - only one SPU per core
8831`define SPU_MA_BUSY_3 `SPC3.spu.spu_pmu_ma_busy[3]
8832`define SPU_MA_TID_3 `SPC3.spu.spu_pmu_ma_busy[2:0]
8833
8834////////////////////////////////////////////////////////////////////////////////
8835//Capture the status register data from rtl. For disrupting traps,
8836//rtl can modify the contents of the status register before the
8837//trap is taken and intp message is sent to Riesling.
8838//For precise traps, once the status register is updated rtl can't
8839//change the register again before jumping to the trap handler.
8840//So, for deferred and disrupting traps, inform Riesling when the
8841//register is modified while for precise traps wait until Fw2 before
8842//telling Riesling.
8843
8844//TLU asserts the flush and input signals in W stage. I latch them at the
8845//+ve edge of FX4.
8846
8847always @(negedge (`SPC3.l2clk & ready))
8848begin // {
8849 if (`DESR_asi_rd_30)
8850 desr_asi_rd <= 1'b1;
8851 if (desr_asi_rd)
8852 begin
8853 if (desr_wr)
8854 desr_pend_wr <= 1'b1;
8855 if (`ASI_LD_COMP_30[2])
8856 desr_asi_rd <= 1'b0;
8857 end
8858
8859 update_dsfsr_w <= (`DSFSR_NEW_IN_30 != 4'b0) && ~`ASI_WR_DSFSR_30;
8860 update_isfsr_w <= (`ISFSR_NEW_IN_30 != 3'b0) && ~`ASI_WR_ISFSR_30;
8861 desr_wr <= (`RAS_WRITE_DESR_1st_30 || `RAS_WRITE_DESR_2nd_30);
8862 update_dfesr_w <= `RAS_WRITE_FESR_30;
8863 take_err_trap_fx4 <= `ST_ERR_30 | `SW_REC_ERR_30 | `DATA_ACC_ERR_30
8864 | `INST_ACC_ERR_30 | `INT_PROC_ERR_30
8865 | `HW_CORR_ERR_30 | `INST_ACC_MMU_ERR_30
8866 | `DATA_ACC_MMU_ERR_30 ;
8867
8868
8869 if (`ST_ERR_30) int_num_fx4 <= 8'h07;
8870 if (`SW_REC_ERR_30) int_num_fx4 <= 8'h40;
8871 if (`DATA_ACC_ERR_30) int_num_fx4 <= 8'h32;
8872 if (`INST_ACC_ERR_30) int_num_fx4 <= 8'h0A;
8873 if (`INT_PROC_ERR_30) int_num_fx4 <= 8'h29;
8874 if (`HW_CORR_ERR_30) int_num_fx4 <= 8'h63;
8875 if (`INST_ACC_MMU_ERR_30) int_num_fx4 <= 8'h71;
8876 if (`DATA_ACC_MMU_ERR_30) int_num_fx4 <= 8'h72;
8877
8878 update_dsfsr_fx4 <= update_dsfsr_w;
8879 update_dsfsr_fx5 <= update_dsfsr_fx4;
8880 update_dsfsr_fb <= update_dsfsr_fx5;
8881 update_dsfsr_fw <= update_dsfsr_fb;
8882 update_dsfsr_fw1 <= update_dsfsr_fw;
8883 update_dsfsr_fw2 <= update_dsfsr_fw1;
8884
8885 update_isfsr_fx4 <= update_isfsr_w;
8886 update_isfsr_fx5 <= update_isfsr_fx4;
8887 update_isfsr_fb <= update_isfsr_fx5;
8888 update_isfsr_fw <= update_isfsr_fb;
8889 update_isfsr_fw1 <= update_isfsr_fw;
8890 update_isfsr_fw2 <= update_isfsr_fw1;
8891
8892 take_err_trap_fx5 <= take_err_trap_fx4;
8893 take_err_trap_fb <= take_err_trap_fx5;
8894 take_err_trap_fw <= take_err_trap_fb;
8895 take_err_trap_fw1 <= take_err_trap_fw;
8896 take_err_trap_fw2 <= take_err_trap_fw1;
8897
8898 int_num_fx5 <= int_num_fx4;
8899 int_num_fb <= int_num_fx5;
8900 int_num_fw <= int_num_fb;
8901 int_num_fw1 <= int_num_fw;
8902 int_num_fw2 <= int_num_fw1;
8903
8904 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
8905 begin // {
8906 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
8907 begin //{
8908 desr_pend_wr <= 1'b0;
8909 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_30[63:56], 45'b0, `DESR_30[10:0]});
8910 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_30[63:56], 45'b0, `DESR_30[10:0]});
8911 end //}
8912 //if (update_dfesr_w)
8913 if (`ST_ERR_30)
8914 begin //{
8915 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_30[61:55], 55'b0});
8916 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_30[61:55], 55'b0});
8917 end //}
8918 if (update_dsfsr_fw2)
8919 begin //{
8920 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
8921 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_30[3:0]});
8922 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_30[47:0]});
8923
8924 end //}
8925 if (update_isfsr_fw2)
8926 begin //{
8927 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
8928 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_30[2:0]});
8929 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_30[47:0]});
8930
8931 end //}
8932 if (take_err_trap_fw2)
8933 begin //{
8934 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
8935 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
8936 end // }
8937 end // }
8938
8939end //}
8940
8941//removing the addr check as the LSU doesn't flag an invalid_asi_exception
8942//if the addr of diagnostic accesses is not in the valid range. The inst.
8943//still executes. LSU expects that HP won't use addresses in invalid range.
8944
8945always @(negedge (`SPC3.l2clk & ready))
8946begin // {
8947 sync_asi = 1'b0;
8948 ld_data_w <= `ASI_LD_DATA_30;
8949
8950 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_30)
8951 chk_if_asi_ld <= 1'b1;
8952 else
8953 chk_if_asi_ld <= 1'b0;
8954
8955 if (chk_if_asi_ld & `ASI_LD_30)
8956 begin
8957 case (`ASI_30)
8958 8'h66: //ASI_IC_INSTR
8959 begin
8960 //if ((`ASI_ADDR_30 >= 0) & (`ASI_ADDR_30 <= 40'h7ff8))
8961 sync_asi = 1'b1;
8962 end
8963 8'h67: //ASI_IC_TAG
8964 begin
8965 //if ((`ASI_ADDR_30 >= 0) & (`ASI_ADDR_30 <= 40'h7fe0))
8966 sync_asi = 1'b1;
8967 end
8968 8'h46: //ASI_DC_DATA
8969 begin
8970 sync_asi = 1'b1;
8971 end
8972 8'h47: //ASI_DC_TAG
8973 begin
8974 //if ((`ASI_ADDR_30 >= 0) & (`ASI_ADDR_30 <= 40'h7ff0))
8975 sync_asi = 1'b1;
8976 end
8977 8'h48://IRF ECC
8978 begin
8979 //if ((`ASI_ADDR_30 >= 0) & (`ASI_ADDR_30 <= 40'hF8))
8980 sync_asi = 1'b1;
8981 end
8982 8'h49://FRF ECC
8983 begin
8984 //if ((`ASI_ADDR_30 >= 0) & (`ASI_ADDR_30 <= 40'hF8))
8985 sync_asi = 1'b1;
8986 end
8987 8'h4A://STB access, stb ptr can be read also
8988 begin
8989 //if ((`ASI_ADDR_30 >= 0) & (`ASI_ADDR_30 <= 40'h100))
8990 sync_asi = 1'b1;
8991 end
8992 8'h5A://Tick compare reg
8993 begin
8994 //if ((`ASI_ADDR_30 >= 0) & (`ASI_ADDR_30 <= 40'h38))
8995 sync_asi = 1'b1;
8996 end
8997 8'h5B://TSA
8998 begin
8999 //if ((`ASI_ADDR_30 >= 0) & (`ASI_ADDR_30 <= 40'h38))
9000 sync_asi = 1'b1;
9001 end
9002 8'h51://MRA
9003 begin
9004 //if ((`ASI_ADDR_30 >= 0) & (`ASI_ADDR_30 <= 40'h38))
9005 sync_asi = 1'b1;
9006 end
9007 8'h59://scratchpad ecc data read
9008 begin
9009 //if ((`ASI_ADDR_30 >= 0) & (`ASI_ADDR_30 <= 40'h38))
9010 //syncup the ecc data only. For ecc bit 6 is 0.
9011 if (~`SPC3.lsu.lmd.lmq6_pkt[6])
9012 sync_asi = 1'b1;
9013 end
9014 8'h40://cwqcsr,ma_sync access
9015 begin
9016 if ((`ASI_ADDR_30 == 40'h20) || (`ASI_ADDR_30 == 40'h30)
9017 || (`ASI_ADDR_30 == 40'h80)
9018 || ((`ASI_ADDR_30 == 40'ha0) & (`SPU_MA_BUSY_3 == 0) & (`SPU_MA_TID_3 == 6))
9019 )
9020 sync_asi = 1'b1;
9021 end
9022 8'h4C://CLESR, CLFESR access
9023 begin
9024 if ((`ASI_ADDR_30 == 40'h20) || (`ASI_ADDR_30 == 40'h28))
9025 sync_asi = 1'b1;
9026 end
9027 endcase
9028 end
9029
9030 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
9031 begin
9032 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_30, `ASI_ADDR_30, ld_data_w);
9033 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_30, {24'b0, `ASI_ADDR_30}, ld_data_w[63:0]);
9034 end
9035end //}
9036`endif
9037endmodule
9038
9039
9040
9041module err_c3t7 ();
9042`ifndef GATESIM
9043
9044`include "defines.vh"
9045
9046wire [2:0] mycid;
9047wire [2:0] mytid;
9048wire [5:0] mytnum;
9049
9050integer junk;
9051reg ready;
9052reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
9053reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
9054
9055reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
9056reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
9057
9058reg update_dfesr_w;
9059
9060reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
9061reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
9062
9063reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
9064reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
9065
9066reg sync_asi;
9067reg chk_if_asi_ld;
9068reg [63:0] ld_data_w;
9069
9070reg desr_asi_rd, desr_wr, desr_pend_wr;
9071
9072assign mycid = 3;
9073assign mytid = 7;
9074assign mytnum = 3*8 + 7;
9075
9076initial begin //{
9077 desr_asi_rd = 1'b0;
9078 desr_pend_wr = 1'b0;
9079 ready = 0;
9080 @(posedge `SPC3.l2clk) ;
9081 @(posedge `SPC3.l2clk) ;
9082 ready = `PARGS.err_sync_on;
9083end //}
9084
9085`define DSFSR_NEW_IN_31 `SPC3.tlu.ras.dsfsr_7_new_in
9086`define ISFSR_NEW_IN_31 `SPC3.tlu.ras.isfsr_7_new_in
9087
9088`define DSFSR_31 `SPC3.tlu.ras.dsfsr_7
9089`define ISFSR_31 `SPC3.tlu.ras.isfsr_7
9090`define DSFAR_31 `SPC3.tlu.dfd.dsfar_7
9091
9092`define ASI_WR_DSFSR_31 `SPC3.tlu.ras.asi_wr_dsfsr[7]
9093`define ASI_WR_ISFSR_31 `SPC3.tlu.ras.asi_wr_isfsr[7]
9094
9095`define RAS_WRITE_DESR_1st_31 `SPC3.tlu.dfd.ras_write_desr_1st[7]
9096`define RAS_WRITE_DESR_2nd_31 `SPC3.tlu.dfd.ras_write_desr_2nd[7]
9097`define DESR_asi_rd_31 `SPC3.tlu.ras_rd_desr[7]
9098`define DESR_31 `SPC3.tlu.dfd.desr_7
9099
9100`define RAS_WRITE_FESR_31 `SPC3.tlu.ras.write_fesr[7]
9101`define FESR_31 `SPC3.tlu.dfd.fesr_7
9102
9103`define ST_ERR_31 `SPC3.tlu.trl1.take_ftt & `SPC3.tlu.trl1.trap[3]
9104`define SW_REC_ERR_31 `SPC3.tlu.trl1.take_ade & `SPC3.tlu.trl1.trap[3]
9105`define DATA_ACC_ERR_31 `SPC3.tlu.trl1.take_dae & `SPC3.tlu.trl1.trap[3]
9106`define INST_ACC_ERR_31 `SPC3.tlu.trl1.take_iae & `SPC3.tlu.trl1.trap[3]
9107`define INT_PROC_ERR_31 `SPC3.tlu.trl1.take_ipe & `SPC3.tlu.trl1.trap[3]
9108`define HW_CORR_ERR_31 `SPC3.tlu.trl1.take_eer & `SPC3.tlu.trl1.trap[3]
9109`define INST_ACC_MMU_ERR_31 `SPC3.tlu.trl1.take_ime & `SPC3.tlu.trl1.trap[3]
9110`define DATA_ACC_MMU_ERR_31 `SPC3.tlu.trl1.take_dme & `SPC3.tlu.trl1.trap[3]
9111
9112`define LSU_LD_VALID_B `PROBES3.lsu_ld_valid
9113`define LSU_TID_DEC_B_31 `PROBES3.lsu_tid_dec_b[7]
9114`define ASI_LD_31 `SPC3.lsu.lmd.lmq7_pkt[60] & (`SPC3.lsu.lmd.lmq7_pkt[49:48] == 2'b0)
9115`define ASI_31 `SPC3.lsu.lmd.lmq7_pkt[47:40]
9116`define ASI_ADDR_31 `SPC3.lsu.lmd.lmq7_pkt[39:0]
9117`define ASI_LD_DATA_31 `SPC3.lsu_exu_ld_data_b[63:0]
9118`define ASI_LD_COMP_31 tb_top.nas_top.c3.t7.complete_fw2
9119
9120//SPU specific - only one SPU per core
9121`define SPU_MA_BUSY_3 `SPC3.spu.spu_pmu_ma_busy[3]
9122`define SPU_MA_TID_3 `SPC3.spu.spu_pmu_ma_busy[2:0]
9123
9124////////////////////////////////////////////////////////////////////////////////
9125//Capture the status register data from rtl. For disrupting traps,
9126//rtl can modify the contents of the status register before the
9127//trap is taken and intp message is sent to Riesling.
9128//For precise traps, once the status register is updated rtl can't
9129//change the register again before jumping to the trap handler.
9130//So, for deferred and disrupting traps, inform Riesling when the
9131//register is modified while for precise traps wait until Fw2 before
9132//telling Riesling.
9133
9134//TLU asserts the flush and input signals in W stage. I latch them at the
9135//+ve edge of FX4.
9136
9137always @(negedge (`SPC3.l2clk & ready))
9138begin // {
9139 if (`DESR_asi_rd_31)
9140 desr_asi_rd <= 1'b1;
9141 if (desr_asi_rd)
9142 begin
9143 if (desr_wr)
9144 desr_pend_wr <= 1'b1;
9145 if (`ASI_LD_COMP_31[2])
9146 desr_asi_rd <= 1'b0;
9147 end
9148
9149 update_dsfsr_w <= (`DSFSR_NEW_IN_31 != 4'b0) && ~`ASI_WR_DSFSR_31;
9150 update_isfsr_w <= (`ISFSR_NEW_IN_31 != 3'b0) && ~`ASI_WR_ISFSR_31;
9151 desr_wr <= (`RAS_WRITE_DESR_1st_31 || `RAS_WRITE_DESR_2nd_31);
9152 update_dfesr_w <= `RAS_WRITE_FESR_31;
9153 take_err_trap_fx4 <= `ST_ERR_31 | `SW_REC_ERR_31 | `DATA_ACC_ERR_31
9154 | `INST_ACC_ERR_31 | `INT_PROC_ERR_31
9155 | `HW_CORR_ERR_31 | `INST_ACC_MMU_ERR_31
9156 | `DATA_ACC_MMU_ERR_31 ;
9157
9158
9159 if (`ST_ERR_31) int_num_fx4 <= 8'h07;
9160 if (`SW_REC_ERR_31) int_num_fx4 <= 8'h40;
9161 if (`DATA_ACC_ERR_31) int_num_fx4 <= 8'h32;
9162 if (`INST_ACC_ERR_31) int_num_fx4 <= 8'h0A;
9163 if (`INT_PROC_ERR_31) int_num_fx4 <= 8'h29;
9164 if (`HW_CORR_ERR_31) int_num_fx4 <= 8'h63;
9165 if (`INST_ACC_MMU_ERR_31) int_num_fx4 <= 8'h71;
9166 if (`DATA_ACC_MMU_ERR_31) int_num_fx4 <= 8'h72;
9167
9168 update_dsfsr_fx4 <= update_dsfsr_w;
9169 update_dsfsr_fx5 <= update_dsfsr_fx4;
9170 update_dsfsr_fb <= update_dsfsr_fx5;
9171 update_dsfsr_fw <= update_dsfsr_fb;
9172 update_dsfsr_fw1 <= update_dsfsr_fw;
9173 update_dsfsr_fw2 <= update_dsfsr_fw1;
9174
9175 update_isfsr_fx4 <= update_isfsr_w;
9176 update_isfsr_fx5 <= update_isfsr_fx4;
9177 update_isfsr_fb <= update_isfsr_fx5;
9178 update_isfsr_fw <= update_isfsr_fb;
9179 update_isfsr_fw1 <= update_isfsr_fw;
9180 update_isfsr_fw2 <= update_isfsr_fw1;
9181
9182 take_err_trap_fx5 <= take_err_trap_fx4;
9183 take_err_trap_fb <= take_err_trap_fx5;
9184 take_err_trap_fw <= take_err_trap_fb;
9185 take_err_trap_fw1 <= take_err_trap_fw;
9186 take_err_trap_fw2 <= take_err_trap_fw1;
9187
9188 int_num_fx5 <= int_num_fx4;
9189 int_num_fb <= int_num_fx5;
9190 int_num_fw <= int_num_fb;
9191 int_num_fw1 <= int_num_fw;
9192 int_num_fw2 <= int_num_fw1;
9193
9194 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
9195 begin // {
9196 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
9197 begin //{
9198 desr_pend_wr <= 1'b0;
9199 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_31[63:56], 45'b0, `DESR_31[10:0]});
9200 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_31[63:56], 45'b0, `DESR_31[10:0]});
9201 end //}
9202 //if (update_dfesr_w)
9203 if (`ST_ERR_31)
9204 begin //{
9205 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_31[61:55], 55'b0});
9206 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_31[61:55], 55'b0});
9207 end //}
9208 if (update_dsfsr_fw2)
9209 begin //{
9210 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
9211 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_31[3:0]});
9212 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_31[47:0]});
9213
9214 end //}
9215 if (update_isfsr_fw2)
9216 begin //{
9217 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
9218 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_31[2:0]});
9219 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_31[47:0]});
9220
9221 end //}
9222 if (take_err_trap_fw2)
9223 begin //{
9224 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
9225 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
9226 end // }
9227 end // }
9228
9229end //}
9230
9231//removing the addr check as the LSU doesn't flag an invalid_asi_exception
9232//if the addr of diagnostic accesses is not in the valid range. The inst.
9233//still executes. LSU expects that HP won't use addresses in invalid range.
9234
9235always @(negedge (`SPC3.l2clk & ready))
9236begin // {
9237 sync_asi = 1'b0;
9238 ld_data_w <= `ASI_LD_DATA_31;
9239
9240 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_31)
9241 chk_if_asi_ld <= 1'b1;
9242 else
9243 chk_if_asi_ld <= 1'b0;
9244
9245 if (chk_if_asi_ld & `ASI_LD_31)
9246 begin
9247 case (`ASI_31)
9248 8'h66: //ASI_IC_INSTR
9249 begin
9250 //if ((`ASI_ADDR_31 >= 0) & (`ASI_ADDR_31 <= 40'h7ff8))
9251 sync_asi = 1'b1;
9252 end
9253 8'h67: //ASI_IC_TAG
9254 begin
9255 //if ((`ASI_ADDR_31 >= 0) & (`ASI_ADDR_31 <= 40'h7fe0))
9256 sync_asi = 1'b1;
9257 end
9258 8'h46: //ASI_DC_DATA
9259 begin
9260 sync_asi = 1'b1;
9261 end
9262 8'h47: //ASI_DC_TAG
9263 begin
9264 //if ((`ASI_ADDR_31 >= 0) & (`ASI_ADDR_31 <= 40'h7ff0))
9265 sync_asi = 1'b1;
9266 end
9267 8'h48://IRF ECC
9268 begin
9269 //if ((`ASI_ADDR_31 >= 0) & (`ASI_ADDR_31 <= 40'hF8))
9270 sync_asi = 1'b1;
9271 end
9272 8'h49://FRF ECC
9273 begin
9274 //if ((`ASI_ADDR_31 >= 0) & (`ASI_ADDR_31 <= 40'hF8))
9275 sync_asi = 1'b1;
9276 end
9277 8'h4A://STB access, stb ptr can be read also
9278 begin
9279 //if ((`ASI_ADDR_31 >= 0) & (`ASI_ADDR_31 <= 40'h100))
9280 sync_asi = 1'b1;
9281 end
9282 8'h5A://Tick compare reg
9283 begin
9284 //if ((`ASI_ADDR_31 >= 0) & (`ASI_ADDR_31 <= 40'h38))
9285 sync_asi = 1'b1;
9286 end
9287 8'h5B://TSA
9288 begin
9289 //if ((`ASI_ADDR_31 >= 0) & (`ASI_ADDR_31 <= 40'h38))
9290 sync_asi = 1'b1;
9291 end
9292 8'h51://MRA
9293 begin
9294 //if ((`ASI_ADDR_31 >= 0) & (`ASI_ADDR_31 <= 40'h38))
9295 sync_asi = 1'b1;
9296 end
9297 8'h59://scratchpad ecc data read
9298 begin
9299 //if ((`ASI_ADDR_31 >= 0) & (`ASI_ADDR_31 <= 40'h38))
9300 //syncup the ecc data only. For ecc bit 6 is 0.
9301 if (~`SPC3.lsu.lmd.lmq7_pkt[6])
9302 sync_asi = 1'b1;
9303 end
9304 8'h40://cwqcsr,ma_sync access
9305 begin
9306 if ((`ASI_ADDR_31 == 40'h20) || (`ASI_ADDR_31 == 40'h30)
9307 || (`ASI_ADDR_31 == 40'h80)
9308 || ((`ASI_ADDR_31 == 40'ha0) & (`SPU_MA_BUSY_3 == 0) & (`SPU_MA_TID_3 == 7))
9309 )
9310 sync_asi = 1'b1;
9311 end
9312 8'h4C://CLESR, CLFESR access
9313 begin
9314 if ((`ASI_ADDR_31 == 40'h20) || (`ASI_ADDR_31 == 40'h28))
9315 sync_asi = 1'b1;
9316 end
9317 endcase
9318 end
9319
9320 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
9321 begin
9322 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_31, `ASI_ADDR_31, ld_data_w);
9323 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_31, {24'b0, `ASI_ADDR_31}, ld_data_w[63:0]);
9324 end
9325end //}
9326`endif
9327endmodule
9328
9329`endif
9330
9331`ifdef CORE_4
9332
9333
9334
9335module err_c4t0 ();
9336`ifndef GATESIM
9337
9338`include "defines.vh"
9339
9340wire [2:0] mycid;
9341wire [2:0] mytid;
9342wire [5:0] mytnum;
9343
9344integer junk;
9345reg ready;
9346reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
9347reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
9348
9349reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
9350reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
9351
9352reg update_dfesr_w;
9353
9354reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
9355reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
9356
9357reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
9358reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
9359
9360reg sync_asi;
9361reg chk_if_asi_ld;
9362reg [63:0] ld_data_w;
9363
9364reg desr_asi_rd, desr_wr, desr_pend_wr;
9365
9366assign mycid = 4;
9367assign mytid = 0;
9368assign mytnum = 4*8 + 0;
9369
9370initial begin //{
9371 desr_asi_rd = 1'b0;
9372 desr_pend_wr = 1'b0;
9373 ready = 0;
9374 @(posedge `SPC4.l2clk) ;
9375 @(posedge `SPC4.l2clk) ;
9376 ready = `PARGS.err_sync_on;
9377end //}
9378
9379`define DSFSR_NEW_IN_32 `SPC4.tlu.ras.dsfsr_0_new_in
9380`define ISFSR_NEW_IN_32 `SPC4.tlu.ras.isfsr_0_new_in
9381
9382`define DSFSR_32 `SPC4.tlu.ras.dsfsr_0
9383`define ISFSR_32 `SPC4.tlu.ras.isfsr_0
9384`define DSFAR_32 `SPC4.tlu.dfd.dsfar_0
9385
9386`define ASI_WR_DSFSR_32 `SPC4.tlu.ras.asi_wr_dsfsr[0]
9387`define ASI_WR_ISFSR_32 `SPC4.tlu.ras.asi_wr_isfsr[0]
9388
9389`define RAS_WRITE_DESR_1st_32 `SPC4.tlu.dfd.ras_write_desr_1st[0]
9390`define RAS_WRITE_DESR_2nd_32 `SPC4.tlu.dfd.ras_write_desr_2nd[0]
9391`define DESR_asi_rd_32 `SPC4.tlu.ras_rd_desr[0]
9392`define DESR_32 `SPC4.tlu.dfd.desr_0
9393
9394`define RAS_WRITE_FESR_32 `SPC4.tlu.ras.write_fesr[0]
9395`define FESR_32 `SPC4.tlu.dfd.fesr_0
9396
9397`define ST_ERR_32 `SPC4.tlu.trl0.take_ftt & `SPC4.tlu.trl0.trap[0]
9398`define SW_REC_ERR_32 `SPC4.tlu.trl0.take_ade & `SPC4.tlu.trl0.trap[0]
9399`define DATA_ACC_ERR_32 `SPC4.tlu.trl0.take_dae & `SPC4.tlu.trl0.trap[0]
9400`define INST_ACC_ERR_32 `SPC4.tlu.trl0.take_iae & `SPC4.tlu.trl0.trap[0]
9401`define INT_PROC_ERR_32 `SPC4.tlu.trl0.take_ipe & `SPC4.tlu.trl0.trap[0]
9402`define HW_CORR_ERR_32 `SPC4.tlu.trl0.take_eer & `SPC4.tlu.trl0.trap[0]
9403`define INST_ACC_MMU_ERR_32 `SPC4.tlu.trl0.take_ime & `SPC4.tlu.trl0.trap[0]
9404`define DATA_ACC_MMU_ERR_32 `SPC4.tlu.trl0.take_dme & `SPC4.tlu.trl0.trap[0]
9405
9406`define LSU_LD_VALID_B `PROBES4.lsu_ld_valid
9407`define LSU_TID_DEC_B_32 `PROBES4.lsu_tid_dec_b[0]
9408`define ASI_LD_32 `SPC4.lsu.lmd.lmq0_pkt[60] & (`SPC4.lsu.lmd.lmq0_pkt[49:48] == 2'b0)
9409`define ASI_32 `SPC4.lsu.lmd.lmq0_pkt[47:40]
9410`define ASI_ADDR_32 `SPC4.lsu.lmd.lmq0_pkt[39:0]
9411`define ASI_LD_DATA_32 `SPC4.lsu_exu_ld_data_b[63:0]
9412`define ASI_LD_COMP_32 tb_top.nas_top.c4.t0.complete_fw2
9413
9414//SPU specific - only one SPU per core
9415`define SPU_MA_BUSY_4 `SPC4.spu.spu_pmu_ma_busy[3]
9416`define SPU_MA_TID_4 `SPC4.spu.spu_pmu_ma_busy[2:0]
9417
9418////////////////////////////////////////////////////////////////////////////////
9419//Capture the status register data from rtl. For disrupting traps,
9420//rtl can modify the contents of the status register before the
9421//trap is taken and intp message is sent to Riesling.
9422//For precise traps, once the status register is updated rtl can't
9423//change the register again before jumping to the trap handler.
9424//So, for deferred and disrupting traps, inform Riesling when the
9425//register is modified while for precise traps wait until Fw2 before
9426//telling Riesling.
9427
9428//TLU asserts the flush and input signals in W stage. I latch them at the
9429//+ve edge of FX4.
9430
9431always @(negedge (`SPC4.l2clk & ready))
9432begin // {
9433 if (`DESR_asi_rd_32)
9434 desr_asi_rd <= 1'b1;
9435 if (desr_asi_rd)
9436 begin
9437 if (desr_wr)
9438 desr_pend_wr <= 1'b1;
9439 if (`ASI_LD_COMP_32[2])
9440 desr_asi_rd <= 1'b0;
9441 end
9442
9443 update_dsfsr_w <= (`DSFSR_NEW_IN_32 != 4'b0) && ~`ASI_WR_DSFSR_32;
9444 update_isfsr_w <= (`ISFSR_NEW_IN_32 != 3'b0) && ~`ASI_WR_ISFSR_32;
9445 desr_wr <= (`RAS_WRITE_DESR_1st_32 || `RAS_WRITE_DESR_2nd_32);
9446 update_dfesr_w <= `RAS_WRITE_FESR_32;
9447 take_err_trap_fx4 <= `ST_ERR_32 | `SW_REC_ERR_32 | `DATA_ACC_ERR_32
9448 | `INST_ACC_ERR_32 | `INT_PROC_ERR_32
9449 | `HW_CORR_ERR_32 | `INST_ACC_MMU_ERR_32
9450 | `DATA_ACC_MMU_ERR_32 ;
9451
9452
9453 if (`ST_ERR_32) int_num_fx4 <= 8'h07;
9454 if (`SW_REC_ERR_32) int_num_fx4 <= 8'h40;
9455 if (`DATA_ACC_ERR_32) int_num_fx4 <= 8'h32;
9456 if (`INST_ACC_ERR_32) int_num_fx4 <= 8'h0A;
9457 if (`INT_PROC_ERR_32) int_num_fx4 <= 8'h29;
9458 if (`HW_CORR_ERR_32) int_num_fx4 <= 8'h63;
9459 if (`INST_ACC_MMU_ERR_32) int_num_fx4 <= 8'h71;
9460 if (`DATA_ACC_MMU_ERR_32) int_num_fx4 <= 8'h72;
9461
9462 update_dsfsr_fx4 <= update_dsfsr_w;
9463 update_dsfsr_fx5 <= update_dsfsr_fx4;
9464 update_dsfsr_fb <= update_dsfsr_fx5;
9465 update_dsfsr_fw <= update_dsfsr_fb;
9466 update_dsfsr_fw1 <= update_dsfsr_fw;
9467 update_dsfsr_fw2 <= update_dsfsr_fw1;
9468
9469 update_isfsr_fx4 <= update_isfsr_w;
9470 update_isfsr_fx5 <= update_isfsr_fx4;
9471 update_isfsr_fb <= update_isfsr_fx5;
9472 update_isfsr_fw <= update_isfsr_fb;
9473 update_isfsr_fw1 <= update_isfsr_fw;
9474 update_isfsr_fw2 <= update_isfsr_fw1;
9475
9476 take_err_trap_fx5 <= take_err_trap_fx4;
9477 take_err_trap_fb <= take_err_trap_fx5;
9478 take_err_trap_fw <= take_err_trap_fb;
9479 take_err_trap_fw1 <= take_err_trap_fw;
9480 take_err_trap_fw2 <= take_err_trap_fw1;
9481
9482 int_num_fx5 <= int_num_fx4;
9483 int_num_fb <= int_num_fx5;
9484 int_num_fw <= int_num_fb;
9485 int_num_fw1 <= int_num_fw;
9486 int_num_fw2 <= int_num_fw1;
9487
9488 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
9489 begin // {
9490 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
9491 begin //{
9492 desr_pend_wr <= 1'b0;
9493 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_32[63:56], 45'b0, `DESR_32[10:0]});
9494 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_32[63:56], 45'b0, `DESR_32[10:0]});
9495 end //}
9496 //if (update_dfesr_w)
9497 if (`ST_ERR_32)
9498 begin //{
9499 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_32[61:55], 55'b0});
9500 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_32[61:55], 55'b0});
9501 end //}
9502 if (update_dsfsr_fw2)
9503 begin //{
9504 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
9505 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_32[3:0]});
9506 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_32[47:0]});
9507
9508 end //}
9509 if (update_isfsr_fw2)
9510 begin //{
9511 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
9512 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_32[2:0]});
9513 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_32[47:0]});
9514
9515 end //}
9516 if (take_err_trap_fw2)
9517 begin //{
9518 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
9519 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
9520 end // }
9521 end // }
9522
9523end //}
9524
9525//removing the addr check as the LSU doesn't flag an invalid_asi_exception
9526//if the addr of diagnostic accesses is not in the valid range. The inst.
9527//still executes. LSU expects that HP won't use addresses in invalid range.
9528
9529always @(negedge (`SPC4.l2clk & ready))
9530begin // {
9531 sync_asi = 1'b0;
9532 ld_data_w <= `ASI_LD_DATA_32;
9533
9534 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_32)
9535 chk_if_asi_ld <= 1'b1;
9536 else
9537 chk_if_asi_ld <= 1'b0;
9538
9539 if (chk_if_asi_ld & `ASI_LD_32)
9540 begin
9541 case (`ASI_32)
9542 8'h66: //ASI_IC_INSTR
9543 begin
9544 //if ((`ASI_ADDR_32 >= 0) & (`ASI_ADDR_32 <= 40'h7ff8))
9545 sync_asi = 1'b1;
9546 end
9547 8'h67: //ASI_IC_TAG
9548 begin
9549 //if ((`ASI_ADDR_32 >= 0) & (`ASI_ADDR_32 <= 40'h7fe0))
9550 sync_asi = 1'b1;
9551 end
9552 8'h46: //ASI_DC_DATA
9553 begin
9554 sync_asi = 1'b1;
9555 end
9556 8'h47: //ASI_DC_TAG
9557 begin
9558 //if ((`ASI_ADDR_32 >= 0) & (`ASI_ADDR_32 <= 40'h7ff0))
9559 sync_asi = 1'b1;
9560 end
9561 8'h48://IRF ECC
9562 begin
9563 //if ((`ASI_ADDR_32 >= 0) & (`ASI_ADDR_32 <= 40'hF8))
9564 sync_asi = 1'b1;
9565 end
9566 8'h49://FRF ECC
9567 begin
9568 //if ((`ASI_ADDR_32 >= 0) & (`ASI_ADDR_32 <= 40'hF8))
9569 sync_asi = 1'b1;
9570 end
9571 8'h4A://STB access, stb ptr can be read also
9572 begin
9573 //if ((`ASI_ADDR_32 >= 0) & (`ASI_ADDR_32 <= 40'h100))
9574 sync_asi = 1'b1;
9575 end
9576 8'h5A://Tick compare reg
9577 begin
9578 //if ((`ASI_ADDR_32 >= 0) & (`ASI_ADDR_32 <= 40'h38))
9579 sync_asi = 1'b1;
9580 end
9581 8'h5B://TSA
9582 begin
9583 //if ((`ASI_ADDR_32 >= 0) & (`ASI_ADDR_32 <= 40'h38))
9584 sync_asi = 1'b1;
9585 end
9586 8'h51://MRA
9587 begin
9588 //if ((`ASI_ADDR_32 >= 0) & (`ASI_ADDR_32 <= 40'h38))
9589 sync_asi = 1'b1;
9590 end
9591 8'h59://scratchpad ecc data read
9592 begin
9593 //if ((`ASI_ADDR_32 >= 0) & (`ASI_ADDR_32 <= 40'h38))
9594 //syncup the ecc data only. For ecc bit 6 is 0.
9595 if (~`SPC4.lsu.lmd.lmq0_pkt[6])
9596 sync_asi = 1'b1;
9597 end
9598 8'h40://cwqcsr,ma_sync access
9599 begin
9600 if ((`ASI_ADDR_32 == 40'h20) || (`ASI_ADDR_32 == 40'h30)
9601 || (`ASI_ADDR_32 == 40'h80)
9602 || ((`ASI_ADDR_32 == 40'ha0) & (`SPU_MA_BUSY_4 == 0) & (`SPU_MA_TID_4 == 0))
9603 )
9604 sync_asi = 1'b1;
9605 end
9606 8'h4C://CLESR, CLFESR access
9607 begin
9608 if ((`ASI_ADDR_32 == 40'h20) || (`ASI_ADDR_32 == 40'h28))
9609 sync_asi = 1'b1;
9610 end
9611 endcase
9612 end
9613
9614 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
9615 begin
9616 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_32, `ASI_ADDR_32, ld_data_w);
9617 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_32, {24'b0, `ASI_ADDR_32}, ld_data_w[63:0]);
9618 end
9619end //}
9620`endif
9621endmodule
9622
9623
9624
9625module err_c4t1 ();
9626`ifndef GATESIM
9627
9628`include "defines.vh"
9629
9630wire [2:0] mycid;
9631wire [2:0] mytid;
9632wire [5:0] mytnum;
9633
9634integer junk;
9635reg ready;
9636reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
9637reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
9638
9639reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
9640reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
9641
9642reg update_dfesr_w;
9643
9644reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
9645reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
9646
9647reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
9648reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
9649
9650reg sync_asi;
9651reg chk_if_asi_ld;
9652reg [63:0] ld_data_w;
9653
9654reg desr_asi_rd, desr_wr, desr_pend_wr;
9655
9656assign mycid = 4;
9657assign mytid = 1;
9658assign mytnum = 4*8 + 1;
9659
9660initial begin //{
9661 desr_asi_rd = 1'b0;
9662 desr_pend_wr = 1'b0;
9663 ready = 0;
9664 @(posedge `SPC4.l2clk) ;
9665 @(posedge `SPC4.l2clk) ;
9666 ready = `PARGS.err_sync_on;
9667end //}
9668
9669`define DSFSR_NEW_IN_33 `SPC4.tlu.ras.dsfsr_1_new_in
9670`define ISFSR_NEW_IN_33 `SPC4.tlu.ras.isfsr_1_new_in
9671
9672`define DSFSR_33 `SPC4.tlu.ras.dsfsr_1
9673`define ISFSR_33 `SPC4.tlu.ras.isfsr_1
9674`define DSFAR_33 `SPC4.tlu.dfd.dsfar_1
9675
9676`define ASI_WR_DSFSR_33 `SPC4.tlu.ras.asi_wr_dsfsr[1]
9677`define ASI_WR_ISFSR_33 `SPC4.tlu.ras.asi_wr_isfsr[1]
9678
9679`define RAS_WRITE_DESR_1st_33 `SPC4.tlu.dfd.ras_write_desr_1st[1]
9680`define RAS_WRITE_DESR_2nd_33 `SPC4.tlu.dfd.ras_write_desr_2nd[1]
9681`define DESR_asi_rd_33 `SPC4.tlu.ras_rd_desr[1]
9682`define DESR_33 `SPC4.tlu.dfd.desr_1
9683
9684`define RAS_WRITE_FESR_33 `SPC4.tlu.ras.write_fesr[1]
9685`define FESR_33 `SPC4.tlu.dfd.fesr_1
9686
9687`define ST_ERR_33 `SPC4.tlu.trl0.take_ftt & `SPC4.tlu.trl0.trap[1]
9688`define SW_REC_ERR_33 `SPC4.tlu.trl0.take_ade & `SPC4.tlu.trl0.trap[1]
9689`define DATA_ACC_ERR_33 `SPC4.tlu.trl0.take_dae & `SPC4.tlu.trl0.trap[1]
9690`define INST_ACC_ERR_33 `SPC4.tlu.trl0.take_iae & `SPC4.tlu.trl0.trap[1]
9691`define INT_PROC_ERR_33 `SPC4.tlu.trl0.take_ipe & `SPC4.tlu.trl0.trap[1]
9692`define HW_CORR_ERR_33 `SPC4.tlu.trl0.take_eer & `SPC4.tlu.trl0.trap[1]
9693`define INST_ACC_MMU_ERR_33 `SPC4.tlu.trl0.take_ime & `SPC4.tlu.trl0.trap[1]
9694`define DATA_ACC_MMU_ERR_33 `SPC4.tlu.trl0.take_dme & `SPC4.tlu.trl0.trap[1]
9695
9696`define LSU_LD_VALID_B `PROBES4.lsu_ld_valid
9697`define LSU_TID_DEC_B_33 `PROBES4.lsu_tid_dec_b[1]
9698`define ASI_LD_33 `SPC4.lsu.lmd.lmq1_pkt[60] & (`SPC4.lsu.lmd.lmq1_pkt[49:48] == 2'b0)
9699`define ASI_33 `SPC4.lsu.lmd.lmq1_pkt[47:40]
9700`define ASI_ADDR_33 `SPC4.lsu.lmd.lmq1_pkt[39:0]
9701`define ASI_LD_DATA_33 `SPC4.lsu_exu_ld_data_b[63:0]
9702`define ASI_LD_COMP_33 tb_top.nas_top.c4.t1.complete_fw2
9703
9704//SPU specific - only one SPU per core
9705`define SPU_MA_BUSY_4 `SPC4.spu.spu_pmu_ma_busy[3]
9706`define SPU_MA_TID_4 `SPC4.spu.spu_pmu_ma_busy[2:0]
9707
9708////////////////////////////////////////////////////////////////////////////////
9709//Capture the status register data from rtl. For disrupting traps,
9710//rtl can modify the contents of the status register before the
9711//trap is taken and intp message is sent to Riesling.
9712//For precise traps, once the status register is updated rtl can't
9713//change the register again before jumping to the trap handler.
9714//So, for deferred and disrupting traps, inform Riesling when the
9715//register is modified while for precise traps wait until Fw2 before
9716//telling Riesling.
9717
9718//TLU asserts the flush and input signals in W stage. I latch them at the
9719//+ve edge of FX4.
9720
9721always @(negedge (`SPC4.l2clk & ready))
9722begin // {
9723 if (`DESR_asi_rd_33)
9724 desr_asi_rd <= 1'b1;
9725 if (desr_asi_rd)
9726 begin
9727 if (desr_wr)
9728 desr_pend_wr <= 1'b1;
9729 if (`ASI_LD_COMP_33[2])
9730 desr_asi_rd <= 1'b0;
9731 end
9732
9733 update_dsfsr_w <= (`DSFSR_NEW_IN_33 != 4'b0) && ~`ASI_WR_DSFSR_33;
9734 update_isfsr_w <= (`ISFSR_NEW_IN_33 != 3'b0) && ~`ASI_WR_ISFSR_33;
9735 desr_wr <= (`RAS_WRITE_DESR_1st_33 || `RAS_WRITE_DESR_2nd_33);
9736 update_dfesr_w <= `RAS_WRITE_FESR_33;
9737 take_err_trap_fx4 <= `ST_ERR_33 | `SW_REC_ERR_33 | `DATA_ACC_ERR_33
9738 | `INST_ACC_ERR_33 | `INT_PROC_ERR_33
9739 | `HW_CORR_ERR_33 | `INST_ACC_MMU_ERR_33
9740 | `DATA_ACC_MMU_ERR_33 ;
9741
9742
9743 if (`ST_ERR_33) int_num_fx4 <= 8'h07;
9744 if (`SW_REC_ERR_33) int_num_fx4 <= 8'h40;
9745 if (`DATA_ACC_ERR_33) int_num_fx4 <= 8'h32;
9746 if (`INST_ACC_ERR_33) int_num_fx4 <= 8'h0A;
9747 if (`INT_PROC_ERR_33) int_num_fx4 <= 8'h29;
9748 if (`HW_CORR_ERR_33) int_num_fx4 <= 8'h63;
9749 if (`INST_ACC_MMU_ERR_33) int_num_fx4 <= 8'h71;
9750 if (`DATA_ACC_MMU_ERR_33) int_num_fx4 <= 8'h72;
9751
9752 update_dsfsr_fx4 <= update_dsfsr_w;
9753 update_dsfsr_fx5 <= update_dsfsr_fx4;
9754 update_dsfsr_fb <= update_dsfsr_fx5;
9755 update_dsfsr_fw <= update_dsfsr_fb;
9756 update_dsfsr_fw1 <= update_dsfsr_fw;
9757 update_dsfsr_fw2 <= update_dsfsr_fw1;
9758
9759 update_isfsr_fx4 <= update_isfsr_w;
9760 update_isfsr_fx5 <= update_isfsr_fx4;
9761 update_isfsr_fb <= update_isfsr_fx5;
9762 update_isfsr_fw <= update_isfsr_fb;
9763 update_isfsr_fw1 <= update_isfsr_fw;
9764 update_isfsr_fw2 <= update_isfsr_fw1;
9765
9766 take_err_trap_fx5 <= take_err_trap_fx4;
9767 take_err_trap_fb <= take_err_trap_fx5;
9768 take_err_trap_fw <= take_err_trap_fb;
9769 take_err_trap_fw1 <= take_err_trap_fw;
9770 take_err_trap_fw2 <= take_err_trap_fw1;
9771
9772 int_num_fx5 <= int_num_fx4;
9773 int_num_fb <= int_num_fx5;
9774 int_num_fw <= int_num_fb;
9775 int_num_fw1 <= int_num_fw;
9776 int_num_fw2 <= int_num_fw1;
9777
9778 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
9779 begin // {
9780 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
9781 begin //{
9782 desr_pend_wr <= 1'b0;
9783 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_33[63:56], 45'b0, `DESR_33[10:0]});
9784 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_33[63:56], 45'b0, `DESR_33[10:0]});
9785 end //}
9786 //if (update_dfesr_w)
9787 if (`ST_ERR_33)
9788 begin //{
9789 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_33[61:55], 55'b0});
9790 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_33[61:55], 55'b0});
9791 end //}
9792 if (update_dsfsr_fw2)
9793 begin //{
9794 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
9795 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_33[3:0]});
9796 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_33[47:0]});
9797
9798 end //}
9799 if (update_isfsr_fw2)
9800 begin //{
9801 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
9802 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_33[2:0]});
9803 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_33[47:0]});
9804
9805 end //}
9806 if (take_err_trap_fw2)
9807 begin //{
9808 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
9809 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
9810 end // }
9811 end // }
9812
9813end //}
9814
9815//removing the addr check as the LSU doesn't flag an invalid_asi_exception
9816//if the addr of diagnostic accesses is not in the valid range. The inst.
9817//still executes. LSU expects that HP won't use addresses in invalid range.
9818
9819always @(negedge (`SPC4.l2clk & ready))
9820begin // {
9821 sync_asi = 1'b0;
9822 ld_data_w <= `ASI_LD_DATA_33;
9823
9824 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_33)
9825 chk_if_asi_ld <= 1'b1;
9826 else
9827 chk_if_asi_ld <= 1'b0;
9828
9829 if (chk_if_asi_ld & `ASI_LD_33)
9830 begin
9831 case (`ASI_33)
9832 8'h66: //ASI_IC_INSTR
9833 begin
9834 //if ((`ASI_ADDR_33 >= 0) & (`ASI_ADDR_33 <= 40'h7ff8))
9835 sync_asi = 1'b1;
9836 end
9837 8'h67: //ASI_IC_TAG
9838 begin
9839 //if ((`ASI_ADDR_33 >= 0) & (`ASI_ADDR_33 <= 40'h7fe0))
9840 sync_asi = 1'b1;
9841 end
9842 8'h46: //ASI_DC_DATA
9843 begin
9844 sync_asi = 1'b1;
9845 end
9846 8'h47: //ASI_DC_TAG
9847 begin
9848 //if ((`ASI_ADDR_33 >= 0) & (`ASI_ADDR_33 <= 40'h7ff0))
9849 sync_asi = 1'b1;
9850 end
9851 8'h48://IRF ECC
9852 begin
9853 //if ((`ASI_ADDR_33 >= 0) & (`ASI_ADDR_33 <= 40'hF8))
9854 sync_asi = 1'b1;
9855 end
9856 8'h49://FRF ECC
9857 begin
9858 //if ((`ASI_ADDR_33 >= 0) & (`ASI_ADDR_33 <= 40'hF8))
9859 sync_asi = 1'b1;
9860 end
9861 8'h4A://STB access, stb ptr can be read also
9862 begin
9863 //if ((`ASI_ADDR_33 >= 0) & (`ASI_ADDR_33 <= 40'h100))
9864 sync_asi = 1'b1;
9865 end
9866 8'h5A://Tick compare reg
9867 begin
9868 //if ((`ASI_ADDR_33 >= 0) & (`ASI_ADDR_33 <= 40'h38))
9869 sync_asi = 1'b1;
9870 end
9871 8'h5B://TSA
9872 begin
9873 //if ((`ASI_ADDR_33 >= 0) & (`ASI_ADDR_33 <= 40'h38))
9874 sync_asi = 1'b1;
9875 end
9876 8'h51://MRA
9877 begin
9878 //if ((`ASI_ADDR_33 >= 0) & (`ASI_ADDR_33 <= 40'h38))
9879 sync_asi = 1'b1;
9880 end
9881 8'h59://scratchpad ecc data read
9882 begin
9883 //if ((`ASI_ADDR_33 >= 0) & (`ASI_ADDR_33 <= 40'h38))
9884 //syncup the ecc data only. For ecc bit 6 is 0.
9885 if (~`SPC4.lsu.lmd.lmq1_pkt[6])
9886 sync_asi = 1'b1;
9887 end
9888 8'h40://cwqcsr,ma_sync access
9889 begin
9890 if ((`ASI_ADDR_33 == 40'h20) || (`ASI_ADDR_33 == 40'h30)
9891 || (`ASI_ADDR_33 == 40'h80)
9892 || ((`ASI_ADDR_33 == 40'ha0) & (`SPU_MA_BUSY_4 == 0) & (`SPU_MA_TID_4 == 1))
9893 )
9894 sync_asi = 1'b1;
9895 end
9896 8'h4C://CLESR, CLFESR access
9897 begin
9898 if ((`ASI_ADDR_33 == 40'h20) || (`ASI_ADDR_33 == 40'h28))
9899 sync_asi = 1'b1;
9900 end
9901 endcase
9902 end
9903
9904 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
9905 begin
9906 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_33, `ASI_ADDR_33, ld_data_w);
9907 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_33, {24'b0, `ASI_ADDR_33}, ld_data_w[63:0]);
9908 end
9909end //}
9910`endif
9911endmodule
9912
9913
9914
9915module err_c4t2 ();
9916`ifndef GATESIM
9917
9918`include "defines.vh"
9919
9920wire [2:0] mycid;
9921wire [2:0] mytid;
9922wire [5:0] mytnum;
9923
9924integer junk;
9925reg ready;
9926reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
9927reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
9928
9929reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
9930reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
9931
9932reg update_dfesr_w;
9933
9934reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
9935reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
9936
9937reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
9938reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
9939
9940reg sync_asi;
9941reg chk_if_asi_ld;
9942reg [63:0] ld_data_w;
9943
9944reg desr_asi_rd, desr_wr, desr_pend_wr;
9945
9946assign mycid = 4;
9947assign mytid = 2;
9948assign mytnum = 4*8 + 2;
9949
9950initial begin //{
9951 desr_asi_rd = 1'b0;
9952 desr_pend_wr = 1'b0;
9953 ready = 0;
9954 @(posedge `SPC4.l2clk) ;
9955 @(posedge `SPC4.l2clk) ;
9956 ready = `PARGS.err_sync_on;
9957end //}
9958
9959`define DSFSR_NEW_IN_34 `SPC4.tlu.ras.dsfsr_2_new_in
9960`define ISFSR_NEW_IN_34 `SPC4.tlu.ras.isfsr_2_new_in
9961
9962`define DSFSR_34 `SPC4.tlu.ras.dsfsr_2
9963`define ISFSR_34 `SPC4.tlu.ras.isfsr_2
9964`define DSFAR_34 `SPC4.tlu.dfd.dsfar_2
9965
9966`define ASI_WR_DSFSR_34 `SPC4.tlu.ras.asi_wr_dsfsr[2]
9967`define ASI_WR_ISFSR_34 `SPC4.tlu.ras.asi_wr_isfsr[2]
9968
9969`define RAS_WRITE_DESR_1st_34 `SPC4.tlu.dfd.ras_write_desr_1st[2]
9970`define RAS_WRITE_DESR_2nd_34 `SPC4.tlu.dfd.ras_write_desr_2nd[2]
9971`define DESR_asi_rd_34 `SPC4.tlu.ras_rd_desr[2]
9972`define DESR_34 `SPC4.tlu.dfd.desr_2
9973
9974`define RAS_WRITE_FESR_34 `SPC4.tlu.ras.write_fesr[2]
9975`define FESR_34 `SPC4.tlu.dfd.fesr_2
9976
9977`define ST_ERR_34 `SPC4.tlu.trl0.take_ftt & `SPC4.tlu.trl0.trap[2]
9978`define SW_REC_ERR_34 `SPC4.tlu.trl0.take_ade & `SPC4.tlu.trl0.trap[2]
9979`define DATA_ACC_ERR_34 `SPC4.tlu.trl0.take_dae & `SPC4.tlu.trl0.trap[2]
9980`define INST_ACC_ERR_34 `SPC4.tlu.trl0.take_iae & `SPC4.tlu.trl0.trap[2]
9981`define INT_PROC_ERR_34 `SPC4.tlu.trl0.take_ipe & `SPC4.tlu.trl0.trap[2]
9982`define HW_CORR_ERR_34 `SPC4.tlu.trl0.take_eer & `SPC4.tlu.trl0.trap[2]
9983`define INST_ACC_MMU_ERR_34 `SPC4.tlu.trl0.take_ime & `SPC4.tlu.trl0.trap[2]
9984`define DATA_ACC_MMU_ERR_34 `SPC4.tlu.trl0.take_dme & `SPC4.tlu.trl0.trap[2]
9985
9986`define LSU_LD_VALID_B `PROBES4.lsu_ld_valid
9987`define LSU_TID_DEC_B_34 `PROBES4.lsu_tid_dec_b[2]
9988`define ASI_LD_34 `SPC4.lsu.lmd.lmq2_pkt[60] & (`SPC4.lsu.lmd.lmq2_pkt[49:48] == 2'b0)
9989`define ASI_34 `SPC4.lsu.lmd.lmq2_pkt[47:40]
9990`define ASI_ADDR_34 `SPC4.lsu.lmd.lmq2_pkt[39:0]
9991`define ASI_LD_DATA_34 `SPC4.lsu_exu_ld_data_b[63:0]
9992`define ASI_LD_COMP_34 tb_top.nas_top.c4.t2.complete_fw2
9993
9994//SPU specific - only one SPU per core
9995`define SPU_MA_BUSY_4 `SPC4.spu.spu_pmu_ma_busy[3]
9996`define SPU_MA_TID_4 `SPC4.spu.spu_pmu_ma_busy[2:0]
9997
9998////////////////////////////////////////////////////////////////////////////////
9999//Capture the status register data from rtl. For disrupting traps,
10000//rtl can modify the contents of the status register before the
10001//trap is taken and intp message is sent to Riesling.
10002//For precise traps, once the status register is updated rtl can't
10003//change the register again before jumping to the trap handler.
10004//So, for deferred and disrupting traps, inform Riesling when the
10005//register is modified while for precise traps wait until Fw2 before
10006//telling Riesling.
10007
10008//TLU asserts the flush and input signals in W stage. I latch them at the
10009//+ve edge of FX4.
10010
10011always @(negedge (`SPC4.l2clk & ready))
10012begin // {
10013 if (`DESR_asi_rd_34)
10014 desr_asi_rd <= 1'b1;
10015 if (desr_asi_rd)
10016 begin
10017 if (desr_wr)
10018 desr_pend_wr <= 1'b1;
10019 if (`ASI_LD_COMP_34[2])
10020 desr_asi_rd <= 1'b0;
10021 end
10022
10023 update_dsfsr_w <= (`DSFSR_NEW_IN_34 != 4'b0) && ~`ASI_WR_DSFSR_34;
10024 update_isfsr_w <= (`ISFSR_NEW_IN_34 != 3'b0) && ~`ASI_WR_ISFSR_34;
10025 desr_wr <= (`RAS_WRITE_DESR_1st_34 || `RAS_WRITE_DESR_2nd_34);
10026 update_dfesr_w <= `RAS_WRITE_FESR_34;
10027 take_err_trap_fx4 <= `ST_ERR_34 | `SW_REC_ERR_34 | `DATA_ACC_ERR_34
10028 | `INST_ACC_ERR_34 | `INT_PROC_ERR_34
10029 | `HW_CORR_ERR_34 | `INST_ACC_MMU_ERR_34
10030 | `DATA_ACC_MMU_ERR_34 ;
10031
10032
10033 if (`ST_ERR_34) int_num_fx4 <= 8'h07;
10034 if (`SW_REC_ERR_34) int_num_fx4 <= 8'h40;
10035 if (`DATA_ACC_ERR_34) int_num_fx4 <= 8'h32;
10036 if (`INST_ACC_ERR_34) int_num_fx4 <= 8'h0A;
10037 if (`INT_PROC_ERR_34) int_num_fx4 <= 8'h29;
10038 if (`HW_CORR_ERR_34) int_num_fx4 <= 8'h63;
10039 if (`INST_ACC_MMU_ERR_34) int_num_fx4 <= 8'h71;
10040 if (`DATA_ACC_MMU_ERR_34) int_num_fx4 <= 8'h72;
10041
10042 update_dsfsr_fx4 <= update_dsfsr_w;
10043 update_dsfsr_fx5 <= update_dsfsr_fx4;
10044 update_dsfsr_fb <= update_dsfsr_fx5;
10045 update_dsfsr_fw <= update_dsfsr_fb;
10046 update_dsfsr_fw1 <= update_dsfsr_fw;
10047 update_dsfsr_fw2 <= update_dsfsr_fw1;
10048
10049 update_isfsr_fx4 <= update_isfsr_w;
10050 update_isfsr_fx5 <= update_isfsr_fx4;
10051 update_isfsr_fb <= update_isfsr_fx5;
10052 update_isfsr_fw <= update_isfsr_fb;
10053 update_isfsr_fw1 <= update_isfsr_fw;
10054 update_isfsr_fw2 <= update_isfsr_fw1;
10055
10056 take_err_trap_fx5 <= take_err_trap_fx4;
10057 take_err_trap_fb <= take_err_trap_fx5;
10058 take_err_trap_fw <= take_err_trap_fb;
10059 take_err_trap_fw1 <= take_err_trap_fw;
10060 take_err_trap_fw2 <= take_err_trap_fw1;
10061
10062 int_num_fx5 <= int_num_fx4;
10063 int_num_fb <= int_num_fx5;
10064 int_num_fw <= int_num_fb;
10065 int_num_fw1 <= int_num_fw;
10066 int_num_fw2 <= int_num_fw1;
10067
10068 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
10069 begin // {
10070 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
10071 begin //{
10072 desr_pend_wr <= 1'b0;
10073 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_34[63:56], 45'b0, `DESR_34[10:0]});
10074 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_34[63:56], 45'b0, `DESR_34[10:0]});
10075 end //}
10076 //if (update_dfesr_w)
10077 if (`ST_ERR_34)
10078 begin //{
10079 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_34[61:55], 55'b0});
10080 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_34[61:55], 55'b0});
10081 end //}
10082 if (update_dsfsr_fw2)
10083 begin //{
10084 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
10085 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_34[3:0]});
10086 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_34[47:0]});
10087
10088 end //}
10089 if (update_isfsr_fw2)
10090 begin //{
10091 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
10092 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_34[2:0]});
10093 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_34[47:0]});
10094
10095 end //}
10096 if (take_err_trap_fw2)
10097 begin //{
10098 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
10099 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
10100 end // }
10101 end // }
10102
10103end //}
10104
10105//removing the addr check as the LSU doesn't flag an invalid_asi_exception
10106//if the addr of diagnostic accesses is not in the valid range. The inst.
10107//still executes. LSU expects that HP won't use addresses in invalid range.
10108
10109always @(negedge (`SPC4.l2clk & ready))
10110begin // {
10111 sync_asi = 1'b0;
10112 ld_data_w <= `ASI_LD_DATA_34;
10113
10114 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_34)
10115 chk_if_asi_ld <= 1'b1;
10116 else
10117 chk_if_asi_ld <= 1'b0;
10118
10119 if (chk_if_asi_ld & `ASI_LD_34)
10120 begin
10121 case (`ASI_34)
10122 8'h66: //ASI_IC_INSTR
10123 begin
10124 //if ((`ASI_ADDR_34 >= 0) & (`ASI_ADDR_34 <= 40'h7ff8))
10125 sync_asi = 1'b1;
10126 end
10127 8'h67: //ASI_IC_TAG
10128 begin
10129 //if ((`ASI_ADDR_34 >= 0) & (`ASI_ADDR_34 <= 40'h7fe0))
10130 sync_asi = 1'b1;
10131 end
10132 8'h46: //ASI_DC_DATA
10133 begin
10134 sync_asi = 1'b1;
10135 end
10136 8'h47: //ASI_DC_TAG
10137 begin
10138 //if ((`ASI_ADDR_34 >= 0) & (`ASI_ADDR_34 <= 40'h7ff0))
10139 sync_asi = 1'b1;
10140 end
10141 8'h48://IRF ECC
10142 begin
10143 //if ((`ASI_ADDR_34 >= 0) & (`ASI_ADDR_34 <= 40'hF8))
10144 sync_asi = 1'b1;
10145 end
10146 8'h49://FRF ECC
10147 begin
10148 //if ((`ASI_ADDR_34 >= 0) & (`ASI_ADDR_34 <= 40'hF8))
10149 sync_asi = 1'b1;
10150 end
10151 8'h4A://STB access, stb ptr can be read also
10152 begin
10153 //if ((`ASI_ADDR_34 >= 0) & (`ASI_ADDR_34 <= 40'h100))
10154 sync_asi = 1'b1;
10155 end
10156 8'h5A://Tick compare reg
10157 begin
10158 //if ((`ASI_ADDR_34 >= 0) & (`ASI_ADDR_34 <= 40'h38))
10159 sync_asi = 1'b1;
10160 end
10161 8'h5B://TSA
10162 begin
10163 //if ((`ASI_ADDR_34 >= 0) & (`ASI_ADDR_34 <= 40'h38))
10164 sync_asi = 1'b1;
10165 end
10166 8'h51://MRA
10167 begin
10168 //if ((`ASI_ADDR_34 >= 0) & (`ASI_ADDR_34 <= 40'h38))
10169 sync_asi = 1'b1;
10170 end
10171 8'h59://scratchpad ecc data read
10172 begin
10173 //if ((`ASI_ADDR_34 >= 0) & (`ASI_ADDR_34 <= 40'h38))
10174 //syncup the ecc data only. For ecc bit 6 is 0.
10175 if (~`SPC4.lsu.lmd.lmq2_pkt[6])
10176 sync_asi = 1'b1;
10177 end
10178 8'h40://cwqcsr,ma_sync access
10179 begin
10180 if ((`ASI_ADDR_34 == 40'h20) || (`ASI_ADDR_34 == 40'h30)
10181 || (`ASI_ADDR_34 == 40'h80)
10182 || ((`ASI_ADDR_34 == 40'ha0) & (`SPU_MA_BUSY_4 == 0) & (`SPU_MA_TID_4 == 2))
10183 )
10184 sync_asi = 1'b1;
10185 end
10186 8'h4C://CLESR, CLFESR access
10187 begin
10188 if ((`ASI_ADDR_34 == 40'h20) || (`ASI_ADDR_34 == 40'h28))
10189 sync_asi = 1'b1;
10190 end
10191 endcase
10192 end
10193
10194 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
10195 begin
10196 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_34, `ASI_ADDR_34, ld_data_w);
10197 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_34, {24'b0, `ASI_ADDR_34}, ld_data_w[63:0]);
10198 end
10199end //}
10200`endif
10201endmodule
10202
10203
10204
10205module err_c4t3 ();
10206`ifndef GATESIM
10207
10208`include "defines.vh"
10209
10210wire [2:0] mycid;
10211wire [2:0] mytid;
10212wire [5:0] mytnum;
10213
10214integer junk;
10215reg ready;
10216reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
10217reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
10218
10219reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
10220reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
10221
10222reg update_dfesr_w;
10223
10224reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
10225reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
10226
10227reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
10228reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
10229
10230reg sync_asi;
10231reg chk_if_asi_ld;
10232reg [63:0] ld_data_w;
10233
10234reg desr_asi_rd, desr_wr, desr_pend_wr;
10235
10236assign mycid = 4;
10237assign mytid = 3;
10238assign mytnum = 4*8 + 3;
10239
10240initial begin //{
10241 desr_asi_rd = 1'b0;
10242 desr_pend_wr = 1'b0;
10243 ready = 0;
10244 @(posedge `SPC4.l2clk) ;
10245 @(posedge `SPC4.l2clk) ;
10246 ready = `PARGS.err_sync_on;
10247end //}
10248
10249`define DSFSR_NEW_IN_35 `SPC4.tlu.ras.dsfsr_3_new_in
10250`define ISFSR_NEW_IN_35 `SPC4.tlu.ras.isfsr_3_new_in
10251
10252`define DSFSR_35 `SPC4.tlu.ras.dsfsr_3
10253`define ISFSR_35 `SPC4.tlu.ras.isfsr_3
10254`define DSFAR_35 `SPC4.tlu.dfd.dsfar_3
10255
10256`define ASI_WR_DSFSR_35 `SPC4.tlu.ras.asi_wr_dsfsr[3]
10257`define ASI_WR_ISFSR_35 `SPC4.tlu.ras.asi_wr_isfsr[3]
10258
10259`define RAS_WRITE_DESR_1st_35 `SPC4.tlu.dfd.ras_write_desr_1st[3]
10260`define RAS_WRITE_DESR_2nd_35 `SPC4.tlu.dfd.ras_write_desr_2nd[3]
10261`define DESR_asi_rd_35 `SPC4.tlu.ras_rd_desr[3]
10262`define DESR_35 `SPC4.tlu.dfd.desr_3
10263
10264`define RAS_WRITE_FESR_35 `SPC4.tlu.ras.write_fesr[3]
10265`define FESR_35 `SPC4.tlu.dfd.fesr_3
10266
10267`define ST_ERR_35 `SPC4.tlu.trl0.take_ftt & `SPC4.tlu.trl0.trap[3]
10268`define SW_REC_ERR_35 `SPC4.tlu.trl0.take_ade & `SPC4.tlu.trl0.trap[3]
10269`define DATA_ACC_ERR_35 `SPC4.tlu.trl0.take_dae & `SPC4.tlu.trl0.trap[3]
10270`define INST_ACC_ERR_35 `SPC4.tlu.trl0.take_iae & `SPC4.tlu.trl0.trap[3]
10271`define INT_PROC_ERR_35 `SPC4.tlu.trl0.take_ipe & `SPC4.tlu.trl0.trap[3]
10272`define HW_CORR_ERR_35 `SPC4.tlu.trl0.take_eer & `SPC4.tlu.trl0.trap[3]
10273`define INST_ACC_MMU_ERR_35 `SPC4.tlu.trl0.take_ime & `SPC4.tlu.trl0.trap[3]
10274`define DATA_ACC_MMU_ERR_35 `SPC4.tlu.trl0.take_dme & `SPC4.tlu.trl0.trap[3]
10275
10276`define LSU_LD_VALID_B `PROBES4.lsu_ld_valid
10277`define LSU_TID_DEC_B_35 `PROBES4.lsu_tid_dec_b[3]
10278`define ASI_LD_35 `SPC4.lsu.lmd.lmq3_pkt[60] & (`SPC4.lsu.lmd.lmq3_pkt[49:48] == 2'b0)
10279`define ASI_35 `SPC4.lsu.lmd.lmq3_pkt[47:40]
10280`define ASI_ADDR_35 `SPC4.lsu.lmd.lmq3_pkt[39:0]
10281`define ASI_LD_DATA_35 `SPC4.lsu_exu_ld_data_b[63:0]
10282`define ASI_LD_COMP_35 tb_top.nas_top.c4.t3.complete_fw2
10283
10284//SPU specific - only one SPU per core
10285`define SPU_MA_BUSY_4 `SPC4.spu.spu_pmu_ma_busy[3]
10286`define SPU_MA_TID_4 `SPC4.spu.spu_pmu_ma_busy[2:0]
10287
10288////////////////////////////////////////////////////////////////////////////////
10289//Capture the status register data from rtl. For disrupting traps,
10290//rtl can modify the contents of the status register before the
10291//trap is taken and intp message is sent to Riesling.
10292//For precise traps, once the status register is updated rtl can't
10293//change the register again before jumping to the trap handler.
10294//So, for deferred and disrupting traps, inform Riesling when the
10295//register is modified while for precise traps wait until Fw2 before
10296//telling Riesling.
10297
10298//TLU asserts the flush and input signals in W stage. I latch them at the
10299//+ve edge of FX4.
10300
10301always @(negedge (`SPC4.l2clk & ready))
10302begin // {
10303 if (`DESR_asi_rd_35)
10304 desr_asi_rd <= 1'b1;
10305 if (desr_asi_rd)
10306 begin
10307 if (desr_wr)
10308 desr_pend_wr <= 1'b1;
10309 if (`ASI_LD_COMP_35[2])
10310 desr_asi_rd <= 1'b0;
10311 end
10312
10313 update_dsfsr_w <= (`DSFSR_NEW_IN_35 != 4'b0) && ~`ASI_WR_DSFSR_35;
10314 update_isfsr_w <= (`ISFSR_NEW_IN_35 != 3'b0) && ~`ASI_WR_ISFSR_35;
10315 desr_wr <= (`RAS_WRITE_DESR_1st_35 || `RAS_WRITE_DESR_2nd_35);
10316 update_dfesr_w <= `RAS_WRITE_FESR_35;
10317 take_err_trap_fx4 <= `ST_ERR_35 | `SW_REC_ERR_35 | `DATA_ACC_ERR_35
10318 | `INST_ACC_ERR_35 | `INT_PROC_ERR_35
10319 | `HW_CORR_ERR_35 | `INST_ACC_MMU_ERR_35
10320 | `DATA_ACC_MMU_ERR_35 ;
10321
10322
10323 if (`ST_ERR_35) int_num_fx4 <= 8'h07;
10324 if (`SW_REC_ERR_35) int_num_fx4 <= 8'h40;
10325 if (`DATA_ACC_ERR_35) int_num_fx4 <= 8'h32;
10326 if (`INST_ACC_ERR_35) int_num_fx4 <= 8'h0A;
10327 if (`INT_PROC_ERR_35) int_num_fx4 <= 8'h29;
10328 if (`HW_CORR_ERR_35) int_num_fx4 <= 8'h63;
10329 if (`INST_ACC_MMU_ERR_35) int_num_fx4 <= 8'h71;
10330 if (`DATA_ACC_MMU_ERR_35) int_num_fx4 <= 8'h72;
10331
10332 update_dsfsr_fx4 <= update_dsfsr_w;
10333 update_dsfsr_fx5 <= update_dsfsr_fx4;
10334 update_dsfsr_fb <= update_dsfsr_fx5;
10335 update_dsfsr_fw <= update_dsfsr_fb;
10336 update_dsfsr_fw1 <= update_dsfsr_fw;
10337 update_dsfsr_fw2 <= update_dsfsr_fw1;
10338
10339 update_isfsr_fx4 <= update_isfsr_w;
10340 update_isfsr_fx5 <= update_isfsr_fx4;
10341 update_isfsr_fb <= update_isfsr_fx5;
10342 update_isfsr_fw <= update_isfsr_fb;
10343 update_isfsr_fw1 <= update_isfsr_fw;
10344 update_isfsr_fw2 <= update_isfsr_fw1;
10345
10346 take_err_trap_fx5 <= take_err_trap_fx4;
10347 take_err_trap_fb <= take_err_trap_fx5;
10348 take_err_trap_fw <= take_err_trap_fb;
10349 take_err_trap_fw1 <= take_err_trap_fw;
10350 take_err_trap_fw2 <= take_err_trap_fw1;
10351
10352 int_num_fx5 <= int_num_fx4;
10353 int_num_fb <= int_num_fx5;
10354 int_num_fw <= int_num_fb;
10355 int_num_fw1 <= int_num_fw;
10356 int_num_fw2 <= int_num_fw1;
10357
10358 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
10359 begin // {
10360 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
10361 begin //{
10362 desr_pend_wr <= 1'b0;
10363 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_35[63:56], 45'b0, `DESR_35[10:0]});
10364 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_35[63:56], 45'b0, `DESR_35[10:0]});
10365 end //}
10366 //if (update_dfesr_w)
10367 if (`ST_ERR_35)
10368 begin //{
10369 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_35[61:55], 55'b0});
10370 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_35[61:55], 55'b0});
10371 end //}
10372 if (update_dsfsr_fw2)
10373 begin //{
10374 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
10375 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_35[3:0]});
10376 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_35[47:0]});
10377
10378 end //}
10379 if (update_isfsr_fw2)
10380 begin //{
10381 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
10382 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_35[2:0]});
10383 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_35[47:0]});
10384
10385 end //}
10386 if (take_err_trap_fw2)
10387 begin //{
10388 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
10389 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
10390 end // }
10391 end // }
10392
10393end //}
10394
10395//removing the addr check as the LSU doesn't flag an invalid_asi_exception
10396//if the addr of diagnostic accesses is not in the valid range. The inst.
10397//still executes. LSU expects that HP won't use addresses in invalid range.
10398
10399always @(negedge (`SPC4.l2clk & ready))
10400begin // {
10401 sync_asi = 1'b0;
10402 ld_data_w <= `ASI_LD_DATA_35;
10403
10404 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_35)
10405 chk_if_asi_ld <= 1'b1;
10406 else
10407 chk_if_asi_ld <= 1'b0;
10408
10409 if (chk_if_asi_ld & `ASI_LD_35)
10410 begin
10411 case (`ASI_35)
10412 8'h66: //ASI_IC_INSTR
10413 begin
10414 //if ((`ASI_ADDR_35 >= 0) & (`ASI_ADDR_35 <= 40'h7ff8))
10415 sync_asi = 1'b1;
10416 end
10417 8'h67: //ASI_IC_TAG
10418 begin
10419 //if ((`ASI_ADDR_35 >= 0) & (`ASI_ADDR_35 <= 40'h7fe0))
10420 sync_asi = 1'b1;
10421 end
10422 8'h46: //ASI_DC_DATA
10423 begin
10424 sync_asi = 1'b1;
10425 end
10426 8'h47: //ASI_DC_TAG
10427 begin
10428 //if ((`ASI_ADDR_35 >= 0) & (`ASI_ADDR_35 <= 40'h7ff0))
10429 sync_asi = 1'b1;
10430 end
10431 8'h48://IRF ECC
10432 begin
10433 //if ((`ASI_ADDR_35 >= 0) & (`ASI_ADDR_35 <= 40'hF8))
10434 sync_asi = 1'b1;
10435 end
10436 8'h49://FRF ECC
10437 begin
10438 //if ((`ASI_ADDR_35 >= 0) & (`ASI_ADDR_35 <= 40'hF8))
10439 sync_asi = 1'b1;
10440 end
10441 8'h4A://STB access, stb ptr can be read also
10442 begin
10443 //if ((`ASI_ADDR_35 >= 0) & (`ASI_ADDR_35 <= 40'h100))
10444 sync_asi = 1'b1;
10445 end
10446 8'h5A://Tick compare reg
10447 begin
10448 //if ((`ASI_ADDR_35 >= 0) & (`ASI_ADDR_35 <= 40'h38))
10449 sync_asi = 1'b1;
10450 end
10451 8'h5B://TSA
10452 begin
10453 //if ((`ASI_ADDR_35 >= 0) & (`ASI_ADDR_35 <= 40'h38))
10454 sync_asi = 1'b1;
10455 end
10456 8'h51://MRA
10457 begin
10458 //if ((`ASI_ADDR_35 >= 0) & (`ASI_ADDR_35 <= 40'h38))
10459 sync_asi = 1'b1;
10460 end
10461 8'h59://scratchpad ecc data read
10462 begin
10463 //if ((`ASI_ADDR_35 >= 0) & (`ASI_ADDR_35 <= 40'h38))
10464 //syncup the ecc data only. For ecc bit 6 is 0.
10465 if (~`SPC4.lsu.lmd.lmq3_pkt[6])
10466 sync_asi = 1'b1;
10467 end
10468 8'h40://cwqcsr,ma_sync access
10469 begin
10470 if ((`ASI_ADDR_35 == 40'h20) || (`ASI_ADDR_35 == 40'h30)
10471 || (`ASI_ADDR_35 == 40'h80)
10472 || ((`ASI_ADDR_35 == 40'ha0) & (`SPU_MA_BUSY_4 == 0) & (`SPU_MA_TID_4 == 3))
10473 )
10474 sync_asi = 1'b1;
10475 end
10476 8'h4C://CLESR, CLFESR access
10477 begin
10478 if ((`ASI_ADDR_35 == 40'h20) || (`ASI_ADDR_35 == 40'h28))
10479 sync_asi = 1'b1;
10480 end
10481 endcase
10482 end
10483
10484 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
10485 begin
10486 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_35, `ASI_ADDR_35, ld_data_w);
10487 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_35, {24'b0, `ASI_ADDR_35}, ld_data_w[63:0]);
10488 end
10489end //}
10490`endif
10491endmodule
10492
10493
10494
10495module err_c4t4 ();
10496`ifndef GATESIM
10497
10498`include "defines.vh"
10499
10500wire [2:0] mycid;
10501wire [2:0] mytid;
10502wire [5:0] mytnum;
10503
10504integer junk;
10505reg ready;
10506reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
10507reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
10508
10509reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
10510reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
10511
10512reg update_dfesr_w;
10513
10514reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
10515reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
10516
10517reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
10518reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
10519
10520reg sync_asi;
10521reg chk_if_asi_ld;
10522reg [63:0] ld_data_w;
10523
10524reg desr_asi_rd, desr_wr, desr_pend_wr;
10525
10526assign mycid = 4;
10527assign mytid = 4;
10528assign mytnum = 4*8 + 4;
10529
10530initial begin //{
10531 desr_asi_rd = 1'b0;
10532 desr_pend_wr = 1'b0;
10533 ready = 0;
10534 @(posedge `SPC4.l2clk) ;
10535 @(posedge `SPC4.l2clk) ;
10536 ready = `PARGS.err_sync_on;
10537end //}
10538
10539`define DSFSR_NEW_IN_36 `SPC4.tlu.ras.dsfsr_4_new_in
10540`define ISFSR_NEW_IN_36 `SPC4.tlu.ras.isfsr_4_new_in
10541
10542`define DSFSR_36 `SPC4.tlu.ras.dsfsr_4
10543`define ISFSR_36 `SPC4.tlu.ras.isfsr_4
10544`define DSFAR_36 `SPC4.tlu.dfd.dsfar_4
10545
10546`define ASI_WR_DSFSR_36 `SPC4.tlu.ras.asi_wr_dsfsr[4]
10547`define ASI_WR_ISFSR_36 `SPC4.tlu.ras.asi_wr_isfsr[4]
10548
10549`define RAS_WRITE_DESR_1st_36 `SPC4.tlu.dfd.ras_write_desr_1st[4]
10550`define RAS_WRITE_DESR_2nd_36 `SPC4.tlu.dfd.ras_write_desr_2nd[4]
10551`define DESR_asi_rd_36 `SPC4.tlu.ras_rd_desr[4]
10552`define DESR_36 `SPC4.tlu.dfd.desr_4
10553
10554`define RAS_WRITE_FESR_36 `SPC4.tlu.ras.write_fesr[4]
10555`define FESR_36 `SPC4.tlu.dfd.fesr_4
10556
10557`define ST_ERR_36 `SPC4.tlu.trl1.take_ftt & `SPC4.tlu.trl1.trap[0]
10558`define SW_REC_ERR_36 `SPC4.tlu.trl1.take_ade & `SPC4.tlu.trl1.trap[0]
10559`define DATA_ACC_ERR_36 `SPC4.tlu.trl1.take_dae & `SPC4.tlu.trl1.trap[0]
10560`define INST_ACC_ERR_36 `SPC4.tlu.trl1.take_iae & `SPC4.tlu.trl1.trap[0]
10561`define INT_PROC_ERR_36 `SPC4.tlu.trl1.take_ipe & `SPC4.tlu.trl1.trap[0]
10562`define HW_CORR_ERR_36 `SPC4.tlu.trl1.take_eer & `SPC4.tlu.trl1.trap[0]
10563`define INST_ACC_MMU_ERR_36 `SPC4.tlu.trl1.take_ime & `SPC4.tlu.trl1.trap[0]
10564`define DATA_ACC_MMU_ERR_36 `SPC4.tlu.trl1.take_dme & `SPC4.tlu.trl1.trap[0]
10565
10566`define LSU_LD_VALID_B `PROBES4.lsu_ld_valid
10567`define LSU_TID_DEC_B_36 `PROBES4.lsu_tid_dec_b[4]
10568`define ASI_LD_36 `SPC4.lsu.lmd.lmq4_pkt[60] & (`SPC4.lsu.lmd.lmq4_pkt[49:48] == 2'b0)
10569`define ASI_36 `SPC4.lsu.lmd.lmq4_pkt[47:40]
10570`define ASI_ADDR_36 `SPC4.lsu.lmd.lmq4_pkt[39:0]
10571`define ASI_LD_DATA_36 `SPC4.lsu_exu_ld_data_b[63:0]
10572`define ASI_LD_COMP_36 tb_top.nas_top.c4.t4.complete_fw2
10573
10574//SPU specific - only one SPU per core
10575`define SPU_MA_BUSY_4 `SPC4.spu.spu_pmu_ma_busy[3]
10576`define SPU_MA_TID_4 `SPC4.spu.spu_pmu_ma_busy[2:0]
10577
10578////////////////////////////////////////////////////////////////////////////////
10579//Capture the status register data from rtl. For disrupting traps,
10580//rtl can modify the contents of the status register before the
10581//trap is taken and intp message is sent to Riesling.
10582//For precise traps, once the status register is updated rtl can't
10583//change the register again before jumping to the trap handler.
10584//So, for deferred and disrupting traps, inform Riesling when the
10585//register is modified while for precise traps wait until Fw2 before
10586//telling Riesling.
10587
10588//TLU asserts the flush and input signals in W stage. I latch them at the
10589//+ve edge of FX4.
10590
10591always @(negedge (`SPC4.l2clk & ready))
10592begin // {
10593 if (`DESR_asi_rd_36)
10594 desr_asi_rd <= 1'b1;
10595 if (desr_asi_rd)
10596 begin
10597 if (desr_wr)
10598 desr_pend_wr <= 1'b1;
10599 if (`ASI_LD_COMP_36[2])
10600 desr_asi_rd <= 1'b0;
10601 end
10602
10603 update_dsfsr_w <= (`DSFSR_NEW_IN_36 != 4'b0) && ~`ASI_WR_DSFSR_36;
10604 update_isfsr_w <= (`ISFSR_NEW_IN_36 != 3'b0) && ~`ASI_WR_ISFSR_36;
10605 desr_wr <= (`RAS_WRITE_DESR_1st_36 || `RAS_WRITE_DESR_2nd_36);
10606 update_dfesr_w <= `RAS_WRITE_FESR_36;
10607 take_err_trap_fx4 <= `ST_ERR_36 | `SW_REC_ERR_36 | `DATA_ACC_ERR_36
10608 | `INST_ACC_ERR_36 | `INT_PROC_ERR_36
10609 | `HW_CORR_ERR_36 | `INST_ACC_MMU_ERR_36
10610 | `DATA_ACC_MMU_ERR_36 ;
10611
10612
10613 if (`ST_ERR_36) int_num_fx4 <= 8'h07;
10614 if (`SW_REC_ERR_36) int_num_fx4 <= 8'h40;
10615 if (`DATA_ACC_ERR_36) int_num_fx4 <= 8'h32;
10616 if (`INST_ACC_ERR_36) int_num_fx4 <= 8'h0A;
10617 if (`INT_PROC_ERR_36) int_num_fx4 <= 8'h29;
10618 if (`HW_CORR_ERR_36) int_num_fx4 <= 8'h63;
10619 if (`INST_ACC_MMU_ERR_36) int_num_fx4 <= 8'h71;
10620 if (`DATA_ACC_MMU_ERR_36) int_num_fx4 <= 8'h72;
10621
10622 update_dsfsr_fx4 <= update_dsfsr_w;
10623 update_dsfsr_fx5 <= update_dsfsr_fx4;
10624 update_dsfsr_fb <= update_dsfsr_fx5;
10625 update_dsfsr_fw <= update_dsfsr_fb;
10626 update_dsfsr_fw1 <= update_dsfsr_fw;
10627 update_dsfsr_fw2 <= update_dsfsr_fw1;
10628
10629 update_isfsr_fx4 <= update_isfsr_w;
10630 update_isfsr_fx5 <= update_isfsr_fx4;
10631 update_isfsr_fb <= update_isfsr_fx5;
10632 update_isfsr_fw <= update_isfsr_fb;
10633 update_isfsr_fw1 <= update_isfsr_fw;
10634 update_isfsr_fw2 <= update_isfsr_fw1;
10635
10636 take_err_trap_fx5 <= take_err_trap_fx4;
10637 take_err_trap_fb <= take_err_trap_fx5;
10638 take_err_trap_fw <= take_err_trap_fb;
10639 take_err_trap_fw1 <= take_err_trap_fw;
10640 take_err_trap_fw2 <= take_err_trap_fw1;
10641
10642 int_num_fx5 <= int_num_fx4;
10643 int_num_fb <= int_num_fx5;
10644 int_num_fw <= int_num_fb;
10645 int_num_fw1 <= int_num_fw;
10646 int_num_fw2 <= int_num_fw1;
10647
10648 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
10649 begin // {
10650 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
10651 begin //{
10652 desr_pend_wr <= 1'b0;
10653 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_36[63:56], 45'b0, `DESR_36[10:0]});
10654 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_36[63:56], 45'b0, `DESR_36[10:0]});
10655 end //}
10656 //if (update_dfesr_w)
10657 if (`ST_ERR_36)
10658 begin //{
10659 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_36[61:55], 55'b0});
10660 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_36[61:55], 55'b0});
10661 end //}
10662 if (update_dsfsr_fw2)
10663 begin //{
10664 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
10665 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_36[3:0]});
10666 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_36[47:0]});
10667
10668 end //}
10669 if (update_isfsr_fw2)
10670 begin //{
10671 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
10672 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_36[2:0]});
10673 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_36[47:0]});
10674
10675 end //}
10676 if (take_err_trap_fw2)
10677 begin //{
10678 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
10679 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
10680 end // }
10681 end // }
10682
10683end //}
10684
10685//removing the addr check as the LSU doesn't flag an invalid_asi_exception
10686//if the addr of diagnostic accesses is not in the valid range. The inst.
10687//still executes. LSU expects that HP won't use addresses in invalid range.
10688
10689always @(negedge (`SPC4.l2clk & ready))
10690begin // {
10691 sync_asi = 1'b0;
10692 ld_data_w <= `ASI_LD_DATA_36;
10693
10694 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_36)
10695 chk_if_asi_ld <= 1'b1;
10696 else
10697 chk_if_asi_ld <= 1'b0;
10698
10699 if (chk_if_asi_ld & `ASI_LD_36)
10700 begin
10701 case (`ASI_36)
10702 8'h66: //ASI_IC_INSTR
10703 begin
10704 //if ((`ASI_ADDR_36 >= 0) & (`ASI_ADDR_36 <= 40'h7ff8))
10705 sync_asi = 1'b1;
10706 end
10707 8'h67: //ASI_IC_TAG
10708 begin
10709 //if ((`ASI_ADDR_36 >= 0) & (`ASI_ADDR_36 <= 40'h7fe0))
10710 sync_asi = 1'b1;
10711 end
10712 8'h46: //ASI_DC_DATA
10713 begin
10714 sync_asi = 1'b1;
10715 end
10716 8'h47: //ASI_DC_TAG
10717 begin
10718 //if ((`ASI_ADDR_36 >= 0) & (`ASI_ADDR_36 <= 40'h7ff0))
10719 sync_asi = 1'b1;
10720 end
10721 8'h48://IRF ECC
10722 begin
10723 //if ((`ASI_ADDR_36 >= 0) & (`ASI_ADDR_36 <= 40'hF8))
10724 sync_asi = 1'b1;
10725 end
10726 8'h49://FRF ECC
10727 begin
10728 //if ((`ASI_ADDR_36 >= 0) & (`ASI_ADDR_36 <= 40'hF8))
10729 sync_asi = 1'b1;
10730 end
10731 8'h4A://STB access, stb ptr can be read also
10732 begin
10733 //if ((`ASI_ADDR_36 >= 0) & (`ASI_ADDR_36 <= 40'h100))
10734 sync_asi = 1'b1;
10735 end
10736 8'h5A://Tick compare reg
10737 begin
10738 //if ((`ASI_ADDR_36 >= 0) & (`ASI_ADDR_36 <= 40'h38))
10739 sync_asi = 1'b1;
10740 end
10741 8'h5B://TSA
10742 begin
10743 //if ((`ASI_ADDR_36 >= 0) & (`ASI_ADDR_36 <= 40'h38))
10744 sync_asi = 1'b1;
10745 end
10746 8'h51://MRA
10747 begin
10748 //if ((`ASI_ADDR_36 >= 0) & (`ASI_ADDR_36 <= 40'h38))
10749 sync_asi = 1'b1;
10750 end
10751 8'h59://scratchpad ecc data read
10752 begin
10753 //if ((`ASI_ADDR_36 >= 0) & (`ASI_ADDR_36 <= 40'h38))
10754 //syncup the ecc data only. For ecc bit 6 is 0.
10755 if (~`SPC4.lsu.lmd.lmq4_pkt[6])
10756 sync_asi = 1'b1;
10757 end
10758 8'h40://cwqcsr,ma_sync access
10759 begin
10760 if ((`ASI_ADDR_36 == 40'h20) || (`ASI_ADDR_36 == 40'h30)
10761 || (`ASI_ADDR_36 == 40'h80)
10762 || ((`ASI_ADDR_36 == 40'ha0) & (`SPU_MA_BUSY_4 == 0) & (`SPU_MA_TID_4 == 4))
10763 )
10764 sync_asi = 1'b1;
10765 end
10766 8'h4C://CLESR, CLFESR access
10767 begin
10768 if ((`ASI_ADDR_36 == 40'h20) || (`ASI_ADDR_36 == 40'h28))
10769 sync_asi = 1'b1;
10770 end
10771 endcase
10772 end
10773
10774 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
10775 begin
10776 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_36, `ASI_ADDR_36, ld_data_w);
10777 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_36, {24'b0, `ASI_ADDR_36}, ld_data_w[63:0]);
10778 end
10779end //}
10780`endif
10781endmodule
10782
10783
10784
10785module err_c4t5 ();
10786`ifndef GATESIM
10787
10788`include "defines.vh"
10789
10790wire [2:0] mycid;
10791wire [2:0] mytid;
10792wire [5:0] mytnum;
10793
10794integer junk;
10795reg ready;
10796reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
10797reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
10798
10799reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
10800reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
10801
10802reg update_dfesr_w;
10803
10804reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
10805reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
10806
10807reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
10808reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
10809
10810reg sync_asi;
10811reg chk_if_asi_ld;
10812reg [63:0] ld_data_w;
10813
10814reg desr_asi_rd, desr_wr, desr_pend_wr;
10815
10816assign mycid = 4;
10817assign mytid = 5;
10818assign mytnum = 4*8 + 5;
10819
10820initial begin //{
10821 desr_asi_rd = 1'b0;
10822 desr_pend_wr = 1'b0;
10823 ready = 0;
10824 @(posedge `SPC4.l2clk) ;
10825 @(posedge `SPC4.l2clk) ;
10826 ready = `PARGS.err_sync_on;
10827end //}
10828
10829`define DSFSR_NEW_IN_37 `SPC4.tlu.ras.dsfsr_5_new_in
10830`define ISFSR_NEW_IN_37 `SPC4.tlu.ras.isfsr_5_new_in
10831
10832`define DSFSR_37 `SPC4.tlu.ras.dsfsr_5
10833`define ISFSR_37 `SPC4.tlu.ras.isfsr_5
10834`define DSFAR_37 `SPC4.tlu.dfd.dsfar_5
10835
10836`define ASI_WR_DSFSR_37 `SPC4.tlu.ras.asi_wr_dsfsr[5]
10837`define ASI_WR_ISFSR_37 `SPC4.tlu.ras.asi_wr_isfsr[5]
10838
10839`define RAS_WRITE_DESR_1st_37 `SPC4.tlu.dfd.ras_write_desr_1st[5]
10840`define RAS_WRITE_DESR_2nd_37 `SPC4.tlu.dfd.ras_write_desr_2nd[5]
10841`define DESR_asi_rd_37 `SPC4.tlu.ras_rd_desr[5]
10842`define DESR_37 `SPC4.tlu.dfd.desr_5
10843
10844`define RAS_WRITE_FESR_37 `SPC4.tlu.ras.write_fesr[5]
10845`define FESR_37 `SPC4.tlu.dfd.fesr_5
10846
10847`define ST_ERR_37 `SPC4.tlu.trl1.take_ftt & `SPC4.tlu.trl1.trap[1]
10848`define SW_REC_ERR_37 `SPC4.tlu.trl1.take_ade & `SPC4.tlu.trl1.trap[1]
10849`define DATA_ACC_ERR_37 `SPC4.tlu.trl1.take_dae & `SPC4.tlu.trl1.trap[1]
10850`define INST_ACC_ERR_37 `SPC4.tlu.trl1.take_iae & `SPC4.tlu.trl1.trap[1]
10851`define INT_PROC_ERR_37 `SPC4.tlu.trl1.take_ipe & `SPC4.tlu.trl1.trap[1]
10852`define HW_CORR_ERR_37 `SPC4.tlu.trl1.take_eer & `SPC4.tlu.trl1.trap[1]
10853`define INST_ACC_MMU_ERR_37 `SPC4.tlu.trl1.take_ime & `SPC4.tlu.trl1.trap[1]
10854`define DATA_ACC_MMU_ERR_37 `SPC4.tlu.trl1.take_dme & `SPC4.tlu.trl1.trap[1]
10855
10856`define LSU_LD_VALID_B `PROBES4.lsu_ld_valid
10857`define LSU_TID_DEC_B_37 `PROBES4.lsu_tid_dec_b[5]
10858`define ASI_LD_37 `SPC4.lsu.lmd.lmq5_pkt[60] & (`SPC4.lsu.lmd.lmq5_pkt[49:48] == 2'b0)
10859`define ASI_37 `SPC4.lsu.lmd.lmq5_pkt[47:40]
10860`define ASI_ADDR_37 `SPC4.lsu.lmd.lmq5_pkt[39:0]
10861`define ASI_LD_DATA_37 `SPC4.lsu_exu_ld_data_b[63:0]
10862`define ASI_LD_COMP_37 tb_top.nas_top.c4.t5.complete_fw2
10863
10864//SPU specific - only one SPU per core
10865`define SPU_MA_BUSY_4 `SPC4.spu.spu_pmu_ma_busy[3]
10866`define SPU_MA_TID_4 `SPC4.spu.spu_pmu_ma_busy[2:0]
10867
10868////////////////////////////////////////////////////////////////////////////////
10869//Capture the status register data from rtl. For disrupting traps,
10870//rtl can modify the contents of the status register before the
10871//trap is taken and intp message is sent to Riesling.
10872//For precise traps, once the status register is updated rtl can't
10873//change the register again before jumping to the trap handler.
10874//So, for deferred and disrupting traps, inform Riesling when the
10875//register is modified while for precise traps wait until Fw2 before
10876//telling Riesling.
10877
10878//TLU asserts the flush and input signals in W stage. I latch them at the
10879//+ve edge of FX4.
10880
10881always @(negedge (`SPC4.l2clk & ready))
10882begin // {
10883 if (`DESR_asi_rd_37)
10884 desr_asi_rd <= 1'b1;
10885 if (desr_asi_rd)
10886 begin
10887 if (desr_wr)
10888 desr_pend_wr <= 1'b1;
10889 if (`ASI_LD_COMP_37[2])
10890 desr_asi_rd <= 1'b0;
10891 end
10892
10893 update_dsfsr_w <= (`DSFSR_NEW_IN_37 != 4'b0) && ~`ASI_WR_DSFSR_37;
10894 update_isfsr_w <= (`ISFSR_NEW_IN_37 != 3'b0) && ~`ASI_WR_ISFSR_37;
10895 desr_wr <= (`RAS_WRITE_DESR_1st_37 || `RAS_WRITE_DESR_2nd_37);
10896 update_dfesr_w <= `RAS_WRITE_FESR_37;
10897 take_err_trap_fx4 <= `ST_ERR_37 | `SW_REC_ERR_37 | `DATA_ACC_ERR_37
10898 | `INST_ACC_ERR_37 | `INT_PROC_ERR_37
10899 | `HW_CORR_ERR_37 | `INST_ACC_MMU_ERR_37
10900 | `DATA_ACC_MMU_ERR_37 ;
10901
10902
10903 if (`ST_ERR_37) int_num_fx4 <= 8'h07;
10904 if (`SW_REC_ERR_37) int_num_fx4 <= 8'h40;
10905 if (`DATA_ACC_ERR_37) int_num_fx4 <= 8'h32;
10906 if (`INST_ACC_ERR_37) int_num_fx4 <= 8'h0A;
10907 if (`INT_PROC_ERR_37) int_num_fx4 <= 8'h29;
10908 if (`HW_CORR_ERR_37) int_num_fx4 <= 8'h63;
10909 if (`INST_ACC_MMU_ERR_37) int_num_fx4 <= 8'h71;
10910 if (`DATA_ACC_MMU_ERR_37) int_num_fx4 <= 8'h72;
10911
10912 update_dsfsr_fx4 <= update_dsfsr_w;
10913 update_dsfsr_fx5 <= update_dsfsr_fx4;
10914 update_dsfsr_fb <= update_dsfsr_fx5;
10915 update_dsfsr_fw <= update_dsfsr_fb;
10916 update_dsfsr_fw1 <= update_dsfsr_fw;
10917 update_dsfsr_fw2 <= update_dsfsr_fw1;
10918
10919 update_isfsr_fx4 <= update_isfsr_w;
10920 update_isfsr_fx5 <= update_isfsr_fx4;
10921 update_isfsr_fb <= update_isfsr_fx5;
10922 update_isfsr_fw <= update_isfsr_fb;
10923 update_isfsr_fw1 <= update_isfsr_fw;
10924 update_isfsr_fw2 <= update_isfsr_fw1;
10925
10926 take_err_trap_fx5 <= take_err_trap_fx4;
10927 take_err_trap_fb <= take_err_trap_fx5;
10928 take_err_trap_fw <= take_err_trap_fb;
10929 take_err_trap_fw1 <= take_err_trap_fw;
10930 take_err_trap_fw2 <= take_err_trap_fw1;
10931
10932 int_num_fx5 <= int_num_fx4;
10933 int_num_fb <= int_num_fx5;
10934 int_num_fw <= int_num_fb;
10935 int_num_fw1 <= int_num_fw;
10936 int_num_fw2 <= int_num_fw1;
10937
10938 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
10939 begin // {
10940 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
10941 begin //{
10942 desr_pend_wr <= 1'b0;
10943 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_37[63:56], 45'b0, `DESR_37[10:0]});
10944 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_37[63:56], 45'b0, `DESR_37[10:0]});
10945 end //}
10946 //if (update_dfesr_w)
10947 if (`ST_ERR_37)
10948 begin //{
10949 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_37[61:55], 55'b0});
10950 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_37[61:55], 55'b0});
10951 end //}
10952 if (update_dsfsr_fw2)
10953 begin //{
10954 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
10955 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_37[3:0]});
10956 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_37[47:0]});
10957
10958 end //}
10959 if (update_isfsr_fw2)
10960 begin //{
10961 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
10962 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_37[2:0]});
10963 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_37[47:0]});
10964
10965 end //}
10966 if (take_err_trap_fw2)
10967 begin //{
10968 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
10969 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
10970 end // }
10971 end // }
10972
10973end //}
10974
10975//removing the addr check as the LSU doesn't flag an invalid_asi_exception
10976//if the addr of diagnostic accesses is not in the valid range. The inst.
10977//still executes. LSU expects that HP won't use addresses in invalid range.
10978
10979always @(negedge (`SPC4.l2clk & ready))
10980begin // {
10981 sync_asi = 1'b0;
10982 ld_data_w <= `ASI_LD_DATA_37;
10983
10984 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_37)
10985 chk_if_asi_ld <= 1'b1;
10986 else
10987 chk_if_asi_ld <= 1'b0;
10988
10989 if (chk_if_asi_ld & `ASI_LD_37)
10990 begin
10991 case (`ASI_37)
10992 8'h66: //ASI_IC_INSTR
10993 begin
10994 //if ((`ASI_ADDR_37 >= 0) & (`ASI_ADDR_37 <= 40'h7ff8))
10995 sync_asi = 1'b1;
10996 end
10997 8'h67: //ASI_IC_TAG
10998 begin
10999 //if ((`ASI_ADDR_37 >= 0) & (`ASI_ADDR_37 <= 40'h7fe0))
11000 sync_asi = 1'b1;
11001 end
11002 8'h46: //ASI_DC_DATA
11003 begin
11004 sync_asi = 1'b1;
11005 end
11006 8'h47: //ASI_DC_TAG
11007 begin
11008 //if ((`ASI_ADDR_37 >= 0) & (`ASI_ADDR_37 <= 40'h7ff0))
11009 sync_asi = 1'b1;
11010 end
11011 8'h48://IRF ECC
11012 begin
11013 //if ((`ASI_ADDR_37 >= 0) & (`ASI_ADDR_37 <= 40'hF8))
11014 sync_asi = 1'b1;
11015 end
11016 8'h49://FRF ECC
11017 begin
11018 //if ((`ASI_ADDR_37 >= 0) & (`ASI_ADDR_37 <= 40'hF8))
11019 sync_asi = 1'b1;
11020 end
11021 8'h4A://STB access, stb ptr can be read also
11022 begin
11023 //if ((`ASI_ADDR_37 >= 0) & (`ASI_ADDR_37 <= 40'h100))
11024 sync_asi = 1'b1;
11025 end
11026 8'h5A://Tick compare reg
11027 begin
11028 //if ((`ASI_ADDR_37 >= 0) & (`ASI_ADDR_37 <= 40'h38))
11029 sync_asi = 1'b1;
11030 end
11031 8'h5B://TSA
11032 begin
11033 //if ((`ASI_ADDR_37 >= 0) & (`ASI_ADDR_37 <= 40'h38))
11034 sync_asi = 1'b1;
11035 end
11036 8'h51://MRA
11037 begin
11038 //if ((`ASI_ADDR_37 >= 0) & (`ASI_ADDR_37 <= 40'h38))
11039 sync_asi = 1'b1;
11040 end
11041 8'h59://scratchpad ecc data read
11042 begin
11043 //if ((`ASI_ADDR_37 >= 0) & (`ASI_ADDR_37 <= 40'h38))
11044 //syncup the ecc data only. For ecc bit 6 is 0.
11045 if (~`SPC4.lsu.lmd.lmq5_pkt[6])
11046 sync_asi = 1'b1;
11047 end
11048 8'h40://cwqcsr,ma_sync access
11049 begin
11050 if ((`ASI_ADDR_37 == 40'h20) || (`ASI_ADDR_37 == 40'h30)
11051 || (`ASI_ADDR_37 == 40'h80)
11052 || ((`ASI_ADDR_37 == 40'ha0) & (`SPU_MA_BUSY_4 == 0) & (`SPU_MA_TID_4 == 5))
11053 )
11054 sync_asi = 1'b1;
11055 end
11056 8'h4C://CLESR, CLFESR access
11057 begin
11058 if ((`ASI_ADDR_37 == 40'h20) || (`ASI_ADDR_37 == 40'h28))
11059 sync_asi = 1'b1;
11060 end
11061 endcase
11062 end
11063
11064 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
11065 begin
11066 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_37, `ASI_ADDR_37, ld_data_w);
11067 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_37, {24'b0, `ASI_ADDR_37}, ld_data_w[63:0]);
11068 end
11069end //}
11070`endif
11071endmodule
11072
11073
11074
11075module err_c4t6 ();
11076`ifndef GATESIM
11077
11078`include "defines.vh"
11079
11080wire [2:0] mycid;
11081wire [2:0] mytid;
11082wire [5:0] mytnum;
11083
11084integer junk;
11085reg ready;
11086reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
11087reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
11088
11089reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
11090reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
11091
11092reg update_dfesr_w;
11093
11094reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
11095reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
11096
11097reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
11098reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
11099
11100reg sync_asi;
11101reg chk_if_asi_ld;
11102reg [63:0] ld_data_w;
11103
11104reg desr_asi_rd, desr_wr, desr_pend_wr;
11105
11106assign mycid = 4;
11107assign mytid = 6;
11108assign mytnum = 4*8 + 6;
11109
11110initial begin //{
11111 desr_asi_rd = 1'b0;
11112 desr_pend_wr = 1'b0;
11113 ready = 0;
11114 @(posedge `SPC4.l2clk) ;
11115 @(posedge `SPC4.l2clk) ;
11116 ready = `PARGS.err_sync_on;
11117end //}
11118
11119`define DSFSR_NEW_IN_38 `SPC4.tlu.ras.dsfsr_6_new_in
11120`define ISFSR_NEW_IN_38 `SPC4.tlu.ras.isfsr_6_new_in
11121
11122`define DSFSR_38 `SPC4.tlu.ras.dsfsr_6
11123`define ISFSR_38 `SPC4.tlu.ras.isfsr_6
11124`define DSFAR_38 `SPC4.tlu.dfd.dsfar_6
11125
11126`define ASI_WR_DSFSR_38 `SPC4.tlu.ras.asi_wr_dsfsr[6]
11127`define ASI_WR_ISFSR_38 `SPC4.tlu.ras.asi_wr_isfsr[6]
11128
11129`define RAS_WRITE_DESR_1st_38 `SPC4.tlu.dfd.ras_write_desr_1st[6]
11130`define RAS_WRITE_DESR_2nd_38 `SPC4.tlu.dfd.ras_write_desr_2nd[6]
11131`define DESR_asi_rd_38 `SPC4.tlu.ras_rd_desr[6]
11132`define DESR_38 `SPC4.tlu.dfd.desr_6
11133
11134`define RAS_WRITE_FESR_38 `SPC4.tlu.ras.write_fesr[6]
11135`define FESR_38 `SPC4.tlu.dfd.fesr_6
11136
11137`define ST_ERR_38 `SPC4.tlu.trl1.take_ftt & `SPC4.tlu.trl1.trap[2]
11138`define SW_REC_ERR_38 `SPC4.tlu.trl1.take_ade & `SPC4.tlu.trl1.trap[2]
11139`define DATA_ACC_ERR_38 `SPC4.tlu.trl1.take_dae & `SPC4.tlu.trl1.trap[2]
11140`define INST_ACC_ERR_38 `SPC4.tlu.trl1.take_iae & `SPC4.tlu.trl1.trap[2]
11141`define INT_PROC_ERR_38 `SPC4.tlu.trl1.take_ipe & `SPC4.tlu.trl1.trap[2]
11142`define HW_CORR_ERR_38 `SPC4.tlu.trl1.take_eer & `SPC4.tlu.trl1.trap[2]
11143`define INST_ACC_MMU_ERR_38 `SPC4.tlu.trl1.take_ime & `SPC4.tlu.trl1.trap[2]
11144`define DATA_ACC_MMU_ERR_38 `SPC4.tlu.trl1.take_dme & `SPC4.tlu.trl1.trap[2]
11145
11146`define LSU_LD_VALID_B `PROBES4.lsu_ld_valid
11147`define LSU_TID_DEC_B_38 `PROBES4.lsu_tid_dec_b[6]
11148`define ASI_LD_38 `SPC4.lsu.lmd.lmq6_pkt[60] & (`SPC4.lsu.lmd.lmq6_pkt[49:48] == 2'b0)
11149`define ASI_38 `SPC4.lsu.lmd.lmq6_pkt[47:40]
11150`define ASI_ADDR_38 `SPC4.lsu.lmd.lmq6_pkt[39:0]
11151`define ASI_LD_DATA_38 `SPC4.lsu_exu_ld_data_b[63:0]
11152`define ASI_LD_COMP_38 tb_top.nas_top.c4.t6.complete_fw2
11153
11154//SPU specific - only one SPU per core
11155`define SPU_MA_BUSY_4 `SPC4.spu.spu_pmu_ma_busy[3]
11156`define SPU_MA_TID_4 `SPC4.spu.spu_pmu_ma_busy[2:0]
11157
11158////////////////////////////////////////////////////////////////////////////////
11159//Capture the status register data from rtl. For disrupting traps,
11160//rtl can modify the contents of the status register before the
11161//trap is taken and intp message is sent to Riesling.
11162//For precise traps, once the status register is updated rtl can't
11163//change the register again before jumping to the trap handler.
11164//So, for deferred and disrupting traps, inform Riesling when the
11165//register is modified while for precise traps wait until Fw2 before
11166//telling Riesling.
11167
11168//TLU asserts the flush and input signals in W stage. I latch them at the
11169//+ve edge of FX4.
11170
11171always @(negedge (`SPC4.l2clk & ready))
11172begin // {
11173 if (`DESR_asi_rd_38)
11174 desr_asi_rd <= 1'b1;
11175 if (desr_asi_rd)
11176 begin
11177 if (desr_wr)
11178 desr_pend_wr <= 1'b1;
11179 if (`ASI_LD_COMP_38[2])
11180 desr_asi_rd <= 1'b0;
11181 end
11182
11183 update_dsfsr_w <= (`DSFSR_NEW_IN_38 != 4'b0) && ~`ASI_WR_DSFSR_38;
11184 update_isfsr_w <= (`ISFSR_NEW_IN_38 != 3'b0) && ~`ASI_WR_ISFSR_38;
11185 desr_wr <= (`RAS_WRITE_DESR_1st_38 || `RAS_WRITE_DESR_2nd_38);
11186 update_dfesr_w <= `RAS_WRITE_FESR_38;
11187 take_err_trap_fx4 <= `ST_ERR_38 | `SW_REC_ERR_38 | `DATA_ACC_ERR_38
11188 | `INST_ACC_ERR_38 | `INT_PROC_ERR_38
11189 | `HW_CORR_ERR_38 | `INST_ACC_MMU_ERR_38
11190 | `DATA_ACC_MMU_ERR_38 ;
11191
11192
11193 if (`ST_ERR_38) int_num_fx4 <= 8'h07;
11194 if (`SW_REC_ERR_38) int_num_fx4 <= 8'h40;
11195 if (`DATA_ACC_ERR_38) int_num_fx4 <= 8'h32;
11196 if (`INST_ACC_ERR_38) int_num_fx4 <= 8'h0A;
11197 if (`INT_PROC_ERR_38) int_num_fx4 <= 8'h29;
11198 if (`HW_CORR_ERR_38) int_num_fx4 <= 8'h63;
11199 if (`INST_ACC_MMU_ERR_38) int_num_fx4 <= 8'h71;
11200 if (`DATA_ACC_MMU_ERR_38) int_num_fx4 <= 8'h72;
11201
11202 update_dsfsr_fx4 <= update_dsfsr_w;
11203 update_dsfsr_fx5 <= update_dsfsr_fx4;
11204 update_dsfsr_fb <= update_dsfsr_fx5;
11205 update_dsfsr_fw <= update_dsfsr_fb;
11206 update_dsfsr_fw1 <= update_dsfsr_fw;
11207 update_dsfsr_fw2 <= update_dsfsr_fw1;
11208
11209 update_isfsr_fx4 <= update_isfsr_w;
11210 update_isfsr_fx5 <= update_isfsr_fx4;
11211 update_isfsr_fb <= update_isfsr_fx5;
11212 update_isfsr_fw <= update_isfsr_fb;
11213 update_isfsr_fw1 <= update_isfsr_fw;
11214 update_isfsr_fw2 <= update_isfsr_fw1;
11215
11216 take_err_trap_fx5 <= take_err_trap_fx4;
11217 take_err_trap_fb <= take_err_trap_fx5;
11218 take_err_trap_fw <= take_err_trap_fb;
11219 take_err_trap_fw1 <= take_err_trap_fw;
11220 take_err_trap_fw2 <= take_err_trap_fw1;
11221
11222 int_num_fx5 <= int_num_fx4;
11223 int_num_fb <= int_num_fx5;
11224 int_num_fw <= int_num_fb;
11225 int_num_fw1 <= int_num_fw;
11226 int_num_fw2 <= int_num_fw1;
11227
11228 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
11229 begin // {
11230 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
11231 begin //{
11232 desr_pend_wr <= 1'b0;
11233 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_38[63:56], 45'b0, `DESR_38[10:0]});
11234 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_38[63:56], 45'b0, `DESR_38[10:0]});
11235 end //}
11236 //if (update_dfesr_w)
11237 if (`ST_ERR_38)
11238 begin //{
11239 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_38[61:55], 55'b0});
11240 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_38[61:55], 55'b0});
11241 end //}
11242 if (update_dsfsr_fw2)
11243 begin //{
11244 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
11245 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_38[3:0]});
11246 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_38[47:0]});
11247
11248 end //}
11249 if (update_isfsr_fw2)
11250 begin //{
11251 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
11252 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_38[2:0]});
11253 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_38[47:0]});
11254
11255 end //}
11256 if (take_err_trap_fw2)
11257 begin //{
11258 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
11259 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
11260 end // }
11261 end // }
11262
11263end //}
11264
11265//removing the addr check as the LSU doesn't flag an invalid_asi_exception
11266//if the addr of diagnostic accesses is not in the valid range. The inst.
11267//still executes. LSU expects that HP won't use addresses in invalid range.
11268
11269always @(negedge (`SPC4.l2clk & ready))
11270begin // {
11271 sync_asi = 1'b0;
11272 ld_data_w <= `ASI_LD_DATA_38;
11273
11274 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_38)
11275 chk_if_asi_ld <= 1'b1;
11276 else
11277 chk_if_asi_ld <= 1'b0;
11278
11279 if (chk_if_asi_ld & `ASI_LD_38)
11280 begin
11281 case (`ASI_38)
11282 8'h66: //ASI_IC_INSTR
11283 begin
11284 //if ((`ASI_ADDR_38 >= 0) & (`ASI_ADDR_38 <= 40'h7ff8))
11285 sync_asi = 1'b1;
11286 end
11287 8'h67: //ASI_IC_TAG
11288 begin
11289 //if ((`ASI_ADDR_38 >= 0) & (`ASI_ADDR_38 <= 40'h7fe0))
11290 sync_asi = 1'b1;
11291 end
11292 8'h46: //ASI_DC_DATA
11293 begin
11294 sync_asi = 1'b1;
11295 end
11296 8'h47: //ASI_DC_TAG
11297 begin
11298 //if ((`ASI_ADDR_38 >= 0) & (`ASI_ADDR_38 <= 40'h7ff0))
11299 sync_asi = 1'b1;
11300 end
11301 8'h48://IRF ECC
11302 begin
11303 //if ((`ASI_ADDR_38 >= 0) & (`ASI_ADDR_38 <= 40'hF8))
11304 sync_asi = 1'b1;
11305 end
11306 8'h49://FRF ECC
11307 begin
11308 //if ((`ASI_ADDR_38 >= 0) & (`ASI_ADDR_38 <= 40'hF8))
11309 sync_asi = 1'b1;
11310 end
11311 8'h4A://STB access, stb ptr can be read also
11312 begin
11313 //if ((`ASI_ADDR_38 >= 0) & (`ASI_ADDR_38 <= 40'h100))
11314 sync_asi = 1'b1;
11315 end
11316 8'h5A://Tick compare reg
11317 begin
11318 //if ((`ASI_ADDR_38 >= 0) & (`ASI_ADDR_38 <= 40'h38))
11319 sync_asi = 1'b1;
11320 end
11321 8'h5B://TSA
11322 begin
11323 //if ((`ASI_ADDR_38 >= 0) & (`ASI_ADDR_38 <= 40'h38))
11324 sync_asi = 1'b1;
11325 end
11326 8'h51://MRA
11327 begin
11328 //if ((`ASI_ADDR_38 >= 0) & (`ASI_ADDR_38 <= 40'h38))
11329 sync_asi = 1'b1;
11330 end
11331 8'h59://scratchpad ecc data read
11332 begin
11333 //if ((`ASI_ADDR_38 >= 0) & (`ASI_ADDR_38 <= 40'h38))
11334 //syncup the ecc data only. For ecc bit 6 is 0.
11335 if (~`SPC4.lsu.lmd.lmq6_pkt[6])
11336 sync_asi = 1'b1;
11337 end
11338 8'h40://cwqcsr,ma_sync access
11339 begin
11340 if ((`ASI_ADDR_38 == 40'h20) || (`ASI_ADDR_38 == 40'h30)
11341 || (`ASI_ADDR_38 == 40'h80)
11342 || ((`ASI_ADDR_38 == 40'ha0) & (`SPU_MA_BUSY_4 == 0) & (`SPU_MA_TID_4 == 6))
11343 )
11344 sync_asi = 1'b1;
11345 end
11346 8'h4C://CLESR, CLFESR access
11347 begin
11348 if ((`ASI_ADDR_38 == 40'h20) || (`ASI_ADDR_38 == 40'h28))
11349 sync_asi = 1'b1;
11350 end
11351 endcase
11352 end
11353
11354 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
11355 begin
11356 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_38, `ASI_ADDR_38, ld_data_w);
11357 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_38, {24'b0, `ASI_ADDR_38}, ld_data_w[63:0]);
11358 end
11359end //}
11360`endif
11361endmodule
11362
11363
11364
11365module err_c4t7 ();
11366`ifndef GATESIM
11367
11368`include "defines.vh"
11369
11370wire [2:0] mycid;
11371wire [2:0] mytid;
11372wire [5:0] mytnum;
11373
11374integer junk;
11375reg ready;
11376reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
11377reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
11378
11379reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
11380reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
11381
11382reg update_dfesr_w;
11383
11384reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
11385reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
11386
11387reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
11388reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
11389
11390reg sync_asi;
11391reg chk_if_asi_ld;
11392reg [63:0] ld_data_w;
11393
11394reg desr_asi_rd, desr_wr, desr_pend_wr;
11395
11396assign mycid = 4;
11397assign mytid = 7;
11398assign mytnum = 4*8 + 7;
11399
11400initial begin //{
11401 desr_asi_rd = 1'b0;
11402 desr_pend_wr = 1'b0;
11403 ready = 0;
11404 @(posedge `SPC4.l2clk) ;
11405 @(posedge `SPC4.l2clk) ;
11406 ready = `PARGS.err_sync_on;
11407end //}
11408
11409`define DSFSR_NEW_IN_39 `SPC4.tlu.ras.dsfsr_7_new_in
11410`define ISFSR_NEW_IN_39 `SPC4.tlu.ras.isfsr_7_new_in
11411
11412`define DSFSR_39 `SPC4.tlu.ras.dsfsr_7
11413`define ISFSR_39 `SPC4.tlu.ras.isfsr_7
11414`define DSFAR_39 `SPC4.tlu.dfd.dsfar_7
11415
11416`define ASI_WR_DSFSR_39 `SPC4.tlu.ras.asi_wr_dsfsr[7]
11417`define ASI_WR_ISFSR_39 `SPC4.tlu.ras.asi_wr_isfsr[7]
11418
11419`define RAS_WRITE_DESR_1st_39 `SPC4.tlu.dfd.ras_write_desr_1st[7]
11420`define RAS_WRITE_DESR_2nd_39 `SPC4.tlu.dfd.ras_write_desr_2nd[7]
11421`define DESR_asi_rd_39 `SPC4.tlu.ras_rd_desr[7]
11422`define DESR_39 `SPC4.tlu.dfd.desr_7
11423
11424`define RAS_WRITE_FESR_39 `SPC4.tlu.ras.write_fesr[7]
11425`define FESR_39 `SPC4.tlu.dfd.fesr_7
11426
11427`define ST_ERR_39 `SPC4.tlu.trl1.take_ftt & `SPC4.tlu.trl1.trap[3]
11428`define SW_REC_ERR_39 `SPC4.tlu.trl1.take_ade & `SPC4.tlu.trl1.trap[3]
11429`define DATA_ACC_ERR_39 `SPC4.tlu.trl1.take_dae & `SPC4.tlu.trl1.trap[3]
11430`define INST_ACC_ERR_39 `SPC4.tlu.trl1.take_iae & `SPC4.tlu.trl1.trap[3]
11431`define INT_PROC_ERR_39 `SPC4.tlu.trl1.take_ipe & `SPC4.tlu.trl1.trap[3]
11432`define HW_CORR_ERR_39 `SPC4.tlu.trl1.take_eer & `SPC4.tlu.trl1.trap[3]
11433`define INST_ACC_MMU_ERR_39 `SPC4.tlu.trl1.take_ime & `SPC4.tlu.trl1.trap[3]
11434`define DATA_ACC_MMU_ERR_39 `SPC4.tlu.trl1.take_dme & `SPC4.tlu.trl1.trap[3]
11435
11436`define LSU_LD_VALID_B `PROBES4.lsu_ld_valid
11437`define LSU_TID_DEC_B_39 `PROBES4.lsu_tid_dec_b[7]
11438`define ASI_LD_39 `SPC4.lsu.lmd.lmq7_pkt[60] & (`SPC4.lsu.lmd.lmq7_pkt[49:48] == 2'b0)
11439`define ASI_39 `SPC4.lsu.lmd.lmq7_pkt[47:40]
11440`define ASI_ADDR_39 `SPC4.lsu.lmd.lmq7_pkt[39:0]
11441`define ASI_LD_DATA_39 `SPC4.lsu_exu_ld_data_b[63:0]
11442`define ASI_LD_COMP_39 tb_top.nas_top.c4.t7.complete_fw2
11443
11444//SPU specific - only one SPU per core
11445`define SPU_MA_BUSY_4 `SPC4.spu.spu_pmu_ma_busy[3]
11446`define SPU_MA_TID_4 `SPC4.spu.spu_pmu_ma_busy[2:0]
11447
11448////////////////////////////////////////////////////////////////////////////////
11449//Capture the status register data from rtl. For disrupting traps,
11450//rtl can modify the contents of the status register before the
11451//trap is taken and intp message is sent to Riesling.
11452//For precise traps, once the status register is updated rtl can't
11453//change the register again before jumping to the trap handler.
11454//So, for deferred and disrupting traps, inform Riesling when the
11455//register is modified while for precise traps wait until Fw2 before
11456//telling Riesling.
11457
11458//TLU asserts the flush and input signals in W stage. I latch them at the
11459//+ve edge of FX4.
11460
11461always @(negedge (`SPC4.l2clk & ready))
11462begin // {
11463 if (`DESR_asi_rd_39)
11464 desr_asi_rd <= 1'b1;
11465 if (desr_asi_rd)
11466 begin
11467 if (desr_wr)
11468 desr_pend_wr <= 1'b1;
11469 if (`ASI_LD_COMP_39[2])
11470 desr_asi_rd <= 1'b0;
11471 end
11472
11473 update_dsfsr_w <= (`DSFSR_NEW_IN_39 != 4'b0) && ~`ASI_WR_DSFSR_39;
11474 update_isfsr_w <= (`ISFSR_NEW_IN_39 != 3'b0) && ~`ASI_WR_ISFSR_39;
11475 desr_wr <= (`RAS_WRITE_DESR_1st_39 || `RAS_WRITE_DESR_2nd_39);
11476 update_dfesr_w <= `RAS_WRITE_FESR_39;
11477 take_err_trap_fx4 <= `ST_ERR_39 | `SW_REC_ERR_39 | `DATA_ACC_ERR_39
11478 | `INST_ACC_ERR_39 | `INT_PROC_ERR_39
11479 | `HW_CORR_ERR_39 | `INST_ACC_MMU_ERR_39
11480 | `DATA_ACC_MMU_ERR_39 ;
11481
11482
11483 if (`ST_ERR_39) int_num_fx4 <= 8'h07;
11484 if (`SW_REC_ERR_39) int_num_fx4 <= 8'h40;
11485 if (`DATA_ACC_ERR_39) int_num_fx4 <= 8'h32;
11486 if (`INST_ACC_ERR_39) int_num_fx4 <= 8'h0A;
11487 if (`INT_PROC_ERR_39) int_num_fx4 <= 8'h29;
11488 if (`HW_CORR_ERR_39) int_num_fx4 <= 8'h63;
11489 if (`INST_ACC_MMU_ERR_39) int_num_fx4 <= 8'h71;
11490 if (`DATA_ACC_MMU_ERR_39) int_num_fx4 <= 8'h72;
11491
11492 update_dsfsr_fx4 <= update_dsfsr_w;
11493 update_dsfsr_fx5 <= update_dsfsr_fx4;
11494 update_dsfsr_fb <= update_dsfsr_fx5;
11495 update_dsfsr_fw <= update_dsfsr_fb;
11496 update_dsfsr_fw1 <= update_dsfsr_fw;
11497 update_dsfsr_fw2 <= update_dsfsr_fw1;
11498
11499 update_isfsr_fx4 <= update_isfsr_w;
11500 update_isfsr_fx5 <= update_isfsr_fx4;
11501 update_isfsr_fb <= update_isfsr_fx5;
11502 update_isfsr_fw <= update_isfsr_fb;
11503 update_isfsr_fw1 <= update_isfsr_fw;
11504 update_isfsr_fw2 <= update_isfsr_fw1;
11505
11506 take_err_trap_fx5 <= take_err_trap_fx4;
11507 take_err_trap_fb <= take_err_trap_fx5;
11508 take_err_trap_fw <= take_err_trap_fb;
11509 take_err_trap_fw1 <= take_err_trap_fw;
11510 take_err_trap_fw2 <= take_err_trap_fw1;
11511
11512 int_num_fx5 <= int_num_fx4;
11513 int_num_fb <= int_num_fx5;
11514 int_num_fw <= int_num_fb;
11515 int_num_fw1 <= int_num_fw;
11516 int_num_fw2 <= int_num_fw1;
11517
11518 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
11519 begin // {
11520 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
11521 begin //{
11522 desr_pend_wr <= 1'b0;
11523 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_39[63:56], 45'b0, `DESR_39[10:0]});
11524 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_39[63:56], 45'b0, `DESR_39[10:0]});
11525 end //}
11526 //if (update_dfesr_w)
11527 if (`ST_ERR_39)
11528 begin //{
11529 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_39[61:55], 55'b0});
11530 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_39[61:55], 55'b0});
11531 end //}
11532 if (update_dsfsr_fw2)
11533 begin //{
11534 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
11535 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_39[3:0]});
11536 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_39[47:0]});
11537
11538 end //}
11539 if (update_isfsr_fw2)
11540 begin //{
11541 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
11542 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_39[2:0]});
11543 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_39[47:0]});
11544
11545 end //}
11546 if (take_err_trap_fw2)
11547 begin //{
11548 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
11549 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
11550 end // }
11551 end // }
11552
11553end //}
11554
11555//removing the addr check as the LSU doesn't flag an invalid_asi_exception
11556//if the addr of diagnostic accesses is not in the valid range. The inst.
11557//still executes. LSU expects that HP won't use addresses in invalid range.
11558
11559always @(negedge (`SPC4.l2clk & ready))
11560begin // {
11561 sync_asi = 1'b0;
11562 ld_data_w <= `ASI_LD_DATA_39;
11563
11564 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_39)
11565 chk_if_asi_ld <= 1'b1;
11566 else
11567 chk_if_asi_ld <= 1'b0;
11568
11569 if (chk_if_asi_ld & `ASI_LD_39)
11570 begin
11571 case (`ASI_39)
11572 8'h66: //ASI_IC_INSTR
11573 begin
11574 //if ((`ASI_ADDR_39 >= 0) & (`ASI_ADDR_39 <= 40'h7ff8))
11575 sync_asi = 1'b1;
11576 end
11577 8'h67: //ASI_IC_TAG
11578 begin
11579 //if ((`ASI_ADDR_39 >= 0) & (`ASI_ADDR_39 <= 40'h7fe0))
11580 sync_asi = 1'b1;
11581 end
11582 8'h46: //ASI_DC_DATA
11583 begin
11584 sync_asi = 1'b1;
11585 end
11586 8'h47: //ASI_DC_TAG
11587 begin
11588 //if ((`ASI_ADDR_39 >= 0) & (`ASI_ADDR_39 <= 40'h7ff0))
11589 sync_asi = 1'b1;
11590 end
11591 8'h48://IRF ECC
11592 begin
11593 //if ((`ASI_ADDR_39 >= 0) & (`ASI_ADDR_39 <= 40'hF8))
11594 sync_asi = 1'b1;
11595 end
11596 8'h49://FRF ECC
11597 begin
11598 //if ((`ASI_ADDR_39 >= 0) & (`ASI_ADDR_39 <= 40'hF8))
11599 sync_asi = 1'b1;
11600 end
11601 8'h4A://STB access, stb ptr can be read also
11602 begin
11603 //if ((`ASI_ADDR_39 >= 0) & (`ASI_ADDR_39 <= 40'h100))
11604 sync_asi = 1'b1;
11605 end
11606 8'h5A://Tick compare reg
11607 begin
11608 //if ((`ASI_ADDR_39 >= 0) & (`ASI_ADDR_39 <= 40'h38))
11609 sync_asi = 1'b1;
11610 end
11611 8'h5B://TSA
11612 begin
11613 //if ((`ASI_ADDR_39 >= 0) & (`ASI_ADDR_39 <= 40'h38))
11614 sync_asi = 1'b1;
11615 end
11616 8'h51://MRA
11617 begin
11618 //if ((`ASI_ADDR_39 >= 0) & (`ASI_ADDR_39 <= 40'h38))
11619 sync_asi = 1'b1;
11620 end
11621 8'h59://scratchpad ecc data read
11622 begin
11623 //if ((`ASI_ADDR_39 >= 0) & (`ASI_ADDR_39 <= 40'h38))
11624 //syncup the ecc data only. For ecc bit 6 is 0.
11625 if (~`SPC4.lsu.lmd.lmq7_pkt[6])
11626 sync_asi = 1'b1;
11627 end
11628 8'h40://cwqcsr,ma_sync access
11629 begin
11630 if ((`ASI_ADDR_39 == 40'h20) || (`ASI_ADDR_39 == 40'h30)
11631 || (`ASI_ADDR_39 == 40'h80)
11632 || ((`ASI_ADDR_39 == 40'ha0) & (`SPU_MA_BUSY_4 == 0) & (`SPU_MA_TID_4 == 7))
11633 )
11634 sync_asi = 1'b1;
11635 end
11636 8'h4C://CLESR, CLFESR access
11637 begin
11638 if ((`ASI_ADDR_39 == 40'h20) || (`ASI_ADDR_39 == 40'h28))
11639 sync_asi = 1'b1;
11640 end
11641 endcase
11642 end
11643
11644 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
11645 begin
11646 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_39, `ASI_ADDR_39, ld_data_w);
11647 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_39, {24'b0, `ASI_ADDR_39}, ld_data_w[63:0]);
11648 end
11649end //}
11650`endif
11651endmodule
11652
11653`endif
11654
11655`ifdef CORE_5
11656
11657
11658
11659module err_c5t0 ();
11660`ifndef GATESIM
11661
11662`include "defines.vh"
11663
11664wire [2:0] mycid;
11665wire [2:0] mytid;
11666wire [5:0] mytnum;
11667
11668integer junk;
11669reg ready;
11670reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
11671reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
11672
11673reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
11674reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
11675
11676reg update_dfesr_w;
11677
11678reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
11679reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
11680
11681reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
11682reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
11683
11684reg sync_asi;
11685reg chk_if_asi_ld;
11686reg [63:0] ld_data_w;
11687
11688reg desr_asi_rd, desr_wr, desr_pend_wr;
11689
11690assign mycid = 5;
11691assign mytid = 0;
11692assign mytnum = 5*8 + 0;
11693
11694initial begin //{
11695 desr_asi_rd = 1'b0;
11696 desr_pend_wr = 1'b0;
11697 ready = 0;
11698 @(posedge `SPC5.l2clk) ;
11699 @(posedge `SPC5.l2clk) ;
11700 ready = `PARGS.err_sync_on;
11701end //}
11702
11703`define DSFSR_NEW_IN_40 `SPC5.tlu.ras.dsfsr_0_new_in
11704`define ISFSR_NEW_IN_40 `SPC5.tlu.ras.isfsr_0_new_in
11705
11706`define DSFSR_40 `SPC5.tlu.ras.dsfsr_0
11707`define ISFSR_40 `SPC5.tlu.ras.isfsr_0
11708`define DSFAR_40 `SPC5.tlu.dfd.dsfar_0
11709
11710`define ASI_WR_DSFSR_40 `SPC5.tlu.ras.asi_wr_dsfsr[0]
11711`define ASI_WR_ISFSR_40 `SPC5.tlu.ras.asi_wr_isfsr[0]
11712
11713`define RAS_WRITE_DESR_1st_40 `SPC5.tlu.dfd.ras_write_desr_1st[0]
11714`define RAS_WRITE_DESR_2nd_40 `SPC5.tlu.dfd.ras_write_desr_2nd[0]
11715`define DESR_asi_rd_40 `SPC5.tlu.ras_rd_desr[0]
11716`define DESR_40 `SPC5.tlu.dfd.desr_0
11717
11718`define RAS_WRITE_FESR_40 `SPC5.tlu.ras.write_fesr[0]
11719`define FESR_40 `SPC5.tlu.dfd.fesr_0
11720
11721`define ST_ERR_40 `SPC5.tlu.trl0.take_ftt & `SPC5.tlu.trl0.trap[0]
11722`define SW_REC_ERR_40 `SPC5.tlu.trl0.take_ade & `SPC5.tlu.trl0.trap[0]
11723`define DATA_ACC_ERR_40 `SPC5.tlu.trl0.take_dae & `SPC5.tlu.trl0.trap[0]
11724`define INST_ACC_ERR_40 `SPC5.tlu.trl0.take_iae & `SPC5.tlu.trl0.trap[0]
11725`define INT_PROC_ERR_40 `SPC5.tlu.trl0.take_ipe & `SPC5.tlu.trl0.trap[0]
11726`define HW_CORR_ERR_40 `SPC5.tlu.trl0.take_eer & `SPC5.tlu.trl0.trap[0]
11727`define INST_ACC_MMU_ERR_40 `SPC5.tlu.trl0.take_ime & `SPC5.tlu.trl0.trap[0]
11728`define DATA_ACC_MMU_ERR_40 `SPC5.tlu.trl0.take_dme & `SPC5.tlu.trl0.trap[0]
11729
11730`define LSU_LD_VALID_B `PROBES5.lsu_ld_valid
11731`define LSU_TID_DEC_B_40 `PROBES5.lsu_tid_dec_b[0]
11732`define ASI_LD_40 `SPC5.lsu.lmd.lmq0_pkt[60] & (`SPC5.lsu.lmd.lmq0_pkt[49:48] == 2'b0)
11733`define ASI_40 `SPC5.lsu.lmd.lmq0_pkt[47:40]
11734`define ASI_ADDR_40 `SPC5.lsu.lmd.lmq0_pkt[39:0]
11735`define ASI_LD_DATA_40 `SPC5.lsu_exu_ld_data_b[63:0]
11736`define ASI_LD_COMP_40 tb_top.nas_top.c5.t0.complete_fw2
11737
11738//SPU specific - only one SPU per core
11739`define SPU_MA_BUSY_5 `SPC5.spu.spu_pmu_ma_busy[3]
11740`define SPU_MA_TID_5 `SPC5.spu.spu_pmu_ma_busy[2:0]
11741
11742////////////////////////////////////////////////////////////////////////////////
11743//Capture the status register data from rtl. For disrupting traps,
11744//rtl can modify the contents of the status register before the
11745//trap is taken and intp message is sent to Riesling.
11746//For precise traps, once the status register is updated rtl can't
11747//change the register again before jumping to the trap handler.
11748//So, for deferred and disrupting traps, inform Riesling when the
11749//register is modified while for precise traps wait until Fw2 before
11750//telling Riesling.
11751
11752//TLU asserts the flush and input signals in W stage. I latch them at the
11753//+ve edge of FX4.
11754
11755always @(negedge (`SPC5.l2clk & ready))
11756begin // {
11757 if (`DESR_asi_rd_40)
11758 desr_asi_rd <= 1'b1;
11759 if (desr_asi_rd)
11760 begin
11761 if (desr_wr)
11762 desr_pend_wr <= 1'b1;
11763 if (`ASI_LD_COMP_40[2])
11764 desr_asi_rd <= 1'b0;
11765 end
11766
11767 update_dsfsr_w <= (`DSFSR_NEW_IN_40 != 4'b0) && ~`ASI_WR_DSFSR_40;
11768 update_isfsr_w <= (`ISFSR_NEW_IN_40 != 3'b0) && ~`ASI_WR_ISFSR_40;
11769 desr_wr <= (`RAS_WRITE_DESR_1st_40 || `RAS_WRITE_DESR_2nd_40);
11770 update_dfesr_w <= `RAS_WRITE_FESR_40;
11771 take_err_trap_fx4 <= `ST_ERR_40 | `SW_REC_ERR_40 | `DATA_ACC_ERR_40
11772 | `INST_ACC_ERR_40 | `INT_PROC_ERR_40
11773 | `HW_CORR_ERR_40 | `INST_ACC_MMU_ERR_40
11774 | `DATA_ACC_MMU_ERR_40 ;
11775
11776
11777 if (`ST_ERR_40) int_num_fx4 <= 8'h07;
11778 if (`SW_REC_ERR_40) int_num_fx4 <= 8'h40;
11779 if (`DATA_ACC_ERR_40) int_num_fx4 <= 8'h32;
11780 if (`INST_ACC_ERR_40) int_num_fx4 <= 8'h0A;
11781 if (`INT_PROC_ERR_40) int_num_fx4 <= 8'h29;
11782 if (`HW_CORR_ERR_40) int_num_fx4 <= 8'h63;
11783 if (`INST_ACC_MMU_ERR_40) int_num_fx4 <= 8'h71;
11784 if (`DATA_ACC_MMU_ERR_40) int_num_fx4 <= 8'h72;
11785
11786 update_dsfsr_fx4 <= update_dsfsr_w;
11787 update_dsfsr_fx5 <= update_dsfsr_fx4;
11788 update_dsfsr_fb <= update_dsfsr_fx5;
11789 update_dsfsr_fw <= update_dsfsr_fb;
11790 update_dsfsr_fw1 <= update_dsfsr_fw;
11791 update_dsfsr_fw2 <= update_dsfsr_fw1;
11792
11793 update_isfsr_fx4 <= update_isfsr_w;
11794 update_isfsr_fx5 <= update_isfsr_fx4;
11795 update_isfsr_fb <= update_isfsr_fx5;
11796 update_isfsr_fw <= update_isfsr_fb;
11797 update_isfsr_fw1 <= update_isfsr_fw;
11798 update_isfsr_fw2 <= update_isfsr_fw1;
11799
11800 take_err_trap_fx5 <= take_err_trap_fx4;
11801 take_err_trap_fb <= take_err_trap_fx5;
11802 take_err_trap_fw <= take_err_trap_fb;
11803 take_err_trap_fw1 <= take_err_trap_fw;
11804 take_err_trap_fw2 <= take_err_trap_fw1;
11805
11806 int_num_fx5 <= int_num_fx4;
11807 int_num_fb <= int_num_fx5;
11808 int_num_fw <= int_num_fb;
11809 int_num_fw1 <= int_num_fw;
11810 int_num_fw2 <= int_num_fw1;
11811
11812 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
11813 begin // {
11814 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
11815 begin //{
11816 desr_pend_wr <= 1'b0;
11817 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_40[63:56], 45'b0, `DESR_40[10:0]});
11818 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_40[63:56], 45'b0, `DESR_40[10:0]});
11819 end //}
11820 //if (update_dfesr_w)
11821 if (`ST_ERR_40)
11822 begin //{
11823 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_40[61:55], 55'b0});
11824 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_40[61:55], 55'b0});
11825 end //}
11826 if (update_dsfsr_fw2)
11827 begin //{
11828 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
11829 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_40[3:0]});
11830 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_40[47:0]});
11831
11832 end //}
11833 if (update_isfsr_fw2)
11834 begin //{
11835 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
11836 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_40[2:0]});
11837 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_40[47:0]});
11838
11839 end //}
11840 if (take_err_trap_fw2)
11841 begin //{
11842 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
11843 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
11844 end // }
11845 end // }
11846
11847end //}
11848
11849//removing the addr check as the LSU doesn't flag an invalid_asi_exception
11850//if the addr of diagnostic accesses is not in the valid range. The inst.
11851//still executes. LSU expects that HP won't use addresses in invalid range.
11852
11853always @(negedge (`SPC5.l2clk & ready))
11854begin // {
11855 sync_asi = 1'b0;
11856 ld_data_w <= `ASI_LD_DATA_40;
11857
11858 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_40)
11859 chk_if_asi_ld <= 1'b1;
11860 else
11861 chk_if_asi_ld <= 1'b0;
11862
11863 if (chk_if_asi_ld & `ASI_LD_40)
11864 begin
11865 case (`ASI_40)
11866 8'h66: //ASI_IC_INSTR
11867 begin
11868 //if ((`ASI_ADDR_40 >= 0) & (`ASI_ADDR_40 <= 40'h7ff8))
11869 sync_asi = 1'b1;
11870 end
11871 8'h67: //ASI_IC_TAG
11872 begin
11873 //if ((`ASI_ADDR_40 >= 0) & (`ASI_ADDR_40 <= 40'h7fe0))
11874 sync_asi = 1'b1;
11875 end
11876 8'h46: //ASI_DC_DATA
11877 begin
11878 sync_asi = 1'b1;
11879 end
11880 8'h47: //ASI_DC_TAG
11881 begin
11882 //if ((`ASI_ADDR_40 >= 0) & (`ASI_ADDR_40 <= 40'h7ff0))
11883 sync_asi = 1'b1;
11884 end
11885 8'h48://IRF ECC
11886 begin
11887 //if ((`ASI_ADDR_40 >= 0) & (`ASI_ADDR_40 <= 40'hF8))
11888 sync_asi = 1'b1;
11889 end
11890 8'h49://FRF ECC
11891 begin
11892 //if ((`ASI_ADDR_40 >= 0) & (`ASI_ADDR_40 <= 40'hF8))
11893 sync_asi = 1'b1;
11894 end
11895 8'h4A://STB access, stb ptr can be read also
11896 begin
11897 //if ((`ASI_ADDR_40 >= 0) & (`ASI_ADDR_40 <= 40'h100))
11898 sync_asi = 1'b1;
11899 end
11900 8'h5A://Tick compare reg
11901 begin
11902 //if ((`ASI_ADDR_40 >= 0) & (`ASI_ADDR_40 <= 40'h38))
11903 sync_asi = 1'b1;
11904 end
11905 8'h5B://TSA
11906 begin
11907 //if ((`ASI_ADDR_40 >= 0) & (`ASI_ADDR_40 <= 40'h38))
11908 sync_asi = 1'b1;
11909 end
11910 8'h51://MRA
11911 begin
11912 //if ((`ASI_ADDR_40 >= 0) & (`ASI_ADDR_40 <= 40'h38))
11913 sync_asi = 1'b1;
11914 end
11915 8'h59://scratchpad ecc data read
11916 begin
11917 //if ((`ASI_ADDR_40 >= 0) & (`ASI_ADDR_40 <= 40'h38))
11918 //syncup the ecc data only. For ecc bit 6 is 0.
11919 if (~`SPC5.lsu.lmd.lmq0_pkt[6])
11920 sync_asi = 1'b1;
11921 end
11922 8'h40://cwqcsr,ma_sync access
11923 begin
11924 if ((`ASI_ADDR_40 == 40'h20) || (`ASI_ADDR_40 == 40'h30)
11925 || (`ASI_ADDR_40 == 40'h80)
11926 || ((`ASI_ADDR_40 == 40'ha0) & (`SPU_MA_BUSY_5 == 0) & (`SPU_MA_TID_5 == 0))
11927 )
11928 sync_asi = 1'b1;
11929 end
11930 8'h4C://CLESR, CLFESR access
11931 begin
11932 if ((`ASI_ADDR_40 == 40'h20) || (`ASI_ADDR_40 == 40'h28))
11933 sync_asi = 1'b1;
11934 end
11935 endcase
11936 end
11937
11938 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
11939 begin
11940 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_40, `ASI_ADDR_40, ld_data_w);
11941 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_40, {24'b0, `ASI_ADDR_40}, ld_data_w[63:0]);
11942 end
11943end //}
11944`endif
11945endmodule
11946
11947
11948
11949module err_c5t1 ();
11950`ifndef GATESIM
11951
11952`include "defines.vh"
11953
11954wire [2:0] mycid;
11955wire [2:0] mytid;
11956wire [5:0] mytnum;
11957
11958integer junk;
11959reg ready;
11960reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
11961reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
11962
11963reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
11964reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
11965
11966reg update_dfesr_w;
11967
11968reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
11969reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
11970
11971reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
11972reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
11973
11974reg sync_asi;
11975reg chk_if_asi_ld;
11976reg [63:0] ld_data_w;
11977
11978reg desr_asi_rd, desr_wr, desr_pend_wr;
11979
11980assign mycid = 5;
11981assign mytid = 1;
11982assign mytnum = 5*8 + 1;
11983
11984initial begin //{
11985 desr_asi_rd = 1'b0;
11986 desr_pend_wr = 1'b0;
11987 ready = 0;
11988 @(posedge `SPC5.l2clk) ;
11989 @(posedge `SPC5.l2clk) ;
11990 ready = `PARGS.err_sync_on;
11991end //}
11992
11993`define DSFSR_NEW_IN_41 `SPC5.tlu.ras.dsfsr_1_new_in
11994`define ISFSR_NEW_IN_41 `SPC5.tlu.ras.isfsr_1_new_in
11995
11996`define DSFSR_41 `SPC5.tlu.ras.dsfsr_1
11997`define ISFSR_41 `SPC5.tlu.ras.isfsr_1
11998`define DSFAR_41 `SPC5.tlu.dfd.dsfar_1
11999
12000`define ASI_WR_DSFSR_41 `SPC5.tlu.ras.asi_wr_dsfsr[1]
12001`define ASI_WR_ISFSR_41 `SPC5.tlu.ras.asi_wr_isfsr[1]
12002
12003`define RAS_WRITE_DESR_1st_41 `SPC5.tlu.dfd.ras_write_desr_1st[1]
12004`define RAS_WRITE_DESR_2nd_41 `SPC5.tlu.dfd.ras_write_desr_2nd[1]
12005`define DESR_asi_rd_41 `SPC5.tlu.ras_rd_desr[1]
12006`define DESR_41 `SPC5.tlu.dfd.desr_1
12007
12008`define RAS_WRITE_FESR_41 `SPC5.tlu.ras.write_fesr[1]
12009`define FESR_41 `SPC5.tlu.dfd.fesr_1
12010
12011`define ST_ERR_41 `SPC5.tlu.trl0.take_ftt & `SPC5.tlu.trl0.trap[1]
12012`define SW_REC_ERR_41 `SPC5.tlu.trl0.take_ade & `SPC5.tlu.trl0.trap[1]
12013`define DATA_ACC_ERR_41 `SPC5.tlu.trl0.take_dae & `SPC5.tlu.trl0.trap[1]
12014`define INST_ACC_ERR_41 `SPC5.tlu.trl0.take_iae & `SPC5.tlu.trl0.trap[1]
12015`define INT_PROC_ERR_41 `SPC5.tlu.trl0.take_ipe & `SPC5.tlu.trl0.trap[1]
12016`define HW_CORR_ERR_41 `SPC5.tlu.trl0.take_eer & `SPC5.tlu.trl0.trap[1]
12017`define INST_ACC_MMU_ERR_41 `SPC5.tlu.trl0.take_ime & `SPC5.tlu.trl0.trap[1]
12018`define DATA_ACC_MMU_ERR_41 `SPC5.tlu.trl0.take_dme & `SPC5.tlu.trl0.trap[1]
12019
12020`define LSU_LD_VALID_B `PROBES5.lsu_ld_valid
12021`define LSU_TID_DEC_B_41 `PROBES5.lsu_tid_dec_b[1]
12022`define ASI_LD_41 `SPC5.lsu.lmd.lmq1_pkt[60] & (`SPC5.lsu.lmd.lmq1_pkt[49:48] == 2'b0)
12023`define ASI_41 `SPC5.lsu.lmd.lmq1_pkt[47:40]
12024`define ASI_ADDR_41 `SPC5.lsu.lmd.lmq1_pkt[39:0]
12025`define ASI_LD_DATA_41 `SPC5.lsu_exu_ld_data_b[63:0]
12026`define ASI_LD_COMP_41 tb_top.nas_top.c5.t1.complete_fw2
12027
12028//SPU specific - only one SPU per core
12029`define SPU_MA_BUSY_5 `SPC5.spu.spu_pmu_ma_busy[3]
12030`define SPU_MA_TID_5 `SPC5.spu.spu_pmu_ma_busy[2:0]
12031
12032////////////////////////////////////////////////////////////////////////////////
12033//Capture the status register data from rtl. For disrupting traps,
12034//rtl can modify the contents of the status register before the
12035//trap is taken and intp message is sent to Riesling.
12036//For precise traps, once the status register is updated rtl can't
12037//change the register again before jumping to the trap handler.
12038//So, for deferred and disrupting traps, inform Riesling when the
12039//register is modified while for precise traps wait until Fw2 before
12040//telling Riesling.
12041
12042//TLU asserts the flush and input signals in W stage. I latch them at the
12043//+ve edge of FX4.
12044
12045always @(negedge (`SPC5.l2clk & ready))
12046begin // {
12047 if (`DESR_asi_rd_41)
12048 desr_asi_rd <= 1'b1;
12049 if (desr_asi_rd)
12050 begin
12051 if (desr_wr)
12052 desr_pend_wr <= 1'b1;
12053 if (`ASI_LD_COMP_41[2])
12054 desr_asi_rd <= 1'b0;
12055 end
12056
12057 update_dsfsr_w <= (`DSFSR_NEW_IN_41 != 4'b0) && ~`ASI_WR_DSFSR_41;
12058 update_isfsr_w <= (`ISFSR_NEW_IN_41 != 3'b0) && ~`ASI_WR_ISFSR_41;
12059 desr_wr <= (`RAS_WRITE_DESR_1st_41 || `RAS_WRITE_DESR_2nd_41);
12060 update_dfesr_w <= `RAS_WRITE_FESR_41;
12061 take_err_trap_fx4 <= `ST_ERR_41 | `SW_REC_ERR_41 | `DATA_ACC_ERR_41
12062 | `INST_ACC_ERR_41 | `INT_PROC_ERR_41
12063 | `HW_CORR_ERR_41 | `INST_ACC_MMU_ERR_41
12064 | `DATA_ACC_MMU_ERR_41 ;
12065
12066
12067 if (`ST_ERR_41) int_num_fx4 <= 8'h07;
12068 if (`SW_REC_ERR_41) int_num_fx4 <= 8'h40;
12069 if (`DATA_ACC_ERR_41) int_num_fx4 <= 8'h32;
12070 if (`INST_ACC_ERR_41) int_num_fx4 <= 8'h0A;
12071 if (`INT_PROC_ERR_41) int_num_fx4 <= 8'h29;
12072 if (`HW_CORR_ERR_41) int_num_fx4 <= 8'h63;
12073 if (`INST_ACC_MMU_ERR_41) int_num_fx4 <= 8'h71;
12074 if (`DATA_ACC_MMU_ERR_41) int_num_fx4 <= 8'h72;
12075
12076 update_dsfsr_fx4 <= update_dsfsr_w;
12077 update_dsfsr_fx5 <= update_dsfsr_fx4;
12078 update_dsfsr_fb <= update_dsfsr_fx5;
12079 update_dsfsr_fw <= update_dsfsr_fb;
12080 update_dsfsr_fw1 <= update_dsfsr_fw;
12081 update_dsfsr_fw2 <= update_dsfsr_fw1;
12082
12083 update_isfsr_fx4 <= update_isfsr_w;
12084 update_isfsr_fx5 <= update_isfsr_fx4;
12085 update_isfsr_fb <= update_isfsr_fx5;
12086 update_isfsr_fw <= update_isfsr_fb;
12087 update_isfsr_fw1 <= update_isfsr_fw;
12088 update_isfsr_fw2 <= update_isfsr_fw1;
12089
12090 take_err_trap_fx5 <= take_err_trap_fx4;
12091 take_err_trap_fb <= take_err_trap_fx5;
12092 take_err_trap_fw <= take_err_trap_fb;
12093 take_err_trap_fw1 <= take_err_trap_fw;
12094 take_err_trap_fw2 <= take_err_trap_fw1;
12095
12096 int_num_fx5 <= int_num_fx4;
12097 int_num_fb <= int_num_fx5;
12098 int_num_fw <= int_num_fb;
12099 int_num_fw1 <= int_num_fw;
12100 int_num_fw2 <= int_num_fw1;
12101
12102 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
12103 begin // {
12104 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
12105 begin //{
12106 desr_pend_wr <= 1'b0;
12107 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_41[63:56], 45'b0, `DESR_41[10:0]});
12108 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_41[63:56], 45'b0, `DESR_41[10:0]});
12109 end //}
12110 //if (update_dfesr_w)
12111 if (`ST_ERR_41)
12112 begin //{
12113 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_41[61:55], 55'b0});
12114 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_41[61:55], 55'b0});
12115 end //}
12116 if (update_dsfsr_fw2)
12117 begin //{
12118 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
12119 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_41[3:0]});
12120 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_41[47:0]});
12121
12122 end //}
12123 if (update_isfsr_fw2)
12124 begin //{
12125 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
12126 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_41[2:0]});
12127 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_41[47:0]});
12128
12129 end //}
12130 if (take_err_trap_fw2)
12131 begin //{
12132 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
12133 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
12134 end // }
12135 end // }
12136
12137end //}
12138
12139//removing the addr check as the LSU doesn't flag an invalid_asi_exception
12140//if the addr of diagnostic accesses is not in the valid range. The inst.
12141//still executes. LSU expects that HP won't use addresses in invalid range.
12142
12143always @(negedge (`SPC5.l2clk & ready))
12144begin // {
12145 sync_asi = 1'b0;
12146 ld_data_w <= `ASI_LD_DATA_41;
12147
12148 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_41)
12149 chk_if_asi_ld <= 1'b1;
12150 else
12151 chk_if_asi_ld <= 1'b0;
12152
12153 if (chk_if_asi_ld & `ASI_LD_41)
12154 begin
12155 case (`ASI_41)
12156 8'h66: //ASI_IC_INSTR
12157 begin
12158 //if ((`ASI_ADDR_41 >= 0) & (`ASI_ADDR_41 <= 40'h7ff8))
12159 sync_asi = 1'b1;
12160 end
12161 8'h67: //ASI_IC_TAG
12162 begin
12163 //if ((`ASI_ADDR_41 >= 0) & (`ASI_ADDR_41 <= 40'h7fe0))
12164 sync_asi = 1'b1;
12165 end
12166 8'h46: //ASI_DC_DATA
12167 begin
12168 sync_asi = 1'b1;
12169 end
12170 8'h47: //ASI_DC_TAG
12171 begin
12172 //if ((`ASI_ADDR_41 >= 0) & (`ASI_ADDR_41 <= 40'h7ff0))
12173 sync_asi = 1'b1;
12174 end
12175 8'h48://IRF ECC
12176 begin
12177 //if ((`ASI_ADDR_41 >= 0) & (`ASI_ADDR_41 <= 40'hF8))
12178 sync_asi = 1'b1;
12179 end
12180 8'h49://FRF ECC
12181 begin
12182 //if ((`ASI_ADDR_41 >= 0) & (`ASI_ADDR_41 <= 40'hF8))
12183 sync_asi = 1'b1;
12184 end
12185 8'h4A://STB access, stb ptr can be read also
12186 begin
12187 //if ((`ASI_ADDR_41 >= 0) & (`ASI_ADDR_41 <= 40'h100))
12188 sync_asi = 1'b1;
12189 end
12190 8'h5A://Tick compare reg
12191 begin
12192 //if ((`ASI_ADDR_41 >= 0) & (`ASI_ADDR_41 <= 40'h38))
12193 sync_asi = 1'b1;
12194 end
12195 8'h5B://TSA
12196 begin
12197 //if ((`ASI_ADDR_41 >= 0) & (`ASI_ADDR_41 <= 40'h38))
12198 sync_asi = 1'b1;
12199 end
12200 8'h51://MRA
12201 begin
12202 //if ((`ASI_ADDR_41 >= 0) & (`ASI_ADDR_41 <= 40'h38))
12203 sync_asi = 1'b1;
12204 end
12205 8'h59://scratchpad ecc data read
12206 begin
12207 //if ((`ASI_ADDR_41 >= 0) & (`ASI_ADDR_41 <= 40'h38))
12208 //syncup the ecc data only. For ecc bit 6 is 0.
12209 if (~`SPC5.lsu.lmd.lmq1_pkt[6])
12210 sync_asi = 1'b1;
12211 end
12212 8'h40://cwqcsr,ma_sync access
12213 begin
12214 if ((`ASI_ADDR_41 == 40'h20) || (`ASI_ADDR_41 == 40'h30)
12215 || (`ASI_ADDR_41 == 40'h80)
12216 || ((`ASI_ADDR_41 == 40'ha0) & (`SPU_MA_BUSY_5 == 0) & (`SPU_MA_TID_5 == 1))
12217 )
12218 sync_asi = 1'b1;
12219 end
12220 8'h4C://CLESR, CLFESR access
12221 begin
12222 if ((`ASI_ADDR_41 == 40'h20) || (`ASI_ADDR_41 == 40'h28))
12223 sync_asi = 1'b1;
12224 end
12225 endcase
12226 end
12227
12228 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
12229 begin
12230 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_41, `ASI_ADDR_41, ld_data_w);
12231 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_41, {24'b0, `ASI_ADDR_41}, ld_data_w[63:0]);
12232 end
12233end //}
12234`endif
12235endmodule
12236
12237
12238
12239module err_c5t2 ();
12240`ifndef GATESIM
12241
12242`include "defines.vh"
12243
12244wire [2:0] mycid;
12245wire [2:0] mytid;
12246wire [5:0] mytnum;
12247
12248integer junk;
12249reg ready;
12250reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
12251reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
12252
12253reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
12254reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
12255
12256reg update_dfesr_w;
12257
12258reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
12259reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
12260
12261reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
12262reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
12263
12264reg sync_asi;
12265reg chk_if_asi_ld;
12266reg [63:0] ld_data_w;
12267
12268reg desr_asi_rd, desr_wr, desr_pend_wr;
12269
12270assign mycid = 5;
12271assign mytid = 2;
12272assign mytnum = 5*8 + 2;
12273
12274initial begin //{
12275 desr_asi_rd = 1'b0;
12276 desr_pend_wr = 1'b0;
12277 ready = 0;
12278 @(posedge `SPC5.l2clk) ;
12279 @(posedge `SPC5.l2clk) ;
12280 ready = `PARGS.err_sync_on;
12281end //}
12282
12283`define DSFSR_NEW_IN_42 `SPC5.tlu.ras.dsfsr_2_new_in
12284`define ISFSR_NEW_IN_42 `SPC5.tlu.ras.isfsr_2_new_in
12285
12286`define DSFSR_42 `SPC5.tlu.ras.dsfsr_2
12287`define ISFSR_42 `SPC5.tlu.ras.isfsr_2
12288`define DSFAR_42 `SPC5.tlu.dfd.dsfar_2
12289
12290`define ASI_WR_DSFSR_42 `SPC5.tlu.ras.asi_wr_dsfsr[2]
12291`define ASI_WR_ISFSR_42 `SPC5.tlu.ras.asi_wr_isfsr[2]
12292
12293`define RAS_WRITE_DESR_1st_42 `SPC5.tlu.dfd.ras_write_desr_1st[2]
12294`define RAS_WRITE_DESR_2nd_42 `SPC5.tlu.dfd.ras_write_desr_2nd[2]
12295`define DESR_asi_rd_42 `SPC5.tlu.ras_rd_desr[2]
12296`define DESR_42 `SPC5.tlu.dfd.desr_2
12297
12298`define RAS_WRITE_FESR_42 `SPC5.tlu.ras.write_fesr[2]
12299`define FESR_42 `SPC5.tlu.dfd.fesr_2
12300
12301`define ST_ERR_42 `SPC5.tlu.trl0.take_ftt & `SPC5.tlu.trl0.trap[2]
12302`define SW_REC_ERR_42 `SPC5.tlu.trl0.take_ade & `SPC5.tlu.trl0.trap[2]
12303`define DATA_ACC_ERR_42 `SPC5.tlu.trl0.take_dae & `SPC5.tlu.trl0.trap[2]
12304`define INST_ACC_ERR_42 `SPC5.tlu.trl0.take_iae & `SPC5.tlu.trl0.trap[2]
12305`define INT_PROC_ERR_42 `SPC5.tlu.trl0.take_ipe & `SPC5.tlu.trl0.trap[2]
12306`define HW_CORR_ERR_42 `SPC5.tlu.trl0.take_eer & `SPC5.tlu.trl0.trap[2]
12307`define INST_ACC_MMU_ERR_42 `SPC5.tlu.trl0.take_ime & `SPC5.tlu.trl0.trap[2]
12308`define DATA_ACC_MMU_ERR_42 `SPC5.tlu.trl0.take_dme & `SPC5.tlu.trl0.trap[2]
12309
12310`define LSU_LD_VALID_B `PROBES5.lsu_ld_valid
12311`define LSU_TID_DEC_B_42 `PROBES5.lsu_tid_dec_b[2]
12312`define ASI_LD_42 `SPC5.lsu.lmd.lmq2_pkt[60] & (`SPC5.lsu.lmd.lmq2_pkt[49:48] == 2'b0)
12313`define ASI_42 `SPC5.lsu.lmd.lmq2_pkt[47:40]
12314`define ASI_ADDR_42 `SPC5.lsu.lmd.lmq2_pkt[39:0]
12315`define ASI_LD_DATA_42 `SPC5.lsu_exu_ld_data_b[63:0]
12316`define ASI_LD_COMP_42 tb_top.nas_top.c5.t2.complete_fw2
12317
12318//SPU specific - only one SPU per core
12319`define SPU_MA_BUSY_5 `SPC5.spu.spu_pmu_ma_busy[3]
12320`define SPU_MA_TID_5 `SPC5.spu.spu_pmu_ma_busy[2:0]
12321
12322////////////////////////////////////////////////////////////////////////////////
12323//Capture the status register data from rtl. For disrupting traps,
12324//rtl can modify the contents of the status register before the
12325//trap is taken and intp message is sent to Riesling.
12326//For precise traps, once the status register is updated rtl can't
12327//change the register again before jumping to the trap handler.
12328//So, for deferred and disrupting traps, inform Riesling when the
12329//register is modified while for precise traps wait until Fw2 before
12330//telling Riesling.
12331
12332//TLU asserts the flush and input signals in W stage. I latch them at the
12333//+ve edge of FX4.
12334
12335always @(negedge (`SPC5.l2clk & ready))
12336begin // {
12337 if (`DESR_asi_rd_42)
12338 desr_asi_rd <= 1'b1;
12339 if (desr_asi_rd)
12340 begin
12341 if (desr_wr)
12342 desr_pend_wr <= 1'b1;
12343 if (`ASI_LD_COMP_42[2])
12344 desr_asi_rd <= 1'b0;
12345 end
12346
12347 update_dsfsr_w <= (`DSFSR_NEW_IN_42 != 4'b0) && ~`ASI_WR_DSFSR_42;
12348 update_isfsr_w <= (`ISFSR_NEW_IN_42 != 3'b0) && ~`ASI_WR_ISFSR_42;
12349 desr_wr <= (`RAS_WRITE_DESR_1st_42 || `RAS_WRITE_DESR_2nd_42);
12350 update_dfesr_w <= `RAS_WRITE_FESR_42;
12351 take_err_trap_fx4 <= `ST_ERR_42 | `SW_REC_ERR_42 | `DATA_ACC_ERR_42
12352 | `INST_ACC_ERR_42 | `INT_PROC_ERR_42
12353 | `HW_CORR_ERR_42 | `INST_ACC_MMU_ERR_42
12354 | `DATA_ACC_MMU_ERR_42 ;
12355
12356
12357 if (`ST_ERR_42) int_num_fx4 <= 8'h07;
12358 if (`SW_REC_ERR_42) int_num_fx4 <= 8'h40;
12359 if (`DATA_ACC_ERR_42) int_num_fx4 <= 8'h32;
12360 if (`INST_ACC_ERR_42) int_num_fx4 <= 8'h0A;
12361 if (`INT_PROC_ERR_42) int_num_fx4 <= 8'h29;
12362 if (`HW_CORR_ERR_42) int_num_fx4 <= 8'h63;
12363 if (`INST_ACC_MMU_ERR_42) int_num_fx4 <= 8'h71;
12364 if (`DATA_ACC_MMU_ERR_42) int_num_fx4 <= 8'h72;
12365
12366 update_dsfsr_fx4 <= update_dsfsr_w;
12367 update_dsfsr_fx5 <= update_dsfsr_fx4;
12368 update_dsfsr_fb <= update_dsfsr_fx5;
12369 update_dsfsr_fw <= update_dsfsr_fb;
12370 update_dsfsr_fw1 <= update_dsfsr_fw;
12371 update_dsfsr_fw2 <= update_dsfsr_fw1;
12372
12373 update_isfsr_fx4 <= update_isfsr_w;
12374 update_isfsr_fx5 <= update_isfsr_fx4;
12375 update_isfsr_fb <= update_isfsr_fx5;
12376 update_isfsr_fw <= update_isfsr_fb;
12377 update_isfsr_fw1 <= update_isfsr_fw;
12378 update_isfsr_fw2 <= update_isfsr_fw1;
12379
12380 take_err_trap_fx5 <= take_err_trap_fx4;
12381 take_err_trap_fb <= take_err_trap_fx5;
12382 take_err_trap_fw <= take_err_trap_fb;
12383 take_err_trap_fw1 <= take_err_trap_fw;
12384 take_err_trap_fw2 <= take_err_trap_fw1;
12385
12386 int_num_fx5 <= int_num_fx4;
12387 int_num_fb <= int_num_fx5;
12388 int_num_fw <= int_num_fb;
12389 int_num_fw1 <= int_num_fw;
12390 int_num_fw2 <= int_num_fw1;
12391
12392 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
12393 begin // {
12394 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
12395 begin //{
12396 desr_pend_wr <= 1'b0;
12397 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_42[63:56], 45'b0, `DESR_42[10:0]});
12398 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_42[63:56], 45'b0, `DESR_42[10:0]});
12399 end //}
12400 //if (update_dfesr_w)
12401 if (`ST_ERR_42)
12402 begin //{
12403 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_42[61:55], 55'b0});
12404 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_42[61:55], 55'b0});
12405 end //}
12406 if (update_dsfsr_fw2)
12407 begin //{
12408 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
12409 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_42[3:0]});
12410 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_42[47:0]});
12411
12412 end //}
12413 if (update_isfsr_fw2)
12414 begin //{
12415 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
12416 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_42[2:0]});
12417 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_42[47:0]});
12418
12419 end //}
12420 if (take_err_trap_fw2)
12421 begin //{
12422 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
12423 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
12424 end // }
12425 end // }
12426
12427end //}
12428
12429//removing the addr check as the LSU doesn't flag an invalid_asi_exception
12430//if the addr of diagnostic accesses is not in the valid range. The inst.
12431//still executes. LSU expects that HP won't use addresses in invalid range.
12432
12433always @(negedge (`SPC5.l2clk & ready))
12434begin // {
12435 sync_asi = 1'b0;
12436 ld_data_w <= `ASI_LD_DATA_42;
12437
12438 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_42)
12439 chk_if_asi_ld <= 1'b1;
12440 else
12441 chk_if_asi_ld <= 1'b0;
12442
12443 if (chk_if_asi_ld & `ASI_LD_42)
12444 begin
12445 case (`ASI_42)
12446 8'h66: //ASI_IC_INSTR
12447 begin
12448 //if ((`ASI_ADDR_42 >= 0) & (`ASI_ADDR_42 <= 40'h7ff8))
12449 sync_asi = 1'b1;
12450 end
12451 8'h67: //ASI_IC_TAG
12452 begin
12453 //if ((`ASI_ADDR_42 >= 0) & (`ASI_ADDR_42 <= 40'h7fe0))
12454 sync_asi = 1'b1;
12455 end
12456 8'h46: //ASI_DC_DATA
12457 begin
12458 sync_asi = 1'b1;
12459 end
12460 8'h47: //ASI_DC_TAG
12461 begin
12462 //if ((`ASI_ADDR_42 >= 0) & (`ASI_ADDR_42 <= 40'h7ff0))
12463 sync_asi = 1'b1;
12464 end
12465 8'h48://IRF ECC
12466 begin
12467 //if ((`ASI_ADDR_42 >= 0) & (`ASI_ADDR_42 <= 40'hF8))
12468 sync_asi = 1'b1;
12469 end
12470 8'h49://FRF ECC
12471 begin
12472 //if ((`ASI_ADDR_42 >= 0) & (`ASI_ADDR_42 <= 40'hF8))
12473 sync_asi = 1'b1;
12474 end
12475 8'h4A://STB access, stb ptr can be read also
12476 begin
12477 //if ((`ASI_ADDR_42 >= 0) & (`ASI_ADDR_42 <= 40'h100))
12478 sync_asi = 1'b1;
12479 end
12480 8'h5A://Tick compare reg
12481 begin
12482 //if ((`ASI_ADDR_42 >= 0) & (`ASI_ADDR_42 <= 40'h38))
12483 sync_asi = 1'b1;
12484 end
12485 8'h5B://TSA
12486 begin
12487 //if ((`ASI_ADDR_42 >= 0) & (`ASI_ADDR_42 <= 40'h38))
12488 sync_asi = 1'b1;
12489 end
12490 8'h51://MRA
12491 begin
12492 //if ((`ASI_ADDR_42 >= 0) & (`ASI_ADDR_42 <= 40'h38))
12493 sync_asi = 1'b1;
12494 end
12495 8'h59://scratchpad ecc data read
12496 begin
12497 //if ((`ASI_ADDR_42 >= 0) & (`ASI_ADDR_42 <= 40'h38))
12498 //syncup the ecc data only. For ecc bit 6 is 0.
12499 if (~`SPC5.lsu.lmd.lmq2_pkt[6])
12500 sync_asi = 1'b1;
12501 end
12502 8'h40://cwqcsr,ma_sync access
12503 begin
12504 if ((`ASI_ADDR_42 == 40'h20) || (`ASI_ADDR_42 == 40'h30)
12505 || (`ASI_ADDR_42 == 40'h80)
12506 || ((`ASI_ADDR_42 == 40'ha0) & (`SPU_MA_BUSY_5 == 0) & (`SPU_MA_TID_5 == 2))
12507 )
12508 sync_asi = 1'b1;
12509 end
12510 8'h4C://CLESR, CLFESR access
12511 begin
12512 if ((`ASI_ADDR_42 == 40'h20) || (`ASI_ADDR_42 == 40'h28))
12513 sync_asi = 1'b1;
12514 end
12515 endcase
12516 end
12517
12518 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
12519 begin
12520 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_42, `ASI_ADDR_42, ld_data_w);
12521 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_42, {24'b0, `ASI_ADDR_42}, ld_data_w[63:0]);
12522 end
12523end //}
12524`endif
12525endmodule
12526
12527
12528
12529module err_c5t3 ();
12530`ifndef GATESIM
12531
12532`include "defines.vh"
12533
12534wire [2:0] mycid;
12535wire [2:0] mytid;
12536wire [5:0] mytnum;
12537
12538integer junk;
12539reg ready;
12540reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
12541reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
12542
12543reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
12544reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
12545
12546reg update_dfesr_w;
12547
12548reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
12549reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
12550
12551reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
12552reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
12553
12554reg sync_asi;
12555reg chk_if_asi_ld;
12556reg [63:0] ld_data_w;
12557
12558reg desr_asi_rd, desr_wr, desr_pend_wr;
12559
12560assign mycid = 5;
12561assign mytid = 3;
12562assign mytnum = 5*8 + 3;
12563
12564initial begin //{
12565 desr_asi_rd = 1'b0;
12566 desr_pend_wr = 1'b0;
12567 ready = 0;
12568 @(posedge `SPC5.l2clk) ;
12569 @(posedge `SPC5.l2clk) ;
12570 ready = `PARGS.err_sync_on;
12571end //}
12572
12573`define DSFSR_NEW_IN_43 `SPC5.tlu.ras.dsfsr_3_new_in
12574`define ISFSR_NEW_IN_43 `SPC5.tlu.ras.isfsr_3_new_in
12575
12576`define DSFSR_43 `SPC5.tlu.ras.dsfsr_3
12577`define ISFSR_43 `SPC5.tlu.ras.isfsr_3
12578`define DSFAR_43 `SPC5.tlu.dfd.dsfar_3
12579
12580`define ASI_WR_DSFSR_43 `SPC5.tlu.ras.asi_wr_dsfsr[3]
12581`define ASI_WR_ISFSR_43 `SPC5.tlu.ras.asi_wr_isfsr[3]
12582
12583`define RAS_WRITE_DESR_1st_43 `SPC5.tlu.dfd.ras_write_desr_1st[3]
12584`define RAS_WRITE_DESR_2nd_43 `SPC5.tlu.dfd.ras_write_desr_2nd[3]
12585`define DESR_asi_rd_43 `SPC5.tlu.ras_rd_desr[3]
12586`define DESR_43 `SPC5.tlu.dfd.desr_3
12587
12588`define RAS_WRITE_FESR_43 `SPC5.tlu.ras.write_fesr[3]
12589`define FESR_43 `SPC5.tlu.dfd.fesr_3
12590
12591`define ST_ERR_43 `SPC5.tlu.trl0.take_ftt & `SPC5.tlu.trl0.trap[3]
12592`define SW_REC_ERR_43 `SPC5.tlu.trl0.take_ade & `SPC5.tlu.trl0.trap[3]
12593`define DATA_ACC_ERR_43 `SPC5.tlu.trl0.take_dae & `SPC5.tlu.trl0.trap[3]
12594`define INST_ACC_ERR_43 `SPC5.tlu.trl0.take_iae & `SPC5.tlu.trl0.trap[3]
12595`define INT_PROC_ERR_43 `SPC5.tlu.trl0.take_ipe & `SPC5.tlu.trl0.trap[3]
12596`define HW_CORR_ERR_43 `SPC5.tlu.trl0.take_eer & `SPC5.tlu.trl0.trap[3]
12597`define INST_ACC_MMU_ERR_43 `SPC5.tlu.trl0.take_ime & `SPC5.tlu.trl0.trap[3]
12598`define DATA_ACC_MMU_ERR_43 `SPC5.tlu.trl0.take_dme & `SPC5.tlu.trl0.trap[3]
12599
12600`define LSU_LD_VALID_B `PROBES5.lsu_ld_valid
12601`define LSU_TID_DEC_B_43 `PROBES5.lsu_tid_dec_b[3]
12602`define ASI_LD_43 `SPC5.lsu.lmd.lmq3_pkt[60] & (`SPC5.lsu.lmd.lmq3_pkt[49:48] == 2'b0)
12603`define ASI_43 `SPC5.lsu.lmd.lmq3_pkt[47:40]
12604`define ASI_ADDR_43 `SPC5.lsu.lmd.lmq3_pkt[39:0]
12605`define ASI_LD_DATA_43 `SPC5.lsu_exu_ld_data_b[63:0]
12606`define ASI_LD_COMP_43 tb_top.nas_top.c5.t3.complete_fw2
12607
12608//SPU specific - only one SPU per core
12609`define SPU_MA_BUSY_5 `SPC5.spu.spu_pmu_ma_busy[3]
12610`define SPU_MA_TID_5 `SPC5.spu.spu_pmu_ma_busy[2:0]
12611
12612////////////////////////////////////////////////////////////////////////////////
12613//Capture the status register data from rtl. For disrupting traps,
12614//rtl can modify the contents of the status register before the
12615//trap is taken and intp message is sent to Riesling.
12616//For precise traps, once the status register is updated rtl can't
12617//change the register again before jumping to the trap handler.
12618//So, for deferred and disrupting traps, inform Riesling when the
12619//register is modified while for precise traps wait until Fw2 before
12620//telling Riesling.
12621
12622//TLU asserts the flush and input signals in W stage. I latch them at the
12623//+ve edge of FX4.
12624
12625always @(negedge (`SPC5.l2clk & ready))
12626begin // {
12627 if (`DESR_asi_rd_43)
12628 desr_asi_rd <= 1'b1;
12629 if (desr_asi_rd)
12630 begin
12631 if (desr_wr)
12632 desr_pend_wr <= 1'b1;
12633 if (`ASI_LD_COMP_43[2])
12634 desr_asi_rd <= 1'b0;
12635 end
12636
12637 update_dsfsr_w <= (`DSFSR_NEW_IN_43 != 4'b0) && ~`ASI_WR_DSFSR_43;
12638 update_isfsr_w <= (`ISFSR_NEW_IN_43 != 3'b0) && ~`ASI_WR_ISFSR_43;
12639 desr_wr <= (`RAS_WRITE_DESR_1st_43 || `RAS_WRITE_DESR_2nd_43);
12640 update_dfesr_w <= `RAS_WRITE_FESR_43;
12641 take_err_trap_fx4 <= `ST_ERR_43 | `SW_REC_ERR_43 | `DATA_ACC_ERR_43
12642 | `INST_ACC_ERR_43 | `INT_PROC_ERR_43
12643 | `HW_CORR_ERR_43 | `INST_ACC_MMU_ERR_43
12644 | `DATA_ACC_MMU_ERR_43 ;
12645
12646
12647 if (`ST_ERR_43) int_num_fx4 <= 8'h07;
12648 if (`SW_REC_ERR_43) int_num_fx4 <= 8'h40;
12649 if (`DATA_ACC_ERR_43) int_num_fx4 <= 8'h32;
12650 if (`INST_ACC_ERR_43) int_num_fx4 <= 8'h0A;
12651 if (`INT_PROC_ERR_43) int_num_fx4 <= 8'h29;
12652 if (`HW_CORR_ERR_43) int_num_fx4 <= 8'h63;
12653 if (`INST_ACC_MMU_ERR_43) int_num_fx4 <= 8'h71;
12654 if (`DATA_ACC_MMU_ERR_43) int_num_fx4 <= 8'h72;
12655
12656 update_dsfsr_fx4 <= update_dsfsr_w;
12657 update_dsfsr_fx5 <= update_dsfsr_fx4;
12658 update_dsfsr_fb <= update_dsfsr_fx5;
12659 update_dsfsr_fw <= update_dsfsr_fb;
12660 update_dsfsr_fw1 <= update_dsfsr_fw;
12661 update_dsfsr_fw2 <= update_dsfsr_fw1;
12662
12663 update_isfsr_fx4 <= update_isfsr_w;
12664 update_isfsr_fx5 <= update_isfsr_fx4;
12665 update_isfsr_fb <= update_isfsr_fx5;
12666 update_isfsr_fw <= update_isfsr_fb;
12667 update_isfsr_fw1 <= update_isfsr_fw;
12668 update_isfsr_fw2 <= update_isfsr_fw1;
12669
12670 take_err_trap_fx5 <= take_err_trap_fx4;
12671 take_err_trap_fb <= take_err_trap_fx5;
12672 take_err_trap_fw <= take_err_trap_fb;
12673 take_err_trap_fw1 <= take_err_trap_fw;
12674 take_err_trap_fw2 <= take_err_trap_fw1;
12675
12676 int_num_fx5 <= int_num_fx4;
12677 int_num_fb <= int_num_fx5;
12678 int_num_fw <= int_num_fb;
12679 int_num_fw1 <= int_num_fw;
12680 int_num_fw2 <= int_num_fw1;
12681
12682 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
12683 begin // {
12684 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
12685 begin //{
12686 desr_pend_wr <= 1'b0;
12687 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_43[63:56], 45'b0, `DESR_43[10:0]});
12688 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_43[63:56], 45'b0, `DESR_43[10:0]});
12689 end //}
12690 //if (update_dfesr_w)
12691 if (`ST_ERR_43)
12692 begin //{
12693 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_43[61:55], 55'b0});
12694 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_43[61:55], 55'b0});
12695 end //}
12696 if (update_dsfsr_fw2)
12697 begin //{
12698 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
12699 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_43[3:0]});
12700 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_43[47:0]});
12701
12702 end //}
12703 if (update_isfsr_fw2)
12704 begin //{
12705 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
12706 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_43[2:0]});
12707 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_43[47:0]});
12708
12709 end //}
12710 if (take_err_trap_fw2)
12711 begin //{
12712 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
12713 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
12714 end // }
12715 end // }
12716
12717end //}
12718
12719//removing the addr check as the LSU doesn't flag an invalid_asi_exception
12720//if the addr of diagnostic accesses is not in the valid range. The inst.
12721//still executes. LSU expects that HP won't use addresses in invalid range.
12722
12723always @(negedge (`SPC5.l2clk & ready))
12724begin // {
12725 sync_asi = 1'b0;
12726 ld_data_w <= `ASI_LD_DATA_43;
12727
12728 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_43)
12729 chk_if_asi_ld <= 1'b1;
12730 else
12731 chk_if_asi_ld <= 1'b0;
12732
12733 if (chk_if_asi_ld & `ASI_LD_43)
12734 begin
12735 case (`ASI_43)
12736 8'h66: //ASI_IC_INSTR
12737 begin
12738 //if ((`ASI_ADDR_43 >= 0) & (`ASI_ADDR_43 <= 40'h7ff8))
12739 sync_asi = 1'b1;
12740 end
12741 8'h67: //ASI_IC_TAG
12742 begin
12743 //if ((`ASI_ADDR_43 >= 0) & (`ASI_ADDR_43 <= 40'h7fe0))
12744 sync_asi = 1'b1;
12745 end
12746 8'h46: //ASI_DC_DATA
12747 begin
12748 sync_asi = 1'b1;
12749 end
12750 8'h47: //ASI_DC_TAG
12751 begin
12752 //if ((`ASI_ADDR_43 >= 0) & (`ASI_ADDR_43 <= 40'h7ff0))
12753 sync_asi = 1'b1;
12754 end
12755 8'h48://IRF ECC
12756 begin
12757 //if ((`ASI_ADDR_43 >= 0) & (`ASI_ADDR_43 <= 40'hF8))
12758 sync_asi = 1'b1;
12759 end
12760 8'h49://FRF ECC
12761 begin
12762 //if ((`ASI_ADDR_43 >= 0) & (`ASI_ADDR_43 <= 40'hF8))
12763 sync_asi = 1'b1;
12764 end
12765 8'h4A://STB access, stb ptr can be read also
12766 begin
12767 //if ((`ASI_ADDR_43 >= 0) & (`ASI_ADDR_43 <= 40'h100))
12768 sync_asi = 1'b1;
12769 end
12770 8'h5A://Tick compare reg
12771 begin
12772 //if ((`ASI_ADDR_43 >= 0) & (`ASI_ADDR_43 <= 40'h38))
12773 sync_asi = 1'b1;
12774 end
12775 8'h5B://TSA
12776 begin
12777 //if ((`ASI_ADDR_43 >= 0) & (`ASI_ADDR_43 <= 40'h38))
12778 sync_asi = 1'b1;
12779 end
12780 8'h51://MRA
12781 begin
12782 //if ((`ASI_ADDR_43 >= 0) & (`ASI_ADDR_43 <= 40'h38))
12783 sync_asi = 1'b1;
12784 end
12785 8'h59://scratchpad ecc data read
12786 begin
12787 //if ((`ASI_ADDR_43 >= 0) & (`ASI_ADDR_43 <= 40'h38))
12788 //syncup the ecc data only. For ecc bit 6 is 0.
12789 if (~`SPC5.lsu.lmd.lmq3_pkt[6])
12790 sync_asi = 1'b1;
12791 end
12792 8'h40://cwqcsr,ma_sync access
12793 begin
12794 if ((`ASI_ADDR_43 == 40'h20) || (`ASI_ADDR_43 == 40'h30)
12795 || (`ASI_ADDR_43 == 40'h80)
12796 || ((`ASI_ADDR_43 == 40'ha0) & (`SPU_MA_BUSY_5 == 0) & (`SPU_MA_TID_5 == 3))
12797 )
12798 sync_asi = 1'b1;
12799 end
12800 8'h4C://CLESR, CLFESR access
12801 begin
12802 if ((`ASI_ADDR_43 == 40'h20) || (`ASI_ADDR_43 == 40'h28))
12803 sync_asi = 1'b1;
12804 end
12805 endcase
12806 end
12807
12808 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
12809 begin
12810 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_43, `ASI_ADDR_43, ld_data_w);
12811 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_43, {24'b0, `ASI_ADDR_43}, ld_data_w[63:0]);
12812 end
12813end //}
12814`endif
12815endmodule
12816
12817
12818
12819module err_c5t4 ();
12820`ifndef GATESIM
12821
12822`include "defines.vh"
12823
12824wire [2:0] mycid;
12825wire [2:0] mytid;
12826wire [5:0] mytnum;
12827
12828integer junk;
12829reg ready;
12830reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
12831reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
12832
12833reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
12834reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
12835
12836reg update_dfesr_w;
12837
12838reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
12839reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
12840
12841reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
12842reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
12843
12844reg sync_asi;
12845reg chk_if_asi_ld;
12846reg [63:0] ld_data_w;
12847
12848reg desr_asi_rd, desr_wr, desr_pend_wr;
12849
12850assign mycid = 5;
12851assign mytid = 4;
12852assign mytnum = 5*8 + 4;
12853
12854initial begin //{
12855 desr_asi_rd = 1'b0;
12856 desr_pend_wr = 1'b0;
12857 ready = 0;
12858 @(posedge `SPC5.l2clk) ;
12859 @(posedge `SPC5.l2clk) ;
12860 ready = `PARGS.err_sync_on;
12861end //}
12862
12863`define DSFSR_NEW_IN_44 `SPC5.tlu.ras.dsfsr_4_new_in
12864`define ISFSR_NEW_IN_44 `SPC5.tlu.ras.isfsr_4_new_in
12865
12866`define DSFSR_44 `SPC5.tlu.ras.dsfsr_4
12867`define ISFSR_44 `SPC5.tlu.ras.isfsr_4
12868`define DSFAR_44 `SPC5.tlu.dfd.dsfar_4
12869
12870`define ASI_WR_DSFSR_44 `SPC5.tlu.ras.asi_wr_dsfsr[4]
12871`define ASI_WR_ISFSR_44 `SPC5.tlu.ras.asi_wr_isfsr[4]
12872
12873`define RAS_WRITE_DESR_1st_44 `SPC5.tlu.dfd.ras_write_desr_1st[4]
12874`define RAS_WRITE_DESR_2nd_44 `SPC5.tlu.dfd.ras_write_desr_2nd[4]
12875`define DESR_asi_rd_44 `SPC5.tlu.ras_rd_desr[4]
12876`define DESR_44 `SPC5.tlu.dfd.desr_4
12877
12878`define RAS_WRITE_FESR_44 `SPC5.tlu.ras.write_fesr[4]
12879`define FESR_44 `SPC5.tlu.dfd.fesr_4
12880
12881`define ST_ERR_44 `SPC5.tlu.trl1.take_ftt & `SPC5.tlu.trl1.trap[0]
12882`define SW_REC_ERR_44 `SPC5.tlu.trl1.take_ade & `SPC5.tlu.trl1.trap[0]
12883`define DATA_ACC_ERR_44 `SPC5.tlu.trl1.take_dae & `SPC5.tlu.trl1.trap[0]
12884`define INST_ACC_ERR_44 `SPC5.tlu.trl1.take_iae & `SPC5.tlu.trl1.trap[0]
12885`define INT_PROC_ERR_44 `SPC5.tlu.trl1.take_ipe & `SPC5.tlu.trl1.trap[0]
12886`define HW_CORR_ERR_44 `SPC5.tlu.trl1.take_eer & `SPC5.tlu.trl1.trap[0]
12887`define INST_ACC_MMU_ERR_44 `SPC5.tlu.trl1.take_ime & `SPC5.tlu.trl1.trap[0]
12888`define DATA_ACC_MMU_ERR_44 `SPC5.tlu.trl1.take_dme & `SPC5.tlu.trl1.trap[0]
12889
12890`define LSU_LD_VALID_B `PROBES5.lsu_ld_valid
12891`define LSU_TID_DEC_B_44 `PROBES5.lsu_tid_dec_b[4]
12892`define ASI_LD_44 `SPC5.lsu.lmd.lmq4_pkt[60] & (`SPC5.lsu.lmd.lmq4_pkt[49:48] == 2'b0)
12893`define ASI_44 `SPC5.lsu.lmd.lmq4_pkt[47:40]
12894`define ASI_ADDR_44 `SPC5.lsu.lmd.lmq4_pkt[39:0]
12895`define ASI_LD_DATA_44 `SPC5.lsu_exu_ld_data_b[63:0]
12896`define ASI_LD_COMP_44 tb_top.nas_top.c5.t4.complete_fw2
12897
12898//SPU specific - only one SPU per core
12899`define SPU_MA_BUSY_5 `SPC5.spu.spu_pmu_ma_busy[3]
12900`define SPU_MA_TID_5 `SPC5.spu.spu_pmu_ma_busy[2:0]
12901
12902////////////////////////////////////////////////////////////////////////////////
12903//Capture the status register data from rtl. For disrupting traps,
12904//rtl can modify the contents of the status register before the
12905//trap is taken and intp message is sent to Riesling.
12906//For precise traps, once the status register is updated rtl can't
12907//change the register again before jumping to the trap handler.
12908//So, for deferred and disrupting traps, inform Riesling when the
12909//register is modified while for precise traps wait until Fw2 before
12910//telling Riesling.
12911
12912//TLU asserts the flush and input signals in W stage. I latch them at the
12913//+ve edge of FX4.
12914
12915always @(negedge (`SPC5.l2clk & ready))
12916begin // {
12917 if (`DESR_asi_rd_44)
12918 desr_asi_rd <= 1'b1;
12919 if (desr_asi_rd)
12920 begin
12921 if (desr_wr)
12922 desr_pend_wr <= 1'b1;
12923 if (`ASI_LD_COMP_44[2])
12924 desr_asi_rd <= 1'b0;
12925 end
12926
12927 update_dsfsr_w <= (`DSFSR_NEW_IN_44 != 4'b0) && ~`ASI_WR_DSFSR_44;
12928 update_isfsr_w <= (`ISFSR_NEW_IN_44 != 3'b0) && ~`ASI_WR_ISFSR_44;
12929 desr_wr <= (`RAS_WRITE_DESR_1st_44 || `RAS_WRITE_DESR_2nd_44);
12930 update_dfesr_w <= `RAS_WRITE_FESR_44;
12931 take_err_trap_fx4 <= `ST_ERR_44 | `SW_REC_ERR_44 | `DATA_ACC_ERR_44
12932 | `INST_ACC_ERR_44 | `INT_PROC_ERR_44
12933 | `HW_CORR_ERR_44 | `INST_ACC_MMU_ERR_44
12934 | `DATA_ACC_MMU_ERR_44 ;
12935
12936
12937 if (`ST_ERR_44) int_num_fx4 <= 8'h07;
12938 if (`SW_REC_ERR_44) int_num_fx4 <= 8'h40;
12939 if (`DATA_ACC_ERR_44) int_num_fx4 <= 8'h32;
12940 if (`INST_ACC_ERR_44) int_num_fx4 <= 8'h0A;
12941 if (`INT_PROC_ERR_44) int_num_fx4 <= 8'h29;
12942 if (`HW_CORR_ERR_44) int_num_fx4 <= 8'h63;
12943 if (`INST_ACC_MMU_ERR_44) int_num_fx4 <= 8'h71;
12944 if (`DATA_ACC_MMU_ERR_44) int_num_fx4 <= 8'h72;
12945
12946 update_dsfsr_fx4 <= update_dsfsr_w;
12947 update_dsfsr_fx5 <= update_dsfsr_fx4;
12948 update_dsfsr_fb <= update_dsfsr_fx5;
12949 update_dsfsr_fw <= update_dsfsr_fb;
12950 update_dsfsr_fw1 <= update_dsfsr_fw;
12951 update_dsfsr_fw2 <= update_dsfsr_fw1;
12952
12953 update_isfsr_fx4 <= update_isfsr_w;
12954 update_isfsr_fx5 <= update_isfsr_fx4;
12955 update_isfsr_fb <= update_isfsr_fx5;
12956 update_isfsr_fw <= update_isfsr_fb;
12957 update_isfsr_fw1 <= update_isfsr_fw;
12958 update_isfsr_fw2 <= update_isfsr_fw1;
12959
12960 take_err_trap_fx5 <= take_err_trap_fx4;
12961 take_err_trap_fb <= take_err_trap_fx5;
12962 take_err_trap_fw <= take_err_trap_fb;
12963 take_err_trap_fw1 <= take_err_trap_fw;
12964 take_err_trap_fw2 <= take_err_trap_fw1;
12965
12966 int_num_fx5 <= int_num_fx4;
12967 int_num_fb <= int_num_fx5;
12968 int_num_fw <= int_num_fb;
12969 int_num_fw1 <= int_num_fw;
12970 int_num_fw2 <= int_num_fw1;
12971
12972 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
12973 begin // {
12974 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
12975 begin //{
12976 desr_pend_wr <= 1'b0;
12977 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_44[63:56], 45'b0, `DESR_44[10:0]});
12978 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_44[63:56], 45'b0, `DESR_44[10:0]});
12979 end //}
12980 //if (update_dfesr_w)
12981 if (`ST_ERR_44)
12982 begin //{
12983 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_44[61:55], 55'b0});
12984 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_44[61:55], 55'b0});
12985 end //}
12986 if (update_dsfsr_fw2)
12987 begin //{
12988 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
12989 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_44[3:0]});
12990 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_44[47:0]});
12991
12992 end //}
12993 if (update_isfsr_fw2)
12994 begin //{
12995 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
12996 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_44[2:0]});
12997 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_44[47:0]});
12998
12999 end //}
13000 if (take_err_trap_fw2)
13001 begin //{
13002 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
13003 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
13004 end // }
13005 end // }
13006
13007end //}
13008
13009//removing the addr check as the LSU doesn't flag an invalid_asi_exception
13010//if the addr of diagnostic accesses is not in the valid range. The inst.
13011//still executes. LSU expects that HP won't use addresses in invalid range.
13012
13013always @(negedge (`SPC5.l2clk & ready))
13014begin // {
13015 sync_asi = 1'b0;
13016 ld_data_w <= `ASI_LD_DATA_44;
13017
13018 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_44)
13019 chk_if_asi_ld <= 1'b1;
13020 else
13021 chk_if_asi_ld <= 1'b0;
13022
13023 if (chk_if_asi_ld & `ASI_LD_44)
13024 begin
13025 case (`ASI_44)
13026 8'h66: //ASI_IC_INSTR
13027 begin
13028 //if ((`ASI_ADDR_44 >= 0) & (`ASI_ADDR_44 <= 40'h7ff8))
13029 sync_asi = 1'b1;
13030 end
13031 8'h67: //ASI_IC_TAG
13032 begin
13033 //if ((`ASI_ADDR_44 >= 0) & (`ASI_ADDR_44 <= 40'h7fe0))
13034 sync_asi = 1'b1;
13035 end
13036 8'h46: //ASI_DC_DATA
13037 begin
13038 sync_asi = 1'b1;
13039 end
13040 8'h47: //ASI_DC_TAG
13041 begin
13042 //if ((`ASI_ADDR_44 >= 0) & (`ASI_ADDR_44 <= 40'h7ff0))
13043 sync_asi = 1'b1;
13044 end
13045 8'h48://IRF ECC
13046 begin
13047 //if ((`ASI_ADDR_44 >= 0) & (`ASI_ADDR_44 <= 40'hF8))
13048 sync_asi = 1'b1;
13049 end
13050 8'h49://FRF ECC
13051 begin
13052 //if ((`ASI_ADDR_44 >= 0) & (`ASI_ADDR_44 <= 40'hF8))
13053 sync_asi = 1'b1;
13054 end
13055 8'h4A://STB access, stb ptr can be read also
13056 begin
13057 //if ((`ASI_ADDR_44 >= 0) & (`ASI_ADDR_44 <= 40'h100))
13058 sync_asi = 1'b1;
13059 end
13060 8'h5A://Tick compare reg
13061 begin
13062 //if ((`ASI_ADDR_44 >= 0) & (`ASI_ADDR_44 <= 40'h38))
13063 sync_asi = 1'b1;
13064 end
13065 8'h5B://TSA
13066 begin
13067 //if ((`ASI_ADDR_44 >= 0) & (`ASI_ADDR_44 <= 40'h38))
13068 sync_asi = 1'b1;
13069 end
13070 8'h51://MRA
13071 begin
13072 //if ((`ASI_ADDR_44 >= 0) & (`ASI_ADDR_44 <= 40'h38))
13073 sync_asi = 1'b1;
13074 end
13075 8'h59://scratchpad ecc data read
13076 begin
13077 //if ((`ASI_ADDR_44 >= 0) & (`ASI_ADDR_44 <= 40'h38))
13078 //syncup the ecc data only. For ecc bit 6 is 0.
13079 if (~`SPC5.lsu.lmd.lmq4_pkt[6])
13080 sync_asi = 1'b1;
13081 end
13082 8'h40://cwqcsr,ma_sync access
13083 begin
13084 if ((`ASI_ADDR_44 == 40'h20) || (`ASI_ADDR_44 == 40'h30)
13085 || (`ASI_ADDR_44 == 40'h80)
13086 || ((`ASI_ADDR_44 == 40'ha0) & (`SPU_MA_BUSY_5 == 0) & (`SPU_MA_TID_5 == 4))
13087 )
13088 sync_asi = 1'b1;
13089 end
13090 8'h4C://CLESR, CLFESR access
13091 begin
13092 if ((`ASI_ADDR_44 == 40'h20) || (`ASI_ADDR_44 == 40'h28))
13093 sync_asi = 1'b1;
13094 end
13095 endcase
13096 end
13097
13098 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
13099 begin
13100 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_44, `ASI_ADDR_44, ld_data_w);
13101 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_44, {24'b0, `ASI_ADDR_44}, ld_data_w[63:0]);
13102 end
13103end //}
13104`endif
13105endmodule
13106
13107
13108
13109module err_c5t5 ();
13110`ifndef GATESIM
13111
13112`include "defines.vh"
13113
13114wire [2:0] mycid;
13115wire [2:0] mytid;
13116wire [5:0] mytnum;
13117
13118integer junk;
13119reg ready;
13120reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
13121reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
13122
13123reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
13124reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
13125
13126reg update_dfesr_w;
13127
13128reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
13129reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
13130
13131reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
13132reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
13133
13134reg sync_asi;
13135reg chk_if_asi_ld;
13136reg [63:0] ld_data_w;
13137
13138reg desr_asi_rd, desr_wr, desr_pend_wr;
13139
13140assign mycid = 5;
13141assign mytid = 5;
13142assign mytnum = 5*8 + 5;
13143
13144initial begin //{
13145 desr_asi_rd = 1'b0;
13146 desr_pend_wr = 1'b0;
13147 ready = 0;
13148 @(posedge `SPC5.l2clk) ;
13149 @(posedge `SPC5.l2clk) ;
13150 ready = `PARGS.err_sync_on;
13151end //}
13152
13153`define DSFSR_NEW_IN_45 `SPC5.tlu.ras.dsfsr_5_new_in
13154`define ISFSR_NEW_IN_45 `SPC5.tlu.ras.isfsr_5_new_in
13155
13156`define DSFSR_45 `SPC5.tlu.ras.dsfsr_5
13157`define ISFSR_45 `SPC5.tlu.ras.isfsr_5
13158`define DSFAR_45 `SPC5.tlu.dfd.dsfar_5
13159
13160`define ASI_WR_DSFSR_45 `SPC5.tlu.ras.asi_wr_dsfsr[5]
13161`define ASI_WR_ISFSR_45 `SPC5.tlu.ras.asi_wr_isfsr[5]
13162
13163`define RAS_WRITE_DESR_1st_45 `SPC5.tlu.dfd.ras_write_desr_1st[5]
13164`define RAS_WRITE_DESR_2nd_45 `SPC5.tlu.dfd.ras_write_desr_2nd[5]
13165`define DESR_asi_rd_45 `SPC5.tlu.ras_rd_desr[5]
13166`define DESR_45 `SPC5.tlu.dfd.desr_5
13167
13168`define RAS_WRITE_FESR_45 `SPC5.tlu.ras.write_fesr[5]
13169`define FESR_45 `SPC5.tlu.dfd.fesr_5
13170
13171`define ST_ERR_45 `SPC5.tlu.trl1.take_ftt & `SPC5.tlu.trl1.trap[1]
13172`define SW_REC_ERR_45 `SPC5.tlu.trl1.take_ade & `SPC5.tlu.trl1.trap[1]
13173`define DATA_ACC_ERR_45 `SPC5.tlu.trl1.take_dae & `SPC5.tlu.trl1.trap[1]
13174`define INST_ACC_ERR_45 `SPC5.tlu.trl1.take_iae & `SPC5.tlu.trl1.trap[1]
13175`define INT_PROC_ERR_45 `SPC5.tlu.trl1.take_ipe & `SPC5.tlu.trl1.trap[1]
13176`define HW_CORR_ERR_45 `SPC5.tlu.trl1.take_eer & `SPC5.tlu.trl1.trap[1]
13177`define INST_ACC_MMU_ERR_45 `SPC5.tlu.trl1.take_ime & `SPC5.tlu.trl1.trap[1]
13178`define DATA_ACC_MMU_ERR_45 `SPC5.tlu.trl1.take_dme & `SPC5.tlu.trl1.trap[1]
13179
13180`define LSU_LD_VALID_B `PROBES5.lsu_ld_valid
13181`define LSU_TID_DEC_B_45 `PROBES5.lsu_tid_dec_b[5]
13182`define ASI_LD_45 `SPC5.lsu.lmd.lmq5_pkt[60] & (`SPC5.lsu.lmd.lmq5_pkt[49:48] == 2'b0)
13183`define ASI_45 `SPC5.lsu.lmd.lmq5_pkt[47:40]
13184`define ASI_ADDR_45 `SPC5.lsu.lmd.lmq5_pkt[39:0]
13185`define ASI_LD_DATA_45 `SPC5.lsu_exu_ld_data_b[63:0]
13186`define ASI_LD_COMP_45 tb_top.nas_top.c5.t5.complete_fw2
13187
13188//SPU specific - only one SPU per core
13189`define SPU_MA_BUSY_5 `SPC5.spu.spu_pmu_ma_busy[3]
13190`define SPU_MA_TID_5 `SPC5.spu.spu_pmu_ma_busy[2:0]
13191
13192////////////////////////////////////////////////////////////////////////////////
13193//Capture the status register data from rtl. For disrupting traps,
13194//rtl can modify the contents of the status register before the
13195//trap is taken and intp message is sent to Riesling.
13196//For precise traps, once the status register is updated rtl can't
13197//change the register again before jumping to the trap handler.
13198//So, for deferred and disrupting traps, inform Riesling when the
13199//register is modified while for precise traps wait until Fw2 before
13200//telling Riesling.
13201
13202//TLU asserts the flush and input signals in W stage. I latch them at the
13203//+ve edge of FX4.
13204
13205always @(negedge (`SPC5.l2clk & ready))
13206begin // {
13207 if (`DESR_asi_rd_45)
13208 desr_asi_rd <= 1'b1;
13209 if (desr_asi_rd)
13210 begin
13211 if (desr_wr)
13212 desr_pend_wr <= 1'b1;
13213 if (`ASI_LD_COMP_45[2])
13214 desr_asi_rd <= 1'b0;
13215 end
13216
13217 update_dsfsr_w <= (`DSFSR_NEW_IN_45 != 4'b0) && ~`ASI_WR_DSFSR_45;
13218 update_isfsr_w <= (`ISFSR_NEW_IN_45 != 3'b0) && ~`ASI_WR_ISFSR_45;
13219 desr_wr <= (`RAS_WRITE_DESR_1st_45 || `RAS_WRITE_DESR_2nd_45);
13220 update_dfesr_w <= `RAS_WRITE_FESR_45;
13221 take_err_trap_fx4 <= `ST_ERR_45 | `SW_REC_ERR_45 | `DATA_ACC_ERR_45
13222 | `INST_ACC_ERR_45 | `INT_PROC_ERR_45
13223 | `HW_CORR_ERR_45 | `INST_ACC_MMU_ERR_45
13224 | `DATA_ACC_MMU_ERR_45 ;
13225
13226
13227 if (`ST_ERR_45) int_num_fx4 <= 8'h07;
13228 if (`SW_REC_ERR_45) int_num_fx4 <= 8'h40;
13229 if (`DATA_ACC_ERR_45) int_num_fx4 <= 8'h32;
13230 if (`INST_ACC_ERR_45) int_num_fx4 <= 8'h0A;
13231 if (`INT_PROC_ERR_45) int_num_fx4 <= 8'h29;
13232 if (`HW_CORR_ERR_45) int_num_fx4 <= 8'h63;
13233 if (`INST_ACC_MMU_ERR_45) int_num_fx4 <= 8'h71;
13234 if (`DATA_ACC_MMU_ERR_45) int_num_fx4 <= 8'h72;
13235
13236 update_dsfsr_fx4 <= update_dsfsr_w;
13237 update_dsfsr_fx5 <= update_dsfsr_fx4;
13238 update_dsfsr_fb <= update_dsfsr_fx5;
13239 update_dsfsr_fw <= update_dsfsr_fb;
13240 update_dsfsr_fw1 <= update_dsfsr_fw;
13241 update_dsfsr_fw2 <= update_dsfsr_fw1;
13242
13243 update_isfsr_fx4 <= update_isfsr_w;
13244 update_isfsr_fx5 <= update_isfsr_fx4;
13245 update_isfsr_fb <= update_isfsr_fx5;
13246 update_isfsr_fw <= update_isfsr_fb;
13247 update_isfsr_fw1 <= update_isfsr_fw;
13248 update_isfsr_fw2 <= update_isfsr_fw1;
13249
13250 take_err_trap_fx5 <= take_err_trap_fx4;
13251 take_err_trap_fb <= take_err_trap_fx5;
13252 take_err_trap_fw <= take_err_trap_fb;
13253 take_err_trap_fw1 <= take_err_trap_fw;
13254 take_err_trap_fw2 <= take_err_trap_fw1;
13255
13256 int_num_fx5 <= int_num_fx4;
13257 int_num_fb <= int_num_fx5;
13258 int_num_fw <= int_num_fb;
13259 int_num_fw1 <= int_num_fw;
13260 int_num_fw2 <= int_num_fw1;
13261
13262 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
13263 begin // {
13264 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
13265 begin //{
13266 desr_pend_wr <= 1'b0;
13267 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_45[63:56], 45'b0, `DESR_45[10:0]});
13268 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_45[63:56], 45'b0, `DESR_45[10:0]});
13269 end //}
13270 //if (update_dfesr_w)
13271 if (`ST_ERR_45)
13272 begin //{
13273 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_45[61:55], 55'b0});
13274 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_45[61:55], 55'b0});
13275 end //}
13276 if (update_dsfsr_fw2)
13277 begin //{
13278 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
13279 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_45[3:0]});
13280 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_45[47:0]});
13281
13282 end //}
13283 if (update_isfsr_fw2)
13284 begin //{
13285 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
13286 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_45[2:0]});
13287 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_45[47:0]});
13288
13289 end //}
13290 if (take_err_trap_fw2)
13291 begin //{
13292 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
13293 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
13294 end // }
13295 end // }
13296
13297end //}
13298
13299//removing the addr check as the LSU doesn't flag an invalid_asi_exception
13300//if the addr of diagnostic accesses is not in the valid range. The inst.
13301//still executes. LSU expects that HP won't use addresses in invalid range.
13302
13303always @(negedge (`SPC5.l2clk & ready))
13304begin // {
13305 sync_asi = 1'b0;
13306 ld_data_w <= `ASI_LD_DATA_45;
13307
13308 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_45)
13309 chk_if_asi_ld <= 1'b1;
13310 else
13311 chk_if_asi_ld <= 1'b0;
13312
13313 if (chk_if_asi_ld & `ASI_LD_45)
13314 begin
13315 case (`ASI_45)
13316 8'h66: //ASI_IC_INSTR
13317 begin
13318 //if ((`ASI_ADDR_45 >= 0) & (`ASI_ADDR_45 <= 40'h7ff8))
13319 sync_asi = 1'b1;
13320 end
13321 8'h67: //ASI_IC_TAG
13322 begin
13323 //if ((`ASI_ADDR_45 >= 0) & (`ASI_ADDR_45 <= 40'h7fe0))
13324 sync_asi = 1'b1;
13325 end
13326 8'h46: //ASI_DC_DATA
13327 begin
13328 sync_asi = 1'b1;
13329 end
13330 8'h47: //ASI_DC_TAG
13331 begin
13332 //if ((`ASI_ADDR_45 >= 0) & (`ASI_ADDR_45 <= 40'h7ff0))
13333 sync_asi = 1'b1;
13334 end
13335 8'h48://IRF ECC
13336 begin
13337 //if ((`ASI_ADDR_45 >= 0) & (`ASI_ADDR_45 <= 40'hF8))
13338 sync_asi = 1'b1;
13339 end
13340 8'h49://FRF ECC
13341 begin
13342 //if ((`ASI_ADDR_45 >= 0) & (`ASI_ADDR_45 <= 40'hF8))
13343 sync_asi = 1'b1;
13344 end
13345 8'h4A://STB access, stb ptr can be read also
13346 begin
13347 //if ((`ASI_ADDR_45 >= 0) & (`ASI_ADDR_45 <= 40'h100))
13348 sync_asi = 1'b1;
13349 end
13350 8'h5A://Tick compare reg
13351 begin
13352 //if ((`ASI_ADDR_45 >= 0) & (`ASI_ADDR_45 <= 40'h38))
13353 sync_asi = 1'b1;
13354 end
13355 8'h5B://TSA
13356 begin
13357 //if ((`ASI_ADDR_45 >= 0) & (`ASI_ADDR_45 <= 40'h38))
13358 sync_asi = 1'b1;
13359 end
13360 8'h51://MRA
13361 begin
13362 //if ((`ASI_ADDR_45 >= 0) & (`ASI_ADDR_45 <= 40'h38))
13363 sync_asi = 1'b1;
13364 end
13365 8'h59://scratchpad ecc data read
13366 begin
13367 //if ((`ASI_ADDR_45 >= 0) & (`ASI_ADDR_45 <= 40'h38))
13368 //syncup the ecc data only. For ecc bit 6 is 0.
13369 if (~`SPC5.lsu.lmd.lmq5_pkt[6])
13370 sync_asi = 1'b1;
13371 end
13372 8'h40://cwqcsr,ma_sync access
13373 begin
13374 if ((`ASI_ADDR_45 == 40'h20) || (`ASI_ADDR_45 == 40'h30)
13375 || (`ASI_ADDR_45 == 40'h80)
13376 || ((`ASI_ADDR_45 == 40'ha0) & (`SPU_MA_BUSY_5 == 0) & (`SPU_MA_TID_5 == 5))
13377 )
13378 sync_asi = 1'b1;
13379 end
13380 8'h4C://CLESR, CLFESR access
13381 begin
13382 if ((`ASI_ADDR_45 == 40'h20) || (`ASI_ADDR_45 == 40'h28))
13383 sync_asi = 1'b1;
13384 end
13385 endcase
13386 end
13387
13388 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
13389 begin
13390 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_45, `ASI_ADDR_45, ld_data_w);
13391 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_45, {24'b0, `ASI_ADDR_45}, ld_data_w[63:0]);
13392 end
13393end //}
13394`endif
13395endmodule
13396
13397
13398
13399module err_c5t6 ();
13400`ifndef GATESIM
13401
13402`include "defines.vh"
13403
13404wire [2:0] mycid;
13405wire [2:0] mytid;
13406wire [5:0] mytnum;
13407
13408integer junk;
13409reg ready;
13410reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
13411reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
13412
13413reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
13414reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
13415
13416reg update_dfesr_w;
13417
13418reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
13419reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
13420
13421reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
13422reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
13423
13424reg sync_asi;
13425reg chk_if_asi_ld;
13426reg [63:0] ld_data_w;
13427
13428reg desr_asi_rd, desr_wr, desr_pend_wr;
13429
13430assign mycid = 5;
13431assign mytid = 6;
13432assign mytnum = 5*8 + 6;
13433
13434initial begin //{
13435 desr_asi_rd = 1'b0;
13436 desr_pend_wr = 1'b0;
13437 ready = 0;
13438 @(posedge `SPC5.l2clk) ;
13439 @(posedge `SPC5.l2clk) ;
13440 ready = `PARGS.err_sync_on;
13441end //}
13442
13443`define DSFSR_NEW_IN_46 `SPC5.tlu.ras.dsfsr_6_new_in
13444`define ISFSR_NEW_IN_46 `SPC5.tlu.ras.isfsr_6_new_in
13445
13446`define DSFSR_46 `SPC5.tlu.ras.dsfsr_6
13447`define ISFSR_46 `SPC5.tlu.ras.isfsr_6
13448`define DSFAR_46 `SPC5.tlu.dfd.dsfar_6
13449
13450`define ASI_WR_DSFSR_46 `SPC5.tlu.ras.asi_wr_dsfsr[6]
13451`define ASI_WR_ISFSR_46 `SPC5.tlu.ras.asi_wr_isfsr[6]
13452
13453`define RAS_WRITE_DESR_1st_46 `SPC5.tlu.dfd.ras_write_desr_1st[6]
13454`define RAS_WRITE_DESR_2nd_46 `SPC5.tlu.dfd.ras_write_desr_2nd[6]
13455`define DESR_asi_rd_46 `SPC5.tlu.ras_rd_desr[6]
13456`define DESR_46 `SPC5.tlu.dfd.desr_6
13457
13458`define RAS_WRITE_FESR_46 `SPC5.tlu.ras.write_fesr[6]
13459`define FESR_46 `SPC5.tlu.dfd.fesr_6
13460
13461`define ST_ERR_46 `SPC5.tlu.trl1.take_ftt & `SPC5.tlu.trl1.trap[2]
13462`define SW_REC_ERR_46 `SPC5.tlu.trl1.take_ade & `SPC5.tlu.trl1.trap[2]
13463`define DATA_ACC_ERR_46 `SPC5.tlu.trl1.take_dae & `SPC5.tlu.trl1.trap[2]
13464`define INST_ACC_ERR_46 `SPC5.tlu.trl1.take_iae & `SPC5.tlu.trl1.trap[2]
13465`define INT_PROC_ERR_46 `SPC5.tlu.trl1.take_ipe & `SPC5.tlu.trl1.trap[2]
13466`define HW_CORR_ERR_46 `SPC5.tlu.trl1.take_eer & `SPC5.tlu.trl1.trap[2]
13467`define INST_ACC_MMU_ERR_46 `SPC5.tlu.trl1.take_ime & `SPC5.tlu.trl1.trap[2]
13468`define DATA_ACC_MMU_ERR_46 `SPC5.tlu.trl1.take_dme & `SPC5.tlu.trl1.trap[2]
13469
13470`define LSU_LD_VALID_B `PROBES5.lsu_ld_valid
13471`define LSU_TID_DEC_B_46 `PROBES5.lsu_tid_dec_b[6]
13472`define ASI_LD_46 `SPC5.lsu.lmd.lmq6_pkt[60] & (`SPC5.lsu.lmd.lmq6_pkt[49:48] == 2'b0)
13473`define ASI_46 `SPC5.lsu.lmd.lmq6_pkt[47:40]
13474`define ASI_ADDR_46 `SPC5.lsu.lmd.lmq6_pkt[39:0]
13475`define ASI_LD_DATA_46 `SPC5.lsu_exu_ld_data_b[63:0]
13476`define ASI_LD_COMP_46 tb_top.nas_top.c5.t6.complete_fw2
13477
13478//SPU specific - only one SPU per core
13479`define SPU_MA_BUSY_5 `SPC5.spu.spu_pmu_ma_busy[3]
13480`define SPU_MA_TID_5 `SPC5.spu.spu_pmu_ma_busy[2:0]
13481
13482////////////////////////////////////////////////////////////////////////////////
13483//Capture the status register data from rtl. For disrupting traps,
13484//rtl can modify the contents of the status register before the
13485//trap is taken and intp message is sent to Riesling.
13486//For precise traps, once the status register is updated rtl can't
13487//change the register again before jumping to the trap handler.
13488//So, for deferred and disrupting traps, inform Riesling when the
13489//register is modified while for precise traps wait until Fw2 before
13490//telling Riesling.
13491
13492//TLU asserts the flush and input signals in W stage. I latch them at the
13493//+ve edge of FX4.
13494
13495always @(negedge (`SPC5.l2clk & ready))
13496begin // {
13497 if (`DESR_asi_rd_46)
13498 desr_asi_rd <= 1'b1;
13499 if (desr_asi_rd)
13500 begin
13501 if (desr_wr)
13502 desr_pend_wr <= 1'b1;
13503 if (`ASI_LD_COMP_46[2])
13504 desr_asi_rd <= 1'b0;
13505 end
13506
13507 update_dsfsr_w <= (`DSFSR_NEW_IN_46 != 4'b0) && ~`ASI_WR_DSFSR_46;
13508 update_isfsr_w <= (`ISFSR_NEW_IN_46 != 3'b0) && ~`ASI_WR_ISFSR_46;
13509 desr_wr <= (`RAS_WRITE_DESR_1st_46 || `RAS_WRITE_DESR_2nd_46);
13510 update_dfesr_w <= `RAS_WRITE_FESR_46;
13511 take_err_trap_fx4 <= `ST_ERR_46 | `SW_REC_ERR_46 | `DATA_ACC_ERR_46
13512 | `INST_ACC_ERR_46 | `INT_PROC_ERR_46
13513 | `HW_CORR_ERR_46 | `INST_ACC_MMU_ERR_46
13514 | `DATA_ACC_MMU_ERR_46 ;
13515
13516
13517 if (`ST_ERR_46) int_num_fx4 <= 8'h07;
13518 if (`SW_REC_ERR_46) int_num_fx4 <= 8'h40;
13519 if (`DATA_ACC_ERR_46) int_num_fx4 <= 8'h32;
13520 if (`INST_ACC_ERR_46) int_num_fx4 <= 8'h0A;
13521 if (`INT_PROC_ERR_46) int_num_fx4 <= 8'h29;
13522 if (`HW_CORR_ERR_46) int_num_fx4 <= 8'h63;
13523 if (`INST_ACC_MMU_ERR_46) int_num_fx4 <= 8'h71;
13524 if (`DATA_ACC_MMU_ERR_46) int_num_fx4 <= 8'h72;
13525
13526 update_dsfsr_fx4 <= update_dsfsr_w;
13527 update_dsfsr_fx5 <= update_dsfsr_fx4;
13528 update_dsfsr_fb <= update_dsfsr_fx5;
13529 update_dsfsr_fw <= update_dsfsr_fb;
13530 update_dsfsr_fw1 <= update_dsfsr_fw;
13531 update_dsfsr_fw2 <= update_dsfsr_fw1;
13532
13533 update_isfsr_fx4 <= update_isfsr_w;
13534 update_isfsr_fx5 <= update_isfsr_fx4;
13535 update_isfsr_fb <= update_isfsr_fx5;
13536 update_isfsr_fw <= update_isfsr_fb;
13537 update_isfsr_fw1 <= update_isfsr_fw;
13538 update_isfsr_fw2 <= update_isfsr_fw1;
13539
13540 take_err_trap_fx5 <= take_err_trap_fx4;
13541 take_err_trap_fb <= take_err_trap_fx5;
13542 take_err_trap_fw <= take_err_trap_fb;
13543 take_err_trap_fw1 <= take_err_trap_fw;
13544 take_err_trap_fw2 <= take_err_trap_fw1;
13545
13546 int_num_fx5 <= int_num_fx4;
13547 int_num_fb <= int_num_fx5;
13548 int_num_fw <= int_num_fb;
13549 int_num_fw1 <= int_num_fw;
13550 int_num_fw2 <= int_num_fw1;
13551
13552 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
13553 begin // {
13554 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
13555 begin //{
13556 desr_pend_wr <= 1'b0;
13557 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_46[63:56], 45'b0, `DESR_46[10:0]});
13558 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_46[63:56], 45'b0, `DESR_46[10:0]});
13559 end //}
13560 //if (update_dfesr_w)
13561 if (`ST_ERR_46)
13562 begin //{
13563 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_46[61:55], 55'b0});
13564 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_46[61:55], 55'b0});
13565 end //}
13566 if (update_dsfsr_fw2)
13567 begin //{
13568 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
13569 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_46[3:0]});
13570 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_46[47:0]});
13571
13572 end //}
13573 if (update_isfsr_fw2)
13574 begin //{
13575 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
13576 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_46[2:0]});
13577 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_46[47:0]});
13578
13579 end //}
13580 if (take_err_trap_fw2)
13581 begin //{
13582 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
13583 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
13584 end // }
13585 end // }
13586
13587end //}
13588
13589//removing the addr check as the LSU doesn't flag an invalid_asi_exception
13590//if the addr of diagnostic accesses is not in the valid range. The inst.
13591//still executes. LSU expects that HP won't use addresses in invalid range.
13592
13593always @(negedge (`SPC5.l2clk & ready))
13594begin // {
13595 sync_asi = 1'b0;
13596 ld_data_w <= `ASI_LD_DATA_46;
13597
13598 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_46)
13599 chk_if_asi_ld <= 1'b1;
13600 else
13601 chk_if_asi_ld <= 1'b0;
13602
13603 if (chk_if_asi_ld & `ASI_LD_46)
13604 begin
13605 case (`ASI_46)
13606 8'h66: //ASI_IC_INSTR
13607 begin
13608 //if ((`ASI_ADDR_46 >= 0) & (`ASI_ADDR_46 <= 40'h7ff8))
13609 sync_asi = 1'b1;
13610 end
13611 8'h67: //ASI_IC_TAG
13612 begin
13613 //if ((`ASI_ADDR_46 >= 0) & (`ASI_ADDR_46 <= 40'h7fe0))
13614 sync_asi = 1'b1;
13615 end
13616 8'h46: //ASI_DC_DATA
13617 begin
13618 sync_asi = 1'b1;
13619 end
13620 8'h47: //ASI_DC_TAG
13621 begin
13622 //if ((`ASI_ADDR_46 >= 0) & (`ASI_ADDR_46 <= 40'h7ff0))
13623 sync_asi = 1'b1;
13624 end
13625 8'h48://IRF ECC
13626 begin
13627 //if ((`ASI_ADDR_46 >= 0) & (`ASI_ADDR_46 <= 40'hF8))
13628 sync_asi = 1'b1;
13629 end
13630 8'h49://FRF ECC
13631 begin
13632 //if ((`ASI_ADDR_46 >= 0) & (`ASI_ADDR_46 <= 40'hF8))
13633 sync_asi = 1'b1;
13634 end
13635 8'h4A://STB access, stb ptr can be read also
13636 begin
13637 //if ((`ASI_ADDR_46 >= 0) & (`ASI_ADDR_46 <= 40'h100))
13638 sync_asi = 1'b1;
13639 end
13640 8'h5A://Tick compare reg
13641 begin
13642 //if ((`ASI_ADDR_46 >= 0) & (`ASI_ADDR_46 <= 40'h38))
13643 sync_asi = 1'b1;
13644 end
13645 8'h5B://TSA
13646 begin
13647 //if ((`ASI_ADDR_46 >= 0) & (`ASI_ADDR_46 <= 40'h38))
13648 sync_asi = 1'b1;
13649 end
13650 8'h51://MRA
13651 begin
13652 //if ((`ASI_ADDR_46 >= 0) & (`ASI_ADDR_46 <= 40'h38))
13653 sync_asi = 1'b1;
13654 end
13655 8'h59://scratchpad ecc data read
13656 begin
13657 //if ((`ASI_ADDR_46 >= 0) & (`ASI_ADDR_46 <= 40'h38))
13658 //syncup the ecc data only. For ecc bit 6 is 0.
13659 if (~`SPC5.lsu.lmd.lmq6_pkt[6])
13660 sync_asi = 1'b1;
13661 end
13662 8'h40://cwqcsr,ma_sync access
13663 begin
13664 if ((`ASI_ADDR_46 == 40'h20) || (`ASI_ADDR_46 == 40'h30)
13665 || (`ASI_ADDR_46 == 40'h80)
13666 || ((`ASI_ADDR_46 == 40'ha0) & (`SPU_MA_BUSY_5 == 0) & (`SPU_MA_TID_5 == 6))
13667 )
13668 sync_asi = 1'b1;
13669 end
13670 8'h4C://CLESR, CLFESR access
13671 begin
13672 if ((`ASI_ADDR_46 == 40'h20) || (`ASI_ADDR_46 == 40'h28))
13673 sync_asi = 1'b1;
13674 end
13675 endcase
13676 end
13677
13678 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
13679 begin
13680 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_46, `ASI_ADDR_46, ld_data_w);
13681 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_46, {24'b0, `ASI_ADDR_46}, ld_data_w[63:0]);
13682 end
13683end //}
13684`endif
13685endmodule
13686
13687
13688
13689module err_c5t7 ();
13690`ifndef GATESIM
13691
13692`include "defines.vh"
13693
13694wire [2:0] mycid;
13695wire [2:0] mytid;
13696wire [5:0] mytnum;
13697
13698integer junk;
13699reg ready;
13700reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
13701reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
13702
13703reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
13704reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
13705
13706reg update_dfesr_w;
13707
13708reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
13709reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
13710
13711reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
13712reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
13713
13714reg sync_asi;
13715reg chk_if_asi_ld;
13716reg [63:0] ld_data_w;
13717
13718reg desr_asi_rd, desr_wr, desr_pend_wr;
13719
13720assign mycid = 5;
13721assign mytid = 7;
13722assign mytnum = 5*8 + 7;
13723
13724initial begin //{
13725 desr_asi_rd = 1'b0;
13726 desr_pend_wr = 1'b0;
13727 ready = 0;
13728 @(posedge `SPC5.l2clk) ;
13729 @(posedge `SPC5.l2clk) ;
13730 ready = `PARGS.err_sync_on;
13731end //}
13732
13733`define DSFSR_NEW_IN_47 `SPC5.tlu.ras.dsfsr_7_new_in
13734`define ISFSR_NEW_IN_47 `SPC5.tlu.ras.isfsr_7_new_in
13735
13736`define DSFSR_47 `SPC5.tlu.ras.dsfsr_7
13737`define ISFSR_47 `SPC5.tlu.ras.isfsr_7
13738`define DSFAR_47 `SPC5.tlu.dfd.dsfar_7
13739
13740`define ASI_WR_DSFSR_47 `SPC5.tlu.ras.asi_wr_dsfsr[7]
13741`define ASI_WR_ISFSR_47 `SPC5.tlu.ras.asi_wr_isfsr[7]
13742
13743`define RAS_WRITE_DESR_1st_47 `SPC5.tlu.dfd.ras_write_desr_1st[7]
13744`define RAS_WRITE_DESR_2nd_47 `SPC5.tlu.dfd.ras_write_desr_2nd[7]
13745`define DESR_asi_rd_47 `SPC5.tlu.ras_rd_desr[7]
13746`define DESR_47 `SPC5.tlu.dfd.desr_7
13747
13748`define RAS_WRITE_FESR_47 `SPC5.tlu.ras.write_fesr[7]
13749`define FESR_47 `SPC5.tlu.dfd.fesr_7
13750
13751`define ST_ERR_47 `SPC5.tlu.trl1.take_ftt & `SPC5.tlu.trl1.trap[3]
13752`define SW_REC_ERR_47 `SPC5.tlu.trl1.take_ade & `SPC5.tlu.trl1.trap[3]
13753`define DATA_ACC_ERR_47 `SPC5.tlu.trl1.take_dae & `SPC5.tlu.trl1.trap[3]
13754`define INST_ACC_ERR_47 `SPC5.tlu.trl1.take_iae & `SPC5.tlu.trl1.trap[3]
13755`define INT_PROC_ERR_47 `SPC5.tlu.trl1.take_ipe & `SPC5.tlu.trl1.trap[3]
13756`define HW_CORR_ERR_47 `SPC5.tlu.trl1.take_eer & `SPC5.tlu.trl1.trap[3]
13757`define INST_ACC_MMU_ERR_47 `SPC5.tlu.trl1.take_ime & `SPC5.tlu.trl1.trap[3]
13758`define DATA_ACC_MMU_ERR_47 `SPC5.tlu.trl1.take_dme & `SPC5.tlu.trl1.trap[3]
13759
13760`define LSU_LD_VALID_B `PROBES5.lsu_ld_valid
13761`define LSU_TID_DEC_B_47 `PROBES5.lsu_tid_dec_b[7]
13762`define ASI_LD_47 `SPC5.lsu.lmd.lmq7_pkt[60] & (`SPC5.lsu.lmd.lmq7_pkt[49:48] == 2'b0)
13763`define ASI_47 `SPC5.lsu.lmd.lmq7_pkt[47:40]
13764`define ASI_ADDR_47 `SPC5.lsu.lmd.lmq7_pkt[39:0]
13765`define ASI_LD_DATA_47 `SPC5.lsu_exu_ld_data_b[63:0]
13766`define ASI_LD_COMP_47 tb_top.nas_top.c5.t7.complete_fw2
13767
13768//SPU specific - only one SPU per core
13769`define SPU_MA_BUSY_5 `SPC5.spu.spu_pmu_ma_busy[3]
13770`define SPU_MA_TID_5 `SPC5.spu.spu_pmu_ma_busy[2:0]
13771
13772////////////////////////////////////////////////////////////////////////////////
13773//Capture the status register data from rtl. For disrupting traps,
13774//rtl can modify the contents of the status register before the
13775//trap is taken and intp message is sent to Riesling.
13776//For precise traps, once the status register is updated rtl can't
13777//change the register again before jumping to the trap handler.
13778//So, for deferred and disrupting traps, inform Riesling when the
13779//register is modified while for precise traps wait until Fw2 before
13780//telling Riesling.
13781
13782//TLU asserts the flush and input signals in W stage. I latch them at the
13783//+ve edge of FX4.
13784
13785always @(negedge (`SPC5.l2clk & ready))
13786begin // {
13787 if (`DESR_asi_rd_47)
13788 desr_asi_rd <= 1'b1;
13789 if (desr_asi_rd)
13790 begin
13791 if (desr_wr)
13792 desr_pend_wr <= 1'b1;
13793 if (`ASI_LD_COMP_47[2])
13794 desr_asi_rd <= 1'b0;
13795 end
13796
13797 update_dsfsr_w <= (`DSFSR_NEW_IN_47 != 4'b0) && ~`ASI_WR_DSFSR_47;
13798 update_isfsr_w <= (`ISFSR_NEW_IN_47 != 3'b0) && ~`ASI_WR_ISFSR_47;
13799 desr_wr <= (`RAS_WRITE_DESR_1st_47 || `RAS_WRITE_DESR_2nd_47);
13800 update_dfesr_w <= `RAS_WRITE_FESR_47;
13801 take_err_trap_fx4 <= `ST_ERR_47 | `SW_REC_ERR_47 | `DATA_ACC_ERR_47
13802 | `INST_ACC_ERR_47 | `INT_PROC_ERR_47
13803 | `HW_CORR_ERR_47 | `INST_ACC_MMU_ERR_47
13804 | `DATA_ACC_MMU_ERR_47 ;
13805
13806
13807 if (`ST_ERR_47) int_num_fx4 <= 8'h07;
13808 if (`SW_REC_ERR_47) int_num_fx4 <= 8'h40;
13809 if (`DATA_ACC_ERR_47) int_num_fx4 <= 8'h32;
13810 if (`INST_ACC_ERR_47) int_num_fx4 <= 8'h0A;
13811 if (`INT_PROC_ERR_47) int_num_fx4 <= 8'h29;
13812 if (`HW_CORR_ERR_47) int_num_fx4 <= 8'h63;
13813 if (`INST_ACC_MMU_ERR_47) int_num_fx4 <= 8'h71;
13814 if (`DATA_ACC_MMU_ERR_47) int_num_fx4 <= 8'h72;
13815
13816 update_dsfsr_fx4 <= update_dsfsr_w;
13817 update_dsfsr_fx5 <= update_dsfsr_fx4;
13818 update_dsfsr_fb <= update_dsfsr_fx5;
13819 update_dsfsr_fw <= update_dsfsr_fb;
13820 update_dsfsr_fw1 <= update_dsfsr_fw;
13821 update_dsfsr_fw2 <= update_dsfsr_fw1;
13822
13823 update_isfsr_fx4 <= update_isfsr_w;
13824 update_isfsr_fx5 <= update_isfsr_fx4;
13825 update_isfsr_fb <= update_isfsr_fx5;
13826 update_isfsr_fw <= update_isfsr_fb;
13827 update_isfsr_fw1 <= update_isfsr_fw;
13828 update_isfsr_fw2 <= update_isfsr_fw1;
13829
13830 take_err_trap_fx5 <= take_err_trap_fx4;
13831 take_err_trap_fb <= take_err_trap_fx5;
13832 take_err_trap_fw <= take_err_trap_fb;
13833 take_err_trap_fw1 <= take_err_trap_fw;
13834 take_err_trap_fw2 <= take_err_trap_fw1;
13835
13836 int_num_fx5 <= int_num_fx4;
13837 int_num_fb <= int_num_fx5;
13838 int_num_fw <= int_num_fb;
13839 int_num_fw1 <= int_num_fw;
13840 int_num_fw2 <= int_num_fw1;
13841
13842 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
13843 begin // {
13844 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
13845 begin //{
13846 desr_pend_wr <= 1'b0;
13847 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_47[63:56], 45'b0, `DESR_47[10:0]});
13848 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_47[63:56], 45'b0, `DESR_47[10:0]});
13849 end //}
13850 //if (update_dfesr_w)
13851 if (`ST_ERR_47)
13852 begin //{
13853 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_47[61:55], 55'b0});
13854 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_47[61:55], 55'b0});
13855 end //}
13856 if (update_dsfsr_fw2)
13857 begin //{
13858 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
13859 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_47[3:0]});
13860 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_47[47:0]});
13861
13862 end //}
13863 if (update_isfsr_fw2)
13864 begin //{
13865 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
13866 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_47[2:0]});
13867 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_47[47:0]});
13868
13869 end //}
13870 if (take_err_trap_fw2)
13871 begin //{
13872 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
13873 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
13874 end // }
13875 end // }
13876
13877end //}
13878
13879//removing the addr check as the LSU doesn't flag an invalid_asi_exception
13880//if the addr of diagnostic accesses is not in the valid range. The inst.
13881//still executes. LSU expects that HP won't use addresses in invalid range.
13882
13883always @(negedge (`SPC5.l2clk & ready))
13884begin // {
13885 sync_asi = 1'b0;
13886 ld_data_w <= `ASI_LD_DATA_47;
13887
13888 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_47)
13889 chk_if_asi_ld <= 1'b1;
13890 else
13891 chk_if_asi_ld <= 1'b0;
13892
13893 if (chk_if_asi_ld & `ASI_LD_47)
13894 begin
13895 case (`ASI_47)
13896 8'h66: //ASI_IC_INSTR
13897 begin
13898 //if ((`ASI_ADDR_47 >= 0) & (`ASI_ADDR_47 <= 40'h7ff8))
13899 sync_asi = 1'b1;
13900 end
13901 8'h67: //ASI_IC_TAG
13902 begin
13903 //if ((`ASI_ADDR_47 >= 0) & (`ASI_ADDR_47 <= 40'h7fe0))
13904 sync_asi = 1'b1;
13905 end
13906 8'h46: //ASI_DC_DATA
13907 begin
13908 sync_asi = 1'b1;
13909 end
13910 8'h47: //ASI_DC_TAG
13911 begin
13912 //if ((`ASI_ADDR_47 >= 0) & (`ASI_ADDR_47 <= 40'h7ff0))
13913 sync_asi = 1'b1;
13914 end
13915 8'h48://IRF ECC
13916 begin
13917 //if ((`ASI_ADDR_47 >= 0) & (`ASI_ADDR_47 <= 40'hF8))
13918 sync_asi = 1'b1;
13919 end
13920 8'h49://FRF ECC
13921 begin
13922 //if ((`ASI_ADDR_47 >= 0) & (`ASI_ADDR_47 <= 40'hF8))
13923 sync_asi = 1'b1;
13924 end
13925 8'h4A://STB access, stb ptr can be read also
13926 begin
13927 //if ((`ASI_ADDR_47 >= 0) & (`ASI_ADDR_47 <= 40'h100))
13928 sync_asi = 1'b1;
13929 end
13930 8'h5A://Tick compare reg
13931 begin
13932 //if ((`ASI_ADDR_47 >= 0) & (`ASI_ADDR_47 <= 40'h38))
13933 sync_asi = 1'b1;
13934 end
13935 8'h5B://TSA
13936 begin
13937 //if ((`ASI_ADDR_47 >= 0) & (`ASI_ADDR_47 <= 40'h38))
13938 sync_asi = 1'b1;
13939 end
13940 8'h51://MRA
13941 begin
13942 //if ((`ASI_ADDR_47 >= 0) & (`ASI_ADDR_47 <= 40'h38))
13943 sync_asi = 1'b1;
13944 end
13945 8'h59://scratchpad ecc data read
13946 begin
13947 //if ((`ASI_ADDR_47 >= 0) & (`ASI_ADDR_47 <= 40'h38))
13948 //syncup the ecc data only. For ecc bit 6 is 0.
13949 if (~`SPC5.lsu.lmd.lmq7_pkt[6])
13950 sync_asi = 1'b1;
13951 end
13952 8'h40://cwqcsr,ma_sync access
13953 begin
13954 if ((`ASI_ADDR_47 == 40'h20) || (`ASI_ADDR_47 == 40'h30)
13955 || (`ASI_ADDR_47 == 40'h80)
13956 || ((`ASI_ADDR_47 == 40'ha0) & (`SPU_MA_BUSY_5 == 0) & (`SPU_MA_TID_5 == 7))
13957 )
13958 sync_asi = 1'b1;
13959 end
13960 8'h4C://CLESR, CLFESR access
13961 begin
13962 if ((`ASI_ADDR_47 == 40'h20) || (`ASI_ADDR_47 == 40'h28))
13963 sync_asi = 1'b1;
13964 end
13965 endcase
13966 end
13967
13968 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
13969 begin
13970 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_47, `ASI_ADDR_47, ld_data_w);
13971 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_47, {24'b0, `ASI_ADDR_47}, ld_data_w[63:0]);
13972 end
13973end //}
13974`endif
13975endmodule
13976
13977`endif
13978
13979`ifdef CORE_6
13980
13981
13982
13983module err_c6t0 ();
13984`ifndef GATESIM
13985
13986`include "defines.vh"
13987
13988wire [2:0] mycid;
13989wire [2:0] mytid;
13990wire [5:0] mytnum;
13991
13992integer junk;
13993reg ready;
13994reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
13995reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
13996
13997reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
13998reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
13999
14000reg update_dfesr_w;
14001
14002reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
14003reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
14004
14005reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
14006reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
14007
14008reg sync_asi;
14009reg chk_if_asi_ld;
14010reg [63:0] ld_data_w;
14011
14012reg desr_asi_rd, desr_wr, desr_pend_wr;
14013
14014assign mycid = 6;
14015assign mytid = 0;
14016assign mytnum = 6*8 + 0;
14017
14018initial begin //{
14019 desr_asi_rd = 1'b0;
14020 desr_pend_wr = 1'b0;
14021 ready = 0;
14022 @(posedge `SPC6.l2clk) ;
14023 @(posedge `SPC6.l2clk) ;
14024 ready = `PARGS.err_sync_on;
14025end //}
14026
14027`define DSFSR_NEW_IN_48 `SPC6.tlu.ras.dsfsr_0_new_in
14028`define ISFSR_NEW_IN_48 `SPC6.tlu.ras.isfsr_0_new_in
14029
14030`define DSFSR_48 `SPC6.tlu.ras.dsfsr_0
14031`define ISFSR_48 `SPC6.tlu.ras.isfsr_0
14032`define DSFAR_48 `SPC6.tlu.dfd.dsfar_0
14033
14034`define ASI_WR_DSFSR_48 `SPC6.tlu.ras.asi_wr_dsfsr[0]
14035`define ASI_WR_ISFSR_48 `SPC6.tlu.ras.asi_wr_isfsr[0]
14036
14037`define RAS_WRITE_DESR_1st_48 `SPC6.tlu.dfd.ras_write_desr_1st[0]
14038`define RAS_WRITE_DESR_2nd_48 `SPC6.tlu.dfd.ras_write_desr_2nd[0]
14039`define DESR_asi_rd_48 `SPC6.tlu.ras_rd_desr[0]
14040`define DESR_48 `SPC6.tlu.dfd.desr_0
14041
14042`define RAS_WRITE_FESR_48 `SPC6.tlu.ras.write_fesr[0]
14043`define FESR_48 `SPC6.tlu.dfd.fesr_0
14044
14045`define ST_ERR_48 `SPC6.tlu.trl0.take_ftt & `SPC6.tlu.trl0.trap[0]
14046`define SW_REC_ERR_48 `SPC6.tlu.trl0.take_ade & `SPC6.tlu.trl0.trap[0]
14047`define DATA_ACC_ERR_48 `SPC6.tlu.trl0.take_dae & `SPC6.tlu.trl0.trap[0]
14048`define INST_ACC_ERR_48 `SPC6.tlu.trl0.take_iae & `SPC6.tlu.trl0.trap[0]
14049`define INT_PROC_ERR_48 `SPC6.tlu.trl0.take_ipe & `SPC6.tlu.trl0.trap[0]
14050`define HW_CORR_ERR_48 `SPC6.tlu.trl0.take_eer & `SPC6.tlu.trl0.trap[0]
14051`define INST_ACC_MMU_ERR_48 `SPC6.tlu.trl0.take_ime & `SPC6.tlu.trl0.trap[0]
14052`define DATA_ACC_MMU_ERR_48 `SPC6.tlu.trl0.take_dme & `SPC6.tlu.trl0.trap[0]
14053
14054`define LSU_LD_VALID_B `PROBES6.lsu_ld_valid
14055`define LSU_TID_DEC_B_48 `PROBES6.lsu_tid_dec_b[0]
14056`define ASI_LD_48 `SPC6.lsu.lmd.lmq0_pkt[60] & (`SPC6.lsu.lmd.lmq0_pkt[49:48] == 2'b0)
14057`define ASI_48 `SPC6.lsu.lmd.lmq0_pkt[47:40]
14058`define ASI_ADDR_48 `SPC6.lsu.lmd.lmq0_pkt[39:0]
14059`define ASI_LD_DATA_48 `SPC6.lsu_exu_ld_data_b[63:0]
14060`define ASI_LD_COMP_48 tb_top.nas_top.c6.t0.complete_fw2
14061
14062//SPU specific - only one SPU per core
14063`define SPU_MA_BUSY_6 `SPC6.spu.spu_pmu_ma_busy[3]
14064`define SPU_MA_TID_6 `SPC6.spu.spu_pmu_ma_busy[2:0]
14065
14066////////////////////////////////////////////////////////////////////////////////
14067//Capture the status register data from rtl. For disrupting traps,
14068//rtl can modify the contents of the status register before the
14069//trap is taken and intp message is sent to Riesling.
14070//For precise traps, once the status register is updated rtl can't
14071//change the register again before jumping to the trap handler.
14072//So, for deferred and disrupting traps, inform Riesling when the
14073//register is modified while for precise traps wait until Fw2 before
14074//telling Riesling.
14075
14076//TLU asserts the flush and input signals in W stage. I latch them at the
14077//+ve edge of FX4.
14078
14079always @(negedge (`SPC6.l2clk & ready))
14080begin // {
14081 if (`DESR_asi_rd_48)
14082 desr_asi_rd <= 1'b1;
14083 if (desr_asi_rd)
14084 begin
14085 if (desr_wr)
14086 desr_pend_wr <= 1'b1;
14087 if (`ASI_LD_COMP_48[2])
14088 desr_asi_rd <= 1'b0;
14089 end
14090
14091 update_dsfsr_w <= (`DSFSR_NEW_IN_48 != 4'b0) && ~`ASI_WR_DSFSR_48;
14092 update_isfsr_w <= (`ISFSR_NEW_IN_48 != 3'b0) && ~`ASI_WR_ISFSR_48;
14093 desr_wr <= (`RAS_WRITE_DESR_1st_48 || `RAS_WRITE_DESR_2nd_48);
14094 update_dfesr_w <= `RAS_WRITE_FESR_48;
14095 take_err_trap_fx4 <= `ST_ERR_48 | `SW_REC_ERR_48 | `DATA_ACC_ERR_48
14096 | `INST_ACC_ERR_48 | `INT_PROC_ERR_48
14097 | `HW_CORR_ERR_48 | `INST_ACC_MMU_ERR_48
14098 | `DATA_ACC_MMU_ERR_48 ;
14099
14100
14101 if (`ST_ERR_48) int_num_fx4 <= 8'h07;
14102 if (`SW_REC_ERR_48) int_num_fx4 <= 8'h40;
14103 if (`DATA_ACC_ERR_48) int_num_fx4 <= 8'h32;
14104 if (`INST_ACC_ERR_48) int_num_fx4 <= 8'h0A;
14105 if (`INT_PROC_ERR_48) int_num_fx4 <= 8'h29;
14106 if (`HW_CORR_ERR_48) int_num_fx4 <= 8'h63;
14107 if (`INST_ACC_MMU_ERR_48) int_num_fx4 <= 8'h71;
14108 if (`DATA_ACC_MMU_ERR_48) int_num_fx4 <= 8'h72;
14109
14110 update_dsfsr_fx4 <= update_dsfsr_w;
14111 update_dsfsr_fx5 <= update_dsfsr_fx4;
14112 update_dsfsr_fb <= update_dsfsr_fx5;
14113 update_dsfsr_fw <= update_dsfsr_fb;
14114 update_dsfsr_fw1 <= update_dsfsr_fw;
14115 update_dsfsr_fw2 <= update_dsfsr_fw1;
14116
14117 update_isfsr_fx4 <= update_isfsr_w;
14118 update_isfsr_fx5 <= update_isfsr_fx4;
14119 update_isfsr_fb <= update_isfsr_fx5;
14120 update_isfsr_fw <= update_isfsr_fb;
14121 update_isfsr_fw1 <= update_isfsr_fw;
14122 update_isfsr_fw2 <= update_isfsr_fw1;
14123
14124 take_err_trap_fx5 <= take_err_trap_fx4;
14125 take_err_trap_fb <= take_err_trap_fx5;
14126 take_err_trap_fw <= take_err_trap_fb;
14127 take_err_trap_fw1 <= take_err_trap_fw;
14128 take_err_trap_fw2 <= take_err_trap_fw1;
14129
14130 int_num_fx5 <= int_num_fx4;
14131 int_num_fb <= int_num_fx5;
14132 int_num_fw <= int_num_fb;
14133 int_num_fw1 <= int_num_fw;
14134 int_num_fw2 <= int_num_fw1;
14135
14136 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
14137 begin // {
14138 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
14139 begin //{
14140 desr_pend_wr <= 1'b0;
14141 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_48[63:56], 45'b0, `DESR_48[10:0]});
14142 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_48[63:56], 45'b0, `DESR_48[10:0]});
14143 end //}
14144 //if (update_dfesr_w)
14145 if (`ST_ERR_48)
14146 begin //{
14147 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_48[61:55], 55'b0});
14148 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_48[61:55], 55'b0});
14149 end //}
14150 if (update_dsfsr_fw2)
14151 begin //{
14152 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
14153 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_48[3:0]});
14154 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_48[47:0]});
14155
14156 end //}
14157 if (update_isfsr_fw2)
14158 begin //{
14159 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
14160 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_48[2:0]});
14161 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_48[47:0]});
14162
14163 end //}
14164 if (take_err_trap_fw2)
14165 begin //{
14166 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
14167 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
14168 end // }
14169 end // }
14170
14171end //}
14172
14173//removing the addr check as the LSU doesn't flag an invalid_asi_exception
14174//if the addr of diagnostic accesses is not in the valid range. The inst.
14175//still executes. LSU expects that HP won't use addresses in invalid range.
14176
14177always @(negedge (`SPC6.l2clk & ready))
14178begin // {
14179 sync_asi = 1'b0;
14180 ld_data_w <= `ASI_LD_DATA_48;
14181
14182 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_48)
14183 chk_if_asi_ld <= 1'b1;
14184 else
14185 chk_if_asi_ld <= 1'b0;
14186
14187 if (chk_if_asi_ld & `ASI_LD_48)
14188 begin
14189 case (`ASI_48)
14190 8'h66: //ASI_IC_INSTR
14191 begin
14192 //if ((`ASI_ADDR_48 >= 0) & (`ASI_ADDR_48 <= 40'h7ff8))
14193 sync_asi = 1'b1;
14194 end
14195 8'h67: //ASI_IC_TAG
14196 begin
14197 //if ((`ASI_ADDR_48 >= 0) & (`ASI_ADDR_48 <= 40'h7fe0))
14198 sync_asi = 1'b1;
14199 end
14200 8'h46: //ASI_DC_DATA
14201 begin
14202 sync_asi = 1'b1;
14203 end
14204 8'h47: //ASI_DC_TAG
14205 begin
14206 //if ((`ASI_ADDR_48 >= 0) & (`ASI_ADDR_48 <= 40'h7ff0))
14207 sync_asi = 1'b1;
14208 end
14209 8'h48://IRF ECC
14210 begin
14211 //if ((`ASI_ADDR_48 >= 0) & (`ASI_ADDR_48 <= 40'hF8))
14212 sync_asi = 1'b1;
14213 end
14214 8'h49://FRF ECC
14215 begin
14216 //if ((`ASI_ADDR_48 >= 0) & (`ASI_ADDR_48 <= 40'hF8))
14217 sync_asi = 1'b1;
14218 end
14219 8'h4A://STB access, stb ptr can be read also
14220 begin
14221 //if ((`ASI_ADDR_48 >= 0) & (`ASI_ADDR_48 <= 40'h100))
14222 sync_asi = 1'b1;
14223 end
14224 8'h5A://Tick compare reg
14225 begin
14226 //if ((`ASI_ADDR_48 >= 0) & (`ASI_ADDR_48 <= 40'h38))
14227 sync_asi = 1'b1;
14228 end
14229 8'h5B://TSA
14230 begin
14231 //if ((`ASI_ADDR_48 >= 0) & (`ASI_ADDR_48 <= 40'h38))
14232 sync_asi = 1'b1;
14233 end
14234 8'h51://MRA
14235 begin
14236 //if ((`ASI_ADDR_48 >= 0) & (`ASI_ADDR_48 <= 40'h38))
14237 sync_asi = 1'b1;
14238 end
14239 8'h59://scratchpad ecc data read
14240 begin
14241 //if ((`ASI_ADDR_48 >= 0) & (`ASI_ADDR_48 <= 40'h38))
14242 //syncup the ecc data only. For ecc bit 6 is 0.
14243 if (~`SPC6.lsu.lmd.lmq0_pkt[6])
14244 sync_asi = 1'b1;
14245 end
14246 8'h40://cwqcsr,ma_sync access
14247 begin
14248 if ((`ASI_ADDR_48 == 40'h20) || (`ASI_ADDR_48 == 40'h30)
14249 || (`ASI_ADDR_48 == 40'h80)
14250 || ((`ASI_ADDR_48 == 40'ha0) & (`SPU_MA_BUSY_6 == 0) & (`SPU_MA_TID_6 == 0))
14251 )
14252 sync_asi = 1'b1;
14253 end
14254 8'h4C://CLESR, CLFESR access
14255 begin
14256 if ((`ASI_ADDR_48 == 40'h20) || (`ASI_ADDR_48 == 40'h28))
14257 sync_asi = 1'b1;
14258 end
14259 endcase
14260 end
14261
14262 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
14263 begin
14264 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_48, `ASI_ADDR_48, ld_data_w);
14265 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_48, {24'b0, `ASI_ADDR_48}, ld_data_w[63:0]);
14266 end
14267end //}
14268`endif
14269endmodule
14270
14271
14272
14273module err_c6t1 ();
14274`ifndef GATESIM
14275
14276`include "defines.vh"
14277
14278wire [2:0] mycid;
14279wire [2:0] mytid;
14280wire [5:0] mytnum;
14281
14282integer junk;
14283reg ready;
14284reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
14285reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
14286
14287reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
14288reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
14289
14290reg update_dfesr_w;
14291
14292reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
14293reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
14294
14295reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
14296reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
14297
14298reg sync_asi;
14299reg chk_if_asi_ld;
14300reg [63:0] ld_data_w;
14301
14302reg desr_asi_rd, desr_wr, desr_pend_wr;
14303
14304assign mycid = 6;
14305assign mytid = 1;
14306assign mytnum = 6*8 + 1;
14307
14308initial begin //{
14309 desr_asi_rd = 1'b0;
14310 desr_pend_wr = 1'b0;
14311 ready = 0;
14312 @(posedge `SPC6.l2clk) ;
14313 @(posedge `SPC6.l2clk) ;
14314 ready = `PARGS.err_sync_on;
14315end //}
14316
14317`define DSFSR_NEW_IN_49 `SPC6.tlu.ras.dsfsr_1_new_in
14318`define ISFSR_NEW_IN_49 `SPC6.tlu.ras.isfsr_1_new_in
14319
14320`define DSFSR_49 `SPC6.tlu.ras.dsfsr_1
14321`define ISFSR_49 `SPC6.tlu.ras.isfsr_1
14322`define DSFAR_49 `SPC6.tlu.dfd.dsfar_1
14323
14324`define ASI_WR_DSFSR_49 `SPC6.tlu.ras.asi_wr_dsfsr[1]
14325`define ASI_WR_ISFSR_49 `SPC6.tlu.ras.asi_wr_isfsr[1]
14326
14327`define RAS_WRITE_DESR_1st_49 `SPC6.tlu.dfd.ras_write_desr_1st[1]
14328`define RAS_WRITE_DESR_2nd_49 `SPC6.tlu.dfd.ras_write_desr_2nd[1]
14329`define DESR_asi_rd_49 `SPC6.tlu.ras_rd_desr[1]
14330`define DESR_49 `SPC6.tlu.dfd.desr_1
14331
14332`define RAS_WRITE_FESR_49 `SPC6.tlu.ras.write_fesr[1]
14333`define FESR_49 `SPC6.tlu.dfd.fesr_1
14334
14335`define ST_ERR_49 `SPC6.tlu.trl0.take_ftt & `SPC6.tlu.trl0.trap[1]
14336`define SW_REC_ERR_49 `SPC6.tlu.trl0.take_ade & `SPC6.tlu.trl0.trap[1]
14337`define DATA_ACC_ERR_49 `SPC6.tlu.trl0.take_dae & `SPC6.tlu.trl0.trap[1]
14338`define INST_ACC_ERR_49 `SPC6.tlu.trl0.take_iae & `SPC6.tlu.trl0.trap[1]
14339`define INT_PROC_ERR_49 `SPC6.tlu.trl0.take_ipe & `SPC6.tlu.trl0.trap[1]
14340`define HW_CORR_ERR_49 `SPC6.tlu.trl0.take_eer & `SPC6.tlu.trl0.trap[1]
14341`define INST_ACC_MMU_ERR_49 `SPC6.tlu.trl0.take_ime & `SPC6.tlu.trl0.trap[1]
14342`define DATA_ACC_MMU_ERR_49 `SPC6.tlu.trl0.take_dme & `SPC6.tlu.trl0.trap[1]
14343
14344`define LSU_LD_VALID_B `PROBES6.lsu_ld_valid
14345`define LSU_TID_DEC_B_49 `PROBES6.lsu_tid_dec_b[1]
14346`define ASI_LD_49 `SPC6.lsu.lmd.lmq1_pkt[60] & (`SPC6.lsu.lmd.lmq1_pkt[49:48] == 2'b0)
14347`define ASI_49 `SPC6.lsu.lmd.lmq1_pkt[47:40]
14348`define ASI_ADDR_49 `SPC6.lsu.lmd.lmq1_pkt[39:0]
14349`define ASI_LD_DATA_49 `SPC6.lsu_exu_ld_data_b[63:0]
14350`define ASI_LD_COMP_49 tb_top.nas_top.c6.t1.complete_fw2
14351
14352//SPU specific - only one SPU per core
14353`define SPU_MA_BUSY_6 `SPC6.spu.spu_pmu_ma_busy[3]
14354`define SPU_MA_TID_6 `SPC6.spu.spu_pmu_ma_busy[2:0]
14355
14356////////////////////////////////////////////////////////////////////////////////
14357//Capture the status register data from rtl. For disrupting traps,
14358//rtl can modify the contents of the status register before the
14359//trap is taken and intp message is sent to Riesling.
14360//For precise traps, once the status register is updated rtl can't
14361//change the register again before jumping to the trap handler.
14362//So, for deferred and disrupting traps, inform Riesling when the
14363//register is modified while for precise traps wait until Fw2 before
14364//telling Riesling.
14365
14366//TLU asserts the flush and input signals in W stage. I latch them at the
14367//+ve edge of FX4.
14368
14369always @(negedge (`SPC6.l2clk & ready))
14370begin // {
14371 if (`DESR_asi_rd_49)
14372 desr_asi_rd <= 1'b1;
14373 if (desr_asi_rd)
14374 begin
14375 if (desr_wr)
14376 desr_pend_wr <= 1'b1;
14377 if (`ASI_LD_COMP_49[2])
14378 desr_asi_rd <= 1'b0;
14379 end
14380
14381 update_dsfsr_w <= (`DSFSR_NEW_IN_49 != 4'b0) && ~`ASI_WR_DSFSR_49;
14382 update_isfsr_w <= (`ISFSR_NEW_IN_49 != 3'b0) && ~`ASI_WR_ISFSR_49;
14383 desr_wr <= (`RAS_WRITE_DESR_1st_49 || `RAS_WRITE_DESR_2nd_49);
14384 update_dfesr_w <= `RAS_WRITE_FESR_49;
14385 take_err_trap_fx4 <= `ST_ERR_49 | `SW_REC_ERR_49 | `DATA_ACC_ERR_49
14386 | `INST_ACC_ERR_49 | `INT_PROC_ERR_49
14387 | `HW_CORR_ERR_49 | `INST_ACC_MMU_ERR_49
14388 | `DATA_ACC_MMU_ERR_49 ;
14389
14390
14391 if (`ST_ERR_49) int_num_fx4 <= 8'h07;
14392 if (`SW_REC_ERR_49) int_num_fx4 <= 8'h40;
14393 if (`DATA_ACC_ERR_49) int_num_fx4 <= 8'h32;
14394 if (`INST_ACC_ERR_49) int_num_fx4 <= 8'h0A;
14395 if (`INT_PROC_ERR_49) int_num_fx4 <= 8'h29;
14396 if (`HW_CORR_ERR_49) int_num_fx4 <= 8'h63;
14397 if (`INST_ACC_MMU_ERR_49) int_num_fx4 <= 8'h71;
14398 if (`DATA_ACC_MMU_ERR_49) int_num_fx4 <= 8'h72;
14399
14400 update_dsfsr_fx4 <= update_dsfsr_w;
14401 update_dsfsr_fx5 <= update_dsfsr_fx4;
14402 update_dsfsr_fb <= update_dsfsr_fx5;
14403 update_dsfsr_fw <= update_dsfsr_fb;
14404 update_dsfsr_fw1 <= update_dsfsr_fw;
14405 update_dsfsr_fw2 <= update_dsfsr_fw1;
14406
14407 update_isfsr_fx4 <= update_isfsr_w;
14408 update_isfsr_fx5 <= update_isfsr_fx4;
14409 update_isfsr_fb <= update_isfsr_fx5;
14410 update_isfsr_fw <= update_isfsr_fb;
14411 update_isfsr_fw1 <= update_isfsr_fw;
14412 update_isfsr_fw2 <= update_isfsr_fw1;
14413
14414 take_err_trap_fx5 <= take_err_trap_fx4;
14415 take_err_trap_fb <= take_err_trap_fx5;
14416 take_err_trap_fw <= take_err_trap_fb;
14417 take_err_trap_fw1 <= take_err_trap_fw;
14418 take_err_trap_fw2 <= take_err_trap_fw1;
14419
14420 int_num_fx5 <= int_num_fx4;
14421 int_num_fb <= int_num_fx5;
14422 int_num_fw <= int_num_fb;
14423 int_num_fw1 <= int_num_fw;
14424 int_num_fw2 <= int_num_fw1;
14425
14426 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
14427 begin // {
14428 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
14429 begin //{
14430 desr_pend_wr <= 1'b0;
14431 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_49[63:56], 45'b0, `DESR_49[10:0]});
14432 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_49[63:56], 45'b0, `DESR_49[10:0]});
14433 end //}
14434 //if (update_dfesr_w)
14435 if (`ST_ERR_49)
14436 begin //{
14437 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_49[61:55], 55'b0});
14438 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_49[61:55], 55'b0});
14439 end //}
14440 if (update_dsfsr_fw2)
14441 begin //{
14442 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
14443 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_49[3:0]});
14444 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_49[47:0]});
14445
14446 end //}
14447 if (update_isfsr_fw2)
14448 begin //{
14449 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
14450 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_49[2:0]});
14451 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_49[47:0]});
14452
14453 end //}
14454 if (take_err_trap_fw2)
14455 begin //{
14456 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
14457 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
14458 end // }
14459 end // }
14460
14461end //}
14462
14463//removing the addr check as the LSU doesn't flag an invalid_asi_exception
14464//if the addr of diagnostic accesses is not in the valid range. The inst.
14465//still executes. LSU expects that HP won't use addresses in invalid range.
14466
14467always @(negedge (`SPC6.l2clk & ready))
14468begin // {
14469 sync_asi = 1'b0;
14470 ld_data_w <= `ASI_LD_DATA_49;
14471
14472 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_49)
14473 chk_if_asi_ld <= 1'b1;
14474 else
14475 chk_if_asi_ld <= 1'b0;
14476
14477 if (chk_if_asi_ld & `ASI_LD_49)
14478 begin
14479 case (`ASI_49)
14480 8'h66: //ASI_IC_INSTR
14481 begin
14482 //if ((`ASI_ADDR_49 >= 0) & (`ASI_ADDR_49 <= 40'h7ff8))
14483 sync_asi = 1'b1;
14484 end
14485 8'h67: //ASI_IC_TAG
14486 begin
14487 //if ((`ASI_ADDR_49 >= 0) & (`ASI_ADDR_49 <= 40'h7fe0))
14488 sync_asi = 1'b1;
14489 end
14490 8'h46: //ASI_DC_DATA
14491 begin
14492 sync_asi = 1'b1;
14493 end
14494 8'h47: //ASI_DC_TAG
14495 begin
14496 //if ((`ASI_ADDR_49 >= 0) & (`ASI_ADDR_49 <= 40'h7ff0))
14497 sync_asi = 1'b1;
14498 end
14499 8'h48://IRF ECC
14500 begin
14501 //if ((`ASI_ADDR_49 >= 0) & (`ASI_ADDR_49 <= 40'hF8))
14502 sync_asi = 1'b1;
14503 end
14504 8'h49://FRF ECC
14505 begin
14506 //if ((`ASI_ADDR_49 >= 0) & (`ASI_ADDR_49 <= 40'hF8))
14507 sync_asi = 1'b1;
14508 end
14509 8'h4A://STB access, stb ptr can be read also
14510 begin
14511 //if ((`ASI_ADDR_49 >= 0) & (`ASI_ADDR_49 <= 40'h100))
14512 sync_asi = 1'b1;
14513 end
14514 8'h5A://Tick compare reg
14515 begin
14516 //if ((`ASI_ADDR_49 >= 0) & (`ASI_ADDR_49 <= 40'h38))
14517 sync_asi = 1'b1;
14518 end
14519 8'h5B://TSA
14520 begin
14521 //if ((`ASI_ADDR_49 >= 0) & (`ASI_ADDR_49 <= 40'h38))
14522 sync_asi = 1'b1;
14523 end
14524 8'h51://MRA
14525 begin
14526 //if ((`ASI_ADDR_49 >= 0) & (`ASI_ADDR_49 <= 40'h38))
14527 sync_asi = 1'b1;
14528 end
14529 8'h59://scratchpad ecc data read
14530 begin
14531 //if ((`ASI_ADDR_49 >= 0) & (`ASI_ADDR_49 <= 40'h38))
14532 //syncup the ecc data only. For ecc bit 6 is 0.
14533 if (~`SPC6.lsu.lmd.lmq1_pkt[6])
14534 sync_asi = 1'b1;
14535 end
14536 8'h40://cwqcsr,ma_sync access
14537 begin
14538 if ((`ASI_ADDR_49 == 40'h20) || (`ASI_ADDR_49 == 40'h30)
14539 || (`ASI_ADDR_49 == 40'h80)
14540 || ((`ASI_ADDR_49 == 40'ha0) & (`SPU_MA_BUSY_6 == 0) & (`SPU_MA_TID_6 == 1))
14541 )
14542 sync_asi = 1'b1;
14543 end
14544 8'h4C://CLESR, CLFESR access
14545 begin
14546 if ((`ASI_ADDR_49 == 40'h20) || (`ASI_ADDR_49 == 40'h28))
14547 sync_asi = 1'b1;
14548 end
14549 endcase
14550 end
14551
14552 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
14553 begin
14554 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_49, `ASI_ADDR_49, ld_data_w);
14555 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_49, {24'b0, `ASI_ADDR_49}, ld_data_w[63:0]);
14556 end
14557end //}
14558`endif
14559endmodule
14560
14561
14562
14563module err_c6t2 ();
14564`ifndef GATESIM
14565
14566`include "defines.vh"
14567
14568wire [2:0] mycid;
14569wire [2:0] mytid;
14570wire [5:0] mytnum;
14571
14572integer junk;
14573reg ready;
14574reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
14575reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
14576
14577reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
14578reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
14579
14580reg update_dfesr_w;
14581
14582reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
14583reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
14584
14585reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
14586reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
14587
14588reg sync_asi;
14589reg chk_if_asi_ld;
14590reg [63:0] ld_data_w;
14591
14592reg desr_asi_rd, desr_wr, desr_pend_wr;
14593
14594assign mycid = 6;
14595assign mytid = 2;
14596assign mytnum = 6*8 + 2;
14597
14598initial begin //{
14599 desr_asi_rd = 1'b0;
14600 desr_pend_wr = 1'b0;
14601 ready = 0;
14602 @(posedge `SPC6.l2clk) ;
14603 @(posedge `SPC6.l2clk) ;
14604 ready = `PARGS.err_sync_on;
14605end //}
14606
14607`define DSFSR_NEW_IN_50 `SPC6.tlu.ras.dsfsr_2_new_in
14608`define ISFSR_NEW_IN_50 `SPC6.tlu.ras.isfsr_2_new_in
14609
14610`define DSFSR_50 `SPC6.tlu.ras.dsfsr_2
14611`define ISFSR_50 `SPC6.tlu.ras.isfsr_2
14612`define DSFAR_50 `SPC6.tlu.dfd.dsfar_2
14613
14614`define ASI_WR_DSFSR_50 `SPC6.tlu.ras.asi_wr_dsfsr[2]
14615`define ASI_WR_ISFSR_50 `SPC6.tlu.ras.asi_wr_isfsr[2]
14616
14617`define RAS_WRITE_DESR_1st_50 `SPC6.tlu.dfd.ras_write_desr_1st[2]
14618`define RAS_WRITE_DESR_2nd_50 `SPC6.tlu.dfd.ras_write_desr_2nd[2]
14619`define DESR_asi_rd_50 `SPC6.tlu.ras_rd_desr[2]
14620`define DESR_50 `SPC6.tlu.dfd.desr_2
14621
14622`define RAS_WRITE_FESR_50 `SPC6.tlu.ras.write_fesr[2]
14623`define FESR_50 `SPC6.tlu.dfd.fesr_2
14624
14625`define ST_ERR_50 `SPC6.tlu.trl0.take_ftt & `SPC6.tlu.trl0.trap[2]
14626`define SW_REC_ERR_50 `SPC6.tlu.trl0.take_ade & `SPC6.tlu.trl0.trap[2]
14627`define DATA_ACC_ERR_50 `SPC6.tlu.trl0.take_dae & `SPC6.tlu.trl0.trap[2]
14628`define INST_ACC_ERR_50 `SPC6.tlu.trl0.take_iae & `SPC6.tlu.trl0.trap[2]
14629`define INT_PROC_ERR_50 `SPC6.tlu.trl0.take_ipe & `SPC6.tlu.trl0.trap[2]
14630`define HW_CORR_ERR_50 `SPC6.tlu.trl0.take_eer & `SPC6.tlu.trl0.trap[2]
14631`define INST_ACC_MMU_ERR_50 `SPC6.tlu.trl0.take_ime & `SPC6.tlu.trl0.trap[2]
14632`define DATA_ACC_MMU_ERR_50 `SPC6.tlu.trl0.take_dme & `SPC6.tlu.trl0.trap[2]
14633
14634`define LSU_LD_VALID_B `PROBES6.lsu_ld_valid
14635`define LSU_TID_DEC_B_50 `PROBES6.lsu_tid_dec_b[2]
14636`define ASI_LD_50 `SPC6.lsu.lmd.lmq2_pkt[60] & (`SPC6.lsu.lmd.lmq2_pkt[49:48] == 2'b0)
14637`define ASI_50 `SPC6.lsu.lmd.lmq2_pkt[47:40]
14638`define ASI_ADDR_50 `SPC6.lsu.lmd.lmq2_pkt[39:0]
14639`define ASI_LD_DATA_50 `SPC6.lsu_exu_ld_data_b[63:0]
14640`define ASI_LD_COMP_50 tb_top.nas_top.c6.t2.complete_fw2
14641
14642//SPU specific - only one SPU per core
14643`define SPU_MA_BUSY_6 `SPC6.spu.spu_pmu_ma_busy[3]
14644`define SPU_MA_TID_6 `SPC6.spu.spu_pmu_ma_busy[2:0]
14645
14646////////////////////////////////////////////////////////////////////////////////
14647//Capture the status register data from rtl. For disrupting traps,
14648//rtl can modify the contents of the status register before the
14649//trap is taken and intp message is sent to Riesling.
14650//For precise traps, once the status register is updated rtl can't
14651//change the register again before jumping to the trap handler.
14652//So, for deferred and disrupting traps, inform Riesling when the
14653//register is modified while for precise traps wait until Fw2 before
14654//telling Riesling.
14655
14656//TLU asserts the flush and input signals in W stage. I latch them at the
14657//+ve edge of FX4.
14658
14659always @(negedge (`SPC6.l2clk & ready))
14660begin // {
14661 if (`DESR_asi_rd_50)
14662 desr_asi_rd <= 1'b1;
14663 if (desr_asi_rd)
14664 begin
14665 if (desr_wr)
14666 desr_pend_wr <= 1'b1;
14667 if (`ASI_LD_COMP_50[2])
14668 desr_asi_rd <= 1'b0;
14669 end
14670
14671 update_dsfsr_w <= (`DSFSR_NEW_IN_50 != 4'b0) && ~`ASI_WR_DSFSR_50;
14672 update_isfsr_w <= (`ISFSR_NEW_IN_50 != 3'b0) && ~`ASI_WR_ISFSR_50;
14673 desr_wr <= (`RAS_WRITE_DESR_1st_50 || `RAS_WRITE_DESR_2nd_50);
14674 update_dfesr_w <= `RAS_WRITE_FESR_50;
14675 take_err_trap_fx4 <= `ST_ERR_50 | `SW_REC_ERR_50 | `DATA_ACC_ERR_50
14676 | `INST_ACC_ERR_50 | `INT_PROC_ERR_50
14677 | `HW_CORR_ERR_50 | `INST_ACC_MMU_ERR_50
14678 | `DATA_ACC_MMU_ERR_50 ;
14679
14680
14681 if (`ST_ERR_50) int_num_fx4 <= 8'h07;
14682 if (`SW_REC_ERR_50) int_num_fx4 <= 8'h40;
14683 if (`DATA_ACC_ERR_50) int_num_fx4 <= 8'h32;
14684 if (`INST_ACC_ERR_50) int_num_fx4 <= 8'h0A;
14685 if (`INT_PROC_ERR_50) int_num_fx4 <= 8'h29;
14686 if (`HW_CORR_ERR_50) int_num_fx4 <= 8'h63;
14687 if (`INST_ACC_MMU_ERR_50) int_num_fx4 <= 8'h71;
14688 if (`DATA_ACC_MMU_ERR_50) int_num_fx4 <= 8'h72;
14689
14690 update_dsfsr_fx4 <= update_dsfsr_w;
14691 update_dsfsr_fx5 <= update_dsfsr_fx4;
14692 update_dsfsr_fb <= update_dsfsr_fx5;
14693 update_dsfsr_fw <= update_dsfsr_fb;
14694 update_dsfsr_fw1 <= update_dsfsr_fw;
14695 update_dsfsr_fw2 <= update_dsfsr_fw1;
14696
14697 update_isfsr_fx4 <= update_isfsr_w;
14698 update_isfsr_fx5 <= update_isfsr_fx4;
14699 update_isfsr_fb <= update_isfsr_fx5;
14700 update_isfsr_fw <= update_isfsr_fb;
14701 update_isfsr_fw1 <= update_isfsr_fw;
14702 update_isfsr_fw2 <= update_isfsr_fw1;
14703
14704 take_err_trap_fx5 <= take_err_trap_fx4;
14705 take_err_trap_fb <= take_err_trap_fx5;
14706 take_err_trap_fw <= take_err_trap_fb;
14707 take_err_trap_fw1 <= take_err_trap_fw;
14708 take_err_trap_fw2 <= take_err_trap_fw1;
14709
14710 int_num_fx5 <= int_num_fx4;
14711 int_num_fb <= int_num_fx5;
14712 int_num_fw <= int_num_fb;
14713 int_num_fw1 <= int_num_fw;
14714 int_num_fw2 <= int_num_fw1;
14715
14716 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
14717 begin // {
14718 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
14719 begin //{
14720 desr_pend_wr <= 1'b0;
14721 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_50[63:56], 45'b0, `DESR_50[10:0]});
14722 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_50[63:56], 45'b0, `DESR_50[10:0]});
14723 end //}
14724 //if (update_dfesr_w)
14725 if (`ST_ERR_50)
14726 begin //{
14727 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_50[61:55], 55'b0});
14728 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_50[61:55], 55'b0});
14729 end //}
14730 if (update_dsfsr_fw2)
14731 begin //{
14732 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
14733 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_50[3:0]});
14734 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_50[47:0]});
14735
14736 end //}
14737 if (update_isfsr_fw2)
14738 begin //{
14739 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
14740 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_50[2:0]});
14741 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_50[47:0]});
14742
14743 end //}
14744 if (take_err_trap_fw2)
14745 begin //{
14746 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
14747 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
14748 end // }
14749 end // }
14750
14751end //}
14752
14753//removing the addr check as the LSU doesn't flag an invalid_asi_exception
14754//if the addr of diagnostic accesses is not in the valid range. The inst.
14755//still executes. LSU expects that HP won't use addresses in invalid range.
14756
14757always @(negedge (`SPC6.l2clk & ready))
14758begin // {
14759 sync_asi = 1'b0;
14760 ld_data_w <= `ASI_LD_DATA_50;
14761
14762 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_50)
14763 chk_if_asi_ld <= 1'b1;
14764 else
14765 chk_if_asi_ld <= 1'b0;
14766
14767 if (chk_if_asi_ld & `ASI_LD_50)
14768 begin
14769 case (`ASI_50)
14770 8'h66: //ASI_IC_INSTR
14771 begin
14772 //if ((`ASI_ADDR_50 >= 0) & (`ASI_ADDR_50 <= 40'h7ff8))
14773 sync_asi = 1'b1;
14774 end
14775 8'h67: //ASI_IC_TAG
14776 begin
14777 //if ((`ASI_ADDR_50 >= 0) & (`ASI_ADDR_50 <= 40'h7fe0))
14778 sync_asi = 1'b1;
14779 end
14780 8'h46: //ASI_DC_DATA
14781 begin
14782 sync_asi = 1'b1;
14783 end
14784 8'h47: //ASI_DC_TAG
14785 begin
14786 //if ((`ASI_ADDR_50 >= 0) & (`ASI_ADDR_50 <= 40'h7ff0))
14787 sync_asi = 1'b1;
14788 end
14789 8'h48://IRF ECC
14790 begin
14791 //if ((`ASI_ADDR_50 >= 0) & (`ASI_ADDR_50 <= 40'hF8))
14792 sync_asi = 1'b1;
14793 end
14794 8'h49://FRF ECC
14795 begin
14796 //if ((`ASI_ADDR_50 >= 0) & (`ASI_ADDR_50 <= 40'hF8))
14797 sync_asi = 1'b1;
14798 end
14799 8'h4A://STB access, stb ptr can be read also
14800 begin
14801 //if ((`ASI_ADDR_50 >= 0) & (`ASI_ADDR_50 <= 40'h100))
14802 sync_asi = 1'b1;
14803 end
14804 8'h5A://Tick compare reg
14805 begin
14806 //if ((`ASI_ADDR_50 >= 0) & (`ASI_ADDR_50 <= 40'h38))
14807 sync_asi = 1'b1;
14808 end
14809 8'h5B://TSA
14810 begin
14811 //if ((`ASI_ADDR_50 >= 0) & (`ASI_ADDR_50 <= 40'h38))
14812 sync_asi = 1'b1;
14813 end
14814 8'h51://MRA
14815 begin
14816 //if ((`ASI_ADDR_50 >= 0) & (`ASI_ADDR_50 <= 40'h38))
14817 sync_asi = 1'b1;
14818 end
14819 8'h59://scratchpad ecc data read
14820 begin
14821 //if ((`ASI_ADDR_50 >= 0) & (`ASI_ADDR_50 <= 40'h38))
14822 //syncup the ecc data only. For ecc bit 6 is 0.
14823 if (~`SPC6.lsu.lmd.lmq2_pkt[6])
14824 sync_asi = 1'b1;
14825 end
14826 8'h40://cwqcsr,ma_sync access
14827 begin
14828 if ((`ASI_ADDR_50 == 40'h20) || (`ASI_ADDR_50 == 40'h30)
14829 || (`ASI_ADDR_50 == 40'h80)
14830 || ((`ASI_ADDR_50 == 40'ha0) & (`SPU_MA_BUSY_6 == 0) & (`SPU_MA_TID_6 == 2))
14831 )
14832 sync_asi = 1'b1;
14833 end
14834 8'h4C://CLESR, CLFESR access
14835 begin
14836 if ((`ASI_ADDR_50 == 40'h20) || (`ASI_ADDR_50 == 40'h28))
14837 sync_asi = 1'b1;
14838 end
14839 endcase
14840 end
14841
14842 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
14843 begin
14844 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_50, `ASI_ADDR_50, ld_data_w);
14845 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_50, {24'b0, `ASI_ADDR_50}, ld_data_w[63:0]);
14846 end
14847end //}
14848`endif
14849endmodule
14850
14851
14852
14853module err_c6t3 ();
14854`ifndef GATESIM
14855
14856`include "defines.vh"
14857
14858wire [2:0] mycid;
14859wire [2:0] mytid;
14860wire [5:0] mytnum;
14861
14862integer junk;
14863reg ready;
14864reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
14865reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
14866
14867reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
14868reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
14869
14870reg update_dfesr_w;
14871
14872reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
14873reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
14874
14875reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
14876reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
14877
14878reg sync_asi;
14879reg chk_if_asi_ld;
14880reg [63:0] ld_data_w;
14881
14882reg desr_asi_rd, desr_wr, desr_pend_wr;
14883
14884assign mycid = 6;
14885assign mytid = 3;
14886assign mytnum = 6*8 + 3;
14887
14888initial begin //{
14889 desr_asi_rd = 1'b0;
14890 desr_pend_wr = 1'b0;
14891 ready = 0;
14892 @(posedge `SPC6.l2clk) ;
14893 @(posedge `SPC6.l2clk) ;
14894 ready = `PARGS.err_sync_on;
14895end //}
14896
14897`define DSFSR_NEW_IN_51 `SPC6.tlu.ras.dsfsr_3_new_in
14898`define ISFSR_NEW_IN_51 `SPC6.tlu.ras.isfsr_3_new_in
14899
14900`define DSFSR_51 `SPC6.tlu.ras.dsfsr_3
14901`define ISFSR_51 `SPC6.tlu.ras.isfsr_3
14902`define DSFAR_51 `SPC6.tlu.dfd.dsfar_3
14903
14904`define ASI_WR_DSFSR_51 `SPC6.tlu.ras.asi_wr_dsfsr[3]
14905`define ASI_WR_ISFSR_51 `SPC6.tlu.ras.asi_wr_isfsr[3]
14906
14907`define RAS_WRITE_DESR_1st_51 `SPC6.tlu.dfd.ras_write_desr_1st[3]
14908`define RAS_WRITE_DESR_2nd_51 `SPC6.tlu.dfd.ras_write_desr_2nd[3]
14909`define DESR_asi_rd_51 `SPC6.tlu.ras_rd_desr[3]
14910`define DESR_51 `SPC6.tlu.dfd.desr_3
14911
14912`define RAS_WRITE_FESR_51 `SPC6.tlu.ras.write_fesr[3]
14913`define FESR_51 `SPC6.tlu.dfd.fesr_3
14914
14915`define ST_ERR_51 `SPC6.tlu.trl0.take_ftt & `SPC6.tlu.trl0.trap[3]
14916`define SW_REC_ERR_51 `SPC6.tlu.trl0.take_ade & `SPC6.tlu.trl0.trap[3]
14917`define DATA_ACC_ERR_51 `SPC6.tlu.trl0.take_dae & `SPC6.tlu.trl0.trap[3]
14918`define INST_ACC_ERR_51 `SPC6.tlu.trl0.take_iae & `SPC6.tlu.trl0.trap[3]
14919`define INT_PROC_ERR_51 `SPC6.tlu.trl0.take_ipe & `SPC6.tlu.trl0.trap[3]
14920`define HW_CORR_ERR_51 `SPC6.tlu.trl0.take_eer & `SPC6.tlu.trl0.trap[3]
14921`define INST_ACC_MMU_ERR_51 `SPC6.tlu.trl0.take_ime & `SPC6.tlu.trl0.trap[3]
14922`define DATA_ACC_MMU_ERR_51 `SPC6.tlu.trl0.take_dme & `SPC6.tlu.trl0.trap[3]
14923
14924`define LSU_LD_VALID_B `PROBES6.lsu_ld_valid
14925`define LSU_TID_DEC_B_51 `PROBES6.lsu_tid_dec_b[3]
14926`define ASI_LD_51 `SPC6.lsu.lmd.lmq3_pkt[60] & (`SPC6.lsu.lmd.lmq3_pkt[49:48] == 2'b0)
14927`define ASI_51 `SPC6.lsu.lmd.lmq3_pkt[47:40]
14928`define ASI_ADDR_51 `SPC6.lsu.lmd.lmq3_pkt[39:0]
14929`define ASI_LD_DATA_51 `SPC6.lsu_exu_ld_data_b[63:0]
14930`define ASI_LD_COMP_51 tb_top.nas_top.c6.t3.complete_fw2
14931
14932//SPU specific - only one SPU per core
14933`define SPU_MA_BUSY_6 `SPC6.spu.spu_pmu_ma_busy[3]
14934`define SPU_MA_TID_6 `SPC6.spu.spu_pmu_ma_busy[2:0]
14935
14936////////////////////////////////////////////////////////////////////////////////
14937//Capture the status register data from rtl. For disrupting traps,
14938//rtl can modify the contents of the status register before the
14939//trap is taken and intp message is sent to Riesling.
14940//For precise traps, once the status register is updated rtl can't
14941//change the register again before jumping to the trap handler.
14942//So, for deferred and disrupting traps, inform Riesling when the
14943//register is modified while for precise traps wait until Fw2 before
14944//telling Riesling.
14945
14946//TLU asserts the flush and input signals in W stage. I latch them at the
14947//+ve edge of FX4.
14948
14949always @(negedge (`SPC6.l2clk & ready))
14950begin // {
14951 if (`DESR_asi_rd_51)
14952 desr_asi_rd <= 1'b1;
14953 if (desr_asi_rd)
14954 begin
14955 if (desr_wr)
14956 desr_pend_wr <= 1'b1;
14957 if (`ASI_LD_COMP_51[2])
14958 desr_asi_rd <= 1'b0;
14959 end
14960
14961 update_dsfsr_w <= (`DSFSR_NEW_IN_51 != 4'b0) && ~`ASI_WR_DSFSR_51;
14962 update_isfsr_w <= (`ISFSR_NEW_IN_51 != 3'b0) && ~`ASI_WR_ISFSR_51;
14963 desr_wr <= (`RAS_WRITE_DESR_1st_51 || `RAS_WRITE_DESR_2nd_51);
14964 update_dfesr_w <= `RAS_WRITE_FESR_51;
14965 take_err_trap_fx4 <= `ST_ERR_51 | `SW_REC_ERR_51 | `DATA_ACC_ERR_51
14966 | `INST_ACC_ERR_51 | `INT_PROC_ERR_51
14967 | `HW_CORR_ERR_51 | `INST_ACC_MMU_ERR_51
14968 | `DATA_ACC_MMU_ERR_51 ;
14969
14970
14971 if (`ST_ERR_51) int_num_fx4 <= 8'h07;
14972 if (`SW_REC_ERR_51) int_num_fx4 <= 8'h40;
14973 if (`DATA_ACC_ERR_51) int_num_fx4 <= 8'h32;
14974 if (`INST_ACC_ERR_51) int_num_fx4 <= 8'h0A;
14975 if (`INT_PROC_ERR_51) int_num_fx4 <= 8'h29;
14976 if (`HW_CORR_ERR_51) int_num_fx4 <= 8'h63;
14977 if (`INST_ACC_MMU_ERR_51) int_num_fx4 <= 8'h71;
14978 if (`DATA_ACC_MMU_ERR_51) int_num_fx4 <= 8'h72;
14979
14980 update_dsfsr_fx4 <= update_dsfsr_w;
14981 update_dsfsr_fx5 <= update_dsfsr_fx4;
14982 update_dsfsr_fb <= update_dsfsr_fx5;
14983 update_dsfsr_fw <= update_dsfsr_fb;
14984 update_dsfsr_fw1 <= update_dsfsr_fw;
14985 update_dsfsr_fw2 <= update_dsfsr_fw1;
14986
14987 update_isfsr_fx4 <= update_isfsr_w;
14988 update_isfsr_fx5 <= update_isfsr_fx4;
14989 update_isfsr_fb <= update_isfsr_fx5;
14990 update_isfsr_fw <= update_isfsr_fb;
14991 update_isfsr_fw1 <= update_isfsr_fw;
14992 update_isfsr_fw2 <= update_isfsr_fw1;
14993
14994 take_err_trap_fx5 <= take_err_trap_fx4;
14995 take_err_trap_fb <= take_err_trap_fx5;
14996 take_err_trap_fw <= take_err_trap_fb;
14997 take_err_trap_fw1 <= take_err_trap_fw;
14998 take_err_trap_fw2 <= take_err_trap_fw1;
14999
15000 int_num_fx5 <= int_num_fx4;
15001 int_num_fb <= int_num_fx5;
15002 int_num_fw <= int_num_fb;
15003 int_num_fw1 <= int_num_fw;
15004 int_num_fw2 <= int_num_fw1;
15005
15006 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
15007 begin // {
15008 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
15009 begin //{
15010 desr_pend_wr <= 1'b0;
15011 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_51[63:56], 45'b0, `DESR_51[10:0]});
15012 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_51[63:56], 45'b0, `DESR_51[10:0]});
15013 end //}
15014 //if (update_dfesr_w)
15015 if (`ST_ERR_51)
15016 begin //{
15017 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_51[61:55], 55'b0});
15018 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_51[61:55], 55'b0});
15019 end //}
15020 if (update_dsfsr_fw2)
15021 begin //{
15022 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
15023 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_51[3:0]});
15024 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_51[47:0]});
15025
15026 end //}
15027 if (update_isfsr_fw2)
15028 begin //{
15029 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
15030 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_51[2:0]});
15031 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_51[47:0]});
15032
15033 end //}
15034 if (take_err_trap_fw2)
15035 begin //{
15036 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
15037 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
15038 end // }
15039 end // }
15040
15041end //}
15042
15043//removing the addr check as the LSU doesn't flag an invalid_asi_exception
15044//if the addr of diagnostic accesses is not in the valid range. The inst.
15045//still executes. LSU expects that HP won't use addresses in invalid range.
15046
15047always @(negedge (`SPC6.l2clk & ready))
15048begin // {
15049 sync_asi = 1'b0;
15050 ld_data_w <= `ASI_LD_DATA_51;
15051
15052 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_51)
15053 chk_if_asi_ld <= 1'b1;
15054 else
15055 chk_if_asi_ld <= 1'b0;
15056
15057 if (chk_if_asi_ld & `ASI_LD_51)
15058 begin
15059 case (`ASI_51)
15060 8'h66: //ASI_IC_INSTR
15061 begin
15062 //if ((`ASI_ADDR_51 >= 0) & (`ASI_ADDR_51 <= 40'h7ff8))
15063 sync_asi = 1'b1;
15064 end
15065 8'h67: //ASI_IC_TAG
15066 begin
15067 //if ((`ASI_ADDR_51 >= 0) & (`ASI_ADDR_51 <= 40'h7fe0))
15068 sync_asi = 1'b1;
15069 end
15070 8'h46: //ASI_DC_DATA
15071 begin
15072 sync_asi = 1'b1;
15073 end
15074 8'h47: //ASI_DC_TAG
15075 begin
15076 //if ((`ASI_ADDR_51 >= 0) & (`ASI_ADDR_51 <= 40'h7ff0))
15077 sync_asi = 1'b1;
15078 end
15079 8'h48://IRF ECC
15080 begin
15081 //if ((`ASI_ADDR_51 >= 0) & (`ASI_ADDR_51 <= 40'hF8))
15082 sync_asi = 1'b1;
15083 end
15084 8'h49://FRF ECC
15085 begin
15086 //if ((`ASI_ADDR_51 >= 0) & (`ASI_ADDR_51 <= 40'hF8))
15087 sync_asi = 1'b1;
15088 end
15089 8'h4A://STB access, stb ptr can be read also
15090 begin
15091 //if ((`ASI_ADDR_51 >= 0) & (`ASI_ADDR_51 <= 40'h100))
15092 sync_asi = 1'b1;
15093 end
15094 8'h5A://Tick compare reg
15095 begin
15096 //if ((`ASI_ADDR_51 >= 0) & (`ASI_ADDR_51 <= 40'h38))
15097 sync_asi = 1'b1;
15098 end
15099 8'h5B://TSA
15100 begin
15101 //if ((`ASI_ADDR_51 >= 0) & (`ASI_ADDR_51 <= 40'h38))
15102 sync_asi = 1'b1;
15103 end
15104 8'h51://MRA
15105 begin
15106 //if ((`ASI_ADDR_51 >= 0) & (`ASI_ADDR_51 <= 40'h38))
15107 sync_asi = 1'b1;
15108 end
15109 8'h59://scratchpad ecc data read
15110 begin
15111 //if ((`ASI_ADDR_51 >= 0) & (`ASI_ADDR_51 <= 40'h38))
15112 //syncup the ecc data only. For ecc bit 6 is 0.
15113 if (~`SPC6.lsu.lmd.lmq3_pkt[6])
15114 sync_asi = 1'b1;
15115 end
15116 8'h40://cwqcsr,ma_sync access
15117 begin
15118 if ((`ASI_ADDR_51 == 40'h20) || (`ASI_ADDR_51 == 40'h30)
15119 || (`ASI_ADDR_51 == 40'h80)
15120 || ((`ASI_ADDR_51 == 40'ha0) & (`SPU_MA_BUSY_6 == 0) & (`SPU_MA_TID_6 == 3))
15121 )
15122 sync_asi = 1'b1;
15123 end
15124 8'h4C://CLESR, CLFESR access
15125 begin
15126 if ((`ASI_ADDR_51 == 40'h20) || (`ASI_ADDR_51 == 40'h28))
15127 sync_asi = 1'b1;
15128 end
15129 endcase
15130 end
15131
15132 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
15133 begin
15134 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_51, `ASI_ADDR_51, ld_data_w);
15135 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_51, {24'b0, `ASI_ADDR_51}, ld_data_w[63:0]);
15136 end
15137end //}
15138`endif
15139endmodule
15140
15141
15142
15143module err_c6t4 ();
15144`ifndef GATESIM
15145
15146`include "defines.vh"
15147
15148wire [2:0] mycid;
15149wire [2:0] mytid;
15150wire [5:0] mytnum;
15151
15152integer junk;
15153reg ready;
15154reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
15155reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
15156
15157reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
15158reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
15159
15160reg update_dfesr_w;
15161
15162reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
15163reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
15164
15165reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
15166reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
15167
15168reg sync_asi;
15169reg chk_if_asi_ld;
15170reg [63:0] ld_data_w;
15171
15172reg desr_asi_rd, desr_wr, desr_pend_wr;
15173
15174assign mycid = 6;
15175assign mytid = 4;
15176assign mytnum = 6*8 + 4;
15177
15178initial begin //{
15179 desr_asi_rd = 1'b0;
15180 desr_pend_wr = 1'b0;
15181 ready = 0;
15182 @(posedge `SPC6.l2clk) ;
15183 @(posedge `SPC6.l2clk) ;
15184 ready = `PARGS.err_sync_on;
15185end //}
15186
15187`define DSFSR_NEW_IN_52 `SPC6.tlu.ras.dsfsr_4_new_in
15188`define ISFSR_NEW_IN_52 `SPC6.tlu.ras.isfsr_4_new_in
15189
15190`define DSFSR_52 `SPC6.tlu.ras.dsfsr_4
15191`define ISFSR_52 `SPC6.tlu.ras.isfsr_4
15192`define DSFAR_52 `SPC6.tlu.dfd.dsfar_4
15193
15194`define ASI_WR_DSFSR_52 `SPC6.tlu.ras.asi_wr_dsfsr[4]
15195`define ASI_WR_ISFSR_52 `SPC6.tlu.ras.asi_wr_isfsr[4]
15196
15197`define RAS_WRITE_DESR_1st_52 `SPC6.tlu.dfd.ras_write_desr_1st[4]
15198`define RAS_WRITE_DESR_2nd_52 `SPC6.tlu.dfd.ras_write_desr_2nd[4]
15199`define DESR_asi_rd_52 `SPC6.tlu.ras_rd_desr[4]
15200`define DESR_52 `SPC6.tlu.dfd.desr_4
15201
15202`define RAS_WRITE_FESR_52 `SPC6.tlu.ras.write_fesr[4]
15203`define FESR_52 `SPC6.tlu.dfd.fesr_4
15204
15205`define ST_ERR_52 `SPC6.tlu.trl1.take_ftt & `SPC6.tlu.trl1.trap[0]
15206`define SW_REC_ERR_52 `SPC6.tlu.trl1.take_ade & `SPC6.tlu.trl1.trap[0]
15207`define DATA_ACC_ERR_52 `SPC6.tlu.trl1.take_dae & `SPC6.tlu.trl1.trap[0]
15208`define INST_ACC_ERR_52 `SPC6.tlu.trl1.take_iae & `SPC6.tlu.trl1.trap[0]
15209`define INT_PROC_ERR_52 `SPC6.tlu.trl1.take_ipe & `SPC6.tlu.trl1.trap[0]
15210`define HW_CORR_ERR_52 `SPC6.tlu.trl1.take_eer & `SPC6.tlu.trl1.trap[0]
15211`define INST_ACC_MMU_ERR_52 `SPC6.tlu.trl1.take_ime & `SPC6.tlu.trl1.trap[0]
15212`define DATA_ACC_MMU_ERR_52 `SPC6.tlu.trl1.take_dme & `SPC6.tlu.trl1.trap[0]
15213
15214`define LSU_LD_VALID_B `PROBES6.lsu_ld_valid
15215`define LSU_TID_DEC_B_52 `PROBES6.lsu_tid_dec_b[4]
15216`define ASI_LD_52 `SPC6.lsu.lmd.lmq4_pkt[60] & (`SPC6.lsu.lmd.lmq4_pkt[49:48] == 2'b0)
15217`define ASI_52 `SPC6.lsu.lmd.lmq4_pkt[47:40]
15218`define ASI_ADDR_52 `SPC6.lsu.lmd.lmq4_pkt[39:0]
15219`define ASI_LD_DATA_52 `SPC6.lsu_exu_ld_data_b[63:0]
15220`define ASI_LD_COMP_52 tb_top.nas_top.c6.t4.complete_fw2
15221
15222//SPU specific - only one SPU per core
15223`define SPU_MA_BUSY_6 `SPC6.spu.spu_pmu_ma_busy[3]
15224`define SPU_MA_TID_6 `SPC6.spu.spu_pmu_ma_busy[2:0]
15225
15226////////////////////////////////////////////////////////////////////////////////
15227//Capture the status register data from rtl. For disrupting traps,
15228//rtl can modify the contents of the status register before the
15229//trap is taken and intp message is sent to Riesling.
15230//For precise traps, once the status register is updated rtl can't
15231//change the register again before jumping to the trap handler.
15232//So, for deferred and disrupting traps, inform Riesling when the
15233//register is modified while for precise traps wait until Fw2 before
15234//telling Riesling.
15235
15236//TLU asserts the flush and input signals in W stage. I latch them at the
15237//+ve edge of FX4.
15238
15239always @(negedge (`SPC6.l2clk & ready))
15240begin // {
15241 if (`DESR_asi_rd_52)
15242 desr_asi_rd <= 1'b1;
15243 if (desr_asi_rd)
15244 begin
15245 if (desr_wr)
15246 desr_pend_wr <= 1'b1;
15247 if (`ASI_LD_COMP_52[2])
15248 desr_asi_rd <= 1'b0;
15249 end
15250
15251 update_dsfsr_w <= (`DSFSR_NEW_IN_52 != 4'b0) && ~`ASI_WR_DSFSR_52;
15252 update_isfsr_w <= (`ISFSR_NEW_IN_52 != 3'b0) && ~`ASI_WR_ISFSR_52;
15253 desr_wr <= (`RAS_WRITE_DESR_1st_52 || `RAS_WRITE_DESR_2nd_52);
15254 update_dfesr_w <= `RAS_WRITE_FESR_52;
15255 take_err_trap_fx4 <= `ST_ERR_52 | `SW_REC_ERR_52 | `DATA_ACC_ERR_52
15256 | `INST_ACC_ERR_52 | `INT_PROC_ERR_52
15257 | `HW_CORR_ERR_52 | `INST_ACC_MMU_ERR_52
15258 | `DATA_ACC_MMU_ERR_52 ;
15259
15260
15261 if (`ST_ERR_52) int_num_fx4 <= 8'h07;
15262 if (`SW_REC_ERR_52) int_num_fx4 <= 8'h40;
15263 if (`DATA_ACC_ERR_52) int_num_fx4 <= 8'h32;
15264 if (`INST_ACC_ERR_52) int_num_fx4 <= 8'h0A;
15265 if (`INT_PROC_ERR_52) int_num_fx4 <= 8'h29;
15266 if (`HW_CORR_ERR_52) int_num_fx4 <= 8'h63;
15267 if (`INST_ACC_MMU_ERR_52) int_num_fx4 <= 8'h71;
15268 if (`DATA_ACC_MMU_ERR_52) int_num_fx4 <= 8'h72;
15269
15270 update_dsfsr_fx4 <= update_dsfsr_w;
15271 update_dsfsr_fx5 <= update_dsfsr_fx4;
15272 update_dsfsr_fb <= update_dsfsr_fx5;
15273 update_dsfsr_fw <= update_dsfsr_fb;
15274 update_dsfsr_fw1 <= update_dsfsr_fw;
15275 update_dsfsr_fw2 <= update_dsfsr_fw1;
15276
15277 update_isfsr_fx4 <= update_isfsr_w;
15278 update_isfsr_fx5 <= update_isfsr_fx4;
15279 update_isfsr_fb <= update_isfsr_fx5;
15280 update_isfsr_fw <= update_isfsr_fb;
15281 update_isfsr_fw1 <= update_isfsr_fw;
15282 update_isfsr_fw2 <= update_isfsr_fw1;
15283
15284 take_err_trap_fx5 <= take_err_trap_fx4;
15285 take_err_trap_fb <= take_err_trap_fx5;
15286 take_err_trap_fw <= take_err_trap_fb;
15287 take_err_trap_fw1 <= take_err_trap_fw;
15288 take_err_trap_fw2 <= take_err_trap_fw1;
15289
15290 int_num_fx5 <= int_num_fx4;
15291 int_num_fb <= int_num_fx5;
15292 int_num_fw <= int_num_fb;
15293 int_num_fw1 <= int_num_fw;
15294 int_num_fw2 <= int_num_fw1;
15295
15296 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
15297 begin // {
15298 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
15299 begin //{
15300 desr_pend_wr <= 1'b0;
15301 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_52[63:56], 45'b0, `DESR_52[10:0]});
15302 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_52[63:56], 45'b0, `DESR_52[10:0]});
15303 end //}
15304 //if (update_dfesr_w)
15305 if (`ST_ERR_52)
15306 begin //{
15307 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_52[61:55], 55'b0});
15308 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_52[61:55], 55'b0});
15309 end //}
15310 if (update_dsfsr_fw2)
15311 begin //{
15312 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
15313 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_52[3:0]});
15314 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_52[47:0]});
15315
15316 end //}
15317 if (update_isfsr_fw2)
15318 begin //{
15319 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
15320 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_52[2:0]});
15321 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_52[47:0]});
15322
15323 end //}
15324 if (take_err_trap_fw2)
15325 begin //{
15326 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
15327 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
15328 end // }
15329 end // }
15330
15331end //}
15332
15333//removing the addr check as the LSU doesn't flag an invalid_asi_exception
15334//if the addr of diagnostic accesses is not in the valid range. The inst.
15335//still executes. LSU expects that HP won't use addresses in invalid range.
15336
15337always @(negedge (`SPC6.l2clk & ready))
15338begin // {
15339 sync_asi = 1'b0;
15340 ld_data_w <= `ASI_LD_DATA_52;
15341
15342 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_52)
15343 chk_if_asi_ld <= 1'b1;
15344 else
15345 chk_if_asi_ld <= 1'b0;
15346
15347 if (chk_if_asi_ld & `ASI_LD_52)
15348 begin
15349 case (`ASI_52)
15350 8'h66: //ASI_IC_INSTR
15351 begin
15352 //if ((`ASI_ADDR_52 >= 0) & (`ASI_ADDR_52 <= 40'h7ff8))
15353 sync_asi = 1'b1;
15354 end
15355 8'h67: //ASI_IC_TAG
15356 begin
15357 //if ((`ASI_ADDR_52 >= 0) & (`ASI_ADDR_52 <= 40'h7fe0))
15358 sync_asi = 1'b1;
15359 end
15360 8'h46: //ASI_DC_DATA
15361 begin
15362 sync_asi = 1'b1;
15363 end
15364 8'h47: //ASI_DC_TAG
15365 begin
15366 //if ((`ASI_ADDR_52 >= 0) & (`ASI_ADDR_52 <= 40'h7ff0))
15367 sync_asi = 1'b1;
15368 end
15369 8'h48://IRF ECC
15370 begin
15371 //if ((`ASI_ADDR_52 >= 0) & (`ASI_ADDR_52 <= 40'hF8))
15372 sync_asi = 1'b1;
15373 end
15374 8'h49://FRF ECC
15375 begin
15376 //if ((`ASI_ADDR_52 >= 0) & (`ASI_ADDR_52 <= 40'hF8))
15377 sync_asi = 1'b1;
15378 end
15379 8'h4A://STB access, stb ptr can be read also
15380 begin
15381 //if ((`ASI_ADDR_52 >= 0) & (`ASI_ADDR_52 <= 40'h100))
15382 sync_asi = 1'b1;
15383 end
15384 8'h5A://Tick compare reg
15385 begin
15386 //if ((`ASI_ADDR_52 >= 0) & (`ASI_ADDR_52 <= 40'h38))
15387 sync_asi = 1'b1;
15388 end
15389 8'h5B://TSA
15390 begin
15391 //if ((`ASI_ADDR_52 >= 0) & (`ASI_ADDR_52 <= 40'h38))
15392 sync_asi = 1'b1;
15393 end
15394 8'h51://MRA
15395 begin
15396 //if ((`ASI_ADDR_52 >= 0) & (`ASI_ADDR_52 <= 40'h38))
15397 sync_asi = 1'b1;
15398 end
15399 8'h59://scratchpad ecc data read
15400 begin
15401 //if ((`ASI_ADDR_52 >= 0) & (`ASI_ADDR_52 <= 40'h38))
15402 //syncup the ecc data only. For ecc bit 6 is 0.
15403 if (~`SPC6.lsu.lmd.lmq4_pkt[6])
15404 sync_asi = 1'b1;
15405 end
15406 8'h40://cwqcsr,ma_sync access
15407 begin
15408 if ((`ASI_ADDR_52 == 40'h20) || (`ASI_ADDR_52 == 40'h30)
15409 || (`ASI_ADDR_52 == 40'h80)
15410 || ((`ASI_ADDR_52 == 40'ha0) & (`SPU_MA_BUSY_6 == 0) & (`SPU_MA_TID_6 == 4))
15411 )
15412 sync_asi = 1'b1;
15413 end
15414 8'h4C://CLESR, CLFESR access
15415 begin
15416 if ((`ASI_ADDR_52 == 40'h20) || (`ASI_ADDR_52 == 40'h28))
15417 sync_asi = 1'b1;
15418 end
15419 endcase
15420 end
15421
15422 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
15423 begin
15424 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_52, `ASI_ADDR_52, ld_data_w);
15425 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_52, {24'b0, `ASI_ADDR_52}, ld_data_w[63:0]);
15426 end
15427end //}
15428`endif
15429endmodule
15430
15431
15432
15433module err_c6t5 ();
15434`ifndef GATESIM
15435
15436`include "defines.vh"
15437
15438wire [2:0] mycid;
15439wire [2:0] mytid;
15440wire [5:0] mytnum;
15441
15442integer junk;
15443reg ready;
15444reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
15445reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
15446
15447reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
15448reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
15449
15450reg update_dfesr_w;
15451
15452reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
15453reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
15454
15455reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
15456reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
15457
15458reg sync_asi;
15459reg chk_if_asi_ld;
15460reg [63:0] ld_data_w;
15461
15462reg desr_asi_rd, desr_wr, desr_pend_wr;
15463
15464assign mycid = 6;
15465assign mytid = 5;
15466assign mytnum = 6*8 + 5;
15467
15468initial begin //{
15469 desr_asi_rd = 1'b0;
15470 desr_pend_wr = 1'b0;
15471 ready = 0;
15472 @(posedge `SPC6.l2clk) ;
15473 @(posedge `SPC6.l2clk) ;
15474 ready = `PARGS.err_sync_on;
15475end //}
15476
15477`define DSFSR_NEW_IN_53 `SPC6.tlu.ras.dsfsr_5_new_in
15478`define ISFSR_NEW_IN_53 `SPC6.tlu.ras.isfsr_5_new_in
15479
15480`define DSFSR_53 `SPC6.tlu.ras.dsfsr_5
15481`define ISFSR_53 `SPC6.tlu.ras.isfsr_5
15482`define DSFAR_53 `SPC6.tlu.dfd.dsfar_5
15483
15484`define ASI_WR_DSFSR_53 `SPC6.tlu.ras.asi_wr_dsfsr[5]
15485`define ASI_WR_ISFSR_53 `SPC6.tlu.ras.asi_wr_isfsr[5]
15486
15487`define RAS_WRITE_DESR_1st_53 `SPC6.tlu.dfd.ras_write_desr_1st[5]
15488`define RAS_WRITE_DESR_2nd_53 `SPC6.tlu.dfd.ras_write_desr_2nd[5]
15489`define DESR_asi_rd_53 `SPC6.tlu.ras_rd_desr[5]
15490`define DESR_53 `SPC6.tlu.dfd.desr_5
15491
15492`define RAS_WRITE_FESR_53 `SPC6.tlu.ras.write_fesr[5]
15493`define FESR_53 `SPC6.tlu.dfd.fesr_5
15494
15495`define ST_ERR_53 `SPC6.tlu.trl1.take_ftt & `SPC6.tlu.trl1.trap[1]
15496`define SW_REC_ERR_53 `SPC6.tlu.trl1.take_ade & `SPC6.tlu.trl1.trap[1]
15497`define DATA_ACC_ERR_53 `SPC6.tlu.trl1.take_dae & `SPC6.tlu.trl1.trap[1]
15498`define INST_ACC_ERR_53 `SPC6.tlu.trl1.take_iae & `SPC6.tlu.trl1.trap[1]
15499`define INT_PROC_ERR_53 `SPC6.tlu.trl1.take_ipe & `SPC6.tlu.trl1.trap[1]
15500`define HW_CORR_ERR_53 `SPC6.tlu.trl1.take_eer & `SPC6.tlu.trl1.trap[1]
15501`define INST_ACC_MMU_ERR_53 `SPC6.tlu.trl1.take_ime & `SPC6.tlu.trl1.trap[1]
15502`define DATA_ACC_MMU_ERR_53 `SPC6.tlu.trl1.take_dme & `SPC6.tlu.trl1.trap[1]
15503
15504`define LSU_LD_VALID_B `PROBES6.lsu_ld_valid
15505`define LSU_TID_DEC_B_53 `PROBES6.lsu_tid_dec_b[5]
15506`define ASI_LD_53 `SPC6.lsu.lmd.lmq5_pkt[60] & (`SPC6.lsu.lmd.lmq5_pkt[49:48] == 2'b0)
15507`define ASI_53 `SPC6.lsu.lmd.lmq5_pkt[47:40]
15508`define ASI_ADDR_53 `SPC6.lsu.lmd.lmq5_pkt[39:0]
15509`define ASI_LD_DATA_53 `SPC6.lsu_exu_ld_data_b[63:0]
15510`define ASI_LD_COMP_53 tb_top.nas_top.c6.t5.complete_fw2
15511
15512//SPU specific - only one SPU per core
15513`define SPU_MA_BUSY_6 `SPC6.spu.spu_pmu_ma_busy[3]
15514`define SPU_MA_TID_6 `SPC6.spu.spu_pmu_ma_busy[2:0]
15515
15516////////////////////////////////////////////////////////////////////////////////
15517//Capture the status register data from rtl. For disrupting traps,
15518//rtl can modify the contents of the status register before the
15519//trap is taken and intp message is sent to Riesling.
15520//For precise traps, once the status register is updated rtl can't
15521//change the register again before jumping to the trap handler.
15522//So, for deferred and disrupting traps, inform Riesling when the
15523//register is modified while for precise traps wait until Fw2 before
15524//telling Riesling.
15525
15526//TLU asserts the flush and input signals in W stage. I latch them at the
15527//+ve edge of FX4.
15528
15529always @(negedge (`SPC6.l2clk & ready))
15530begin // {
15531 if (`DESR_asi_rd_53)
15532 desr_asi_rd <= 1'b1;
15533 if (desr_asi_rd)
15534 begin
15535 if (desr_wr)
15536 desr_pend_wr <= 1'b1;
15537 if (`ASI_LD_COMP_53[2])
15538 desr_asi_rd <= 1'b0;
15539 end
15540
15541 update_dsfsr_w <= (`DSFSR_NEW_IN_53 != 4'b0) && ~`ASI_WR_DSFSR_53;
15542 update_isfsr_w <= (`ISFSR_NEW_IN_53 != 3'b0) && ~`ASI_WR_ISFSR_53;
15543 desr_wr <= (`RAS_WRITE_DESR_1st_53 || `RAS_WRITE_DESR_2nd_53);
15544 update_dfesr_w <= `RAS_WRITE_FESR_53;
15545 take_err_trap_fx4 <= `ST_ERR_53 | `SW_REC_ERR_53 | `DATA_ACC_ERR_53
15546 | `INST_ACC_ERR_53 | `INT_PROC_ERR_53
15547 | `HW_CORR_ERR_53 | `INST_ACC_MMU_ERR_53
15548 | `DATA_ACC_MMU_ERR_53 ;
15549
15550
15551 if (`ST_ERR_53) int_num_fx4 <= 8'h07;
15552 if (`SW_REC_ERR_53) int_num_fx4 <= 8'h40;
15553 if (`DATA_ACC_ERR_53) int_num_fx4 <= 8'h32;
15554 if (`INST_ACC_ERR_53) int_num_fx4 <= 8'h0A;
15555 if (`INT_PROC_ERR_53) int_num_fx4 <= 8'h29;
15556 if (`HW_CORR_ERR_53) int_num_fx4 <= 8'h63;
15557 if (`INST_ACC_MMU_ERR_53) int_num_fx4 <= 8'h71;
15558 if (`DATA_ACC_MMU_ERR_53) int_num_fx4 <= 8'h72;
15559
15560 update_dsfsr_fx4 <= update_dsfsr_w;
15561 update_dsfsr_fx5 <= update_dsfsr_fx4;
15562 update_dsfsr_fb <= update_dsfsr_fx5;
15563 update_dsfsr_fw <= update_dsfsr_fb;
15564 update_dsfsr_fw1 <= update_dsfsr_fw;
15565 update_dsfsr_fw2 <= update_dsfsr_fw1;
15566
15567 update_isfsr_fx4 <= update_isfsr_w;
15568 update_isfsr_fx5 <= update_isfsr_fx4;
15569 update_isfsr_fb <= update_isfsr_fx5;
15570 update_isfsr_fw <= update_isfsr_fb;
15571 update_isfsr_fw1 <= update_isfsr_fw;
15572 update_isfsr_fw2 <= update_isfsr_fw1;
15573
15574 take_err_trap_fx5 <= take_err_trap_fx4;
15575 take_err_trap_fb <= take_err_trap_fx5;
15576 take_err_trap_fw <= take_err_trap_fb;
15577 take_err_trap_fw1 <= take_err_trap_fw;
15578 take_err_trap_fw2 <= take_err_trap_fw1;
15579
15580 int_num_fx5 <= int_num_fx4;
15581 int_num_fb <= int_num_fx5;
15582 int_num_fw <= int_num_fb;
15583 int_num_fw1 <= int_num_fw;
15584 int_num_fw2 <= int_num_fw1;
15585
15586 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
15587 begin // {
15588 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
15589 begin //{
15590 desr_pend_wr <= 1'b0;
15591 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_53[63:56], 45'b0, `DESR_53[10:0]});
15592 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_53[63:56], 45'b0, `DESR_53[10:0]});
15593 end //}
15594 //if (update_dfesr_w)
15595 if (`ST_ERR_53)
15596 begin //{
15597 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_53[61:55], 55'b0});
15598 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_53[61:55], 55'b0});
15599 end //}
15600 if (update_dsfsr_fw2)
15601 begin //{
15602 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
15603 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_53[3:0]});
15604 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_53[47:0]});
15605
15606 end //}
15607 if (update_isfsr_fw2)
15608 begin //{
15609 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
15610 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_53[2:0]});
15611 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_53[47:0]});
15612
15613 end //}
15614 if (take_err_trap_fw2)
15615 begin //{
15616 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
15617 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
15618 end // }
15619 end // }
15620
15621end //}
15622
15623//removing the addr check as the LSU doesn't flag an invalid_asi_exception
15624//if the addr of diagnostic accesses is not in the valid range. The inst.
15625//still executes. LSU expects that HP won't use addresses in invalid range.
15626
15627always @(negedge (`SPC6.l2clk & ready))
15628begin // {
15629 sync_asi = 1'b0;
15630 ld_data_w <= `ASI_LD_DATA_53;
15631
15632 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_53)
15633 chk_if_asi_ld <= 1'b1;
15634 else
15635 chk_if_asi_ld <= 1'b0;
15636
15637 if (chk_if_asi_ld & `ASI_LD_53)
15638 begin
15639 case (`ASI_53)
15640 8'h66: //ASI_IC_INSTR
15641 begin
15642 //if ((`ASI_ADDR_53 >= 0) & (`ASI_ADDR_53 <= 40'h7ff8))
15643 sync_asi = 1'b1;
15644 end
15645 8'h67: //ASI_IC_TAG
15646 begin
15647 //if ((`ASI_ADDR_53 >= 0) & (`ASI_ADDR_53 <= 40'h7fe0))
15648 sync_asi = 1'b1;
15649 end
15650 8'h46: //ASI_DC_DATA
15651 begin
15652 sync_asi = 1'b1;
15653 end
15654 8'h47: //ASI_DC_TAG
15655 begin
15656 //if ((`ASI_ADDR_53 >= 0) & (`ASI_ADDR_53 <= 40'h7ff0))
15657 sync_asi = 1'b1;
15658 end
15659 8'h48://IRF ECC
15660 begin
15661 //if ((`ASI_ADDR_53 >= 0) & (`ASI_ADDR_53 <= 40'hF8))
15662 sync_asi = 1'b1;
15663 end
15664 8'h49://FRF ECC
15665 begin
15666 //if ((`ASI_ADDR_53 >= 0) & (`ASI_ADDR_53 <= 40'hF8))
15667 sync_asi = 1'b1;
15668 end
15669 8'h4A://STB access, stb ptr can be read also
15670 begin
15671 //if ((`ASI_ADDR_53 >= 0) & (`ASI_ADDR_53 <= 40'h100))
15672 sync_asi = 1'b1;
15673 end
15674 8'h5A://Tick compare reg
15675 begin
15676 //if ((`ASI_ADDR_53 >= 0) & (`ASI_ADDR_53 <= 40'h38))
15677 sync_asi = 1'b1;
15678 end
15679 8'h5B://TSA
15680 begin
15681 //if ((`ASI_ADDR_53 >= 0) & (`ASI_ADDR_53 <= 40'h38))
15682 sync_asi = 1'b1;
15683 end
15684 8'h51://MRA
15685 begin
15686 //if ((`ASI_ADDR_53 >= 0) & (`ASI_ADDR_53 <= 40'h38))
15687 sync_asi = 1'b1;
15688 end
15689 8'h59://scratchpad ecc data read
15690 begin
15691 //if ((`ASI_ADDR_53 >= 0) & (`ASI_ADDR_53 <= 40'h38))
15692 //syncup the ecc data only. For ecc bit 6 is 0.
15693 if (~`SPC6.lsu.lmd.lmq5_pkt[6])
15694 sync_asi = 1'b1;
15695 end
15696 8'h40://cwqcsr,ma_sync access
15697 begin
15698 if ((`ASI_ADDR_53 == 40'h20) || (`ASI_ADDR_53 == 40'h30)
15699 || (`ASI_ADDR_53 == 40'h80)
15700 || ((`ASI_ADDR_53 == 40'ha0) & (`SPU_MA_BUSY_6 == 0) & (`SPU_MA_TID_6 == 5))
15701 )
15702 sync_asi = 1'b1;
15703 end
15704 8'h4C://CLESR, CLFESR access
15705 begin
15706 if ((`ASI_ADDR_53 == 40'h20) || (`ASI_ADDR_53 == 40'h28))
15707 sync_asi = 1'b1;
15708 end
15709 endcase
15710 end
15711
15712 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
15713 begin
15714 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_53, `ASI_ADDR_53, ld_data_w);
15715 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_53, {24'b0, `ASI_ADDR_53}, ld_data_w[63:0]);
15716 end
15717end //}
15718`endif
15719endmodule
15720
15721
15722
15723module err_c6t6 ();
15724`ifndef GATESIM
15725
15726`include "defines.vh"
15727
15728wire [2:0] mycid;
15729wire [2:0] mytid;
15730wire [5:0] mytnum;
15731
15732integer junk;
15733reg ready;
15734reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
15735reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
15736
15737reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
15738reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
15739
15740reg update_dfesr_w;
15741
15742reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
15743reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
15744
15745reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
15746reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
15747
15748reg sync_asi;
15749reg chk_if_asi_ld;
15750reg [63:0] ld_data_w;
15751
15752reg desr_asi_rd, desr_wr, desr_pend_wr;
15753
15754assign mycid = 6;
15755assign mytid = 6;
15756assign mytnum = 6*8 + 6;
15757
15758initial begin //{
15759 desr_asi_rd = 1'b0;
15760 desr_pend_wr = 1'b0;
15761 ready = 0;
15762 @(posedge `SPC6.l2clk) ;
15763 @(posedge `SPC6.l2clk) ;
15764 ready = `PARGS.err_sync_on;
15765end //}
15766
15767`define DSFSR_NEW_IN_54 `SPC6.tlu.ras.dsfsr_6_new_in
15768`define ISFSR_NEW_IN_54 `SPC6.tlu.ras.isfsr_6_new_in
15769
15770`define DSFSR_54 `SPC6.tlu.ras.dsfsr_6
15771`define ISFSR_54 `SPC6.tlu.ras.isfsr_6
15772`define DSFAR_54 `SPC6.tlu.dfd.dsfar_6
15773
15774`define ASI_WR_DSFSR_54 `SPC6.tlu.ras.asi_wr_dsfsr[6]
15775`define ASI_WR_ISFSR_54 `SPC6.tlu.ras.asi_wr_isfsr[6]
15776
15777`define RAS_WRITE_DESR_1st_54 `SPC6.tlu.dfd.ras_write_desr_1st[6]
15778`define RAS_WRITE_DESR_2nd_54 `SPC6.tlu.dfd.ras_write_desr_2nd[6]
15779`define DESR_asi_rd_54 `SPC6.tlu.ras_rd_desr[6]
15780`define DESR_54 `SPC6.tlu.dfd.desr_6
15781
15782`define RAS_WRITE_FESR_54 `SPC6.tlu.ras.write_fesr[6]
15783`define FESR_54 `SPC6.tlu.dfd.fesr_6
15784
15785`define ST_ERR_54 `SPC6.tlu.trl1.take_ftt & `SPC6.tlu.trl1.trap[2]
15786`define SW_REC_ERR_54 `SPC6.tlu.trl1.take_ade & `SPC6.tlu.trl1.trap[2]
15787`define DATA_ACC_ERR_54 `SPC6.tlu.trl1.take_dae & `SPC6.tlu.trl1.trap[2]
15788`define INST_ACC_ERR_54 `SPC6.tlu.trl1.take_iae & `SPC6.tlu.trl1.trap[2]
15789`define INT_PROC_ERR_54 `SPC6.tlu.trl1.take_ipe & `SPC6.tlu.trl1.trap[2]
15790`define HW_CORR_ERR_54 `SPC6.tlu.trl1.take_eer & `SPC6.tlu.trl1.trap[2]
15791`define INST_ACC_MMU_ERR_54 `SPC6.tlu.trl1.take_ime & `SPC6.tlu.trl1.trap[2]
15792`define DATA_ACC_MMU_ERR_54 `SPC6.tlu.trl1.take_dme & `SPC6.tlu.trl1.trap[2]
15793
15794`define LSU_LD_VALID_B `PROBES6.lsu_ld_valid
15795`define LSU_TID_DEC_B_54 `PROBES6.lsu_tid_dec_b[6]
15796`define ASI_LD_54 `SPC6.lsu.lmd.lmq6_pkt[60] & (`SPC6.lsu.lmd.lmq6_pkt[49:48] == 2'b0)
15797`define ASI_54 `SPC6.lsu.lmd.lmq6_pkt[47:40]
15798`define ASI_ADDR_54 `SPC6.lsu.lmd.lmq6_pkt[39:0]
15799`define ASI_LD_DATA_54 `SPC6.lsu_exu_ld_data_b[63:0]
15800`define ASI_LD_COMP_54 tb_top.nas_top.c6.t6.complete_fw2
15801
15802//SPU specific - only one SPU per core
15803`define SPU_MA_BUSY_6 `SPC6.spu.spu_pmu_ma_busy[3]
15804`define SPU_MA_TID_6 `SPC6.spu.spu_pmu_ma_busy[2:0]
15805
15806////////////////////////////////////////////////////////////////////////////////
15807//Capture the status register data from rtl. For disrupting traps,
15808//rtl can modify the contents of the status register before the
15809//trap is taken and intp message is sent to Riesling.
15810//For precise traps, once the status register is updated rtl can't
15811//change the register again before jumping to the trap handler.
15812//So, for deferred and disrupting traps, inform Riesling when the
15813//register is modified while for precise traps wait until Fw2 before
15814//telling Riesling.
15815
15816//TLU asserts the flush and input signals in W stage. I latch them at the
15817//+ve edge of FX4.
15818
15819always @(negedge (`SPC6.l2clk & ready))
15820begin // {
15821 if (`DESR_asi_rd_54)
15822 desr_asi_rd <= 1'b1;
15823 if (desr_asi_rd)
15824 begin
15825 if (desr_wr)
15826 desr_pend_wr <= 1'b1;
15827 if (`ASI_LD_COMP_54[2])
15828 desr_asi_rd <= 1'b0;
15829 end
15830
15831 update_dsfsr_w <= (`DSFSR_NEW_IN_54 != 4'b0) && ~`ASI_WR_DSFSR_54;
15832 update_isfsr_w <= (`ISFSR_NEW_IN_54 != 3'b0) && ~`ASI_WR_ISFSR_54;
15833 desr_wr <= (`RAS_WRITE_DESR_1st_54 || `RAS_WRITE_DESR_2nd_54);
15834 update_dfesr_w <= `RAS_WRITE_FESR_54;
15835 take_err_trap_fx4 <= `ST_ERR_54 | `SW_REC_ERR_54 | `DATA_ACC_ERR_54
15836 | `INST_ACC_ERR_54 | `INT_PROC_ERR_54
15837 | `HW_CORR_ERR_54 | `INST_ACC_MMU_ERR_54
15838 | `DATA_ACC_MMU_ERR_54 ;
15839
15840
15841 if (`ST_ERR_54) int_num_fx4 <= 8'h07;
15842 if (`SW_REC_ERR_54) int_num_fx4 <= 8'h40;
15843 if (`DATA_ACC_ERR_54) int_num_fx4 <= 8'h32;
15844 if (`INST_ACC_ERR_54) int_num_fx4 <= 8'h0A;
15845 if (`INT_PROC_ERR_54) int_num_fx4 <= 8'h29;
15846 if (`HW_CORR_ERR_54) int_num_fx4 <= 8'h63;
15847 if (`INST_ACC_MMU_ERR_54) int_num_fx4 <= 8'h71;
15848 if (`DATA_ACC_MMU_ERR_54) int_num_fx4 <= 8'h72;
15849
15850 update_dsfsr_fx4 <= update_dsfsr_w;
15851 update_dsfsr_fx5 <= update_dsfsr_fx4;
15852 update_dsfsr_fb <= update_dsfsr_fx5;
15853 update_dsfsr_fw <= update_dsfsr_fb;
15854 update_dsfsr_fw1 <= update_dsfsr_fw;
15855 update_dsfsr_fw2 <= update_dsfsr_fw1;
15856
15857 update_isfsr_fx4 <= update_isfsr_w;
15858 update_isfsr_fx5 <= update_isfsr_fx4;
15859 update_isfsr_fb <= update_isfsr_fx5;
15860 update_isfsr_fw <= update_isfsr_fb;
15861 update_isfsr_fw1 <= update_isfsr_fw;
15862 update_isfsr_fw2 <= update_isfsr_fw1;
15863
15864 take_err_trap_fx5 <= take_err_trap_fx4;
15865 take_err_trap_fb <= take_err_trap_fx5;
15866 take_err_trap_fw <= take_err_trap_fb;
15867 take_err_trap_fw1 <= take_err_trap_fw;
15868 take_err_trap_fw2 <= take_err_trap_fw1;
15869
15870 int_num_fx5 <= int_num_fx4;
15871 int_num_fb <= int_num_fx5;
15872 int_num_fw <= int_num_fb;
15873 int_num_fw1 <= int_num_fw;
15874 int_num_fw2 <= int_num_fw1;
15875
15876 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
15877 begin // {
15878 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
15879 begin //{
15880 desr_pend_wr <= 1'b0;
15881 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_54[63:56], 45'b0, `DESR_54[10:0]});
15882 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_54[63:56], 45'b0, `DESR_54[10:0]});
15883 end //}
15884 //if (update_dfesr_w)
15885 if (`ST_ERR_54)
15886 begin //{
15887 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_54[61:55], 55'b0});
15888 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_54[61:55], 55'b0});
15889 end //}
15890 if (update_dsfsr_fw2)
15891 begin //{
15892 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
15893 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_54[3:0]});
15894 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_54[47:0]});
15895
15896 end //}
15897 if (update_isfsr_fw2)
15898 begin //{
15899 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
15900 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_54[2:0]});
15901 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_54[47:0]});
15902
15903 end //}
15904 if (take_err_trap_fw2)
15905 begin //{
15906 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
15907 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
15908 end // }
15909 end // }
15910
15911end //}
15912
15913//removing the addr check as the LSU doesn't flag an invalid_asi_exception
15914//if the addr of diagnostic accesses is not in the valid range. The inst.
15915//still executes. LSU expects that HP won't use addresses in invalid range.
15916
15917always @(negedge (`SPC6.l2clk & ready))
15918begin // {
15919 sync_asi = 1'b0;
15920 ld_data_w <= `ASI_LD_DATA_54;
15921
15922 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_54)
15923 chk_if_asi_ld <= 1'b1;
15924 else
15925 chk_if_asi_ld <= 1'b0;
15926
15927 if (chk_if_asi_ld & `ASI_LD_54)
15928 begin
15929 case (`ASI_54)
15930 8'h66: //ASI_IC_INSTR
15931 begin
15932 //if ((`ASI_ADDR_54 >= 0) & (`ASI_ADDR_54 <= 40'h7ff8))
15933 sync_asi = 1'b1;
15934 end
15935 8'h67: //ASI_IC_TAG
15936 begin
15937 //if ((`ASI_ADDR_54 >= 0) & (`ASI_ADDR_54 <= 40'h7fe0))
15938 sync_asi = 1'b1;
15939 end
15940 8'h46: //ASI_DC_DATA
15941 begin
15942 sync_asi = 1'b1;
15943 end
15944 8'h47: //ASI_DC_TAG
15945 begin
15946 //if ((`ASI_ADDR_54 >= 0) & (`ASI_ADDR_54 <= 40'h7ff0))
15947 sync_asi = 1'b1;
15948 end
15949 8'h48://IRF ECC
15950 begin
15951 //if ((`ASI_ADDR_54 >= 0) & (`ASI_ADDR_54 <= 40'hF8))
15952 sync_asi = 1'b1;
15953 end
15954 8'h49://FRF ECC
15955 begin
15956 //if ((`ASI_ADDR_54 >= 0) & (`ASI_ADDR_54 <= 40'hF8))
15957 sync_asi = 1'b1;
15958 end
15959 8'h4A://STB access, stb ptr can be read also
15960 begin
15961 //if ((`ASI_ADDR_54 >= 0) & (`ASI_ADDR_54 <= 40'h100))
15962 sync_asi = 1'b1;
15963 end
15964 8'h5A://Tick compare reg
15965 begin
15966 //if ((`ASI_ADDR_54 >= 0) & (`ASI_ADDR_54 <= 40'h38))
15967 sync_asi = 1'b1;
15968 end
15969 8'h5B://TSA
15970 begin
15971 //if ((`ASI_ADDR_54 >= 0) & (`ASI_ADDR_54 <= 40'h38))
15972 sync_asi = 1'b1;
15973 end
15974 8'h51://MRA
15975 begin
15976 //if ((`ASI_ADDR_54 >= 0) & (`ASI_ADDR_54 <= 40'h38))
15977 sync_asi = 1'b1;
15978 end
15979 8'h59://scratchpad ecc data read
15980 begin
15981 //if ((`ASI_ADDR_54 >= 0) & (`ASI_ADDR_54 <= 40'h38))
15982 //syncup the ecc data only. For ecc bit 6 is 0.
15983 if (~`SPC6.lsu.lmd.lmq6_pkt[6])
15984 sync_asi = 1'b1;
15985 end
15986 8'h40://cwqcsr,ma_sync access
15987 begin
15988 if ((`ASI_ADDR_54 == 40'h20) || (`ASI_ADDR_54 == 40'h30)
15989 || (`ASI_ADDR_54 == 40'h80)
15990 || ((`ASI_ADDR_54 == 40'ha0) & (`SPU_MA_BUSY_6 == 0) & (`SPU_MA_TID_6 == 6))
15991 )
15992 sync_asi = 1'b1;
15993 end
15994 8'h4C://CLESR, CLFESR access
15995 begin
15996 if ((`ASI_ADDR_54 == 40'h20) || (`ASI_ADDR_54 == 40'h28))
15997 sync_asi = 1'b1;
15998 end
15999 endcase
16000 end
16001
16002 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
16003 begin
16004 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_54, `ASI_ADDR_54, ld_data_w);
16005 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_54, {24'b0, `ASI_ADDR_54}, ld_data_w[63:0]);
16006 end
16007end //}
16008`endif
16009endmodule
16010
16011
16012
16013module err_c6t7 ();
16014`ifndef GATESIM
16015
16016`include "defines.vh"
16017
16018wire [2:0] mycid;
16019wire [2:0] mytid;
16020wire [5:0] mytnum;
16021
16022integer junk;
16023reg ready;
16024reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
16025reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
16026
16027reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
16028reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
16029
16030reg update_dfesr_w;
16031
16032reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
16033reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
16034
16035reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
16036reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
16037
16038reg sync_asi;
16039reg chk_if_asi_ld;
16040reg [63:0] ld_data_w;
16041
16042reg desr_asi_rd, desr_wr, desr_pend_wr;
16043
16044assign mycid = 6;
16045assign mytid = 7;
16046assign mytnum = 6*8 + 7;
16047
16048initial begin //{
16049 desr_asi_rd = 1'b0;
16050 desr_pend_wr = 1'b0;
16051 ready = 0;
16052 @(posedge `SPC6.l2clk) ;
16053 @(posedge `SPC6.l2clk) ;
16054 ready = `PARGS.err_sync_on;
16055end //}
16056
16057`define DSFSR_NEW_IN_55 `SPC6.tlu.ras.dsfsr_7_new_in
16058`define ISFSR_NEW_IN_55 `SPC6.tlu.ras.isfsr_7_new_in
16059
16060`define DSFSR_55 `SPC6.tlu.ras.dsfsr_7
16061`define ISFSR_55 `SPC6.tlu.ras.isfsr_7
16062`define DSFAR_55 `SPC6.tlu.dfd.dsfar_7
16063
16064`define ASI_WR_DSFSR_55 `SPC6.tlu.ras.asi_wr_dsfsr[7]
16065`define ASI_WR_ISFSR_55 `SPC6.tlu.ras.asi_wr_isfsr[7]
16066
16067`define RAS_WRITE_DESR_1st_55 `SPC6.tlu.dfd.ras_write_desr_1st[7]
16068`define RAS_WRITE_DESR_2nd_55 `SPC6.tlu.dfd.ras_write_desr_2nd[7]
16069`define DESR_asi_rd_55 `SPC6.tlu.ras_rd_desr[7]
16070`define DESR_55 `SPC6.tlu.dfd.desr_7
16071
16072`define RAS_WRITE_FESR_55 `SPC6.tlu.ras.write_fesr[7]
16073`define FESR_55 `SPC6.tlu.dfd.fesr_7
16074
16075`define ST_ERR_55 `SPC6.tlu.trl1.take_ftt & `SPC6.tlu.trl1.trap[3]
16076`define SW_REC_ERR_55 `SPC6.tlu.trl1.take_ade & `SPC6.tlu.trl1.trap[3]
16077`define DATA_ACC_ERR_55 `SPC6.tlu.trl1.take_dae & `SPC6.tlu.trl1.trap[3]
16078`define INST_ACC_ERR_55 `SPC6.tlu.trl1.take_iae & `SPC6.tlu.trl1.trap[3]
16079`define INT_PROC_ERR_55 `SPC6.tlu.trl1.take_ipe & `SPC6.tlu.trl1.trap[3]
16080`define HW_CORR_ERR_55 `SPC6.tlu.trl1.take_eer & `SPC6.tlu.trl1.trap[3]
16081`define INST_ACC_MMU_ERR_55 `SPC6.tlu.trl1.take_ime & `SPC6.tlu.trl1.trap[3]
16082`define DATA_ACC_MMU_ERR_55 `SPC6.tlu.trl1.take_dme & `SPC6.tlu.trl1.trap[3]
16083
16084`define LSU_LD_VALID_B `PROBES6.lsu_ld_valid
16085`define LSU_TID_DEC_B_55 `PROBES6.lsu_tid_dec_b[7]
16086`define ASI_LD_55 `SPC6.lsu.lmd.lmq7_pkt[60] & (`SPC6.lsu.lmd.lmq7_pkt[49:48] == 2'b0)
16087`define ASI_55 `SPC6.lsu.lmd.lmq7_pkt[47:40]
16088`define ASI_ADDR_55 `SPC6.lsu.lmd.lmq7_pkt[39:0]
16089`define ASI_LD_DATA_55 `SPC6.lsu_exu_ld_data_b[63:0]
16090`define ASI_LD_COMP_55 tb_top.nas_top.c6.t7.complete_fw2
16091
16092//SPU specific - only one SPU per core
16093`define SPU_MA_BUSY_6 `SPC6.spu.spu_pmu_ma_busy[3]
16094`define SPU_MA_TID_6 `SPC6.spu.spu_pmu_ma_busy[2:0]
16095
16096////////////////////////////////////////////////////////////////////////////////
16097//Capture the status register data from rtl. For disrupting traps,
16098//rtl can modify the contents of the status register before the
16099//trap is taken and intp message is sent to Riesling.
16100//For precise traps, once the status register is updated rtl can't
16101//change the register again before jumping to the trap handler.
16102//So, for deferred and disrupting traps, inform Riesling when the
16103//register is modified while for precise traps wait until Fw2 before
16104//telling Riesling.
16105
16106//TLU asserts the flush and input signals in W stage. I latch them at the
16107//+ve edge of FX4.
16108
16109always @(negedge (`SPC6.l2clk & ready))
16110begin // {
16111 if (`DESR_asi_rd_55)
16112 desr_asi_rd <= 1'b1;
16113 if (desr_asi_rd)
16114 begin
16115 if (desr_wr)
16116 desr_pend_wr <= 1'b1;
16117 if (`ASI_LD_COMP_55[2])
16118 desr_asi_rd <= 1'b0;
16119 end
16120
16121 update_dsfsr_w <= (`DSFSR_NEW_IN_55 != 4'b0) && ~`ASI_WR_DSFSR_55;
16122 update_isfsr_w <= (`ISFSR_NEW_IN_55 != 3'b0) && ~`ASI_WR_ISFSR_55;
16123 desr_wr <= (`RAS_WRITE_DESR_1st_55 || `RAS_WRITE_DESR_2nd_55);
16124 update_dfesr_w <= `RAS_WRITE_FESR_55;
16125 take_err_trap_fx4 <= `ST_ERR_55 | `SW_REC_ERR_55 | `DATA_ACC_ERR_55
16126 | `INST_ACC_ERR_55 | `INT_PROC_ERR_55
16127 | `HW_CORR_ERR_55 | `INST_ACC_MMU_ERR_55
16128 | `DATA_ACC_MMU_ERR_55 ;
16129
16130
16131 if (`ST_ERR_55) int_num_fx4 <= 8'h07;
16132 if (`SW_REC_ERR_55) int_num_fx4 <= 8'h40;
16133 if (`DATA_ACC_ERR_55) int_num_fx4 <= 8'h32;
16134 if (`INST_ACC_ERR_55) int_num_fx4 <= 8'h0A;
16135 if (`INT_PROC_ERR_55) int_num_fx4 <= 8'h29;
16136 if (`HW_CORR_ERR_55) int_num_fx4 <= 8'h63;
16137 if (`INST_ACC_MMU_ERR_55) int_num_fx4 <= 8'h71;
16138 if (`DATA_ACC_MMU_ERR_55) int_num_fx4 <= 8'h72;
16139
16140 update_dsfsr_fx4 <= update_dsfsr_w;
16141 update_dsfsr_fx5 <= update_dsfsr_fx4;
16142 update_dsfsr_fb <= update_dsfsr_fx5;
16143 update_dsfsr_fw <= update_dsfsr_fb;
16144 update_dsfsr_fw1 <= update_dsfsr_fw;
16145 update_dsfsr_fw2 <= update_dsfsr_fw1;
16146
16147 update_isfsr_fx4 <= update_isfsr_w;
16148 update_isfsr_fx5 <= update_isfsr_fx4;
16149 update_isfsr_fb <= update_isfsr_fx5;
16150 update_isfsr_fw <= update_isfsr_fb;
16151 update_isfsr_fw1 <= update_isfsr_fw;
16152 update_isfsr_fw2 <= update_isfsr_fw1;
16153
16154 take_err_trap_fx5 <= take_err_trap_fx4;
16155 take_err_trap_fb <= take_err_trap_fx5;
16156 take_err_trap_fw <= take_err_trap_fb;
16157 take_err_trap_fw1 <= take_err_trap_fw;
16158 take_err_trap_fw2 <= take_err_trap_fw1;
16159
16160 int_num_fx5 <= int_num_fx4;
16161 int_num_fb <= int_num_fx5;
16162 int_num_fw <= int_num_fb;
16163 int_num_fw1 <= int_num_fw;
16164 int_num_fw2 <= int_num_fw1;
16165
16166 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
16167 begin // {
16168 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
16169 begin //{
16170 desr_pend_wr <= 1'b0;
16171 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_55[63:56], 45'b0, `DESR_55[10:0]});
16172 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_55[63:56], 45'b0, `DESR_55[10:0]});
16173 end //}
16174 //if (update_dfesr_w)
16175 if (`ST_ERR_55)
16176 begin //{
16177 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_55[61:55], 55'b0});
16178 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_55[61:55], 55'b0});
16179 end //}
16180 if (update_dsfsr_fw2)
16181 begin //{
16182 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
16183 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_55[3:0]});
16184 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_55[47:0]});
16185
16186 end //}
16187 if (update_isfsr_fw2)
16188 begin //{
16189 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
16190 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_55[2:0]});
16191 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_55[47:0]});
16192
16193 end //}
16194 if (take_err_trap_fw2)
16195 begin //{
16196 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
16197 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
16198 end // }
16199 end // }
16200
16201end //}
16202
16203//removing the addr check as the LSU doesn't flag an invalid_asi_exception
16204//if the addr of diagnostic accesses is not in the valid range. The inst.
16205//still executes. LSU expects that HP won't use addresses in invalid range.
16206
16207always @(negedge (`SPC6.l2clk & ready))
16208begin // {
16209 sync_asi = 1'b0;
16210 ld_data_w <= `ASI_LD_DATA_55;
16211
16212 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_55)
16213 chk_if_asi_ld <= 1'b1;
16214 else
16215 chk_if_asi_ld <= 1'b0;
16216
16217 if (chk_if_asi_ld & `ASI_LD_55)
16218 begin
16219 case (`ASI_55)
16220 8'h66: //ASI_IC_INSTR
16221 begin
16222 //if ((`ASI_ADDR_55 >= 0) & (`ASI_ADDR_55 <= 40'h7ff8))
16223 sync_asi = 1'b1;
16224 end
16225 8'h67: //ASI_IC_TAG
16226 begin
16227 //if ((`ASI_ADDR_55 >= 0) & (`ASI_ADDR_55 <= 40'h7fe0))
16228 sync_asi = 1'b1;
16229 end
16230 8'h46: //ASI_DC_DATA
16231 begin
16232 sync_asi = 1'b1;
16233 end
16234 8'h47: //ASI_DC_TAG
16235 begin
16236 //if ((`ASI_ADDR_55 >= 0) & (`ASI_ADDR_55 <= 40'h7ff0))
16237 sync_asi = 1'b1;
16238 end
16239 8'h48://IRF ECC
16240 begin
16241 //if ((`ASI_ADDR_55 >= 0) & (`ASI_ADDR_55 <= 40'hF8))
16242 sync_asi = 1'b1;
16243 end
16244 8'h49://FRF ECC
16245 begin
16246 //if ((`ASI_ADDR_55 >= 0) & (`ASI_ADDR_55 <= 40'hF8))
16247 sync_asi = 1'b1;
16248 end
16249 8'h4A://STB access, stb ptr can be read also
16250 begin
16251 //if ((`ASI_ADDR_55 >= 0) & (`ASI_ADDR_55 <= 40'h100))
16252 sync_asi = 1'b1;
16253 end
16254 8'h5A://Tick compare reg
16255 begin
16256 //if ((`ASI_ADDR_55 >= 0) & (`ASI_ADDR_55 <= 40'h38))
16257 sync_asi = 1'b1;
16258 end
16259 8'h5B://TSA
16260 begin
16261 //if ((`ASI_ADDR_55 >= 0) & (`ASI_ADDR_55 <= 40'h38))
16262 sync_asi = 1'b1;
16263 end
16264 8'h51://MRA
16265 begin
16266 //if ((`ASI_ADDR_55 >= 0) & (`ASI_ADDR_55 <= 40'h38))
16267 sync_asi = 1'b1;
16268 end
16269 8'h59://scratchpad ecc data read
16270 begin
16271 //if ((`ASI_ADDR_55 >= 0) & (`ASI_ADDR_55 <= 40'h38))
16272 //syncup the ecc data only. For ecc bit 6 is 0.
16273 if (~`SPC6.lsu.lmd.lmq7_pkt[6])
16274 sync_asi = 1'b1;
16275 end
16276 8'h40://cwqcsr,ma_sync access
16277 begin
16278 if ((`ASI_ADDR_55 == 40'h20) || (`ASI_ADDR_55 == 40'h30)
16279 || (`ASI_ADDR_55 == 40'h80)
16280 || ((`ASI_ADDR_55 == 40'ha0) & (`SPU_MA_BUSY_6 == 0) & (`SPU_MA_TID_6 == 7))
16281 )
16282 sync_asi = 1'b1;
16283 end
16284 8'h4C://CLESR, CLFESR access
16285 begin
16286 if ((`ASI_ADDR_55 == 40'h20) || (`ASI_ADDR_55 == 40'h28))
16287 sync_asi = 1'b1;
16288 end
16289 endcase
16290 end
16291
16292 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
16293 begin
16294 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_55, `ASI_ADDR_55, ld_data_w);
16295 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_55, {24'b0, `ASI_ADDR_55}, ld_data_w[63:0]);
16296 end
16297end //}
16298`endif
16299endmodule
16300
16301`endif
16302
16303`ifdef CORE_7
16304
16305
16306
16307module err_c7t0 ();
16308`ifndef GATESIM
16309
16310`include "defines.vh"
16311
16312wire [2:0] mycid;
16313wire [2:0] mytid;
16314wire [5:0] mytnum;
16315
16316integer junk;
16317reg ready;
16318reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
16319reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
16320
16321reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
16322reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
16323
16324reg update_dfesr_w;
16325
16326reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
16327reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
16328
16329reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
16330reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
16331
16332reg sync_asi;
16333reg chk_if_asi_ld;
16334reg [63:0] ld_data_w;
16335
16336reg desr_asi_rd, desr_wr, desr_pend_wr;
16337
16338assign mycid = 7;
16339assign mytid = 0;
16340assign mytnum = 7*8 + 0;
16341
16342initial begin //{
16343 desr_asi_rd = 1'b0;
16344 desr_pend_wr = 1'b0;
16345 ready = 0;
16346 @(posedge `SPC7.l2clk) ;
16347 @(posedge `SPC7.l2clk) ;
16348 ready = `PARGS.err_sync_on;
16349end //}
16350
16351`define DSFSR_NEW_IN_56 `SPC7.tlu.ras.dsfsr_0_new_in
16352`define ISFSR_NEW_IN_56 `SPC7.tlu.ras.isfsr_0_new_in
16353
16354`define DSFSR_56 `SPC7.tlu.ras.dsfsr_0
16355`define ISFSR_56 `SPC7.tlu.ras.isfsr_0
16356`define DSFAR_56 `SPC7.tlu.dfd.dsfar_0
16357
16358`define ASI_WR_DSFSR_56 `SPC7.tlu.ras.asi_wr_dsfsr[0]
16359`define ASI_WR_ISFSR_56 `SPC7.tlu.ras.asi_wr_isfsr[0]
16360
16361`define RAS_WRITE_DESR_1st_56 `SPC7.tlu.dfd.ras_write_desr_1st[0]
16362`define RAS_WRITE_DESR_2nd_56 `SPC7.tlu.dfd.ras_write_desr_2nd[0]
16363`define DESR_asi_rd_56 `SPC7.tlu.ras_rd_desr[0]
16364`define DESR_56 `SPC7.tlu.dfd.desr_0
16365
16366`define RAS_WRITE_FESR_56 `SPC7.tlu.ras.write_fesr[0]
16367`define FESR_56 `SPC7.tlu.dfd.fesr_0
16368
16369`define ST_ERR_56 `SPC7.tlu.trl0.take_ftt & `SPC7.tlu.trl0.trap[0]
16370`define SW_REC_ERR_56 `SPC7.tlu.trl0.take_ade & `SPC7.tlu.trl0.trap[0]
16371`define DATA_ACC_ERR_56 `SPC7.tlu.trl0.take_dae & `SPC7.tlu.trl0.trap[0]
16372`define INST_ACC_ERR_56 `SPC7.tlu.trl0.take_iae & `SPC7.tlu.trl0.trap[0]
16373`define INT_PROC_ERR_56 `SPC7.tlu.trl0.take_ipe & `SPC7.tlu.trl0.trap[0]
16374`define HW_CORR_ERR_56 `SPC7.tlu.trl0.take_eer & `SPC7.tlu.trl0.trap[0]
16375`define INST_ACC_MMU_ERR_56 `SPC7.tlu.trl0.take_ime & `SPC7.tlu.trl0.trap[0]
16376`define DATA_ACC_MMU_ERR_56 `SPC7.tlu.trl0.take_dme & `SPC7.tlu.trl0.trap[0]
16377
16378`define LSU_LD_VALID_B `PROBES7.lsu_ld_valid
16379`define LSU_TID_DEC_B_56 `PROBES7.lsu_tid_dec_b[0]
16380`define ASI_LD_56 `SPC7.lsu.lmd.lmq0_pkt[60] & (`SPC7.lsu.lmd.lmq0_pkt[49:48] == 2'b0)
16381`define ASI_56 `SPC7.lsu.lmd.lmq0_pkt[47:40]
16382`define ASI_ADDR_56 `SPC7.lsu.lmd.lmq0_pkt[39:0]
16383`define ASI_LD_DATA_56 `SPC7.lsu_exu_ld_data_b[63:0]
16384`define ASI_LD_COMP_56 tb_top.nas_top.c7.t0.complete_fw2
16385
16386//SPU specific - only one SPU per core
16387`define SPU_MA_BUSY_7 `SPC7.spu.spu_pmu_ma_busy[3]
16388`define SPU_MA_TID_7 `SPC7.spu.spu_pmu_ma_busy[2:0]
16389
16390////////////////////////////////////////////////////////////////////////////////
16391//Capture the status register data from rtl. For disrupting traps,
16392//rtl can modify the contents of the status register before the
16393//trap is taken and intp message is sent to Riesling.
16394//For precise traps, once the status register is updated rtl can't
16395//change the register again before jumping to the trap handler.
16396//So, for deferred and disrupting traps, inform Riesling when the
16397//register is modified while for precise traps wait until Fw2 before
16398//telling Riesling.
16399
16400//TLU asserts the flush and input signals in W stage. I latch them at the
16401//+ve edge of FX4.
16402
16403always @(negedge (`SPC7.l2clk & ready))
16404begin // {
16405 if (`DESR_asi_rd_56)
16406 desr_asi_rd <= 1'b1;
16407 if (desr_asi_rd)
16408 begin
16409 if (desr_wr)
16410 desr_pend_wr <= 1'b1;
16411 if (`ASI_LD_COMP_56[2])
16412 desr_asi_rd <= 1'b0;
16413 end
16414
16415 update_dsfsr_w <= (`DSFSR_NEW_IN_56 != 4'b0) && ~`ASI_WR_DSFSR_56;
16416 update_isfsr_w <= (`ISFSR_NEW_IN_56 != 3'b0) && ~`ASI_WR_ISFSR_56;
16417 desr_wr <= (`RAS_WRITE_DESR_1st_56 || `RAS_WRITE_DESR_2nd_56);
16418 update_dfesr_w <= `RAS_WRITE_FESR_56;
16419 take_err_trap_fx4 <= `ST_ERR_56 | `SW_REC_ERR_56 | `DATA_ACC_ERR_56
16420 | `INST_ACC_ERR_56 | `INT_PROC_ERR_56
16421 | `HW_CORR_ERR_56 | `INST_ACC_MMU_ERR_56
16422 | `DATA_ACC_MMU_ERR_56 ;
16423
16424
16425 if (`ST_ERR_56) int_num_fx4 <= 8'h07;
16426 if (`SW_REC_ERR_56) int_num_fx4 <= 8'h40;
16427 if (`DATA_ACC_ERR_56) int_num_fx4 <= 8'h32;
16428 if (`INST_ACC_ERR_56) int_num_fx4 <= 8'h0A;
16429 if (`INT_PROC_ERR_56) int_num_fx4 <= 8'h29;
16430 if (`HW_CORR_ERR_56) int_num_fx4 <= 8'h63;
16431 if (`INST_ACC_MMU_ERR_56) int_num_fx4 <= 8'h71;
16432 if (`DATA_ACC_MMU_ERR_56) int_num_fx4 <= 8'h72;
16433
16434 update_dsfsr_fx4 <= update_dsfsr_w;
16435 update_dsfsr_fx5 <= update_dsfsr_fx4;
16436 update_dsfsr_fb <= update_dsfsr_fx5;
16437 update_dsfsr_fw <= update_dsfsr_fb;
16438 update_dsfsr_fw1 <= update_dsfsr_fw;
16439 update_dsfsr_fw2 <= update_dsfsr_fw1;
16440
16441 update_isfsr_fx4 <= update_isfsr_w;
16442 update_isfsr_fx5 <= update_isfsr_fx4;
16443 update_isfsr_fb <= update_isfsr_fx5;
16444 update_isfsr_fw <= update_isfsr_fb;
16445 update_isfsr_fw1 <= update_isfsr_fw;
16446 update_isfsr_fw2 <= update_isfsr_fw1;
16447
16448 take_err_trap_fx5 <= take_err_trap_fx4;
16449 take_err_trap_fb <= take_err_trap_fx5;
16450 take_err_trap_fw <= take_err_trap_fb;
16451 take_err_trap_fw1 <= take_err_trap_fw;
16452 take_err_trap_fw2 <= take_err_trap_fw1;
16453
16454 int_num_fx5 <= int_num_fx4;
16455 int_num_fb <= int_num_fx5;
16456 int_num_fw <= int_num_fb;
16457 int_num_fw1 <= int_num_fw;
16458 int_num_fw2 <= int_num_fw1;
16459
16460 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
16461 begin // {
16462 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
16463 begin //{
16464 desr_pend_wr <= 1'b0;
16465 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_56[63:56], 45'b0, `DESR_56[10:0]});
16466 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_56[63:56], 45'b0, `DESR_56[10:0]});
16467 end //}
16468 //if (update_dfesr_w)
16469 if (`ST_ERR_56)
16470 begin //{
16471 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_56[61:55], 55'b0});
16472 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_56[61:55], 55'b0});
16473 end //}
16474 if (update_dsfsr_fw2)
16475 begin //{
16476 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
16477 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_56[3:0]});
16478 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_56[47:0]});
16479
16480 end //}
16481 if (update_isfsr_fw2)
16482 begin //{
16483 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
16484 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_56[2:0]});
16485 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_56[47:0]});
16486
16487 end //}
16488 if (take_err_trap_fw2)
16489 begin //{
16490 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
16491 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
16492 end // }
16493 end // }
16494
16495end //}
16496
16497//removing the addr check as the LSU doesn't flag an invalid_asi_exception
16498//if the addr of diagnostic accesses is not in the valid range. The inst.
16499//still executes. LSU expects that HP won't use addresses in invalid range.
16500
16501always @(negedge (`SPC7.l2clk & ready))
16502begin // {
16503 sync_asi = 1'b0;
16504 ld_data_w <= `ASI_LD_DATA_56;
16505
16506 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_56)
16507 chk_if_asi_ld <= 1'b1;
16508 else
16509 chk_if_asi_ld <= 1'b0;
16510
16511 if (chk_if_asi_ld & `ASI_LD_56)
16512 begin
16513 case (`ASI_56)
16514 8'h66: //ASI_IC_INSTR
16515 begin
16516 //if ((`ASI_ADDR_56 >= 0) & (`ASI_ADDR_56 <= 40'h7ff8))
16517 sync_asi = 1'b1;
16518 end
16519 8'h67: //ASI_IC_TAG
16520 begin
16521 //if ((`ASI_ADDR_56 >= 0) & (`ASI_ADDR_56 <= 40'h7fe0))
16522 sync_asi = 1'b1;
16523 end
16524 8'h46: //ASI_DC_DATA
16525 begin
16526 sync_asi = 1'b1;
16527 end
16528 8'h47: //ASI_DC_TAG
16529 begin
16530 //if ((`ASI_ADDR_56 >= 0) & (`ASI_ADDR_56 <= 40'h7ff0))
16531 sync_asi = 1'b1;
16532 end
16533 8'h48://IRF ECC
16534 begin
16535 //if ((`ASI_ADDR_56 >= 0) & (`ASI_ADDR_56 <= 40'hF8))
16536 sync_asi = 1'b1;
16537 end
16538 8'h49://FRF ECC
16539 begin
16540 //if ((`ASI_ADDR_56 >= 0) & (`ASI_ADDR_56 <= 40'hF8))
16541 sync_asi = 1'b1;
16542 end
16543 8'h4A://STB access, stb ptr can be read also
16544 begin
16545 //if ((`ASI_ADDR_56 >= 0) & (`ASI_ADDR_56 <= 40'h100))
16546 sync_asi = 1'b1;
16547 end
16548 8'h5A://Tick compare reg
16549 begin
16550 //if ((`ASI_ADDR_56 >= 0) & (`ASI_ADDR_56 <= 40'h38))
16551 sync_asi = 1'b1;
16552 end
16553 8'h5B://TSA
16554 begin
16555 //if ((`ASI_ADDR_56 >= 0) & (`ASI_ADDR_56 <= 40'h38))
16556 sync_asi = 1'b1;
16557 end
16558 8'h51://MRA
16559 begin
16560 //if ((`ASI_ADDR_56 >= 0) & (`ASI_ADDR_56 <= 40'h38))
16561 sync_asi = 1'b1;
16562 end
16563 8'h59://scratchpad ecc data read
16564 begin
16565 //if ((`ASI_ADDR_56 >= 0) & (`ASI_ADDR_56 <= 40'h38))
16566 //syncup the ecc data only. For ecc bit 6 is 0.
16567 if (~`SPC7.lsu.lmd.lmq0_pkt[6])
16568 sync_asi = 1'b1;
16569 end
16570 8'h40://cwqcsr,ma_sync access
16571 begin
16572 if ((`ASI_ADDR_56 == 40'h20) || (`ASI_ADDR_56 == 40'h30)
16573 || (`ASI_ADDR_56 == 40'h80)
16574 || ((`ASI_ADDR_56 == 40'ha0) & (`SPU_MA_BUSY_7 == 0) & (`SPU_MA_TID_7 == 0))
16575 )
16576 sync_asi = 1'b1;
16577 end
16578 8'h4C://CLESR, CLFESR access
16579 begin
16580 if ((`ASI_ADDR_56 == 40'h20) || (`ASI_ADDR_56 == 40'h28))
16581 sync_asi = 1'b1;
16582 end
16583 endcase
16584 end
16585
16586 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
16587 begin
16588 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_56, `ASI_ADDR_56, ld_data_w);
16589 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_56, {24'b0, `ASI_ADDR_56}, ld_data_w[63:0]);
16590 end
16591end //}
16592`endif
16593endmodule
16594
16595
16596
16597module err_c7t1 ();
16598`ifndef GATESIM
16599
16600`include "defines.vh"
16601
16602wire [2:0] mycid;
16603wire [2:0] mytid;
16604wire [5:0] mytnum;
16605
16606integer junk;
16607reg ready;
16608reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
16609reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
16610
16611reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
16612reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
16613
16614reg update_dfesr_w;
16615
16616reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
16617reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
16618
16619reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
16620reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
16621
16622reg sync_asi;
16623reg chk_if_asi_ld;
16624reg [63:0] ld_data_w;
16625
16626reg desr_asi_rd, desr_wr, desr_pend_wr;
16627
16628assign mycid = 7;
16629assign mytid = 1;
16630assign mytnum = 7*8 + 1;
16631
16632initial begin //{
16633 desr_asi_rd = 1'b0;
16634 desr_pend_wr = 1'b0;
16635 ready = 0;
16636 @(posedge `SPC7.l2clk) ;
16637 @(posedge `SPC7.l2clk) ;
16638 ready = `PARGS.err_sync_on;
16639end //}
16640
16641`define DSFSR_NEW_IN_57 `SPC7.tlu.ras.dsfsr_1_new_in
16642`define ISFSR_NEW_IN_57 `SPC7.tlu.ras.isfsr_1_new_in
16643
16644`define DSFSR_57 `SPC7.tlu.ras.dsfsr_1
16645`define ISFSR_57 `SPC7.tlu.ras.isfsr_1
16646`define DSFAR_57 `SPC7.tlu.dfd.dsfar_1
16647
16648`define ASI_WR_DSFSR_57 `SPC7.tlu.ras.asi_wr_dsfsr[1]
16649`define ASI_WR_ISFSR_57 `SPC7.tlu.ras.asi_wr_isfsr[1]
16650
16651`define RAS_WRITE_DESR_1st_57 `SPC7.tlu.dfd.ras_write_desr_1st[1]
16652`define RAS_WRITE_DESR_2nd_57 `SPC7.tlu.dfd.ras_write_desr_2nd[1]
16653`define DESR_asi_rd_57 `SPC7.tlu.ras_rd_desr[1]
16654`define DESR_57 `SPC7.tlu.dfd.desr_1
16655
16656`define RAS_WRITE_FESR_57 `SPC7.tlu.ras.write_fesr[1]
16657`define FESR_57 `SPC7.tlu.dfd.fesr_1
16658
16659`define ST_ERR_57 `SPC7.tlu.trl0.take_ftt & `SPC7.tlu.trl0.trap[1]
16660`define SW_REC_ERR_57 `SPC7.tlu.trl0.take_ade & `SPC7.tlu.trl0.trap[1]
16661`define DATA_ACC_ERR_57 `SPC7.tlu.trl0.take_dae & `SPC7.tlu.trl0.trap[1]
16662`define INST_ACC_ERR_57 `SPC7.tlu.trl0.take_iae & `SPC7.tlu.trl0.trap[1]
16663`define INT_PROC_ERR_57 `SPC7.tlu.trl0.take_ipe & `SPC7.tlu.trl0.trap[1]
16664`define HW_CORR_ERR_57 `SPC7.tlu.trl0.take_eer & `SPC7.tlu.trl0.trap[1]
16665`define INST_ACC_MMU_ERR_57 `SPC7.tlu.trl0.take_ime & `SPC7.tlu.trl0.trap[1]
16666`define DATA_ACC_MMU_ERR_57 `SPC7.tlu.trl0.take_dme & `SPC7.tlu.trl0.trap[1]
16667
16668`define LSU_LD_VALID_B `PROBES7.lsu_ld_valid
16669`define LSU_TID_DEC_B_57 `PROBES7.lsu_tid_dec_b[1]
16670`define ASI_LD_57 `SPC7.lsu.lmd.lmq1_pkt[60] & (`SPC7.lsu.lmd.lmq1_pkt[49:48] == 2'b0)
16671`define ASI_57 `SPC7.lsu.lmd.lmq1_pkt[47:40]
16672`define ASI_ADDR_57 `SPC7.lsu.lmd.lmq1_pkt[39:0]
16673`define ASI_LD_DATA_57 `SPC7.lsu_exu_ld_data_b[63:0]
16674`define ASI_LD_COMP_57 tb_top.nas_top.c7.t1.complete_fw2
16675
16676//SPU specific - only one SPU per core
16677`define SPU_MA_BUSY_7 `SPC7.spu.spu_pmu_ma_busy[3]
16678`define SPU_MA_TID_7 `SPC7.spu.spu_pmu_ma_busy[2:0]
16679
16680////////////////////////////////////////////////////////////////////////////////
16681//Capture the status register data from rtl. For disrupting traps,
16682//rtl can modify the contents of the status register before the
16683//trap is taken and intp message is sent to Riesling.
16684//For precise traps, once the status register is updated rtl can't
16685//change the register again before jumping to the trap handler.
16686//So, for deferred and disrupting traps, inform Riesling when the
16687//register is modified while for precise traps wait until Fw2 before
16688//telling Riesling.
16689
16690//TLU asserts the flush and input signals in W stage. I latch them at the
16691//+ve edge of FX4.
16692
16693always @(negedge (`SPC7.l2clk & ready))
16694begin // {
16695 if (`DESR_asi_rd_57)
16696 desr_asi_rd <= 1'b1;
16697 if (desr_asi_rd)
16698 begin
16699 if (desr_wr)
16700 desr_pend_wr <= 1'b1;
16701 if (`ASI_LD_COMP_57[2])
16702 desr_asi_rd <= 1'b0;
16703 end
16704
16705 update_dsfsr_w <= (`DSFSR_NEW_IN_57 != 4'b0) && ~`ASI_WR_DSFSR_57;
16706 update_isfsr_w <= (`ISFSR_NEW_IN_57 != 3'b0) && ~`ASI_WR_ISFSR_57;
16707 desr_wr <= (`RAS_WRITE_DESR_1st_57 || `RAS_WRITE_DESR_2nd_57);
16708 update_dfesr_w <= `RAS_WRITE_FESR_57;
16709 take_err_trap_fx4 <= `ST_ERR_57 | `SW_REC_ERR_57 | `DATA_ACC_ERR_57
16710 | `INST_ACC_ERR_57 | `INT_PROC_ERR_57
16711 | `HW_CORR_ERR_57 | `INST_ACC_MMU_ERR_57
16712 | `DATA_ACC_MMU_ERR_57 ;
16713
16714
16715 if (`ST_ERR_57) int_num_fx4 <= 8'h07;
16716 if (`SW_REC_ERR_57) int_num_fx4 <= 8'h40;
16717 if (`DATA_ACC_ERR_57) int_num_fx4 <= 8'h32;
16718 if (`INST_ACC_ERR_57) int_num_fx4 <= 8'h0A;
16719 if (`INT_PROC_ERR_57) int_num_fx4 <= 8'h29;
16720 if (`HW_CORR_ERR_57) int_num_fx4 <= 8'h63;
16721 if (`INST_ACC_MMU_ERR_57) int_num_fx4 <= 8'h71;
16722 if (`DATA_ACC_MMU_ERR_57) int_num_fx4 <= 8'h72;
16723
16724 update_dsfsr_fx4 <= update_dsfsr_w;
16725 update_dsfsr_fx5 <= update_dsfsr_fx4;
16726 update_dsfsr_fb <= update_dsfsr_fx5;
16727 update_dsfsr_fw <= update_dsfsr_fb;
16728 update_dsfsr_fw1 <= update_dsfsr_fw;
16729 update_dsfsr_fw2 <= update_dsfsr_fw1;
16730
16731 update_isfsr_fx4 <= update_isfsr_w;
16732 update_isfsr_fx5 <= update_isfsr_fx4;
16733 update_isfsr_fb <= update_isfsr_fx5;
16734 update_isfsr_fw <= update_isfsr_fb;
16735 update_isfsr_fw1 <= update_isfsr_fw;
16736 update_isfsr_fw2 <= update_isfsr_fw1;
16737
16738 take_err_trap_fx5 <= take_err_trap_fx4;
16739 take_err_trap_fb <= take_err_trap_fx5;
16740 take_err_trap_fw <= take_err_trap_fb;
16741 take_err_trap_fw1 <= take_err_trap_fw;
16742 take_err_trap_fw2 <= take_err_trap_fw1;
16743
16744 int_num_fx5 <= int_num_fx4;
16745 int_num_fb <= int_num_fx5;
16746 int_num_fw <= int_num_fb;
16747 int_num_fw1 <= int_num_fw;
16748 int_num_fw2 <= int_num_fw1;
16749
16750 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
16751 begin // {
16752 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
16753 begin //{
16754 desr_pend_wr <= 1'b0;
16755 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_57[63:56], 45'b0, `DESR_57[10:0]});
16756 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_57[63:56], 45'b0, `DESR_57[10:0]});
16757 end //}
16758 //if (update_dfesr_w)
16759 if (`ST_ERR_57)
16760 begin //{
16761 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_57[61:55], 55'b0});
16762 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_57[61:55], 55'b0});
16763 end //}
16764 if (update_dsfsr_fw2)
16765 begin //{
16766 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
16767 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_57[3:0]});
16768 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_57[47:0]});
16769
16770 end //}
16771 if (update_isfsr_fw2)
16772 begin //{
16773 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
16774 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_57[2:0]});
16775 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_57[47:0]});
16776
16777 end //}
16778 if (take_err_trap_fw2)
16779 begin //{
16780 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
16781 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
16782 end // }
16783 end // }
16784
16785end //}
16786
16787//removing the addr check as the LSU doesn't flag an invalid_asi_exception
16788//if the addr of diagnostic accesses is not in the valid range. The inst.
16789//still executes. LSU expects that HP won't use addresses in invalid range.
16790
16791always @(negedge (`SPC7.l2clk & ready))
16792begin // {
16793 sync_asi = 1'b0;
16794 ld_data_w <= `ASI_LD_DATA_57;
16795
16796 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_57)
16797 chk_if_asi_ld <= 1'b1;
16798 else
16799 chk_if_asi_ld <= 1'b0;
16800
16801 if (chk_if_asi_ld & `ASI_LD_57)
16802 begin
16803 case (`ASI_57)
16804 8'h66: //ASI_IC_INSTR
16805 begin
16806 //if ((`ASI_ADDR_57 >= 0) & (`ASI_ADDR_57 <= 40'h7ff8))
16807 sync_asi = 1'b1;
16808 end
16809 8'h67: //ASI_IC_TAG
16810 begin
16811 //if ((`ASI_ADDR_57 >= 0) & (`ASI_ADDR_57 <= 40'h7fe0))
16812 sync_asi = 1'b1;
16813 end
16814 8'h46: //ASI_DC_DATA
16815 begin
16816 sync_asi = 1'b1;
16817 end
16818 8'h47: //ASI_DC_TAG
16819 begin
16820 //if ((`ASI_ADDR_57 >= 0) & (`ASI_ADDR_57 <= 40'h7ff0))
16821 sync_asi = 1'b1;
16822 end
16823 8'h48://IRF ECC
16824 begin
16825 //if ((`ASI_ADDR_57 >= 0) & (`ASI_ADDR_57 <= 40'hF8))
16826 sync_asi = 1'b1;
16827 end
16828 8'h49://FRF ECC
16829 begin
16830 //if ((`ASI_ADDR_57 >= 0) & (`ASI_ADDR_57 <= 40'hF8))
16831 sync_asi = 1'b1;
16832 end
16833 8'h4A://STB access, stb ptr can be read also
16834 begin
16835 //if ((`ASI_ADDR_57 >= 0) & (`ASI_ADDR_57 <= 40'h100))
16836 sync_asi = 1'b1;
16837 end
16838 8'h5A://Tick compare reg
16839 begin
16840 //if ((`ASI_ADDR_57 >= 0) & (`ASI_ADDR_57 <= 40'h38))
16841 sync_asi = 1'b1;
16842 end
16843 8'h5B://TSA
16844 begin
16845 //if ((`ASI_ADDR_57 >= 0) & (`ASI_ADDR_57 <= 40'h38))
16846 sync_asi = 1'b1;
16847 end
16848 8'h51://MRA
16849 begin
16850 //if ((`ASI_ADDR_57 >= 0) & (`ASI_ADDR_57 <= 40'h38))
16851 sync_asi = 1'b1;
16852 end
16853 8'h59://scratchpad ecc data read
16854 begin
16855 //if ((`ASI_ADDR_57 >= 0) & (`ASI_ADDR_57 <= 40'h38))
16856 //syncup the ecc data only. For ecc bit 6 is 0.
16857 if (~`SPC7.lsu.lmd.lmq1_pkt[6])
16858 sync_asi = 1'b1;
16859 end
16860 8'h40://cwqcsr,ma_sync access
16861 begin
16862 if ((`ASI_ADDR_57 == 40'h20) || (`ASI_ADDR_57 == 40'h30)
16863 || (`ASI_ADDR_57 == 40'h80)
16864 || ((`ASI_ADDR_57 == 40'ha0) & (`SPU_MA_BUSY_7 == 0) & (`SPU_MA_TID_7 == 1))
16865 )
16866 sync_asi = 1'b1;
16867 end
16868 8'h4C://CLESR, CLFESR access
16869 begin
16870 if ((`ASI_ADDR_57 == 40'h20) || (`ASI_ADDR_57 == 40'h28))
16871 sync_asi = 1'b1;
16872 end
16873 endcase
16874 end
16875
16876 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
16877 begin
16878 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_57, `ASI_ADDR_57, ld_data_w);
16879 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_57, {24'b0, `ASI_ADDR_57}, ld_data_w[63:0]);
16880 end
16881end //}
16882`endif
16883endmodule
16884
16885
16886
16887module err_c7t2 ();
16888`ifndef GATESIM
16889
16890`include "defines.vh"
16891
16892wire [2:0] mycid;
16893wire [2:0] mytid;
16894wire [5:0] mytnum;
16895
16896integer junk;
16897reg ready;
16898reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
16899reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
16900
16901reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
16902reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
16903
16904reg update_dfesr_w;
16905
16906reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
16907reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
16908
16909reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
16910reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
16911
16912reg sync_asi;
16913reg chk_if_asi_ld;
16914reg [63:0] ld_data_w;
16915
16916reg desr_asi_rd, desr_wr, desr_pend_wr;
16917
16918assign mycid = 7;
16919assign mytid = 2;
16920assign mytnum = 7*8 + 2;
16921
16922initial begin //{
16923 desr_asi_rd = 1'b0;
16924 desr_pend_wr = 1'b0;
16925 ready = 0;
16926 @(posedge `SPC7.l2clk) ;
16927 @(posedge `SPC7.l2clk) ;
16928 ready = `PARGS.err_sync_on;
16929end //}
16930
16931`define DSFSR_NEW_IN_58 `SPC7.tlu.ras.dsfsr_2_new_in
16932`define ISFSR_NEW_IN_58 `SPC7.tlu.ras.isfsr_2_new_in
16933
16934`define DSFSR_58 `SPC7.tlu.ras.dsfsr_2
16935`define ISFSR_58 `SPC7.tlu.ras.isfsr_2
16936`define DSFAR_58 `SPC7.tlu.dfd.dsfar_2
16937
16938`define ASI_WR_DSFSR_58 `SPC7.tlu.ras.asi_wr_dsfsr[2]
16939`define ASI_WR_ISFSR_58 `SPC7.tlu.ras.asi_wr_isfsr[2]
16940
16941`define RAS_WRITE_DESR_1st_58 `SPC7.tlu.dfd.ras_write_desr_1st[2]
16942`define RAS_WRITE_DESR_2nd_58 `SPC7.tlu.dfd.ras_write_desr_2nd[2]
16943`define DESR_asi_rd_58 `SPC7.tlu.ras_rd_desr[2]
16944`define DESR_58 `SPC7.tlu.dfd.desr_2
16945
16946`define RAS_WRITE_FESR_58 `SPC7.tlu.ras.write_fesr[2]
16947`define FESR_58 `SPC7.tlu.dfd.fesr_2
16948
16949`define ST_ERR_58 `SPC7.tlu.trl0.take_ftt & `SPC7.tlu.trl0.trap[2]
16950`define SW_REC_ERR_58 `SPC7.tlu.trl0.take_ade & `SPC7.tlu.trl0.trap[2]
16951`define DATA_ACC_ERR_58 `SPC7.tlu.trl0.take_dae & `SPC7.tlu.trl0.trap[2]
16952`define INST_ACC_ERR_58 `SPC7.tlu.trl0.take_iae & `SPC7.tlu.trl0.trap[2]
16953`define INT_PROC_ERR_58 `SPC7.tlu.trl0.take_ipe & `SPC7.tlu.trl0.trap[2]
16954`define HW_CORR_ERR_58 `SPC7.tlu.trl0.take_eer & `SPC7.tlu.trl0.trap[2]
16955`define INST_ACC_MMU_ERR_58 `SPC7.tlu.trl0.take_ime & `SPC7.tlu.trl0.trap[2]
16956`define DATA_ACC_MMU_ERR_58 `SPC7.tlu.trl0.take_dme & `SPC7.tlu.trl0.trap[2]
16957
16958`define LSU_LD_VALID_B `PROBES7.lsu_ld_valid
16959`define LSU_TID_DEC_B_58 `PROBES7.lsu_tid_dec_b[2]
16960`define ASI_LD_58 `SPC7.lsu.lmd.lmq2_pkt[60] & (`SPC7.lsu.lmd.lmq2_pkt[49:48] == 2'b0)
16961`define ASI_58 `SPC7.lsu.lmd.lmq2_pkt[47:40]
16962`define ASI_ADDR_58 `SPC7.lsu.lmd.lmq2_pkt[39:0]
16963`define ASI_LD_DATA_58 `SPC7.lsu_exu_ld_data_b[63:0]
16964`define ASI_LD_COMP_58 tb_top.nas_top.c7.t2.complete_fw2
16965
16966//SPU specific - only one SPU per core
16967`define SPU_MA_BUSY_7 `SPC7.spu.spu_pmu_ma_busy[3]
16968`define SPU_MA_TID_7 `SPC7.spu.spu_pmu_ma_busy[2:0]
16969
16970////////////////////////////////////////////////////////////////////////////////
16971//Capture the status register data from rtl. For disrupting traps,
16972//rtl can modify the contents of the status register before the
16973//trap is taken and intp message is sent to Riesling.
16974//For precise traps, once the status register is updated rtl can't
16975//change the register again before jumping to the trap handler.
16976//So, for deferred and disrupting traps, inform Riesling when the
16977//register is modified while for precise traps wait until Fw2 before
16978//telling Riesling.
16979
16980//TLU asserts the flush and input signals in W stage. I latch them at the
16981//+ve edge of FX4.
16982
16983always @(negedge (`SPC7.l2clk & ready))
16984begin // {
16985 if (`DESR_asi_rd_58)
16986 desr_asi_rd <= 1'b1;
16987 if (desr_asi_rd)
16988 begin
16989 if (desr_wr)
16990 desr_pend_wr <= 1'b1;
16991 if (`ASI_LD_COMP_58[2])
16992 desr_asi_rd <= 1'b0;
16993 end
16994
16995 update_dsfsr_w <= (`DSFSR_NEW_IN_58 != 4'b0) && ~`ASI_WR_DSFSR_58;
16996 update_isfsr_w <= (`ISFSR_NEW_IN_58 != 3'b0) && ~`ASI_WR_ISFSR_58;
16997 desr_wr <= (`RAS_WRITE_DESR_1st_58 || `RAS_WRITE_DESR_2nd_58);
16998 update_dfesr_w <= `RAS_WRITE_FESR_58;
16999 take_err_trap_fx4 <= `ST_ERR_58 | `SW_REC_ERR_58 | `DATA_ACC_ERR_58
17000 | `INST_ACC_ERR_58 | `INT_PROC_ERR_58
17001 | `HW_CORR_ERR_58 | `INST_ACC_MMU_ERR_58
17002 | `DATA_ACC_MMU_ERR_58 ;
17003
17004
17005 if (`ST_ERR_58) int_num_fx4 <= 8'h07;
17006 if (`SW_REC_ERR_58) int_num_fx4 <= 8'h40;
17007 if (`DATA_ACC_ERR_58) int_num_fx4 <= 8'h32;
17008 if (`INST_ACC_ERR_58) int_num_fx4 <= 8'h0A;
17009 if (`INT_PROC_ERR_58) int_num_fx4 <= 8'h29;
17010 if (`HW_CORR_ERR_58) int_num_fx4 <= 8'h63;
17011 if (`INST_ACC_MMU_ERR_58) int_num_fx4 <= 8'h71;
17012 if (`DATA_ACC_MMU_ERR_58) int_num_fx4 <= 8'h72;
17013
17014 update_dsfsr_fx4 <= update_dsfsr_w;
17015 update_dsfsr_fx5 <= update_dsfsr_fx4;
17016 update_dsfsr_fb <= update_dsfsr_fx5;
17017 update_dsfsr_fw <= update_dsfsr_fb;
17018 update_dsfsr_fw1 <= update_dsfsr_fw;
17019 update_dsfsr_fw2 <= update_dsfsr_fw1;
17020
17021 update_isfsr_fx4 <= update_isfsr_w;
17022 update_isfsr_fx5 <= update_isfsr_fx4;
17023 update_isfsr_fb <= update_isfsr_fx5;
17024 update_isfsr_fw <= update_isfsr_fb;
17025 update_isfsr_fw1 <= update_isfsr_fw;
17026 update_isfsr_fw2 <= update_isfsr_fw1;
17027
17028 take_err_trap_fx5 <= take_err_trap_fx4;
17029 take_err_trap_fb <= take_err_trap_fx5;
17030 take_err_trap_fw <= take_err_trap_fb;
17031 take_err_trap_fw1 <= take_err_trap_fw;
17032 take_err_trap_fw2 <= take_err_trap_fw1;
17033
17034 int_num_fx5 <= int_num_fx4;
17035 int_num_fb <= int_num_fx5;
17036 int_num_fw <= int_num_fb;
17037 int_num_fw1 <= int_num_fw;
17038 int_num_fw2 <= int_num_fw1;
17039
17040 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
17041 begin // {
17042 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
17043 begin //{
17044 desr_pend_wr <= 1'b0;
17045 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_58[63:56], 45'b0, `DESR_58[10:0]});
17046 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_58[63:56], 45'b0, `DESR_58[10:0]});
17047 end //}
17048 //if (update_dfesr_w)
17049 if (`ST_ERR_58)
17050 begin //{
17051 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_58[61:55], 55'b0});
17052 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_58[61:55], 55'b0});
17053 end //}
17054 if (update_dsfsr_fw2)
17055 begin //{
17056 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
17057 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_58[3:0]});
17058 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_58[47:0]});
17059
17060 end //}
17061 if (update_isfsr_fw2)
17062 begin //{
17063 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
17064 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_58[2:0]});
17065 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_58[47:0]});
17066
17067 end //}
17068 if (take_err_trap_fw2)
17069 begin //{
17070 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
17071 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
17072 end // }
17073 end // }
17074
17075end //}
17076
17077//removing the addr check as the LSU doesn't flag an invalid_asi_exception
17078//if the addr of diagnostic accesses is not in the valid range. The inst.
17079//still executes. LSU expects that HP won't use addresses in invalid range.
17080
17081always @(negedge (`SPC7.l2clk & ready))
17082begin // {
17083 sync_asi = 1'b0;
17084 ld_data_w <= `ASI_LD_DATA_58;
17085
17086 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_58)
17087 chk_if_asi_ld <= 1'b1;
17088 else
17089 chk_if_asi_ld <= 1'b0;
17090
17091 if (chk_if_asi_ld & `ASI_LD_58)
17092 begin
17093 case (`ASI_58)
17094 8'h66: //ASI_IC_INSTR
17095 begin
17096 //if ((`ASI_ADDR_58 >= 0) & (`ASI_ADDR_58 <= 40'h7ff8))
17097 sync_asi = 1'b1;
17098 end
17099 8'h67: //ASI_IC_TAG
17100 begin
17101 //if ((`ASI_ADDR_58 >= 0) & (`ASI_ADDR_58 <= 40'h7fe0))
17102 sync_asi = 1'b1;
17103 end
17104 8'h46: //ASI_DC_DATA
17105 begin
17106 sync_asi = 1'b1;
17107 end
17108 8'h47: //ASI_DC_TAG
17109 begin
17110 //if ((`ASI_ADDR_58 >= 0) & (`ASI_ADDR_58 <= 40'h7ff0))
17111 sync_asi = 1'b1;
17112 end
17113 8'h48://IRF ECC
17114 begin
17115 //if ((`ASI_ADDR_58 >= 0) & (`ASI_ADDR_58 <= 40'hF8))
17116 sync_asi = 1'b1;
17117 end
17118 8'h49://FRF ECC
17119 begin
17120 //if ((`ASI_ADDR_58 >= 0) & (`ASI_ADDR_58 <= 40'hF8))
17121 sync_asi = 1'b1;
17122 end
17123 8'h4A://STB access, stb ptr can be read also
17124 begin
17125 //if ((`ASI_ADDR_58 >= 0) & (`ASI_ADDR_58 <= 40'h100))
17126 sync_asi = 1'b1;
17127 end
17128 8'h5A://Tick compare reg
17129 begin
17130 //if ((`ASI_ADDR_58 >= 0) & (`ASI_ADDR_58 <= 40'h38))
17131 sync_asi = 1'b1;
17132 end
17133 8'h5B://TSA
17134 begin
17135 //if ((`ASI_ADDR_58 >= 0) & (`ASI_ADDR_58 <= 40'h38))
17136 sync_asi = 1'b1;
17137 end
17138 8'h51://MRA
17139 begin
17140 //if ((`ASI_ADDR_58 >= 0) & (`ASI_ADDR_58 <= 40'h38))
17141 sync_asi = 1'b1;
17142 end
17143 8'h59://scratchpad ecc data read
17144 begin
17145 //if ((`ASI_ADDR_58 >= 0) & (`ASI_ADDR_58 <= 40'h38))
17146 //syncup the ecc data only. For ecc bit 6 is 0.
17147 if (~`SPC7.lsu.lmd.lmq2_pkt[6])
17148 sync_asi = 1'b1;
17149 end
17150 8'h40://cwqcsr,ma_sync access
17151 begin
17152 if ((`ASI_ADDR_58 == 40'h20) || (`ASI_ADDR_58 == 40'h30)
17153 || (`ASI_ADDR_58 == 40'h80)
17154 || ((`ASI_ADDR_58 == 40'ha0) & (`SPU_MA_BUSY_7 == 0) & (`SPU_MA_TID_7 == 2))
17155 )
17156 sync_asi = 1'b1;
17157 end
17158 8'h4C://CLESR, CLFESR access
17159 begin
17160 if ((`ASI_ADDR_58 == 40'h20) || (`ASI_ADDR_58 == 40'h28))
17161 sync_asi = 1'b1;
17162 end
17163 endcase
17164 end
17165
17166 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
17167 begin
17168 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_58, `ASI_ADDR_58, ld_data_w);
17169 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_58, {24'b0, `ASI_ADDR_58}, ld_data_w[63:0]);
17170 end
17171end //}
17172`endif
17173endmodule
17174
17175
17176
17177module err_c7t3 ();
17178`ifndef GATESIM
17179
17180`include "defines.vh"
17181
17182wire [2:0] mycid;
17183wire [2:0] mytid;
17184wire [5:0] mytnum;
17185
17186integer junk;
17187reg ready;
17188reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
17189reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
17190
17191reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
17192reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
17193
17194reg update_dfesr_w;
17195
17196reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
17197reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
17198
17199reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
17200reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
17201
17202reg sync_asi;
17203reg chk_if_asi_ld;
17204reg [63:0] ld_data_w;
17205
17206reg desr_asi_rd, desr_wr, desr_pend_wr;
17207
17208assign mycid = 7;
17209assign mytid = 3;
17210assign mytnum = 7*8 + 3;
17211
17212initial begin //{
17213 desr_asi_rd = 1'b0;
17214 desr_pend_wr = 1'b0;
17215 ready = 0;
17216 @(posedge `SPC7.l2clk) ;
17217 @(posedge `SPC7.l2clk) ;
17218 ready = `PARGS.err_sync_on;
17219end //}
17220
17221`define DSFSR_NEW_IN_59 `SPC7.tlu.ras.dsfsr_3_new_in
17222`define ISFSR_NEW_IN_59 `SPC7.tlu.ras.isfsr_3_new_in
17223
17224`define DSFSR_59 `SPC7.tlu.ras.dsfsr_3
17225`define ISFSR_59 `SPC7.tlu.ras.isfsr_3
17226`define DSFAR_59 `SPC7.tlu.dfd.dsfar_3
17227
17228`define ASI_WR_DSFSR_59 `SPC7.tlu.ras.asi_wr_dsfsr[3]
17229`define ASI_WR_ISFSR_59 `SPC7.tlu.ras.asi_wr_isfsr[3]
17230
17231`define RAS_WRITE_DESR_1st_59 `SPC7.tlu.dfd.ras_write_desr_1st[3]
17232`define RAS_WRITE_DESR_2nd_59 `SPC7.tlu.dfd.ras_write_desr_2nd[3]
17233`define DESR_asi_rd_59 `SPC7.tlu.ras_rd_desr[3]
17234`define DESR_59 `SPC7.tlu.dfd.desr_3
17235
17236`define RAS_WRITE_FESR_59 `SPC7.tlu.ras.write_fesr[3]
17237`define FESR_59 `SPC7.tlu.dfd.fesr_3
17238
17239`define ST_ERR_59 `SPC7.tlu.trl0.take_ftt & `SPC7.tlu.trl0.trap[3]
17240`define SW_REC_ERR_59 `SPC7.tlu.trl0.take_ade & `SPC7.tlu.trl0.trap[3]
17241`define DATA_ACC_ERR_59 `SPC7.tlu.trl0.take_dae & `SPC7.tlu.trl0.trap[3]
17242`define INST_ACC_ERR_59 `SPC7.tlu.trl0.take_iae & `SPC7.tlu.trl0.trap[3]
17243`define INT_PROC_ERR_59 `SPC7.tlu.trl0.take_ipe & `SPC7.tlu.trl0.trap[3]
17244`define HW_CORR_ERR_59 `SPC7.tlu.trl0.take_eer & `SPC7.tlu.trl0.trap[3]
17245`define INST_ACC_MMU_ERR_59 `SPC7.tlu.trl0.take_ime & `SPC7.tlu.trl0.trap[3]
17246`define DATA_ACC_MMU_ERR_59 `SPC7.tlu.trl0.take_dme & `SPC7.tlu.trl0.trap[3]
17247
17248`define LSU_LD_VALID_B `PROBES7.lsu_ld_valid
17249`define LSU_TID_DEC_B_59 `PROBES7.lsu_tid_dec_b[3]
17250`define ASI_LD_59 `SPC7.lsu.lmd.lmq3_pkt[60] & (`SPC7.lsu.lmd.lmq3_pkt[49:48] == 2'b0)
17251`define ASI_59 `SPC7.lsu.lmd.lmq3_pkt[47:40]
17252`define ASI_ADDR_59 `SPC7.lsu.lmd.lmq3_pkt[39:0]
17253`define ASI_LD_DATA_59 `SPC7.lsu_exu_ld_data_b[63:0]
17254`define ASI_LD_COMP_59 tb_top.nas_top.c7.t3.complete_fw2
17255
17256//SPU specific - only one SPU per core
17257`define SPU_MA_BUSY_7 `SPC7.spu.spu_pmu_ma_busy[3]
17258`define SPU_MA_TID_7 `SPC7.spu.spu_pmu_ma_busy[2:0]
17259
17260////////////////////////////////////////////////////////////////////////////////
17261//Capture the status register data from rtl. For disrupting traps,
17262//rtl can modify the contents of the status register before the
17263//trap is taken and intp message is sent to Riesling.
17264//For precise traps, once the status register is updated rtl can't
17265//change the register again before jumping to the trap handler.
17266//So, for deferred and disrupting traps, inform Riesling when the
17267//register is modified while for precise traps wait until Fw2 before
17268//telling Riesling.
17269
17270//TLU asserts the flush and input signals in W stage. I latch them at the
17271//+ve edge of FX4.
17272
17273always @(negedge (`SPC7.l2clk & ready))
17274begin // {
17275 if (`DESR_asi_rd_59)
17276 desr_asi_rd <= 1'b1;
17277 if (desr_asi_rd)
17278 begin
17279 if (desr_wr)
17280 desr_pend_wr <= 1'b1;
17281 if (`ASI_LD_COMP_59[2])
17282 desr_asi_rd <= 1'b0;
17283 end
17284
17285 update_dsfsr_w <= (`DSFSR_NEW_IN_59 != 4'b0) && ~`ASI_WR_DSFSR_59;
17286 update_isfsr_w <= (`ISFSR_NEW_IN_59 != 3'b0) && ~`ASI_WR_ISFSR_59;
17287 desr_wr <= (`RAS_WRITE_DESR_1st_59 || `RAS_WRITE_DESR_2nd_59);
17288 update_dfesr_w <= `RAS_WRITE_FESR_59;
17289 take_err_trap_fx4 <= `ST_ERR_59 | `SW_REC_ERR_59 | `DATA_ACC_ERR_59
17290 | `INST_ACC_ERR_59 | `INT_PROC_ERR_59
17291 | `HW_CORR_ERR_59 | `INST_ACC_MMU_ERR_59
17292 | `DATA_ACC_MMU_ERR_59 ;
17293
17294
17295 if (`ST_ERR_59) int_num_fx4 <= 8'h07;
17296 if (`SW_REC_ERR_59) int_num_fx4 <= 8'h40;
17297 if (`DATA_ACC_ERR_59) int_num_fx4 <= 8'h32;
17298 if (`INST_ACC_ERR_59) int_num_fx4 <= 8'h0A;
17299 if (`INT_PROC_ERR_59) int_num_fx4 <= 8'h29;
17300 if (`HW_CORR_ERR_59) int_num_fx4 <= 8'h63;
17301 if (`INST_ACC_MMU_ERR_59) int_num_fx4 <= 8'h71;
17302 if (`DATA_ACC_MMU_ERR_59) int_num_fx4 <= 8'h72;
17303
17304 update_dsfsr_fx4 <= update_dsfsr_w;
17305 update_dsfsr_fx5 <= update_dsfsr_fx4;
17306 update_dsfsr_fb <= update_dsfsr_fx5;
17307 update_dsfsr_fw <= update_dsfsr_fb;
17308 update_dsfsr_fw1 <= update_dsfsr_fw;
17309 update_dsfsr_fw2 <= update_dsfsr_fw1;
17310
17311 update_isfsr_fx4 <= update_isfsr_w;
17312 update_isfsr_fx5 <= update_isfsr_fx4;
17313 update_isfsr_fb <= update_isfsr_fx5;
17314 update_isfsr_fw <= update_isfsr_fb;
17315 update_isfsr_fw1 <= update_isfsr_fw;
17316 update_isfsr_fw2 <= update_isfsr_fw1;
17317
17318 take_err_trap_fx5 <= take_err_trap_fx4;
17319 take_err_trap_fb <= take_err_trap_fx5;
17320 take_err_trap_fw <= take_err_trap_fb;
17321 take_err_trap_fw1 <= take_err_trap_fw;
17322 take_err_trap_fw2 <= take_err_trap_fw1;
17323
17324 int_num_fx5 <= int_num_fx4;
17325 int_num_fb <= int_num_fx5;
17326 int_num_fw <= int_num_fb;
17327 int_num_fw1 <= int_num_fw;
17328 int_num_fw2 <= int_num_fw1;
17329
17330 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
17331 begin // {
17332 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
17333 begin //{
17334 desr_pend_wr <= 1'b0;
17335 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_59[63:56], 45'b0, `DESR_59[10:0]});
17336 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_59[63:56], 45'b0, `DESR_59[10:0]});
17337 end //}
17338 //if (update_dfesr_w)
17339 if (`ST_ERR_59)
17340 begin //{
17341 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_59[61:55], 55'b0});
17342 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_59[61:55], 55'b0});
17343 end //}
17344 if (update_dsfsr_fw2)
17345 begin //{
17346 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
17347 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_59[3:0]});
17348 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_59[47:0]});
17349
17350 end //}
17351 if (update_isfsr_fw2)
17352 begin //{
17353 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
17354 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_59[2:0]});
17355 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_59[47:0]});
17356
17357 end //}
17358 if (take_err_trap_fw2)
17359 begin //{
17360 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
17361 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
17362 end // }
17363 end // }
17364
17365end //}
17366
17367//removing the addr check as the LSU doesn't flag an invalid_asi_exception
17368//if the addr of diagnostic accesses is not in the valid range. The inst.
17369//still executes. LSU expects that HP won't use addresses in invalid range.
17370
17371always @(negedge (`SPC7.l2clk & ready))
17372begin // {
17373 sync_asi = 1'b0;
17374 ld_data_w <= `ASI_LD_DATA_59;
17375
17376 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_59)
17377 chk_if_asi_ld <= 1'b1;
17378 else
17379 chk_if_asi_ld <= 1'b0;
17380
17381 if (chk_if_asi_ld & `ASI_LD_59)
17382 begin
17383 case (`ASI_59)
17384 8'h66: //ASI_IC_INSTR
17385 begin
17386 //if ((`ASI_ADDR_59 >= 0) & (`ASI_ADDR_59 <= 40'h7ff8))
17387 sync_asi = 1'b1;
17388 end
17389 8'h67: //ASI_IC_TAG
17390 begin
17391 //if ((`ASI_ADDR_59 >= 0) & (`ASI_ADDR_59 <= 40'h7fe0))
17392 sync_asi = 1'b1;
17393 end
17394 8'h46: //ASI_DC_DATA
17395 begin
17396 sync_asi = 1'b1;
17397 end
17398 8'h47: //ASI_DC_TAG
17399 begin
17400 //if ((`ASI_ADDR_59 >= 0) & (`ASI_ADDR_59 <= 40'h7ff0))
17401 sync_asi = 1'b1;
17402 end
17403 8'h48://IRF ECC
17404 begin
17405 //if ((`ASI_ADDR_59 >= 0) & (`ASI_ADDR_59 <= 40'hF8))
17406 sync_asi = 1'b1;
17407 end
17408 8'h49://FRF ECC
17409 begin
17410 //if ((`ASI_ADDR_59 >= 0) & (`ASI_ADDR_59 <= 40'hF8))
17411 sync_asi = 1'b1;
17412 end
17413 8'h4A://STB access, stb ptr can be read also
17414 begin
17415 //if ((`ASI_ADDR_59 >= 0) & (`ASI_ADDR_59 <= 40'h100))
17416 sync_asi = 1'b1;
17417 end
17418 8'h5A://Tick compare reg
17419 begin
17420 //if ((`ASI_ADDR_59 >= 0) & (`ASI_ADDR_59 <= 40'h38))
17421 sync_asi = 1'b1;
17422 end
17423 8'h5B://TSA
17424 begin
17425 //if ((`ASI_ADDR_59 >= 0) & (`ASI_ADDR_59 <= 40'h38))
17426 sync_asi = 1'b1;
17427 end
17428 8'h51://MRA
17429 begin
17430 //if ((`ASI_ADDR_59 >= 0) & (`ASI_ADDR_59 <= 40'h38))
17431 sync_asi = 1'b1;
17432 end
17433 8'h59://scratchpad ecc data read
17434 begin
17435 //if ((`ASI_ADDR_59 >= 0) & (`ASI_ADDR_59 <= 40'h38))
17436 //syncup the ecc data only. For ecc bit 6 is 0.
17437 if (~`SPC7.lsu.lmd.lmq3_pkt[6])
17438 sync_asi = 1'b1;
17439 end
17440 8'h40://cwqcsr,ma_sync access
17441 begin
17442 if ((`ASI_ADDR_59 == 40'h20) || (`ASI_ADDR_59 == 40'h30)
17443 || (`ASI_ADDR_59 == 40'h80)
17444 || ((`ASI_ADDR_59 == 40'ha0) & (`SPU_MA_BUSY_7 == 0) & (`SPU_MA_TID_7 == 3))
17445 )
17446 sync_asi = 1'b1;
17447 end
17448 8'h4C://CLESR, CLFESR access
17449 begin
17450 if ((`ASI_ADDR_59 == 40'h20) || (`ASI_ADDR_59 == 40'h28))
17451 sync_asi = 1'b1;
17452 end
17453 endcase
17454 end
17455
17456 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
17457 begin
17458 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_59, `ASI_ADDR_59, ld_data_w);
17459 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_59, {24'b0, `ASI_ADDR_59}, ld_data_w[63:0]);
17460 end
17461end //}
17462`endif
17463endmodule
17464
17465
17466
17467module err_c7t4 ();
17468`ifndef GATESIM
17469
17470`include "defines.vh"
17471
17472wire [2:0] mycid;
17473wire [2:0] mytid;
17474wire [5:0] mytnum;
17475
17476integer junk;
17477reg ready;
17478reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
17479reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
17480
17481reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
17482reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
17483
17484reg update_dfesr_w;
17485
17486reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
17487reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
17488
17489reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
17490reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
17491
17492reg sync_asi;
17493reg chk_if_asi_ld;
17494reg [63:0] ld_data_w;
17495
17496reg desr_asi_rd, desr_wr, desr_pend_wr;
17497
17498assign mycid = 7;
17499assign mytid = 4;
17500assign mytnum = 7*8 + 4;
17501
17502initial begin //{
17503 desr_asi_rd = 1'b0;
17504 desr_pend_wr = 1'b0;
17505 ready = 0;
17506 @(posedge `SPC7.l2clk) ;
17507 @(posedge `SPC7.l2clk) ;
17508 ready = `PARGS.err_sync_on;
17509end //}
17510
17511`define DSFSR_NEW_IN_60 `SPC7.tlu.ras.dsfsr_4_new_in
17512`define ISFSR_NEW_IN_60 `SPC7.tlu.ras.isfsr_4_new_in
17513
17514`define DSFSR_60 `SPC7.tlu.ras.dsfsr_4
17515`define ISFSR_60 `SPC7.tlu.ras.isfsr_4
17516`define DSFAR_60 `SPC7.tlu.dfd.dsfar_4
17517
17518`define ASI_WR_DSFSR_60 `SPC7.tlu.ras.asi_wr_dsfsr[4]
17519`define ASI_WR_ISFSR_60 `SPC7.tlu.ras.asi_wr_isfsr[4]
17520
17521`define RAS_WRITE_DESR_1st_60 `SPC7.tlu.dfd.ras_write_desr_1st[4]
17522`define RAS_WRITE_DESR_2nd_60 `SPC7.tlu.dfd.ras_write_desr_2nd[4]
17523`define DESR_asi_rd_60 `SPC7.tlu.ras_rd_desr[4]
17524`define DESR_60 `SPC7.tlu.dfd.desr_4
17525
17526`define RAS_WRITE_FESR_60 `SPC7.tlu.ras.write_fesr[4]
17527`define FESR_60 `SPC7.tlu.dfd.fesr_4
17528
17529`define ST_ERR_60 `SPC7.tlu.trl1.take_ftt & `SPC7.tlu.trl1.trap[0]
17530`define SW_REC_ERR_60 `SPC7.tlu.trl1.take_ade & `SPC7.tlu.trl1.trap[0]
17531`define DATA_ACC_ERR_60 `SPC7.tlu.trl1.take_dae & `SPC7.tlu.trl1.trap[0]
17532`define INST_ACC_ERR_60 `SPC7.tlu.trl1.take_iae & `SPC7.tlu.trl1.trap[0]
17533`define INT_PROC_ERR_60 `SPC7.tlu.trl1.take_ipe & `SPC7.tlu.trl1.trap[0]
17534`define HW_CORR_ERR_60 `SPC7.tlu.trl1.take_eer & `SPC7.tlu.trl1.trap[0]
17535`define INST_ACC_MMU_ERR_60 `SPC7.tlu.trl1.take_ime & `SPC7.tlu.trl1.trap[0]
17536`define DATA_ACC_MMU_ERR_60 `SPC7.tlu.trl1.take_dme & `SPC7.tlu.trl1.trap[0]
17537
17538`define LSU_LD_VALID_B `PROBES7.lsu_ld_valid
17539`define LSU_TID_DEC_B_60 `PROBES7.lsu_tid_dec_b[4]
17540`define ASI_LD_60 `SPC7.lsu.lmd.lmq4_pkt[60] & (`SPC7.lsu.lmd.lmq4_pkt[49:48] == 2'b0)
17541`define ASI_60 `SPC7.lsu.lmd.lmq4_pkt[47:40]
17542`define ASI_ADDR_60 `SPC7.lsu.lmd.lmq4_pkt[39:0]
17543`define ASI_LD_DATA_60 `SPC7.lsu_exu_ld_data_b[63:0]
17544`define ASI_LD_COMP_60 tb_top.nas_top.c7.t4.complete_fw2
17545
17546//SPU specific - only one SPU per core
17547`define SPU_MA_BUSY_7 `SPC7.spu.spu_pmu_ma_busy[3]
17548`define SPU_MA_TID_7 `SPC7.spu.spu_pmu_ma_busy[2:0]
17549
17550////////////////////////////////////////////////////////////////////////////////
17551//Capture the status register data from rtl. For disrupting traps,
17552//rtl can modify the contents of the status register before the
17553//trap is taken and intp message is sent to Riesling.
17554//For precise traps, once the status register is updated rtl can't
17555//change the register again before jumping to the trap handler.
17556//So, for deferred and disrupting traps, inform Riesling when the
17557//register is modified while for precise traps wait until Fw2 before
17558//telling Riesling.
17559
17560//TLU asserts the flush and input signals in W stage. I latch them at the
17561//+ve edge of FX4.
17562
17563always @(negedge (`SPC7.l2clk & ready))
17564begin // {
17565 if (`DESR_asi_rd_60)
17566 desr_asi_rd <= 1'b1;
17567 if (desr_asi_rd)
17568 begin
17569 if (desr_wr)
17570 desr_pend_wr <= 1'b1;
17571 if (`ASI_LD_COMP_60[2])
17572 desr_asi_rd <= 1'b0;
17573 end
17574
17575 update_dsfsr_w <= (`DSFSR_NEW_IN_60 != 4'b0) && ~`ASI_WR_DSFSR_60;
17576 update_isfsr_w <= (`ISFSR_NEW_IN_60 != 3'b0) && ~`ASI_WR_ISFSR_60;
17577 desr_wr <= (`RAS_WRITE_DESR_1st_60 || `RAS_WRITE_DESR_2nd_60);
17578 update_dfesr_w <= `RAS_WRITE_FESR_60;
17579 take_err_trap_fx4 <= `ST_ERR_60 | `SW_REC_ERR_60 | `DATA_ACC_ERR_60
17580 | `INST_ACC_ERR_60 | `INT_PROC_ERR_60
17581 | `HW_CORR_ERR_60 | `INST_ACC_MMU_ERR_60
17582 | `DATA_ACC_MMU_ERR_60 ;
17583
17584
17585 if (`ST_ERR_60) int_num_fx4 <= 8'h07;
17586 if (`SW_REC_ERR_60) int_num_fx4 <= 8'h40;
17587 if (`DATA_ACC_ERR_60) int_num_fx4 <= 8'h32;
17588 if (`INST_ACC_ERR_60) int_num_fx4 <= 8'h0A;
17589 if (`INT_PROC_ERR_60) int_num_fx4 <= 8'h29;
17590 if (`HW_CORR_ERR_60) int_num_fx4 <= 8'h63;
17591 if (`INST_ACC_MMU_ERR_60) int_num_fx4 <= 8'h71;
17592 if (`DATA_ACC_MMU_ERR_60) int_num_fx4 <= 8'h72;
17593
17594 update_dsfsr_fx4 <= update_dsfsr_w;
17595 update_dsfsr_fx5 <= update_dsfsr_fx4;
17596 update_dsfsr_fb <= update_dsfsr_fx5;
17597 update_dsfsr_fw <= update_dsfsr_fb;
17598 update_dsfsr_fw1 <= update_dsfsr_fw;
17599 update_dsfsr_fw2 <= update_dsfsr_fw1;
17600
17601 update_isfsr_fx4 <= update_isfsr_w;
17602 update_isfsr_fx5 <= update_isfsr_fx4;
17603 update_isfsr_fb <= update_isfsr_fx5;
17604 update_isfsr_fw <= update_isfsr_fb;
17605 update_isfsr_fw1 <= update_isfsr_fw;
17606 update_isfsr_fw2 <= update_isfsr_fw1;
17607
17608 take_err_trap_fx5 <= take_err_trap_fx4;
17609 take_err_trap_fb <= take_err_trap_fx5;
17610 take_err_trap_fw <= take_err_trap_fb;
17611 take_err_trap_fw1 <= take_err_trap_fw;
17612 take_err_trap_fw2 <= take_err_trap_fw1;
17613
17614 int_num_fx5 <= int_num_fx4;
17615 int_num_fb <= int_num_fx5;
17616 int_num_fw <= int_num_fb;
17617 int_num_fw1 <= int_num_fw;
17618 int_num_fw2 <= int_num_fw1;
17619
17620 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
17621 begin // {
17622 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
17623 begin //{
17624 desr_pend_wr <= 1'b0;
17625 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_60[63:56], 45'b0, `DESR_60[10:0]});
17626 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_60[63:56], 45'b0, `DESR_60[10:0]});
17627 end //}
17628 //if (update_dfesr_w)
17629 if (`ST_ERR_60)
17630 begin //{
17631 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_60[61:55], 55'b0});
17632 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_60[61:55], 55'b0});
17633 end //}
17634 if (update_dsfsr_fw2)
17635 begin //{
17636 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
17637 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_60[3:0]});
17638 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_60[47:0]});
17639
17640 end //}
17641 if (update_isfsr_fw2)
17642 begin //{
17643 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
17644 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_60[2:0]});
17645 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_60[47:0]});
17646
17647 end //}
17648 if (take_err_trap_fw2)
17649 begin //{
17650 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
17651 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
17652 end // }
17653 end // }
17654
17655end //}
17656
17657//removing the addr check as the LSU doesn't flag an invalid_asi_exception
17658//if the addr of diagnostic accesses is not in the valid range. The inst.
17659//still executes. LSU expects that HP won't use addresses in invalid range.
17660
17661always @(negedge (`SPC7.l2clk & ready))
17662begin // {
17663 sync_asi = 1'b0;
17664 ld_data_w <= `ASI_LD_DATA_60;
17665
17666 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_60)
17667 chk_if_asi_ld <= 1'b1;
17668 else
17669 chk_if_asi_ld <= 1'b0;
17670
17671 if (chk_if_asi_ld & `ASI_LD_60)
17672 begin
17673 case (`ASI_60)
17674 8'h66: //ASI_IC_INSTR
17675 begin
17676 //if ((`ASI_ADDR_60 >= 0) & (`ASI_ADDR_60 <= 40'h7ff8))
17677 sync_asi = 1'b1;
17678 end
17679 8'h67: //ASI_IC_TAG
17680 begin
17681 //if ((`ASI_ADDR_60 >= 0) & (`ASI_ADDR_60 <= 40'h7fe0))
17682 sync_asi = 1'b1;
17683 end
17684 8'h46: //ASI_DC_DATA
17685 begin
17686 sync_asi = 1'b1;
17687 end
17688 8'h47: //ASI_DC_TAG
17689 begin
17690 //if ((`ASI_ADDR_60 >= 0) & (`ASI_ADDR_60 <= 40'h7ff0))
17691 sync_asi = 1'b1;
17692 end
17693 8'h48://IRF ECC
17694 begin
17695 //if ((`ASI_ADDR_60 >= 0) & (`ASI_ADDR_60 <= 40'hF8))
17696 sync_asi = 1'b1;
17697 end
17698 8'h49://FRF ECC
17699 begin
17700 //if ((`ASI_ADDR_60 >= 0) & (`ASI_ADDR_60 <= 40'hF8))
17701 sync_asi = 1'b1;
17702 end
17703 8'h4A://STB access, stb ptr can be read also
17704 begin
17705 //if ((`ASI_ADDR_60 >= 0) & (`ASI_ADDR_60 <= 40'h100))
17706 sync_asi = 1'b1;
17707 end
17708 8'h5A://Tick compare reg
17709 begin
17710 //if ((`ASI_ADDR_60 >= 0) & (`ASI_ADDR_60 <= 40'h38))
17711 sync_asi = 1'b1;
17712 end
17713 8'h5B://TSA
17714 begin
17715 //if ((`ASI_ADDR_60 >= 0) & (`ASI_ADDR_60 <= 40'h38))
17716 sync_asi = 1'b1;
17717 end
17718 8'h51://MRA
17719 begin
17720 //if ((`ASI_ADDR_60 >= 0) & (`ASI_ADDR_60 <= 40'h38))
17721 sync_asi = 1'b1;
17722 end
17723 8'h59://scratchpad ecc data read
17724 begin
17725 //if ((`ASI_ADDR_60 >= 0) & (`ASI_ADDR_60 <= 40'h38))
17726 //syncup the ecc data only. For ecc bit 6 is 0.
17727 if (~`SPC7.lsu.lmd.lmq4_pkt[6])
17728 sync_asi = 1'b1;
17729 end
17730 8'h40://cwqcsr,ma_sync access
17731 begin
17732 if ((`ASI_ADDR_60 == 40'h20) || (`ASI_ADDR_60 == 40'h30)
17733 || (`ASI_ADDR_60 == 40'h80)
17734 || ((`ASI_ADDR_60 == 40'ha0) & (`SPU_MA_BUSY_7 == 0) & (`SPU_MA_TID_7 == 4))
17735 )
17736 sync_asi = 1'b1;
17737 end
17738 8'h4C://CLESR, CLFESR access
17739 begin
17740 if ((`ASI_ADDR_60 == 40'h20) || (`ASI_ADDR_60 == 40'h28))
17741 sync_asi = 1'b1;
17742 end
17743 endcase
17744 end
17745
17746 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
17747 begin
17748 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_60, `ASI_ADDR_60, ld_data_w);
17749 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_60, {24'b0, `ASI_ADDR_60}, ld_data_w[63:0]);
17750 end
17751end //}
17752`endif
17753endmodule
17754
17755
17756
17757module err_c7t5 ();
17758`ifndef GATESIM
17759
17760`include "defines.vh"
17761
17762wire [2:0] mycid;
17763wire [2:0] mytid;
17764wire [5:0] mytnum;
17765
17766integer junk;
17767reg ready;
17768reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
17769reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
17770
17771reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
17772reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
17773
17774reg update_dfesr_w;
17775
17776reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
17777reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
17778
17779reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
17780reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
17781
17782reg sync_asi;
17783reg chk_if_asi_ld;
17784reg [63:0] ld_data_w;
17785
17786reg desr_asi_rd, desr_wr, desr_pend_wr;
17787
17788assign mycid = 7;
17789assign mytid = 5;
17790assign mytnum = 7*8 + 5;
17791
17792initial begin //{
17793 desr_asi_rd = 1'b0;
17794 desr_pend_wr = 1'b0;
17795 ready = 0;
17796 @(posedge `SPC7.l2clk) ;
17797 @(posedge `SPC7.l2clk) ;
17798 ready = `PARGS.err_sync_on;
17799end //}
17800
17801`define DSFSR_NEW_IN_61 `SPC7.tlu.ras.dsfsr_5_new_in
17802`define ISFSR_NEW_IN_61 `SPC7.tlu.ras.isfsr_5_new_in
17803
17804`define DSFSR_61 `SPC7.tlu.ras.dsfsr_5
17805`define ISFSR_61 `SPC7.tlu.ras.isfsr_5
17806`define DSFAR_61 `SPC7.tlu.dfd.dsfar_5
17807
17808`define ASI_WR_DSFSR_61 `SPC7.tlu.ras.asi_wr_dsfsr[5]
17809`define ASI_WR_ISFSR_61 `SPC7.tlu.ras.asi_wr_isfsr[5]
17810
17811`define RAS_WRITE_DESR_1st_61 `SPC7.tlu.dfd.ras_write_desr_1st[5]
17812`define RAS_WRITE_DESR_2nd_61 `SPC7.tlu.dfd.ras_write_desr_2nd[5]
17813`define DESR_asi_rd_61 `SPC7.tlu.ras_rd_desr[5]
17814`define DESR_61 `SPC7.tlu.dfd.desr_5
17815
17816`define RAS_WRITE_FESR_61 `SPC7.tlu.ras.write_fesr[5]
17817`define FESR_61 `SPC7.tlu.dfd.fesr_5
17818
17819`define ST_ERR_61 `SPC7.tlu.trl1.take_ftt & `SPC7.tlu.trl1.trap[1]
17820`define SW_REC_ERR_61 `SPC7.tlu.trl1.take_ade & `SPC7.tlu.trl1.trap[1]
17821`define DATA_ACC_ERR_61 `SPC7.tlu.trl1.take_dae & `SPC7.tlu.trl1.trap[1]
17822`define INST_ACC_ERR_61 `SPC7.tlu.trl1.take_iae & `SPC7.tlu.trl1.trap[1]
17823`define INT_PROC_ERR_61 `SPC7.tlu.trl1.take_ipe & `SPC7.tlu.trl1.trap[1]
17824`define HW_CORR_ERR_61 `SPC7.tlu.trl1.take_eer & `SPC7.tlu.trl1.trap[1]
17825`define INST_ACC_MMU_ERR_61 `SPC7.tlu.trl1.take_ime & `SPC7.tlu.trl1.trap[1]
17826`define DATA_ACC_MMU_ERR_61 `SPC7.tlu.trl1.take_dme & `SPC7.tlu.trl1.trap[1]
17827
17828`define LSU_LD_VALID_B `PROBES7.lsu_ld_valid
17829`define LSU_TID_DEC_B_61 `PROBES7.lsu_tid_dec_b[5]
17830`define ASI_LD_61 `SPC7.lsu.lmd.lmq5_pkt[60] & (`SPC7.lsu.lmd.lmq5_pkt[49:48] == 2'b0)
17831`define ASI_61 `SPC7.lsu.lmd.lmq5_pkt[47:40]
17832`define ASI_ADDR_61 `SPC7.lsu.lmd.lmq5_pkt[39:0]
17833`define ASI_LD_DATA_61 `SPC7.lsu_exu_ld_data_b[63:0]
17834`define ASI_LD_COMP_61 tb_top.nas_top.c7.t5.complete_fw2
17835
17836//SPU specific - only one SPU per core
17837`define SPU_MA_BUSY_7 `SPC7.spu.spu_pmu_ma_busy[3]
17838`define SPU_MA_TID_7 `SPC7.spu.spu_pmu_ma_busy[2:0]
17839
17840////////////////////////////////////////////////////////////////////////////////
17841//Capture the status register data from rtl. For disrupting traps,
17842//rtl can modify the contents of the status register before the
17843//trap is taken and intp message is sent to Riesling.
17844//For precise traps, once the status register is updated rtl can't
17845//change the register again before jumping to the trap handler.
17846//So, for deferred and disrupting traps, inform Riesling when the
17847//register is modified while for precise traps wait until Fw2 before
17848//telling Riesling.
17849
17850//TLU asserts the flush and input signals in W stage. I latch them at the
17851//+ve edge of FX4.
17852
17853always @(negedge (`SPC7.l2clk & ready))
17854begin // {
17855 if (`DESR_asi_rd_61)
17856 desr_asi_rd <= 1'b1;
17857 if (desr_asi_rd)
17858 begin
17859 if (desr_wr)
17860 desr_pend_wr <= 1'b1;
17861 if (`ASI_LD_COMP_61[2])
17862 desr_asi_rd <= 1'b0;
17863 end
17864
17865 update_dsfsr_w <= (`DSFSR_NEW_IN_61 != 4'b0) && ~`ASI_WR_DSFSR_61;
17866 update_isfsr_w <= (`ISFSR_NEW_IN_61 != 3'b0) && ~`ASI_WR_ISFSR_61;
17867 desr_wr <= (`RAS_WRITE_DESR_1st_61 || `RAS_WRITE_DESR_2nd_61);
17868 update_dfesr_w <= `RAS_WRITE_FESR_61;
17869 take_err_trap_fx4 <= `ST_ERR_61 | `SW_REC_ERR_61 | `DATA_ACC_ERR_61
17870 | `INST_ACC_ERR_61 | `INT_PROC_ERR_61
17871 | `HW_CORR_ERR_61 | `INST_ACC_MMU_ERR_61
17872 | `DATA_ACC_MMU_ERR_61 ;
17873
17874
17875 if (`ST_ERR_61) int_num_fx4 <= 8'h07;
17876 if (`SW_REC_ERR_61) int_num_fx4 <= 8'h40;
17877 if (`DATA_ACC_ERR_61) int_num_fx4 <= 8'h32;
17878 if (`INST_ACC_ERR_61) int_num_fx4 <= 8'h0A;
17879 if (`INT_PROC_ERR_61) int_num_fx4 <= 8'h29;
17880 if (`HW_CORR_ERR_61) int_num_fx4 <= 8'h63;
17881 if (`INST_ACC_MMU_ERR_61) int_num_fx4 <= 8'h71;
17882 if (`DATA_ACC_MMU_ERR_61) int_num_fx4 <= 8'h72;
17883
17884 update_dsfsr_fx4 <= update_dsfsr_w;
17885 update_dsfsr_fx5 <= update_dsfsr_fx4;
17886 update_dsfsr_fb <= update_dsfsr_fx5;
17887 update_dsfsr_fw <= update_dsfsr_fb;
17888 update_dsfsr_fw1 <= update_dsfsr_fw;
17889 update_dsfsr_fw2 <= update_dsfsr_fw1;
17890
17891 update_isfsr_fx4 <= update_isfsr_w;
17892 update_isfsr_fx5 <= update_isfsr_fx4;
17893 update_isfsr_fb <= update_isfsr_fx5;
17894 update_isfsr_fw <= update_isfsr_fb;
17895 update_isfsr_fw1 <= update_isfsr_fw;
17896 update_isfsr_fw2 <= update_isfsr_fw1;
17897
17898 take_err_trap_fx5 <= take_err_trap_fx4;
17899 take_err_trap_fb <= take_err_trap_fx5;
17900 take_err_trap_fw <= take_err_trap_fb;
17901 take_err_trap_fw1 <= take_err_trap_fw;
17902 take_err_trap_fw2 <= take_err_trap_fw1;
17903
17904 int_num_fx5 <= int_num_fx4;
17905 int_num_fb <= int_num_fx5;
17906 int_num_fw <= int_num_fb;
17907 int_num_fw1 <= int_num_fw;
17908 int_num_fw2 <= int_num_fw1;
17909
17910 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
17911 begin // {
17912 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
17913 begin //{
17914 desr_pend_wr <= 1'b0;
17915 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_61[63:56], 45'b0, `DESR_61[10:0]});
17916 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_61[63:56], 45'b0, `DESR_61[10:0]});
17917 end //}
17918 //if (update_dfesr_w)
17919 if (`ST_ERR_61)
17920 begin //{
17921 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_61[61:55], 55'b0});
17922 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_61[61:55], 55'b0});
17923 end //}
17924 if (update_dsfsr_fw2)
17925 begin //{
17926 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
17927 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_61[3:0]});
17928 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_61[47:0]});
17929
17930 end //}
17931 if (update_isfsr_fw2)
17932 begin //{
17933 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
17934 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_61[2:0]});
17935 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_61[47:0]});
17936
17937 end //}
17938 if (take_err_trap_fw2)
17939 begin //{
17940 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
17941 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
17942 end // }
17943 end // }
17944
17945end //}
17946
17947//removing the addr check as the LSU doesn't flag an invalid_asi_exception
17948//if the addr of diagnostic accesses is not in the valid range. The inst.
17949//still executes. LSU expects that HP won't use addresses in invalid range.
17950
17951always @(negedge (`SPC7.l2clk & ready))
17952begin // {
17953 sync_asi = 1'b0;
17954 ld_data_w <= `ASI_LD_DATA_61;
17955
17956 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_61)
17957 chk_if_asi_ld <= 1'b1;
17958 else
17959 chk_if_asi_ld <= 1'b0;
17960
17961 if (chk_if_asi_ld & `ASI_LD_61)
17962 begin
17963 case (`ASI_61)
17964 8'h66: //ASI_IC_INSTR
17965 begin
17966 //if ((`ASI_ADDR_61 >= 0) & (`ASI_ADDR_61 <= 40'h7ff8))
17967 sync_asi = 1'b1;
17968 end
17969 8'h67: //ASI_IC_TAG
17970 begin
17971 //if ((`ASI_ADDR_61 >= 0) & (`ASI_ADDR_61 <= 40'h7fe0))
17972 sync_asi = 1'b1;
17973 end
17974 8'h46: //ASI_DC_DATA
17975 begin
17976 sync_asi = 1'b1;
17977 end
17978 8'h47: //ASI_DC_TAG
17979 begin
17980 //if ((`ASI_ADDR_61 >= 0) & (`ASI_ADDR_61 <= 40'h7ff0))
17981 sync_asi = 1'b1;
17982 end
17983 8'h48://IRF ECC
17984 begin
17985 //if ((`ASI_ADDR_61 >= 0) & (`ASI_ADDR_61 <= 40'hF8))
17986 sync_asi = 1'b1;
17987 end
17988 8'h49://FRF ECC
17989 begin
17990 //if ((`ASI_ADDR_61 >= 0) & (`ASI_ADDR_61 <= 40'hF8))
17991 sync_asi = 1'b1;
17992 end
17993 8'h4A://STB access, stb ptr can be read also
17994 begin
17995 //if ((`ASI_ADDR_61 >= 0) & (`ASI_ADDR_61 <= 40'h100))
17996 sync_asi = 1'b1;
17997 end
17998 8'h5A://Tick compare reg
17999 begin
18000 //if ((`ASI_ADDR_61 >= 0) & (`ASI_ADDR_61 <= 40'h38))
18001 sync_asi = 1'b1;
18002 end
18003 8'h5B://TSA
18004 begin
18005 //if ((`ASI_ADDR_61 >= 0) & (`ASI_ADDR_61 <= 40'h38))
18006 sync_asi = 1'b1;
18007 end
18008 8'h51://MRA
18009 begin
18010 //if ((`ASI_ADDR_61 >= 0) & (`ASI_ADDR_61 <= 40'h38))
18011 sync_asi = 1'b1;
18012 end
18013 8'h59://scratchpad ecc data read
18014 begin
18015 //if ((`ASI_ADDR_61 >= 0) & (`ASI_ADDR_61 <= 40'h38))
18016 //syncup the ecc data only. For ecc bit 6 is 0.
18017 if (~`SPC7.lsu.lmd.lmq5_pkt[6])
18018 sync_asi = 1'b1;
18019 end
18020 8'h40://cwqcsr,ma_sync access
18021 begin
18022 if ((`ASI_ADDR_61 == 40'h20) || (`ASI_ADDR_61 == 40'h30)
18023 || (`ASI_ADDR_61 == 40'h80)
18024 || ((`ASI_ADDR_61 == 40'ha0) & (`SPU_MA_BUSY_7 == 0) & (`SPU_MA_TID_7 == 5))
18025 )
18026 sync_asi = 1'b1;
18027 end
18028 8'h4C://CLESR, CLFESR access
18029 begin
18030 if ((`ASI_ADDR_61 == 40'h20) || (`ASI_ADDR_61 == 40'h28))
18031 sync_asi = 1'b1;
18032 end
18033 endcase
18034 end
18035
18036 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
18037 begin
18038 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_61, `ASI_ADDR_61, ld_data_w);
18039 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_61, {24'b0, `ASI_ADDR_61}, ld_data_w[63:0]);
18040 end
18041end //}
18042`endif
18043endmodule
18044
18045
18046
18047module err_c7t6 ();
18048`ifndef GATESIM
18049
18050`include "defines.vh"
18051
18052wire [2:0] mycid;
18053wire [2:0] mytid;
18054wire [5:0] mytnum;
18055
18056integer junk;
18057reg ready;
18058reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
18059reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
18060
18061reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
18062reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
18063
18064reg update_dfesr_w;
18065
18066reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
18067reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
18068
18069reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
18070reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
18071
18072reg sync_asi;
18073reg chk_if_asi_ld;
18074reg [63:0] ld_data_w;
18075
18076reg desr_asi_rd, desr_wr, desr_pend_wr;
18077
18078assign mycid = 7;
18079assign mytid = 6;
18080assign mytnum = 7*8 + 6;
18081
18082initial begin //{
18083 desr_asi_rd = 1'b0;
18084 desr_pend_wr = 1'b0;
18085 ready = 0;
18086 @(posedge `SPC7.l2clk) ;
18087 @(posedge `SPC7.l2clk) ;
18088 ready = `PARGS.err_sync_on;
18089end //}
18090
18091`define DSFSR_NEW_IN_62 `SPC7.tlu.ras.dsfsr_6_new_in
18092`define ISFSR_NEW_IN_62 `SPC7.tlu.ras.isfsr_6_new_in
18093
18094`define DSFSR_62 `SPC7.tlu.ras.dsfsr_6
18095`define ISFSR_62 `SPC7.tlu.ras.isfsr_6
18096`define DSFAR_62 `SPC7.tlu.dfd.dsfar_6
18097
18098`define ASI_WR_DSFSR_62 `SPC7.tlu.ras.asi_wr_dsfsr[6]
18099`define ASI_WR_ISFSR_62 `SPC7.tlu.ras.asi_wr_isfsr[6]
18100
18101`define RAS_WRITE_DESR_1st_62 `SPC7.tlu.dfd.ras_write_desr_1st[6]
18102`define RAS_WRITE_DESR_2nd_62 `SPC7.tlu.dfd.ras_write_desr_2nd[6]
18103`define DESR_asi_rd_62 `SPC7.tlu.ras_rd_desr[6]
18104`define DESR_62 `SPC7.tlu.dfd.desr_6
18105
18106`define RAS_WRITE_FESR_62 `SPC7.tlu.ras.write_fesr[6]
18107`define FESR_62 `SPC7.tlu.dfd.fesr_6
18108
18109`define ST_ERR_62 `SPC7.tlu.trl1.take_ftt & `SPC7.tlu.trl1.trap[2]
18110`define SW_REC_ERR_62 `SPC7.tlu.trl1.take_ade & `SPC7.tlu.trl1.trap[2]
18111`define DATA_ACC_ERR_62 `SPC7.tlu.trl1.take_dae & `SPC7.tlu.trl1.trap[2]
18112`define INST_ACC_ERR_62 `SPC7.tlu.trl1.take_iae & `SPC7.tlu.trl1.trap[2]
18113`define INT_PROC_ERR_62 `SPC7.tlu.trl1.take_ipe & `SPC7.tlu.trl1.trap[2]
18114`define HW_CORR_ERR_62 `SPC7.tlu.trl1.take_eer & `SPC7.tlu.trl1.trap[2]
18115`define INST_ACC_MMU_ERR_62 `SPC7.tlu.trl1.take_ime & `SPC7.tlu.trl1.trap[2]
18116`define DATA_ACC_MMU_ERR_62 `SPC7.tlu.trl1.take_dme & `SPC7.tlu.trl1.trap[2]
18117
18118`define LSU_LD_VALID_B `PROBES7.lsu_ld_valid
18119`define LSU_TID_DEC_B_62 `PROBES7.lsu_tid_dec_b[6]
18120`define ASI_LD_62 `SPC7.lsu.lmd.lmq6_pkt[60] & (`SPC7.lsu.lmd.lmq6_pkt[49:48] == 2'b0)
18121`define ASI_62 `SPC7.lsu.lmd.lmq6_pkt[47:40]
18122`define ASI_ADDR_62 `SPC7.lsu.lmd.lmq6_pkt[39:0]
18123`define ASI_LD_DATA_62 `SPC7.lsu_exu_ld_data_b[63:0]
18124`define ASI_LD_COMP_62 tb_top.nas_top.c7.t6.complete_fw2
18125
18126//SPU specific - only one SPU per core
18127`define SPU_MA_BUSY_7 `SPC7.spu.spu_pmu_ma_busy[3]
18128`define SPU_MA_TID_7 `SPC7.spu.spu_pmu_ma_busy[2:0]
18129
18130////////////////////////////////////////////////////////////////////////////////
18131//Capture the status register data from rtl. For disrupting traps,
18132//rtl can modify the contents of the status register before the
18133//trap is taken and intp message is sent to Riesling.
18134//For precise traps, once the status register is updated rtl can't
18135//change the register again before jumping to the trap handler.
18136//So, for deferred and disrupting traps, inform Riesling when the
18137//register is modified while for precise traps wait until Fw2 before
18138//telling Riesling.
18139
18140//TLU asserts the flush and input signals in W stage. I latch them at the
18141//+ve edge of FX4.
18142
18143always @(negedge (`SPC7.l2clk & ready))
18144begin // {
18145 if (`DESR_asi_rd_62)
18146 desr_asi_rd <= 1'b1;
18147 if (desr_asi_rd)
18148 begin
18149 if (desr_wr)
18150 desr_pend_wr <= 1'b1;
18151 if (`ASI_LD_COMP_62[2])
18152 desr_asi_rd <= 1'b0;
18153 end
18154
18155 update_dsfsr_w <= (`DSFSR_NEW_IN_62 != 4'b0) && ~`ASI_WR_DSFSR_62;
18156 update_isfsr_w <= (`ISFSR_NEW_IN_62 != 3'b0) && ~`ASI_WR_ISFSR_62;
18157 desr_wr <= (`RAS_WRITE_DESR_1st_62 || `RAS_WRITE_DESR_2nd_62);
18158 update_dfesr_w <= `RAS_WRITE_FESR_62;
18159 take_err_trap_fx4 <= `ST_ERR_62 | `SW_REC_ERR_62 | `DATA_ACC_ERR_62
18160 | `INST_ACC_ERR_62 | `INT_PROC_ERR_62
18161 | `HW_CORR_ERR_62 | `INST_ACC_MMU_ERR_62
18162 | `DATA_ACC_MMU_ERR_62 ;
18163
18164
18165 if (`ST_ERR_62) int_num_fx4 <= 8'h07;
18166 if (`SW_REC_ERR_62) int_num_fx4 <= 8'h40;
18167 if (`DATA_ACC_ERR_62) int_num_fx4 <= 8'h32;
18168 if (`INST_ACC_ERR_62) int_num_fx4 <= 8'h0A;
18169 if (`INT_PROC_ERR_62) int_num_fx4 <= 8'h29;
18170 if (`HW_CORR_ERR_62) int_num_fx4 <= 8'h63;
18171 if (`INST_ACC_MMU_ERR_62) int_num_fx4 <= 8'h71;
18172 if (`DATA_ACC_MMU_ERR_62) int_num_fx4 <= 8'h72;
18173
18174 update_dsfsr_fx4 <= update_dsfsr_w;
18175 update_dsfsr_fx5 <= update_dsfsr_fx4;
18176 update_dsfsr_fb <= update_dsfsr_fx5;
18177 update_dsfsr_fw <= update_dsfsr_fb;
18178 update_dsfsr_fw1 <= update_dsfsr_fw;
18179 update_dsfsr_fw2 <= update_dsfsr_fw1;
18180
18181 update_isfsr_fx4 <= update_isfsr_w;
18182 update_isfsr_fx5 <= update_isfsr_fx4;
18183 update_isfsr_fb <= update_isfsr_fx5;
18184 update_isfsr_fw <= update_isfsr_fb;
18185 update_isfsr_fw1 <= update_isfsr_fw;
18186 update_isfsr_fw2 <= update_isfsr_fw1;
18187
18188 take_err_trap_fx5 <= take_err_trap_fx4;
18189 take_err_trap_fb <= take_err_trap_fx5;
18190 take_err_trap_fw <= take_err_trap_fb;
18191 take_err_trap_fw1 <= take_err_trap_fw;
18192 take_err_trap_fw2 <= take_err_trap_fw1;
18193
18194 int_num_fx5 <= int_num_fx4;
18195 int_num_fb <= int_num_fx5;
18196 int_num_fw <= int_num_fb;
18197 int_num_fw1 <= int_num_fw;
18198 int_num_fw2 <= int_num_fw1;
18199
18200 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
18201 begin // {
18202 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
18203 begin //{
18204 desr_pend_wr <= 1'b0;
18205 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_62[63:56], 45'b0, `DESR_62[10:0]});
18206 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_62[63:56], 45'b0, `DESR_62[10:0]});
18207 end //}
18208 //if (update_dfesr_w)
18209 if (`ST_ERR_62)
18210 begin //{
18211 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_62[61:55], 55'b0});
18212 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_62[61:55], 55'b0});
18213 end //}
18214 if (update_dsfsr_fw2)
18215 begin //{
18216 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
18217 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_62[3:0]});
18218 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_62[47:0]});
18219
18220 end //}
18221 if (update_isfsr_fw2)
18222 begin //{
18223 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
18224 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_62[2:0]});
18225 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_62[47:0]});
18226
18227 end //}
18228 if (take_err_trap_fw2)
18229 begin //{
18230 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
18231 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
18232 end // }
18233 end // }
18234
18235end //}
18236
18237//removing the addr check as the LSU doesn't flag an invalid_asi_exception
18238//if the addr of diagnostic accesses is not in the valid range. The inst.
18239//still executes. LSU expects that HP won't use addresses in invalid range.
18240
18241always @(negedge (`SPC7.l2clk & ready))
18242begin // {
18243 sync_asi = 1'b0;
18244 ld_data_w <= `ASI_LD_DATA_62;
18245
18246 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_62)
18247 chk_if_asi_ld <= 1'b1;
18248 else
18249 chk_if_asi_ld <= 1'b0;
18250
18251 if (chk_if_asi_ld & `ASI_LD_62)
18252 begin
18253 case (`ASI_62)
18254 8'h66: //ASI_IC_INSTR
18255 begin
18256 //if ((`ASI_ADDR_62 >= 0) & (`ASI_ADDR_62 <= 40'h7ff8))
18257 sync_asi = 1'b1;
18258 end
18259 8'h67: //ASI_IC_TAG
18260 begin
18261 //if ((`ASI_ADDR_62 >= 0) & (`ASI_ADDR_62 <= 40'h7fe0))
18262 sync_asi = 1'b1;
18263 end
18264 8'h46: //ASI_DC_DATA
18265 begin
18266 sync_asi = 1'b1;
18267 end
18268 8'h47: //ASI_DC_TAG
18269 begin
18270 //if ((`ASI_ADDR_62 >= 0) & (`ASI_ADDR_62 <= 40'h7ff0))
18271 sync_asi = 1'b1;
18272 end
18273 8'h48://IRF ECC
18274 begin
18275 //if ((`ASI_ADDR_62 >= 0) & (`ASI_ADDR_62 <= 40'hF8))
18276 sync_asi = 1'b1;
18277 end
18278 8'h49://FRF ECC
18279 begin
18280 //if ((`ASI_ADDR_62 >= 0) & (`ASI_ADDR_62 <= 40'hF8))
18281 sync_asi = 1'b1;
18282 end
18283 8'h4A://STB access, stb ptr can be read also
18284 begin
18285 //if ((`ASI_ADDR_62 >= 0) & (`ASI_ADDR_62 <= 40'h100))
18286 sync_asi = 1'b1;
18287 end
18288 8'h5A://Tick compare reg
18289 begin
18290 //if ((`ASI_ADDR_62 >= 0) & (`ASI_ADDR_62 <= 40'h38))
18291 sync_asi = 1'b1;
18292 end
18293 8'h5B://TSA
18294 begin
18295 //if ((`ASI_ADDR_62 >= 0) & (`ASI_ADDR_62 <= 40'h38))
18296 sync_asi = 1'b1;
18297 end
18298 8'h51://MRA
18299 begin
18300 //if ((`ASI_ADDR_62 >= 0) & (`ASI_ADDR_62 <= 40'h38))
18301 sync_asi = 1'b1;
18302 end
18303 8'h59://scratchpad ecc data read
18304 begin
18305 //if ((`ASI_ADDR_62 >= 0) & (`ASI_ADDR_62 <= 40'h38))
18306 //syncup the ecc data only. For ecc bit 6 is 0.
18307 if (~`SPC7.lsu.lmd.lmq6_pkt[6])
18308 sync_asi = 1'b1;
18309 end
18310 8'h40://cwqcsr,ma_sync access
18311 begin
18312 if ((`ASI_ADDR_62 == 40'h20) || (`ASI_ADDR_62 == 40'h30)
18313 || (`ASI_ADDR_62 == 40'h80)
18314 || ((`ASI_ADDR_62 == 40'ha0) & (`SPU_MA_BUSY_7 == 0) & (`SPU_MA_TID_7 == 6))
18315 )
18316 sync_asi = 1'b1;
18317 end
18318 8'h4C://CLESR, CLFESR access
18319 begin
18320 if ((`ASI_ADDR_62 == 40'h20) || (`ASI_ADDR_62 == 40'h28))
18321 sync_asi = 1'b1;
18322 end
18323 endcase
18324 end
18325
18326 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
18327 begin
18328 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_62, `ASI_ADDR_62, ld_data_w);
18329 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_62, {24'b0, `ASI_ADDR_62}, ld_data_w[63:0]);
18330 end
18331end //}
18332`endif
18333endmodule
18334
18335
18336
18337module err_c7t7 ();
18338`ifndef GATESIM
18339
18340`include "defines.vh"
18341
18342wire [2:0] mycid;
18343wire [2:0] mytid;
18344wire [5:0] mytnum;
18345
18346integer junk;
18347reg ready;
18348reg update_dsfsr_w, update_dsfsr_fx4, update_dsfsr_fx5;
18349reg update_dsfsr_fb, update_dsfsr_fw, update_dsfsr_fw1, update_dsfsr_fw2;
18350
18351reg update_isfsr_w, update_isfsr_fx4, update_isfsr_fx5;
18352reg update_isfsr_fb, update_isfsr_fw, update_isfsr_fw1, update_isfsr_fw2;
18353
18354reg update_dfesr_w;
18355
18356reg take_err_trap_fx4, take_err_trap_fx5, take_err_trap_fb;
18357reg take_err_trap_fw, take_err_trap_fw1, take_err_trap_fw2;
18358
18359reg [7:0] int_num_fx4, int_num_fx5, int_num_fb;
18360reg [7:0] int_num_fw, int_num_fw1, int_num_fw2;
18361
18362reg sync_asi;
18363reg chk_if_asi_ld;
18364reg [63:0] ld_data_w;
18365
18366reg desr_asi_rd, desr_wr, desr_pend_wr;
18367
18368assign mycid = 7;
18369assign mytid = 7;
18370assign mytnum = 7*8 + 7;
18371
18372initial begin //{
18373 desr_asi_rd = 1'b0;
18374 desr_pend_wr = 1'b0;
18375 ready = 0;
18376 @(posedge `SPC7.l2clk) ;
18377 @(posedge `SPC7.l2clk) ;
18378 ready = `PARGS.err_sync_on;
18379end //}
18380
18381`define DSFSR_NEW_IN_63 `SPC7.tlu.ras.dsfsr_7_new_in
18382`define ISFSR_NEW_IN_63 `SPC7.tlu.ras.isfsr_7_new_in
18383
18384`define DSFSR_63 `SPC7.tlu.ras.dsfsr_7
18385`define ISFSR_63 `SPC7.tlu.ras.isfsr_7
18386`define DSFAR_63 `SPC7.tlu.dfd.dsfar_7
18387
18388`define ASI_WR_DSFSR_63 `SPC7.tlu.ras.asi_wr_dsfsr[7]
18389`define ASI_WR_ISFSR_63 `SPC7.tlu.ras.asi_wr_isfsr[7]
18390
18391`define RAS_WRITE_DESR_1st_63 `SPC7.tlu.dfd.ras_write_desr_1st[7]
18392`define RAS_WRITE_DESR_2nd_63 `SPC7.tlu.dfd.ras_write_desr_2nd[7]
18393`define DESR_asi_rd_63 `SPC7.tlu.ras_rd_desr[7]
18394`define DESR_63 `SPC7.tlu.dfd.desr_7
18395
18396`define RAS_WRITE_FESR_63 `SPC7.tlu.ras.write_fesr[7]
18397`define FESR_63 `SPC7.tlu.dfd.fesr_7
18398
18399`define ST_ERR_63 `SPC7.tlu.trl1.take_ftt & `SPC7.tlu.trl1.trap[3]
18400`define SW_REC_ERR_63 `SPC7.tlu.trl1.take_ade & `SPC7.tlu.trl1.trap[3]
18401`define DATA_ACC_ERR_63 `SPC7.tlu.trl1.take_dae & `SPC7.tlu.trl1.trap[3]
18402`define INST_ACC_ERR_63 `SPC7.tlu.trl1.take_iae & `SPC7.tlu.trl1.trap[3]
18403`define INT_PROC_ERR_63 `SPC7.tlu.trl1.take_ipe & `SPC7.tlu.trl1.trap[3]
18404`define HW_CORR_ERR_63 `SPC7.tlu.trl1.take_eer & `SPC7.tlu.trl1.trap[3]
18405`define INST_ACC_MMU_ERR_63 `SPC7.tlu.trl1.take_ime & `SPC7.tlu.trl1.trap[3]
18406`define DATA_ACC_MMU_ERR_63 `SPC7.tlu.trl1.take_dme & `SPC7.tlu.trl1.trap[3]
18407
18408`define LSU_LD_VALID_B `PROBES7.lsu_ld_valid
18409`define LSU_TID_DEC_B_63 `PROBES7.lsu_tid_dec_b[7]
18410`define ASI_LD_63 `SPC7.lsu.lmd.lmq7_pkt[60] & (`SPC7.lsu.lmd.lmq7_pkt[49:48] == 2'b0)
18411`define ASI_63 `SPC7.lsu.lmd.lmq7_pkt[47:40]
18412`define ASI_ADDR_63 `SPC7.lsu.lmd.lmq7_pkt[39:0]
18413`define ASI_LD_DATA_63 `SPC7.lsu_exu_ld_data_b[63:0]
18414`define ASI_LD_COMP_63 tb_top.nas_top.c7.t7.complete_fw2
18415
18416//SPU specific - only one SPU per core
18417`define SPU_MA_BUSY_7 `SPC7.spu.spu_pmu_ma_busy[3]
18418`define SPU_MA_TID_7 `SPC7.spu.spu_pmu_ma_busy[2:0]
18419
18420////////////////////////////////////////////////////////////////////////////////
18421//Capture the status register data from rtl. For disrupting traps,
18422//rtl can modify the contents of the status register before the
18423//trap is taken and intp message is sent to Riesling.
18424//For precise traps, once the status register is updated rtl can't
18425//change the register again before jumping to the trap handler.
18426//So, for deferred and disrupting traps, inform Riesling when the
18427//register is modified while for precise traps wait until Fw2 before
18428//telling Riesling.
18429
18430//TLU asserts the flush and input signals in W stage. I latch them at the
18431//+ve edge of FX4.
18432
18433always @(negedge (`SPC7.l2clk & ready))
18434begin // {
18435 if (`DESR_asi_rd_63)
18436 desr_asi_rd <= 1'b1;
18437 if (desr_asi_rd)
18438 begin
18439 if (desr_wr)
18440 desr_pend_wr <= 1'b1;
18441 if (`ASI_LD_COMP_63[2])
18442 desr_asi_rd <= 1'b0;
18443 end
18444
18445 update_dsfsr_w <= (`DSFSR_NEW_IN_63 != 4'b0) && ~`ASI_WR_DSFSR_63;
18446 update_isfsr_w <= (`ISFSR_NEW_IN_63 != 3'b0) && ~`ASI_WR_ISFSR_63;
18447 desr_wr <= (`RAS_WRITE_DESR_1st_63 || `RAS_WRITE_DESR_2nd_63);
18448 update_dfesr_w <= `RAS_WRITE_FESR_63;
18449 take_err_trap_fx4 <= `ST_ERR_63 | `SW_REC_ERR_63 | `DATA_ACC_ERR_63
18450 | `INST_ACC_ERR_63 | `INT_PROC_ERR_63
18451 | `HW_CORR_ERR_63 | `INST_ACC_MMU_ERR_63
18452 | `DATA_ACC_MMU_ERR_63 ;
18453
18454
18455 if (`ST_ERR_63) int_num_fx4 <= 8'h07;
18456 if (`SW_REC_ERR_63) int_num_fx4 <= 8'h40;
18457 if (`DATA_ACC_ERR_63) int_num_fx4 <= 8'h32;
18458 if (`INST_ACC_ERR_63) int_num_fx4 <= 8'h0A;
18459 if (`INT_PROC_ERR_63) int_num_fx4 <= 8'h29;
18460 if (`HW_CORR_ERR_63) int_num_fx4 <= 8'h63;
18461 if (`INST_ACC_MMU_ERR_63) int_num_fx4 <= 8'h71;
18462 if (`DATA_ACC_MMU_ERR_63) int_num_fx4 <= 8'h72;
18463
18464 update_dsfsr_fx4 <= update_dsfsr_w;
18465 update_dsfsr_fx5 <= update_dsfsr_fx4;
18466 update_dsfsr_fb <= update_dsfsr_fx5;
18467 update_dsfsr_fw <= update_dsfsr_fb;
18468 update_dsfsr_fw1 <= update_dsfsr_fw;
18469 update_dsfsr_fw2 <= update_dsfsr_fw1;
18470
18471 update_isfsr_fx4 <= update_isfsr_w;
18472 update_isfsr_fx5 <= update_isfsr_fx4;
18473 update_isfsr_fb <= update_isfsr_fx5;
18474 update_isfsr_fw <= update_isfsr_fb;
18475 update_isfsr_fw1 <= update_isfsr_fw;
18476 update_isfsr_fw2 <= update_isfsr_fw1;
18477
18478 take_err_trap_fx5 <= take_err_trap_fx4;
18479 take_err_trap_fb <= take_err_trap_fx5;
18480 take_err_trap_fw <= take_err_trap_fb;
18481 take_err_trap_fw1 <= take_err_trap_fw;
18482 take_err_trap_fw2 <= take_err_trap_fw1;
18483
18484 int_num_fx5 <= int_num_fx4;
18485 int_num_fb <= int_num_fx5;
18486 int_num_fw <= int_num_fb;
18487 int_num_fw1 <= int_num_fw;
18488 int_num_fw2 <= int_num_fw1;
18489
18490 if (`PARGS.nas_check_on && `PARGS.err_sync_on)
18491 begin // {
18492 if ((desr_wr & ~desr_asi_rd) || (desr_pend_wr & ~desr_asi_rd))
18493 begin //{
18494 desr_pend_wr <= 1'b0;
18495 `PR_INFO ("err_sync", `INFO, "<C%0d T%0d> UPDATE_DESR. Data = %0h", mycid,mytid, {`DESR_63[63:56], 45'b0, `DESR_63[10:0]});
18496 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h0, {`DESR_63[63:56], 45'b0, `DESR_63[10:0]});
18497 end //}
18498 //if (update_dfesr_w)
18499 if (`ST_ERR_63)
18500 begin //{
18501 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DFESR. Data = %0h", mycid,mytid, {2'b0, `FESR_63[61:55], 55'b0});
18502 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h4C, 64'h8, {2'b0, `FESR_63[61:55], 55'b0});
18503 end //}
18504 if (update_dsfsr_fw2)
18505 begin //{
18506 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_DSFSR", mycid,mytid);
18507 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h18, {60'b0, `DSFSR_63[3:0]});
18508 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_63[47:0]});
18509
18510 end //}
18511 if (update_isfsr_fw2)
18512 begin //{
18513 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> UPDATE_ISFSR", mycid,mytid);
18514 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h50, 64'h18, {61'b0, `ISFSR_63[2:0]});
18515 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h58, 64'h20, {16'b0, `DSFAR_63[47:0]});
18516
18517 end //}
18518 if (take_err_trap_fw2)
18519 begin //{
18520 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> ERR_TRAP_TAKEN 0x%0h", mycid, mytid, int_num_fw2);
18521 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
18522 end // }
18523 end // }
18524
18525end //}
18526
18527//removing the addr check as the LSU doesn't flag an invalid_asi_exception
18528//if the addr of diagnostic accesses is not in the valid range. The inst.
18529//still executes. LSU expects that HP won't use addresses in invalid range.
18530
18531always @(negedge (`SPC7.l2clk & ready))
18532begin // {
18533 sync_asi = 1'b0;
18534 ld_data_w <= `ASI_LD_DATA_63;
18535
18536 if (`LSU_LD_VALID_B & `LSU_TID_DEC_B_63)
18537 chk_if_asi_ld <= 1'b1;
18538 else
18539 chk_if_asi_ld <= 1'b0;
18540
18541 if (chk_if_asi_ld & `ASI_LD_63)
18542 begin
18543 case (`ASI_63)
18544 8'h66: //ASI_IC_INSTR
18545 begin
18546 //if ((`ASI_ADDR_63 >= 0) & (`ASI_ADDR_63 <= 40'h7ff8))
18547 sync_asi = 1'b1;
18548 end
18549 8'h67: //ASI_IC_TAG
18550 begin
18551 //if ((`ASI_ADDR_63 >= 0) & (`ASI_ADDR_63 <= 40'h7fe0))
18552 sync_asi = 1'b1;
18553 end
18554 8'h46: //ASI_DC_DATA
18555 begin
18556 sync_asi = 1'b1;
18557 end
18558 8'h47: //ASI_DC_TAG
18559 begin
18560 //if ((`ASI_ADDR_63 >= 0) & (`ASI_ADDR_63 <= 40'h7ff0))
18561 sync_asi = 1'b1;
18562 end
18563 8'h48://IRF ECC
18564 begin
18565 //if ((`ASI_ADDR_63 >= 0) & (`ASI_ADDR_63 <= 40'hF8))
18566 sync_asi = 1'b1;
18567 end
18568 8'h49://FRF ECC
18569 begin
18570 //if ((`ASI_ADDR_63 >= 0) & (`ASI_ADDR_63 <= 40'hF8))
18571 sync_asi = 1'b1;
18572 end
18573 8'h4A://STB access, stb ptr can be read also
18574 begin
18575 //if ((`ASI_ADDR_63 >= 0) & (`ASI_ADDR_63 <= 40'h100))
18576 sync_asi = 1'b1;
18577 end
18578 8'h5A://Tick compare reg
18579 begin
18580 //if ((`ASI_ADDR_63 >= 0) & (`ASI_ADDR_63 <= 40'h38))
18581 sync_asi = 1'b1;
18582 end
18583 8'h5B://TSA
18584 begin
18585 //if ((`ASI_ADDR_63 >= 0) & (`ASI_ADDR_63 <= 40'h38))
18586 sync_asi = 1'b1;
18587 end
18588 8'h51://MRA
18589 begin
18590 //if ((`ASI_ADDR_63 >= 0) & (`ASI_ADDR_63 <= 40'h38))
18591 sync_asi = 1'b1;
18592 end
18593 8'h59://scratchpad ecc data read
18594 begin
18595 //if ((`ASI_ADDR_63 >= 0) & (`ASI_ADDR_63 <= 40'h38))
18596 //syncup the ecc data only. For ecc bit 6 is 0.
18597 if (~`SPC7.lsu.lmd.lmq7_pkt[6])
18598 sync_asi = 1'b1;
18599 end
18600 8'h40://cwqcsr,ma_sync access
18601 begin
18602 if ((`ASI_ADDR_63 == 40'h20) || (`ASI_ADDR_63 == 40'h30)
18603 || (`ASI_ADDR_63 == 40'h80)
18604 || ((`ASI_ADDR_63 == 40'ha0) & (`SPU_MA_BUSY_7 == 0) & (`SPU_MA_TID_7 == 7))
18605 )
18606 sync_asi = 1'b1;
18607 end
18608 8'h4C://CLESR, CLFESR access
18609 begin
18610 if ((`ASI_ADDR_63 == 40'h20) || (`ASI_ADDR_63 == 40'h28))
18611 sync_asi = 1'b1;
18612 end
18613 endcase
18614 end
18615
18616 if (`PARGS.nas_check_on && `PARGS.err_sync_on && sync_asi)
18617 begin
18618 `PR_INFO ("err_sync", `INFO, "<C%0dT%0d> SYNC ASI %0h. VA = %0h, data = %0h", mycid,mytid, `ASI_63, `ASI_ADDR_63, ld_data_w);
18619 junk = $sim_send(`PLI_ASI_READ, mytnum ,`ASI_63, {24'b0, `ASI_ADDR_63}, ld_data_w[63:0]);
18620 end
18621end //}
18622`endif
18623endmodule
18624
18625`endif
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