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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / niu / rxc_sat / vera / monitor / control_fifo_chkr.vr
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: control_fifo_chkr.vr
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#include <vera_defines.vrh>
36
37#include "control_fifo_mon.vri"
38#include "mbox_class.vrh"
39#include "ip_ingress_classes.vrh"
40
41extern mbox_class mbox_id;
42
43class control_fifo_chkr{
44
45 integer my_port;
46
47 local bit randomize_req_drv = 1'b1; // Enabled by default ?
48 local bit [15:0] start_delay = 16'h0; // Default is NO delay
49 bit check_2B_cntl_hdr_only;
50
51 Mesg be_msg_cntl_fifo;
52
53 task new(integer iport);
54
55 task check_cntl_port (dmc_zcp_drv_port port_bind, integer port_num);
56
57}
58
59task control_fifo_chkr::new( integer iport ){
60
61 static bit[7:0] ports_used = 0;
62
63 if (get_plus_arg(CHECK, "EN_2B_CTRL_FIFO_CHK_ONLY"))
64 check_2B_cntl_hdr_only = 1;
65 else
66 check_2B_cntl_hdr_only = 0;
67
68 be_msg_cntl_fifo = new;
69
70 if(iport > 3 ) {
71 error("ERROR: FAKE DMC_RXC I/F module: Port %0d is invalid.\n", iport);
72 return;
73 }
74
75 // Check if port already in use
76 if(ports_used[iport] == 1) {
77 error("\nERROR: FAKE DMC_RXC I/F module is already attached to port %0d"
78 ,iport);
79 my_port = -1;
80 terminate;
81 }
82 else my_port = iport;
83
84
85 fork
86 case (my_port) {
87
88 0: begin
89 check_cntl_port (dmc_zcp_drv0, 0);
90 end
91 1: begin
92 check_cntl_port (dmc_zcp_drv1, 1);
93 end
94 }
95
96 join none
97}
98
99
100task control_fifo_chkr::check_cntl_port(dmc_zcp_drv_port port_bind, integer port_num){
101
102integer num_of_cycle = 0;
103Cpkt_info fflp_ctrl_pkt;
104bit [129:0] control_fifo_data_1, control_fifo_data_2;
105integer rtl_pkt_id;
106
107 // allocate the mailboxes from which to snoop the fflp_model pkt,
108 // to compare it with the RTL packet
109 mbox_id.cntl_chkr_mbox[port_num] = alloc(MAILBOX, 0, 1);
110 rtl_pkt_id = 0;
111
112 while (1) {
113 @(posedge port_bind.$clk);
114
115 if ((port_bind.$control_fifo_ack == 1'b1) && (num_of_cycle == 0)) {
116 control_fifo_data_1 = port_bind.$control_fifo_data[129:0];
117 printf("%0d: First Cycle Control fifo = %h\n", {get_time(HI), get_time(LO)}, control_fifo_data_1);
118
119 // get the control fifo model object from FFLP to compare with the RTL snoop
120 mailbox_get(WAIT, mbox_id.cntl_chkr_mbox[port_num], fflp_ctrl_pkt);
121 num_of_cycle = num_of_cycle + 1;
122 }
123 else {
124 if (port_bind.$control_fifo_ack == 1'b1) {
125 control_fifo_data_2 = port_bind.$control_fifo_data[129:0];
126 printf("%0d: Second Cycle Control fifo Data = %h\n",
127 {get_time(HI), get_time(LO)}, control_fifo_data_2[129:0]);
128 printf("CNTL_FIFO_CHKR: ---------------------------------------------------\n");
129 printf("CNTL_FIFO_CHKR: Control FIFO Checker RTL_PKT_ID = %d \n", rtl_pkt_id);
130 printf("CNTL_FIFO_CHKR: ---------------------------------------------------\n");
131 printf("CNTL_FIFO_CHKR: RTL MODEL \n");
132 printf("CNTL_FIFO_CHKR: ---------------------------------------------------\n");
133 // Second Cycle
134 if (!check_2B_cntl_hdr_only) {
135 if (control_fifo_data_2[71:40]!==fflp_ctrl_pkt.tcp_seq_num)
136 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "TCP-sequence = %0h\t\t%0h\n", control_fifo_data_2[71:40], fflp_ctrl_pkt.tcp_seq_num);
137 else
138 printf("CNTL_FIFO_CHKR: TCP-sequence = %0h\t\t%0h\n", control_fifo_data_2[71:40], fflp_ctrl_pkt.tcp_seq_num);
139 if (control_fifo_data_2[75:72]!==fflp_ctrl_pkt.tcp_hdr_len)
140 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "TCP-hdr-len = %0h\t\t%0h\n", control_fifo_data_2[75:72], fflp_ctrl_pkt.tcp_hdr_len);
141 else
142 printf("CNTL_FIFO_CHKR: TCP-hdr-len = %0h\t\t%0h\n", control_fifo_data_2[75:72], fflp_ctrl_pkt.tcp_hdr_len);
143 if (control_fifo_data_2[75:72]!==fflp_ctrl_pkt.tcp_hdr_len)
144 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "Ipv4-hdr-len = %0h\t\t%0h\n", control_fifo_data_2[79:76], fflp_ctrl_pkt.ipv4_hdr_len);
145 else
146 printf("CNTL_FIFO_CHKR: Ipv4-hdr-len = %0h\t\t%0h\n", control_fifo_data_2[79:76], fflp_ctrl_pkt.ipv4_hdr_len);
147 if (control_fifo_data_2[75:72]!==fflp_ctrl_pkt.tcp_hdr_len)
148 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "L3-pkt-len = %0h\t\t%0h\n", control_fifo_data_2[95:80], fflp_ctrl_pkt.L3_pkt_len);
149 else
150 printf("CNTL_FIFO_CHKR: L3-pkt-len = %0h\t\t%0h\n", control_fifo_data_2[95:80], fflp_ctrl_pkt.L3_pkt_len);
151
152 if (control_fifo_data_2[75:72]!==fflp_ctrl_pkt.tcp_hdr_len)
153 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "zc-RDC = %0h\t\t%0h\n", control_fifo_data_2[100:96], fflp_ctrl_pkt.zc_rdc);
154 else
155 printf("CNTL_FIFO_CHKR: zc-RDC = %0h\t\t%0h\n", control_fifo_data_2[100:96], fflp_ctrl_pkt.zc_rdc);
156
157
158 if (control_fifo_data_2[102:101]!==fflp_ctrl_pkt.dmaw_type)
159 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "DMAW-type = %0h\t\t%0h\n", control_fifo_data_2[102:101], fflp_ctrl_pkt.dmaw_type);
160 else
161 printf("CNTL_FIFO_CHKR: DMAW-type = %0h\t\t%0h\n", control_fifo_data_2[102:101], fflp_ctrl_pkt.dmaw_type);
162
163 if (control_fifo_data_2[105:104]!==fflp_ctrl_pkt.L4_protocol)
164 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "ULP-type = %0h\t\t%0h\n", control_fifo_data_2[105:104], fflp_ctrl_pkt.L4_protocol);
165 else
166 printf("CNTL_FIFO_CHKR: ULP-type = %0h\t\t%0h\n", control_fifo_data_2[105:104], fflp_ctrl_pkt.L4_protocol);
167
168 if (control_fifo_data_2[109:106]!==fflp_ctrl_pkt.pkt_id)
169 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "Pkt-ID = %0h\t\t%0h\n", control_fifo_data_2[109:106], fflp_ctrl_pkt.pkt_id);
170 else
171 printf("CNTL_FIFO_CHKR: Pkt-ID = %0h\t\t%0h\n", control_fifo_data_2[109:106], fflp_ctrl_pkt.pkt_id);
172
173 if (control_fifo_data_2[110]!==fflp_ctrl_pkt.ip_version)
174 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "IP-ver = %0h\t\t%0h\n", control_fifo_data_2[110], fflp_ctrl_pkt.ip_version);
175 printf("CNTL_FIFO_CHKR: IP-ver = %0h\t\t%0h\n", control_fifo_data_2[110], fflp_ctrl_pkt.ip_version);
176
177 if (fflp_ctrl_pkt.tt_succeed) { // If tt_succeed==1, ZCP related info takes these fields
178 //printf("CNTL_FIFO_CHKR: Control fifo checker detected tt_succeed=1 (ZCP-intensive) from the FFLP model packet\n");
179 if (control_fifo_data_1[63:48]!==fflp_ctrl_pkt.tt_hdr_len)
180 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "tt_hdr_len = %0h\t\t%0h\n", control_fifo_data_1[63:48], fflp_ctrl_pkt.tt_hdr_len);
181 else
182 printf("CNTL_FIFO_CHKR: tt_hdr_len = %0h\t\t%0h\n", control_fifo_data_1[63:48], fflp_ctrl_pkt.tt_hdr_len);
183 if (control_fifo_data_1[47:32]!==fflp_ctrl_pkt.tcp_payload_len)
184 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "TCP_Payload_Len = %0h\t\t%0h\n", control_fifo_data_1[47:32], fflp_ctrl_pkt.tcp_payload_len);
185 else
186 printf("CNTL_FIFO_CHKR: TCP_Payload_Len = %0h\t\t%0h\n", control_fifo_data_1[47:32], fflp_ctrl_pkt.tcp_payload_len);
187
188 if (control_fifo_data_1[31:16]!==fflp_ctrl_pkt.HoQ)
189 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "HoQ = %0h\t\t%0h\n", control_fifo_data_1[31:16], fflp_ctrl_pkt.HoQ);
190 else
191 printf("CNTL_FIFO_CHKR: HoQ = %0h\t\t%0h\n", control_fifo_data_1[31:16], fflp_ctrl_pkt.HoQ);
192
193 if ({control_fifo_data_1[15:0],control_fifo_data_2[127:120]}!==fflp_ctrl_pkt.first_byte_offset)
194 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "FirstByteOffset = %0h\t\t%0h\n", {control_fifo_data_1[15:0],control_fifo_data_2[127:120]},
195 fflp_ctrl_pkt.first_byte_offset);
196 else
197 printf("CNTL_FIFO_CHKR: FirstByteOffset = %0h\t\t%0h\n", {control_fifo_data_1[15:0],control_fifo_data_2[127:120]},
198 fflp_ctrl_pkt.first_byte_offset);
199
200 if (control_fifo_data_2[119] !== fflp_ctrl_pkt.reach_buf_end)
201 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "reach_buf_end = %0h\t\t%0h\n", control_fifo_data_2[119], fflp_ctrl_pkt.reach_buf_end);
202 else
203 printf("CNTL_FIFO_CHKR: reach_buf_end = %0h\t\t%0h\n", control_fifo_data_2[119], fflp_ctrl_pkt.reach_buf_end);
204
205 if (control_fifo_data_2[118:117]!==fflp_ctrl_pkt.dmaw_type_1)
206 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "dmaw_type_1 = %0h\t\t%0h\n", control_fifo_data_2[118:117], fflp_ctrl_pkt.dmaw_type_1);
207 else
208 printf("CNTL_FIFO_CHKR: dmaw_type_1 = %0h\t\t%0h\n", control_fifo_data_2[118:117], fflp_ctrl_pkt.dmaw_type_1);
209
210 if (control_fifo_data_2[116:112]!==fflp_ctrl_pkt.win_buf_offset)
211 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "win_buf_offset = %0h\t\t%0h\n", control_fifo_data_2[116:112], fflp_ctrl_pkt.win_buf_offset);
212 else
213 printf("CNTL_FIFO_CHKR: win_buf_offset = %0h\t\t%0h\n", control_fifo_data_2[116:112], fflp_ctrl_pkt.win_buf_offset);
214 }
215 else {
216 //printf("CNTL_FIFO_CHKR: Control fifo checker detected tt_succeed=0 (non-ZCP-intensive) from the FFLP model packet\n");
217 if ({control_fifo_data_1[23:0],control_fifo_data_2[127:112]}!==fflp_ctrl_pkt.user_data)
218 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "Usr_Data[39:0] = %0h\t\t%0h\n", {control_fifo_data_1[23:0],control_fifo_data_2[127:112]},
219 fflp_ctrl_pkt.user_data);
220 else
221 printf("CNTL_FIFO_CHKR: Usr_Data[39:0] = %0h\t\t%0h\n", {control_fifo_data_1[23:0],control_fifo_data_2[127:112]},
222 fflp_ctrl_pkt.user_data);
223
224 if (control_fifo_data_1[43:24]!==fflp_ctrl_pkt.hash_value1)
225 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "Hash_Val1 = %0h\t\t%0h\n", control_fifo_data_1[43:24], fflp_ctrl_pkt.hash_value1);
226 else
227 printf("CNTL_FIFO_CHKR: Hash_Val1 = %0h\t\t%0h\n", control_fifo_data_1[43:24], fflp_ctrl_pkt.hash_value1);
228
229 if (control_fifo_data_1[63:48]!==fflp_ctrl_pkt.hash_value2)
230 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "Hash_Val2 = %0h\t\t%0h\n", control_fifo_data_1[63:48], fflp_ctrl_pkt.hash_value2);
231 else
232 printf("CNTL_FIFO_CHKR: Hash_Val2 = %0h\t\t%0h\n", control_fifo_data_1[63:48], fflp_ctrl_pkt.hash_value2);
233 }
234
235 // First Cycle
236 if (control_fifo_data_1[75:64] !==fflp_ctrl_pkt.zc_flow_id)
237 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "Zflowid = %0h\t\t%0h\n", control_fifo_data_1[75:64], fflp_ctrl_pkt.zc_flow_id);
238 else
239 printf("CNTL_FIFO_CHKR: Zflowid = %0h\t\t%0h\n", control_fifo_data_1[75:64], fflp_ctrl_pkt.zc_flow_id);
240
241 if (control_fifo_data_1[76]!==fflp_ctrl_pkt.solicited_event_bit)
242 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "SE-bit = %0h\t\t%0h\n", control_fifo_data_1[76], fflp_ctrl_pkt.solicited_event_bit);
243 else
244 printf("CNTL_FIFO_CHKR: SE-bit = %0h\t\t%0h\n", control_fifo_data_1[76], fflp_ctrl_pkt.solicited_event_bit);
245
246 if (control_fifo_data_1[77]!==fflp_ctrl_pkt.asdata_disc)
247 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "Drop-pkt = %0h\t\t%0h\n", control_fifo_data_1[77], fflp_ctrl_pkt.asdata_disc);
248 else
249 printf("CNTL_FIFO_CHKR: Drop-pkt = %0h\t\t%0h\n", control_fifo_data_1[77], fflp_ctrl_pkt.asdata_disc);
250
251 if (control_fifo_data_1[78]!==fflp_ctrl_pkt.fflp_hw_err)
252 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "FFLP-hw-err = %0h\t\t%0h\n", control_fifo_data_1[78], fflp_ctrl_pkt.fflp_hw_err);
253 else
254 printf("CNTL_FIFO_CHKR: FFLP-hw-err = %0h\t\t%0h\n", control_fifo_data_1[78], fflp_ctrl_pkt.fflp_hw_err);
255
256 if (control_fifo_data_1[79]!==fflp_ctrl_pkt.mac_promiscuous)
257 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "MAC-promiscuous = %0h\t\t%0h\n", control_fifo_data_1[79], fflp_ctrl_pkt.mac_promiscuous);
258 else
259 printf("CNTL_FIFO_CHKR: MAC-promiscuous = %0h\t\t%0h\n", control_fifo_data_1[79], fflp_ctrl_pkt.mac_promiscuous);
260
261 if (control_fifo_data_1[86]!==fflp_ctrl_pkt.tt_err)
262 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "tt-err = %0h\t\t%0h\n", control_fifo_data_1[86], fflp_ctrl_pkt.tt_err);
263 else
264 printf("CNTL_FIFO_CHKR: tt-err = %0h\t\t%0h\n", control_fifo_data_1[86], fflp_ctrl_pkt.tt_err);
265
266 if (control_fifo_data_1[87]!==fflp_ctrl_pkt.tt_succeed)
267 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "tt-succeed = %0h\t\t%0h\n", control_fifo_data_1[87], fflp_ctrl_pkt.tt_succeed);
268 else
269 printf("CNTL_FIFO_CHKR: tt-succeed = %0h\t\t%0h\n", control_fifo_data_1[87], fflp_ctrl_pkt.tt_succeed);
270
271 if (control_fifo_data_1[90:88]!==fflp_ctrl_pkt.hash_index)
272 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "Hash-sub-index = %0h\t\t%0h\n", control_fifo_data_1[90:88], fflp_ctrl_pkt.hash_index);
273 else
274 printf("CNTL_FIFO_CHKR: Hash-sub-index = %0h\t\t%0h\n", control_fifo_data_1[90:88], fflp_ctrl_pkt.hash_index);
275
276 if (control_fifo_data_1[91]!==fflp_ctrl_pkt.hzfvld)
277 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "HZFVLD = %0h\t\t%0h\n", control_fifo_data_1[91], fflp_ctrl_pkt.hzfvld);
278 else
279 printf("CNTL_FIFO_CHKR: HZFVLD = %0h\t\t%0h\n", control_fifo_data_1[91], fflp_ctrl_pkt.hzfvld);
280
281 if (control_fifo_data_1[92]!==fflp_ctrl_pkt.hash_exact_match)
282 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "Exact = %0h\t\t%0h\n", control_fifo_data_1[92], fflp_ctrl_pkt.hash_exact_match);
283 else
284 printf("CNTL_FIFO_CHKR: Exact = %0h\t\t%0h\n", control_fifo_data_1[92], fflp_ctrl_pkt.hash_exact_match);
285
286 if (control_fifo_data_1[93]!==fflp_ctrl_pkt.hash_hit)
287 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "Hash-hit = %0h\t\t%0h\n", control_fifo_data_1[93], fflp_ctrl_pkt.hash_hit);
288 else
289 printf("CNTL_FIFO_CHKR: Hash-hit = %0h\t\t%0h\n", control_fifo_data_1[93], fflp_ctrl_pkt.hash_hit);
290
291 if (control_fifo_data_1[103:96]!==fflp_ctrl_pkt.tcamm_index)
292 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "TCAM-M-index = %0h\t\t%0h\n", control_fifo_data_1[103:96], fflp_ctrl_pkt.tcamm_index);
293 else
294 printf("CNTL_FIFO_CHKR: TCAM-M-index = %0h\t\t%0h\n", control_fifo_data_1[103:96], fflp_ctrl_pkt.tcamm_index);
295
296 if ({control_fifo_data_1[106:104],control_fifo_data_1[95:94]}!==fflp_ctrl_pkt.default_dma_num)
297 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "Table-RDC = %0h\t\t%0h\n", {control_fifo_data_1[106:104],control_fifo_data_1[95:94]},
298 fflp_ctrl_pkt.default_dma_num);
299 else
300 printf("CNTL_FIFO_CHKR: Table-RDC = %0h\t\t%0h\n", {control_fifo_data_1[106:104],control_fifo_data_1[95:94]},
301 fflp_ctrl_pkt.default_dma_num);
302
303 if (control_fifo_data_1[111:107]!==fflp_ctrl_pkt.dma_num)
304 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "Default-RDC = %0h\t\t%0h\n", control_fifo_data_1[111:107], fflp_ctrl_pkt.dma_num);
305 else
306 printf("CNTL_FIFO_CHKR: Default-RDC = %0h\t\t%0h\n", control_fifo_data_1[111:107], fflp_ctrl_pkt.dma_num);
307 } // skipping above if asked to check only 2 bytes
308
309 if (control_fifo_data_1[112]!==fflp_ctrl_pkt.tzfvld)
310 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "TZFVLD = %0h\t\t%0h\n", control_fifo_data_1[112], fflp_ctrl_pkt.tzfvld);
311 else
312 printf("CNTL_FIFO_CHKR: TZFVLD = %0h\t\t%0h\n", control_fifo_data_1[112], fflp_ctrl_pkt.tzfvld);
313 if (control_fifo_data_1[114:113]!==fflp_ctrl_pkt.tres)
314 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "TRES = %0h\t\t%0h\n", control_fifo_data_1[114:113], fflp_ctrl_pkt.tres);
315 else
316 printf("CNTL_FIFO_CHKR: TRES = %0h\t\t%0h\n", control_fifo_data_1[114:113], fflp_ctrl_pkt.tres);
317 if (control_fifo_data_1[115]!==fflp_ctrl_pkt.tcamhit)
318 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "TCAM-Hit = %0h\t\t%0h\n", control_fifo_data_1[115], fflp_ctrl_pkt.tcamhit);
319 else
320 printf("CNTL_FIFO_CHKR: TCAM-Hit = %0h\t\t%0h\n", control_fifo_data_1[115], fflp_ctrl_pkt.tcamhit);
321 if (control_fifo_data_1[116]!==fflp_ctrl_pkt.badip)
322 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "Bad-IP = %0h\t\t%0h\n", control_fifo_data_1[116], fflp_ctrl_pkt.badip);
323 else
324 printf("CNTL_FIFO_CHKR: Bad-IP = %0h\t\t%0h\n", control_fifo_data_1[116], fflp_ctrl_pkt.badip);
325 if (control_fifo_data_1[117]!==fflp_ctrl_pkt.noport)
326 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "No-port = %0h\t\t%0h\n", control_fifo_data_1[117], fflp_ctrl_pkt.noport);
327 else
328 printf("CNTL_FIFO_CHKR: No-port = %0h\t\t%0h\n", control_fifo_data_1[117], fflp_ctrl_pkt.noport);
329 if (control_fifo_data_1[118]!==fflp_ctrl_pkt.llcsnap)
330 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "LLC-SNAP = %0h\t\t%0h\n", control_fifo_data_1[118], fflp_ctrl_pkt.llcsnap);
331 else
332 printf("CNTL_FIFO_CHKR: LLC-SNAP = %0h\t\t%0h\n", control_fifo_data_1[118], fflp_ctrl_pkt.llcsnap);
333 if (control_fifo_data_1[119]!==fflp_ctrl_pkt.vlan)
334 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "VLAN = %0h\t\t%0h\n", control_fifo_data_1[119], fflp_ctrl_pkt.vlan);
335 else
336 printf("CNTL_FIFO_CHKR: VLAN = %0h\t\t%0h\n", control_fifo_data_1[119], fflp_ctrl_pkt.vlan);
337 if (control_fifo_data_1[124:120]!==fflp_ctrl_pkt.packet_class)
338 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "CLASS = %0h\t\t%0h\n", control_fifo_data_1[124:120], fflp_ctrl_pkt.packet_class);
339 else
340 printf("CNTL_FIFO_CHKR: CLASS = %0h\t\t%0h\n", control_fifo_data_1[124:120], fflp_ctrl_pkt.packet_class);
341 if (control_fifo_data_1[125]!==fflp_ctrl_pkt.maccheck)
342 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "MAC-check = %0h\t\t%0h\n", control_fifo_data_1[125], fflp_ctrl_pkt.maccheck);
343 else
344 printf("CNTL_FIFO_CHKR: MAC-check = %0h\t\t%0h\n", control_fifo_data_1[125], fflp_ctrl_pkt.maccheck);
345 if (control_fifo_data_1[127:126]!==fflp_ctrl_pkt.mac_prt)
346 be_msg_cntl_fifo.print(e_mesg_error,"CNTL_FIFO_CHKR", "", "MAC-PORT = %0h\t\t%0h\n", control_fifo_data_1[127:126], fflp_ctrl_pkt.mac_prt);
347 else
348 printf("CNTL_FIFO_CHKR: MAC-PORT = %0h\t\t%0h\n", control_fifo_data_1[127:126], fflp_ctrl_pkt.mac_prt);
349 printf("CNTL_FIFO_CHKR: ---------------------------------------------------\n");
350 num_of_cycle = 0;
351 rtl_pkt_id ++;
352 }
353 }
354
355
356 } // end of while
357
358} // end of task check_cntl_port
Full OpenSPARC design & verification tarball including full HDL.