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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: serdes_wrapper.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module serdes_wrapper ( | |
36 | BSINITCLK, | |
37 | CFGPLL, | |
38 | CFGRX0, | |
39 | CFGRX1, | |
40 | CFGRX2, | |
41 | CFGRX3, | |
42 | CFGTX0, | |
43 | CFGTX1, | |
44 | CFGTX2, | |
45 | CFGTX3, | |
46 | FCLK, | |
47 | FCLRZ, | |
48 | FDI, | |
49 | REFCLKN, | |
50 | REFCLKP, | |
51 | RXBCLKIN, | |
52 | RXN0, | |
53 | RXN1, | |
54 | RXN2, | |
55 | RXN3, | |
56 | RXP0, | |
57 | RXP1, | |
58 | RXP2, | |
59 | RXP3, | |
60 | STCICFG, | |
61 | STCICLK, | |
62 | STCID, | |
63 | TD0, | |
64 | TD1, | |
65 | TD2, | |
66 | TD3, | |
67 | TESTCFG, | |
68 | TESTCLKR, | |
69 | TESTCLKT, | |
70 | TXBCLKIN, | |
71 | AMUX, | |
72 | FDO, | |
73 | RD0, | |
74 | RD1, | |
75 | RD2, | |
76 | RD3, | |
77 | RDLL0, | |
78 | RDLL1, | |
79 | RDLL2, | |
80 | RDLL3, | |
81 | RXBCLK, | |
82 | RXBCLKLLN, | |
83 | RXBCLKLLP, | |
84 | STCIQ, | |
85 | STSPLL, | |
86 | STSRX0, | |
87 | STSRX1, | |
88 | STSRX2, | |
89 | STSRX3, | |
90 | STSTX0, | |
91 | STSTX1, | |
92 | STSTX2, | |
93 | STSTX3, | |
94 | TXBCLK, | |
95 | TXN0, | |
96 | TXN1, | |
97 | TXN2, | |
98 | TXN3, | |
99 | TXP0, | |
100 | TXP1, | |
101 | TXP2, | |
102 | TXP3 | |
103 | ); | |
104 | ||
105 | input BSINITCLK; | |
106 | input [11:0] CFGPLL; | |
107 | input [27:0] CFGRX0; | |
108 | input [27:0] CFGRX1; | |
109 | input [27:0] CFGRX2; | |
110 | input [27:0] CFGRX3; | |
111 | input [19:0] CFGTX0; | |
112 | input [19:0] CFGTX1; | |
113 | input [19:0] CFGTX2; | |
114 | input [19:0] CFGTX3; | |
115 | input FCLK; | |
116 | input FCLRZ; | |
117 | input FDI; | |
118 | input REFCLKN; | |
119 | input REFCLKP; | |
120 | input [3:0] RXBCLKIN; | |
121 | input RXN0; | |
122 | input RXN1; | |
123 | input RXN2; | |
124 | input RXN3; | |
125 | input RXP0; | |
126 | input RXP1; | |
127 | input RXP2; | |
128 | input RXP3; | |
129 | input [1:0] STCICFG; | |
130 | input STCICLK; | |
131 | input STCID; | |
132 | input [9:0] TD0; | |
133 | input [9:0] TD1; | |
134 | input [9:0] TD2; | |
135 | input [9:0] TD3; | |
136 | input [19:0] TESTCFG; | |
137 | input TESTCLKR; | |
138 | input TESTCLKT; | |
139 | input [3:0] TXBCLKIN; | |
140 | output AMUX; | |
141 | output FDO; | |
142 | output [9:0] RD0; | |
143 | output [9:0] RD1; | |
144 | output [9:0] RD2; | |
145 | output [9:0] RD3; | |
146 | output [1:0] RDLL0; | |
147 | output [1:0] RDLL1; | |
148 | output [1:0] RDLL2; | |
149 | output [1:0] RDLL3; | |
150 | output [3:0] RXBCLK; | |
151 | output [3:0] RXBCLKLLN; | |
152 | output [3:0] RXBCLKLLP; | |
153 | output STCIQ; | |
154 | output [3:0] STSPLL; | |
155 | output [7:0] STSRX0; | |
156 | output [7:0] STSRX1; | |
157 | output [7:0] STSRX2; | |
158 | output [7:0] STSRX3; | |
159 | output [3:0] STSTX0; | |
160 | output [3:0] STSTX1; | |
161 | output [3:0] STSTX2; | |
162 | output [3:0] STSTX3; | |
163 | output [3:0] TXBCLK; | |
164 | output TXN0; | |
165 | output TXN1; | |
166 | output TXN2; | |
167 | output TXN3; | |
168 | output TXP0; | |
169 | output TXP1; | |
170 | output TXP2; | |
171 | output TXP3; | |
172 | wire xaui_clk; | |
173 | clock_multiplier_10x clock_multiplier_10x (tb_top.cpu.XAUI0_REFCLK_P, xaui_clk); | |
174 | xaui_port xaui0 ( | |
175 | .XAUI_RX_N ({RXN3,RXN2,RXN1,RXN0}), | |
176 | .XAUI_RX_P ({RXP3,RXP2,RXP1,RXP0}), | |
177 | .XAUI_AMUX (AMUX), | |
178 | .XAUI_TX_N ({TXN3,TXN2,TXN1,TXN0}), | |
179 | .XAUI_TX_P ({TXP3,TXP2,TXP1,TXP0}), | |
180 | .esr_mac_rxd0 (RD0), | |
181 | .esr_mac_rxd1 (RD1), | |
182 | .esr_mac_rxd2 (RD2), | |
183 | .esr_mac_rxd3 (RD3), | |
184 | .mac_esr_txd0 (TD0), | |
185 | .mac_esr_txd1 (TD1), | |
186 | .mac_esr_txd2 (TD2), | |
187 | .mac_esr_txd3 (TD3), | |
188 | .xaui_clk (xaui_clk), | |
189 | .mac_clk (tb_top.cpu.XAUI0_REFCLK_P), | |
190 | .reset (~tb_top.cpu.n2_clk_gl_cust.gl_rst_mac_c1b) ); | |
191 | ||
192 | endmodule |