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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: cpu.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module cpu ( | |
36 | L2T_VNW, | |
37 | SPC_VNW, | |
38 | L2D_VNW0, | |
39 | L2D_VNW1, | |
40 | FBDIMM0A_TX_P, | |
41 | FBDIMM0A_TX_N, | |
42 | FBDIMM0A_RX_P, | |
43 | FBDIMM0A_RX_N, | |
44 | FBDIMM0A_AMUX, | |
45 | FBDIMM0B_TX_P, | |
46 | FBDIMM0B_TX_N, | |
47 | FBDIMM0B_RX_P, | |
48 | FBDIMM0B_RX_N, | |
49 | FBDIMM0B_AMUX, | |
50 | FBDIMM1A_TX_P, | |
51 | FBDIMM1A_TX_N, | |
52 | FBDIMM1A_RX_P, | |
53 | FBDIMM1A_RX_N, | |
54 | FBDIMM1A_AMUX, | |
55 | FBDIMM1B_TX_P, | |
56 | FBDIMM1B_TX_N, | |
57 | FBDIMM1B_RX_P, | |
58 | FBDIMM1B_RX_N, | |
59 | FBDIMM1B_AMUX, | |
60 | FBDIMM2A_TX_P, | |
61 | FBDIMM2A_TX_N, | |
62 | FBDIMM2A_RX_P, | |
63 | FBDIMM2A_RX_N, | |
64 | FBDIMM2A_AMUX, | |
65 | FBDIMM2B_TX_P, | |
66 | FBDIMM2B_TX_N, | |
67 | FBDIMM2B_RX_P, | |
68 | FBDIMM2B_RX_N, | |
69 | FBDIMM2B_AMUX, | |
70 | FBDIMM3A_TX_P, | |
71 | FBDIMM3A_TX_N, | |
72 | FBDIMM3A_RX_P, | |
73 | FBDIMM3A_RX_N, | |
74 | FBDIMM3A_AMUX, | |
75 | FBDIMM3B_TX_P, | |
76 | FBDIMM3B_TX_N, | |
77 | FBDIMM3B_RX_P, | |
78 | FBDIMM3B_RX_N, | |
79 | FBDIMM3B_AMUX, | |
80 | FBDIMM1_REFCLK_P, | |
81 | FBDIMM1_REFCLK_N, | |
82 | FBDIMM2_REFCLK_P, | |
83 | FBDIMM2_REFCLK_N, | |
84 | FBDIMM3_REFCLK_P, | |
85 | FBDIMM3_REFCLK_N, | |
86 | VDDA_FSRL, | |
87 | VDDD_FSRL, | |
88 | VDDR_FSRL, | |
89 | VDDT_FSRL, | |
90 | VSSA_FSRL, | |
91 | VDDA_FSRR, | |
92 | VDDD_FSRR, | |
93 | VDDR_FSRR, | |
94 | VDDT_FSRR, | |
95 | VSSA_FSRR, | |
96 | VDDA_FSRB, | |
97 | VDDD_FSRB, | |
98 | VDDR_FSRB, | |
99 | VDDT_FSRB, | |
100 | VSSA_FSRB, | |
101 | PEX_TX_P, | |
102 | PEX_TX_N, | |
103 | PEX_RX_P, | |
104 | PEX_RX_N, | |
105 | PEX_REFCLK_P, | |
106 | PEX_REFCLK_N, | |
107 | PEX_AMUX, | |
108 | VDDT_PSR, | |
109 | VDDD_PSR, | |
110 | VDDC_PSR, | |
111 | VDDA_PSR, | |
112 | VDDR_PSR, | |
113 | VSSA_PSR, | |
114 | STCIQ, | |
115 | TESTCLKT, | |
116 | TESTCLKR, | |
117 | STCID, | |
118 | PLL_CMP_BYPASS, | |
119 | STCICFG, | |
120 | STCICLK, | |
121 | PGRM_EN, | |
122 | VDDO_PCM, | |
123 | `ifndef FC_NO_NIU_T2 | |
124 | XAUI0_AMUX, | |
125 | XAUI0_TX_N, | |
126 | XAUI0_TX_P, | |
127 | XAUI0_REFCLK_N, | |
128 | XAUI0_REFCLK_P, | |
129 | XAUI0_RX_N, | |
130 | XAUI0_RX_P, | |
131 | XAUI1_AMUX, | |
132 | XAUI1_TX_N, | |
133 | XAUI1_TX_P, | |
134 | XAUI1_RX_N, | |
135 | XAUI1_RX_P, | |
136 | XAUI0_LINK_LED, | |
137 | XAUI1_LINK_LED, | |
138 | XAUI0_ACT_LED, | |
139 | XAUI1_ACT_LED, | |
140 | XAUI_MDC, | |
141 | XAUI_MDIO, | |
142 | XAUI_MDINT1_L, | |
143 | XAUI_MDINT0_L, | |
144 | VDDT_ESR, | |
145 | VDDA_ESR, | |
146 | VDDD_ESR, | |
147 | VDDR_ESR, | |
148 | VSSA_ESR, | |
149 | `endif | |
150 | PLL_CMP_CLK_P, | |
151 | PLL_CMP_CLK_N, | |
152 | DIODE_TOP, | |
153 | DIODE_BOT, | |
154 | VDD_PLL_CMP_REG, | |
155 | VDD_RNG_HV, | |
156 | VDD_SENSE, | |
157 | VSS_SENSE, | |
158 | RNG_ANLG_CHAR_OUT, | |
159 | PWRON_RST_L, | |
160 | BUTTON_XIR_L, | |
161 | PB_RST_L, | |
162 | PEX_RESET_L, | |
163 | SSI_SYNC_L, | |
164 | VPP, | |
165 | TMS, | |
166 | TDI, | |
167 | TRST_L, | |
168 | TCK, | |
169 | TESTMODE, | |
170 | TDO, | |
171 | DIVIDER_BYPASS, | |
172 | DBG_DQ, | |
173 | DBG_CK0, | |
174 | TRIGIN, | |
175 | TRIGOUT, | |
176 | SSI_MISO, | |
177 | SSI_EXT_INT_L, | |
178 | SSI_SCK, | |
179 | SSI_MOSI, | |
180 | PMI, | |
181 | VREG_SELBG_L, | |
182 | PLL_CHAR_OUT, | |
183 | PLL_TESTMODE, | |
184 | PWR_THRTTL_0, | |
185 | PWR_THRTTL_1, | |
186 | PMO, | |
187 | BURNIN); | |
188 | wire arb_pio_all_npwdirty; | |
189 | wire arb_pio_all_rddirty; | |
190 | wire [5:0] arb_pio_dirtid_npwstatus; | |
191 | wire [5:0] arb_pio_dirtid_rdstatus; | |
192 | wire cluster_arst_l; | |
193 | wire cmp_gclk_c0_rdp; | |
194 | wire efu_niu_ram0_clr; | |
195 | wire efu_niu_ram0_xfer_en; | |
196 | wire efu_niu_ram1_clr; | |
197 | wire efu_niu_ram1_xfer_en; | |
198 | wire efu_niu_ram_data; | |
199 | wire [31:0] fflp_debug_port; | |
200 | wire fflp_pio_ack; | |
201 | wire fflp_pio_err; | |
202 | wire fflp_pio_intr; | |
203 | wire [63:0] fflp_pio_rdata; | |
204 | wire gl_io2x_out_c1b; | |
205 | wire gl_io_out_c1b; | |
206 | wire [31:0] ipp_debug_port; | |
207 | wire ipp_dmc_dat_ack0; | |
208 | wire ipp_dmc_dat_ack1; | |
209 | wire ipp_dmc_dat_err0; | |
210 | wire ipp_dmc_dat_err1; | |
211 | wire [129:0] ipp_dmc_data0; | |
212 | wire [129:0] ipp_dmc_data1; | |
213 | wire ipp_dmc_ful_pkt0; | |
214 | wire ipp_dmc_ful_pkt1; | |
215 | wire ipp_pio_ack; | |
216 | wire ipp_pio_err; | |
217 | wire ipp_pio_intr; | |
218 | wire [63:0] ipp_pio_rdata; | |
219 | wire [31:0] mac_debug_port; | |
220 | wire mac_pio_ack; | |
221 | wire mac_pio_err; | |
222 | wire mac_pio_intr0; | |
223 | wire mac_pio_intr1; | |
224 | wire [63:0] mac_pio_rdata; | |
225 | wire meta_dmc_ack_client_rdmc; | |
226 | wire [7:0] meta_dmc_ack_cmd; | |
227 | wire [3:0] meta_dmc_ack_cmd_status; | |
228 | wire [4:0] meta_dmc_ack_dma_num; | |
229 | wire meta_dmc_ack_ready; | |
230 | wire arb0_rcr_data_req; | |
231 | wire arb0_rcr_req_accept; | |
232 | wire arb0_rdc_data_req; | |
233 | wire arb0_rdc_req_accept; | |
234 | wire arb1_rbr_req_accept; | |
235 | wire arb1_rbr_req_errors; | |
236 | wire [15:0] meta1_rdmc_rbr_resp_byteenable; | |
237 | wire meta_dmc_resp_client_rdmc; | |
238 | wire [7:0] meta1_rdmc_rbr_resp_cmd; | |
239 | wire [3:0] meta1_rdmc_rbr_resp_cmd_status; | |
240 | wire meta_dmc_resp_complete_rdmc; | |
241 | wire [127:0] meta1_rdmc_rbr_resp_data; | |
242 | wire [3:0] meta_dmc_data_status; | |
243 | wire meta_dmc_data_valid_rdmc; | |
244 | wire [4:0] meta1_rdmc_rbr_resp_dma_num; | |
245 | wire meta1_rdmc_rbr_resp_ready; | |
246 | wire meta_dmc_resp_transfer_cmpl_rdmc; | |
247 | wire [31:0] meta_arb_debug_port; | |
248 | wire mif_pio_intr; | |
249 | wire [31:0] ncu_niu_data; | |
250 | wire ncu_niu_stall; | |
251 | wire ncu_niu_vld; | |
252 | wire rdp_rdmc_mbist_scan_in; | |
253 | wire gl_rst_niu_wmr_c1b; | |
254 | wire [31:0] smx_debug_port; | |
255 | wire smx_pio_intr; | |
256 | wire [31:0] smx_pio_status; | |
257 | wire tcu_asic_aclk; | |
258 | wire tcu_asic_bclk; | |
259 | wire tcu_div_bypass; | |
260 | wire tcu_mbist_bisi_en; | |
261 | wire tcu_mbist_user_mode; | |
262 | wire tcu_pce_ov; | |
263 | wire tcu_rdp_rdmc_mbist_start; | |
264 | wire tcu_asic_scan_en; | |
265 | wire tcu_asic_se_scancollar_in; | |
266 | wire tcu_asic_se_scancollar_out; | |
267 | wire [31:0] tdmc_debug_port; | |
268 | wire tdmc_pio_ack; | |
269 | wire tdmc_pio_err; | |
270 | wire [63:0] tdmc_pio_rdata; | |
271 | wire [31:0] txc_debug_port; | |
272 | wire txc_pio_ack; | |
273 | wire txc_pio_err; | |
274 | wire niu_txc_interrupts; | |
275 | wire [63:0] txc_pio_rdata; | |
276 | wire [31:0] zcp_debug_port; | |
277 | wire zcp_dmc_ack0; | |
278 | wire zcp_dmc_ack1; | |
279 | wire [129:0] zcp_dmc_dat0; | |
280 | wire [129:0] zcp_dmc_dat1; | |
281 | wire zcp_dmc_dat_err0; | |
282 | wire zcp_dmc_dat_err1; | |
283 | wire zcp_dmc_ful_pkt0; | |
284 | wire zcp_dmc_ful_pkt1; | |
285 | wire zcp_pio_ack; | |
286 | wire zcp_pio_err; | |
287 | wire zcp_pio_intr; | |
288 | wire [63:0] zcp_pio_rdata; | |
289 | wire dmc_ipp_dat_req0; | |
290 | wire dmc_ipp_dat_req1; | |
291 | wire dmc_zcp_req0; | |
292 | wire dmc_zcp_req1; | |
293 | wire mac_reset0; | |
294 | wire mac_reset1; | |
295 | wire niu_efu_ram0_xfer_en; | |
296 | wire niu_efu_ram1_xfer_en; | |
297 | wire [31:0] niu_ncu_data; | |
298 | wire niu_ncu_stall; | |
299 | wire niu_ncu_vld; | |
300 | wire [31:0] pio_arb_ctrl; | |
301 | wire [31:0] pio_arb_debug_vector; | |
302 | wire pio_arb_dirtid_clr; | |
303 | wire pio_arb_dirtid_enable; | |
304 | wire [5:0] pio_arb_np_threshold; | |
305 | wire [5:0] pio_arb_rd_threshold; | |
306 | wire pio_fflp_sel; | |
307 | wire pio_ipp_sel; | |
308 | wire pio_mac_sel; | |
309 | wire [31:0] pio_smx_cfg_data; | |
310 | wire pio_smx_clear_intr; | |
311 | wire [31:0] pio_smx_ctrl; | |
312 | wire [31:0] pio_smx_debug_vector; | |
313 | wire pio_tdmc_sel; | |
314 | wire pio_txc_sel; | |
315 | wire pio_zcp_sel; | |
316 | wire rdmc_meta_ack_accept; | |
317 | wire [127:0] rcr_arb0_data; | |
318 | wire rcr_arb0_data_valid; | |
319 | wire rcr_arb0_req; | |
320 | wire [63:0] rcr_arb0_req_address; | |
321 | wire [15:0] rcr_arb0_req_byteenable; | |
322 | wire [7:0] rcr_arb0_req_cmd; | |
323 | wire [4:0] rcr_arb0_req_dma_num; | |
324 | wire [1:0] rcr_arb0_req_func_num; | |
325 | wire [13:0] rcr_arb0_req_length; | |
326 | wire [1:0] rcr_arb0_req_port_num; | |
327 | wire [3:0] rcr_arb0_status; | |
328 | wire rcr_arb0_transfer_complete; | |
329 | wire [127:0] rdc_arb0_data; | |
330 | wire rdc_arb0_data_valid; | |
331 | wire rdc_arb0_req; | |
332 | wire [63:0] rdc_arb0_req_address; | |
333 | wire [15:0] rdc_arb0_req_byteenable; | |
334 | wire [7:0] rdc_arb0_req_cmd; | |
335 | wire [4:0] rdc_arb0_req_dma_num; | |
336 | wire [1:0] rdc_arb0_req_func_num; | |
337 | wire [13:0] rdc_arb0_req_length; | |
338 | wire [1:0] rdc_arb0_req_port_num; | |
339 | wire [3:0] rdc_arb0_status; | |
340 | wire rdc_arb0_transfer_complete; | |
341 | wire rbr_arb1_req; | |
342 | wire [63:0] rbr_arb1_req_address; | |
343 | wire [7:0] rbr_arb1_req_cmd; | |
344 | wire [4:0] rbr_arb1_req_dma_num; | |
345 | wire [1:0] rbr_arb1_req_func_num; | |
346 | wire [13:0] rbr_arb1_req_length; | |
347 | wire [1:0] rbr_arb1_req_port_num; | |
348 | wire rdmc_meta_resp_accept; | |
349 | wire rdp_rdmc_mbist_scan_out; | |
350 | wire rdp_rdmc_tcu_mbist_done; | |
351 | wire rdp_rdmc_tcu_mbist_fail; | |
352 | wire [39:0] rdp_tcu_dmo_dout; | |
353 | wire tcu_asic_array_wr_inhibit; | |
354 | wire tcu_soce_scan_out; | |
355 | wire rdp_scan_out; | |
356 | wire [63:0] pio_clients_wdata; | |
357 | wire [19:0] pio_clients_addr; | |
358 | wire pio_clients_rd; | |
359 | wire [4:0] dbg1_niu_dbg_sel; | |
360 | wire [1:0] niu_mio_debug_clock; | |
361 | wire [31:0] niu_mio_debug_data; | |
362 | wire niu_efu_ram0_data; | |
363 | wire niu_efu_ram1_data; | |
364 | wire gl_rdp_io_clk_stop; | |
365 | wire [63:0] tdmc_pio_intr; | |
366 | wire cmp_gclk_c0_tds; | |
367 | wire dbg1_niu_resume; | |
368 | wire dbg1_niu_stall; | |
369 | wire efu_niu_ram_clr; | |
370 | wire efu_niu_ram_xfer_en; | |
371 | wire ncu_niu_ctag_cei; | |
372 | wire ncu_niu_ctag_uei; | |
373 | wire ncu_niu_d_pei; | |
374 | wire tcu_soc4_scan_out; | |
375 | wire sii_niu_bqdq; | |
376 | wire sii_niu_oqdq; | |
377 | wire [127:0] sio_niu_data; | |
378 | wire sio_niu_datareq; | |
379 | wire sio_niu_hdr_vld; | |
380 | wire [7:0] sio_niu_parity; | |
381 | wire gl_tds_io_clk_stop; | |
382 | wire tcu_tds_smx_mbist_start; | |
383 | wire tcu_tds_tdmc_mbist_start; | |
384 | wire tds_mbist_scan_in; | |
385 | wire txc_arb1_req; | |
386 | wire [63:0] txc_arb1_req_address; | |
387 | wire [7:0] txc_arb1_req_cmd; | |
388 | wire [4:0] txc_arb1_req_dma_num; | |
389 | wire [1:0] txc_arb1_req_func_num; | |
390 | wire [13:0] txc_arb1_req_length; | |
391 | wire [1:0] txc_arb1_req_port_num; | |
392 | wire txc_dmc_dma0_getnxtdesc; | |
393 | wire txc_dmc_dma0_inc_head; | |
394 | wire txc_dmc_dma0_inc_pkt_cnt; | |
395 | wire txc_dmc_dma0_mark_bit; | |
396 | wire txc_dmc_dma0_reset_done; | |
397 | wire txc_dmc_dma10_getnxtdesc; | |
398 | wire txc_dmc_dma10_inc_head; | |
399 | wire txc_dmc_dma10_inc_pkt_cnt; | |
400 | wire txc_dmc_dma10_mark_bit; | |
401 | wire txc_dmc_dma10_reset_done; | |
402 | wire txc_dmc_dma11_getnxtdesc; | |
403 | wire txc_dmc_dma11_inc_head; | |
404 | wire txc_dmc_dma11_inc_pkt_cnt; | |
405 | wire txc_dmc_dma11_mark_bit; | |
406 | wire txc_dmc_dma11_reset_done; | |
407 | wire txc_dmc_dma12_getnxtdesc; | |
408 | wire txc_dmc_dma12_inc_head; | |
409 | wire txc_dmc_dma12_inc_pkt_cnt; | |
410 | wire txc_dmc_dma12_mark_bit; | |
411 | wire txc_dmc_dma12_reset_done; | |
412 | wire txc_dmc_dma13_getnxtdesc; | |
413 | wire txc_dmc_dma13_inc_head; | |
414 | wire txc_dmc_dma13_inc_pkt_cnt; | |
415 | wire txc_dmc_dma13_mark_bit; | |
416 | wire txc_dmc_dma13_reset_done; | |
417 | wire txc_dmc_dma14_getnxtdesc; | |
418 | wire txc_dmc_dma14_inc_head; | |
419 | wire txc_dmc_dma14_inc_pkt_cnt; | |
420 | wire txc_dmc_dma14_mark_bit; | |
421 | wire txc_dmc_dma14_reset_done; | |
422 | wire txc_dmc_dma15_getnxtdesc; | |
423 | wire txc_dmc_dma15_inc_head; | |
424 | wire txc_dmc_dma15_inc_pkt_cnt; | |
425 | wire txc_dmc_dma15_mark_bit; | |
426 | wire txc_dmc_dma15_reset_done; | |
427 | wire txc_dmc_dma1_getnxtdesc; | |
428 | wire txc_dmc_dma1_inc_head; | |
429 | wire txc_dmc_dma1_inc_pkt_cnt; | |
430 | wire txc_dmc_dma1_mark_bit; | |
431 | wire txc_dmc_dma1_reset_done; | |
432 | wire txc_dmc_dma2_getnxtdesc; | |
433 | wire txc_dmc_dma2_inc_head; | |
434 | wire txc_dmc_dma2_inc_pkt_cnt; | |
435 | wire txc_dmc_dma2_mark_bit; | |
436 | wire txc_dmc_dma2_reset_done; | |
437 | wire txc_dmc_dma3_getnxtdesc; | |
438 | wire txc_dmc_dma3_inc_head; | |
439 | wire txc_dmc_dma3_inc_pkt_cnt; | |
440 | wire txc_dmc_dma3_mark_bit; | |
441 | wire txc_dmc_dma3_reset_done; | |
442 | wire txc_dmc_dma4_getnxtdesc; | |
443 | wire txc_dmc_dma4_inc_head; | |
444 | wire txc_dmc_dma4_inc_pkt_cnt; | |
445 | wire txc_dmc_dma4_mark_bit; | |
446 | wire txc_dmc_dma4_reset_done; | |
447 | wire txc_dmc_dma5_getnxtdesc; | |
448 | wire txc_dmc_dma5_inc_head; | |
449 | wire txc_dmc_dma5_inc_pkt_cnt; | |
450 | wire txc_dmc_dma5_mark_bit; | |
451 | wire txc_dmc_dma5_reset_done; | |
452 | wire txc_dmc_dma6_getnxtdesc; | |
453 | wire txc_dmc_dma6_inc_head; | |
454 | wire txc_dmc_dma6_inc_pkt_cnt; | |
455 | wire txc_dmc_dma6_mark_bit; | |
456 | wire txc_dmc_dma6_reset_done; | |
457 | wire txc_dmc_dma7_getnxtdesc; | |
458 | wire txc_dmc_dma7_inc_head; | |
459 | wire txc_dmc_dma7_inc_pkt_cnt; | |
460 | wire txc_dmc_dma7_mark_bit; | |
461 | wire txc_dmc_dma7_reset_done; | |
462 | wire txc_dmc_dma8_getnxtdesc; | |
463 | wire txc_dmc_dma8_inc_head; | |
464 | wire txc_dmc_dma8_inc_pkt_cnt; | |
465 | wire txc_dmc_dma8_mark_bit; | |
466 | wire txc_dmc_dma8_reset_done; | |
467 | wire txc_dmc_dma9_getnxtdesc; | |
468 | wire txc_dmc_dma9_inc_head; | |
469 | wire txc_dmc_dma9_inc_pkt_cnt; | |
470 | wire txc_dmc_dma9_mark_bit; | |
471 | wire txc_dmc_dma9_reset_done; | |
472 | wire [15:0] txc_dmc_dma_nack_pkt_rd; | |
473 | wire txc_dmc_nack_pkt_rd; | |
474 | wire [43:0] txc_dmc_nack_pkt_rd_addr; | |
475 | wire [15:0] txc_dmc_p0_dma_pkt_size_err; | |
476 | wire txc_dmc_p0_pkt_size_err; | |
477 | wire [43:0] txc_dmc_p0_pkt_size_err_addr; | |
478 | wire [15:0] txc_dmc_p1_dma_pkt_size_err; | |
479 | wire txc_dmc_p1_pkt_size_err; | |
480 | wire [43:0] txc_dmc_p1_pkt_size_err_addr; | |
481 | wire txc_meta_resp_accept; | |
482 | wire arb1_txc_req_accept; | |
483 | wire [5:0] dmc_meta1_req_trans_id; | |
484 | wire dmc_txc_dma0_active; | |
485 | wire dmc_txc_dma0_cacheready; | |
486 | wire [63:0] dmc_txc_dma0_descriptor; | |
487 | wire dmc_txc_dma0_eoflist; | |
488 | wire dmc_txc_dma0_error; | |
489 | wire [1:0] dmc_txc_dma0_func_num; | |
490 | wire dmc_txc_dma0_gotnxtdesc; | |
491 | wire [19:0] dmc_txc_dma0_page_handle; | |
492 | wire dmc_txc_dma0_partial; | |
493 | wire dmc_txc_dma0_reset_scheduled; | |
494 | wire dmc_txc_dma10_active; | |
495 | wire dmc_txc_dma10_cacheready; | |
496 | wire [63:0] dmc_txc_dma10_descriptor; | |
497 | wire dmc_txc_dma10_eoflist; | |
498 | wire dmc_txc_dma10_error; | |
499 | wire [1:0] dmc_txc_dma10_func_num; | |
500 | wire dmc_txc_dma10_gotnxtdesc; | |
501 | wire [19:0] dmc_txc_dma10_page_handle; | |
502 | wire dmc_txc_dma10_partial; | |
503 | wire dmc_txc_dma10_reset_scheduled; | |
504 | wire dmc_txc_dma11_active; | |
505 | wire dmc_txc_dma11_cacheready; | |
506 | wire [63:0] dmc_txc_dma11_descriptor; | |
507 | wire dmc_txc_dma11_eoflist; | |
508 | wire dmc_txc_dma11_error; | |
509 | wire [1:0] dmc_txc_dma11_func_num; | |
510 | wire dmc_txc_dma11_gotnxtdesc; | |
511 | wire [19:0] dmc_txc_dma11_page_handle; | |
512 | wire dmc_txc_dma11_partial; | |
513 | wire dmc_txc_dma11_reset_scheduled; | |
514 | wire dmc_txc_dma12_active; | |
515 | wire dmc_txc_dma12_cacheready; | |
516 | wire [63:0] dmc_txc_dma12_descriptor; | |
517 | wire dmc_txc_dma12_eoflist; | |
518 | wire dmc_txc_dma12_error; | |
519 | wire [1:0] dmc_txc_dma12_func_num; | |
520 | wire dmc_txc_dma12_gotnxtdesc; | |
521 | wire [19:0] dmc_txc_dma12_page_handle; | |
522 | wire dmc_txc_dma12_partial; | |
523 | wire dmc_txc_dma12_reset_scheduled; | |
524 | wire dmc_txc_dma13_active; | |
525 | wire dmc_txc_dma13_cacheready; | |
526 | wire [63:0] dmc_txc_dma13_descriptor; | |
527 | wire dmc_txc_dma13_eoflist; | |
528 | wire dmc_txc_dma13_error; | |
529 | wire [1:0] dmc_txc_dma13_func_num; | |
530 | wire dmc_txc_dma13_gotnxtdesc; | |
531 | wire [19:0] dmc_txc_dma13_page_handle; | |
532 | wire dmc_txc_dma13_partial; | |
533 | wire dmc_txc_dma13_reset_scheduled; | |
534 | wire dmc_txc_dma14_active; | |
535 | wire dmc_txc_dma14_cacheready; | |
536 | wire [63:0] dmc_txc_dma14_descriptor; | |
537 | wire dmc_txc_dma14_eoflist; | |
538 | wire dmc_txc_dma14_error; | |
539 | wire [1:0] dmc_txc_dma14_func_num; | |
540 | wire dmc_txc_dma14_gotnxtdesc; | |
541 | wire [19:0] dmc_txc_dma14_page_handle; | |
542 | wire dmc_txc_dma14_partial; | |
543 | wire dmc_txc_dma14_reset_scheduled; | |
544 | wire dmc_txc_dma15_active; | |
545 | wire dmc_txc_dma15_cacheready; | |
546 | wire [63:0] dmc_txc_dma15_descriptor; | |
547 | wire dmc_txc_dma15_eoflist; | |
548 | wire dmc_txc_dma15_error; | |
549 | wire [1:0] dmc_txc_dma15_func_num; | |
550 | wire dmc_txc_dma15_gotnxtdesc; | |
551 | wire [19:0] dmc_txc_dma15_page_handle; | |
552 | wire dmc_txc_dma15_partial; | |
553 | wire dmc_txc_dma15_reset_scheduled; | |
554 | wire dmc_txc_dma1_active; | |
555 | wire dmc_txc_dma1_cacheready; | |
556 | wire [63:0] dmc_txc_dma1_descriptor; | |
557 | wire dmc_txc_dma1_eoflist; | |
558 | wire dmc_txc_dma1_error; | |
559 | wire [1:0] dmc_txc_dma1_func_num; | |
560 | wire dmc_txc_dma1_gotnxtdesc; | |
561 | wire [19:0] dmc_txc_dma1_page_handle; | |
562 | wire dmc_txc_dma1_partial; | |
563 | wire dmc_txc_dma1_reset_scheduled; | |
564 | wire dmc_txc_dma2_active; | |
565 | wire dmc_txc_dma2_cacheready; | |
566 | wire [63:0] dmc_txc_dma2_descriptor; | |
567 | wire dmc_txc_dma2_eoflist; | |
568 | wire dmc_txc_dma2_error; | |
569 | wire [1:0] dmc_txc_dma2_func_num; | |
570 | wire dmc_txc_dma2_gotnxtdesc; | |
571 | wire [19:0] dmc_txc_dma2_page_handle; | |
572 | wire dmc_txc_dma2_partial; | |
573 | wire dmc_txc_dma2_reset_scheduled; | |
574 | wire dmc_txc_dma3_active; | |
575 | wire dmc_txc_dma3_cacheready; | |
576 | wire [63:0] dmc_txc_dma3_descriptor; | |
577 | wire dmc_txc_dma3_eoflist; | |
578 | wire dmc_txc_dma3_error; | |
579 | wire [1:0] dmc_txc_dma3_func_num; | |
580 | wire dmc_txc_dma3_gotnxtdesc; | |
581 | wire [19:0] dmc_txc_dma3_page_handle; | |
582 | wire dmc_txc_dma3_partial; | |
583 | wire dmc_txc_dma3_reset_scheduled; | |
584 | wire dmc_txc_dma4_active; | |
585 | wire dmc_txc_dma4_cacheready; | |
586 | wire [63:0] dmc_txc_dma4_descriptor; | |
587 | wire dmc_txc_dma4_eoflist; | |
588 | wire dmc_txc_dma4_error; | |
589 | wire [1:0] dmc_txc_dma4_func_num; | |
590 | wire dmc_txc_dma4_gotnxtdesc; | |
591 | wire [19:0] dmc_txc_dma4_page_handle; | |
592 | wire dmc_txc_dma4_partial; | |
593 | wire dmc_txc_dma4_reset_scheduled; | |
594 | wire dmc_txc_dma5_active; | |
595 | wire dmc_txc_dma5_cacheready; | |
596 | wire [63:0] dmc_txc_dma5_descriptor; | |
597 | wire dmc_txc_dma5_eoflist; | |
598 | wire dmc_txc_dma5_error; | |
599 | wire [1:0] dmc_txc_dma5_func_num; | |
600 | wire dmc_txc_dma5_gotnxtdesc; | |
601 | wire [19:0] dmc_txc_dma5_page_handle; | |
602 | wire dmc_txc_dma5_partial; | |
603 | wire dmc_txc_dma5_reset_scheduled; | |
604 | wire dmc_txc_dma6_active; | |
605 | wire dmc_txc_dma6_cacheready; | |
606 | wire [63:0] dmc_txc_dma6_descriptor; | |
607 | wire dmc_txc_dma6_eoflist; | |
608 | wire dmc_txc_dma6_error; | |
609 | wire [1:0] dmc_txc_dma6_func_num; | |
610 | wire dmc_txc_dma6_gotnxtdesc; | |
611 | wire [19:0] dmc_txc_dma6_page_handle; | |
612 | wire dmc_txc_dma6_partial; | |
613 | wire dmc_txc_dma6_reset_scheduled; | |
614 | wire dmc_txc_dma7_active; | |
615 | wire dmc_txc_dma7_cacheready; | |
616 | wire [63:0] dmc_txc_dma7_descriptor; | |
617 | wire dmc_txc_dma7_eoflist; | |
618 | wire dmc_txc_dma7_error; | |
619 | wire [1:0] dmc_txc_dma7_func_num; | |
620 | wire dmc_txc_dma7_gotnxtdesc; | |
621 | wire [19:0] dmc_txc_dma7_page_handle; | |
622 | wire dmc_txc_dma7_partial; | |
623 | wire dmc_txc_dma7_reset_scheduled; | |
624 | wire dmc_txc_dma8_active; | |
625 | wire dmc_txc_dma8_cacheready; | |
626 | wire [63:0] dmc_txc_dma8_descriptor; | |
627 | wire dmc_txc_dma8_eoflist; | |
628 | wire dmc_txc_dma8_error; | |
629 | wire [1:0] dmc_txc_dma8_func_num; | |
630 | wire dmc_txc_dma8_gotnxtdesc; | |
631 | wire [19:0] dmc_txc_dma8_page_handle; | |
632 | wire dmc_txc_dma8_partial; | |
633 | wire dmc_txc_dma8_reset_scheduled; | |
634 | wire dmc_txc_dma9_active; | |
635 | wire dmc_txc_dma9_cacheready; | |
636 | wire [63:0] dmc_txc_dma9_descriptor; | |
637 | wire dmc_txc_dma9_eoflist; | |
638 | wire dmc_txc_dma9_error; | |
639 | wire [1:0] dmc_txc_dma9_func_num; | |
640 | wire dmc_txc_dma9_gotnxtdesc; | |
641 | wire [19:0] dmc_txc_dma9_page_handle; | |
642 | wire dmc_txc_dma9_partial; | |
643 | wire dmc_txc_dma9_reset_scheduled; | |
644 | wire dmc_txc_tx_addr_md; | |
645 | wire [127:0] meta_dmc_data; | |
646 | wire meta_dmc_data_valid_txc; | |
647 | wire [63:0] meta_dmc_resp_address; | |
648 | wire [15:0] meta_dmc_resp_byteenable; | |
649 | wire meta_dmc_resp_client_txc; | |
650 | wire [7:0] meta_dmc_resp_cmd; | |
651 | wire [3:0] meta_dmc_resp_cmd_status; | |
652 | wire meta_dmc_resp_complete_txc; | |
653 | wire [4:0] meta_dmc_resp_dma_num; | |
654 | wire [13:0] meta_dmc_resp_length; | |
655 | wire [1:0] meta_dmc_resp_port_num; | |
656 | wire meta_dmc_resp_ready; | |
657 | wire [5:0] meta_dmc_resp_trans_id; | |
658 | wire meta_dmc_resp_transfer_cmpl_txc; | |
659 | wire niu_dbg1_stall_ack; | |
660 | wire niu_efu_ram_data; | |
661 | wire niu_efu_ram_xfer_en; | |
662 | wire niu_ncu_ctag_ce; | |
663 | wire niu_ncu_ctag_ue; | |
664 | wire niu_ncu_d_pe; | |
665 | wire [127:0] niu_sii_data; | |
666 | wire niu_sii_datareq; | |
667 | wire niu_sii_hdr_vld; | |
668 | wire [7:0] niu_sii_parity; | |
669 | wire niu_sii_reqbypass; | |
670 | wire niu_sio_dq; | |
671 | wire tds_scan_out; | |
672 | wire tds_mbist_scan_out; | |
673 | wire tds_smx_tcu_mbist_done; | |
674 | wire tds_smx_tcu_mbist_fail; | |
675 | wire [39:0] tds_tcu_dmo_dout; | |
676 | wire tds_tdmc_tcu_mbist_done; | |
677 | wire tds_tdmc_tcu_mbist_fail; | |
678 | wire cmp_gclk_c0_rtx; | |
679 | wire efu_niu_4k_clr; | |
680 | wire efu_niu_4k_data; | |
681 | wire efu_niu_4k_xfer_en; | |
682 | wire efu_niu_cfifo0_clr; | |
683 | wire efu_niu_cfifo0_xfer_en; | |
684 | wire efu_niu_cfifo1_clr; | |
685 | wire efu_niu_cfifo1_xfer_en; | |
686 | wire efu_niu_cfifo_data; | |
687 | wire efu_niu_ipp0_clr; | |
688 | wire efu_niu_ipp0_xfer_en; | |
689 | wire efu_niu_ipp1_clr; | |
690 | wire efu_niu_ipp1_xfer_en; | |
691 | wire efu_niu_mac01_sfro_data; | |
692 | wire efu_niu_mac0_ro_clr; | |
693 | wire efu_niu_mac0_ro_xfer_en; | |
694 | wire efu_niu_mac0_sf_clr; | |
695 | wire efu_niu_mac0_sf_xfer_en; | |
696 | wire efu_niu_mac1_ro_clr; | |
697 | wire efu_niu_mac1_ro_xfer_en; | |
698 | wire efu_niu_mac1_sf_clr; | |
699 | wire efu_niu_mac1_sf_xfer_en; | |
700 | wire mac_rxc_ack0; | |
701 | wire mac_rxc_ack1; | |
702 | wire mac_rxc_ctrl0; | |
703 | wire mac_rxc_ctrl1; | |
704 | wire [63:0] mac_rxc_data0; | |
705 | wire [63:0] mac_rxc_data1; | |
706 | wire [22:0] mac_rxc_stat0; | |
707 | wire [22:0] mac_rxc_stat1; | |
708 | wire mac_rxc_tag0; | |
709 | wire mac_rxc_tag1; | |
710 | wire mac_txc_req0; | |
711 | wire mac_txc_req1; | |
712 | wire rtx_mbist_scan_in; | |
713 | wire tcu_socf_scan_out; | |
714 | wire [2:0] tcu_rtx_dmo_ctl; | |
715 | wire gl_rtx_io_clk_stop; | |
716 | wire tcu_rtx_rxc_ipp0_mbist_start; | |
717 | wire tcu_rtx_rxc_ipp1_mbist_start; | |
718 | wire tcu_rtx_rxc_mb5_mbist_start; | |
719 | wire tcu_rtx_rxc_mb6_mbist_start; | |
720 | wire tcu_rtx_rxc_zcp0_mbist_start; | |
721 | wire tcu_rtx_rxc_zcp1_mbist_start; | |
722 | wire tcu_rtx_txc_txe0_mbist_start; | |
723 | wire tcu_rtx_txc_txe1_mbist_start; | |
724 | wire niu_efu_4k_data; | |
725 | wire niu_efu_4k_xfer_en; | |
726 | wire niu_efu_cfifo0_data; | |
727 | wire niu_efu_cfifo0_xfer_en; | |
728 | wire niu_efu_cfifo1_data; | |
729 | wire niu_efu_cfifo1_xfer_en; | |
730 | wire niu_efu_ipp0_data; | |
731 | wire niu_efu_ipp0_xfer_en; | |
732 | wire niu_efu_ipp1_data; | |
733 | wire niu_efu_ipp1_xfer_en; | |
734 | wire niu_efu_mac0_ro_data; | |
735 | wire niu_efu_mac0_ro_xfer_en; | |
736 | wire niu_efu_mac0_sf_data; | |
737 | wire niu_efu_mac0_sf_xfer_en; | |
738 | wire niu_efu_mac1_ro_data; | |
739 | wire niu_efu_mac1_ro_xfer_en; | |
740 | wire niu_efu_mac1_sf_data; | |
741 | wire niu_efu_mac1_sf_xfer_en; | |
742 | wire rtx_mbist_scan_out; | |
743 | wire rtx_rxc_ipp0_tcu_mbist_done; | |
744 | wire rtx_rxc_ipp0_tcu_mbist_fail; | |
745 | wire rtx_rxc_ipp1_tcu_mbist_done; | |
746 | wire rtx_rxc_ipp1_tcu_mbist_fail; | |
747 | wire rtx_rxc_mb5_tcu_mbist_done; | |
748 | wire rtx_rxc_mb5_tcu_mbist_fail; | |
749 | wire rtx_rxc_mb6_tcu_mbist_done; | |
750 | wire rtx_rxc_mb6_tcu_mbist_fail; | |
751 | wire rtx_rxc_zcp0_tcu_mbist_done; | |
752 | wire rtx_rxc_zcp0_tcu_mbist_fail; | |
753 | wire rtx_rxc_zcp1_tcu_mbist_done; | |
754 | wire rtx_rxc_zcp1_tcu_mbist_fail; | |
755 | wire [39:0] rtx_tcu_dmo_data_out; | |
756 | wire rtx_txc_txe0_tcu_mbist_done; | |
757 | wire rtx_txc_txe0_tcu_mbist_fail; | |
758 | wire rtx_txc_txe1_tcu_mbist_done; | |
759 | wire rtx_txc_txe1_tcu_mbist_fail; | |
760 | wire rxc_mac_req0; | |
761 | wire rxc_mac_req1; | |
762 | wire rtx_scan_out; | |
763 | wire txc_mac_abort0; | |
764 | wire txc_mac_abort1; | |
765 | wire txc_mac_ack0; | |
766 | wire txc_mac_ack1; | |
767 | wire [63:0] txc_mac_data0; | |
768 | wire [63:0] txc_mac_data1; | |
769 | wire [3:0] txc_mac_stat0; | |
770 | wire [3:0] txc_mac_stat1; | |
771 | wire txc_mac_tag0; | |
772 | wire txc_mac_tag1; | |
773 | wire [3:0] esr_mac_rclk_0; | |
774 | wire [3:0] esr_mac_rclk_1; | |
775 | wire [9:0] esr_mac_rxd0_0; | |
776 | wire [9:0] esr_mac_rxd0_1; | |
777 | wire [9:0] esr_mac_rxd1_0; | |
778 | wire [9:0] esr_mac_rxd1_1; | |
779 | wire [9:0] esr_mac_rxd2_0; | |
780 | wire [9:0] esr_mac_rxd2_1; | |
781 | wire [9:0] esr_mac_rxd3_0; | |
782 | wire [9:0] esr_mac_rxd3_1; | |
783 | wire esr_mac_tclk_0; | |
784 | wire esr_mac_tclk_1; | |
785 | wire cmp_gclk_c1_mac; | |
786 | wire gl_mac_io_clk_stop; | |
787 | wire mac_125rx_test_clk; | |
788 | wire mac_125tx_test_clk; | |
789 | wire mac_156rx_test_clk; | |
790 | wire mac_156tx_test_clk; | |
791 | wire mac_312rx_test_clk; | |
792 | wire mac_312tx_test_clk; | |
793 | wire mdi; | |
794 | wire peu_mac_sbs_input; | |
795 | wire gl_rst_mac_c1b; | |
796 | wire tcu_soc5_scan_out; | |
797 | wire [3:0] stspll_0; | |
798 | wire [3:0] stspll_1; | |
799 | wire [7:0] stsrx0_0; | |
800 | wire [7:0] stsrx0_1; | |
801 | wire [7:0] stsrx1_0; | |
802 | wire [7:0] stsrx1_1; | |
803 | wire [7:0] stsrx2_0; | |
804 | wire [7:0] stsrx2_1; | |
805 | wire [7:0] stsrx3_0; | |
806 | wire [7:0] stsrx3_1; | |
807 | wire [3:0] ststx0_0; | |
808 | wire [3:0] ststx0_1; | |
809 | wire [3:0] ststx1_0; | |
810 | wire [3:0] ststx1_1; | |
811 | wire [3:0] ststx2_0; | |
812 | wire [3:0] ststx2_1; | |
813 | wire [3:0] ststx3_0; | |
814 | wire [3:0] ststx3_1; | |
815 | wire tcu_sbs_acmode; | |
816 | wire tcu_sbs_actestsignal; | |
817 | wire tcu_sbs_aclk; | |
818 | wire tcu_sbs_bclk; | |
819 | wire tcu_sbs_clk; | |
820 | wire tcu_sbs_enbspt; | |
821 | wire tcu_sbs_enbsrx; | |
822 | wire tcu_sbs_enbstx; | |
823 | wire tcu_sbs_scan_en; | |
824 | wire tcu_sbs_uclk; | |
825 | wire tcu_mac_testmode; | |
826 | wire [11:0] cfgpll_0; | |
827 | wire [11:0] cfgpll_1; | |
828 | wire [27:0] cfgrx0_0; | |
829 | wire [27:0] cfgrx0_1; | |
830 | wire [27:0] cfgrx1_0; | |
831 | wire [27:0] cfgrx1_1; | |
832 | wire [27:0] cfgrx2_0; | |
833 | wire [27:0] cfgrx2_1; | |
834 | wire [27:0] cfgrx3_0; | |
835 | wire [27:0] cfgrx3_1; | |
836 | wire [19:0] cfgtx0_0; | |
837 | wire [19:0] cfgtx0_1; | |
838 | wire [19:0] cfgtx1_0; | |
839 | wire [19:0] cfgtx1_1; | |
840 | wire [19:0] cfgtx2_0; | |
841 | wire [19:0] cfgtx2_1; | |
842 | wire [19:0] cfgtx3_0; | |
843 | wire [19:0] cfgtx3_1; | |
844 | wire [3:0] mac_esr_tclk_0; | |
845 | wire [3:0] mac_esr_tclk_1; | |
846 | wire [9:0] mac_esr_txd0_0; | |
847 | wire [9:0] mac_esr_txd0_1; | |
848 | wire [9:0] mac_esr_txd1_0; | |
849 | wire [9:0] mac_esr_txd1_1; | |
850 | wire [9:0] mac_esr_txd2_0; | |
851 | wire [9:0] mac_esr_txd2_1; | |
852 | wire [9:0] mac_esr_txd3_0; | |
853 | wire [9:0] mac_esr_txd3_1; | |
854 | wire mac_mcu_3_sbs_output; | |
855 | wire mdoe; | |
856 | wire mac_scan_out; | |
857 | wire [15:0] testcfg_0; | |
858 | wire [15:0] testcfg_1; | |
859 | wire xaui_act_led_0; | |
860 | wire xaui_act_led_1; | |
861 | wire xaui_link_led_0; | |
862 | wire xaui_link_led_1; | |
863 | wire mio_mac_xaui_mdint1_l; | |
864 | wire mio_mac_xaui_mdint0_l; | |
865 | wire mdc; | |
866 | wire [1:0] tcu_stcicfg; | |
867 | wire tcu_stciclk; | |
868 | wire esr_stcid; | |
869 | wire stcid_1; | |
870 | wire mio_esr_testclkr; | |
871 | wire mio_esr_testclkt; | |
872 | wire fdi_1; | |
873 | wire efu_niu_fclk; | |
874 | wire efu_niu_fclrz; | |
875 | wire efu_niu_fdi; | |
876 | wire esr_stciq; | |
877 | wire niu_efu_fdo; | |
878 | wire tcu_sbs_bsinitclk; | |
879 | wire tcu_srd_atpgse; | |
880 | wire [2:0] tcu_srd_atpgmode; | |
881 | wire esr_atpgd; | |
882 | wire esr_atpgq; | |
883 | wire db0_scan_out; | |
884 | wire cmp_gclk_c3_mio; | |
885 | wire cmp_gclk_c2_mio_left; | |
886 | wire cmp_gclk_c2_mio_right; | |
887 | wire cmp_gclk_c1_mio; | |
888 | wire gl_mio_clk_stop_c3t; | |
889 | wire gl_mio_clk_stop_c2t; | |
890 | wire gl_mio_clk_stop_c1t; | |
891 | wire gl_io2x_sync_en_c3t0; | |
892 | wire gl_io2x_sync_en_c2t; | |
893 | wire gl_mio_io2x_sync_en_c1t; | |
894 | wire gl_io_out_c3t; | |
895 | wire pcmb0_mio_ro_in; | |
896 | wire mio_tcu_tms; | |
897 | wire mio_tcu_tdi; | |
898 | wire mio_tcu_trst_l; | |
899 | wire mio_tcu_tck; | |
900 | wire mio_tcu_testmode; | |
901 | wire mio_psr_testclkt; | |
902 | wire mio_psr_testclkr; | |
903 | wire [2:0] mio_spc_pwr_throttle_0; | |
904 | wire [2:0] mio_spc_pwr_throttle_1; | |
905 | wire mio_pcmb0_sel59; | |
906 | wire mio_pcmb1_sel60; | |
907 | wire mio_pcma_sel61; | |
908 | wire mio_pcm_burnin; | |
909 | wire mio_efu_prgm_en; | |
910 | wire mio_scan_out; | |
911 | wire db1_scan_out; | |
912 | wire [7:0] dmu_mio_debug_bus_a; | |
913 | wire [7:0] dmu_mio_debug_bus_b; | |
914 | wire cmp_gclk_c3_db0; | |
915 | wire gl_db0_clk_stop; | |
916 | wire gl_io_out_c3b0; | |
917 | wire gl_io2x_sync_en_c3t; | |
918 | wire gl_io_cmp_sync_en_c3b; | |
919 | wire tcu_aclk; | |
920 | wire tcu_bclk; | |
921 | wire tcu_scan_en; | |
922 | wire dmu_ncu_wrack_vld; | |
923 | wire [3:0] dmu_ncu_wrack_tag; | |
924 | wire [31:0] dmu_ncu_data; | |
925 | wire dmu_ncu_vld; | |
926 | wire dmu_ncu_stall; | |
927 | wire dmu_sii_hdr_vld; | |
928 | wire dmu_sii_reqbypass; | |
929 | wire dmu_sii_datareq; | |
930 | wire dmu_sii_datareq16; | |
931 | wire [127:0] dmu_sii_data; | |
932 | wire [15:0] dmu_sii_be; | |
933 | wire l2t0_dbg0_sii_iq_dequeue; | |
934 | wire l2t2_dbg0_sii_iq_dequeue; | |
935 | wire l2t0_dbg0_sii_wib_dequeue; | |
936 | wire l2t2_dbg0_sii_wib_dequeue; | |
937 | wire l2t0_dbg0_err_event; | |
938 | wire l2t2_dbg0_err_event; | |
939 | wire l2t0_dbg0_pa_match; | |
940 | wire l2t2_dbg0_pa_match; | |
941 | wire [5:0] l2t0_dbg0_xbar_vcid; | |
942 | wire [5:0] l2t2_dbg0_xbar_vcid; | |
943 | wire l2b0_dbg0_sio_ctag_vld; | |
944 | wire l2b1_dbg0_sio_ctag_vld; | |
945 | wire l2b2_dbg0_sio_ctag_vld; | |
946 | wire l2b3_dbg0_sio_ctag_vld; | |
947 | wire l2b0_dbg0_sio_ack_type; | |
948 | wire l2b1_dbg0_sio_ack_type; | |
949 | wire l2b2_dbg0_sio_ack_type; | |
950 | wire l2b3_dbg0_sio_ack_type; | |
951 | wire l2b0_dbg0_sio_ack_dest; | |
952 | wire l2b1_dbg0_sio_ack_dest; | |
953 | wire l2b2_dbg0_sio_ack_dest; | |
954 | wire l2b3_dbg0_sio_ack_dest; | |
955 | wire [1:0] spc0_dbg0_instr_cmt_grp0; | |
956 | wire [1:0] spc0_dbg0_instr_cmt_grp1; | |
957 | wire [1:0] spc2_dbg0_instr_cmt_grp0; | |
958 | wire [1:0] spc2_dbg0_instr_cmt_grp1; | |
959 | wire [165:0] dbg0_dbg1_debug_data; | |
960 | wire dbg0_dbg1_l2t0_sii_iq_dequeue; | |
961 | wire dbg0_dbg1_l2t2_sii_iq_dequeue; | |
962 | wire dbg0_dbg1_l2t0_sii_wib_dequeue; | |
963 | wire dbg0_dbg1_l2t2_sii_wib_dequeue; | |
964 | wire dbg0_dbg1_l2t0_err_event; | |
965 | wire dbg0_dbg1_l2t2_err_event; | |
966 | wire dbg0_dbg1_l2t0_pa_match; | |
967 | wire dbg0_dbg1_l2t2_pa_match; | |
968 | wire [5:0] dbg0_dbg1_l2t0_xbar_vcid; | |
969 | wire [5:0] dbg0_dbg1_l2t2_xbar_vcid; | |
970 | wire dbg0_dbg1_l2b0_sio_ctag_vld; | |
971 | wire dbg0_dbg1_l2b1_sio_ctag_vld; | |
972 | wire dbg0_dbg1_l2b2_sio_ctag_vld; | |
973 | wire dbg0_dbg1_l2b3_sio_ctag_vld; | |
974 | wire dbg0_dbg1_l2b0_sio_ack_type; | |
975 | wire dbg0_dbg1_l2b1_sio_ack_type; | |
976 | wire dbg0_dbg1_l2b2_sio_ack_type; | |
977 | wire dbg0_dbg1_l2b3_sio_ack_type; | |
978 | wire dbg0_dbg1_l2b0_sio_ack_dest; | |
979 | wire dbg0_dbg1_l2b1_sio_ack_dest; | |
980 | wire dbg0_dbg1_l2b2_sio_ack_dest; | |
981 | wire dbg0_dbg1_l2b3_sio_ack_dest; | |
982 | wire [1:0] dbg0_dbg1_spc0_instr_cmt_grp0; | |
983 | wire [1:0] dbg0_dbg1_spc0_instr_cmt_grp1; | |
984 | wire [1:0] dbg0_dbg1_spc2_instr_cmt_grp0; | |
985 | wire [1:0] dbg0_dbg1_spc2_instr_cmt_grp1; | |
986 | wire [7:0] dbg0_mio_debug_bus_a; | |
987 | wire [7:0] dbg0_mio_debug_bus_b; | |
988 | wire tcu_soc6_scan_out; | |
989 | wire dmu_dbg_err_event; | |
990 | wire cmp_gclk_c1_db1; | |
991 | wire gl_db1_clk_stop; | |
992 | wire gl_io_out_c1m; | |
993 | wire gl_io2x_sync_en_c1m; | |
994 | wire gl_io_cmp_sync_en_c1m; | |
995 | wire gl_cmp_io_sync_en_c1m; | |
996 | wire rst_wmr_protect; | |
997 | wire ccu_dbg1_serdes_dtm; | |
998 | wire l2t1_dbg1_sii_iq_dequeue; | |
999 | wire l2t3_dbg1_sii_iq_dequeue; | |
1000 | wire l2t4_dbg1_sii_iq_dequeue; | |
1001 | wire l2t5_dbg1_sii_iq_dequeue; | |
1002 | wire l2t6_dbg1_sii_iq_dequeue; | |
1003 | wire l2t7_dbg1_sii_iq_dequeue; | |
1004 | wire l2t1_dbg1_sii_wib_dequeue; | |
1005 | wire l2t3_dbg1_sii_wib_dequeue; | |
1006 | wire l2t4_dbg1_sii_wib_dequeue; | |
1007 | wire l2t5_dbg1_sii_wib_dequeue; | |
1008 | wire l2t6_dbg1_sii_wib_dequeue; | |
1009 | wire l2t7_dbg1_sii_wib_dequeue; | |
1010 | wire l2t1_dbg1_err_event; | |
1011 | wire l2t3_dbg1_err_event; | |
1012 | wire l2t4_dbg1_err_event; | |
1013 | wire l2t6_dbg1_err_event; | |
1014 | wire l2t7_dbg1_err_event; | |
1015 | wire l2t1_dbg1_pa_match; | |
1016 | wire l2t3_dbg1_pa_match; | |
1017 | wire l2t4_dbg1_pa_match; | |
1018 | wire l2t5_dbg1_pa_match; | |
1019 | wire l2t6_dbg1_pa_match; | |
1020 | wire l2t7_dbg1_pa_match; | |
1021 | wire [5:0] l2t1_dbg1_xbar_vcid; | |
1022 | wire [5:0] l2t3_dbg1_xbar_vcid; | |
1023 | wire [5:0] l2t4_dbg1_xbar_vcid; | |
1024 | wire [5:0] l2t5_dbg1_xbar_vcid; | |
1025 | wire [5:0] l2t6_dbg1_xbar_vcid; | |
1026 | wire [5:0] l2t7_dbg1_xbar_vcid; | |
1027 | wire l2b4_dbg1_sio_ctag_vld; | |
1028 | wire l2b5_dbg1_sio_ctag_vld; | |
1029 | wire l2b6_dbg1_sio_ctag_vld; | |
1030 | wire l2b7_dbg1_sio_ctag_vld; | |
1031 | wire l2b4_dbg1_sio_ack_type; | |
1032 | wire l2b5_dbg1_sio_ack_type; | |
1033 | wire l2b6_dbg1_sio_ack_type; | |
1034 | wire l2b7_dbg1_sio_ack_type; | |
1035 | wire l2b4_dbg1_sio_ack_dest; | |
1036 | wire l2b5_dbg1_sio_ack_dest; | |
1037 | wire l2b6_dbg1_sio_ack_dest; | |
1038 | wire l2b7_dbg1_sio_ack_dest; | |
1039 | wire [1:0] spc1_dbg1_instr_cmt_grp0; | |
1040 | wire [1:0] spc1_dbg1_instr_cmt_grp1; | |
1041 | wire [1:0] spc3_dbg1_instr_cmt_grp0; | |
1042 | wire [1:0] spc3_dbg1_instr_cmt_grp1; | |
1043 | wire [1:0] spc4_dbg1_instr_cmt_grp0; | |
1044 | wire [1:0] spc4_dbg1_instr_cmt_grp1; | |
1045 | wire [1:0] spc5_dbg1_instr_cmt_grp0; | |
1046 | wire [1:0] spc5_dbg1_instr_cmt_grp1; | |
1047 | wire [1:0] spc6_dbg1_instr_cmt_grp0; | |
1048 | wire [1:0] spc6_dbg1_instr_cmt_grp1; | |
1049 | wire [1:0] spc7_dbg1_instr_cmt_grp0; | |
1050 | wire [1:0] spc7_dbg1_instr_cmt_grp1; | |
1051 | wire mcu0_dbg1_crc21; | |
1052 | wire [3:0] mcu0_dbg1_rd_req_in_0; | |
1053 | wire [3:0] mcu0_dbg1_rd_req_in_1; | |
1054 | wire [4:0] mcu0_dbg1_rd_req_out; | |
1055 | wire mcu0_dbg1_wr_req_in_0; | |
1056 | wire mcu0_dbg1_wr_req_in_1; | |
1057 | wire [1:0] mcu0_dbg1_wr_req_out; | |
1058 | wire mcu0_dbg1_mecc_err; | |
1059 | wire mcu0_dbg1_secc_err; | |
1060 | wire mcu0_dbg1_fbd_err; | |
1061 | wire mcu0_dbg1_err_mode; | |
1062 | wire mcu0_dbg1_err_event; | |
1063 | wire mcu1_dbg1_crc21; | |
1064 | wire [3:0] mcu1_dbg1_rd_req_in_0; | |
1065 | wire [3:0] mcu1_dbg1_rd_req_in_1; | |
1066 | wire [4:0] mcu1_dbg1_rd_req_out; | |
1067 | wire mcu1_dbg1_wr_req_in_0; | |
1068 | wire mcu1_dbg1_wr_req_in_1; | |
1069 | wire [1:0] mcu1_dbg1_wr_req_out; | |
1070 | wire mcu1_dbg1_mecc_err; | |
1071 | wire mcu1_dbg1_secc_err; | |
1072 | wire mcu1_dbg1_fbd_err; | |
1073 | wire mcu1_dbg1_err_mode; | |
1074 | wire mcu1_dbg1_err_event; | |
1075 | wire mcu2_dbg1_crc21; | |
1076 | wire [3:0] mcu2_dbg1_rd_req_in_0; | |
1077 | wire [3:0] mcu2_dbg1_rd_req_in_1; | |
1078 | wire [4:0] mcu2_dbg1_rd_req_out; | |
1079 | wire mcu2_dbg1_wr_req_in_0; | |
1080 | wire mcu2_dbg1_wr_req_in_1; | |
1081 | wire [1:0] mcu2_dbg1_wr_req_out; | |
1082 | wire mcu2_dbg1_mecc_err; | |
1083 | wire mcu2_dbg1_secc_err; | |
1084 | wire mcu2_dbg1_fbd_err; | |
1085 | wire mcu2_dbg1_err_mode; | |
1086 | wire mcu2_dbg1_err_event; | |
1087 | wire mcu3_dbg1_crc21; | |
1088 | wire [3:0] mcu3_dbg1_rd_req_in_0; | |
1089 | wire [3:0] mcu3_dbg1_rd_req_in_1; | |
1090 | wire [4:0] mcu3_dbg1_rd_req_out; | |
1091 | wire mcu3_dbg1_wr_req_in_0; | |
1092 | wire mcu3_dbg1_wr_req_in_1; | |
1093 | wire [1:0] mcu3_dbg1_wr_req_out; | |
1094 | wire mcu3_dbg1_mecc_err; | |
1095 | wire mcu3_dbg1_secc_err; | |
1096 | wire mcu3_dbg1_fbd_err; | |
1097 | wire mcu3_dbg1_err_mode; | |
1098 | wire mcu3_dbg1_err_event; | |
1099 | wire dbg1_dmu_stall; | |
1100 | wire dmu_dbg1_stall_ack; | |
1101 | wire dbg1_dmu_resume; | |
1102 | wire [1:0] sii_dbg1_l2t0_req_ccxrff; | |
1103 | wire [1:0] sii_dbg1_l2t1_req_ccxrff; | |
1104 | wire [1:0] sii_dbg1_l2t2_req_ccxrff; | |
1105 | wire [1:0] sii_dbg1_l2t3_req_ccxrff; | |
1106 | wire [1:0] sii_dbg1_l2t4_req_ccxrff; | |
1107 | wire [1:0] sii_dbg1_l2t5_req_ccxrff; | |
1108 | wire [1:0] sii_dbg1_l2t6_req_ccxrff; | |
1109 | wire [1:0] sii_dbg1_l2t7_req_ccxrff; | |
1110 | wire ncu_dbg1_error_event; | |
1111 | wire ncu_dbg1_stall; | |
1112 | wire ncu_dbg1_vld; | |
1113 | wire [3:0] ncu_dbg1_data; | |
1114 | wire dbg1_ncu_stall; | |
1115 | wire dbg1_ncu_vld; | |
1116 | wire [3:0] dbg1_ncu_data; | |
1117 | wire dbg1_tcu_soc_hard_stop; | |
1118 | wire dbg1_tcu_soc_asrt_trigout; | |
1119 | wire tcu_mio_jtag_membist_mode; | |
1120 | wire mio_pll_testmode; | |
1121 | wire [165:0] dbg1_mio_dbg_dq; | |
1122 | wire dbg1_mio_drv_en_op_only; | |
1123 | wire dbg1_mio_drv_en_muxtest_op; | |
1124 | wire dbg1_mio_drv_en_muxbist_op; | |
1125 | wire dbg1_mio_drv_en_muxtest_inp; | |
1126 | wire dbg1_mio_drv_en_muxtestpll_inp; | |
1127 | wire dbg1_mio_sel_niu_debug_mode; | |
1128 | wire dbg1_mio_sel_pcix_debug_mode; | |
1129 | wire dbg1_mio_sel_soc_obs_mode; | |
1130 | wire [1:0] dbg1_mio_drv_imped; | |
1131 | wire dbg0_dbg1_l2b0_sio_ack_dest_ccxlff; | |
1132 | wire dbg0_dbg1_l2b0_sio_ack_type_ccxlff; | |
1133 | wire dbg0_dbg1_l2b0_sio_ctag_vld_ccxlff; | |
1134 | wire dbg0_dbg1_l2b1_sio_ack_dest_ccxlff; | |
1135 | wire dbg0_dbg1_l2b1_sio_ack_type_ccxlff; | |
1136 | wire dbg0_dbg1_l2b1_sio_ctag_vld_ccxlff; | |
1137 | wire dbg0_dbg1_l2b2_sio_ack_dest_ccxlff; | |
1138 | wire dbg0_dbg1_l2b2_sio_ack_type_ccxlff; | |
1139 | wire dbg0_dbg1_l2b2_sio_ctag_vld_ccxlff; | |
1140 | wire dbg0_dbg1_l2b3_sio_ack_dest_ccxlff; | |
1141 | wire dbg0_dbg1_l2b3_sio_ack_type_ccxlff; | |
1142 | wire dbg0_dbg1_l2b3_sio_ctag_vld_ccxlff; | |
1143 | wire dbg0_dbg1_l2t0_err_event_ccxlff; | |
1144 | wire dbg0_dbg1_l2t0_pa_match_ccxlff; | |
1145 | wire dbg0_dbg1_l2t0_sii_iq_dequeue_ccxlff; | |
1146 | wire dbg0_dbg1_l2t0_sii_wib_dequeue_ccxlff; | |
1147 | wire [5:0] dbg0_dbg1_l2t0_xbar_vcid_ccxlff; | |
1148 | wire dbg0_dbg1_l2t2_err_event_ccxlff; | |
1149 | wire dbg0_dbg1_l2t2_pa_match_ccxlff; | |
1150 | wire dbg0_dbg1_l2t2_sii_iq_dequeue_ccxlff; | |
1151 | wire dbg0_dbg1_l2t2_sii_wib_dequeue_ccxlff; | |
1152 | wire [5:0] dbg0_dbg1_l2t2_xbar_vcid_ccxlff; | |
1153 | wire dbg0_dbg1_spc0_instr_cmt_grp0_ccxlff_1; | |
1154 | wire dbg0_dbg1_spc0_instr_cmt_grp0_ccxlff_0; | |
1155 | wire dbg0_dbg1_spc0_instr_cmt_grp1_ccxlff_1; | |
1156 | wire dbg0_dbg1_spc0_instr_cmt_grp1_ccxlff_0; | |
1157 | wire dbg0_dbg1_spc2_instr_cmt_grp0_ccxlff_1; | |
1158 | wire dbg0_dbg1_spc2_instr_cmt_grp0_ccxlff_0; | |
1159 | wire dbg0_dbg1_spc2_instr_cmt_grp1_ccxlff_1; | |
1160 | wire dbg0_dbg1_spc2_instr_cmt_grp1_ccxlff_0; | |
1161 | wire cmp_gclk_c3_spc0; | |
1162 | wire gl_spc0_clk_stop; | |
1163 | wire [145:0] cpx_spc0_data_cx2; | |
1164 | wire [8:0] pcx_spc0_grant_px; | |
1165 | wire [8:0] spc0_pcx_req_pq; | |
1166 | wire [8:0] spc0_pcx_atm_pq; | |
1167 | wire [129:0] spc0_pcx_data_pa; | |
1168 | wire spc0_hardstop_request; | |
1169 | wire spc0_softstop_request; | |
1170 | wire spc0_trigger_pulse; | |
1171 | wire [7:0] tcu_ss_mode; | |
1172 | wire [7:0] tcu_do_mode; | |
1173 | wire tcu_ss_request_t1lff_0; | |
1174 | wire spc0_ss_complete; | |
1175 | wire tcu_spc0_aclk; | |
1176 | wire tcu_spc0_bclk; | |
1177 | wire tcu_spc0_scan_en; | |
1178 | wire tcu_spc0_se_scancollar_in; | |
1179 | wire tcu_spc0_se_scancollar_out; | |
1180 | wire tcu_spc0_array_wr_inhibit; | |
1181 | wire [7:0] ncu_spc0_core_running; | |
1182 | wire [7:0] spc0_ncu_core_running_status; | |
1183 | wire [1:0] spc0_tcu_scan_in; | |
1184 | wire [1:0] tcu_spc0_scan_out; | |
1185 | wire tcu_spc0_mbist_start_t1lff_0; | |
1186 | wire spc0_tcu_mbist_done; | |
1187 | wire spc0_tcu_mbist_fail; | |
1188 | wire tcu_spc0_mbist_scan_in; | |
1189 | wire spc0_tcu_mbist_scan_out; | |
1190 | wire [35:0] spc0_dmo_dout; | |
1191 | wire [7:0] tcu_spc_lbist_start; | |
1192 | wire [7:0] tcu_spc_lbist_scan_in; | |
1193 | wire spc0_tcu_lbist_done; | |
1194 | wire spc0_tcu_lbist_scan_out; | |
1195 | wire tcu_spc_shscan_pce_ov; | |
1196 | wire tcu_spc_shscan_aclk; | |
1197 | wire tcu_spc_shscan_bclk; | |
1198 | wire tcu_spc_shscan_scan_en; | |
1199 | wire [2:0] tcu_spc_shscanid; | |
1200 | wire tcu_spc0_shscan_scan_out; | |
1201 | wire spc0_tcu_shscan_scan_in; | |
1202 | wire tcu_spc0_shscan_clk_stop; | |
1203 | wire efu_spc0246_fuse_data; | |
1204 | wire efu_spc0_fuse_ixfer_en; | |
1205 | wire efu_spc0_fuse_iclr; | |
1206 | wire efu_spc0_fuse_dxfer_en; | |
1207 | wire efu_spc0_fuse_dclr; | |
1208 | wire spc0_efu_fuse_dxfer_en; | |
1209 | wire spc0_efu_fuse_ixfer_en; | |
1210 | wire spc0_efu_fuse_ddata; | |
1211 | wire spc0_efu_fuse_idata; | |
1212 | wire gl_io_cmp_sync_en_c3t0; | |
1213 | wire gl_cmp_io_sync_en_c3t0; | |
1214 | wire [3:0] spc_revid_out; | |
1215 | wire tcu_dectest; | |
1216 | wire tcu_muxtest; | |
1217 | wire ncu_cmp_tick_enable; | |
1218 | wire ncu_wmr_vec_mask; | |
1219 | wire ncu_spc_pm; | |
1220 | wire ncu_spc_ba01; | |
1221 | wire ncu_spc_ba23; | |
1222 | wire ncu_spc_ba45; | |
1223 | wire ncu_spc_ba67; | |
1224 | wire tcu_spc_lbist_pgm; | |
1225 | wire tcu_spc0_test_mode; | |
1226 | wire dmo_icmuxctl; | |
1227 | wire dmo_dcmuxctl; | |
1228 | wire cmp_gclk_c2_spc1; | |
1229 | wire gl_spc1_clk_stop; | |
1230 | wire [145:0] cpx_spc1_data_cx2; | |
1231 | wire [8:0] pcx_spc1_grant_px; | |
1232 | wire [8:0] spc1_pcx_req_pq; | |
1233 | wire [8:0] spc1_pcx_atm_pq; | |
1234 | wire [129:0] spc1_pcx_data_pa; | |
1235 | wire spc1_hardstop_request; | |
1236 | wire spc1_softstop_request; | |
1237 | wire spc1_trigger_pulse; | |
1238 | wire [7:0] tcu_ss_request; | |
1239 | wire spc1_ss_complete; | |
1240 | wire tcu_spc1_aclk; | |
1241 | wire tcu_spc1_bclk; | |
1242 | wire tcu_spc1_scan_en; | |
1243 | wire tcu_spc1_se_scancollar_in; | |
1244 | wire tcu_spc1_se_scancollar_out; | |
1245 | wire tcu_spc1_array_wr_inhibit; | |
1246 | wire [7:0] ncu_spc1_core_running; | |
1247 | wire [7:0] spc1_ncu_core_running_status; | |
1248 | wire [1:0] spc1_tcu_scan_in; | |
1249 | wire [1:0] tcu_spc1_scan_out; | |
1250 | wire [7:0] tcu_spc_mbist_start; | |
1251 | wire spc1_tcu_mbist_done; | |
1252 | wire spc1_tcu_mbist_fail; | |
1253 | wire tcu_spc1_mbist_scan_in; | |
1254 | wire spc1_tcu_mbist_scan_out; | |
1255 | wire [35:0] spc1_dmo_dout; | |
1256 | wire [5:0] dmo_coresel; | |
1257 | wire spc1_tcu_lbist_done; | |
1258 | wire spc1_tcu_lbist_scan_out; | |
1259 | wire tcu_spc1_shscan_scan_out; | |
1260 | wire spc1_tcu_shscan_scan_in; | |
1261 | wire tcu_spc1_shscan_clk_stop; | |
1262 | wire efu_spc1357_fuse_data; | |
1263 | wire efu_spc1_fuse_ixfer_en; | |
1264 | wire efu_spc1_fuse_iclr; | |
1265 | wire efu_spc1_fuse_dxfer_en; | |
1266 | wire efu_spc1_fuse_dclr; | |
1267 | wire spc1_efu_fuse_dxfer_en; | |
1268 | wire spc1_efu_fuse_ixfer_en; | |
1269 | wire spc1_efu_fuse_ddata; | |
1270 | wire spc1_efu_fuse_idata; | |
1271 | wire gl_io_cmp_sync_en_c2t; | |
1272 | wire gl_cmp_io_sync_en_c2t; | |
1273 | wire tcu_spc1_test_mode; | |
1274 | wire cmp_gclk_c3_spc2; | |
1275 | wire gl_spc2_clk_stop; | |
1276 | wire [145:0] cpx_spc2_data_cx2; | |
1277 | wire [8:0] pcx_spc2_grant_px; | |
1278 | wire [8:0] spc2_pcx_req_pq; | |
1279 | wire [8:0] spc2_pcx_atm_pq; | |
1280 | wire [129:0] spc2_pcx_data_pa; | |
1281 | wire spc2_hardstop_request; | |
1282 | wire spc2_softstop_request; | |
1283 | wire spc2_trigger_pulse; | |
1284 | wire tcu_ss_request_t3lff_2; | |
1285 | wire spc2_ss_complete; | |
1286 | wire tcu_spc2_aclk; | |
1287 | wire tcu_spc2_bclk; | |
1288 | wire tcu_spc2_scan_en; | |
1289 | wire tcu_spc2_se_scancollar_in; | |
1290 | wire tcu_spc2_se_scancollar_out; | |
1291 | wire tcu_spc2_array_wr_inhibit; | |
1292 | wire [7:0] ncu_spc2_core_running; | |
1293 | wire [7:0] spc2_ncu_core_running_status; | |
1294 | wire [1:0] spc2_tcu_scan_in; | |
1295 | wire [1:0] tcu_spc2_scan_out; | |
1296 | wire tcu_spc_mbist_start_t3lff_2; | |
1297 | wire spc2_tcu_mbist_done; | |
1298 | wire spc2_tcu_mbist_fail; | |
1299 | wire tcu_spc2_mbist_scan_in; | |
1300 | wire spc2_tcu_mbist_scan_out; | |
1301 | wire [35:0] spc2_dmo_dout; | |
1302 | wire spc2_tcu_lbist_done; | |
1303 | wire spc2_tcu_lbist_scan_out; | |
1304 | wire tcu_spc2_shscan_scan_out; | |
1305 | wire spc2_tcu_shscan_scan_in; | |
1306 | wire tcu_spc2_shscan_clk_stop; | |
1307 | wire efu_spc2_fuse_ixfer_en; | |
1308 | wire efu_spc2_fuse_iclr; | |
1309 | wire efu_spc2_fuse_dxfer_en; | |
1310 | wire efu_spc2_fuse_dclr; | |
1311 | wire spc2_efu_fuse_dxfer_en; | |
1312 | wire spc2_efu_fuse_ixfer_en; | |
1313 | wire spc2_efu_fuse_ddata; | |
1314 | wire spc2_efu_fuse_idata; | |
1315 | wire gl_cmp_io_sync_en_c3b; | |
1316 | wire tcu_spc2_test_mode; | |
1317 | wire cmp_gclk_c2_spc3; | |
1318 | wire gl_spc3_clk_stop; | |
1319 | wire [145:0] cpx_spc3_data_cx2; | |
1320 | wire [8:0] pcx_spc3_grant_px; | |
1321 | wire [8:0] spc3_pcx_req_pq; | |
1322 | wire [8:0] spc3_pcx_atm_pq; | |
1323 | wire [129:0] spc3_pcx_data_pa; | |
1324 | wire spc3_hardstop_request; | |
1325 | wire spc3_softstop_request; | |
1326 | wire spc3_trigger_pulse; | |
1327 | wire spc3_ss_complete; | |
1328 | wire tcu_spc3_aclk; | |
1329 | wire tcu_spc3_bclk; | |
1330 | wire tcu_spc3_scan_en; | |
1331 | wire tcu_spc3_se_scancollar_in; | |
1332 | wire tcu_spc3_se_scancollar_out; | |
1333 | wire tcu_spc3_array_wr_inhibit; | |
1334 | wire [7:0] ncu_spc3_core_running; | |
1335 | wire [7:0] spc3_ncu_core_running_status; | |
1336 | wire [1:0] spc3_tcu_scan_in; | |
1337 | wire [1:0] tcu_spc3_scan_out; | |
1338 | wire spc3_tcu_mbist_done; | |
1339 | wire spc3_tcu_mbist_fail; | |
1340 | wire tcu_spc3_mbist_scan_in; | |
1341 | wire spc3_tcu_mbist_scan_out; | |
1342 | wire [35:0] spc3_dmo_dout; | |
1343 | wire spc3_tcu_lbist_done; | |
1344 | wire spc3_tcu_lbist_scan_out; | |
1345 | wire tcu_spc3_shscan_scan_out; | |
1346 | wire spc3_tcu_shscan_scan_in; | |
1347 | wire tcu_spc3_shscan_clk_stop; | |
1348 | wire efu_spc3_fuse_ixfer_en; | |
1349 | wire efu_spc3_fuse_iclr; | |
1350 | wire efu_spc3_fuse_dxfer_en; | |
1351 | wire efu_spc3_fuse_dclr; | |
1352 | wire spc3_efu_fuse_dxfer_en; | |
1353 | wire spc3_efu_fuse_ixfer_en; | |
1354 | wire spc3_efu_fuse_ddata; | |
1355 | wire spc3_efu_fuse_idata; | |
1356 | wire gl_io_cmp_sync_en_c2b; | |
1357 | wire gl_cmp_io_sync_en_c2b; | |
1358 | wire tcu_spc3_test_mode; | |
1359 | wire cmp_gclk_c1_spc4; | |
1360 | wire gl_spc4_clk_stop; | |
1361 | wire [145:0] cpx_spc4_data_cx2; | |
1362 | wire [8:0] pcx_spc4_grant_px; | |
1363 | wire [8:0] spc4_pcx_req_pq; | |
1364 | wire [8:0] spc4_pcx_atm_pq; | |
1365 | wire [129:0] spc4_pcx_data_pa; | |
1366 | wire spc4_hardstop_request; | |
1367 | wire spc4_softstop_request; | |
1368 | wire spc4_trigger_pulse; | |
1369 | wire spc4_ss_complete; | |
1370 | wire tcu_spc4_aclk; | |
1371 | wire tcu_spc4_bclk; | |
1372 | wire tcu_spc4_scan_en; | |
1373 | wire tcu_spc4_se_scancollar_in; | |
1374 | wire tcu_spc4_se_scancollar_out; | |
1375 | wire tcu_spc4_array_wr_inhibit; | |
1376 | wire [7:0] ncu_spc4_core_running; | |
1377 | wire [7:0] spc4_ncu_core_running_status; | |
1378 | wire [1:0] spc4_tcu_scan_in; | |
1379 | wire [1:0] tcu_spc4_scan_out; | |
1380 | wire spc4_tcu_mbist_done; | |
1381 | wire spc4_tcu_mbist_fail; | |
1382 | wire tcu_spc4_mbist_scan_in; | |
1383 | wire spc4_tcu_mbist_scan_out; | |
1384 | wire [35:0] spc5_dmo_dout; | |
1385 | wire [35:0] spc4_dmo_dout; | |
1386 | wire spc4_tcu_lbist_done; | |
1387 | wire spc4_tcu_lbist_scan_out; | |
1388 | wire tcu_spc4_shscan_scan_out; | |
1389 | wire spc4_tcu_shscan_scan_in; | |
1390 | wire tcu_spc4_shscan_clk_stop; | |
1391 | wire efu_spc4_fuse_ixfer_en; | |
1392 | wire efu_spc4_fuse_iclr; | |
1393 | wire efu_spc4_fuse_dxfer_en; | |
1394 | wire efu_spc4_fuse_dclr; | |
1395 | wire spc4_efu_fuse_dxfer_en; | |
1396 | wire spc4_efu_fuse_ixfer_en; | |
1397 | wire spc4_efu_fuse_ddata; | |
1398 | wire spc4_efu_fuse_idata; | |
1399 | wire gl_io_cmp_sync_en_c1t; | |
1400 | wire gl_cmp_io_sync_en_c1t; | |
1401 | wire tcu_spc4_test_mode; | |
1402 | wire cmp_gclk_c2_spc5; | |
1403 | wire gl_spc5_clk_stop; | |
1404 | wire [145:0] cpx_spc5_data_cx2; | |
1405 | wire [8:0] pcx_spc5_grant_px; | |
1406 | wire [8:0] spc5_pcx_req_pq; | |
1407 | wire [8:0] spc5_pcx_atm_pq; | |
1408 | wire [129:0] spc5_pcx_data_pa; | |
1409 | wire spc5_hardstop_request; | |
1410 | wire spc5_softstop_request; | |
1411 | wire spc5_trigger_pulse; | |
1412 | wire spc5_ss_complete; | |
1413 | wire tcu_spc5_aclk; | |
1414 | wire tcu_spc5_bclk; | |
1415 | wire tcu_spc5_scan_en; | |
1416 | wire tcu_spc5_se_scancollar_in; | |
1417 | wire tcu_spc5_se_scancollar_out; | |
1418 | wire tcu_spc5_array_wr_inhibit; | |
1419 | wire [7:0] ncu_spc5_core_running; | |
1420 | wire [7:0] spc5_ncu_core_running_status; | |
1421 | wire [1:0] spc5_tcu_scan_in; | |
1422 | wire [1:0] tcu_spc5_scan_out; | |
1423 | wire spc5_tcu_mbist_done; | |
1424 | wire spc5_tcu_mbist_fail; | |
1425 | wire tcu_spc5_mbist_scan_in; | |
1426 | wire spc5_tcu_mbist_scan_out; | |
1427 | wire spc5_tcu_lbist_done; | |
1428 | wire spc5_tcu_lbist_scan_out; | |
1429 | wire tcu_spc5_shscan_scan_out; | |
1430 | wire spc5_tcu_shscan_scan_in; | |
1431 | wire tcu_spc5_shscan_clk_stop; | |
1432 | wire efu_spc5_fuse_ixfer_en; | |
1433 | wire efu_spc5_fuse_iclr; | |
1434 | wire efu_spc5_fuse_dxfer_en; | |
1435 | wire efu_spc5_fuse_dclr; | |
1436 | wire spc5_efu_fuse_dxfer_en; | |
1437 | wire spc5_efu_fuse_ixfer_en; | |
1438 | wire spc5_efu_fuse_ddata; | |
1439 | wire spc5_efu_fuse_idata; | |
1440 | wire tcu_spc5_test_mode; | |
1441 | wire cmp_gclk_c1_spc6; | |
1442 | wire gl_spc6_clk_stop; | |
1443 | wire [145:0] cpx_spc6_data_cx2; | |
1444 | wire [8:0] pcx_spc6_grant_px; | |
1445 | wire [8:0] spc6_pcx_req_pq; | |
1446 | wire [8:0] spc6_pcx_atm_pq; | |
1447 | wire [129:0] spc6_pcx_data_pa; | |
1448 | wire spc6_hardstop_request; | |
1449 | wire spc6_softstop_request; | |
1450 | wire spc6_trigger_pulse; | |
1451 | wire spc6_ss_complete; | |
1452 | wire tcu_spc6_aclk; | |
1453 | wire tcu_spc6_bclk; | |
1454 | wire tcu_spc6_scan_en; | |
1455 | wire tcu_spc6_se_scancollar_in; | |
1456 | wire tcu_spc6_se_scancollar_out; | |
1457 | wire tcu_spc6_array_wr_inhibit; | |
1458 | wire [7:0] ncu_spc6_core_running; | |
1459 | wire [7:0] spc6_ncu_core_running_status; | |
1460 | wire [1:0] spc6_tcu_scan_in; | |
1461 | wire [1:0] tcu_spc6_scan_out; | |
1462 | wire spc6_tcu_mbist_done; | |
1463 | wire spc6_tcu_mbist_fail; | |
1464 | wire tcu_spc6_mbist_scan_in; | |
1465 | wire spc6_tcu_mbist_scan_out; | |
1466 | wire [35:0] spc7_dmo_dout; | |
1467 | wire [35:0] spc6_dmo_dout; | |
1468 | wire spc6_tcu_lbist_done; | |
1469 | wire spc6_tcu_lbist_scan_out; | |
1470 | wire tcu_spc6_shscan_scan_out; | |
1471 | wire spc6_tcu_shscan_scan_in; | |
1472 | wire tcu_spc6_shscan_clk_stop; | |
1473 | wire efu_spc6_fuse_ixfer_en; | |
1474 | wire efu_spc6_fuse_iclr; | |
1475 | wire efu_spc6_fuse_dxfer_en; | |
1476 | wire efu_spc6_fuse_dclr; | |
1477 | wire spc6_efu_fuse_dxfer_en; | |
1478 | wire spc6_efu_fuse_ixfer_en; | |
1479 | wire spc6_efu_fuse_ddata; | |
1480 | wire spc6_efu_fuse_idata; | |
1481 | wire gl_io_cmp_sync_en_c1b; | |
1482 | wire gl_cmp_io_sync_en_c1b; | |
1483 | wire tcu_spc6_test_mode; | |
1484 | wire cmp_gclk_c2_spc7; | |
1485 | wire gl_spc7_clk_stop; | |
1486 | wire [145:0] cpx_spc7_data_cx2; | |
1487 | wire [8:0] pcx_spc7_grant_px; | |
1488 | wire [8:0] spc7_pcx_req_pq; | |
1489 | wire [8:0] spc7_pcx_atm_pq; | |
1490 | wire [129:0] spc7_pcx_data_pa; | |
1491 | wire spc7_hardstop_request; | |
1492 | wire spc7_softstop_request; | |
1493 | wire spc7_trigger_pulse; | |
1494 | wire spc7_ss_complete; | |
1495 | wire tcu_spc7_aclk; | |
1496 | wire tcu_spc7_bclk; | |
1497 | wire tcu_spc7_scan_en; | |
1498 | wire tcu_spc7_se_scancollar_in; | |
1499 | wire tcu_spc7_se_scancollar_out; | |
1500 | wire tcu_spc7_array_wr_inhibit; | |
1501 | wire [7:0] ncu_spc7_core_running; | |
1502 | wire [7:0] spc7_ncu_core_running_status; | |
1503 | wire [1:0] spc7_tcu_scan_in; | |
1504 | wire [1:0] tcu_spc7_scan_out; | |
1505 | wire spc7_tcu_mbist_done; | |
1506 | wire spc7_tcu_mbist_fail; | |
1507 | wire tcu_spc7_mbist_scan_in; | |
1508 | wire spc7_tcu_mbist_scan_out; | |
1509 | wire spc7_tcu_lbist_done; | |
1510 | wire spc7_tcu_lbist_scan_out; | |
1511 | wire tcu_spc7_shscan_scan_out; | |
1512 | wire spc7_tcu_shscan_scan_in; | |
1513 | wire tcu_spc7_shscan_clk_stop; | |
1514 | wire efu_spc7_fuse_ixfer_en; | |
1515 | wire efu_spc7_fuse_iclr; | |
1516 | wire efu_spc7_fuse_dxfer_en; | |
1517 | wire efu_spc7_fuse_dclr; | |
1518 | wire spc7_efu_fuse_dxfer_en; | |
1519 | wire spc7_efu_fuse_ixfer_en; | |
1520 | wire spc7_efu_fuse_ddata; | |
1521 | wire spc7_efu_fuse_idata; | |
1522 | wire tcu_spc7_test_mode; | |
1523 | wire gl_ccx_clk_stop; | |
1524 | wire [1:0] tcu_ccx_scan_out; | |
1525 | wire [1:0] ccx_scan_out; | |
1526 | wire [7:0] ncu_cpx_req_cq; | |
1527 | wire [7:0] cpx_ncu_grant_cx; | |
1528 | wire [145:0] ncu_cpx_data_ca; | |
1529 | wire ncu_pcx_stall_pq; | |
1530 | wire [129:0] pcx_ncu_data_px2; | |
1531 | wire [145:0] sctag0_cpx_data_ca; | |
1532 | wire [145:0] sctag1_cpx_data_ca; | |
1533 | wire [145:0] sctag2_cpx_data_ca; | |
1534 | wire [145:0] sctag3_cpx_data_ca; | |
1535 | wire [145:0] sctag4_cpx_data_ca; | |
1536 | wire [145:0] sctag5_cpx_data_ca; | |
1537 | wire [145:0] sctag6_cpx_data_ca; | |
1538 | wire [145:0] sctag7_cpx_data_ca; | |
1539 | wire pcx_ncu_data_rdy_px1; | |
1540 | wire [31:0] l2b1_sio_data; | |
1541 | wire [1:0] l2b1_sio_parity; | |
1542 | wire l2b1_sio_ctag_vld; | |
1543 | wire l2b1_sio_ue_err; | |
1544 | wire [31:0] l2b2_sio_data; | |
1545 | wire [1:0] l2b2_sio_parity; | |
1546 | wire l2b2_sio_ctag_vld; | |
1547 | wire l2b2_sio_ue_err; | |
1548 | wire [31:0] l2b3_sio_data; | |
1549 | wire [1:0] l2b3_sio_parity; | |
1550 | wire l2b3_sio_ctag_vld; | |
1551 | wire l2b3_sio_ue_err; | |
1552 | wire l2b0_tcu_mbist_done; | |
1553 | wire l2b0_tcu_mbist_fail; | |
1554 | wire tcu_l2b0_mbist_start; | |
1555 | wire l2b1_tcu_mbist_done; | |
1556 | wire l2b1_tcu_mbist_fail; | |
1557 | wire tcu_l2b1_mbist_start; | |
1558 | wire l2b2_tcu_mbist_done; | |
1559 | wire l2b2_tcu_mbist_fail; | |
1560 | wire tcu_l2b2_mbist_start; | |
1561 | wire l2b3_tcu_mbist_done; | |
1562 | wire l2b3_tcu_mbist_fail; | |
1563 | wire tcu_l2b3_mbist_start; | |
1564 | wire [31:0] l2b1_sio_data_ccxlff; | |
1565 | wire [1:0] l2b1_sio_parity_ccxlff; | |
1566 | wire l2b1_sio_ctag_vld_ccxlff; | |
1567 | wire l2b1_sio_ue_err_ccxlff; | |
1568 | wire [31:0] l2b2_sio_data_ccxlff; | |
1569 | wire [1:0] l2b2_sio_parity_ccxlff; | |
1570 | wire l2b2_sio_ctag_vld_ccxlff; | |
1571 | wire l2b2_sio_ue_err_ccxlff; | |
1572 | wire [31:0] l2b3_sio_data_ccxlff; | |
1573 | wire [1:0] l2b3_sio_parity_ccxlff; | |
1574 | wire l2b3_sio_ctag_vld_ccxlff; | |
1575 | wire l2b3_sio_ue_err_ccxlff; | |
1576 | wire l2b0_tcu_mbist_done_ccxlff; | |
1577 | wire l2b0_tcu_mbist_fail_ccxlff; | |
1578 | wire tcu_l2b0_mbist_start_ccxlff; | |
1579 | wire l2b1_tcu_mbist_done_ccxlff; | |
1580 | wire l2b1_tcu_mbist_fail_ccxlff; | |
1581 | wire tcu_l2b1_mbist_start_ccxlff; | |
1582 | wire l2b2_tcu_mbist_done_ccxlff; | |
1583 | wire l2b2_tcu_mbist_fail_ccxlff; | |
1584 | wire tcu_l2b2_mbist_start_ccxlff; | |
1585 | wire l2b3_tcu_mbist_done_ccxlff; | |
1586 | wire l2b3_tcu_mbist_fail_ccxlff; | |
1587 | wire tcu_l2b3_mbist_start_ccxlff; | |
1588 | wire [6:0] sii_l2b5_ecc; | |
1589 | wire [1:0] sii_dbg1_l2t0_req; | |
1590 | wire [1:0] sii_dbg1_l2t1_req; | |
1591 | wire [1:0] sii_dbg1_l2t2_req; | |
1592 | wire [1:0] sii_dbg1_l2t3_req; | |
1593 | wire [1:0] sii_dbg1_l2t4_req; | |
1594 | wire [1:0] sii_dbg1_l2t5_req; | |
1595 | wire [1:0] sii_dbg1_l2t6_req; | |
1596 | wire [1:0] sii_dbg1_l2t7_req; | |
1597 | wire [1:0] sii_tcu_mbist_done; | |
1598 | wire [1:0] sii_tcu_mbist_fail; | |
1599 | wire [1:0] tcu_sii_mbist_start; | |
1600 | wire tcu_sii_data; | |
1601 | wire tcu_sii_vld; | |
1602 | wire [6:0] sii_l2b6_ecc; | |
1603 | wire [6:0] sii_l2b7_ecc; | |
1604 | wire [159:2] ccx_rstg_out_unconnected; | |
1605 | wire [6:0] sii_l2b5_ecc_ccxrff; | |
1606 | wire sii_tcu_mbist_done_ccxrff_1; | |
1607 | wire sii_tcu_mbist_done_ccxrff_0; | |
1608 | wire sii_tcu_mbist_fail_ccxrff_1; | |
1609 | wire sii_tcu_mbist_fail_ccxrff_0; | |
1610 | wire tcu_sii_mbist_start_ccxrff_1; | |
1611 | wire tcu_sii_mbist_start_ccxrff_0; | |
1612 | wire tcu_sii_data_ccxrff; | |
1613 | wire tcu_sii_vld_ccxrff; | |
1614 | wire [6:0] sii_l2b6_ecc_ccxrff; | |
1615 | wire [6:0] sii_l2b7_ecc_ccxrff; | |
1616 | wire [191:0] cpu_rep0_out_unconnected; | |
1617 | wire [191:0] cpu_rep1_out_unconnected; | |
1618 | wire cmp_gclk_c3_l2d0; | |
1619 | wire gl_l2d0_clk_stop; | |
1620 | wire [15:0] l2t0_l2d0_way_sel_c2; | |
1621 | wire [3:0] l2t0_l2d0_col_offset_c2; | |
1622 | wire l2t0_l2d0_fb_hit_c3; | |
1623 | wire l2t0_l2d0_fbrd_c3; | |
1624 | wire l2t0_l2d0_rd_wr_c2; | |
1625 | wire [8:0] l2t0_l2d0_set_c2; | |
1626 | wire [15:0] l2t0_l2d0_word_en_c2; | |
1627 | wire [77:0] l2t0_l2d0_stdecc_c2; | |
1628 | wire [623:0] l2b0_l2d0_fbdecc_c4; | |
1629 | wire gl_l2_por_c3t0; | |
1630 | wire gl_l2_wmr_c3t0; | |
1631 | wire tcu_se_scancollar_in; | |
1632 | wire tcu_se_scancollar_out; | |
1633 | wire tcu_array_wr_inhibit; | |
1634 | wire l2t1_scan_out; | |
1635 | wire [9:0] l2b0_l2d0_rvalue; | |
1636 | wire [6:0] l2b0_l2d0_rid; | |
1637 | wire l2b0_l2d0_wr_en; | |
1638 | wire l2b0_l2d0_fuse_clr; | |
1639 | wire [9:0] l2d0_l2b0_fuse_data; | |
1640 | wire l2d0_scan_out; | |
1641 | wire [623:0] l2d0_l2b0_decc_out_c7; | |
1642 | wire [155:0] l2d0_l2t0_decc_c6; | |
1643 | wire cmp_gclk_c3_l2d1; | |
1644 | wire gl_l2d1_clk_stop; | |
1645 | wire l2d1_scan_out; | |
1646 | wire [623:0] l2b1_l2d1_fbdecc_c4; | |
1647 | wire gl_l2_por_c3t; | |
1648 | wire gl_l2_wmr_c3t; | |
1649 | wire [3:0] l2t1_l2d1_col_offset_c2; | |
1650 | wire l2t1_l2d1_fb_hit_c3; | |
1651 | wire l2t1_l2d1_fbrd_c3; | |
1652 | wire l2t1_l2d1_rd_wr_c2; | |
1653 | wire [8:0] l2t1_l2d1_set_c2; | |
1654 | wire [77:0] l2t1_l2d1_stdecc_c2; | |
1655 | wire [15:0] l2t1_l2d1_way_sel_c2; | |
1656 | wire [15:0] l2t1_l2d1_word_en_c2; | |
1657 | wire [9:0] l2b1_l2d1_rvalue; | |
1658 | wire [6:0] l2b1_l2d1_rid; | |
1659 | wire l2b1_l2d1_wr_en; | |
1660 | wire l2b1_l2d1_fuse_clr; | |
1661 | wire [9:0] l2d1_l2b1_fuse_data; | |
1662 | wire [623:0] l2d1_l2b1_decc_out_c7; | |
1663 | wire [155:0] l2d1_l2t1_decc_c6; | |
1664 | wire cmp_gclk_c3_l2d2; | |
1665 | wire gl_l2d2_clk_stop; | |
1666 | wire l2t3_scan_out; | |
1667 | wire l2d2_scan_out; | |
1668 | wire [623:0] l2b2_l2d2_fbdecc_c4; | |
1669 | wire gl_l2_por_c3b0; | |
1670 | wire gl_l2_wmr_c3b; | |
1671 | wire [3:0] l2t2_l2d2_col_offset_c2; | |
1672 | wire l2t2_l2d2_fb_hit_c3; | |
1673 | wire l2t2_l2d2_fbrd_c3; | |
1674 | wire l2t2_l2d2_rd_wr_c2; | |
1675 | wire [8:0] l2t2_l2d2_set_c2; | |
1676 | wire [77:0] l2t2_l2d2_stdecc_c2; | |
1677 | wire [15:0] l2t2_l2d2_way_sel_c2; | |
1678 | wire [15:0] l2t2_l2d2_word_en_c2; | |
1679 | wire [623:0] l2d2_l2b2_decc_out_c7; | |
1680 | wire [155:0] l2d2_l2t2_decc_c6; | |
1681 | wire [9:0] l2b2_l2d2_rvalue; | |
1682 | wire [6:0] l2b2_l2d2_rid; | |
1683 | wire l2b2_l2d2_wr_en; | |
1684 | wire l2b2_l2d2_fuse_clr; | |
1685 | wire [9:0] l2d2_l2b2_fuse_data; | |
1686 | wire cmp_gclk_c3_l2d3; | |
1687 | wire gl_l2d3_clk_stop; | |
1688 | wire l2d3_scan_out; | |
1689 | wire [9:0] l2b3_l2d3_rvalue; | |
1690 | wire [6:0] l2b3_l2d3_rid; | |
1691 | wire l2b3_l2d3_wr_en; | |
1692 | wire l2b3_l2d3_fuse_clr; | |
1693 | wire [9:0] l2d3_l2b3_fuse_data; | |
1694 | wire [623:0] l2b3_l2d3_fbdecc_c4; | |
1695 | wire [3:0] l2t3_l2d3_col_offset_c2; | |
1696 | wire l2t3_l2d3_fb_hit_c3; | |
1697 | wire l2t3_l2d3_fbrd_c3; | |
1698 | wire l2t3_l2d3_rd_wr_c2; | |
1699 | wire [8:0] l2t3_l2d3_set_c2; | |
1700 | wire [77:0] l2t3_l2d3_stdecc_c2; | |
1701 | wire [15:0] l2t3_l2d3_way_sel_c2; | |
1702 | wire [15:0] l2t3_l2d3_word_en_c2; | |
1703 | wire [623:0] l2d3_l2b3_decc_out_c7; | |
1704 | wire [155:0] l2d3_l2t3_decc_c6; | |
1705 | wire cmp_gclk_c1_l2d4; | |
1706 | wire gl_l2d4_clk_stop; | |
1707 | wire l2t5_scan_out; | |
1708 | wire l2d4_scan_out; | |
1709 | wire [9:0] l2b4_l2d4_rvalue; | |
1710 | wire [6:0] l2b4_l2d4_rid; | |
1711 | wire l2b4_l2d4_wr_en; | |
1712 | wire l2b4_l2d4_fuse_clr; | |
1713 | wire [9:0] l2d4_l2b4_fuse_data; | |
1714 | wire [623:0] l2b4_l2d4_fbdecc_c4; | |
1715 | wire gl_l2_por_c1t; | |
1716 | wire gl_l2_wmr_c1t; | |
1717 | wire [3:0] l2t4_l2d4_col_offset_c2; | |
1718 | wire l2t4_l2d4_fb_hit_c3; | |
1719 | wire l2t4_l2d4_fbrd_c3; | |
1720 | wire l2t4_l2d4_rd_wr_c2; | |
1721 | wire [8:0] l2t4_l2d4_set_c2; | |
1722 | wire [77:0] l2t4_l2d4_stdecc_c2; | |
1723 | wire [15:0] l2t4_l2d4_way_sel_c2; | |
1724 | wire [15:0] l2t4_l2d4_word_en_c2; | |
1725 | wire [623:0] l2d4_l2b4_decc_out_c7; | |
1726 | wire [155:0] l2d4_l2t4_decc_c6; | |
1727 | wire cmp_gclk_c1_l2d5; | |
1728 | wire gl_l2d5_clk_stop; | |
1729 | wire l2d5_scan_out; | |
1730 | wire [623:0] l2b5_l2d5_fbdecc_c4; | |
1731 | wire [3:0] l2t5_l2d5_col_offset_c2; | |
1732 | wire l2t5_l2d5_fb_hit_c3; | |
1733 | wire l2t5_l2d5_fbrd_c3; | |
1734 | wire l2t5_l2d5_rd_wr_c2; | |
1735 | wire [8:0] l2t5_l2d5_set_c2; | |
1736 | wire [77:0] l2t5_l2d5_stdecc_c2; | |
1737 | wire [15:0] l2t5_l2d5_way_sel_c2; | |
1738 | wire [15:0] l2t5_l2d5_word_en_c2; | |
1739 | wire [9:0] l2b5_l2d5_rvalue; | |
1740 | wire [6:0] l2b5_l2d5_rid; | |
1741 | wire l2b5_l2d5_wr_en; | |
1742 | wire l2b5_l2d5_fuse_clr; | |
1743 | wire [9:0] l2d5_l2b5_fuse_data; | |
1744 | wire [623:0] l2d5_l2b5_decc_out_c7; | |
1745 | wire [155:0] l2d5_l2t5_decc_c6; | |
1746 | wire cmp_gclk_c1_l2d6; | |
1747 | wire gl_l2d6_clk_stop; | |
1748 | wire l2t7_scan_out; | |
1749 | wire l2d6_scan_out; | |
1750 | wire [9:0] l2b6_l2d6_rvalue; | |
1751 | wire [6:0] l2b6_l2d6_rid; | |
1752 | wire l2b6_l2d6_wr_en; | |
1753 | wire l2b6_l2d6_fuse_clr; | |
1754 | wire [9:0] l2d6_l2b6_fuse_data; | |
1755 | wire [623:0] l2b6_l2d6_fbdecc_c4; | |
1756 | wire gl_l2_por_c1b; | |
1757 | wire gl_l2_wmr_c1b; | |
1758 | wire [3:0] l2t6_l2d6_col_offset_c2; | |
1759 | wire l2t6_l2d6_fb_hit_c3; | |
1760 | wire l2t6_l2d6_fbrd_c3; | |
1761 | wire l2t6_l2d6_rd_wr_c2; | |
1762 | wire [8:0] l2t6_l2d6_set_c2; | |
1763 | wire [77:0] l2t6_l2d6_stdecc_c2; | |
1764 | wire [15:0] l2t6_l2d6_way_sel_c2; | |
1765 | wire [15:0] l2t6_l2d6_word_en_c2; | |
1766 | wire [623:0] l2d6_l2b6_decc_out_c7; | |
1767 | wire [155:0] l2d6_l2t6_decc_c6; | |
1768 | wire cmp_gclk_c1_l2d7; | |
1769 | wire gl_l2d7_clk_stop; | |
1770 | wire l2d7_scan_out; | |
1771 | wire [9:0] l2b7_l2d7_rvalue; | |
1772 | wire [6:0] l2b7_l2d7_rid; | |
1773 | wire l2b7_l2d7_wr_en; | |
1774 | wire l2b7_l2d7_fuse_clr; | |
1775 | wire [9:0] l2d7_l2b7_fuse_data; | |
1776 | wire [623:0] l2b7_l2d7_fbdecc_c4; | |
1777 | wire [3:0] l2t7_l2d7_col_offset_c2; | |
1778 | wire l2t7_l2d7_fb_hit_c3; | |
1779 | wire l2t7_l2d7_fbrd_c3; | |
1780 | wire l2t7_l2d7_rd_wr_c2; | |
1781 | wire [8:0] l2t7_l2d7_set_c2; | |
1782 | wire [77:0] l2t7_l2d7_stdecc_c2; | |
1783 | wire [15:0] l2t7_l2d7_way_sel_c2; | |
1784 | wire [15:0] l2t7_l2d7_word_en_c2; | |
1785 | wire [623:0] l2d7_l2b7_decc_out_c7; | |
1786 | wire [155:0] l2d7_l2t7_decc_c6; | |
1787 | wire l2t1_mcu0_rd_req; | |
1788 | wire l2t1_mcu0_rd_dummy_req; | |
1789 | wire [2:0] l2t1_mcu0_rd_req_id; | |
1790 | wire l2t1_mcu0_wr_req; | |
1791 | wire l2t1_mcu0_addr_5; | |
1792 | wire [39:7] l2t1_mcu0_addr; | |
1793 | wire l2t1_mcu0_rd_req_t0lff; | |
1794 | wire l2t1_mcu0_rd_dummy_req_t0lff; | |
1795 | wire [2:0] l2t1_mcu0_rd_req_id_t0lff; | |
1796 | wire l2t1_mcu0_wr_req_t0lff; | |
1797 | wire l2t1_mcu0_addr_5_t0lff; | |
1798 | wire [39:7] l2t1_mcu0_addr_t0lff; | |
1799 | wire [1:0] l2b0_sio_parity; | |
1800 | wire [1:0] l2b0_sio_parity_t0rff; | |
1801 | wire [38:0] l2t0_dmo_dout; | |
1802 | wire dmo_tagmuxctl; | |
1803 | wire gl_io_cmp_sync_en_c3t; | |
1804 | wire gl_cmp_io_sync_en_c3t; | |
1805 | wire [7:0] sctag0_cpx_req_cq; | |
1806 | wire sctag0_cpx_atom_cq; | |
1807 | wire sctag0_pcx_stall_pq; | |
1808 | wire pcx_sctag0_data_rdy_px1; | |
1809 | wire [129:0] pcx_sctag0_data_px2; | |
1810 | wire pcx_sctag0_atm_px1; | |
1811 | wire [7:0] cpx_sctag0_grant_cx; | |
1812 | wire l2t0_rst_fatal_error; | |
1813 | wire l2t0_l2b0_fbrd_en_c3; | |
1814 | wire [2:0] l2t0_l2b0_fbrd_wl_c3; | |
1815 | wire [15:0] l2t0_l2b0_fbwr_wen_r2; | |
1816 | wire [2:0] l2t0_l2b0_fbwr_wl_r2; | |
1817 | wire l2t0_l2b0_fbd_stdatasel_c3; | |
1818 | wire [3:0] l2t0_l2b0_wbwr_wen_c6; | |
1819 | wire [2:0] l2t0_l2b0_wbwr_wl_c6; | |
1820 | wire l2t0_l2b0_wbrd_en_r0; | |
1821 | wire [2:0] l2t0_l2b0_wbrd_wl_r0; | |
1822 | wire [2:0] l2t0_l2b0_ev_dword_r0; | |
1823 | wire l2t0_l2b0_evict_en_r0; | |
1824 | wire l2b0_l2t0_ev_uerr_r5; | |
1825 | wire l2b0_l2t0_ev_cerr_r5; | |
1826 | wire [15:0] l2t0_l2b0_rdma_wren_s2; | |
1827 | wire [1:0] l2t0_l2b0_rdma_wrwl_s2; | |
1828 | wire [1:0] l2t0_l2b0_rdma_rdwl_r0; | |
1829 | wire l2t0_l2b0_rdma_rden_r0; | |
1830 | wire l2t0_l2b0_ctag_en_c7; | |
1831 | wire [31:0] l2t0_l2b0_ctag_c7; | |
1832 | wire [3:0] l2t0_l2b0_word_c7; | |
1833 | wire l2t0_l2b0_req_en_c7; | |
1834 | wire l2t0_l2b0_word_vld_c7; | |
1835 | wire l2b0_l2t0_rdma_uerr_c10; | |
1836 | wire l2b0_l2t0_rdma_cerr_c10; | |
1837 | wire l2b0_l2t0_rdma_notdata_c10; | |
1838 | wire l2t0_mcu0_rd_req; | |
1839 | wire l2t0_mcu0_rd_dummy_req; | |
1840 | wire [2:0] l2t0_mcu0_rd_req_id; | |
1841 | wire [39:7] l2t0_mcu0_addr; | |
1842 | wire l2t0_mcu0_addr_5; | |
1843 | wire l2t0_mcu0_wr_req; | |
1844 | wire mcu0_l2t0_rd_ack; | |
1845 | wire mcu0_l2t0_wr_ack; | |
1846 | wire [1:0] mcu0_l2t0_qword_id_r0; | |
1847 | wire mcu0_l2t0_data_vld_r0; | |
1848 | wire [2:0] mcu0_l2t0_rd_req_id_r0; | |
1849 | wire mcu0_l2t0_secc_err_r2; | |
1850 | wire mcu0_l2t0_mecc_err_r2; | |
1851 | wire mcu0_l2t0_scb_mecc_err; | |
1852 | wire mcu0_l2t0_scb_secc_err; | |
1853 | wire sii_l2t0_req_vld; | |
1854 | wire [31:0] sii_l2t0_req; | |
1855 | wire [6:0] sii_l2b0_ecc; | |
1856 | wire l2t0_sii_iq_dequeue; | |
1857 | wire l2t0_sii_wib_dequeue; | |
1858 | wire tcu_soc0_scan_out; | |
1859 | wire l2t0_scan_out; | |
1860 | wire efu_l2t0_fuse_clr; | |
1861 | wire efu_l2t0_fuse_xfer_en; | |
1862 | wire efu_l2t0246_fuse_data; | |
1863 | wire l2t0_efu_fuse_data; | |
1864 | wire l2t0_efu_fuse_xfer_en; | |
1865 | wire tcu_l2t0_mbist_start_t1lff; | |
1866 | wire tcu_l2t0_mbist_scan_in; | |
1867 | wire l2t0_tcu_mbist_done; | |
1868 | wire l2t0_tcu_mbist_fail; | |
1869 | wire l2t0_tcu_mbist_scan_out; | |
1870 | wire cmp_gclk_c3_l2t0; | |
1871 | wire gl_l2t0_clk_stop; | |
1872 | wire tcu_l2t0_shscan_scan_in; | |
1873 | wire tcu_l2t_shscan_aclk; | |
1874 | wire tcu_l2t_shscan_bclk; | |
1875 | wire tcu_l2t_shscan_scan_en; | |
1876 | wire tcu_l2t_shscan_pce_ov; | |
1877 | wire l2t0_tcu_shscan_scan_out; | |
1878 | wire tcu_l2t0_shscan_clk_stop; | |
1879 | wire [23:0] l2t0_rep_out0_unused; | |
1880 | wire [23:0] l2t0_rep_out1_unused; | |
1881 | wire [23:0] l2t0_rep_out2_unused; | |
1882 | wire [23:0] l2t0_rep_out3_unused; | |
1883 | wire [23:0] l2t0_rep_out4_unused; | |
1884 | wire [23:0] l2t0_rep_out5_unused; | |
1885 | wire [23:0] l2t0_rep_out6_unused; | |
1886 | wire [23:0] l2t0_rep_out7_unused; | |
1887 | wire [23:0] l2t0_rep_out8_unused; | |
1888 | wire [23:0] l2t0_rep_out9_unused; | |
1889 | wire [23:0] l2t0_rep_out10_unused; | |
1890 | wire [23:0] l2t0_rep_out11_unused; | |
1891 | wire [23:0] l2t0_rep_out12_unused; | |
1892 | wire [23:0] l2t0_rep_out13_unused; | |
1893 | wire [23:0] l2t0_rep_out14_unused; | |
1894 | wire [23:0] l2t0_rep_out15_unused; | |
1895 | wire [23:0] l2t0_rep_out16_unused; | |
1896 | wire [23:0] l2t0_rep_out17_unused; | |
1897 | wire [23:0] l2t0_rep_out18_unused; | |
1898 | wire [23:0] l2t0_rep_out19_unused; | |
1899 | wire [1:0] tcu_ncu_mbist_start; | |
1900 | wire l2t4_sii_iq_dequeue; | |
1901 | wire l2t4_sii_wib_dequeue; | |
1902 | wire l2t5_sii_iq_dequeue; | |
1903 | wire l2t5_sii_wib_dequeue; | |
1904 | wire tcu_l2t0_mbist_start; | |
1905 | wire tcu_mcu0_mbist_start; | |
1906 | wire tcu_mcu1_mbist_start; | |
1907 | wire [31:0] l2b0_sio_data; | |
1908 | wire l2b0_sio_ctag_vld; | |
1909 | wire l2b0_sio_ue_err; | |
1910 | wire mcu0_l2t1_rd_ack; | |
1911 | wire mcu0_l2t1_wr_ack; | |
1912 | wire [1:0] mcu0_l2t1_qword_id_r0; | |
1913 | wire mcu0_l2t1_data_vld_r0; | |
1914 | wire [2:0] mcu0_l2t1_rd_req_id_r0; | |
1915 | wire mcu0_l2t1_secc_err_r2; | |
1916 | wire mcu0_l2t1_mecc_err_r2; | |
1917 | wire mcu0_l2t1_scb_mecc_err; | |
1918 | wire mcu0_l2t1_scb_secc_err; | |
1919 | wire tcu_ncu_mbist_start_t1lff_0; | |
1920 | wire l2t4_sii_iq_dequeue_t1lff; | |
1921 | wire l2t4_sii_wib_dequeue_t1lff; | |
1922 | wire l2t5_sii_iq_dequeue_t1lff; | |
1923 | wire l2t5_sii_wib_dequeue_t1lff; | |
1924 | wire tcu_mcu0_mbist_start_t1lff; | |
1925 | wire tcu_mcu1_mbist_start_t1lff; | |
1926 | wire [62:0] unconnectedt1lff_t1lff; | |
1927 | wire [31:0] l2b0_sio_data_t1rff; | |
1928 | wire l2b0_sio_ctag_vld_t1rff; | |
1929 | wire l2b0_sio_ue_err_t1rff; | |
1930 | wire mcu0_l2t1_rd_ack_t1rff; | |
1931 | wire mcu0_l2t1_wr_ack_t1rff; | |
1932 | wire [1:0] mcu0_l2t1_qword_id_r0_t1rff; | |
1933 | wire mcu0_l2t1_data_vld_r0_t1rff; | |
1934 | wire [2:0] mcu0_l2t1_rd_req_id_r0_t1rff; | |
1935 | wire mcu0_l2t1_secc_err_r2_t1rff; | |
1936 | wire mcu0_l2t1_mecc_err_r2_t1rff; | |
1937 | wire mcu0_l2t1_scb_mecc_err_t1rff; | |
1938 | wire mcu0_l2t1_scb_secc_err_t1rff; | |
1939 | wire [38:0] l2t1_dmo_dout; | |
1940 | wire [5:0] dmo_l2tsel; | |
1941 | wire [7:0] sctag1_cpx_req_cq; | |
1942 | wire sctag1_cpx_atom_cq; | |
1943 | wire sctag1_pcx_stall_pq; | |
1944 | wire pcx_sctag1_data_rdy_px1; | |
1945 | wire [129:0] pcx_sctag1_data_px2; | |
1946 | wire pcx_sctag1_atm_px1; | |
1947 | wire [7:0] cpx_sctag1_grant_cx; | |
1948 | wire l2t1_rst_fatal_error; | |
1949 | wire l2t1_l2b1_fbrd_en_c3; | |
1950 | wire [2:0] l2t1_l2b1_fbrd_wl_c3; | |
1951 | wire [15:0] l2t1_l2b1_fbwr_wen_r2; | |
1952 | wire [2:0] l2t1_l2b1_fbwr_wl_r2; | |
1953 | wire l2t1_l2b1_fbd_stdatasel_c3; | |
1954 | wire [3:0] l2t1_l2b1_wbwr_wen_c6; | |
1955 | wire [2:0] l2t1_l2b1_wbwr_wl_c6; | |
1956 | wire l2t1_l2b1_wbrd_en_r0; | |
1957 | wire [2:0] l2t1_l2b1_wbrd_wl_r0; | |
1958 | wire [2:0] l2t1_l2b1_ev_dword_r0; | |
1959 | wire l2t1_l2b1_evict_en_r0; | |
1960 | wire l2b1_l2t1_ev_uerr_r5; | |
1961 | wire l2b1_l2t1_ev_cerr_r5; | |
1962 | wire [15:0] l2t1_l2b1_rdma_wren_s2; | |
1963 | wire [1:0] l2t1_l2b1_rdma_wrwl_s2; | |
1964 | wire [1:0] l2t1_l2b1_rdma_rdwl_r0; | |
1965 | wire l2t1_l2b1_rdma_rden_r0; | |
1966 | wire l2t1_l2b1_ctag_en_c7; | |
1967 | wire [31:0] l2t1_l2b1_ctag_c7; | |
1968 | wire [3:0] l2t1_l2b1_word_c7; | |
1969 | wire l2t1_l2b1_req_en_c7; | |
1970 | wire l2t1_l2b1_word_vld_c7; | |
1971 | wire l2b1_l2t1_rdma_uerr_c10; | |
1972 | wire l2b1_l2t1_rdma_cerr_c10; | |
1973 | wire l2b1_l2t1_rdma_notdata_c10; | |
1974 | wire sii_l2t1_req_vld; | |
1975 | wire [31:0] sii_l2t1_req; | |
1976 | wire [6:0] sii_l2b1_ecc; | |
1977 | wire l2t1_sii_iq_dequeue; | |
1978 | wire l2t1_sii_wib_dequeue; | |
1979 | wire gl_l2_por_c2t; | |
1980 | wire gl_l2_wmr_c2t; | |
1981 | wire efu_l2t1_fuse_clr; | |
1982 | wire efu_l2t1_fuse_xfer_en; | |
1983 | wire efu_l2t1357_fuse_data; | |
1984 | wire l2t1_efu_fuse_data; | |
1985 | wire l2t1_efu_fuse_xfer_en; | |
1986 | wire tcu_l2t1_mbist_start; | |
1987 | wire tcu_l2t1_mbist_scan_in; | |
1988 | wire l2t1_tcu_mbist_done; | |
1989 | wire l2t1_tcu_mbist_fail; | |
1990 | wire l2t1_tcu_mbist_scan_out; | |
1991 | wire cmp_gclk_c2_l2t1; | |
1992 | wire gl_l2t1_clk_stop; | |
1993 | wire tcu_l2t1_shscan_scan_in; | |
1994 | wire l2t1_tcu_shscan_scan_out; | |
1995 | wire tcu_l2t1_shscan_clk_stop; | |
1996 | wire [23:0] l2t1_rep_out0_unused; | |
1997 | wire [23:0] l2t1_rep_out1_unused; | |
1998 | wire [23:0] l2t1_rep_out2_unused; | |
1999 | wire [23:0] l2t1_rep_out3_unused; | |
2000 | wire [23:0] l2t1_rep_out4_unused; | |
2001 | wire [23:0] l2t1_rep_out5_unused; | |
2002 | wire [23:0] l2t1_rep_out6_unused; | |
2003 | wire [23:0] l2t1_rep_out7_unused; | |
2004 | wire [23:0] l2t1_rep_out8_unused; | |
2005 | wire [23:0] l2t1_rep_out9_unused; | |
2006 | wire [23:0] l2t1_rep_out10_unused; | |
2007 | wire [23:0] l2t1_rep_out11_unused; | |
2008 | wire [23:0] l2t1_rep_out12_unused; | |
2009 | wire [23:0] l2t1_rep_out13_unused; | |
2010 | wire [23:0] l2t1_rep_out14_unused; | |
2011 | wire [23:0] l2t1_rep_out15_unused; | |
2012 | wire [23:0] l2t1_rep_out16_unused; | |
2013 | wire [23:0] l2t1_rep_out17_unused; | |
2014 | wire [23:0] l2t1_rep_out18_unused; | |
2015 | wire [23:0] l2t1_rep_out19_unused; | |
2016 | wire l2t3_mcu1_rd_req; | |
2017 | wire l2t3_mcu1_rd_dummy_req; | |
2018 | wire [2:0] l2t3_mcu1_rd_req_id; | |
2019 | wire l2t3_mcu1_wr_req; | |
2020 | wire l2t3_mcu1_addr_5; | |
2021 | wire [39:7] l2t3_mcu1_addr; | |
2022 | wire l2t3_mcu1_rd_req_t2lff; | |
2023 | wire l2t3_mcu1_rd_dummy_req_t2lff; | |
2024 | wire [2:0] l2t3_mcu1_rd_req_id_t2lff; | |
2025 | wire l2t3_mcu1_wr_req_t2lff; | |
2026 | wire l2t3_mcu1_addr_5_t2lff; | |
2027 | wire [39:7] l2t3_mcu1_addr_t2lff; | |
2028 | wire [38:0] l2t2_dmo_dout; | |
2029 | wire [7:0] sctag2_cpx_req_cq; | |
2030 | wire sctag2_cpx_atom_cq; | |
2031 | wire sctag2_pcx_stall_pq; | |
2032 | wire pcx_sctag2_data_rdy_px1; | |
2033 | wire [129:0] pcx_sctag2_data_px2; | |
2034 | wire pcx_sctag2_atm_px1; | |
2035 | wire [7:0] cpx_sctag2_grant_cx; | |
2036 | wire l2t2_rst_fatal_error; | |
2037 | wire l2t2_l2b2_fbrd_en_c3; | |
2038 | wire [2:0] l2t2_l2b2_fbrd_wl_c3; | |
2039 | wire [15:0] l2t2_l2b2_fbwr_wen_r2; | |
2040 | wire [2:0] l2t2_l2b2_fbwr_wl_r2; | |
2041 | wire l2t2_l2b2_fbd_stdatasel_c3; | |
2042 | wire [3:0] l2t2_l2b2_wbwr_wen_c6; | |
2043 | wire [2:0] l2t2_l2b2_wbwr_wl_c6; | |
2044 | wire l2t2_l2b2_wbrd_en_r0; | |
2045 | wire [2:0] l2t2_l2b2_wbrd_wl_r0; | |
2046 | wire [2:0] l2t2_l2b2_ev_dword_r0; | |
2047 | wire l2t2_l2b2_evict_en_r0; | |
2048 | wire l2b2_l2t2_ev_uerr_r5; | |
2049 | wire l2b2_l2t2_ev_cerr_r5; | |
2050 | wire [15:0] l2t2_l2b2_rdma_wren_s2; | |
2051 | wire [1:0] l2t2_l2b2_rdma_wrwl_s2; | |
2052 | wire [1:0] l2t2_l2b2_rdma_rdwl_r0; | |
2053 | wire l2t2_l2b2_rdma_rden_r0; | |
2054 | wire l2t2_l2b2_ctag_en_c7; | |
2055 | wire [31:0] l2t2_l2b2_ctag_c7; | |
2056 | wire [3:0] l2t2_l2b2_word_c7; | |
2057 | wire l2t2_l2b2_req_en_c7; | |
2058 | wire l2t2_l2b2_word_vld_c7; | |
2059 | wire l2b2_l2t2_rdma_uerr_c10; | |
2060 | wire l2b2_l2t2_rdma_cerr_c10; | |
2061 | wire l2b2_l2t2_rdma_notdata_c10; | |
2062 | wire l2t2_mcu1_rd_req; | |
2063 | wire l2t2_mcu1_rd_dummy_req; | |
2064 | wire [2:0] l2t2_mcu1_rd_req_id; | |
2065 | wire [39:7] l2t2_mcu1_addr; | |
2066 | wire l2t2_mcu1_addr_5; | |
2067 | wire l2t2_mcu1_wr_req; | |
2068 | wire mcu1_l2t2_rd_ack; | |
2069 | wire mcu1_l2t2_wr_ack; | |
2070 | wire [1:0] mcu1_l2t2_qword_id_r0; | |
2071 | wire mcu1_l2t2_data_vld_r0; | |
2072 | wire [2:0] mcu1_l2t2_rd_req_id_r0; | |
2073 | wire mcu1_l2t2_secc_err_r2; | |
2074 | wire mcu1_l2t2_mecc_err_r2; | |
2075 | wire mcu1_l2t2_scb_mecc_err; | |
2076 | wire mcu1_l2t2_scb_secc_err; | |
2077 | wire sii_l2t2_req_vld; | |
2078 | wire [31:0] sii_l2t2_req; | |
2079 | wire [6:0] sii_l2b2_ecc; | |
2080 | wire l2t2_sii_iq_dequeue; | |
2081 | wire l2t2_sii_wib_dequeue; | |
2082 | wire tcu_soc1_scan_out; | |
2083 | wire l2t2_scan_out; | |
2084 | wire tcu_l2t2_mbist_start_t3lff; | |
2085 | wire tcu_l2t2_mbist_scan_in; | |
2086 | wire l2t2_tcu_mbist_done; | |
2087 | wire l2t2_tcu_mbist_fail; | |
2088 | wire l2t2_tcu_mbist_scan_out; | |
2089 | wire efu_l2t2_fuse_clr; | |
2090 | wire efu_l2t2_fuse_xfer_en; | |
2091 | wire l2t2_efu_fuse_data; | |
2092 | wire l2t2_efu_fuse_xfer_en; | |
2093 | wire cmp_gclk_c3_l2t2; | |
2094 | wire gl_l2t2_clk_stop; | |
2095 | wire tcu_l2t2_shscan_scan_in; | |
2096 | wire l2t2_tcu_shscan_scan_out; | |
2097 | wire tcu_l2t2_shscan_clk_stop; | |
2098 | wire [23:0] l2t2_rep_out0_unused; | |
2099 | wire [23:0] l2t2_rep_out1_unused; | |
2100 | wire [23:0] l2t2_rep_out2_unused; | |
2101 | wire [23:0] l2t2_rep_out3_unused; | |
2102 | wire [23:0] l2t2_rep_out4_unused; | |
2103 | wire [23:0] l2t2_rep_out5_unused; | |
2104 | wire [23:0] l2t2_rep_out6_unused; | |
2105 | wire [23:0] l2t2_rep_out7_unused; | |
2106 | wire [23:0] l2t2_rep_out8_unused; | |
2107 | wire [23:0] l2t2_rep_out9_unused; | |
2108 | wire [23:0] l2t2_rep_out10_unused; | |
2109 | wire [23:0] l2t2_rep_out11_unused; | |
2110 | wire [23:0] l2t2_rep_out12_unused; | |
2111 | wire [23:0] l2t2_rep_out13_unused; | |
2112 | wire [23:0] l2t2_rep_out14_unused; | |
2113 | wire [23:0] l2t2_rep_out15_unused; | |
2114 | wire [23:0] l2t2_rep_out16_unused; | |
2115 | wire [23:0] l2t2_rep_out17_unused; | |
2116 | wire [23:0] l2t2_rep_out18_unused; | |
2117 | wire [23:0] l2t2_rep_out19_unused; | |
2118 | wire l2t6_sii_iq_dequeue; | |
2119 | wire l2t6_sii_wib_dequeue; | |
2120 | wire l2t7_sii_iq_dequeue; | |
2121 | wire l2t7_sii_wib_dequeue; | |
2122 | wire tcu_l2t2_mbist_start; | |
2123 | wire mcu1_l2t3_rd_ack; | |
2124 | wire mcu1_l2t3_wr_ack; | |
2125 | wire [1:0] mcu1_l2t3_qword_id_r0; | |
2126 | wire mcu1_l2t3_data_vld_r0; | |
2127 | wire [2:0] mcu1_l2t3_rd_req_id_r0; | |
2128 | wire mcu1_l2t3_secc_err_r2; | |
2129 | wire mcu1_l2t3_mecc_err_r2; | |
2130 | wire mcu1_l2t3_scb_mecc_err; | |
2131 | wire mcu1_l2t3_scb_secc_err; | |
2132 | wire l2t6_sii_iq_dequeue_t3lff; | |
2133 | wire l2t6_sii_wib_dequeue_t3lff; | |
2134 | wire l2t7_sii_iq_dequeue_t3lff; | |
2135 | wire l2t7_sii_wib_dequeue_t3lff; | |
2136 | wire mcu1_l2t3_rd_ack_t3rff; | |
2137 | wire mcu1_l2t3_wr_ack_t3rff; | |
2138 | wire [1:0] mcu1_l2t3_qword_id_r0_t3rff; | |
2139 | wire mcu1_l2t3_data_vld_r0_t3rff; | |
2140 | wire [2:0] mcu1_l2t3_rd_req_id_r0_t3rff; | |
2141 | wire mcu1_l2t3_secc_err_r2_t3rff; | |
2142 | wire mcu1_l2t3_mecc_err_r2_t3rff; | |
2143 | wire mcu1_l2t3_scb_mecc_err_t3rff; | |
2144 | wire mcu1_l2t3_scb_secc_err_t3rff; | |
2145 | wire [38:0] l2t3_dmo_dout; | |
2146 | wire [7:0] sctag3_cpx_req_cq; | |
2147 | wire sctag3_cpx_atom_cq; | |
2148 | wire sctag3_pcx_stall_pq; | |
2149 | wire pcx_sctag3_data_rdy_px1; | |
2150 | wire [129:0] pcx_sctag3_data_px2; | |
2151 | wire pcx_sctag3_atm_px1; | |
2152 | wire [7:0] cpx_sctag3_grant_cx; | |
2153 | wire l2t3_rst_fatal_error; | |
2154 | wire l2t3_l2b3_fbrd_en_c3; | |
2155 | wire [2:0] l2t3_l2b3_fbrd_wl_c3; | |
2156 | wire [15:0] l2t3_l2b3_fbwr_wen_r2; | |
2157 | wire [2:0] l2t3_l2b3_fbwr_wl_r2; | |
2158 | wire l2t3_l2b3_fbd_stdatasel_c3; | |
2159 | wire [3:0] l2t3_l2b3_wbwr_wen_c6; | |
2160 | wire [2:0] l2t3_l2b3_wbwr_wl_c6; | |
2161 | wire l2t3_l2b3_wbrd_en_r0; | |
2162 | wire [2:0] l2t3_l2b3_wbrd_wl_r0; | |
2163 | wire [2:0] l2t3_l2b3_ev_dword_r0; | |
2164 | wire l2t3_l2b3_evict_en_r0; | |
2165 | wire l2b3_l2t3_ev_uerr_r5; | |
2166 | wire l2b3_l2t3_ev_cerr_r5; | |
2167 | wire [15:0] l2t3_l2b3_rdma_wren_s2; | |
2168 | wire [1:0] l2t3_l2b3_rdma_wrwl_s2; | |
2169 | wire [1:0] l2t3_l2b3_rdma_rdwl_r0; | |
2170 | wire l2t3_l2b3_rdma_rden_r0; | |
2171 | wire l2t3_l2b3_ctag_en_c7; | |
2172 | wire [31:0] l2t3_l2b3_ctag_c7; | |
2173 | wire [3:0] l2t3_l2b3_word_c7; | |
2174 | wire l2t3_l2b3_req_en_c7; | |
2175 | wire l2t3_l2b3_word_vld_c7; | |
2176 | wire l2b3_l2t3_rdma_uerr_c10; | |
2177 | wire l2b3_l2t3_rdma_cerr_c10; | |
2178 | wire l2b3_l2t3_rdma_notdata_c10; | |
2179 | wire sii_l2t3_req_vld; | |
2180 | wire [31:0] sii_l2t3_req; | |
2181 | wire [6:0] sii_l2b3_ecc; | |
2182 | wire l2t3_sii_iq_dequeue; | |
2183 | wire l2t3_sii_wib_dequeue; | |
2184 | wire gl_l2_por_c2b; | |
2185 | wire gl_l2_wmr_c2b; | |
2186 | wire tcu_l2t3_mbist_start; | |
2187 | wire tcu_l2t3_mbist_scan_in; | |
2188 | wire l2t3_tcu_mbist_done; | |
2189 | wire l2t3_tcu_mbist_fail; | |
2190 | wire l2t3_tcu_mbist_scan_out; | |
2191 | wire efu_l2t3_fuse_clr; | |
2192 | wire efu_l2t3_fuse_xfer_en; | |
2193 | wire l2t3_efu_fuse_data; | |
2194 | wire l2t3_efu_fuse_xfer_en; | |
2195 | wire cmp_gclk_c2_l2t3; | |
2196 | wire gl_l2t3_clk_stop; | |
2197 | wire tcu_l2t3_shscan_scan_in; | |
2198 | wire l2t3_tcu_shscan_scan_out; | |
2199 | wire tcu_l2t3_shscan_clk_stop; | |
2200 | wire [23:0] l2t3_rep_out0_unused; | |
2201 | wire [23:0] l2t3_rep_out1_unused; | |
2202 | wire [23:0] l2t3_rep_out2_unused; | |
2203 | wire [23:0] l2t3_rep_out3_unused; | |
2204 | wire [23:0] l2t3_rep_out4_unused; | |
2205 | wire [23:0] l2t3_rep_out5_unused; | |
2206 | wire [23:0] l2t3_rep_out6_unused; | |
2207 | wire [23:0] l2t3_rep_out7_unused; | |
2208 | wire [23:0] l2t3_rep_out8_unused; | |
2209 | wire [23:0] l2t3_rep_out9_unused; | |
2210 | wire [23:0] l2t3_rep_out10_unused; | |
2211 | wire [23:0] l2t3_rep_out11_unused; | |
2212 | wire [23:0] l2t3_rep_out12_unused; | |
2213 | wire [23:0] l2t3_rep_out13_unused; | |
2214 | wire [23:0] l2t3_rep_out14_unused; | |
2215 | wire [23:0] l2t3_rep_out15_unused; | |
2216 | wire [23:0] l2t3_rep_out16_unused; | |
2217 | wire [23:0] l2t3_rep_out17_unused; | |
2218 | wire [23:0] l2t3_rep_out18_unused; | |
2219 | wire [23:0] l2t3_rep_out19_unused; | |
2220 | wire [31:0] sii_l2t4_req; | |
2221 | wire sii_l2t4_req_vld; | |
2222 | wire [31:0] sii_l2t5_req; | |
2223 | wire sii_l2t5_req_vld; | |
2224 | wire [6:0] sii_l2b4_ecc; | |
2225 | wire l2t5_mcu2_rd_req; | |
2226 | wire l2t5_mcu2_rd_dummy_req; | |
2227 | wire [2:0] l2t5_mcu2_rd_req_id; | |
2228 | wire l2t5_mcu2_wr_req; | |
2229 | wire l2t5_mcu2_addr_5; | |
2230 | wire [39:7] l2t5_mcu2_addr; | |
2231 | wire [31:0] l2b4_sio_data; | |
2232 | wire [1:0] l2b4_sio_parity; | |
2233 | wire l2b4_sio_ctag_vld; | |
2234 | wire l2b4_sio_ue_err; | |
2235 | wire [31:0] sii_l2t4_req_t4lff; | |
2236 | wire sii_l2t4_req_vld_t4lff; | |
2237 | wire [31:0] sii_l2t5_req_t4lff; | |
2238 | wire sii_l2t5_req_vld_t4lff; | |
2239 | wire [6:0] sii_l2b4_ecc_t4lff; | |
2240 | wire [31:0] l2b0_sio_data_t4lff; | |
2241 | wire l2b0_sio_ctag_vld_t4lff; | |
2242 | wire l2b0_sio_ue_err_t4lff; | |
2243 | wire l2t5_mcu2_rd_req_t4lff; | |
2244 | wire l2t5_mcu2_rd_dummy_req_t4lff; | |
2245 | wire [2:0] l2t5_mcu2_rd_req_id_t4lff; | |
2246 | wire l2t5_mcu2_wr_req_t4lff; | |
2247 | wire l2t5_mcu2_addr_5_t4lff; | |
2248 | wire [39:7] l2t5_mcu2_addr_t4lff; | |
2249 | wire [31:0] l2b4_sio_data_t4rff; | |
2250 | wire [1:0] l2b4_sio_parity_t4rff; | |
2251 | wire l2b4_sio_ctag_vld_t4rff; | |
2252 | wire l2b4_sio_ue_err_t4rff; | |
2253 | wire [38:0] l2t5_dmo_dout; | |
2254 | wire [38:0] l2t4_dmo_dout; | |
2255 | wire [7:0] sctag4_cpx_req_cq; | |
2256 | wire sctag4_cpx_atom_cq; | |
2257 | wire sctag4_pcx_stall_pq; | |
2258 | wire pcx_sctag4_data_rdy_px1; | |
2259 | wire [129:0] pcx_sctag4_data_px2; | |
2260 | wire pcx_sctag4_atm_px1; | |
2261 | wire [7:0] cpx_sctag4_grant_cx; | |
2262 | wire l2t4_rst_fatal_error; | |
2263 | wire l2t4_l2b4_fbrd_en_c3; | |
2264 | wire [2:0] l2t4_l2b4_fbrd_wl_c3; | |
2265 | wire [15:0] l2t4_l2b4_fbwr_wen_r2; | |
2266 | wire [2:0] l2t4_l2b4_fbwr_wl_r2; | |
2267 | wire l2t4_l2b4_fbd_stdatasel_c3; | |
2268 | wire [3:0] l2t4_l2b4_wbwr_wen_c6; | |
2269 | wire [2:0] l2t4_l2b4_wbwr_wl_c6; | |
2270 | wire l2t4_l2b4_wbrd_en_r0; | |
2271 | wire [2:0] l2t4_l2b4_wbrd_wl_r0; | |
2272 | wire [2:0] l2t4_l2b4_ev_dword_r0; | |
2273 | wire l2t4_l2b4_evict_en_r0; | |
2274 | wire l2b4_l2t4_ev_uerr_r5; | |
2275 | wire l2b4_l2t4_ev_cerr_r5; | |
2276 | wire [15:0] l2t4_l2b4_rdma_wren_s2; | |
2277 | wire [1:0] l2t4_l2b4_rdma_wrwl_s2; | |
2278 | wire [1:0] l2t4_l2b4_rdma_rdwl_r0; | |
2279 | wire l2t4_l2b4_rdma_rden_r0; | |
2280 | wire l2t4_l2b4_ctag_en_c7; | |
2281 | wire [31:0] l2t4_l2b4_ctag_c7; | |
2282 | wire [3:0] l2t4_l2b4_word_c7; | |
2283 | wire l2t4_l2b4_req_en_c7; | |
2284 | wire l2t4_l2b4_word_vld_c7; | |
2285 | wire l2b4_l2t4_rdma_uerr_c10; | |
2286 | wire l2b4_l2t4_rdma_cerr_c10; | |
2287 | wire l2b4_l2t4_rdma_notdata_c10; | |
2288 | wire l2t4_mcu2_rd_req; | |
2289 | wire l2t4_mcu2_rd_dummy_req; | |
2290 | wire [2:0] l2t4_mcu2_rd_req_id; | |
2291 | wire [39:7] l2t4_mcu2_addr; | |
2292 | wire l2t4_mcu2_addr_5; | |
2293 | wire l2t4_mcu2_wr_req; | |
2294 | wire mcu2_l2t4_rd_ack; | |
2295 | wire mcu2_l2t4_wr_ack; | |
2296 | wire [1:0] mcu2_l2t4_qword_id_r0; | |
2297 | wire mcu2_l2t4_data_vld_r0; | |
2298 | wire [2:0] mcu2_l2t4_rd_req_id_r0; | |
2299 | wire mcu2_l2t4_secc_err_r2; | |
2300 | wire mcu2_l2t4_mecc_err_r2; | |
2301 | wire mcu2_l2t4_scb_mecc_err; | |
2302 | wire mcu2_l2t4_scb_secc_err; | |
2303 | wire gl_rst_l2_por_c1m; | |
2304 | wire gl_rst_l2_wmr_c1m; | |
2305 | wire tcu_soc2_scan_out; | |
2306 | wire l2t4_scan_out; | |
2307 | wire tcu_l2t4_mbist_start; | |
2308 | wire tcu_l2t4_mbist_scan_in; | |
2309 | wire l2t4_tcu_mbist_done; | |
2310 | wire l2t4_tcu_mbist_fail; | |
2311 | wire l2t4_tcu_mbist_scan_out; | |
2312 | wire efu_l2t4_fuse_clr; | |
2313 | wire efu_l2t4_fuse_xfer_en; | |
2314 | wire l2t4_efu_fuse_data; | |
2315 | wire l2t4_efu_fuse_xfer_en; | |
2316 | wire cmp_gclk_c1_l2t4; | |
2317 | wire gl_l2t4_clk_stop; | |
2318 | wire tcu_l2t4_shscan_scan_in; | |
2319 | wire l2t4_tcu_shscan_scan_out; | |
2320 | wire tcu_l2t4_shscan_clk_stop; | |
2321 | wire [23:0] l2t4_rep_out0_unused; | |
2322 | wire [23:0] l2t4_rep_out1_unused; | |
2323 | wire [23:0] l2t4_rep_out2_unused; | |
2324 | wire [23:0] l2t4_rep_out3_unused; | |
2325 | wire [23:0] l2t4_rep_out4_unused; | |
2326 | wire [23:0] l2t4_rep_out5_unused; | |
2327 | wire [23:0] l2t4_rep_out6_unused; | |
2328 | wire [23:0] l2t4_rep_out7_unused; | |
2329 | wire [23:0] l2t4_rep_out8_unused; | |
2330 | wire [23:0] l2t4_rep_out9_unused; | |
2331 | wire [23:0] l2t4_rep_out10_unused; | |
2332 | wire [23:0] l2t4_rep_out11_unused; | |
2333 | wire [23:0] l2t4_rep_out12_unused; | |
2334 | wire [23:0] l2t4_rep_out13_unused; | |
2335 | wire [23:0] l2t4_rep_out14_unused; | |
2336 | wire [23:0] l2t4_rep_out15_unused; | |
2337 | wire [23:0] l2t4_rep_out16_unused; | |
2338 | wire [23:0] l2t4_rep_out17_unused; | |
2339 | wire [23:0] l2t4_rep_out18_unused; | |
2340 | wire [23:0] l2t4_rep_out19_unused; | |
2341 | wire mcu1_tcu_mbist_fail; | |
2342 | wire [1:0] ncu_tcu_mbist_done; | |
2343 | wire [1:0] ncu_tcu_mbist_fail; | |
2344 | wire mcu0_tcu_mbist_done; | |
2345 | wire mcu0_tcu_mbist_fail; | |
2346 | wire mcu1_tcu_mbist_done; | |
2347 | wire mcu2_l2t5_rd_ack; | |
2348 | wire mcu2_l2t5_wr_ack; | |
2349 | wire [1:0] mcu2_l2t5_qword_id_r0; | |
2350 | wire mcu2_l2t5_data_vld_r0; | |
2351 | wire [2:0] mcu2_l2t5_rd_req_id_r0; | |
2352 | wire mcu2_l2t5_secc_err_r2; | |
2353 | wire mcu2_l2t5_mecc_err_r2; | |
2354 | wire mcu2_l2t5_scb_mecc_err; | |
2355 | wire mcu2_l2t5_scb_secc_err; | |
2356 | wire mcu1_tcu_mbist_fail_t5lff; | |
2357 | wire ncu_tcu_mbist_done_t5lff_0; | |
2358 | wire ncu_tcu_mbist_fail_t5lff_0; | |
2359 | wire [1:0] l2b0_sio_parity_t5lff; | |
2360 | wire l2t0_tcu_mbist_done_t5lff; | |
2361 | wire l2t0_tcu_mbist_fail_t5lff; | |
2362 | wire spc0_tcu_mbist_done_t5lff; | |
2363 | wire spc0_tcu_mbist_fail_t5lff; | |
2364 | wire mcu0_tcu_mbist_done_t5lff; | |
2365 | wire mcu0_tcu_mbist_fail_t5lff; | |
2366 | wire mcu1_tcu_mbist_done_t5lff; | |
2367 | wire spc0_softstop_request_t5lff; | |
2368 | wire spc0_hardstop_request_t5lff; | |
2369 | wire spc0_trigger_pulse_t5lff; | |
2370 | wire spc0_ss_complete_t5lff; | |
2371 | wire mcu2_l2t5_rd_ack_t5rff; | |
2372 | wire mcu2_l2t5_wr_ack_t5rff; | |
2373 | wire [1:0] mcu2_l2t5_qword_id_r0_t5rff; | |
2374 | wire mcu2_l2t5_data_vld_r0_t5rff; | |
2375 | wire [2:0] mcu2_l2t5_rd_req_id_r0_t5rff; | |
2376 | wire mcu2_l2t5_secc_err_r2_t5rff; | |
2377 | wire mcu2_l2t5_mecc_err_r2_t5rff; | |
2378 | wire mcu2_l2t5_scb_mecc_err_t5rff; | |
2379 | wire mcu2_l2t5_scb_secc_err_t5rff; | |
2380 | wire l2t5_dbg1_err_event; | |
2381 | wire [7:0] sctag5_cpx_req_cq; | |
2382 | wire sctag5_cpx_atom_cq; | |
2383 | wire sctag5_pcx_stall_pq; | |
2384 | wire pcx_sctag5_data_rdy_px1; | |
2385 | wire [129:0] pcx_sctag5_data_px2; | |
2386 | wire pcx_sctag5_atm_px1; | |
2387 | wire [7:0] cpx_sctag5_grant_cx; | |
2388 | wire l2t5_rst_fatal_error; | |
2389 | wire l2t5_l2b5_fbrd_en_c3; | |
2390 | wire [2:0] l2t5_l2b5_fbrd_wl_c3; | |
2391 | wire [15:0] l2t5_l2b5_fbwr_wen_r2; | |
2392 | wire [2:0] l2t5_l2b5_fbwr_wl_r2; | |
2393 | wire l2t5_l2b5_fbd_stdatasel_c3; | |
2394 | wire [3:0] l2t5_l2b5_wbwr_wen_c6; | |
2395 | wire [2:0] l2t5_l2b5_wbwr_wl_c6; | |
2396 | wire l2t5_l2b5_wbrd_en_r0; | |
2397 | wire [2:0] l2t5_l2b5_wbrd_wl_r0; | |
2398 | wire [2:0] l2t5_l2b5_ev_dword_r0; | |
2399 | wire l2t5_l2b5_evict_en_r0; | |
2400 | wire l2b5_l2t5_ev_uerr_r5; | |
2401 | wire l2b5_l2t5_ev_cerr_r5; | |
2402 | wire [15:0] l2t5_l2b5_rdma_wren_s2; | |
2403 | wire [1:0] l2t5_l2b5_rdma_wrwl_s2; | |
2404 | wire [1:0] l2t5_l2b5_rdma_rdwl_r0; | |
2405 | wire l2t5_l2b5_rdma_rden_r0; | |
2406 | wire l2t5_l2b5_ctag_en_c7; | |
2407 | wire [31:0] l2t5_l2b5_ctag_c7; | |
2408 | wire [3:0] l2t5_l2b5_word_c7; | |
2409 | wire l2t5_l2b5_req_en_c7; | |
2410 | wire l2t5_l2b5_word_vld_c7; | |
2411 | wire l2b5_l2t5_rdma_uerr_c10; | |
2412 | wire l2b5_l2t5_rdma_cerr_c10; | |
2413 | wire l2b5_l2t5_rdma_notdata_c10; | |
2414 | wire tcu_l2t5_mbist_start; | |
2415 | wire tcu_l2t5_mbist_scan_in; | |
2416 | wire l2t5_tcu_mbist_done; | |
2417 | wire l2t5_tcu_mbist_fail; | |
2418 | wire l2t5_tcu_mbist_scan_out; | |
2419 | wire efu_l2t5_fuse_clr; | |
2420 | wire efu_l2t5_fuse_xfer_en; | |
2421 | wire l2t5_efu_fuse_data; | |
2422 | wire l2t5_efu_fuse_xfer_en; | |
2423 | wire cmp_gclk_c2_l2t5; | |
2424 | wire gl_l2t5_clk_stop; | |
2425 | wire tcu_l2t5_shscan_scan_in; | |
2426 | wire l2t5_tcu_shscan_scan_out; | |
2427 | wire tcu_l2t5_shscan_clk_stop; | |
2428 | wire [23:0] l2t5_rep_out0_unused; | |
2429 | wire [23:0] l2t5_rep_out1_unused; | |
2430 | wire [23:0] l2t5_rep_out2_unused; | |
2431 | wire [23:0] l2t5_rep_out3_unused; | |
2432 | wire [23:0] l2t5_rep_out4_unused; | |
2433 | wire [23:0] l2t5_rep_out5_unused; | |
2434 | wire [23:0] l2t5_rep_out6_unused; | |
2435 | wire [23:0] l2t5_rep_out7_unused; | |
2436 | wire [23:0] l2t5_rep_out8_unused; | |
2437 | wire [23:0] l2t5_rep_out9_unused; | |
2438 | wire [23:0] l2t5_rep_out10_unused; | |
2439 | wire [23:0] l2t5_rep_out11_unused; | |
2440 | wire [23:0] l2t5_rep_out12_unused; | |
2441 | wire [23:0] l2t5_rep_out13_unused; | |
2442 | wire [23:0] l2t5_rep_out14_unused; | |
2443 | wire [23:0] l2t5_rep_out15_unused; | |
2444 | wire [23:0] l2t5_rep_out16_unused; | |
2445 | wire [23:0] l2t5_rep_out17_unused; | |
2446 | wire [23:0] l2t5_rep_out18_unused; | |
2447 | wire [23:0] l2t5_rep_out19_unused; | |
2448 | wire [31:0] sii_l2t6_req; | |
2449 | wire sii_l2t6_req_vld; | |
2450 | wire [31:0] sii_l2t7_req; | |
2451 | wire sii_l2t7_req_vld; | |
2452 | wire l2t7_mcu3_rd_req; | |
2453 | wire l2t7_mcu3_rd_dummy_req; | |
2454 | wire [2:0] l2t7_mcu3_rd_req_id; | |
2455 | wire l2t7_mcu3_wr_req; | |
2456 | wire l2t7_mcu3_addr_5; | |
2457 | wire [39:7] l2t7_mcu3_addr; | |
2458 | wire [31:0] sii_l2t6_req_t6lff; | |
2459 | wire sii_l2t6_req_vld_t6lff; | |
2460 | wire [31:0] sii_l2t7_req_t6lff; | |
2461 | wire sii_l2t7_req_vld_t6lff; | |
2462 | wire l2t7_mcu3_rd_req_t6lff; | |
2463 | wire l2t7_mcu3_rd_dummy_req_t6lff; | |
2464 | wire [2:0] l2t7_mcu3_rd_req_id_t6lff; | |
2465 | wire l2t7_mcu3_wr_req_t6lff; | |
2466 | wire l2t7_mcu3_addr_5_t6lff; | |
2467 | wire [39:7] l2t7_mcu3_addr_t6lff; | |
2468 | wire [38:0] l2t7_dmo_dout; | |
2469 | wire [38:0] l2t6_dmo_dout; | |
2470 | wire [7:0] sctag6_cpx_req_cq; | |
2471 | wire sctag6_cpx_atom_cq; | |
2472 | wire sctag6_pcx_stall_pq; | |
2473 | wire pcx_sctag6_data_rdy_px1; | |
2474 | wire [129:0] pcx_sctag6_data_px2; | |
2475 | wire pcx_sctag6_atm_px1; | |
2476 | wire [7:0] cpx_sctag6_grant_cx; | |
2477 | wire l2t6_rst_fatal_error; | |
2478 | wire l2t6_l2b6_fbrd_en_c3; | |
2479 | wire [2:0] l2t6_l2b6_fbrd_wl_c3; | |
2480 | wire [15:0] l2t6_l2b6_fbwr_wen_r2; | |
2481 | wire [2:0] l2t6_l2b6_fbwr_wl_r2; | |
2482 | wire l2t6_l2b6_fbd_stdatasel_c3; | |
2483 | wire [3:0] l2t6_l2b6_wbwr_wen_c6; | |
2484 | wire [2:0] l2t6_l2b6_wbwr_wl_c6; | |
2485 | wire l2t6_l2b6_wbrd_en_r0; | |
2486 | wire [2:0] l2t6_l2b6_wbrd_wl_r0; | |
2487 | wire [2:0] l2t6_l2b6_ev_dword_r0; | |
2488 | wire l2t6_l2b6_evict_en_r0; | |
2489 | wire l2b6_l2t6_ev_uerr_r5; | |
2490 | wire l2b6_l2t6_ev_cerr_r5; | |
2491 | wire [15:0] l2t6_l2b6_rdma_wren_s2; | |
2492 | wire [1:0] l2t6_l2b6_rdma_wrwl_s2; | |
2493 | wire [1:0] l2t6_l2b6_rdma_rdwl_r0; | |
2494 | wire l2t6_l2b6_rdma_rden_r0; | |
2495 | wire l2t6_l2b6_ctag_en_c7; | |
2496 | wire [31:0] l2t6_l2b6_ctag_c7; | |
2497 | wire [3:0] l2t6_l2b6_word_c7; | |
2498 | wire l2t6_l2b6_req_en_c7; | |
2499 | wire l2t6_l2b6_word_vld_c7; | |
2500 | wire l2b6_l2t6_rdma_uerr_c10; | |
2501 | wire l2b6_l2t6_rdma_cerr_c10; | |
2502 | wire l2b6_l2t6_rdma_notdata_c10; | |
2503 | wire l2t6_mcu3_rd_req; | |
2504 | wire l2t6_mcu3_rd_dummy_req; | |
2505 | wire [2:0] l2t6_mcu3_rd_req_id; | |
2506 | wire [39:7] l2t6_mcu3_addr; | |
2507 | wire l2t6_mcu3_addr_5; | |
2508 | wire l2t6_mcu3_wr_req; | |
2509 | wire mcu3_l2t6_rd_ack; | |
2510 | wire mcu3_l2t6_wr_ack; | |
2511 | wire [1:0] mcu3_l2t6_qword_id_r0; | |
2512 | wire mcu3_l2t6_data_vld_r0; | |
2513 | wire [2:0] mcu3_l2t6_rd_req_id_r0; | |
2514 | wire mcu3_l2t6_secc_err_r2; | |
2515 | wire mcu3_l2t6_mecc_err_r2; | |
2516 | wire mcu3_l2t6_scb_mecc_err; | |
2517 | wire mcu3_l2t6_scb_secc_err; | |
2518 | wire tcu_soc3_scan_out; | |
2519 | wire l2t6_scan_out; | |
2520 | wire tcu_l2t6_mbist_start; | |
2521 | wire tcu_l2t6_mbist_scan_in; | |
2522 | wire l2t6_tcu_mbist_done; | |
2523 | wire l2t6_tcu_mbist_fail; | |
2524 | wire l2t6_tcu_mbist_scan_out; | |
2525 | wire efu_l2t6_fuse_clr; | |
2526 | wire efu_l2t6_fuse_xfer_en; | |
2527 | wire l2t6_efu_fuse_data; | |
2528 | wire l2t6_efu_fuse_xfer_en; | |
2529 | wire cmp_gclk_c1_l2t6; | |
2530 | wire gl_l2t6_clk_stop; | |
2531 | wire tcu_l2t6_shscan_scan_in; | |
2532 | wire l2t6_tcu_shscan_scan_out; | |
2533 | wire tcu_l2t6_shscan_clk_stop; | |
2534 | wire [23:0] l2t6_rep_out0_unused; | |
2535 | wire [23:0] l2t6_rep_out1_unused; | |
2536 | wire [23:0] l2t6_rep_out2_unused; | |
2537 | wire [23:0] l2t6_rep_out3_unused; | |
2538 | wire [23:0] l2t6_rep_out4_unused; | |
2539 | wire [23:0] l2t6_rep_out5_unused; | |
2540 | wire [23:0] l2t6_rep_out6_unused; | |
2541 | wire [23:0] l2t6_rep_out7_unused; | |
2542 | wire [23:0] l2t6_rep_out8_unused; | |
2543 | wire [23:0] l2t6_rep_out9_unused; | |
2544 | wire [23:0] l2t6_rep_out10_unused; | |
2545 | wire [23:0] l2t6_rep_out11_unused; | |
2546 | wire [23:0] l2t6_rep_out12_unused; | |
2547 | wire [23:0] l2t6_rep_out13_unused; | |
2548 | wire [23:0] l2t6_rep_out14_unused; | |
2549 | wire [23:0] l2t6_rep_out15_unused; | |
2550 | wire [23:0] l2t6_rep_out16_unused; | |
2551 | wire [23:0] l2t6_rep_out17_unused; | |
2552 | wire [23:0] l2t6_rep_out18_unused; | |
2553 | wire [23:0] l2t6_rep_out19_unused; | |
2554 | wire mcu3_l2t7_rd_ack; | |
2555 | wire mcu3_l2t7_wr_ack; | |
2556 | wire [1:0] mcu3_l2t7_qword_id_r0; | |
2557 | wire mcu3_l2t7_data_vld_r0; | |
2558 | wire [2:0] mcu3_l2t7_rd_req_id_r0; | |
2559 | wire mcu3_l2t7_secc_err_r2; | |
2560 | wire mcu3_l2t7_mecc_err_r2; | |
2561 | wire mcu3_l2t7_scb_mecc_err; | |
2562 | wire mcu3_l2t7_scb_secc_err; | |
2563 | wire l2t2_tcu_mbist_done_t7lff; | |
2564 | wire l2t2_tcu_mbist_fail_t7lff; | |
2565 | wire spc2_tcu_mbist_done_t7lff; | |
2566 | wire spc2_tcu_mbist_fail_t7lff; | |
2567 | wire spc2_softstop_request_t7lff; | |
2568 | wire spc2_hardstop_request_t7lff; | |
2569 | wire spc2_trigger_pulse_t7lff; | |
2570 | wire spc2_ss_complete_t7lff; | |
2571 | wire mcu3_l2t7_rd_ack_t7rff; | |
2572 | wire mcu3_l2t7_wr_ack_t7rff; | |
2573 | wire [1:0] mcu3_l2t7_qword_id_r0_t7rff; | |
2574 | wire mcu3_l2t7_data_vld_r0_t7rff; | |
2575 | wire [2:0] mcu3_l2t7_rd_req_id_r0_t7rff; | |
2576 | wire mcu3_l2t7_secc_err_r2_t7rff; | |
2577 | wire mcu3_l2t7_mecc_err_r2_t7rff; | |
2578 | wire mcu3_l2t7_scb_mecc_err_t7rff; | |
2579 | wire mcu3_l2t7_scb_secc_err_t7rff; | |
2580 | wire [7:0] sctag7_cpx_req_cq; | |
2581 | wire sctag7_cpx_atom_cq; | |
2582 | wire sctag7_pcx_stall_pq; | |
2583 | wire pcx_sctag7_data_rdy_px1; | |
2584 | wire [129:0] pcx_sctag7_data_px2; | |
2585 | wire pcx_sctag7_atm_px1; | |
2586 | wire [7:0] cpx_sctag7_grant_cx; | |
2587 | wire l2t7_rst_fatal_error; | |
2588 | wire l2t7_l2b7_fbrd_en_c3; | |
2589 | wire [2:0] l2t7_l2b7_fbrd_wl_c3; | |
2590 | wire [15:0] l2t7_l2b7_fbwr_wen_r2; | |
2591 | wire [2:0] l2t7_l2b7_fbwr_wl_r2; | |
2592 | wire l2t7_l2b7_fbd_stdatasel_c3; | |
2593 | wire [3:0] l2t7_l2b7_wbwr_wen_c6; | |
2594 | wire [2:0] l2t7_l2b7_wbwr_wl_c6; | |
2595 | wire l2t7_l2b7_wbrd_en_r0; | |
2596 | wire [2:0] l2t7_l2b7_wbrd_wl_r0; | |
2597 | wire [2:0] l2t7_l2b7_ev_dword_r0; | |
2598 | wire l2t7_l2b7_evict_en_r0; | |
2599 | wire l2b7_l2t7_ev_uerr_r5; | |
2600 | wire l2b7_l2t7_ev_cerr_r5; | |
2601 | wire [15:0] l2t7_l2b7_rdma_wren_s2; | |
2602 | wire [1:0] l2t7_l2b7_rdma_wrwl_s2; | |
2603 | wire [1:0] l2t7_l2b7_rdma_rdwl_r0; | |
2604 | wire l2t7_l2b7_rdma_rden_r0; | |
2605 | wire l2t7_l2b7_ctag_en_c7; | |
2606 | wire [31:0] l2t7_l2b7_ctag_c7; | |
2607 | wire [3:0] l2t7_l2b7_word_c7; | |
2608 | wire l2t7_l2b7_req_en_c7; | |
2609 | wire l2t7_l2b7_word_vld_c7; | |
2610 | wire l2b7_l2t7_rdma_uerr_c10; | |
2611 | wire l2b7_l2t7_rdma_cerr_c10; | |
2612 | wire l2b7_l2t7_rdma_notdata_c10; | |
2613 | wire tcu_l2t7_mbist_start; | |
2614 | wire tcu_l2t7_mbist_scan_in; | |
2615 | wire l2t7_tcu_mbist_done; | |
2616 | wire l2t7_tcu_mbist_fail; | |
2617 | wire l2t7_tcu_mbist_scan_out; | |
2618 | wire efu_l2t7_fuse_clr; | |
2619 | wire efu_l2t7_fuse_xfer_en; | |
2620 | wire l2t7_efu_fuse_data; | |
2621 | wire l2t7_efu_fuse_xfer_en; | |
2622 | wire cmp_gclk_c2_l2t7; | |
2623 | wire gl_l2t7_clk_stop; | |
2624 | wire tcu_l2t7_shscan_scan_in; | |
2625 | wire l2t7_tcu_shscan_scan_out; | |
2626 | wire tcu_l2t7_shscan_clk_stop; | |
2627 | wire [23:0] l2t7_rep_out0_unused; | |
2628 | wire [23:0] l2t7_rep_out1_unused; | |
2629 | wire [23:0] l2t7_rep_out2_unused; | |
2630 | wire [23:0] l2t7_rep_out3_unused; | |
2631 | wire [23:0] l2t7_rep_out4_unused; | |
2632 | wire [23:0] l2t7_rep_out5_unused; | |
2633 | wire [23:0] l2t7_rep_out6_unused; | |
2634 | wire [23:0] l2t7_rep_out7_unused; | |
2635 | wire [23:0] l2t7_rep_out8_unused; | |
2636 | wire [23:0] l2t7_rep_out9_unused; | |
2637 | wire [23:0] l2t7_rep_out10_unused; | |
2638 | wire [23:0] l2t7_rep_out11_unused; | |
2639 | wire [23:0] l2t7_rep_out12_unused; | |
2640 | wire [23:0] l2t7_rep_out13_unused; | |
2641 | wire [23:0] l2t7_rep_out14_unused; | |
2642 | wire [23:0] l2t7_rep_out15_unused; | |
2643 | wire [23:0] l2t7_rep_out16_unused; | |
2644 | wire [23:0] l2t7_rep_out17_unused; | |
2645 | wire [23:0] l2t7_rep_out18_unused; | |
2646 | wire [23:0] l2t7_rep_out19_unused; | |
2647 | wire cmp_gclk_c3_l2b0; | |
2648 | wire gl_l2b0_clk_stop; | |
2649 | wire efu_l2b0246_fuse_data; | |
2650 | wire efu_l2b0_fuse_xfer_en; | |
2651 | wire efu_l2b0_fuse_clr; | |
2652 | wire l2b0_efu_fuse_xfer_en; | |
2653 | wire l2b0_efu_fuse_data; | |
2654 | wire [127:0] mcu0_l2b01_data_r2; | |
2655 | wire [27:0] mcu0_l2b01_ecc_r2; | |
2656 | wire tcu_l2b0_mbist_scan_in; | |
2657 | wire l2b0_tcu_mbist_scan_out; | |
2658 | wire l2b0_mcu0_data_mecc_r5; | |
2659 | wire [63:0] l2b0_mcu0_wr_data_r5; | |
2660 | wire l2b0_mcu0_data_vld_r5; | |
2661 | wire tcu_soch_scan_out; | |
2662 | wire l2b0_scan_out; | |
2663 | wire cmp_gclk_c3_l2b1; | |
2664 | wire gl_l2b1_clk_stop; | |
2665 | wire efu_l2b1357_fuse_data; | |
2666 | wire efu_l2b1_fuse_xfer_en; | |
2667 | wire efu_l2b1_fuse_clr; | |
2668 | wire l2b1_efu_fuse_xfer_en; | |
2669 | wire l2b1_efu_fuse_data; | |
2670 | wire tcu_l2b1_mbist_scan_in; | |
2671 | wire l2b1_tcu_mbist_scan_out; | |
2672 | wire l2b1_mcu0_data_mecc_r5; | |
2673 | wire [63:0] l2b1_mcu0_wr_data_r5; | |
2674 | wire l2b1_mcu0_data_vld_r5; | |
2675 | wire l2b1_scan_out; | |
2676 | wire cmp_gclk_c3_l2b2; | |
2677 | wire gl_l2b2_clk_stop; | |
2678 | wire efu_l2b2_fuse_xfer_en; | |
2679 | wire efu_l2b2_fuse_clr; | |
2680 | wire l2b2_efu_fuse_xfer_en; | |
2681 | wire l2b2_efu_fuse_data; | |
2682 | wire [127:0] mcu1_l2b23_data_r2; | |
2683 | wire [27:0] mcu1_l2b23_ecc_r2; | |
2684 | wire tcu_l2b2_mbist_scan_in; | |
2685 | wire l2b2_tcu_mbist_scan_out; | |
2686 | wire l2b2_mcu1_data_mecc_r5; | |
2687 | wire [63:0] l2b2_mcu1_wr_data_r5; | |
2688 | wire l2b2_mcu1_data_vld_r5; | |
2689 | wire l2b2_scan_out; | |
2690 | wire cmp_gclk_c3_l2b3; | |
2691 | wire gl_l2b3_clk_stop; | |
2692 | wire efu_l2b3_fuse_xfer_en; | |
2693 | wire efu_l2b3_fuse_clr; | |
2694 | wire l2b3_efu_fuse_xfer_en; | |
2695 | wire l2b3_efu_fuse_data; | |
2696 | wire tcu_l2b3_mbist_scan_in; | |
2697 | wire l2b3_tcu_mbist_scan_out; | |
2698 | wire l2b3_mcu1_data_mecc_r5; | |
2699 | wire [63:0] l2b3_mcu1_wr_data_r5; | |
2700 | wire l2b3_mcu1_data_vld_r5; | |
2701 | wire l2b3_scan_out; | |
2702 | wire cmp_gclk_c1_l2b4; | |
2703 | wire gl_l2b4_clk_stop; | |
2704 | wire efu_l2b4_fuse_xfer_en; | |
2705 | wire efu_l2b4_fuse_clr; | |
2706 | wire l2b4_efu_fuse_xfer_en; | |
2707 | wire l2b4_efu_fuse_data; | |
2708 | wire [127:0] mcu2_l2b45_data_r2; | |
2709 | wire [27:0] mcu2_l2b45_ecc_r2; | |
2710 | wire tcu_l2b4_mbist_start; | |
2711 | wire l2b4_tcu_mbist_done; | |
2712 | wire l2b4_tcu_mbist_fail; | |
2713 | wire tcu_l2b4_mbist_scan_in; | |
2714 | wire l2b4_tcu_mbist_scan_out; | |
2715 | wire l2b4_mcu2_data_mecc_r5; | |
2716 | wire [63:0] l2b4_mcu2_wr_data_r5; | |
2717 | wire l2b4_mcu2_data_vld_r5; | |
2718 | wire l2b4_scan_out; | |
2719 | wire cmp_gclk_c1_l2b5; | |
2720 | wire gl_l2b5_clk_stop; | |
2721 | wire efu_l2b5_fuse_xfer_en; | |
2722 | wire efu_l2b5_fuse_clr; | |
2723 | wire l2b5_efu_fuse_xfer_en; | |
2724 | wire l2b5_efu_fuse_data; | |
2725 | wire l2b5_sio_ctag_vld; | |
2726 | wire [31:0] l2b5_sio_data; | |
2727 | wire [1:0] l2b5_sio_parity; | |
2728 | wire l2b5_sio_ue_err; | |
2729 | wire tcu_l2b5_mbist_start; | |
2730 | wire l2b5_tcu_mbist_done; | |
2731 | wire l2b5_tcu_mbist_fail; | |
2732 | wire tcu_l2b5_mbist_scan_in; | |
2733 | wire l2b5_tcu_mbist_scan_out; | |
2734 | wire l2b5_mcu2_data_mecc_r5; | |
2735 | wire [63:0] l2b5_mcu2_wr_data_r5; | |
2736 | wire l2b5_mcu2_data_vld_r5; | |
2737 | wire l2b5_scan_out; | |
2738 | wire cmp_gclk_c1_l2b6; | |
2739 | wire gl_l2b6_clk_stop; | |
2740 | wire efu_l2b6_fuse_xfer_en; | |
2741 | wire efu_l2b6_fuse_clr; | |
2742 | wire l2b6_efu_fuse_xfer_en; | |
2743 | wire l2b6_efu_fuse_data; | |
2744 | wire l2b6_sio_ctag_vld; | |
2745 | wire [31:0] l2b6_sio_data; | |
2746 | wire [1:0] l2b6_sio_parity; | |
2747 | wire l2b6_sio_ue_err; | |
2748 | wire [127:0] mcu3_l2b67_data_r2; | |
2749 | wire [27:0] mcu3_l2b67_ecc_r2; | |
2750 | wire tcu_l2b6_mbist_start; | |
2751 | wire l2b6_tcu_mbist_done; | |
2752 | wire l2b6_tcu_mbist_fail; | |
2753 | wire tcu_l2b6_mbist_scan_in; | |
2754 | wire l2b6_tcu_mbist_scan_out; | |
2755 | wire l2b6_mcu3_data_mecc_r5; | |
2756 | wire [63:0] l2b6_mcu3_wr_data_r5; | |
2757 | wire l2b6_mcu3_data_vld_r5; | |
2758 | wire l2b6_scan_out; | |
2759 | wire cmp_gclk_c1_l2b7; | |
2760 | wire gl_l2b7_clk_stop; | |
2761 | wire efu_l2b7_fuse_xfer_en; | |
2762 | wire efu_l2b7_fuse_clr; | |
2763 | wire l2b7_efu_fuse_xfer_en; | |
2764 | wire l2b7_efu_fuse_data; | |
2765 | wire l2b7_sio_ctag_vld; | |
2766 | wire [31:0] l2b7_sio_data; | |
2767 | wire [1:0] l2b7_sio_parity; | |
2768 | wire l2b7_sio_ue_err; | |
2769 | wire tcu_l2b7_mbist_start; | |
2770 | wire l2b7_tcu_mbist_done; | |
2771 | wire l2b7_tcu_mbist_fail; | |
2772 | wire tcu_l2b7_mbist_scan_in; | |
2773 | wire l2b7_tcu_mbist_scan_out; | |
2774 | wire l2b7_mcu3_data_mecc_r5; | |
2775 | wire [63:0] l2b7_mcu3_wr_data_r5; | |
2776 | wire l2b7_mcu3_data_vld_r5; | |
2777 | wire l2b7_scan_out; | |
2778 | wire cmp_gclk_c4_mcu0; | |
2779 | wire gl_mcu0_clk_stop; | |
2780 | wire gl_mcu0_dr_clk_stop; | |
2781 | wire gl_mcu0_io_clk_stop; | |
2782 | wire dr_gclk_c4_mcu0; | |
2783 | wire gl_dr_sync_en_c3t; | |
2784 | wire tcu_mcu0_fbd_clk_stop; | |
2785 | wire mcu0_pt_sync_out; | |
2786 | wire mcu1_pt_sync_out; | |
2787 | wire mcu2_pt_sync_out; | |
2788 | wire mcu3_pt_sync_out; | |
2789 | wire [3:0] mcu0_ncu_data; | |
2790 | wire mcu0_ncu_stall; | |
2791 | wire mcu0_ncu_vld; | |
2792 | wire [3:0] ncu_mcu0_data; | |
2793 | wire ncu_mcu0_stall; | |
2794 | wire ncu_mcu0_vld; | |
2795 | wire mcu0_ncu_ecc; | |
2796 | wire mcu0_ncu_fbr; | |
2797 | wire ncu_mcu0_ecci; | |
2798 | wire ncu_mcu0_fbui; | |
2799 | wire ncu_mcu0_fbri; | |
2800 | wire [119:0] mcu0_fsr0_data; | |
2801 | wire [119:0] mcu0_fsr1_data; | |
2802 | wire mcu0_fsr0_cfgpll_enpll; | |
2803 | wire mcu0_fsr1_cfgpll_enpll; | |
2804 | wire [1:0] mcu0_fsr01_cfgpll_lb; | |
2805 | wire [3:0] mcu0_fsr01_cfgpll_mpy; | |
2806 | wire mcu0_fsr0_cfgrx_enrx; | |
2807 | wire mcu0_fsr1_cfgrx_enrx; | |
2808 | wire mcu0_fsr0_cfgrx_align; | |
2809 | wire mcu0_fsr1_cfgrx_align; | |
2810 | wire [13:0] mcu0_fsr0_cfgrx_invpair; | |
2811 | wire [13:0] mcu0_fsr1_cfgrx_invpair; | |
2812 | wire [3:0] mcu0_fsr01_cfgrx_eq; | |
2813 | wire [2:0] mcu0_fsr01_cfgrx_cdr; | |
2814 | wire [2:0] mcu0_fsr01_cfgrx_term; | |
2815 | wire mcu0_fsr0_cfgtx_entx; | |
2816 | wire mcu0_fsr1_cfgtx_entx; | |
2817 | wire mcu0_fsr0_cfgtx_enidl; | |
2818 | wire mcu0_fsr1_cfgtx_enidl; | |
2819 | wire [9:0] mcu0_fsr0_cfgtx_invpair; | |
2820 | wire [9:0] mcu0_fsr1_cfgtx_invpair; | |
2821 | wire mcu0_fsr01_cfgtx_enftp; | |
2822 | wire [3:0] mcu0_fsr01_cfgtx_de; | |
2823 | wire [2:0] mcu0_fsr01_cfgtx_swing; | |
2824 | wire mcu0_fsr01_cfgtx_cm; | |
2825 | wire [1:0] mcu0_fsr01_cfgrtx_rate; | |
2826 | wire mcu0_fsr0_cfgrx_entest; | |
2827 | wire mcu0_fsr1_cfgrx_entest; | |
2828 | wire mcu0_fsr0_cfgtx_entest; | |
2829 | wire mcu0_fsr1_cfgtx_entest; | |
2830 | wire [9:0] mcu0_fsr0_cfgtx_bstx; | |
2831 | wire [9:0] mcu0_fsr1_cfgtx_bstx; | |
2832 | wire [167:0] fsr0_mcu0_data; | |
2833 | wire [167:0] fsr1_mcu0_data; | |
2834 | wire [13:0] fsr0_mcu0_rxbclk; | |
2835 | wire [13:0] fsr1_mcu0_rxbclk; | |
2836 | wire [2:0] fsr0_mcu0_stspll_lock; | |
2837 | wire [2:0] fsr1_mcu0_stspll_lock; | |
2838 | wire [11:0] mcu0_fsr0_testcfg; | |
2839 | wire [11:0] mcu0_fsr1_testcfg; | |
2840 | wire [13:0] fsr0_mcu0_stsrx_sync; | |
2841 | wire [13:0] fsr1_mcu0_stsrx_sync; | |
2842 | wire [13:0] fsr0_mcu0_stsrx_losdtct; | |
2843 | wire [13:0] fsr1_mcu0_stsrx_losdtct; | |
2844 | wire [13:0] fsr0_mcu0_stsrx_testfail; | |
2845 | wire [13:0] fsr1_mcu0_stsrx_testfail; | |
2846 | wire [13:0] fsr0_mcu0_stsrx_bsrxp; | |
2847 | wire [13:0] fsr1_mcu0_stsrx_bsrxp; | |
2848 | wire [13:0] fsr0_mcu0_stsrx_bsrxn; | |
2849 | wire [13:0] fsr1_mcu0_stsrx_bsrxn; | |
2850 | wire [9:0] fsr0_mcu0_ststx_testfail; | |
2851 | wire [9:0] fsr1_mcu0_ststx_testfail; | |
2852 | wire tcu_mcu0_mbist_scan_in; | |
2853 | wire mcu0_tcu_mbist_scan_out; | |
2854 | wire tcu_sbs_scan_in; | |
2855 | wire mcu0_sbs_scan_out; | |
2856 | wire mcu0_scan_out; | |
2857 | wire cmp_gclk_c4_mcu1; | |
2858 | wire gl_mcu1_dr_clk_stop; | |
2859 | wire gl_mcu1_clk_stop; | |
2860 | wire gl_mcu1_io_clk_stop; | |
2861 | wire dr_gclk_c4_mcu1; | |
2862 | wire tcu_mcu1_fbd_clk_stop; | |
2863 | wire [3:0] mcu1_ncu_data; | |
2864 | wire mcu1_ncu_stall; | |
2865 | wire mcu1_ncu_vld; | |
2866 | wire [3:0] ncu_mcu1_data; | |
2867 | wire ncu_mcu1_stall; | |
2868 | wire ncu_mcu1_vld; | |
2869 | wire mcu1_ncu_ecc; | |
2870 | wire mcu1_ncu_fbr; | |
2871 | wire ncu_mcu1_ecci; | |
2872 | wire ncu_mcu1_fbui; | |
2873 | wire ncu_mcu1_fbri; | |
2874 | wire [119:0] mcu1_fsr2_data; | |
2875 | wire [119:0] mcu1_fsr3_data; | |
2876 | wire mcu1_fsr2_cfgpll_enpll; | |
2877 | wire mcu1_fsr3_cfgpll_enpll; | |
2878 | wire [1:0] mcu1_fsr23_cfgpll_lb; | |
2879 | wire [3:0] mcu1_fsr23_cfgpll_mpy; | |
2880 | wire mcu1_fsr2_cfgrx_enrx; | |
2881 | wire mcu1_fsr3_cfgrx_enrx; | |
2882 | wire mcu1_fsr2_cfgrx_align; | |
2883 | wire mcu1_fsr3_cfgrx_align; | |
2884 | wire [13:0] mcu1_fsr2_cfgrx_invpair; | |
2885 | wire [13:0] mcu1_fsr3_cfgrx_invpair; | |
2886 | wire [3:0] mcu1_fsr23_cfgrx_eq; | |
2887 | wire [2:0] mcu1_fsr23_cfgrx_cdr; | |
2888 | wire [2:0] mcu1_fsr23_cfgrx_term; | |
2889 | wire mcu1_fsr2_cfgtx_entx; | |
2890 | wire mcu1_fsr3_cfgtx_entx; | |
2891 | wire mcu1_fsr2_cfgtx_enidl; | |
2892 | wire mcu1_fsr3_cfgtx_enidl; | |
2893 | wire [9:0] mcu1_fsr2_cfgtx_invpair; | |
2894 | wire [9:0] mcu1_fsr3_cfgtx_invpair; | |
2895 | wire mcu1_fsr23_cfgtx_enftp; | |
2896 | wire [3:0] mcu1_fsr23_cfgtx_de; | |
2897 | wire [2:0] mcu1_fsr23_cfgtx_swing; | |
2898 | wire mcu1_fsr23_cfgtx_cm; | |
2899 | wire [1:0] mcu1_fsr23_cfgrtx_rate; | |
2900 | wire mcu1_fsr2_cfgrx_entest; | |
2901 | wire mcu1_fsr3_cfgrx_entest; | |
2902 | wire mcu1_fsr2_cfgtx_entest; | |
2903 | wire mcu1_fsr3_cfgtx_entest; | |
2904 | wire [9:0] mcu1_fsr2_cfgtx_bstx; | |
2905 | wire [9:0] mcu1_fsr3_cfgtx_bstx; | |
2906 | wire [167:0] fsr2_mcu1_data; | |
2907 | wire [167:0] fsr3_mcu1_data; | |
2908 | wire [13:0] fsr2_mcu1_rxbclk; | |
2909 | wire [13:0] fsr3_mcu1_rxbclk; | |
2910 | wire [2:0] fsr2_mcu1_stspll_lock; | |
2911 | wire [2:0] fsr3_mcu1_stspll_lock; | |
2912 | wire [11:0] mcu1_fsr2_testcfg; | |
2913 | wire [11:0] mcu1_fsr3_testcfg; | |
2914 | wire [13:0] fsr2_mcu1_stsrx_sync; | |
2915 | wire [13:0] fsr3_mcu1_stsrx_sync; | |
2916 | wire [13:0] fsr2_mcu1_stsrx_losdtct; | |
2917 | wire [13:0] fsr3_mcu1_stsrx_losdtct; | |
2918 | wire [13:0] fsr2_mcu1_stsrx_testfail; | |
2919 | wire [13:0] fsr3_mcu1_stsrx_testfail; | |
2920 | wire [13:0] fsr2_mcu1_stsrx_bsrxp; | |
2921 | wire [13:0] fsr3_mcu1_stsrx_bsrxp; | |
2922 | wire [13:0] fsr2_mcu1_stsrx_bsrxn; | |
2923 | wire [13:0] fsr3_mcu1_stsrx_bsrxn; | |
2924 | wire [9:0] fsr2_mcu1_ststx_testfail; | |
2925 | wire [9:0] fsr3_mcu1_ststx_testfail; | |
2926 | wire tcu_mcu1_mbist_scan_in; | |
2927 | wire mcu1_tcu_mbist_scan_out; | |
2928 | wire mcu1_sbs_scan_out; | |
2929 | wire tcu_socc_scan_out; | |
2930 | wire mcu1_scan_out; | |
2931 | wire cmp_gclk_c0_mcu2; | |
2932 | wire gl_mcu2_dr_clk_stop; | |
2933 | wire gl_mcu2_io_clk_stop; | |
2934 | wire gl_mcu2_clk_stop; | |
2935 | wire dr_gclk_c0_mcu2; | |
2936 | wire gl_dr_sync_en_c1m; | |
2937 | wire tcu_mcu2_fbd_clk_stop; | |
2938 | wire [3:0] mcu2_ncu_data; | |
2939 | wire mcu2_ncu_stall; | |
2940 | wire mcu2_ncu_vld; | |
2941 | wire [3:0] ncu_mcu2_data; | |
2942 | wire ncu_mcu2_stall; | |
2943 | wire ncu_mcu2_vld; | |
2944 | wire mcu2_ncu_ecc; | |
2945 | wire mcu2_ncu_fbr; | |
2946 | wire ncu_mcu2_ecci; | |
2947 | wire ncu_mcu2_fbui; | |
2948 | wire ncu_mcu2_fbri; | |
2949 | wire [119:0] mcu2_fsr4_data; | |
2950 | wire [119:0] mcu2_fsr5_data; | |
2951 | wire mcu2_fsr4_cfgpll_enpll; | |
2952 | wire mcu2_fsr5_cfgpll_enpll; | |
2953 | wire [1:0] mcu2_fsr45_cfgpll_lb; | |
2954 | wire [3:0] mcu2_fsr45_cfgpll_mpy; | |
2955 | wire mcu2_fsr4_cfgrx_enrx; | |
2956 | wire mcu2_fsr5_cfgrx_enrx; | |
2957 | wire mcu2_fsr4_cfgrx_align; | |
2958 | wire mcu2_fsr5_cfgrx_align; | |
2959 | wire [13:0] mcu2_fsr4_cfgrx_invpair; | |
2960 | wire [13:0] mcu2_fsr5_cfgrx_invpair; | |
2961 | wire [3:0] mcu2_fsr45_cfgrx_eq; | |
2962 | wire [2:0] mcu2_fsr45_cfgrx_cdr; | |
2963 | wire [2:0] mcu2_fsr45_cfgrx_term; | |
2964 | wire mcu2_fsr4_cfgtx_entx; | |
2965 | wire mcu2_fsr5_cfgtx_entx; | |
2966 | wire mcu2_fsr4_cfgtx_enidl; | |
2967 | wire mcu2_fsr5_cfgtx_enidl; | |
2968 | wire [9:0] mcu2_fsr4_cfgtx_invpair; | |
2969 | wire [9:0] mcu2_fsr5_cfgtx_invpair; | |
2970 | wire mcu2_fsr45_cfgtx_enftp; | |
2971 | wire [3:0] mcu2_fsr45_cfgtx_de; | |
2972 | wire [2:0] mcu2_fsr45_cfgtx_swing; | |
2973 | wire mcu2_fsr45_cfgtx_cm; | |
2974 | wire [1:0] mcu2_fsr45_cfgrtx_rate; | |
2975 | wire mcu2_fsr4_cfgrx_entest; | |
2976 | wire mcu2_fsr5_cfgrx_entest; | |
2977 | wire mcu2_fsr4_cfgtx_entest; | |
2978 | wire mcu2_fsr5_cfgtx_entest; | |
2979 | wire [9:0] mcu2_fsr4_cfgtx_bstx; | |
2980 | wire [9:0] mcu2_fsr5_cfgtx_bstx; | |
2981 | wire [167:0] fsr4_mcu2_data; | |
2982 | wire [167:0] fsr5_mcu2_data; | |
2983 | wire [13:0] fsr4_mcu2_rxbclk; | |
2984 | wire [13:0] fsr5_mcu2_rxbclk; | |
2985 | wire [2:0] fsr4_mcu2_stspll_lock; | |
2986 | wire [2:0] fsr5_mcu2_stspll_lock; | |
2987 | wire [11:0] mcu2_fsr4_testcfg; | |
2988 | wire [11:0] mcu2_fsr5_testcfg; | |
2989 | wire [13:0] fsr4_mcu2_stsrx_sync; | |
2990 | wire [13:0] fsr5_mcu2_stsrx_sync; | |
2991 | wire [13:0] fsr4_mcu2_stsrx_losdtct; | |
2992 | wire [13:0] fsr5_mcu2_stsrx_losdtct; | |
2993 | wire [13:0] fsr4_mcu2_stsrx_testfail; | |
2994 | wire [13:0] fsr5_mcu2_stsrx_testfail; | |
2995 | wire [13:0] fsr4_mcu2_stsrx_bsrxp; | |
2996 | wire [13:0] fsr5_mcu2_stsrx_bsrxp; | |
2997 | wire [13:0] fsr4_mcu2_stsrx_bsrxn; | |
2998 | wire [13:0] fsr5_mcu2_stsrx_bsrxn; | |
2999 | wire [9:0] fsr4_mcu2_ststx_testfail; | |
3000 | wire [9:0] fsr5_mcu2_ststx_testfail; | |
3001 | wire tcu_mcu2_mbist_start; | |
3002 | wire mcu2_tcu_mbist_done; | |
3003 | wire mcu2_tcu_mbist_fail; | |
3004 | wire tcu_mcu2_mbist_scan_in; | |
3005 | wire mcu2_tcu_mbist_scan_out; | |
3006 | wire mcu3_sbs_scan_out; | |
3007 | wire mcu2_sbs_scan_out; | |
3008 | wire mcu2_scan_out; | |
3009 | wire cmp_gclk_c0_mcu3; | |
3010 | wire gl_mcu3_dr_clk_stop; | |
3011 | wire gl_mcu3_io_clk_stop; | |
3012 | wire gl_mcu3_clk_stop; | |
3013 | wire dr_gclk_c0_mcu3; | |
3014 | wire tcu_mcu3_fbd_clk_stop; | |
3015 | wire [3:0] mcu3_ncu_data; | |
3016 | wire mcu3_ncu_stall; | |
3017 | wire mcu3_ncu_vld; | |
3018 | wire [3:0] ncu_mcu3_data; | |
3019 | wire ncu_mcu3_stall; | |
3020 | wire ncu_mcu3_vld; | |
3021 | wire mcu3_ncu_ecc; | |
3022 | wire mcu3_ncu_fbr; | |
3023 | wire ncu_mcu3_ecci; | |
3024 | wire ncu_mcu3_fbui; | |
3025 | wire ncu_mcu3_fbri; | |
3026 | wire [119:0] mcu3_fsr6_data; | |
3027 | wire [119:0] mcu3_fsr7_data; | |
3028 | wire mcu3_fsr6_cfgpll_enpll; | |
3029 | wire mcu3_fsr7_cfgpll_enpll; | |
3030 | wire [1:0] mcu3_fsr67_cfgpll_lb; | |
3031 | wire [3:0] mcu3_fsr67_cfgpll_mpy; | |
3032 | wire mcu3_fsr6_cfgrx_enrx; | |
3033 | wire mcu3_fsr7_cfgrx_enrx; | |
3034 | wire mcu3_fsr6_cfgrx_align; | |
3035 | wire mcu3_fsr7_cfgrx_align; | |
3036 | wire [13:0] mcu3_fsr6_cfgrx_invpair; | |
3037 | wire [13:0] mcu3_fsr7_cfgrx_invpair; | |
3038 | wire [3:0] mcu3_fsr67_cfgrx_eq; | |
3039 | wire [2:0] mcu3_fsr67_cfgrx_cdr; | |
3040 | wire [2:0] mcu3_fsr67_cfgrx_term; | |
3041 | wire mcu3_fsr6_cfgtx_entx; | |
3042 | wire mcu3_fsr7_cfgtx_entx; | |
3043 | wire mcu3_fsr6_cfgtx_enidl; | |
3044 | wire mcu3_fsr7_cfgtx_enidl; | |
3045 | wire [9:0] mcu3_fsr6_cfgtx_invpair; | |
3046 | wire [9:0] mcu3_fsr7_cfgtx_invpair; | |
3047 | wire mcu3_fsr67_cfgtx_enftp; | |
3048 | wire [3:0] mcu3_fsr67_cfgtx_de; | |
3049 | wire [2:0] mcu3_fsr67_cfgtx_swing; | |
3050 | wire mcu3_fsr67_cfgtx_cm; | |
3051 | wire [1:0] mcu3_fsr67_cfgrtx_rate; | |
3052 | wire mcu3_fsr6_cfgrx_entest; | |
3053 | wire mcu3_fsr7_cfgrx_entest; | |
3054 | wire mcu3_fsr6_cfgtx_entest; | |
3055 | wire mcu3_fsr7_cfgtx_entest; | |
3056 | wire [9:0] mcu3_fsr6_cfgtx_bstx; | |
3057 | wire [9:0] mcu3_fsr7_cfgtx_bstx; | |
3058 | wire [167:0] fsr6_mcu3_data; | |
3059 | wire [167:0] fsr7_mcu3_data; | |
3060 | wire [13:0] fsr6_mcu3_rxbclk; | |
3061 | wire [13:0] fsr7_mcu3_rxbclk; | |
3062 | wire [2:0] fsr6_mcu3_stspll_lock; | |
3063 | wire [2:0] fsr7_mcu3_stspll_lock; | |
3064 | wire [11:0] mcu3_fsr6_testcfg; | |
3065 | wire [11:0] mcu3_fsr7_testcfg; | |
3066 | wire [13:0] fsr6_mcu3_stsrx_sync; | |
3067 | wire [13:0] fsr7_mcu3_stsrx_sync; | |
3068 | wire [13:0] fsr6_mcu3_stsrx_losdtct; | |
3069 | wire [13:0] fsr7_mcu3_stsrx_losdtct; | |
3070 | wire [13:0] fsr6_mcu3_stsrx_testfail; | |
3071 | wire [13:0] fsr7_mcu3_stsrx_testfail; | |
3072 | wire [13:0] fsr6_mcu3_stsrx_bsrxp; | |
3073 | wire [13:0] fsr7_mcu3_stsrx_bsrxp; | |
3074 | wire [13:0] fsr6_mcu3_stsrx_bsrxn; | |
3075 | wire [13:0] fsr7_mcu3_stsrx_bsrxn; | |
3076 | wire [9:0] fsr6_mcu3_ststx_testfail; | |
3077 | wire [9:0] fsr7_mcu3_ststx_testfail; | |
3078 | wire tcu_mcu3_mbist_start; | |
3079 | wire mcu3_tcu_mbist_done; | |
3080 | wire mcu3_tcu_mbist_fail; | |
3081 | wire tcu_mcu3_mbist_scan_in; | |
3082 | wire mcu3_tcu_mbist_scan_out; | |
3083 | wire ncu_scan_out; | |
3084 | wire mcu3_scan_out; | |
3085 | wire dr_gclk_c4_fsr0_2; | |
3086 | wire dr_gclk_c4_fsr0_1; | |
3087 | wire dr_gclk_c4_fsr0_0; | |
3088 | wire efu_mcu_fclk; | |
3089 | wire efu_mcu_fclrz; | |
3090 | wire efu_mcu_fdi; | |
3091 | wire [2:0] fsr0_fdo; | |
3092 | wire [2:0] fsr0_stciq; | |
3093 | wire tcu_stcid; | |
3094 | wire [7:0] mio_fsr_testclkr; | |
3095 | wire [7:0] mio_fsr_testclkt; | |
3096 | wire dr_gclk_c4_fsr1_2; | |
3097 | wire dr_gclk_c4_fsr1_1; | |
3098 | wire dr_gclk_c4_fsr1_0; | |
3099 | wire [2:0] fsr1_fdo; | |
3100 | wire [2:0] fsr1_stciq; | |
3101 | wire dr_gclk_c4_fsr2_2; | |
3102 | wire dr_gclk_c4_fsr2_1; | |
3103 | wire dr_gclk_c4_fsr2_0; | |
3104 | wire [2:0] fsr2_fdo; | |
3105 | wire [2:0] fsr2_stciq; | |
3106 | wire dr_gclk_c4_fsr3_2; | |
3107 | wire dr_gclk_c4_fsr3_1; | |
3108 | wire dr_gclk_c4_fsr3_0; | |
3109 | wire [2:0] fsr3_fdo; | |
3110 | wire [2:0] fsr3_stciq; | |
3111 | wire tcu_srd_atpgd; | |
3112 | wire fsr_left_atpgq; | |
3113 | wire dr_gclk_c0_fsr4_2; | |
3114 | wire dr_gclk_c0_fsr4_1; | |
3115 | wire dr_gclk_c0_fsr4_0; | |
3116 | wire [2:0] fsr4_fdo; | |
3117 | wire [2:0] fsr5_stciq; | |
3118 | wire [2:0] fsr4_stciq; | |
3119 | wire dr_gclk_c0_fsr5_2; | |
3120 | wire dr_gclk_c0_fsr5_1; | |
3121 | wire dr_gclk_c0_fsr5_0; | |
3122 | wire [2:0] fsr5_fdo; | |
3123 | wire [2:0] fsr6_stciq; | |
3124 | wire dr_gclk_c0_fsr6_2; | |
3125 | wire dr_gclk_c0_fsr6_1; | |
3126 | wire dr_gclk_c0_fsr6_0; | |
3127 | wire [2:0] fsr6_fdo; | |
3128 | wire [2:0] fsr7_stciq; | |
3129 | wire fsr_bottom_atpgq; | |
3130 | wire srd_tcu_atpgq; | |
3131 | wire dr_gclk_c2_fsr7_2; | |
3132 | wire dr_gclk_c2_fsr7_1; | |
3133 | wire dr_gclk_c2_fsr7_0; | |
3134 | wire [1:0] fsr7_fdo; | |
3135 | wire mcu_efu_fdo; | |
3136 | wire cmp_gclk_c3_sii; | |
3137 | wire gl_sii_clk_stop; | |
3138 | wire gl_sii_io_clk_stop; | |
3139 | wire sii_scan_out; | |
3140 | wire cmp_gclk_c1_sio; | |
3141 | wire gl_sio_clk_stop; | |
3142 | wire gl_sio_io_clk_stop; | |
3143 | wire sio_scan_out; | |
3144 | wire cmp_gclk_c3_ncu; | |
3145 | wire gl_ncu_io_clk_stop; | |
3146 | wire gl_ncu_clk_stop; | |
3147 | wire tcu_socg_scan_out; | |
3148 | wire cmp_gclk_c1_efu; | |
3149 | wire gl_efu_io_clk_stop; | |
3150 | wire gl_efu_clk_stop; | |
3151 | wire efu_scan_out; | |
3152 | wire [6:0] tcu_efu_rowaddr; | |
3153 | wire [4:0] tcu_efu_coladdr; | |
3154 | wire tcu_efu_read_en; | |
3155 | wire [2:0] tcu_efu_read_mode; | |
3156 | wire tcu_efu_read_start; | |
3157 | wire tcu_efu_fuse_bypass; | |
3158 | wire tcu_efu_dest_sample; | |
3159 | wire tcu_efu_data_in; | |
3160 | wire efu_tcu_data_out; | |
3161 | wire tcu_efu_updatedr; | |
3162 | wire tcu_efu_shiftdr; | |
3163 | wire tcu_efu_capturedr; | |
3164 | wire [6:0] tcu_efu_rvclr; | |
3165 | wire tck; | |
3166 | wire pcmb1_out; | |
3167 | wire pcma_out; | |
3168 | wire cmp_gclk_c3_rng; | |
3169 | wire rng_arst_l; | |
3170 | wire [1:0] rng_ch_sel; | |
3171 | wire rng_bypass; | |
3172 | wire mio_ccu_vreg_selbg_l; | |
3173 | wire [1:0] rng_vcoctrl_sel; | |
3174 | wire [1:0] rng_anlg_sel; | |
3175 | wire l2clk; | |
3176 | wire drl2clk; | |
3177 | wire cmp_gclk_c1_ccu; | |
3178 | wire rst_scan_out; | |
3179 | wire ccu_scan_out; | |
3180 | wire cmp_gclk_c1_tcu; | |
3181 | wire rst_tcu_pwron_rst_l; | |
3182 | wire ncu_spc0_core_enable_status; | |
3183 | wire ncu_spc1_core_enable_status; | |
3184 | wire ncu_spc2_core_enable_status; | |
3185 | wire ncu_spc3_core_enable_status; | |
3186 | wire ncu_spc4_core_enable_status; | |
3187 | wire ncu_spc5_core_enable_status; | |
3188 | wire ncu_spc6_core_enable_status; | |
3189 | wire ncu_spc7_core_enable_status; | |
3190 | wire dmu_scan_out; | |
3191 | wire peu_scan_out; | |
3192 | wire tcu_socd_scan_out; | |
3193 | wire tcu_peu_scan_out; | |
3194 | wire gl_dmu_peu_por_c3b; | |
3195 | wire gl_dmu_peu_wmr_c3b; | |
3196 | wire tcu_array_bypass; | |
3197 | wire sii_dmu_wrack_parity; | |
3198 | wire cmp_gclk_c3_dmu; | |
3199 | wire gl_dmu_io_clk_stop; | |
3200 | wire gl_io_out_c3b; | |
3201 | wire cmp_gclk_c3_peu; | |
3202 | wire gl_peu_io_clk_stop; | |
3203 | wire psr_peu_txbclk0; | |
3204 | wire [1:0] dmu_psr_rate_scale; | |
3205 | wire [3:0] peu_psr_pll_mpy; | |
3206 | wire [1:0] peu_psr_pll_lb; | |
3207 | wire psr_stciq_sds0; | |
3208 | wire efu_psr_fclk; | |
3209 | wire efu_psr_fclrz; | |
3210 | wire efu_psr_fdi; | |
3211 | wire psr_fdo_sds0; | |
3212 | wire psr_efu_fdo; | |
3213 | wire psr_peu_rxbclk_b3sds1; | |
3214 | wire psr_peu_rxbclk_b2sds1; | |
3215 | wire psr_peu_rxbclk_b1sds1; | |
3216 | wire psr_peu_rxbclk_b0sds1; | |
3217 | wire psr_peu_rxbclk_b3sds0; | |
3218 | wire psr_peu_rxbclk_b2sds0; | |
3219 | wire psr_peu_rxbclk_b1sds0; | |
3220 | wire psr_peu_rxbclk_b0sds0; | |
3221 | wire tcu_rst_scan_out; | |
3222 | wire gl_rst_io_clk_stop; | |
3223 | wire gl_rst_clk_stop; | |
3224 | wire stg1_ccx_clk_stop_c1b; | |
3225 | wire stg1_cmp_io_sync_en_c1b; | |
3226 | wire stg1_cmp_io_sync_en_c1t; | |
3227 | wire stg1_db0_clk_stop_c1b; | |
3228 | wire stg1_dmu_io_clk_stop_c1b; | |
3229 | wire stg1_dmu_peu_por_c1b; | |
3230 | wire stg1_dmu_peu_wmr_c1b; | |
3231 | wire stg1_dr_sync_en_c1t; | |
3232 | wire stg1_io2x_out_c1b; | |
3233 | wire stg1_io_cmp_sync_en_c1b; | |
3234 | wire stg1_io_cmp_sync_en_c1t; | |
3235 | wire stg1_io_out_c1b; | |
3236 | wire stg1_io_out_c1t; | |
3237 | wire stg1_rst_l2_por_c1b; | |
3238 | wire stg1_rst_l2_por_c1t; | |
3239 | wire stg1_rst_l2_wmr_c1b; | |
3240 | wire stg1_rst_l2_wmr_c1t; | |
3241 | wire stg1_l2b0_clk_stop_c1t; | |
3242 | wire stg1_l2b1_clk_stop_c1t; | |
3243 | wire stg1_l2b2_clk_stop_c1b; | |
3244 | wire stg1_l2b3_clk_stop_c1b; | |
3245 | wire stg1_l2b4_clk_stop_c1t; | |
3246 | wire stg1_l2b5_clk_stop_c1t; | |
3247 | wire stg1_l2d0_clk_stop_c1t; | |
3248 | wire stg1_l2d1_clk_stop_c1t; | |
3249 | wire stg1_l2d2_clk_stop_c1b; | |
3250 | wire stg1_l2d3_clk_stop_c1b; | |
3251 | wire stg1_l2d4_clk_stop_c1t; | |
3252 | wire stg1_l2d5_clk_stop_c1t; | |
3253 | wire stg1_l2d7_clk_stop_c1b; | |
3254 | wire stg1_l2t0_clk_stop_c1t; | |
3255 | wire stg1_l2t1_clk_stop_c1t; | |
3256 | wire stg1_l2t2_clk_stop_c1b; | |
3257 | wire stg1_l2t3_clk_stop_c1b; | |
3258 | wire stg1_l2t5_clk_stop_c1t; | |
3259 | wire stg1_l2t7_clk_stop_c1b; | |
3260 | wire stg1_mac_io_clk_stop_c1b; | |
3261 | wire stg1_mcu0_clk_stop_c1t; | |
3262 | wire stg1_mcu0_dr_clk_stop_c1t; | |
3263 | wire stg1_mcu0_io_clk_stop_c1t; | |
3264 | wire stg1_mcu1_clk_stop_c1t; | |
3265 | wire stg1_mcu1_dr_clk_stop_c1t; | |
3266 | wire stg1_mcu1_io_clk_stop_c1t; | |
3267 | wire stg1_mio_clk_stop_c1t; | |
3268 | wire stg1_io2x_sync_en_c1t; | |
3269 | wire stg1_ncu_clk_stop_c1b; | |
3270 | wire stg1_ncu_io_clk_stop_c1b; | |
3271 | wire stg1_peu_io_clk_stop_c1b; | |
3272 | wire stg1_rdp_io_clk_stop_c1b; | |
3273 | wire stg1_rst_niu_mac_c1b; | |
3274 | wire stg1_rst_niu_wmr_c1b; | |
3275 | wire stg1_tds_io_clk_stop_c1b; | |
3276 | wire stg1_rtx_io_clk_stop_c1b; | |
3277 | wire stg1_sii_clk_stop_c1b; | |
3278 | wire stg1_sii_io_clk_stop_c1b; | |
3279 | wire stg4_cmp_io_sync_en_c3t; | |
3280 | wire stg4_io_cmp_sync_en_c3t; | |
3281 | wire stg4_io_out_c3b; | |
3282 | wire stg4_l2_por_c3t; | |
3283 | wire stg4_l2_wmr_c3t; | |
3284 | wire stg1_spc0_clk_stop_c1t; | |
3285 | wire stg1_spc1_clk_stop_c1t; | |
3286 | wire stg1_spc2_clk_stop_c1b; | |
3287 | wire stg1_spc3_clk_stop_c1b; | |
3288 | wire stg1_spc4_clk_stop_c1t; | |
3289 | wire stg1_spc5_clk_stop_c1t; | |
3290 | wire stg1_spc6_clk_stop_c1b; | |
3291 | wire stg1_spc7_clk_stop_c1b; | |
3292 | wire stg2_ccx_clk_stop_c1b; | |
3293 | wire stg2_cmp_io_sync_en_c1b; | |
3294 | wire stg2_cmp_io_sync_en_c1t; | |
3295 | wire stg2_db0_clk_stop_c1b; | |
3296 | wire stg2_dmu_io_clk_stop_c1b; | |
3297 | wire stg2_dmu_peu_por_c1b; | |
3298 | wire stg2_dmu_peu_wmr_c1b; | |
3299 | wire stg2_dr_sync_en_c1t; | |
3300 | wire stg2_io_cmp_sync_en_c1b; | |
3301 | wire stg2_io_cmp_sync_en_c1t; | |
3302 | wire stg2_io_out_c1t; | |
3303 | wire stg2_io_out_c1b; | |
3304 | wire stg2_l2_por_c1b; | |
3305 | wire stg2_l2_por_c1t; | |
3306 | wire stg2_l2_wmr_c1b; | |
3307 | wire stg2_l2_wmr_c1t; | |
3308 | wire stg2_l2b0_clk_stop_c1t; | |
3309 | wire stg2_l2b1_clk_stop_c1t; | |
3310 | wire stg2_l2b2_clk_stop_c1b; | |
3311 | wire stg2_l2b3_clk_stop_c1b; | |
3312 | wire stg2_l2d0_clk_stop_c1t; | |
3313 | wire stg2_l2d1_clk_stop_c1t; | |
3314 | wire stg2_l2d2_clk_stop_c1b; | |
3315 | wire stg2_l2d3_clk_stop_c1b; | |
3316 | wire stg2_l2t0_clk_stop_c1t; | |
3317 | wire stg2_l2t1_clk_stop_c1t; | |
3318 | wire stg2_l2t2_clk_stop_c1b; | |
3319 | wire stg2_l2t3_clk_stop_c1b; | |
3320 | wire stg2_l2t5_clk_stop_c1t; | |
3321 | wire stg2_l2t7_clk_stop_c1b; | |
3322 | wire stg2_mio_io2x_sync_en_c1t; | |
3323 | wire stg2_mio_clk_stop_c1t; | |
3324 | wire stg2_ncu_clk_stop_c1b; | |
3325 | wire stg2_ncu_io_clk_stop_c1b; | |
3326 | wire stg2_peu_io_clk_stop_c1b; | |
3327 | wire stg2_sii_clk_stop_c1b; | |
3328 | wire stg2_sii_io_clk_stop_c1b; | |
3329 | wire stg2_spc0_clk_stop_c1t; | |
3330 | wire stg2_spc1_clk_stop_c1t; | |
3331 | wire stg2_spc2_clk_stop_c1b; | |
3332 | wire stg2_spc3_clk_stop_c1b; | |
3333 | wire stg2_spc5_clk_stop_c1t; | |
3334 | wire stg2_spc7_clk_stop_c1b; | |
3335 | wire stg3_ccx_clk_stop_c2b; | |
3336 | wire stg3_cmp_io_sync_en_c2b; | |
3337 | wire stg3_cmp_io_sync_en_c2t; | |
3338 | wire stg3_db0_clk_stop_c2b; | |
3339 | wire stg3_dmu_io_clk_stop_c2b; | |
3340 | wire stg3_dmu_peu_por_c2b; | |
3341 | wire stg3_dmu_peu_wmr_c2b; | |
3342 | wire stg3_dr_sync_en_c2t; | |
3343 | wire stg3_mio_io2x_sync_en_c2t; | |
3344 | wire stg3_io_cmp_sync_en_c2b; | |
3345 | wire stg3_io_cmp_sync_en_c2t; | |
3346 | wire stg3_io_out_c2b; | |
3347 | wire stg3_io_out_c2t; | |
3348 | wire stg3_l2_por_c2b; | |
3349 | wire stg3_l2_por_c2t; | |
3350 | wire stg3_l2_wmr_c2b; | |
3351 | wire stg3_l2_wmr_c2t; | |
3352 | wire stg3_l2b0_clk_stop_c2t; | |
3353 | wire stg3_l2b1_clk_stop_c2t; | |
3354 | wire stg3_l2b2_clk_stop_c2b; | |
3355 | wire stg3_l2b3_clk_stop_c2b; | |
3356 | wire stg3_l2d0_clk_stop_c2t; | |
3357 | wire stg3_l2d1_clk_stop_c2t; | |
3358 | wire stg3_l2d2_clk_stop_c2b; | |
3359 | wire stg3_l2d3_clk_stop_c2b; | |
3360 | wire stg3_l2t0_clk_stop_c2t; | |
3361 | wire stg3_l2t1_clk_stop_c2t; | |
3362 | wire stg3_l2t2_clk_stop_c2b; | |
3363 | wire stg3_l2t3_clk_stop_c2b; | |
3364 | wire stg3_l2t5_clk_stop_c2t; | |
3365 | wire stg3_l2t7_clk_stop_c2b; | |
3366 | wire stg3_mcu0_clk_stop_c2t; | |
3367 | wire stg2_mcu0_dr_clk_stop_c2b; | |
3368 | wire stg3_mcu0_io_clk_stop_c2t; | |
3369 | wire stg3_mcu1_clk_stop_c2t; | |
3370 | wire stg2_mcu1_dr_clk_stop_c2b; | |
3371 | wire stg3_mcu1_io_clk_stop_c2t; | |
3372 | wire stg3_mio_clk_stop_c2t; | |
3373 | wire stg3_ncu_clk_stop_c2b; | |
3374 | wire stg3_ncu_io_clk_stop_c2b; | |
3375 | wire stg3_peu_io_clk_stop_c2b; | |
3376 | wire stg3_sii_clk_stop_c2b; | |
3377 | wire stg3_sii_io_clk_stop_c2b; | |
3378 | wire stg3_spc0_clk_stop_c2t; | |
3379 | wire stg3_spc1_clk_stop_c2t; | |
3380 | wire stg3_spc2_clk_stop_c2b; | |
3381 | wire stg3_spc3_clk_stop_c2b; | |
3382 | wire stg3_spc5_clk_stop_c2t; | |
3383 | wire stg3_spc7_clk_stop_c2b; | |
3384 | wire stg4_cmp_io_sync_en_c3b; | |
3385 | wire stg4_db0_clk_stop_c3b; | |
3386 | wire stg4_dmu_io_clk_stop_c3b; | |
3387 | wire stg4_dmu_peu_por_c3b; | |
3388 | wire stg4_dmu_peu_wmr_c3b; | |
3389 | wire stg4_dr_sync_en_c3t; | |
3390 | wire stg4_mio_io2x_sync_en_c3t; | |
3391 | wire stg4_io_cmp_sync_en_c3b; | |
3392 | wire stg4_io_out_c3t; | |
3393 | wire stg4_l2_por_c3b; | |
3394 | wire stg4_l2_wmr_c3b; | |
3395 | wire stg4_l2b0_clk_stop_c3t; | |
3396 | wire stg4_l2b1_clk_stop_c3t; | |
3397 | wire stg4_l2b2_clk_stop_c3b; | |
3398 | wire stg4_l2b3_clk_stop_c3b; | |
3399 | wire stg4_l2d0_clk_stop_c3t; | |
3400 | wire stg4_l2d1_clk_stop_c3t; | |
3401 | wire stg4_l2d2_clk_stop_c3b; | |
3402 | wire stg4_l2d3_clk_stop_c3b; | |
3403 | wire stg4_l2t0_clk_stop_c3t; | |
3404 | wire stg4_l2t2_clk_stop_c3b; | |
3405 | wire stg4_mcu0_clk_stop_c3t; | |
3406 | wire stg4_mcu0_io_clk_stop_c3t; | |
3407 | wire stg4_mcu1_clk_stop_c3t; | |
3408 | wire stg4_mcu1_io_clk_stop_c3t; | |
3409 | wire stg4_mio_clk_stop_c3t; | |
3410 | wire stg4_ncu_clk_stop_c3b; | |
3411 | wire stg4_ncu_io_clk_stop_c3b; | |
3412 | wire stg4_peu_io_clk_stop_c3b; | |
3413 | wire stg4_sii_clk_stop_c3b; | |
3414 | wire stg4_sii_io_clk_stop_c3b; | |
3415 | wire stg4_spc0_clk_stop_c3t; | |
3416 | wire stg4_spc2_clk_stop_c3b; | |
3417 | wire stg2_mcu0_io_clk_stop_c1t; | |
3418 | wire stg2_mcu1_io_clk_stop_c1t; | |
3419 | wire stg1_io2x_sync_en_c1b; | |
3420 | wire stg2_mcu0_clk_stop_c1t; | |
3421 | wire stg2_mcu1_clk_stop_c1t; | |
3422 | wire stg3_io2x_sync_en_c2t; | |
3423 | wire tcu_atpg_mode; | |
3424 | wire ccu_mio_serdes_dtm; | |
3425 | wire tcu_mio_tdo; | |
3426 | wire tcu_mio_tdo_en; | |
3427 | wire tcu_mio_stciq; | |
3428 | wire mio_tcu_stcid; | |
3429 | wire [1:0] mio_tcu_stcicfg; | |
3430 | wire mio_tcu_stciclk; | |
3431 | wire mio_tcu_divider_bypass; | |
3432 | wire mio_tcu_pll_cmp_bypass; | |
3433 | wire mio_tcu_scan_in31; | |
3434 | wire tcu_mio_scan_out31; | |
3435 | wire [7:0] peu_mio_debug_bus_a; | |
3436 | wire [7:0] peu_mio_debug_bus_b; | |
3437 | wire [63:0] peu_mio_pipe_txdata; | |
3438 | wire [7:0] peu_mio_pipe_txdatak; | |
3439 | wire peu_mio_debug_clk; | |
3440 | wire mio_ccu_pll_char_in; | |
3441 | wire [5:0] mio_ccu_pll_div2; | |
3442 | wire mio_ccu_pll_trst_l; | |
3443 | wire mio_ccu_pll_clamp_fltr; | |
3444 | wire [6:0] mio_ccu_pll_div4; | |
3445 | wire mio_ext_dr_clk; | |
3446 | wire mio_ext_cmp_clk; | |
3447 | wire [1:0] ccu_mio_pll_char_out; | |
3448 | wire mio_tcu_io_ac_testmode; | |
3449 | wire mio_tcu_io_ac_testtrig; | |
3450 | wire mio_tcu_io_aclk; | |
3451 | wire mio_tcu_io_bclk; | |
3452 | wire [30:0] mio_tcu_io_scan_in; | |
3453 | wire mio_tcu_peu_clk_ext; | |
3454 | wire [5:0] mio_tcu_niu_clk_ext; | |
3455 | wire mio_tcu_io_scan_en; | |
3456 | wire [30:0] tcu_mio_pins_scan_out; | |
3457 | wire [39:0] tcu_mio_dmo_data; | |
3458 | wire tcu_mio_mbist_done; | |
3459 | wire tcu_mio_mbist_fail; | |
3460 | wire tcu_mio_dmo_sync; | |
3461 | wire mio_tcu_trigin; | |
3462 | wire tcu_mio_trigout; | |
3463 | wire rst_mio_pex_reset_l; | |
3464 | wire [5:0] rst_mio_rst_state; | |
3465 | wire mio_rst_pb_rst_l; | |
3466 | wire mio_rst_button_xir_l; | |
3467 | wire mio_rst_pwron_rst_l; | |
3468 | wire ncu_mio_ssi_mosi; | |
3469 | wire mio_ncu_ssi_miso; | |
3470 | wire ncu_mio_ssi_sck; | |
3471 | wire mio_ncu_ext_int_l; | |
3472 | wire rst_mio_ssi_sync_l; | |
3473 | wire tcu_mio_bs_scan_in; | |
3474 | wire tcu_mio_bs_highz_l; | |
3475 | wire mio_tcu_bs_scan_out; | |
3476 | wire tcu_mio_bs_scan_en; | |
3477 | wire tcu_mio_bs_clk; | |
3478 | wire tcu_mio_bs_aclk; | |
3479 | wire tcu_mio_bs_bclk; | |
3480 | wire tcu_mio_bs_uclk; | |
3481 | wire tcu_mio_bs_mode_ctl; | |
3482 | wire tcu_dbr_gateoff; | |
3483 | wire ncu_spc_l2_idx_hash_en; | |
3484 | wire cmp_gclk_c2_ccx_left; | |
3485 | wire cmp_gclk_c2_ccx_right; | |
3486 | wire ncu_l2t_pm; | |
3487 | wire ncu_l2t_ba01; | |
3488 | wire ncu_l2t_ba23; | |
3489 | wire ncu_l2t_ba45; | |
3490 | wire ncu_l2t_ba67; | |
3491 | wire ncu_mcu_pm; | |
3492 | wire ncu_mcu_ba01; | |
3493 | wire ncu_mcu_ba23; | |
3494 | wire ncu_mcu_ba45; | |
3495 | wire ncu_mcu_ba67; | |
3496 | wire rst_mcu_selfrsh; | |
3497 | wire tcu_mcu_testmode; | |
3498 | wire ccu_serdes_dtm; | |
3499 | wire tcu_sii_mbist_scan_in; | |
3500 | wire sii_tcu_mbist_scan_out; | |
3501 | wire ncu_sii_niuctag_uei; | |
3502 | wire ncu_sii_niuctag_cei; | |
3503 | wire ncu_sii_niua_pei; | |
3504 | wire ncu_sii_niud_pei; | |
3505 | wire ncu_sii_dmuctag_uei; | |
3506 | wire ncu_sii_dmuctag_cei; | |
3507 | wire ncu_sii_dmua_pei; | |
3508 | wire ncu_sii_dmud_pei; | |
3509 | wire ncu_sii_gnt; | |
3510 | wire ncu_sii_pm; | |
3511 | wire ncu_sii_ba01; | |
3512 | wire ncu_sii_ba23; | |
3513 | wire ncu_sii_ba45; | |
3514 | wire ncu_sii_ba67; | |
3515 | wire ncu_sii_l2_idx_hash_en; | |
3516 | wire sii_ncu_niuctag_ue; | |
3517 | wire sii_ncu_niuctag_ce; | |
3518 | wire sii_ncu_niua_pe; | |
3519 | wire sii_ncu_niud_pe; | |
3520 | wire sii_ncu_dmuctag_ue; | |
3521 | wire sii_ncu_dmuctag_ce; | |
3522 | wire sii_ncu_dmua_pe; | |
3523 | wire sii_ncu_dmud_pe; | |
3524 | wire [3:0] sii_ncu_syn_data; | |
3525 | wire sii_ncu_syn_vld; | |
3526 | wire [1:0] sii_ncu_dparity; | |
3527 | wire [31:0] sii_ncu_data; | |
3528 | wire sii_ncu_req; | |
3529 | wire [7:0] dmu_sii_parity; | |
3530 | wire dmu_sii_be_parity; | |
3531 | wire sii_dmu_wrack_vld; | |
3532 | wire [3:0] sii_dmu_wrack_tag; | |
3533 | wire sio_sii_opcc_ipcc_niu_by_deq; | |
3534 | wire [3:0] sio_sii_opcc_ipcc_niu_by_cnt; | |
3535 | wire sio_sii_opcc_ipcc_niu_or_deq; | |
3536 | wire sio_sii_opcc_ipcc_dmu_by_deq; | |
3537 | wire [3:0] sio_sii_opcc_ipcc_dmu_by_cnt; | |
3538 | wire sio_sii_opcc_ipcc_dmu_or_deq; | |
3539 | wire sio_sii_olc0_ilc0_dequeue; | |
3540 | wire sio_sii_olc1_ilc1_dequeue; | |
3541 | wire sio_sii_olc2_ilc2_dequeue; | |
3542 | wire sio_sii_olc3_ilc3_dequeue; | |
3543 | wire sio_sii_olc4_ilc4_dequeue; | |
3544 | wire sio_sii_olc5_ilc5_dequeue; | |
3545 | wire sio_sii_olc6_ilc6_dequeue; | |
3546 | wire sio_sii_olc7_ilc7_dequeue; | |
3547 | wire sio_tcu_vld; | |
3548 | wire sio_tcu_data; | |
3549 | wire [1:0] tcu_sio_mbist_start; | |
3550 | wire [1:0] sio_tcu_mbist_done; | |
3551 | wire [1:0] sio_tcu_mbist_fail; | |
3552 | wire tcu_sio_mbist_scan_in; | |
3553 | wire sio_tcu_mbist_scan_out; | |
3554 | wire sio_dmu_hdr_vld; | |
3555 | wire [127:0] sio_dmu_data; | |
3556 | wire [7:0] sio_dmu_parity; | |
3557 | wire sio_ncu_ctag_ue; | |
3558 | wire sio_ncu_ctag_ce; | |
3559 | wire ncu_sio_ctag_cei; | |
3560 | wire ncu_sio_ctag_uei; | |
3561 | wire ncu_sio_d_pei; | |
3562 | wire tcu_ncu_mbist_scan_in; | |
3563 | wire ncu_tcu_mbist_scan_out; | |
3564 | wire [63:0] ncu_dmu_pio_data; | |
3565 | wire ncu_dmu_pio_hdr_vld; | |
3566 | wire ncu_dmu_mmu_addr_vld; | |
3567 | wire ncu_dmu_mondo_ack; | |
3568 | wire ncu_dmu_mondo_nack; | |
3569 | wire [5:0] ncu_dmu_mondo_id; | |
3570 | wire ncu_dmu_vld; | |
3571 | wire [31:0] ncu_dmu_data; | |
3572 | wire ncu_dmu_stall; | |
3573 | wire ncu_ccu_vld; | |
3574 | wire [3:0] ncu_ccu_data; | |
3575 | wire [3:0] ccu_ncu_data; | |
3576 | wire ccu_ncu_vld; | |
3577 | wire ccu_ncu_stall; | |
3578 | wire ncu_ccu_stall; | |
3579 | wire ncu_tcu_vld; | |
3580 | wire [7:0] ncu_tcu_data; | |
3581 | wire tcu_ncu_stall; | |
3582 | wire tcu_ncu_vld; | |
3583 | wire [7:0] tcu_ncu_data; | |
3584 | wire ncu_tcu_stall; | |
3585 | wire ncu_rst_vld; | |
3586 | wire [3:0] ncu_rst_data; | |
3587 | wire rst_ncu_stall; | |
3588 | wire rst_ncu_vld; | |
3589 | wire [3:0] rst_ncu_data; | |
3590 | wire ncu_rst_stall; | |
3591 | wire efu_ncu_fuse_data; | |
3592 | wire efu_ncu_srlnum0_xfer_en; | |
3593 | wire efu_ncu_srlnum1_xfer_en; | |
3594 | wire efu_ncu_srlnum2_xfer_en; | |
3595 | wire efu_ncu_fusestat_xfer_en; | |
3596 | wire efu_ncu_coreavl_xfer_en; | |
3597 | wire efu_ncu_bankavl_xfer_en; | |
3598 | wire rst_ncu_unpark_thread; | |
3599 | wire rst_ncu_xir_; | |
3600 | wire ncu_rst_xir_done; | |
3601 | wire ncu_spc0_core_available; | |
3602 | wire ncu_spc1_core_available; | |
3603 | wire ncu_spc2_core_available; | |
3604 | wire ncu_spc3_core_available; | |
3605 | wire ncu_spc4_core_available; | |
3606 | wire ncu_spc5_core_available; | |
3607 | wire ncu_spc6_core_available; | |
3608 | wire ncu_spc7_core_available; | |
3609 | wire ncu_rst_fatal_error; | |
3610 | wire [7:0] ncu_tcu_bank_avail; | |
3611 | wire tcu_sck_bypass; | |
3612 | wire dmu_ncu_wrack_par; | |
3613 | wire ncu_dmu_mondo_id_par; | |
3614 | wire dmu_ncu_d_pe; | |
3615 | wire ncu_dmu_d_pei; | |
3616 | wire dmu_ncu_siicr_pe; | |
3617 | wire ncu_dmu_siicr_pei; | |
3618 | wire dmu_ncu_ctag_ue; | |
3619 | wire ncu_dmu_ctag_uei; | |
3620 | wire dmu_ncu_ctag_ce; | |
3621 | wire ncu_dmu_ctag_cei; | |
3622 | wire dmu_ncu_ncucr_pe; | |
3623 | wire ncu_dmu_ncucr_pei; | |
3624 | wire dmu_ncu_ie; | |
3625 | wire ncu_dmu_iei; | |
3626 | wire efu_dmu_data; | |
3627 | wire efu_dmu_xfer_en; | |
3628 | wire efu_dmu_clr; | |
3629 | wire dmu_efu_xfer_en; | |
3630 | wire dmu_efu_data; | |
3631 | wire rng_data; | |
3632 | wire ccu_vco_aligned; | |
3633 | wire gclk_aligned; | |
3634 | wire ccu_cmp_io_sync_en; | |
3635 | wire ccu_io_cmp_sync_en; | |
3636 | wire ccu_io2x_sync_en; | |
3637 | wire ccu_dr_sync_en; | |
3638 | wire ccu_io2x_out; | |
3639 | wire ccu_io_out; | |
3640 | wire gl_ccu_io_clk_stop; | |
3641 | wire gl_ccu_clk_stop; | |
3642 | wire [1:0] tcu_ccu_mux_sel; | |
3643 | wire tcu_ccu_ext_cmp_clk; | |
3644 | wire tcu_ccu_ext_dr_clk; | |
3645 | wire tcu_ccu_clk_stretch; | |
3646 | wire rst_ccu_pll_; | |
3647 | wire rst_ccu_; | |
3648 | wire ccu_rst_change; | |
3649 | wire ccu_rst_sys_clk; | |
3650 | wire ccu_rst_sync_stable; | |
3651 | wire ccu_sys_cmp_sync_en; | |
3652 | wire ccu_cmp_sys_sync_en; | |
3653 | wire tcu_ccu_clk_stop; | |
3654 | wire tcu_ccu_io_clk_stop; | |
3655 | wire [3:0] jtag_revid_out; | |
3656 | wire tcu_spc0_clk_stop; | |
3657 | wire tcu_spc1_clk_stop; | |
3658 | wire tcu_spc2_clk_stop; | |
3659 | wire tcu_spc3_clk_stop; | |
3660 | wire tcu_spc4_clk_stop; | |
3661 | wire tcu_spc5_clk_stop; | |
3662 | wire tcu_spc6_clk_stop; | |
3663 | wire tcu_spc7_clk_stop; | |
3664 | wire tcu_l2d0_clk_stop; | |
3665 | wire tcu_l2d1_clk_stop; | |
3666 | wire tcu_l2d2_clk_stop; | |
3667 | wire tcu_l2d3_clk_stop; | |
3668 | wire tcu_l2d4_clk_stop; | |
3669 | wire tcu_l2d5_clk_stop; | |
3670 | wire tcu_l2d6_clk_stop; | |
3671 | wire tcu_l2d7_clk_stop; | |
3672 | wire tcu_l2t0_clk_stop; | |
3673 | wire tcu_l2t1_clk_stop; | |
3674 | wire tcu_l2t2_clk_stop; | |
3675 | wire tcu_l2t3_clk_stop; | |
3676 | wire tcu_l2t4_clk_stop; | |
3677 | wire tcu_l2t5_clk_stop; | |
3678 | wire tcu_l2t6_clk_stop; | |
3679 | wire tcu_l2t7_clk_stop; | |
3680 | wire tcu_l2b0_clk_stop; | |
3681 | wire tcu_l2b1_clk_stop; | |
3682 | wire tcu_l2b2_clk_stop; | |
3683 | wire tcu_l2b3_clk_stop; | |
3684 | wire tcu_l2b4_clk_stop; | |
3685 | wire tcu_l2b5_clk_stop; | |
3686 | wire tcu_l2b6_clk_stop; | |
3687 | wire tcu_l2b7_clk_stop; | |
3688 | wire tcu_mcu0_clk_stop; | |
3689 | wire tcu_mcu0_dr_clk_stop; | |
3690 | wire tcu_mcu0_io_clk_stop; | |
3691 | wire tcu_mcu1_clk_stop; | |
3692 | wire tcu_mcu1_dr_clk_stop; | |
3693 | wire tcu_mcu1_io_clk_stop; | |
3694 | wire tcu_mcu2_clk_stop; | |
3695 | wire tcu_mcu2_dr_clk_stop; | |
3696 | wire tcu_mcu2_io_clk_stop; | |
3697 | wire tcu_mcu3_clk_stop; | |
3698 | wire tcu_mcu3_dr_clk_stop; | |
3699 | wire tcu_mcu3_io_clk_stop; | |
3700 | wire tcu_ccx_clk_stop; | |
3701 | wire tcu_sii_clk_stop; | |
3702 | wire tcu_sii_io_clk_stop; | |
3703 | wire tcu_sio_clk_stop; | |
3704 | wire tcu_sio_io_clk_stop; | |
3705 | wire tcu_ncu_clk_stop; | |
3706 | wire tcu_ncu_io_clk_stop; | |
3707 | wire tcu_efu_clk_stop; | |
3708 | wire tcu_efu_io_clk_stop; | |
3709 | wire tcu_rst_clk_stop; | |
3710 | wire tcu_rst_io_clk_stop; | |
3711 | wire tcu_dmu_io_clk_stop; | |
3712 | wire tcu_rdp_io_clk_stop; | |
3713 | wire tcu_mac_io_clk_stop; | |
3714 | wire tcu_rtx_io_clk_stop; | |
3715 | wire tcu_tds_io_clk_stop; | |
3716 | wire tcu_peu_pc_clk_stop; | |
3717 | wire tcu_peu_io_clk_stop; | |
3718 | wire tcu_rst_efu_done; | |
3719 | wire tcu_test_protect; | |
3720 | wire [1:0] tcu_dmu_mbist_start; | |
3721 | wire tcu_dmu_mbist_scan_in; | |
3722 | wire [1:0] dmu_tcu_mbist_done; | |
3723 | wire [1:0] dmu_tcu_mbist_fail; | |
3724 | wire dmu_tcu_mbist_scan_out; | |
3725 | wire tcu_peu_mbist_start; | |
3726 | wire tcu_peu_mbist_scan_in; | |
3727 | wire peu_tcu_mbist_done; | |
3728 | wire peu_tcu_mbist_fail; | |
3729 | wire peu_tcu_mbist_scan_out; | |
3730 | wire rst_tcu_flush_init_req; | |
3731 | wire rst_tcu_flush_stop_req; | |
3732 | wire rst_tcu_asicflush_stop_req; | |
3733 | wire tcu_rst_asicflush_stop_ack; | |
3734 | wire tcu_rst_flush_init_ack; | |
3735 | wire tcu_rst_flush_stop_ack; | |
3736 | wire tcu_bisx_done; | |
3737 | wire tcu_rst_scan_mode; | |
3738 | wire rst_tcu_clk_stop; | |
3739 | wire rst_tcu_dbr_gen; | |
3740 | wire tcu_mio_clk_stop; | |
3741 | wire tcu_peu_entestcfg; | |
3742 | wire tcu_peu_clk_ext; | |
3743 | wire tcu_peu_testmode; | |
3744 | wire tcu_db0_clk_stop; | |
3745 | wire tcu_db1_clk_stop; | |
3746 | wire p2d_ce_int; | |
3747 | wire p2d_csr_ack; | |
3748 | wire [95:0] p2d_csr_rcd; | |
3749 | wire p2d_csr_req; | |
3750 | wire p2d_cto_req; | |
3751 | wire [4:0] p2d_cto_tag; | |
3752 | wire p2d_drain; | |
3753 | wire [7:0] p2d_ecd_rptr; | |
3754 | wire [5:0] p2d_ech_rptr; | |
3755 | wire [7:0] p2d_erd_rptr; | |
3756 | wire [5:0] p2d_erh_rptr; | |
3757 | wire p2d_ibc_ack; | |
3758 | wire [127:0] p2d_idb_data; | |
3759 | wire [3:0] p2d_idb_dpar; | |
3760 | wire [127:0] p2d_ihb_data; | |
3761 | wire [3:0] p2d_ihb_dpar; | |
3762 | wire d2p_ihb_rd; | |
3763 | wire d2p_idb_rd; | |
3764 | wire [6:0] p2d_ihb_wptr; | |
3765 | wire [2:0] p2d_mps; | |
3766 | wire p2d_oe_int; | |
3767 | wire [4:0] p2d_spare; | |
3768 | wire p2d_ue_int; | |
3769 | wire p2d_npwr_stall_en; | |
3770 | wire rst_dmu_async_por_; | |
3771 | wire d2p_csr_ack; | |
3772 | wire [95:0] d2p_csr_rcd; | |
3773 | wire d2p_csr_req; | |
3774 | wire d2p_cto_ack; | |
3775 | wire [5:0] d2p_ech_wptr; | |
3776 | wire [7:0] d2p_edb_addr; | |
3777 | wire [127:0] d2p_edb_data; | |
3778 | wire [3:0] d2p_edb_dpar; | |
3779 | wire d2p_edb_we; | |
3780 | wire [5:0] d2p_ehb_addr; | |
3781 | wire [127:0] d2p_ehb_data; | |
3782 | wire [3:0] d2p_ehb_dpar; | |
3783 | wire d2p_ehb_we; | |
3784 | wire [5:0] d2p_erh_wptr; | |
3785 | wire [7:0] d2p_ibc_nhc; | |
3786 | wire [11:0] d2p_ibc_pdc; | |
3787 | wire [7:0] d2p_ibc_phc; | |
3788 | wire d2p_ibc_req; | |
3789 | wire [7:0] d2p_idb_addr; | |
3790 | wire [5:0] d2p_ihb_addr; | |
3791 | wire [4:0] d2p_spare; | |
3792 | wire dmu_psr_pll_en_sds0; | |
3793 | wire dmu_psr_pll_en_sds1; | |
3794 | wire dmu_psr_rx_en_b0_sds0; | |
3795 | wire dmu_psr_rx_en_b1_sds0; | |
3796 | wire dmu_psr_rx_en_b2_sds0; | |
3797 | wire dmu_psr_rx_en_b3_sds0; | |
3798 | wire dmu_psr_rx_en_b0_sds1; | |
3799 | wire dmu_psr_rx_en_b1_sds1; | |
3800 | wire dmu_psr_rx_en_b2_sds1; | |
3801 | wire dmu_psr_rx_en_b3_sds1; | |
3802 | wire dmu_psr_tx_en_b0_sds0; | |
3803 | wire dmu_psr_tx_en_b1_sds0; | |
3804 | wire dmu_psr_tx_en_b2_sds0; | |
3805 | wire dmu_psr_tx_en_b3_sds0; | |
3806 | wire dmu_psr_tx_en_b0_sds1; | |
3807 | wire dmu_psr_tx_en_b1_sds1; | |
3808 | wire dmu_psr_tx_en_b2_sds1; | |
3809 | wire dmu_psr_tx_en_b3_sds1; | |
3810 | wire [15:0] d2p_req_id; | |
3811 | wire [9:0] psr_peu_rd_b0sds0; | |
3812 | wire [9:0] psr_peu_rd_b1sds0; | |
3813 | wire [9:0] psr_peu_rd_b2sds0; | |
3814 | wire [9:0] psr_peu_rd_b3sds0; | |
3815 | wire [9:0] psr_peu_rd_b0sds1; | |
3816 | wire [9:0] psr_peu_rd_b1sds1; | |
3817 | wire [9:0] psr_peu_rd_b2sds1; | |
3818 | wire [9:0] psr_peu_rd_b3sds1; | |
3819 | wire psr_peu_bsrxn_b0sds0; | |
3820 | wire psr_peu_bsrxn_b1sds0; | |
3821 | wire psr_peu_bsrxn_b2sds0; | |
3822 | wire psr_peu_bsrxn_b3sds0; | |
3823 | wire psr_peu_bsrxn_b0sds1; | |
3824 | wire psr_peu_bsrxn_b1sds1; | |
3825 | wire psr_peu_bsrxn_b2sds1; | |
3826 | wire psr_peu_bsrxn_b3sds1; | |
3827 | wire psr_peu_bsrxp_b0sds0; | |
3828 | wire psr_peu_bsrxp_b1sds0; | |
3829 | wire psr_peu_bsrxp_b2sds0; | |
3830 | wire psr_peu_bsrxp_b3sds0; | |
3831 | wire psr_peu_bsrxp_b0sds1; | |
3832 | wire psr_peu_bsrxp_b1sds1; | |
3833 | wire psr_peu_bsrxp_b2sds1; | |
3834 | wire psr_peu_bsrxp_b3sds1; | |
3835 | wire psr_peu_losdtct_b0sds0; | |
3836 | wire psr_peu_losdtct_b1sds0; | |
3837 | wire psr_peu_losdtct_b2sds0; | |
3838 | wire psr_peu_losdtct_b3sds0; | |
3839 | wire psr_peu_losdtct_b0sds1; | |
3840 | wire psr_peu_losdtct_b1sds1; | |
3841 | wire psr_peu_losdtct_b2sds1; | |
3842 | wire psr_peu_losdtct_b3sds1; | |
3843 | wire psr_peu_sync_b0sds0; | |
3844 | wire psr_peu_sync_b1sds0; | |
3845 | wire psr_peu_sync_b2sds0; | |
3846 | wire psr_peu_sync_b3sds0; | |
3847 | wire psr_peu_sync_b0sds1; | |
3848 | wire psr_peu_sync_b1sds1; | |
3849 | wire psr_peu_sync_b2sds1; | |
3850 | wire psr_peu_sync_b3sds1; | |
3851 | wire psr_peu_rx_tstfail_b0sds0; | |
3852 | wire psr_peu_rx_tstfail_b1sds0; | |
3853 | wire psr_peu_rx_tstfail_b2sds0; | |
3854 | wire psr_peu_rx_tstfail_b3sds0; | |
3855 | wire psr_peu_rx_tstfail_b0sds1; | |
3856 | wire psr_peu_rx_tstfail_b1sds1; | |
3857 | wire psr_peu_rx_tstfail_b2sds1; | |
3858 | wire psr_peu_rx_tstfail_b3sds1; | |
3859 | wire psr_peu_rdtcip_b0sds0; | |
3860 | wire psr_peu_rdtcip_b1sds0; | |
3861 | wire psr_peu_rdtcip_b2sds0; | |
3862 | wire psr_peu_rdtcip_b3sds0; | |
3863 | wire psr_peu_rdtcip_b0sds1; | |
3864 | wire psr_peu_rdtcip_b1sds1; | |
3865 | wire psr_peu_rdtcip_b2sds1; | |
3866 | wire psr_peu_rdtcip_b3sds1; | |
3867 | wire psr_peu_tx_tstfail_b0sds0; | |
3868 | wire psr_peu_tx_tstfail_b1sds0; | |
3869 | wire psr_peu_tx_tstfail_b2sds0; | |
3870 | wire psr_peu_tx_tstfail_b3sds0; | |
3871 | wire psr_peu_tx_tstfail_b0sds1; | |
3872 | wire psr_peu_tx_tstfail_b1sds1; | |
3873 | wire psr_peu_tx_tstfail_b2sds1; | |
3874 | wire psr_peu_tx_tstfail_b3sds1; | |
3875 | wire psr_peu_lock_sds0; | |
3876 | wire psr_peu_lock_sds1; | |
3877 | wire [9:0] peu_psr_td_b0sds0; | |
3878 | wire [9:0] peu_psr_td_b1sds0; | |
3879 | wire [9:0] peu_psr_td_b2sds0; | |
3880 | wire [9:0] peu_psr_td_b3sds0; | |
3881 | wire [9:0] peu_psr_td_b0sds1; | |
3882 | wire [9:0] peu_psr_td_b1sds1; | |
3883 | wire [9:0] peu_psr_td_b2sds1; | |
3884 | wire [9:0] peu_psr_td_b3sds1; | |
3885 | wire peu_psr_invpair_b0sds0; | |
3886 | wire peu_psr_invpair_b1sds0; | |
3887 | wire peu_psr_invpair_b2sds0; | |
3888 | wire peu_psr_invpair_b3sds0; | |
3889 | wire peu_psr_invpair_b0sds1; | |
3890 | wire peu_psr_invpair_b1sds1; | |
3891 | wire peu_psr_invpair_b2sds1; | |
3892 | wire peu_psr_invpair_b3sds1; | |
3893 | wire [15:0] peu_psr_rx_lane_ctl_0; | |
3894 | wire [15:0] peu_psr_rx_lane_ctl_1; | |
3895 | wire [15:0] peu_psr_rx_lane_ctl_2; | |
3896 | wire [15:0] peu_psr_rx_lane_ctl_3; | |
3897 | wire [15:0] peu_psr_rx_lane_ctl_4; | |
3898 | wire [15:0] peu_psr_rx_lane_ctl_5; | |
3899 | wire [15:0] peu_psr_rx_lane_ctl_6; | |
3900 | wire [15:0] peu_psr_rx_lane_ctl_7; | |
3901 | wire [1:0] peu_psr_rdtct_b0sds0; | |
3902 | wire [1:0] peu_psr_rdtct_b1sds0; | |
3903 | wire [1:0] peu_psr_rdtct_b2sds0; | |
3904 | wire [1:0] peu_psr_rdtct_b3sds0; | |
3905 | wire [1:0] peu_psr_rdtct_b0sds1; | |
3906 | wire [1:0] peu_psr_rdtct_b1sds1; | |
3907 | wire [1:0] peu_psr_rdtct_b2sds1; | |
3908 | wire [1:0] peu_psr_rdtct_b3sds1; | |
3909 | wire peu_psr_enidl_b0sds0; | |
3910 | wire peu_psr_enidl_b1sds0; | |
3911 | wire peu_psr_enidl_b2sds0; | |
3912 | wire peu_psr_enidl_b3sds0; | |
3913 | wire peu_psr_enidl_b0sds1; | |
3914 | wire peu_psr_enidl_b1sds1; | |
3915 | wire peu_psr_enidl_b2sds1; | |
3916 | wire peu_psr_enidl_b3sds1; | |
3917 | wire peu_psr_bstx_b0sds0; | |
3918 | wire peu_psr_bstx_b1sds0; | |
3919 | wire peu_psr_bstx_b2sds0; | |
3920 | wire peu_psr_bstx_b3sds0; | |
3921 | wire peu_psr_bstx_b0sds1; | |
3922 | wire peu_psr_bstx_b1sds1; | |
3923 | wire peu_psr_bstx_b2sds1; | |
3924 | wire peu_psr_bstx_b3sds1; | |
3925 | wire [9:0] peu_psr_tx_lane_ctl_0; | |
3926 | wire [9:0] peu_psr_tx_lane_ctl_1; | |
3927 | wire [9:0] peu_psr_tx_lane_ctl_2; | |
3928 | wire [9:0] peu_psr_tx_lane_ctl_3; | |
3929 | wire [9:0] peu_psr_tx_lane_ctl_4; | |
3930 | wire [9:0] peu_psr_tx_lane_ctl_5; | |
3931 | wire [9:0] peu_psr_tx_lane_ctl_6; | |
3932 | wire [9:0] peu_psr_tx_lane_ctl_7; | |
3933 | wire [7:0] peu_psr_txbclkin; | |
3934 | wire [15:0] peu_psr_testcfg_sds0; | |
3935 | wire [15:0] peu_psr_testcfg_sds1; | |
3936 | wire rst_l2_por_; | |
3937 | wire rst_l2_wmr_; | |
3938 | wire rst_niu_mac_; | |
3939 | wire rst_niu_wmr_; | |
3940 | wire rst_dmu_peu_por_; | |
3941 | wire rst_dmu_peu_wmr_; | |
3942 | ||
3943 | ||
3944 | input [ 7 : 0 ] L2T_VNW; | |
3945 | input [ 7 : 0 ] SPC_VNW; | |
3946 | input [ 7 : 0 ] L2D_VNW0; | |
3947 | input [ 7 : 0 ] L2D_VNW1; | |
3948 | ||
3949 | output [ 9 : 0 ] FBDIMM0A_TX_P; | |
3950 | output [ 9 : 0 ] FBDIMM0A_TX_N; | |
3951 | input [ 13 : 0 ] FBDIMM0A_RX_P; | |
3952 | input [ 13 : 0 ] FBDIMM0A_RX_N; | |
3953 | output [ 2 : 0 ] FBDIMM0A_AMUX; | |
3954 | ||
3955 | output [ 9 : 0 ] FBDIMM0B_TX_P; | |
3956 | output [ 9 : 0 ] FBDIMM0B_TX_N; | |
3957 | input [ 13 : 0 ] FBDIMM0B_RX_P; | |
3958 | input [ 13 : 0 ] FBDIMM0B_RX_N; | |
3959 | output [ 2 : 0 ] FBDIMM0B_AMUX; | |
3960 | ||
3961 | output [ 9 : 0 ] FBDIMM1A_TX_P; | |
3962 | output [ 9 : 0 ] FBDIMM1A_TX_N; | |
3963 | input [ 13 : 0 ] FBDIMM1A_RX_P; | |
3964 | input [ 13 : 0 ] FBDIMM1A_RX_N; | |
3965 | output [ 2 : 0 ] FBDIMM1A_AMUX; | |
3966 | ||
3967 | output [ 9 : 0 ] FBDIMM1B_TX_P; | |
3968 | output [ 9 : 0 ] FBDIMM1B_TX_N; | |
3969 | input [ 13 : 0 ] FBDIMM1B_RX_P; | |
3970 | input [ 13 : 0 ] FBDIMM1B_RX_N; | |
3971 | output [ 2 : 0 ] FBDIMM1B_AMUX; | |
3972 | ||
3973 | output [ 9 : 0 ] FBDIMM2A_TX_P; | |
3974 | output [ 9 : 0 ] FBDIMM2A_TX_N; | |
3975 | input [ 13 : 0 ] FBDIMM2A_RX_P; | |
3976 | input [ 13 : 0 ] FBDIMM2A_RX_N; | |
3977 | output [ 2 : 0 ] FBDIMM2A_AMUX; | |
3978 | ||
3979 | output [ 9 : 0 ] FBDIMM2B_TX_P; | |
3980 | output [ 9 : 0 ] FBDIMM2B_TX_N; | |
3981 | input [ 13 : 0 ] FBDIMM2B_RX_P; | |
3982 | input [ 13 : 0 ] FBDIMM2B_RX_N; | |
3983 | output [ 2 : 0 ] FBDIMM2B_AMUX; | |
3984 | ||
3985 | output [ 9 : 0 ] FBDIMM3A_TX_P; | |
3986 | output [ 9 : 0 ] FBDIMM3A_TX_N; | |
3987 | input [ 13 : 0 ] FBDIMM3A_RX_P; | |
3988 | input [ 13 : 0 ] FBDIMM3A_RX_N; | |
3989 | output [ 2 : 0 ] FBDIMM3A_AMUX; | |
3990 | ||
3991 | output [ 9 : 0 ] FBDIMM3B_TX_P; | |
3992 | output [ 9 : 0 ] FBDIMM3B_TX_N; | |
3993 | input [ 13 : 0 ] FBDIMM3B_RX_P; | |
3994 | input [ 13 : 0 ] FBDIMM3B_RX_N; | |
3995 | output [ 2 : 0 ] FBDIMM3B_AMUX; | |
3996 | ||
3997 | input FBDIMM1_REFCLK_P; | |
3998 | input FBDIMM1_REFCLK_N; | |
3999 | input FBDIMM2_REFCLK_P; | |
4000 | input FBDIMM2_REFCLK_N; | |
4001 | input FBDIMM3_REFCLK_P; | |
4002 | input FBDIMM3_REFCLK_N; | |
4003 | ||
4004 | input VDDA_FSRL; | |
4005 | input VDDD_FSRL; | |
4006 | input VDDR_FSRL; | |
4007 | input VDDT_FSRL; | |
4008 | input VSSA_FSRL; | |
4009 | ||
4010 | input VDDA_FSRR; | |
4011 | input VDDD_FSRR; | |
4012 | input VDDR_FSRR; | |
4013 | input VDDT_FSRR; | |
4014 | input VSSA_FSRR; | |
4015 | ||
4016 | input VDDA_FSRB; | |
4017 | input VDDD_FSRB; | |
4018 | input VDDR_FSRB; | |
4019 | input VDDT_FSRB; | |
4020 | input VSSA_FSRB; | |
4021 | ||
4022 | // PCI-E Bumps | |
4023 | ||
4024 | output [ 7 : 0 ] PEX_TX_P ; | |
4025 | output [ 7 : 0 ] PEX_TX_N ; | |
4026 | input [ 7 : 0 ] PEX_RX_P ; | |
4027 | input [ 7 : 0 ] PEX_RX_N ; | |
4028 | input PEX_REFCLK_P ; | |
4029 | input PEX_REFCLK_N ; | |
4030 | output [ 1 : 0 ] PEX_AMUX ; | |
4031 | ||
4032 | input VDDT_PSR; // PAD | |
4033 | input VDDD_PSR; // PAD | |
4034 | input VDDC_PSR; // PAD | |
4035 | input VDDA_PSR; // PAD | |
4036 | input VDDR_PSR; // PAD | |
4037 | input VSSA_PSR; // PAD | |
4038 | ||
4039 | ||
4040 | output STCIQ; | |
4041 | input TESTCLKT; // moved out of NIU | |
4042 | input TESTCLKR; | |
4043 | input STCID; | |
4044 | //input PLL_DR_BYPASS; | |
4045 | input PLL_CMP_BYPASS; | |
4046 | input [ 1 : 0 ] STCICFG; | |
4047 | input STCICLK; | |
4048 | input PGRM_EN; | |
4049 | input VDDO_PCM; // PCM 1.5 Supply | |
4050 | ||
4051 | ||
4052 | //wire scan_in = 1'b0; | |
4053 | ||
4054 | `ifndef FC_NO_NIU_T2 | |
4055 | // NIU START | |
4056 | // Updated by on Sep_1_19_13_16.2005 | |
4057 | // start XAUI serdes IO Pads | |
4058 | // XAUI serdes IO Pads | |
4059 | output XAUI0_AMUX ; // PAD TI only. | |
4060 | output [ 3 : 0 ] XAUI0_TX_N ; // PAD | |
4061 | output [ 3 : 0 ] XAUI0_TX_P ; // PAD | |
4062 | input XAUI0_REFCLK_N ; // PAD | |
4063 | input XAUI0_REFCLK_P ; // PAD | |
4064 | input [ 3 : 0 ] XAUI0_RX_N ; // PAD | |
4065 | input [ 3 : 0 ] XAUI0_RX_P ; // PAD | |
4066 | output XAUI1_AMUX ; // PAD TI only. | |
4067 | output [ 3 : 0 ] XAUI1_TX_N ; // PAD | |
4068 | output [ 3 : 0 ] XAUI1_TX_P ; // PAD | |
4069 | input [ 3 : 0 ] XAUI1_RX_N ; // PAD | |
4070 | input [ 3 : 0 ] XAUI1_RX_P ; // PAD | |
4071 | ||
4072 | output XAUI0_LINK_LED; // PAD | |
4073 | output XAUI1_LINK_LED; // PAD | |
4074 | output XAUI0_ACT_LED; // PAD | |
4075 | output XAUI1_ACT_LED; // PAD | |
4076 | output XAUI_MDC; // PAD | |
4077 | inout XAUI_MDIO; // PAD | |
4078 | inout XAUI_MDINT1_L; // PAD, XAUI INterrupt 1 | |
4079 | inout XAUI_MDINT0_L; // PAD, XAUI INterrupt 0 | |
4080 | // inout [1:0] SPARE; // Spare PADs | |
4081 | ||
4082 | input VDDT_ESR; // PAD cc | |
4083 | input VDDA_ESR; // PAD cc | |
4084 | input VDDD_ESR; // PAD cc | |
4085 | input VDDR_ESR; // PAD cc | |
4086 | input VSSA_ESR; // PAD cc | |
4087 | ||
4088 | `endif | |
4089 | ||
4090 | // added this to exclude NIU specific code | |
4091 | `ifndef FC_NO_NIU_T2 | |
4092 | ||
4093 | ||
4094 | `ifdef NIU_SYSTEMC_T2 | |
4095 | ||
4096 | `ifdef OPENSPARC_CMP | |
4097 | `else | |
4098 | ||
4099 | niu niu ( | |
4100 | .XAUI0_REFCLK_N (XAUI0_REFCLK_N), | |
4101 | .XAUI0_REFCLK_P (XAUI0_REFCLK_P), | |
4102 | .XAUI0_RX_N (XAUI0_RX_N[3:0]), | |
4103 | .XAUI0_RX_P (XAUI0_RX_P[3:0]), | |
4104 | .XAUI1_RX_N (XAUI1_RX_N[3:0]), | |
4105 | .XAUI1_RX_P (XAUI1_RX_P[3:0]), | |
4106 | .cluster_arst_l (cluster_arst_l), | |
4107 | .cmp_gclk_c0_rdp (cmp_gclk_c0_rdp), | |
4108 | .cmp_gclk_c0_rtx (cmp_gclk_c0_rtx), | |
4109 | .cmp_gclk_c0_tds (cmp_gclk_c0_tds), | |
4110 | .cmp_gclk_c1_mac (cmp_gclk_c1_mac), | |
4111 | .dbg1_niu_dbg_sel (dbg1_niu_dbg_sel[4:0]), | |
4112 | .dbg1_niu_resume (dbg1_niu_resume), | |
4113 | .dbg1_niu_stall (dbg1_niu_stall), | |
4114 | .efu_niu_4k_clr (efu_niu_4k_clr), | |
4115 | .efu_niu_4k_data (efu_niu_4k_data), | |
4116 | .efu_niu_4k_xfer_en (efu_niu_4k_xfer_en), | |
4117 | .efu_niu_cfifo0_clr (efu_niu_cfifo0_clr), | |
4118 | .efu_niu_cfifo0_xfer_en (efu_niu_cfifo0_xfer_en), | |
4119 | .efu_niu_cfifo1_clr (efu_niu_cfifo1_clr), | |
4120 | .efu_niu_cfifo1_xfer_en (efu_niu_cfifo1_xfer_en), | |
4121 | .efu_niu_cfifo_data (efu_niu_cfifo_data), | |
4122 | .efu_niu_ipp0_clr (efu_niu_ipp0_clr), | |
4123 | .efu_niu_ipp0_xfer_en (efu_niu_ipp0_xfer_en), | |
4124 | .efu_niu_ipp1_clr (efu_niu_ipp1_clr), | |
4125 | .efu_niu_ipp1_xfer_en (efu_niu_ipp1_xfer_en), | |
4126 | .efu_niu_mac01_sfro_data (efu_niu_mac01_sfro_data), | |
4127 | .efu_niu_mac0_ro_clr (efu_niu_mac0_ro_clr), | |
4128 | .efu_niu_mac0_ro_xfer_en (efu_niu_mac0_ro_xfer_en), | |
4129 | .efu_niu_mac0_sf_clr (efu_niu_mac0_sf_clr), | |
4130 | .efu_niu_mac0_sf_xfer_en (efu_niu_mac0_sf_xfer_en), | |
4131 | .efu_niu_mac1_ro_clr (efu_niu_mac1_ro_clr), | |
4132 | .efu_niu_mac1_ro_xfer_en (efu_niu_mac1_ro_xfer_en), | |
4133 | .efu_niu_mac1_sf_clr (efu_niu_mac1_sf_clr), | |
4134 | .efu_niu_mac1_sf_xfer_en (efu_niu_mac1_sf_xfer_en), | |
4135 | .efu_niu_ram0_clr (efu_niu_ram0_clr), | |
4136 | .efu_niu_ram0_xfer_en (efu_niu_ram0_xfer_en), | |
4137 | .efu_niu_ram1_clr (efu_niu_ram1_clr), | |
4138 | .efu_niu_ram1_xfer_en (efu_niu_ram1_xfer_en), | |
4139 | .efu_niu_ram_clr (efu_niu_ram_clr), | |
4140 | .efu_niu_ram_data (efu_niu_ram_data), | |
4141 | .efu_niu_ram_xfer_en (efu_niu_ram_xfer_en), | |
4142 | .esr_atpgd (esr_atpgd), | |
4143 | .gl_mac_io_clk_stop (gl_mac_io_clk_stop), | |
4144 | .mac_125rx_test_clk (mac_125rx_test_clk), | |
4145 | .mac_125tx_test_clk (mac_125tx_test_clk), | |
4146 | .mac_156rx_test_clk (mac_156rx_test_clk), | |
4147 | .mac_156tx_test_clk (mac_156tx_test_clk), | |
4148 | .mac_312rx_test_clk (mac_312rx_test_clk), | |
4149 | .mac_312tx_test_clk (mac_312tx_test_clk), | |
4150 | .mdi (mdi), | |
4151 | .ncu_niu_ctag_cei (ncu_niu_ctag_cei), | |
4152 | .ncu_niu_ctag_uei (ncu_niu_ctag_uei), | |
4153 | .ncu_niu_d_pei (ncu_niu_d_pei), | |
4154 | .ncu_niu_data (ncu_niu_data[31:0]), | |
4155 | .ncu_niu_stall (ncu_niu_stall), | |
4156 | .ncu_niu_vld (ncu_niu_vld), | |
4157 | .peu_mac_sbs_input (peu_mac_sbs_input), | |
4158 | .rdp_rdmc_mbist_scan_in (rdp_rdmc_mbist_scan_in), | |
4159 | .rtx_mbist_scan_in (rtx_mbist_scan_in), | |
4160 | .sii_niu_bqdq (sii_niu_bqdq), | |
4161 | .sii_niu_oqdq (sii_niu_oqdq), | |
4162 | .sio_niu_data (sio_niu_data[127:0]), | |
4163 | .sio_niu_datareq (sio_niu_datareq), | |
4164 | .sio_niu_hdr_vld (sio_niu_hdr_vld), | |
4165 | .sio_niu_parity (sio_niu_parity[7:0]), | |
4166 | .tcu_div_bypass (tcu_div_bypass), | |
4167 | .tcu_mbist_bisi_en (tcu_mbist_bisi_en), | |
4168 | .tcu_mbist_user_mode (tcu_mbist_user_mode), | |
4169 | .tcu_pce_ov (tcu_pce_ov), | |
4170 | .tcu_rdp_rdmc_mbist_start (tcu_rdp_rdmc_mbist_start), | |
4171 | .tcu_rtx_dmo_ctl (tcu_rtx_dmo_ctl[2:0]), | |
4172 | .tcu_rtx_rxc_ipp0_mbist_start (tcu_rtx_rxc_ipp0_mbist_start), | |
4173 | .tcu_rtx_rxc_ipp1_mbist_start (tcu_rtx_rxc_ipp1_mbist_start), | |
4174 | .tcu_rtx_rxc_mb5_mbist_start (tcu_rtx_rxc_mb5_mbist_start), | |
4175 | .tcu_rtx_rxc_mb6_mbist_start (tcu_rtx_rxc_mb6_mbist_start), | |
4176 | .tcu_rtx_rxc_zcp0_mbist_start (tcu_rtx_rxc_zcp0_mbist_start), | |
4177 | .tcu_rtx_rxc_zcp1_mbist_start (tcu_rtx_rxc_zcp1_mbist_start), | |
4178 | .tcu_rtx_txc_txe0_mbist_start (tcu_rtx_txc_txe0_mbist_start), | |
4179 | .tcu_rtx_txc_txe1_mbist_start (tcu_rtx_txc_txe1_mbist_start), | |
4180 | .tcu_sbs_aclk (tcu_sbs_aclk), | |
4181 | .tcu_sbs_acmode (tcu_sbs_acmode), | |
4182 | .tcu_sbs_actestsignal (tcu_sbs_actestsignal), | |
4183 | .tcu_sbs_bclk (tcu_sbs_bclk), | |
4184 | .tcu_sbs_clk (tcu_sbs_clk), | |
4185 | .tcu_sbs_enbspt (tcu_sbs_enbspt), | |
4186 | .tcu_sbs_enbsrx (tcu_sbs_enbsrx), | |
4187 | .tcu_sbs_enbstx (tcu_sbs_enbstx), | |
4188 | .tcu_sbs_scan_en (tcu_sbs_scan_en), | |
4189 | .tcu_sbs_uclk (tcu_sbs_uclk), | |
4190 | .tcu_tds_smx_mbist_start (tcu_tds_smx_mbist_start), | |
4191 | .tcu_tds_tdmc_mbist_start (tcu_tds_tdmc_mbist_start), | |
4192 | .tds_mbist_scan_in (tds_mbist_scan_in), | |
4193 | .VDDT_ESR (VDDT_ESR), | |
4194 | .VDDA_ESR (VDDA_ESR), | |
4195 | .VDDD_ESR (VDDD_ESR), | |
4196 | .VDDR_ESR (VDDR_ESR), | |
4197 | .VSSA_ESR (VSSA_ESR), | |
4198 | .gl_io2x_out_c1b (gl_io2x_out_c1b), | |
4199 | .gl_io_out_c1b (gl_io_out_c1b), | |
4200 | .gl_rst_niu_wmr_c1b (gl_rst_niu_wmr_c1b), | |
4201 | .tcu_asic_aclk (tcu_asic_aclk), | |
4202 | .tcu_asic_bclk (tcu_asic_bclk), | |
4203 | .tcu_asic_scan_en (tcu_asic_scan_en), | |
4204 | .tcu_asic_se_scancollar_in (tcu_asic_se_scancollar_in), | |
4205 | .tcu_asic_se_scancollar_out (tcu_asic_se_scancollar_out), | |
4206 | .tcu_asic_array_wr_inhibit (tcu_asic_array_wr_inhibit), | |
4207 | .tcu_soce_scan_out (tcu_soce_scan_out), | |
4208 | .gl_rdp_io_clk_stop (gl_rdp_io_clk_stop), | |
4209 | .tcu_soc4_scan_out (tcu_soc4_scan_out), | |
4210 | .gl_tds_io_clk_stop (gl_tds_io_clk_stop), | |
4211 | .tcu_socf_scan_out (tcu_socf_scan_out), | |
4212 | .gl_rtx_io_clk_stop (gl_rtx_io_clk_stop), | |
4213 | .gl_rst_mac_c1b (gl_rst_mac_c1b), | |
4214 | .tcu_soc5_scan_out (tcu_soc5_scan_out), | |
4215 | .tcu_mac_testmode (tcu_mac_testmode), | |
4216 | .tcu_stcicfg (tcu_stcicfg[1:0]), | |
4217 | .tcu_stciclk (tcu_stciclk), | |
4218 | .esr_stcid (esr_stcid), | |
4219 | .mio_esr_testclkr (mio_esr_testclkr), | |
4220 | .mio_esr_testclkt (mio_esr_testclkt), | |
4221 | .efu_niu_fclk (efu_niu_fclk), | |
4222 | .efu_niu_fclrz (efu_niu_fclrz), | |
4223 | .efu_niu_fdi (efu_niu_fdi), | |
4224 | .tcu_sbs_bsinitclk (tcu_sbs_bsinitclk), | |
4225 | .tcu_srd_atpgse (tcu_srd_atpgse), | |
4226 | .tcu_srd_atpgmode (tcu_srd_atpgmode[2:0]), | |
4227 | .XAUI0_AMUX (XAUI0_AMUX), | |
4228 | .XAUI0_TX_N (XAUI0_TX_N[3:0]), | |
4229 | .XAUI0_TX_P (XAUI0_TX_P[3:0]), | |
4230 | .XAUI1_AMUX (XAUI1_AMUX), | |
4231 | .XAUI1_TX_N (XAUI1_TX_N[3:0]), | |
4232 | .XAUI1_TX_P (XAUI1_TX_P[3:0]), | |
4233 | .arb0_rcr_data_req (arb0_rcr_data_req), | |
4234 | .arb0_rcr_req_accept (arb0_rcr_req_accept), | |
4235 | .arb0_rdc_data_req (arb0_rdc_data_req), | |
4236 | .arb0_rdc_req_accept (arb0_rdc_req_accept), | |
4237 | .arb1_rbr_req_accept (arb1_rbr_req_accept), | |
4238 | .arb1_rbr_req_errors (arb1_rbr_req_errors), | |
4239 | .esr_atpgq (esr_atpgq), | |
4240 | .mac_mcu_3_sbs_output (mac_mcu_3_sbs_output), | |
4241 | .mdoe (mdoe), | |
4242 | .niu_dbg1_stall_ack (niu_dbg1_stall_ack), | |
4243 | .niu_efu_4k_data (niu_efu_4k_data), | |
4244 | .niu_efu_4k_xfer_en (niu_efu_4k_xfer_en), | |
4245 | .niu_efu_cfifo0_data (niu_efu_cfifo0_data), | |
4246 | .niu_efu_cfifo0_xfer_en (niu_efu_cfifo0_xfer_en), | |
4247 | .niu_efu_cfifo1_data (niu_efu_cfifo1_data), | |
4248 | .niu_efu_cfifo1_xfer_en (niu_efu_cfifo1_xfer_en), | |
4249 | .niu_efu_ipp0_data (niu_efu_ipp0_data), | |
4250 | .niu_efu_ipp0_xfer_en (niu_efu_ipp0_xfer_en), | |
4251 | .niu_efu_ipp1_data (niu_efu_ipp1_data), | |
4252 | .niu_efu_ipp1_xfer_en (niu_efu_ipp1_xfer_en), | |
4253 | .niu_efu_mac0_ro_data (niu_efu_mac0_ro_data), | |
4254 | .niu_efu_mac0_ro_xfer_en (niu_efu_mac0_ro_xfer_en), | |
4255 | .niu_efu_mac0_sf_data (niu_efu_mac0_sf_data), | |
4256 | .niu_efu_mac0_sf_xfer_en (niu_efu_mac0_sf_xfer_en), | |
4257 | .niu_efu_mac1_ro_data (niu_efu_mac1_ro_data), | |
4258 | .niu_efu_mac1_ro_xfer_en (niu_efu_mac1_ro_xfer_en), | |
4259 | .niu_efu_mac1_sf_data (niu_efu_mac1_sf_data), | |
4260 | .niu_efu_mac1_sf_xfer_en (niu_efu_mac1_sf_xfer_en), | |
4261 | .niu_efu_ram0_data (niu_efu_ram0_data), | |
4262 | .niu_efu_ram0_xfer_en (niu_efu_ram0_xfer_en), | |
4263 | .niu_efu_ram1_data (niu_efu_ram1_data), | |
4264 | .niu_efu_ram1_xfer_en (niu_efu_ram1_xfer_en), | |
4265 | .niu_efu_ram_data (niu_efu_ram_data), | |
4266 | .niu_efu_ram_xfer_en (niu_efu_ram_xfer_en), | |
4267 | .niu_mio_debug_clock (niu_mio_debug_clock[1:0]), | |
4268 | .niu_mio_debug_data (niu_mio_debug_data[31:0]), | |
4269 | .niu_ncu_ctag_ce (niu_ncu_ctag_ce), | |
4270 | .niu_ncu_ctag_ue (niu_ncu_ctag_ue), | |
4271 | .niu_ncu_d_pe (niu_ncu_d_pe), | |
4272 | .niu_ncu_data (niu_ncu_data[31:0]), | |
4273 | .niu_ncu_stall (niu_ncu_stall), | |
4274 | .niu_ncu_vld (niu_ncu_vld), | |
4275 | .niu_sii_data (niu_sii_data[127:0]), | |
4276 | .niu_sii_datareq (niu_sii_datareq), | |
4277 | .niu_sii_hdr_vld (niu_sii_hdr_vld), | |
4278 | .niu_sii_parity (niu_sii_parity[7:0]), | |
4279 | .niu_sii_reqbypass (niu_sii_reqbypass), | |
4280 | .niu_sio_dq (niu_sio_dq), | |
4281 | .niu_txc_interrupts (niu_txc_interrupts), | |
4282 | .rdp_rdmc_mbist_scan_out (rdp_rdmc_mbist_scan_out), | |
4283 | .rdp_rdmc_tcu_mbist_done (rdp_rdmc_tcu_mbist_done), | |
4284 | .rdp_rdmc_tcu_mbist_fail (rdp_rdmc_tcu_mbist_fail), | |
4285 | .rdp_tcu_dmo_dout (rdp_tcu_dmo_dout[39:0]), | |
4286 | .rtx_mbist_scan_out (rtx_mbist_scan_out), | |
4287 | .rtx_rxc_ipp0_tcu_mbist_done (rtx_rxc_ipp0_tcu_mbist_done), | |
4288 | .rtx_rxc_ipp0_tcu_mbist_fail (rtx_rxc_ipp0_tcu_mbist_fail), | |
4289 | .rtx_rxc_ipp1_tcu_mbist_done (rtx_rxc_ipp1_tcu_mbist_done), | |
4290 | .rtx_rxc_ipp1_tcu_mbist_fail (rtx_rxc_ipp1_tcu_mbist_fail), | |
4291 | .rtx_rxc_mb5_tcu_mbist_done (rtx_rxc_mb5_tcu_mbist_done), | |
4292 | .rtx_rxc_mb5_tcu_mbist_fail (rtx_rxc_mb5_tcu_mbist_fail), | |
4293 | .rtx_rxc_mb6_tcu_mbist_done (rtx_rxc_mb6_tcu_mbist_done), | |
4294 | .rtx_rxc_mb6_tcu_mbist_fail (rtx_rxc_mb6_tcu_mbist_fail), | |
4295 | .rtx_rxc_zcp0_tcu_mbist_done (rtx_rxc_zcp0_tcu_mbist_done), | |
4296 | .rtx_rxc_zcp0_tcu_mbist_fail (rtx_rxc_zcp0_tcu_mbist_fail), | |
4297 | .rtx_rxc_zcp1_tcu_mbist_done (rtx_rxc_zcp1_tcu_mbist_done), | |
4298 | .rtx_rxc_zcp1_tcu_mbist_fail (rtx_rxc_zcp1_tcu_mbist_fail), | |
4299 | .rtx_tcu_dmo_data_out (rtx_tcu_dmo_data_out[39:0]), | |
4300 | .rtx_txc_txe0_tcu_mbist_done (rtx_txc_txe0_tcu_mbist_done), | |
4301 | .rtx_txc_txe0_tcu_mbist_fail (rtx_txc_txe0_tcu_mbist_fail), | |
4302 | .rtx_txc_txe1_tcu_mbist_done (rtx_txc_txe1_tcu_mbist_done), | |
4303 | .rtx_txc_txe1_tcu_mbist_fail (rtx_txc_txe1_tcu_mbist_fail), | |
4304 | .tdmc_pio_intr (tdmc_pio_intr[63:0]), | |
4305 | .tds_mbist_scan_out (tds_mbist_scan_out), | |
4306 | .tds_smx_tcu_mbist_done (tds_smx_tcu_mbist_done), | |
4307 | .tds_smx_tcu_mbist_fail (tds_smx_tcu_mbist_fail), | |
4308 | .tds_tcu_dmo_dout (tds_tcu_dmo_dout[39:0]), | |
4309 | .tds_tdmc_tcu_mbist_done (tds_tdmc_tcu_mbist_done), | |
4310 | .tds_tdmc_tcu_mbist_fail (tds_tdmc_tcu_mbist_fail), | |
4311 | .xaui_act_led_0 (xaui_act_led_0), | |
4312 | .xaui_act_led_1 (xaui_act_led_1), | |
4313 | .xaui_link_led_0 (xaui_link_led_0), | |
4314 | .xaui_link_led_1 (xaui_link_led_1), | |
4315 | .rdp_scan_out (rdp_scan_out), | |
4316 | .tds_scan_out (tds_scan_out), | |
4317 | .rtx_scan_out (rtx_scan_out), | |
4318 | .mac_scan_out (mac_scan_out), | |
4319 | .mdc (mdc), | |
4320 | .esr_stciq (esr_stciq), | |
4321 | .niu_efu_fdo (niu_efu_fdo) | |
4322 | ); | |
4323 | ||
4324 | `endif | |
4325 | ||
4326 | ||
4327 | `else | |
4328 | ||
4329 | `ifdef OPENSPARC_CMP | |
4330 | `else | |
4331 | ||
4332 | // - 4 repartitioned NIU blocks + esr module - 0304 | |
4333 | ||
4334 | // leave this instance out of cmp model | |
4335 | rdp rdp ( | |
4336 | .arb_pio_all_npwdirty (arb_pio_all_npwdirty), // <= | |
4337 | .arb_pio_all_rddirty (arb_pio_all_rddirty), // <= | |
4338 | .arb_pio_dirtid_npwstatus (arb_pio_dirtid_npwstatus[ 5 : 0 ]), // <= | |
4339 | .arb_pio_dirtid_rdstatus (arb_pio_dirtid_rdstatus[ 5 : 0 ]), // <= | |
4340 | .cluster_arst_l (cluster_arst_l), // <= | |
4341 | .cmp_gclk_c0_rdp (cmp_gclk_c0_rdp), // <= | |
4342 | .efu_niu_ram0_clr (efu_niu_ram0_clr), // <= | |
4343 | .efu_niu_ram0_xfer_en (efu_niu_ram0_xfer_en), // <= | |
4344 | .efu_niu_ram1_clr (efu_niu_ram1_clr), // <= | |
4345 | .efu_niu_ram1_xfer_en (efu_niu_ram1_xfer_en), // <= | |
4346 | .efu_niu_ram_data (efu_niu_ram_data), // <= | |
4347 | .fflp_debug_port (fflp_debug_port[ 31 : 0 ]), // <= | |
4348 | .fflp_pio_ack (fflp_pio_ack), // <= | |
4349 | .fflp_pio_err (fflp_pio_err), // <= | |
4350 | .fflp_pio_intr (fflp_pio_intr), // <= | |
4351 | .fflp_pio_rdata (fflp_pio_rdata[ 63 : 0 ]), // <= | |
4352 | .gl_rdp_io2x_out (gl_io2x_out_c1b), // <= | |
4353 | .gl_rdp_io_out (gl_io_out_c1b), // <= | |
4354 | .ipp_debug_port (ipp_debug_port[ 31 : 0 ]), // <= | |
4355 | .ipp_dmc_dat_ack0 (ipp_dmc_dat_ack0), // <= | |
4356 | .ipp_dmc_dat_ack1 (ipp_dmc_dat_ack1), // <= | |
4357 | .ipp_dmc_dat_err0 (ipp_dmc_dat_err0), // <= | |
4358 | .ipp_dmc_dat_err1 (ipp_dmc_dat_err1), // <= | |
4359 | .ipp_dmc_data0 (ipp_dmc_data0[ 129 : 0 ]), // <= | |
4360 | .ipp_dmc_data1 (ipp_dmc_data1[ 129 : 0 ]), // <= | |
4361 | .ipp_dmc_ful_pkt0 (ipp_dmc_ful_pkt0), // <= | |
4362 | .ipp_dmc_ful_pkt1 (ipp_dmc_ful_pkt1), // <= | |
4363 | .ipp_pio_ack (ipp_pio_ack), // <= | |
4364 | .ipp_pio_err (ipp_pio_err), // <= | |
4365 | .ipp_pio_intr (ipp_pio_intr), // <= | |
4366 | .ipp_pio_rdata (ipp_pio_rdata[ 63 : 0 ]), // <= | |
4367 | .mac_debug_port (mac_debug_port[ 31 : 0 ]), // <= | |
4368 | .mac_pio_ack (mac_pio_ack), // <= | |
4369 | .mac_pio_err (mac_pio_err), // <= | |
4370 | .mac_pio_intr0 (mac_pio_intr0), // <= | |
4371 | .mac_pio_intr1 (mac_pio_intr1), // <= | |
4372 | .mac_pio_rdata (mac_pio_rdata[ 63 : 0 ]), // <= | |
4373 | .meta0_rdmc_rcr_ack_client ({meta_dmc_ack_client_rdmc}), // <= | |
4374 | .meta0_rdmc_rcr_ack_cmd (meta_dmc_ack_cmd), // <= | |
4375 | .meta0_rdmc_rcr_ack_cmd_status (meta_dmc_ack_cmd_status), // <= | |
4376 | .meta0_rdmc_rcr_ack_dma_num (meta_dmc_ack_dma_num[ 4 : 0 ]), // <= | |
4377 | .meta0_rdmc_rcr_ack_ready (meta_dmc_ack_ready), // <= | |
4378 | .meta0_rdmc_rcr_data_req (arb0_rcr_data_req), // <= | |
4379 | .meta0_rdmc_rcr_req_accept (arb0_rcr_req_accept), // <= | |
4380 | .meta0_rdmc_wr_data_req (arb0_rdc_data_req), // <= | |
4381 | .meta0_rdmc_wr_req_accept (arb0_rdc_req_accept), // <= | |
4382 | .meta1_rdmc_rbr_req_accept (arb1_rbr_req_accept), // <= | |
4383 | .meta1_rdmc_rbr_req_error (arb1_rbr_req_errors), // <= | |
4384 | .meta1_rdmc_rbr_resp_byteenable (meta1_rdmc_rbr_resp_byteenable[ 15 : 0 ]), // <= | |
4385 | .meta1_rdmc_rbr_resp_client ({meta_dmc_resp_client_rdmc}), // <= | |
4386 | .meta1_rdmc_rbr_resp_cmd (meta1_rdmc_rbr_resp_cmd[ 7 : 0 ]), // <= | |
4387 | .meta1_rdmc_rbr_resp_cmd_status (meta1_rdmc_rbr_resp_cmd_status[ 3 : 0 ]), // <= | |
4388 | .meta1_rdmc_rbr_resp_comp ({meta_dmc_resp_complete_rdmc}), // <= | |
4389 | .meta1_rdmc_rbr_resp_data (meta1_rdmc_rbr_resp_data[ 127 : 0 ]), // <= | |
4390 | .meta1_rdmc_rbr_resp_data_status (meta_dmc_data_status[ 3 : 0 ]), // <= | |
4391 | .meta1_rdmc_rbr_resp_data_valid ({meta_dmc_data_valid_rdmc}), // <= | |
4392 | .meta1_rdmc_rbr_resp_dma_num (meta1_rdmc_rbr_resp_dma_num[ 4 : 0 ]), // <= | |
4393 | .meta1_rdmc_rbr_resp_ready (meta1_rdmc_rbr_resp_ready), // <= | |
4394 | .meta1_rdmc_rbr_resp_trans_comp ({meta_dmc_resp_transfer_cmpl_rdmc}), // <= | |
4395 | .meta_arb_debug_port (meta_arb_debug_port[ 31 : 0 ]), // <= | |
4396 | .mif_pio_intr (mif_pio_intr), // <= | |
4397 | .ncu_niu_data (ncu_niu_data), // <= | |
4398 | .ncu_niu_stall (ncu_niu_stall), // <= | |
4399 | .ncu_niu_vld (ncu_niu_vld), // <= | |
4400 | .rdp_rdmc_mbist_scan_in (rdp_rdmc_mbist_scan_in), // <= | |
4401 | .rst_por_ (gl_rst_niu_wmr_c1b), // <= | |
4402 | .smx_debug_port (smx_debug_port[ 31 : 0 ]), // <= | |
4403 | .smx_pio_intr (smx_pio_intr), // <= | |
4404 | .smx_pio_status (smx_pio_status[ 31 : 0 ]), // <= | |
4405 | .tcu_aclk (tcu_asic_aclk), // <= | |
4406 | .tcu_bclk (tcu_asic_bclk), // <= | |
4407 | .tcu_div_bypass (tcu_div_bypass), // <= | |
4408 | .tcu_mbist_bisi_en (tcu_mbist_bisi_en), // <= | |
4409 | .tcu_mbist_user_mode (tcu_mbist_user_mode), // <= | |
4410 | .tcu_pce_ov (tcu_pce_ov), // <= | |
4411 | .tcu_rdp_rdmc_mbist_start (tcu_rdp_rdmc_mbist_start), // <= | |
4412 | .tcu_scan_en (tcu_asic_scan_en), // <= | |
4413 | .tcu_se_scancollar_in (tcu_asic_se_scancollar_in), // <= | |
4414 | .tcu_se_scancollar_out (tcu_asic_se_scancollar_out), // <= | |
4415 | .tdmc_debug_port (tdmc_debug_port[ 31 : 0 ]), // <= | |
4416 | .tdmc_pio_ack (tdmc_pio_ack), // <= | |
4417 | .tdmc_pio_err (tdmc_pio_err), // <= | |
4418 | .tdmc_pio_rdata (tdmc_pio_rdata[ 63 : 0 ]), // <= | |
4419 | .txc_debug_port (txc_debug_port[ 31 : 0 ]), // <= | |
4420 | .txc_pio_ack (txc_pio_ack), // <= | |
4421 | .txc_pio_err (txc_pio_err), // <= | |
4422 | .txc_pio_intr (niu_txc_interrupts), // <= | |
4423 | .txc_pio_rdata (txc_pio_rdata[ 63 : 0 ]), // <= | |
4424 | .zcp_debug_port (zcp_debug_port[ 31 : 0 ]), // <= | |
4425 | .zcp_dmc_ack0 (zcp_dmc_ack0), // <= | |
4426 | .zcp_dmc_ack1 (zcp_dmc_ack1), // <= | |
4427 | .zcp_dmc_dat0 (zcp_dmc_dat0[ 129 : 0 ]), // <= | |
4428 | .zcp_dmc_dat1 (zcp_dmc_dat1[ 129 : 0 ]), // <= | |
4429 | .zcp_dmc_dat_err0 (zcp_dmc_dat_err0), // <= | |
4430 | .zcp_dmc_dat_err1 (zcp_dmc_dat_err1), // <= | |
4431 | .zcp_dmc_ful_pkt0 (zcp_dmc_ful_pkt0), // <= | |
4432 | .zcp_dmc_ful_pkt1 (zcp_dmc_ful_pkt1), // <= | |
4433 | .zcp_pio_ack (zcp_pio_ack), // <= | |
4434 | .zcp_pio_err (zcp_pio_err), // <= | |
4435 | .zcp_pio_intr (zcp_pio_intr), // <= | |
4436 | .zcp_pio_rdata (zcp_pio_rdata[ 63 : 0 ]), // <= | |
4437 | .dmc_ipp_dat_req0 (dmc_ipp_dat_req0), // => | |
4438 | .dmc_ipp_dat_req1 (dmc_ipp_dat_req1), // => | |
4439 | .dmc_zcp_req0 (dmc_zcp_req0), // => | |
4440 | .dmc_zcp_req1 (dmc_zcp_req1), // => | |
4441 | .mac_reset0 (mac_reset0), // => | |
4442 | .mac_reset1 (mac_reset1), // => | |
4443 | .niu_efu_ram0_xfer_en (niu_efu_ram0_xfer_en), // => | |
4444 | .niu_efu_ram1_xfer_en (niu_efu_ram1_xfer_en), // => | |
4445 | .niu_ncu_data (niu_ncu_data), // => | |
4446 | .niu_ncu_stall (niu_ncu_stall), // => | |
4447 | .niu_ncu_vld (niu_ncu_vld), // => | |
4448 | .pio_arb_ctrl (pio_arb_ctrl[ 31 : 0 ]), // => | |
4449 | .pio_arb_debug_vector (pio_arb_debug_vector[ 31 : 0 ]), // => | |
4450 | .pio_arb_dirtid_clr (pio_arb_dirtid_clr), // => | |
4451 | .pio_arb_dirtid_enable (pio_arb_dirtid_enable), // => | |
4452 | .pio_arb_np_threshold (pio_arb_np_threshold[ 5 : 0 ]), // => | |
4453 | .pio_arb_rd_threshold (pio_arb_rd_threshold[ 5 : 0 ]), // => | |
4454 | .pio_fflp_sel (pio_fflp_sel), // => | |
4455 | .pio_ipp_sel (pio_ipp_sel), // => | |
4456 | .pio_mac_sel (pio_mac_sel), // => | |
4457 | .pio_smx_cfg_data (pio_smx_cfg_data[ 31 : 0 ]), // => | |
4458 | .pio_smx_clear_intr (pio_smx_clear_intr), // => | |
4459 | .pio_smx_ctrl (pio_smx_ctrl[ 31 : 0 ]), // => | |
4460 | .pio_smx_debug_vector (pio_smx_debug_vector[ 31 : 0 ]), // => | |
4461 | .pio_tdmc_sel (pio_tdmc_sel), // => | |
4462 | .pio_txc_sel (pio_txc_sel), // => | |
4463 | .pio_zcp_sel (pio_zcp_sel), // => | |
4464 | .rdmc_meta0_rcr_ack_accept (rdmc_meta_ack_accept), // => | |
4465 | .rdmc_meta0_rcr_data (rcr_arb0_data[ 127 : 0 ]), // => | |
4466 | .rdmc_meta0_rcr_data_valid (rcr_arb0_data_valid), // => | |
4467 | .rdmc_meta0_rcr_req (rcr_arb0_req), // => | |
4468 | .rdmc_meta0_rcr_req_address (rcr_arb0_req_address[ 63 : 0 ]), // => | |
4469 | .rdmc_meta0_rcr_req_byteenable (rcr_arb0_req_byteenable[ 15 : 0 ]), // => | |
4470 | .rdmc_meta0_rcr_req_cmd (rcr_arb0_req_cmd[ 7 : 0 ]), // => | |
4471 | .rdmc_meta0_rcr_req_dma_num (rcr_arb0_req_dma_num[ 4 : 0 ]), // => | |
4472 | .rdmc_meta0_rcr_req_func_num (rcr_arb0_req_func_num[ 1 : 0 ]), // => | |
4473 | .rdmc_meta0_rcr_req_length (rcr_arb0_req_length[ 13 : 0 ]), // => | |
4474 | .rdmc_meta0_rcr_req_port_num (rcr_arb0_req_port_num[ 1 : 0 ]), // => | |
4475 | .rdmc_meta0_rcr_status (rcr_arb0_status[ 3 : 0 ]), // => | |
4476 | .rdmc_meta0_rcr_transfer_comp (rcr_arb0_transfer_complete), // => | |
4477 | .rdmc_meta0_wr_data (rdc_arb0_data[ 127 : 0 ]), // => | |
4478 | .rdmc_meta0_wr_data_valid (rdc_arb0_data_valid), // => | |
4479 | .rdmc_meta0_wr_req (rdc_arb0_req), // => | |
4480 | .rdmc_meta0_wr_req_address (rdc_arb0_req_address[ 63 : 0 ]), // => | |
4481 | .rdmc_meta0_wr_req_byteenable (rdc_arb0_req_byteenable[ 15 : 0 ]), // => | |
4482 | .rdmc_meta0_wr_req_cmd (rdc_arb0_req_cmd[ 7 : 0 ]), // => | |
4483 | .rdmc_meta0_wr_req_dma_num (rdc_arb0_req_dma_num[ 4 : 0 ]), // => | |
4484 | .rdmc_meta0_wr_req_func_num (rdc_arb0_req_func_num[ 1 : 0 ]), // => | |
4485 | .rdmc_meta0_wr_req_length (rdc_arb0_req_length[ 13 : 0 ]), // => | |
4486 | .rdmc_meta0_wr_req_port_num (rdc_arb0_req_port_num[ 1 : 0 ]), // => | |
4487 | .rdmc_meta0_wr_status (rdc_arb0_status[ 3 : 0 ]), // => | |
4488 | .rdmc_meta0_wr_transfer_comp (rdc_arb0_transfer_complete), // => | |
4489 | .rdmc_meta1_rbr_req (rbr_arb1_req), // => | |
4490 | .rdmc_meta1_rbr_req_address (rbr_arb1_req_address[ 63 : 0 ]), // => | |
4491 | .rdmc_meta1_rbr_req_cmd (rbr_arb1_req_cmd[ 7 : 0 ]), // => | |
4492 | .rdmc_meta1_rbr_req_dma_num (rbr_arb1_req_dma_num[ 4 : 0 ]), // => | |
4493 | .rdmc_meta1_rbr_req_func_num (rbr_arb1_req_func_num[ 1 : 0 ]), // => | |
4494 | .rdmc_meta1_rbr_req_length (rbr_arb1_req_length[ 13 : 0 ]), // => | |
4495 | .rdmc_meta1_rbr_req_port_num (rbr_arb1_req_port_num), // => | |
4496 | .rdmc_meta1_rbr_resp_accept (rdmc_meta_resp_accept), // => | |
4497 | .rdp_rdmc_mbist_scan_out (rdp_rdmc_mbist_scan_out), // => | |
4498 | .rdp_rdmc_tcu_mbist_done (rdp_rdmc_tcu_mbist_done), // => | |
4499 | .rdp_rdmc_tcu_mbist_fail (rdp_rdmc_tcu_mbist_fail), // => | |
4500 | .rdp_tcu_dmo_dout (rdp_tcu_dmo_dout[ 39 : 0 ]), // => | |
4501 | .tcu_wr_inhibit (tcu_asic_array_wr_inhibit), // <= | |
4502 | .scan_in (tcu_soce_scan_out), // <= | |
4503 | .scan_out (rdp_scan_out), // => | |
4504 | .pio_clients_wdata (pio_clients_wdata[ 63 : 0 ]), // => | |
4505 | .pio_clients_addr (pio_clients_addr[ 19 : 0 ]), // => | |
4506 | .pio_clients_rd (pio_clients_rd), // => | |
4507 | .dbg1_niu_dbg_sel (dbg1_niu_dbg_sel[ 4 : 0 ]), // <= | |
4508 | .niu_mio_debug_clock (niu_mio_debug_clock), // => | |
4509 | .niu_mio_debug_data (niu_mio_debug_data), // => | |
4510 | .niu_efu_ram0_data (niu_efu_ram0_data), // => | |
4511 | .niu_efu_ram1_data (niu_efu_ram1_data), // => | |
4512 | .tcu_rdp_io_clk_stop (gl_rdp_io_clk_stop), // <= | |
4513 | .tdmc_pio_intri (tdmc_pio_intr[ 31 : 0 ]), // <= | |
4514 | .tdmc_pio_intrj (tdmc_pio_intr[ 63 : 32 ]), | |
4515 | .tcu_atpg_mode(tcu_atpg_mode) // <= | |
4516 | ); | |
4517 | `endif // OPENSPARC_CMP | |
4518 | ||
4519 | ||
4520 | ||
4521 | // leave this instance out of cmp model | |
4522 | `ifdef OPENSPARC_CMP | |
4523 | `else | |
4524 | tds tds ( | |
4525 | .cluster_arst_l (cluster_arst_l), // <= | |
4526 | .cmp_gclk_c0_tds (cmp_gclk_c0_tds), // <= | |
4527 | .dbg1_niu_resume (dbg1_niu_resume), // <= | |
4528 | .dbg1_niu_stall (dbg1_niu_stall), // <= | |
4529 | .efu_niu_ram_clr (efu_niu_ram_clr), // <= | |
4530 | .efu_niu_ram_data (efu_niu_ram_data), // <= | |
4531 | .efu_niu_ram_xfer_en (efu_niu_ram_xfer_en), // <= | |
4532 | .gl_tds_io2x_out (gl_io2x_out_c1b), // <= | |
4533 | .gl_tds_io_out (gl_io_out_c1b), // <= | |
4534 | .ncu_niu_ctag_cei (ncu_niu_ctag_cei), // <= | |
4535 | .ncu_niu_ctag_uei (ncu_niu_ctag_uei), // <= | |
4536 | .ncu_niu_d_pei (ncu_niu_d_pei), // <= | |
4537 | .pio_arb_ctrl (pio_arb_ctrl[ 31 : 0 ]), // <= | |
4538 | .pio_arb_debug_vector (pio_arb_debug_vector[ 31 : 0 ]), // <= | |
4539 | .pio_arb_dirtid_clr (pio_arb_dirtid_clr), // <= | |
4540 | .pio_arb_dirtid_enable (pio_arb_dirtid_enable), // <= | |
4541 | .pio_arb_np_threshold (pio_arb_np_threshold[ 5 : 0 ]), // <= | |
4542 | .pio_arb_rd_threshold (pio_arb_rd_threshold[ 5 : 0 ]), // <= | |
4543 | .pio_clients_addr (pio_clients_addr[ 19 : 0 ]), // <= | |
4544 | .pio_clients_rd (pio_clients_rd), // <= | |
4545 | .pio_clients_wdata (pio_clients_wdata[ 63 : 0 ]), // <= | |
4546 | .pio_smx_cfg_data (pio_smx_cfg_data[ 31 : 0 ]), // <= | |
4547 | .pio_smx_clear_intr (pio_smx_clear_intr), // <= | |
4548 | .pio_smx_ctrl (pio_smx_ctrl[ 31 : 0 ]), // <= | |
4549 | .pio_smx_debug_vector (pio_smx_debug_vector[ 31 : 0 ]), // <= | |
4550 | .pio_tdmc_sel (pio_tdmc_sel), // <= | |
4551 | .rbr_arb1_req (rbr_arb1_req), // <= | |
4552 | .rbr_arb1_req_address (rbr_arb1_req_address[ 63 : 0 ]), // <= | |
4553 | .rbr_arb1_req_cmd (rbr_arb1_req_cmd[ 7 : 0 ]), // <= | |
4554 | .rbr_arb1_req_dma_num (rbr_arb1_req_dma_num[ 4 : 0 ]), // <= | |
4555 | .rbr_arb1_req_func_num (rbr_arb1_req_func_num[ 1 : 0 ]), // <= | |
4556 | .rbr_arb1_req_length (rbr_arb1_req_length[ 13 : 0 ]), // <= | |
4557 | .rbr_arb1_req_port_num (rbr_arb1_req_port_num[ 1 : 0 ]), // <= | |
4558 | .rcr_arb0_data (rcr_arb0_data[ 127 : 0 ]), // <= | |
4559 | .rcr_arb0_data_valid (rcr_arb0_data_valid), // <= | |
4560 | .rcr_arb0_req (rcr_arb0_req), // <= | |
4561 | .rcr_arb0_req_address (rcr_arb0_req_address[ 63 : 0 ]), // <= | |
4562 | .rcr_arb0_req_byteenable (rcr_arb0_req_byteenable[ 15 : 0 ]), // <= | |
4563 | .rcr_arb0_req_cmd (rcr_arb0_req_cmd[ 7 : 0 ]), // <= | |
4564 | .rcr_arb0_req_dma_num (rcr_arb0_req_dma_num[ 4 : 0 ]), // <= | |
4565 | .rcr_arb0_req_func_num (rcr_arb0_req_func_num[ 1 : 0 ]), // <= | |
4566 | .rcr_arb0_req_length (rcr_arb0_req_length[ 13 : 0 ]), // <= | |
4567 | .rcr_arb0_req_port_num (rcr_arb0_req_port_num[ 1 : 0 ]), // <= | |
4568 | .rcr_arb0_status (rcr_arb0_status[ 3 : 0 ]), // <= | |
4569 | .rcr_arb0_transfer_complete (rcr_arb0_transfer_complete), // <= | |
4570 | .rdc_arb0_data (rdc_arb0_data[ 127 : 0 ]), // <= | |
4571 | .rdc_arb0_data_valid (rdc_arb0_data_valid), // <= | |
4572 | .rdc_arb0_req (rdc_arb0_req), // <= | |
4573 | .rdc_arb0_req_address (rdc_arb0_req_address[ 63 : 0 ]), // <= | |
4574 | .rdc_arb0_req_byteenable (rdc_arb0_req_byteenable[ 15 : 0 ]), // <= | |
4575 | .rdc_arb0_req_cmd (rdc_arb0_req_cmd[ 7 : 0 ]), // <= | |
4576 | .rdc_arb0_req_dma_num (rdc_arb0_req_dma_num[ 4 : 0 ]), // <= | |
4577 | .rdc_arb0_req_func_num (rdc_arb0_req_func_num[ 1 : 0 ]), // <= | |
4578 | .rdc_arb0_req_length (rdc_arb0_req_length[ 13 : 0 ]), // <= | |
4579 | .rdc_arb0_req_port_num (rdc_arb0_req_port_num[ 1 : 0 ]), // <= | |
4580 | .rdc_arb0_status (rdc_arb0_status[ 3 : 0 ]), // <= | |
4581 | .rdc_arb0_transfer_complete (rdc_arb0_transfer_complete), // <= | |
4582 | .rdmc_meta_ack_accept (rdmc_meta_ack_accept), // <= | |
4583 | .rdmc_meta_resp_accept (rdmc_meta_resp_accept), // <= | |
4584 | .rst_por_ (gl_rst_niu_wmr_c1b), // <= | |
4585 | .scan_in (tcu_soc4_scan_out), // <= | |
4586 | .sii_niu_bqdq (sii_niu_bqdq), // <= | |
4587 | .sii_niu_oqdq (sii_niu_oqdq), // <= | |
4588 | .sio_niu_data (sio_niu_data), // <= | |
4589 | .sio_niu_datareq (sio_niu_datareq), // <= | |
4590 | .sio_niu_hdr_vld (sio_niu_hdr_vld), // <= | |
4591 | .sio_niu_parity (sio_niu_parity), // <= | |
4592 | .tcu_aclk (tcu_asic_aclk), // <= | |
4593 | .tcu_bclk (tcu_asic_bclk), // <= | |
4594 | .tcu_div_bypass (tcu_div_bypass), // <= | |
4595 | .tcu_mbist_bisi_en (tcu_mbist_bisi_en), // <= | |
4596 | .tcu_mbist_user_mode (tcu_mbist_user_mode), // <= | |
4597 | .tcu_pce_ov (tcu_pce_ov), // <= | |
4598 | .tcu_scan_en (tcu_asic_scan_en), // <= | |
4599 | .tcu_se_scancollar_in (tcu_asic_se_scancollar_in), // <= | |
4600 | .tcu_se_scancollar_out (tcu_asic_se_scancollar_out), // <= | |
4601 | .tcu_tds_io_clk_stop (gl_tds_io_clk_stop), // <= | |
4602 | .tcu_tds_smx_mbist_start (tcu_tds_smx_mbist_start), // <= | |
4603 | .tcu_tds_tdmc_mbist_start (tcu_tds_tdmc_mbist_start), // <= | |
4604 | .tcu_wr_inhibit (tcu_asic_array_wr_inhibit), // <= | |
4605 | .tds_mbist_scan_in (tds_mbist_scan_in), // <= | |
4606 | .txc_arb1_req (txc_arb1_req), // <= | |
4607 | .txc_arb1_req_address (txc_arb1_req_address[ 63 : 0 ]), // <= | |
4608 | .txc_arb1_req_cmd (txc_arb1_req_cmd[ 7 : 0 ]), // <= | |
4609 | .txc_arb1_req_dma_num (txc_arb1_req_dma_num[ 4 : 0 ]), // <= | |
4610 | .txc_arb1_req_func_num (txc_arb1_req_func_num[ 1 : 0 ]), // <= | |
4611 | .txc_arb1_req_length (txc_arb1_req_length[ 13 : 0 ]), // <= | |
4612 | .txc_arb1_req_port_num (txc_arb1_req_port_num[ 1 : 0 ]), // <= | |
4613 | .txc_dmc_dma0_getnxtdesc (txc_dmc_dma0_getnxtdesc), // <= | |
4614 | .txc_dmc_dma0_inc_head (txc_dmc_dma0_inc_head), // <= | |
4615 | .txc_dmc_dma0_inc_pkt_cnt (txc_dmc_dma0_inc_pkt_cnt), // <= | |
4616 | .txc_dmc_dma0_mark_bit (txc_dmc_dma0_mark_bit), // <= | |
4617 | .txc_dmc_dma0_reset_done (txc_dmc_dma0_reset_done), // <= | |
4618 | .txc_dmc_dma10_getnxtdesc (txc_dmc_dma10_getnxtdesc), // <= | |
4619 | .txc_dmc_dma10_inc_head (txc_dmc_dma10_inc_head), // <= | |
4620 | .txc_dmc_dma10_inc_pkt_cnt (txc_dmc_dma10_inc_pkt_cnt), // <= | |
4621 | .txc_dmc_dma10_mark_bit (txc_dmc_dma10_mark_bit), // <= | |
4622 | .txc_dmc_dma10_reset_done (txc_dmc_dma10_reset_done), // <= | |
4623 | .txc_dmc_dma11_getnxtdesc (txc_dmc_dma11_getnxtdesc), // <= | |
4624 | .txc_dmc_dma11_inc_head (txc_dmc_dma11_inc_head), // <= | |
4625 | .txc_dmc_dma11_inc_pkt_cnt (txc_dmc_dma11_inc_pkt_cnt), // <= | |
4626 | .txc_dmc_dma11_mark_bit (txc_dmc_dma11_mark_bit), // <= | |
4627 | .txc_dmc_dma11_reset_done (txc_dmc_dma11_reset_done), // <= | |
4628 | .txc_dmc_dma12_getnxtdesc (txc_dmc_dma12_getnxtdesc), // <= | |
4629 | .txc_dmc_dma12_inc_head (txc_dmc_dma12_inc_head), // <= | |
4630 | .txc_dmc_dma12_inc_pkt_cnt (txc_dmc_dma12_inc_pkt_cnt), // <= | |
4631 | .txc_dmc_dma12_mark_bit (txc_dmc_dma12_mark_bit), // <= | |
4632 | .txc_dmc_dma12_reset_done (txc_dmc_dma12_reset_done), // <= | |
4633 | .txc_dmc_dma13_getnxtdesc (txc_dmc_dma13_getnxtdesc), // <= | |
4634 | .txc_dmc_dma13_inc_head (txc_dmc_dma13_inc_head), // <= | |
4635 | .txc_dmc_dma13_inc_pkt_cnt (txc_dmc_dma13_inc_pkt_cnt), // <= | |
4636 | .txc_dmc_dma13_mark_bit (txc_dmc_dma13_mark_bit), // <= | |
4637 | .txc_dmc_dma13_reset_done (txc_dmc_dma13_reset_done), // <= | |
4638 | .txc_dmc_dma14_getnxtdesc (txc_dmc_dma14_getnxtdesc), // <= | |
4639 | .txc_dmc_dma14_inc_head (txc_dmc_dma14_inc_head), // <= | |
4640 | .txc_dmc_dma14_inc_pkt_cnt (txc_dmc_dma14_inc_pkt_cnt), // <= | |
4641 | .txc_dmc_dma14_mark_bit (txc_dmc_dma14_mark_bit), // <= | |
4642 | .txc_dmc_dma14_reset_done (txc_dmc_dma14_reset_done), // <= | |
4643 | .txc_dmc_dma15_getnxtdesc (txc_dmc_dma15_getnxtdesc), // <= | |
4644 | .txc_dmc_dma15_inc_head (txc_dmc_dma15_inc_head), // <= | |
4645 | .txc_dmc_dma15_inc_pkt_cnt (txc_dmc_dma15_inc_pkt_cnt), // <= | |
4646 | .txc_dmc_dma15_mark_bit (txc_dmc_dma15_mark_bit), // <= | |
4647 | .txc_dmc_dma15_reset_done (txc_dmc_dma15_reset_done), // <= | |
4648 | .txc_dmc_dma1_getnxtdesc (txc_dmc_dma1_getnxtdesc), // <= | |
4649 | .txc_dmc_dma1_inc_head (txc_dmc_dma1_inc_head), // <= | |
4650 | .txc_dmc_dma1_inc_pkt_cnt (txc_dmc_dma1_inc_pkt_cnt), // <= | |
4651 | .txc_dmc_dma1_mark_bit (txc_dmc_dma1_mark_bit), // <= | |
4652 | .txc_dmc_dma1_reset_done (txc_dmc_dma1_reset_done), // <= | |
4653 | .txc_dmc_dma2_getnxtdesc (txc_dmc_dma2_getnxtdesc), // <= | |
4654 | .txc_dmc_dma2_inc_head (txc_dmc_dma2_inc_head), // <= | |
4655 | .txc_dmc_dma2_inc_pkt_cnt (txc_dmc_dma2_inc_pkt_cnt), // <= | |
4656 | .txc_dmc_dma2_mark_bit (txc_dmc_dma2_mark_bit), // <= | |
4657 | .txc_dmc_dma2_reset_done (txc_dmc_dma2_reset_done), // <= | |
4658 | .txc_dmc_dma3_getnxtdesc (txc_dmc_dma3_getnxtdesc), // <= | |
4659 | .txc_dmc_dma3_inc_head (txc_dmc_dma3_inc_head), // <= | |
4660 | .txc_dmc_dma3_inc_pkt_cnt (txc_dmc_dma3_inc_pkt_cnt), // <= | |
4661 | .txc_dmc_dma3_mark_bit (txc_dmc_dma3_mark_bit), // <= | |
4662 | .txc_dmc_dma3_reset_done (txc_dmc_dma3_reset_done), // <= | |
4663 | .txc_dmc_dma4_getnxtdesc (txc_dmc_dma4_getnxtdesc), // <= | |
4664 | .txc_dmc_dma4_inc_head (txc_dmc_dma4_inc_head), // <= | |
4665 | .txc_dmc_dma4_inc_pkt_cnt (txc_dmc_dma4_inc_pkt_cnt), // <= | |
4666 | .txc_dmc_dma4_mark_bit (txc_dmc_dma4_mark_bit), // <= | |
4667 | .txc_dmc_dma4_reset_done (txc_dmc_dma4_reset_done), // <= | |
4668 | .txc_dmc_dma5_getnxtdesc (txc_dmc_dma5_getnxtdesc), // <= | |
4669 | .txc_dmc_dma5_inc_head (txc_dmc_dma5_inc_head), // <= | |
4670 | .txc_dmc_dma5_inc_pkt_cnt (txc_dmc_dma5_inc_pkt_cnt), // <= | |
4671 | .txc_dmc_dma5_mark_bit (txc_dmc_dma5_mark_bit), // <= | |
4672 | .txc_dmc_dma5_reset_done (txc_dmc_dma5_reset_done), // <= | |
4673 | .txc_dmc_dma6_getnxtdesc (txc_dmc_dma6_getnxtdesc), // <= | |
4674 | .txc_dmc_dma6_inc_head (txc_dmc_dma6_inc_head), // <= | |
4675 | .txc_dmc_dma6_inc_pkt_cnt (txc_dmc_dma6_inc_pkt_cnt), // <= | |
4676 | .txc_dmc_dma6_mark_bit (txc_dmc_dma6_mark_bit), // <= | |
4677 | .txc_dmc_dma6_reset_done (txc_dmc_dma6_reset_done), // <= | |
4678 | .txc_dmc_dma7_getnxtdesc (txc_dmc_dma7_getnxtdesc), // <= | |
4679 | .txc_dmc_dma7_inc_head (txc_dmc_dma7_inc_head), // <= | |
4680 | .txc_dmc_dma7_inc_pkt_cnt (txc_dmc_dma7_inc_pkt_cnt), // <= | |
4681 | .txc_dmc_dma7_mark_bit (txc_dmc_dma7_mark_bit), // <= | |
4682 | .txc_dmc_dma7_reset_done (txc_dmc_dma7_reset_done), // <= | |
4683 | .txc_dmc_dma8_getnxtdesc (txc_dmc_dma8_getnxtdesc), // <= | |
4684 | .txc_dmc_dma8_inc_head (txc_dmc_dma8_inc_head), // <= | |
4685 | .txc_dmc_dma8_inc_pkt_cnt (txc_dmc_dma8_inc_pkt_cnt), // <= | |
4686 | .txc_dmc_dma8_mark_bit (txc_dmc_dma8_mark_bit), // <= | |
4687 | .txc_dmc_dma8_reset_done (txc_dmc_dma8_reset_done), // <= | |
4688 | .txc_dmc_dma9_getnxtdesc (txc_dmc_dma9_getnxtdesc), // <= | |
4689 | .txc_dmc_dma9_inc_head (txc_dmc_dma9_inc_head), // <= | |
4690 | .txc_dmc_dma9_inc_pkt_cnt (txc_dmc_dma9_inc_pkt_cnt), // <= | |
4691 | .txc_dmc_dma9_mark_bit (txc_dmc_dma9_mark_bit), // <= | |
4692 | .txc_dmc_dma9_reset_done (txc_dmc_dma9_reset_done), // <= | |
4693 | .txc_dmc_dma_nack_pkt_rd (txc_dmc_dma_nack_pkt_rd[ 15 : 0 ]), // <= | |
4694 | .txc_dmc_nack_pkt_rd (txc_dmc_nack_pkt_rd), // <= | |
4695 | .txc_dmc_nack_pkt_rd_addr (txc_dmc_nack_pkt_rd_addr[ 43 : 0 ]), // <= | |
4696 | .txc_dmc_p0_dma_pkt_size_err (txc_dmc_p0_dma_pkt_size_err[ 15 : 0 ]), // <= | |
4697 | .txc_dmc_p0_pkt_size_err (txc_dmc_p0_pkt_size_err), // <= | |
4698 | .txc_dmc_p0_pkt_size_err_addr (txc_dmc_p0_pkt_size_err_addr[ 43 : 0 ]), // <= | |
4699 | .txc_dmc_p1_dma_pkt_size_err (txc_dmc_p1_dma_pkt_size_err[ 15 : 0 ]), // <= | |
4700 | .txc_dmc_p1_pkt_size_err (txc_dmc_p1_pkt_size_err), // <= | |
4701 | .txc_dmc_p1_pkt_size_err_addr (txc_dmc_p1_pkt_size_err_addr[ 43 : 0 ]), // <= | |
4702 | .txc_meta_resp_accept (txc_meta_resp_accept), // <= | |
4703 | .arb0_rcr_data_req (arb0_rcr_data_req), // => | |
4704 | .arb0_rcr_req_accept (arb0_rcr_req_accept), // => | |
4705 | .arb0_rdc_data_req (arb0_rdc_data_req), // => | |
4706 | .arb0_rdc_req_accept (arb0_rdc_req_accept), // => | |
4707 | .arb1_rbr_req_accept (arb1_rbr_req_accept), // => | |
4708 | .arb1_rbr_req_errors (arb1_rbr_req_errors), // => | |
4709 | .arb1_txc_req_accept (arb1_txc_req_accept), // => | |
4710 | .arb_pio_all_npwdirty (arb_pio_all_npwdirty), // => | |
4711 | .arb_pio_all_rddirty (arb_pio_all_rddirty), // => | |
4712 | .arb_pio_dirtid_npwstatus (arb_pio_dirtid_npwstatus[ 5 : 0 ]), // => | |
4713 | .arb_pio_dirtid_rdstatus (arb_pio_dirtid_rdstatus[ 5 : 0 ]), // => | |
4714 | .dmc_meta1_req_trans_id (dmc_meta1_req_trans_id[ 5 : 0 ]), // => | |
4715 | .dmc_txc_dma0_active (dmc_txc_dma0_active), // => | |
4716 | .dmc_txc_dma0_cacheready (dmc_txc_dma0_cacheready), // => | |
4717 | .dmc_txc_dma0_descriptor (dmc_txc_dma0_descriptor[ 63 : 0 ]), // => | |
4718 | .dmc_txc_dma0_eoflist (dmc_txc_dma0_eoflist), // => | |
4719 | .dmc_txc_dma0_error (dmc_txc_dma0_error), // => | |
4720 | .dmc_txc_dma0_func_num (dmc_txc_dma0_func_num[ 1 : 0 ]), // => | |
4721 | .dmc_txc_dma0_gotnxtdesc (dmc_txc_dma0_gotnxtdesc), // => | |
4722 | .dmc_txc_dma0_page_handle (dmc_txc_dma0_page_handle[ 19 : 0 ]), // => | |
4723 | .dmc_txc_dma0_partial (dmc_txc_dma0_partial), // => | |
4724 | .dmc_txc_dma0_reset_scheduled (dmc_txc_dma0_reset_scheduled), // => | |
4725 | .dmc_txc_dma10_active (dmc_txc_dma10_active), // => | |
4726 | .dmc_txc_dma10_cacheready (dmc_txc_dma10_cacheready), // => | |
4727 | .dmc_txc_dma10_descriptor (dmc_txc_dma10_descriptor[ 63 : 0 ]), // => | |
4728 | .dmc_txc_dma10_eoflist (dmc_txc_dma10_eoflist), // => | |
4729 | .dmc_txc_dma10_error (dmc_txc_dma10_error), // => | |
4730 | .dmc_txc_dma10_func_num (dmc_txc_dma10_func_num[ 1 : 0 ]), // => | |
4731 | .dmc_txc_dma10_gotnxtdesc (dmc_txc_dma10_gotnxtdesc), // => | |
4732 | .dmc_txc_dma10_page_handle (dmc_txc_dma10_page_handle[ 19 : 0 ]), // => | |
4733 | .dmc_txc_dma10_partial (dmc_txc_dma10_partial), // => | |
4734 | .dmc_txc_dma10_reset_scheduled (dmc_txc_dma10_reset_scheduled), // => | |
4735 | .dmc_txc_dma11_active (dmc_txc_dma11_active), // => | |
4736 | .dmc_txc_dma11_cacheready (dmc_txc_dma11_cacheready), // => | |
4737 | .dmc_txc_dma11_descriptor (dmc_txc_dma11_descriptor[ 63 : 0 ]), // => | |
4738 | .dmc_txc_dma11_eoflist (dmc_txc_dma11_eoflist), // => | |
4739 | .dmc_txc_dma11_error (dmc_txc_dma11_error), // => | |
4740 | .dmc_txc_dma11_func_num (dmc_txc_dma11_func_num[ 1 : 0 ]), // => | |
4741 | .dmc_txc_dma11_gotnxtdesc (dmc_txc_dma11_gotnxtdesc), // => | |
4742 | .dmc_txc_dma11_page_handle (dmc_txc_dma11_page_handle[ 19 : 0 ]), // => | |
4743 | .dmc_txc_dma11_partial (dmc_txc_dma11_partial), // => | |
4744 | .dmc_txc_dma11_reset_scheduled (dmc_txc_dma11_reset_scheduled), // => | |
4745 | .dmc_txc_dma12_active (dmc_txc_dma12_active), // => | |
4746 | .dmc_txc_dma12_cacheready (dmc_txc_dma12_cacheready), // => | |
4747 | .dmc_txc_dma12_descriptor (dmc_txc_dma12_descriptor[ 63 : 0 ]), // => | |
4748 | .dmc_txc_dma12_eoflist (dmc_txc_dma12_eoflist), // => | |
4749 | .dmc_txc_dma12_error (dmc_txc_dma12_error), // => | |
4750 | .dmc_txc_dma12_func_num (dmc_txc_dma12_func_num[ 1 : 0 ]), // => | |
4751 | .dmc_txc_dma12_gotnxtdesc (dmc_txc_dma12_gotnxtdesc), // => | |
4752 | .dmc_txc_dma12_page_handle (dmc_txc_dma12_page_handle[ 19 : 0 ]), // => | |
4753 | .dmc_txc_dma12_partial (dmc_txc_dma12_partial), // => | |
4754 | .dmc_txc_dma12_reset_scheduled (dmc_txc_dma12_reset_scheduled), // => | |
4755 | .dmc_txc_dma13_active (dmc_txc_dma13_active), // => | |
4756 | .dmc_txc_dma13_cacheready (dmc_txc_dma13_cacheready), // => | |
4757 | .dmc_txc_dma13_descriptor (dmc_txc_dma13_descriptor[ 63 : 0 ]), // => | |
4758 | .dmc_txc_dma13_eoflist (dmc_txc_dma13_eoflist), // => | |
4759 | .dmc_txc_dma13_error (dmc_txc_dma13_error), // => | |
4760 | .dmc_txc_dma13_func_num (dmc_txc_dma13_func_num[ 1 : 0 ]), // => | |
4761 | .dmc_txc_dma13_gotnxtdesc (dmc_txc_dma13_gotnxtdesc), // => | |
4762 | .dmc_txc_dma13_page_handle (dmc_txc_dma13_page_handle[ 19 : 0 ]), // => | |
4763 | .dmc_txc_dma13_partial (dmc_txc_dma13_partial), // => | |
4764 | .dmc_txc_dma13_reset_scheduled (dmc_txc_dma13_reset_scheduled), // => | |
4765 | .dmc_txc_dma14_active (dmc_txc_dma14_active), // => | |
4766 | .dmc_txc_dma14_cacheready (dmc_txc_dma14_cacheready), // => | |
4767 | .dmc_txc_dma14_descriptor (dmc_txc_dma14_descriptor[ 63 : 0 ]), // => | |
4768 | .dmc_txc_dma14_eoflist (dmc_txc_dma14_eoflist), // => | |
4769 | .dmc_txc_dma14_error (dmc_txc_dma14_error), // => | |
4770 | .dmc_txc_dma14_func_num (dmc_txc_dma14_func_num[ 1 : 0 ]), // => | |
4771 | .dmc_txc_dma14_gotnxtdesc (dmc_txc_dma14_gotnxtdesc), // => | |
4772 | .dmc_txc_dma14_page_handle (dmc_txc_dma14_page_handle[ 19 : 0 ]), // => | |
4773 | .dmc_txc_dma14_partial (dmc_txc_dma14_partial), // => | |
4774 | .dmc_txc_dma14_reset_scheduled (dmc_txc_dma14_reset_scheduled), // => | |
4775 | .dmc_txc_dma15_active (dmc_txc_dma15_active), // => | |
4776 | .dmc_txc_dma15_cacheready (dmc_txc_dma15_cacheready), // => | |
4777 | .dmc_txc_dma15_descriptor (dmc_txc_dma15_descriptor[ 63 : 0 ]), // => | |
4778 | .dmc_txc_dma15_eoflist (dmc_txc_dma15_eoflist), // => | |
4779 | .dmc_txc_dma15_error (dmc_txc_dma15_error), // => | |
4780 | .dmc_txc_dma15_func_num (dmc_txc_dma15_func_num[ 1 : 0 ]), // => | |
4781 | .dmc_txc_dma15_gotnxtdesc (dmc_txc_dma15_gotnxtdesc), // => | |
4782 | .dmc_txc_dma15_page_handle (dmc_txc_dma15_page_handle[ 19 : 0 ]), // => | |
4783 | .dmc_txc_dma15_partial (dmc_txc_dma15_partial), // => | |
4784 | .dmc_txc_dma15_reset_scheduled (dmc_txc_dma15_reset_scheduled), // => | |
4785 | .dmc_txc_dma1_active (dmc_txc_dma1_active), // => | |
4786 | .dmc_txc_dma1_cacheready (dmc_txc_dma1_cacheready), // => | |
4787 | .dmc_txc_dma1_descriptor (dmc_txc_dma1_descriptor[ 63 : 0 ]), // => | |
4788 | .dmc_txc_dma1_eoflist (dmc_txc_dma1_eoflist), // => | |
4789 | .dmc_txc_dma1_error (dmc_txc_dma1_error), // => | |
4790 | .dmc_txc_dma1_func_num (dmc_txc_dma1_func_num[ 1 : 0 ]), // => | |
4791 | .dmc_txc_dma1_gotnxtdesc (dmc_txc_dma1_gotnxtdesc), // => | |
4792 | .dmc_txc_dma1_page_handle (dmc_txc_dma1_page_handle[ 19 : 0 ]), // => | |
4793 | .dmc_txc_dma1_partial (dmc_txc_dma1_partial), // => | |
4794 | .dmc_txc_dma1_reset_scheduled (dmc_txc_dma1_reset_scheduled), // => | |
4795 | .dmc_txc_dma2_active (dmc_txc_dma2_active), // => | |
4796 | .dmc_txc_dma2_cacheready (dmc_txc_dma2_cacheready), // => | |
4797 | .dmc_txc_dma2_descriptor (dmc_txc_dma2_descriptor[ 63 : 0 ]), // => | |
4798 | .dmc_txc_dma2_eoflist (dmc_txc_dma2_eoflist), // => | |
4799 | .dmc_txc_dma2_error (dmc_txc_dma2_error), // => | |
4800 | .dmc_txc_dma2_func_num (dmc_txc_dma2_func_num[ 1 : 0 ]), // => | |
4801 | .dmc_txc_dma2_gotnxtdesc (dmc_txc_dma2_gotnxtdesc), // => | |
4802 | .dmc_txc_dma2_page_handle (dmc_txc_dma2_page_handle[ 19 : 0 ]), // => | |
4803 | .dmc_txc_dma2_partial (dmc_txc_dma2_partial), // => | |
4804 | .dmc_txc_dma2_reset_scheduled (dmc_txc_dma2_reset_scheduled), // => | |
4805 | .dmc_txc_dma3_active (dmc_txc_dma3_active), // => | |
4806 | .dmc_txc_dma3_cacheready (dmc_txc_dma3_cacheready), // => | |
4807 | .dmc_txc_dma3_descriptor (dmc_txc_dma3_descriptor[ 63 : 0 ]), // => | |
4808 | .dmc_txc_dma3_eoflist (dmc_txc_dma3_eoflist), // => | |
4809 | .dmc_txc_dma3_error (dmc_txc_dma3_error), // => | |
4810 | .dmc_txc_dma3_func_num (dmc_txc_dma3_func_num[ 1 : 0 ]), // => | |
4811 | .dmc_txc_dma3_gotnxtdesc (dmc_txc_dma3_gotnxtdesc), // => | |
4812 | .dmc_txc_dma3_page_handle (dmc_txc_dma3_page_handle[ 19 : 0 ]), // => | |
4813 | .dmc_txc_dma3_partial (dmc_txc_dma3_partial), // => | |
4814 | .dmc_txc_dma3_reset_scheduled (dmc_txc_dma3_reset_scheduled), // => | |
4815 | .dmc_txc_dma4_active (dmc_txc_dma4_active), // => | |
4816 | .dmc_txc_dma4_cacheready (dmc_txc_dma4_cacheready), // => | |
4817 | .dmc_txc_dma4_descriptor (dmc_txc_dma4_descriptor[ 63 : 0 ]), // => | |
4818 | .dmc_txc_dma4_eoflist (dmc_txc_dma4_eoflist), // => | |
4819 | .dmc_txc_dma4_error (dmc_txc_dma4_error), // => | |
4820 | .dmc_txc_dma4_func_num (dmc_txc_dma4_func_num[ 1 : 0 ]), // => | |
4821 | .dmc_txc_dma4_gotnxtdesc (dmc_txc_dma4_gotnxtdesc), // => | |
4822 | .dmc_txc_dma4_page_handle (dmc_txc_dma4_page_handle[ 19 : 0 ]), // => | |
4823 | .dmc_txc_dma4_partial (dmc_txc_dma4_partial), // => | |
4824 | .dmc_txc_dma4_reset_scheduled (dmc_txc_dma4_reset_scheduled), // => | |
4825 | .dmc_txc_dma5_active (dmc_txc_dma5_active), // => | |
4826 | .dmc_txc_dma5_cacheready (dmc_txc_dma5_cacheready), // => | |
4827 | .dmc_txc_dma5_descriptor (dmc_txc_dma5_descriptor[ 63 : 0 ]), // => | |
4828 | .dmc_txc_dma5_eoflist (dmc_txc_dma5_eoflist), // => | |
4829 | .dmc_txc_dma5_error (dmc_txc_dma5_error), // => | |
4830 | .dmc_txc_dma5_func_num (dmc_txc_dma5_func_num[ 1 : 0 ]), // => | |
4831 | .dmc_txc_dma5_gotnxtdesc (dmc_txc_dma5_gotnxtdesc), // => | |
4832 | .dmc_txc_dma5_page_handle (dmc_txc_dma5_page_handle[ 19 : 0 ]), // => | |
4833 | .dmc_txc_dma5_partial (dmc_txc_dma5_partial), // => | |
4834 | .dmc_txc_dma5_reset_scheduled (dmc_txc_dma5_reset_scheduled), // => | |
4835 | .dmc_txc_dma6_active (dmc_txc_dma6_active), // => | |
4836 | .dmc_txc_dma6_cacheready (dmc_txc_dma6_cacheready), // => | |
4837 | .dmc_txc_dma6_descriptor (dmc_txc_dma6_descriptor[ 63 : 0 ]), // => | |
4838 | .dmc_txc_dma6_eoflist (dmc_txc_dma6_eoflist), // => | |
4839 | .dmc_txc_dma6_error (dmc_txc_dma6_error), // => | |
4840 | .dmc_txc_dma6_func_num (dmc_txc_dma6_func_num[ 1 : 0 ]), // => | |
4841 | .dmc_txc_dma6_gotnxtdesc (dmc_txc_dma6_gotnxtdesc), // => | |
4842 | .dmc_txc_dma6_page_handle (dmc_txc_dma6_page_handle[ 19 : 0 ]), // => | |
4843 | .dmc_txc_dma6_partial (dmc_txc_dma6_partial), // => | |
4844 | .dmc_txc_dma6_reset_scheduled (dmc_txc_dma6_reset_scheduled), // => | |
4845 | .dmc_txc_dma7_active (dmc_txc_dma7_active), // => | |
4846 | .dmc_txc_dma7_cacheready (dmc_txc_dma7_cacheready), // => | |
4847 | .dmc_txc_dma7_descriptor (dmc_txc_dma7_descriptor[ 63 : 0 ]), // => | |
4848 | .dmc_txc_dma7_eoflist (dmc_txc_dma7_eoflist), // => | |
4849 | .dmc_txc_dma7_error (dmc_txc_dma7_error), // => | |
4850 | .dmc_txc_dma7_func_num (dmc_txc_dma7_func_num[ 1 : 0 ]), // => | |
4851 | .dmc_txc_dma7_gotnxtdesc (dmc_txc_dma7_gotnxtdesc), // => | |
4852 | .dmc_txc_dma7_page_handle (dmc_txc_dma7_page_handle[ 19 : 0 ]), // => | |
4853 | .dmc_txc_dma7_partial (dmc_txc_dma7_partial), // => | |
4854 | .dmc_txc_dma7_reset_scheduled (dmc_txc_dma7_reset_scheduled), // => | |
4855 | .dmc_txc_dma8_active (dmc_txc_dma8_active), // => | |
4856 | .dmc_txc_dma8_cacheready (dmc_txc_dma8_cacheready), // => | |
4857 | .dmc_txc_dma8_descriptor (dmc_txc_dma8_descriptor[ 63 : 0 ]), // => | |
4858 | .dmc_txc_dma8_eoflist (dmc_txc_dma8_eoflist), // => | |
4859 | .dmc_txc_dma8_error (dmc_txc_dma8_error), // => | |
4860 | .dmc_txc_dma8_func_num (dmc_txc_dma8_func_num[ 1 : 0 ]), // => | |
4861 | .dmc_txc_dma8_gotnxtdesc (dmc_txc_dma8_gotnxtdesc), // => | |
4862 | .dmc_txc_dma8_page_handle (dmc_txc_dma8_page_handle[ 19 : 0 ]), // => | |
4863 | .dmc_txc_dma8_partial (dmc_txc_dma8_partial), // => | |
4864 | .dmc_txc_dma8_reset_scheduled (dmc_txc_dma8_reset_scheduled), // => | |
4865 | .dmc_txc_dma9_active (dmc_txc_dma9_active), // => | |
4866 | .dmc_txc_dma9_cacheready (dmc_txc_dma9_cacheready), // => | |
4867 | .dmc_txc_dma9_descriptor (dmc_txc_dma9_descriptor[ 63 : 0 ]), // => | |
4868 | .dmc_txc_dma9_eoflist (dmc_txc_dma9_eoflist), // => | |
4869 | .dmc_txc_dma9_error (dmc_txc_dma9_error), // => | |
4870 | .dmc_txc_dma9_func_num (dmc_txc_dma9_func_num[ 1 : 0 ]), // => | |
4871 | .dmc_txc_dma9_gotnxtdesc (dmc_txc_dma9_gotnxtdesc), // => | |
4872 | .dmc_txc_dma9_page_handle (dmc_txc_dma9_page_handle[ 19 : 0 ]), // => | |
4873 | .dmc_txc_dma9_partial (dmc_txc_dma9_partial), // => | |
4874 | .dmc_txc_dma9_reset_scheduled (dmc_txc_dma9_reset_scheduled), // => | |
4875 | .dmc_txc_tx_addr_md (dmc_txc_tx_addr_md), // => | |
4876 | .meta1_rdmc_rbr_resp_byteenable (meta1_rdmc_rbr_resp_byteenable[ 15 : 0 ]), // => | |
4877 | .meta1_rdmc_rbr_resp_cmd (meta1_rdmc_rbr_resp_cmd[ 7 : 0 ]), // => | |
4878 | .meta1_rdmc_rbr_resp_cmd_status (meta1_rdmc_rbr_resp_cmd_status[ 3 : 0 ]), // => | |
4879 | .meta1_rdmc_rbr_resp_data (meta1_rdmc_rbr_resp_data[ 127 : 0 ]), // => | |
4880 | .meta1_rdmc_rbr_resp_dma_num (meta1_rdmc_rbr_resp_dma_num[ 4 : 0 ]), // => | |
4881 | .meta1_rdmc_rbr_resp_ready (meta1_rdmc_rbr_resp_ready), // => | |
4882 | .meta_arb_debug_port (meta_arb_debug_port[ 31 : 0 ]), // => | |
4883 | .meta_dmc_ack_client_rdmc (meta_dmc_ack_client_rdmc), // => | |
4884 | .meta_dmc_ack_cmd (meta_dmc_ack_cmd[ 7 : 0 ]), // => | |
4885 | .meta_dmc_ack_cmd_status (meta_dmc_ack_cmd_status[ 3 : 0 ]), // => | |
4886 | .meta_dmc_ack_dma_num (meta_dmc_ack_dma_num[ 4 : 0 ]), // => | |
4887 | .meta_dmc_ack_ready (meta_dmc_ack_ready), // => | |
4888 | .meta_dmc_data (meta_dmc_data[ 127 : 0 ]), // => | |
4889 | .meta_dmc_data_status (meta_dmc_data_status[ 3 : 0 ]), // => | |
4890 | .meta_dmc_data_valid_rdmc (meta_dmc_data_valid_rdmc), // => | |
4891 | .meta_dmc_data_valid_txc (meta_dmc_data_valid_txc), // => | |
4892 | .meta_dmc_resp_address (meta_dmc_resp_address[ 63 : 0 ]), // => | |
4893 | .meta_dmc_resp_byteenable (meta_dmc_resp_byteenable[ 15 : 0 ]), // => | |
4894 | .meta_dmc_resp_client_rdmc (meta_dmc_resp_client_rdmc), // => | |
4895 | .meta_dmc_resp_client_txc (meta_dmc_resp_client_txc), // => | |
4896 | .meta_dmc_resp_cmd (meta_dmc_resp_cmd[ 7 : 0 ]), // => | |
4897 | .meta_dmc_resp_cmd_status (meta_dmc_resp_cmd_status[ 3 : 0 ]), // => | |
4898 | .meta_dmc_resp_complete_rdmc (meta_dmc_resp_complete_rdmc), // => | |
4899 | .meta_dmc_resp_complete_txc (meta_dmc_resp_complete_txc), // => | |
4900 | .meta_dmc_resp_dma_num (meta_dmc_resp_dma_num[ 4 : 0 ]), // => | |
4901 | .meta_dmc_resp_length (meta_dmc_resp_length[ 13 : 0 ]), // => | |
4902 | .meta_dmc_resp_port_num (meta_dmc_resp_port_num[ 1 : 0 ]), // => | |
4903 | .meta_dmc_resp_ready (meta_dmc_resp_ready), // => | |
4904 | .meta_dmc_resp_trans_id (meta_dmc_resp_trans_id[ 5 : 0 ]), // => | |
4905 | .meta_dmc_resp_transfer_cmpl_rdmc (meta_dmc_resp_transfer_cmpl_rdmc), // => | |
4906 | .meta_dmc_resp_transfer_cmpl_txc (meta_dmc_resp_transfer_cmpl_txc), // => | |
4907 | .niu_dbg1_stall_ack (niu_dbg1_stall_ack), // => | |
4908 | .niu_efu_ram_data (niu_efu_ram_data), // => | |
4909 | .niu_efu_ram_xfer_en (niu_efu_ram_xfer_en), // => | |
4910 | .niu_ncu_ctag_ce (niu_ncu_ctag_ce), // => | |
4911 | .niu_ncu_ctag_ue (niu_ncu_ctag_ue), // => | |
4912 | .niu_ncu_d_pe (niu_ncu_d_pe), // => | |
4913 | .niu_sii_data (niu_sii_data), // => | |
4914 | .niu_sii_datareq (niu_sii_datareq), // => | |
4915 | .niu_sii_hdr_vld (niu_sii_hdr_vld), // => | |
4916 | .niu_sii_parity (niu_sii_parity), // => | |
4917 | .niu_sii_reqbypass (niu_sii_reqbypass), // => | |
4918 | .niu_sio_dq (niu_sio_dq), // => | |
4919 | .scan_out (tds_scan_out), // => | |
4920 | .smx_debug_port (smx_debug_port[ 31 : 0 ]), // => | |
4921 | .smx_pio_intr (smx_pio_intr), // => | |
4922 | .smx_pio_status (smx_pio_status[ 31 : 0 ]), // => | |
4923 | .tdmc_debug_port (tdmc_debug_port[ 31 : 0 ]), // => | |
4924 | .tdmc_pio_ack (tdmc_pio_ack), // => | |
4925 | .tdmc_pio_err (tdmc_pio_err), // => | |
4926 | .tdmc_pio_intr (tdmc_pio_intr[ 63 : 0 ]), // => | |
4927 | .tdmc_pio_rdata (tdmc_pio_rdata[ 63 : 0 ]), // => | |
4928 | .tds_mbist_scan_out (tds_mbist_scan_out), // => | |
4929 | .tds_smx_tcu_mbist_done (tds_smx_tcu_mbist_done), // => | |
4930 | .tds_smx_tcu_mbist_fail (tds_smx_tcu_mbist_fail), // => | |
4931 | .tds_tcu_dmo_dout (tds_tcu_dmo_dout[ 39 : 0 ]), // => | |
4932 | .tds_tdmc_tcu_mbist_done (tds_tdmc_tcu_mbist_done), // => | |
4933 | .tds_tdmc_tcu_mbist_fail (tds_tdmc_tcu_mbist_fail), | |
4934 | .tcu_atpg_mode(tcu_atpg_mode) // => | |
4935 | ); | |
4936 | `endif // OPENSPARC_CMP | |
4937 | ||
4938 | ||
4939 | ||
4940 | ||
4941 | // leave this instance out of cmp model | |
4942 | `ifdef OPENSPARC_CMP | |
4943 | `else | |
4944 | rtx rtx ( | |
4945 | .arb1_txc_req_accept (arb1_txc_req_accept), // <= | |
4946 | .arb1_txc_req_transid (dmc_meta1_req_trans_id[ 5 : 0 ]), // <= | |
4947 | .cluster_arst_l (cluster_arst_l), // <= | |
4948 | .cmp_gclk_c0_rtx (cmp_gclk_c0_rtx), // <= | |
4949 | .dmc_ipp_dat_req0 (dmc_ipp_dat_req0), // <= | |
4950 | .dmc_ipp_dat_req1 (dmc_ipp_dat_req1), // <= | |
4951 | .dmc_txc_dma0_active (dmc_txc_dma0_active), // <= | |
4952 | .dmc_txc_dma0_cacheready (dmc_txc_dma0_cacheready), // <= | |
4953 | .dmc_txc_dma0_descriptor (dmc_txc_dma0_descriptor[ 63 : 0 ]), // <= | |
4954 | .dmc_txc_dma0_eoflist (dmc_txc_dma0_eoflist), // <= | |
4955 | .dmc_txc_dma0_error (dmc_txc_dma0_error), // <= | |
4956 | .dmc_txc_dma0_func_num (dmc_txc_dma0_func_num[ 1 : 0 ]), // <= | |
4957 | .dmc_txc_dma0_gotnxtdesc (dmc_txc_dma0_gotnxtdesc), // <= | |
4958 | .dmc_txc_dma0_page_handle (dmc_txc_dma0_page_handle[ 19 : 0 ]), // <= | |
4959 | .dmc_txc_dma0_partial (dmc_txc_dma0_partial), // <= | |
4960 | .dmc_txc_dma0_reset_scheduled (dmc_txc_dma0_reset_scheduled), // <= | |
4961 | .dmc_txc_dma10_active (dmc_txc_dma10_active), // <= | |
4962 | .dmc_txc_dma10_cacheready (dmc_txc_dma10_cacheready), // <= | |
4963 | .dmc_txc_dma10_descriptor (dmc_txc_dma10_descriptor[ 63 : 0 ]), // <= | |
4964 | .dmc_txc_dma10_eoflist (dmc_txc_dma10_eoflist), // <= | |
4965 | .dmc_txc_dma10_error (dmc_txc_dma10_error), // <= | |
4966 | .dmc_txc_dma10_func_num (dmc_txc_dma10_func_num[ 1 : 0 ]), // <= | |
4967 | .dmc_txc_dma10_gotnxtdesc (dmc_txc_dma10_gotnxtdesc), // <= | |
4968 | .dmc_txc_dma10_page_handle (dmc_txc_dma10_page_handle[ 19 : 0 ]), // <= | |
4969 | .dmc_txc_dma10_partial (dmc_txc_dma10_partial), // <= | |
4970 | .dmc_txc_dma10_reset_scheduled (dmc_txc_dma10_reset_scheduled), // <= | |
4971 | .dmc_txc_dma11_active (dmc_txc_dma11_active), // <= | |
4972 | .dmc_txc_dma11_cacheready (dmc_txc_dma11_cacheready), // <= | |
4973 | .dmc_txc_dma11_descriptor (dmc_txc_dma11_descriptor[ 63 : 0 ]), // <= | |
4974 | .dmc_txc_dma11_eoflist (dmc_txc_dma11_eoflist), // <= | |
4975 | .dmc_txc_dma11_error (dmc_txc_dma11_error), // <= | |
4976 | .dmc_txc_dma11_func_num (dmc_txc_dma11_func_num[ 1 : 0 ]), // <= | |
4977 | .dmc_txc_dma11_gotnxtdesc (dmc_txc_dma11_gotnxtdesc), // <= | |
4978 | .dmc_txc_dma11_page_handle (dmc_txc_dma11_page_handle[ 19 : 0 ]), // <= | |
4979 | .dmc_txc_dma11_partial (dmc_txc_dma11_partial), // <= | |
4980 | .dmc_txc_dma11_reset_scheduled (dmc_txc_dma11_reset_scheduled), // <= | |
4981 | .dmc_txc_dma12_active (dmc_txc_dma12_active), // <= | |
4982 | .dmc_txc_dma12_cacheready (dmc_txc_dma12_cacheready), // <= | |
4983 | .dmc_txc_dma12_descriptor (dmc_txc_dma12_descriptor[ 63 : 0 ]), // <= | |
4984 | .dmc_txc_dma12_eoflist (dmc_txc_dma12_eoflist), // <= | |
4985 | .dmc_txc_dma12_error (dmc_txc_dma12_error), // <= | |
4986 | .dmc_txc_dma12_func_num (dmc_txc_dma12_func_num[ 1 : 0 ]), // <= | |
4987 | .dmc_txc_dma12_gotnxtdesc (dmc_txc_dma12_gotnxtdesc), // <= | |
4988 | .dmc_txc_dma12_page_handle (dmc_txc_dma12_page_handle[ 19 : 0 ]), // <= | |
4989 | .dmc_txc_dma12_partial (dmc_txc_dma12_partial), // <= | |
4990 | .dmc_txc_dma12_reset_scheduled (dmc_txc_dma12_reset_scheduled), // <= | |
4991 | .dmc_txc_dma13_active (dmc_txc_dma13_active), // <= | |
4992 | .dmc_txc_dma13_cacheready (dmc_txc_dma13_cacheready), // <= | |
4993 | .dmc_txc_dma13_descriptor (dmc_txc_dma13_descriptor[ 63 : 0 ]), // <= | |
4994 | .dmc_txc_dma13_eoflist (dmc_txc_dma13_eoflist), // <= | |
4995 | .dmc_txc_dma13_error (dmc_txc_dma13_error), // <= | |
4996 | .dmc_txc_dma13_func_num (dmc_txc_dma13_func_num[ 1 : 0 ]), // <= | |
4997 | .dmc_txc_dma13_gotnxtdesc (dmc_txc_dma13_gotnxtdesc), // <= | |
4998 | .dmc_txc_dma13_page_handle (dmc_txc_dma13_page_handle[ 19 : 0 ]), // <= | |
4999 | .dmc_txc_dma13_partial (dmc_txc_dma13_partial), // <= | |
5000 | .dmc_txc_dma13_reset_scheduled (dmc_txc_dma13_reset_scheduled), // <= | |
5001 | .dmc_txc_dma14_active (dmc_txc_dma14_active), // <= | |
5002 | .dmc_txc_dma14_cacheready (dmc_txc_dma14_cacheready), // <= | |
5003 | .dmc_txc_dma14_descriptor (dmc_txc_dma14_descriptor[ 63 : 0 ]), // <= | |
5004 | .dmc_txc_dma14_eoflist (dmc_txc_dma14_eoflist), // <= | |
5005 | .dmc_txc_dma14_error (dmc_txc_dma14_error), // <= | |
5006 | .dmc_txc_dma14_func_num (dmc_txc_dma14_func_num[ 1 : 0 ]), // <= | |
5007 | .dmc_txc_dma14_gotnxtdesc (dmc_txc_dma14_gotnxtdesc), // <= | |
5008 | .dmc_txc_dma14_page_handle (dmc_txc_dma14_page_handle[ 19 : 0 ]), // <= | |
5009 | .dmc_txc_dma14_partial (dmc_txc_dma14_partial), // <= | |
5010 | .dmc_txc_dma14_reset_scheduled (dmc_txc_dma14_reset_scheduled), // <= | |
5011 | .dmc_txc_dma15_active (dmc_txc_dma15_active), // <= | |
5012 | .dmc_txc_dma15_cacheready (dmc_txc_dma15_cacheready), // <= | |
5013 | .dmc_txc_dma15_descriptor (dmc_txc_dma15_descriptor[ 63 : 0 ]), // <= | |
5014 | .dmc_txc_dma15_eoflist (dmc_txc_dma15_eoflist), // <= | |
5015 | .dmc_txc_dma15_error (dmc_txc_dma15_error), // <= | |
5016 | .dmc_txc_dma15_func_num (dmc_txc_dma15_func_num[ 1 : 0 ]), // <= | |
5017 | .dmc_txc_dma15_gotnxtdesc (dmc_txc_dma15_gotnxtdesc), // <= | |
5018 | .dmc_txc_dma15_page_handle (dmc_txc_dma15_page_handle[ 19 : 0 ]), // <= | |
5019 | .dmc_txc_dma15_partial (dmc_txc_dma15_partial), // <= | |
5020 | .dmc_txc_dma15_reset_scheduled (dmc_txc_dma15_reset_scheduled), // <= | |
5021 | .dmc_txc_dma1_active (dmc_txc_dma1_active), // <= | |
5022 | .dmc_txc_dma1_cacheready (dmc_txc_dma1_cacheready), // <= | |
5023 | .dmc_txc_dma1_descriptor (dmc_txc_dma1_descriptor[ 63 : 0 ]), // <= | |
5024 | .dmc_txc_dma1_eoflist (dmc_txc_dma1_eoflist), // <= | |
5025 | .dmc_txc_dma1_error (dmc_txc_dma1_error), // <= | |
5026 | .dmc_txc_dma1_func_num (dmc_txc_dma1_func_num[ 1 : 0 ]), // <= | |
5027 | .dmc_txc_dma1_gotnxtdesc (dmc_txc_dma1_gotnxtdesc), // <= | |
5028 | .dmc_txc_dma1_page_handle (dmc_txc_dma1_page_handle[ 19 : 0 ]), // <= | |
5029 | .dmc_txc_dma1_partial (dmc_txc_dma1_partial), // <= | |
5030 | .dmc_txc_dma1_reset_scheduled (dmc_txc_dma1_reset_scheduled), // <= | |
5031 | .dmc_txc_dma2_active (dmc_txc_dma2_active), // <= | |
5032 | .dmc_txc_dma2_cacheready (dmc_txc_dma2_cacheready), // <= | |
5033 | .dmc_txc_dma2_descriptor (dmc_txc_dma2_descriptor[ 63 : 0 ]), // <= | |
5034 | .dmc_txc_dma2_eoflist (dmc_txc_dma2_eoflist), // <= | |
5035 | .dmc_txc_dma2_error (dmc_txc_dma2_error), // <= | |
5036 | .dmc_txc_dma2_func_num (dmc_txc_dma2_func_num[ 1 : 0 ]), // <= | |
5037 | .dmc_txc_dma2_gotnxtdesc (dmc_txc_dma2_gotnxtdesc), // <= | |
5038 | .dmc_txc_dma2_page_handle (dmc_txc_dma2_page_handle[ 19 : 0 ]), // <= | |
5039 | .dmc_txc_dma2_partial (dmc_txc_dma2_partial), // <= | |
5040 | .dmc_txc_dma2_reset_scheduled (dmc_txc_dma2_reset_scheduled), // <= | |
5041 | .dmc_txc_dma3_active (dmc_txc_dma3_active), // <= | |
5042 | .dmc_txc_dma3_cacheready (dmc_txc_dma3_cacheready), // <= | |
5043 | .dmc_txc_dma3_descriptor (dmc_txc_dma3_descriptor[ 63 : 0 ]), // <= | |
5044 | .dmc_txc_dma3_eoflist (dmc_txc_dma3_eoflist), // <= | |
5045 | .dmc_txc_dma3_error (dmc_txc_dma3_error), // <= | |
5046 | .dmc_txc_dma3_func_num (dmc_txc_dma3_func_num[ 1 : 0 ]), // <= | |
5047 | .dmc_txc_dma3_gotnxtdesc (dmc_txc_dma3_gotnxtdesc), // <= | |
5048 | .dmc_txc_dma3_page_handle (dmc_txc_dma3_page_handle[ 19 : 0 ]), // <= | |
5049 | .dmc_txc_dma3_partial (dmc_txc_dma3_partial), // <= | |
5050 | .dmc_txc_dma3_reset_scheduled (dmc_txc_dma3_reset_scheduled), // <= | |
5051 | .dmc_txc_dma4_active (dmc_txc_dma4_active), // <= | |
5052 | .dmc_txc_dma4_cacheready (dmc_txc_dma4_cacheready), // <= | |
5053 | .dmc_txc_dma4_descriptor (dmc_txc_dma4_descriptor[ 63 : 0 ]), // <= | |
5054 | .dmc_txc_dma4_eoflist (dmc_txc_dma4_eoflist), // <= | |
5055 | .dmc_txc_dma4_error (dmc_txc_dma4_error), // <= | |
5056 | .dmc_txc_dma4_func_num (dmc_txc_dma4_func_num[ 1 : 0 ]), // <= | |
5057 | .dmc_txc_dma4_gotnxtdesc (dmc_txc_dma4_gotnxtdesc), // <= | |
5058 | .dmc_txc_dma4_page_handle (dmc_txc_dma4_page_handle[ 19 : 0 ]), // <= | |
5059 | .dmc_txc_dma4_partial (dmc_txc_dma4_partial), // <= | |
5060 | .dmc_txc_dma4_reset_scheduled (dmc_txc_dma4_reset_scheduled), // <= | |
5061 | .dmc_txc_dma5_active (dmc_txc_dma5_active), // <= | |
5062 | .dmc_txc_dma5_cacheready (dmc_txc_dma5_cacheready), // <= | |
5063 | .dmc_txc_dma5_descriptor (dmc_txc_dma5_descriptor[ 63 : 0 ]), // <= | |
5064 | .dmc_txc_dma5_eoflist (dmc_txc_dma5_eoflist), // <= | |
5065 | .dmc_txc_dma5_error (dmc_txc_dma5_error), // <= | |
5066 | .dmc_txc_dma5_func_num (dmc_txc_dma5_func_num[ 1 : 0 ]), // <= | |
5067 | .dmc_txc_dma5_gotnxtdesc (dmc_txc_dma5_gotnxtdesc), // <= | |
5068 | .dmc_txc_dma5_page_handle (dmc_txc_dma5_page_handle[ 19 : 0 ]), // <= | |
5069 | .dmc_txc_dma5_partial (dmc_txc_dma5_partial), // <= | |
5070 | .dmc_txc_dma5_reset_scheduled (dmc_txc_dma5_reset_scheduled), // <= | |
5071 | .dmc_txc_dma6_active (dmc_txc_dma6_active), // <= | |
5072 | .dmc_txc_dma6_cacheready (dmc_txc_dma6_cacheready), // <= | |
5073 | .dmc_txc_dma6_descriptor (dmc_txc_dma6_descriptor[ 63 : 0 ]), // <= | |
5074 | .dmc_txc_dma6_eoflist (dmc_txc_dma6_eoflist), // <= | |
5075 | .dmc_txc_dma6_error (dmc_txc_dma6_error), // <= | |
5076 | .dmc_txc_dma6_func_num (dmc_txc_dma6_func_num[ 1 : 0 ]), // <= | |
5077 | .dmc_txc_dma6_gotnxtdesc (dmc_txc_dma6_gotnxtdesc), // <= | |
5078 | .dmc_txc_dma6_page_handle (dmc_txc_dma6_page_handle[ 19 : 0 ]), // <= | |
5079 | .dmc_txc_dma6_partial (dmc_txc_dma6_partial), // <= | |
5080 | .dmc_txc_dma6_reset_scheduled (dmc_txc_dma6_reset_scheduled), // <= | |
5081 | .dmc_txc_dma7_active (dmc_txc_dma7_active), // <= | |
5082 | .dmc_txc_dma7_cacheready (dmc_txc_dma7_cacheready), // <= | |
5083 | .dmc_txc_dma7_descriptor (dmc_txc_dma7_descriptor[ 63 : 0 ]), // <= | |
5084 | .dmc_txc_dma7_eoflist (dmc_txc_dma7_eoflist), // <= | |
5085 | .dmc_txc_dma7_error (dmc_txc_dma7_error), // <= | |
5086 | .dmc_txc_dma7_func_num (dmc_txc_dma7_func_num[ 1 : 0 ]), // <= | |
5087 | .dmc_txc_dma7_gotnxtdesc (dmc_txc_dma7_gotnxtdesc), // <= | |
5088 | .dmc_txc_dma7_page_handle (dmc_txc_dma7_page_handle[ 19 : 0 ]), // <= | |
5089 | .dmc_txc_dma7_partial (dmc_txc_dma7_partial), // <= | |
5090 | .dmc_txc_dma7_reset_scheduled (dmc_txc_dma7_reset_scheduled), // <= | |
5091 | .dmc_txc_dma8_active (dmc_txc_dma8_active), // <= | |
5092 | .dmc_txc_dma8_cacheready (dmc_txc_dma8_cacheready), // <= | |
5093 | .dmc_txc_dma8_descriptor (dmc_txc_dma8_descriptor[ 63 : 0 ]), // <= | |
5094 | .dmc_txc_dma8_eoflist (dmc_txc_dma8_eoflist), // <= | |
5095 | .dmc_txc_dma8_error (dmc_txc_dma8_error), // <= | |
5096 | .dmc_txc_dma8_func_num (dmc_txc_dma8_func_num[ 1 : 0 ]), // <= | |
5097 | .dmc_txc_dma8_gotnxtdesc (dmc_txc_dma8_gotnxtdesc), // <= | |
5098 | .dmc_txc_dma8_page_handle (dmc_txc_dma8_page_handle[ 19 : 0 ]), // <= | |
5099 | .dmc_txc_dma8_partial (dmc_txc_dma8_partial), // <= | |
5100 | .dmc_txc_dma8_reset_scheduled (dmc_txc_dma8_reset_scheduled), // <= | |
5101 | .dmc_txc_dma9_active (dmc_txc_dma9_active), // <= | |
5102 | .dmc_txc_dma9_cacheready (dmc_txc_dma9_cacheready), // <= | |
5103 | .dmc_txc_dma9_descriptor (dmc_txc_dma9_descriptor[ 63 : 0 ]), // <= | |
5104 | .dmc_txc_dma9_eoflist (dmc_txc_dma9_eoflist), // <= | |
5105 | .dmc_txc_dma9_error (dmc_txc_dma9_error), // <= | |
5106 | .dmc_txc_dma9_func_num (dmc_txc_dma9_func_num[ 1 : 0 ]), // <= | |
5107 | .dmc_txc_dma9_gotnxtdesc (dmc_txc_dma9_gotnxtdesc), // <= | |
5108 | .dmc_txc_dma9_page_handle (dmc_txc_dma9_page_handle[ 19 : 0 ]), // <= | |
5109 | .dmc_txc_dma9_partial (dmc_txc_dma9_partial), // <= | |
5110 | .dmc_txc_dma9_reset_scheduled (dmc_txc_dma9_reset_scheduled), // <= | |
5111 | .dmc_txc_tx_addr_md (dmc_txc_tx_addr_md), // <= | |
5112 | .dmc_zcp_req0 (dmc_zcp_req0), // <= | |
5113 | .dmc_zcp_req1 (dmc_zcp_req1), // <= | |
5114 | .efu_niu_4k_clr (efu_niu_4k_clr), // <= | |
5115 | .efu_niu_4k_data (efu_niu_4k_data), // <= | |
5116 | .efu_niu_4k_xfer_en (efu_niu_4k_xfer_en), // <= | |
5117 | .efu_niu_cfifo0_clr (efu_niu_cfifo0_clr), // <= | |
5118 | .efu_niu_cfifo0_xfer_en (efu_niu_cfifo0_xfer_en), // <= | |
5119 | .efu_niu_cfifo1_clr (efu_niu_cfifo1_clr), // <= | |
5120 | .efu_niu_cfifo1_xfer_en (efu_niu_cfifo1_xfer_en), // <= | |
5121 | .efu_niu_cfifo_data (efu_niu_cfifo_data), // <= | |
5122 | .efu_niu_ipp0_clr (efu_niu_ipp0_clr), // <= | |
5123 | .efu_niu_ipp0_xfer_en (efu_niu_ipp0_xfer_en), // <= | |
5124 | .efu_niu_ipp1_clr (efu_niu_ipp1_clr), // <= | |
5125 | .efu_niu_ipp1_xfer_en (efu_niu_ipp1_xfer_en), // <= | |
5126 | .efu_niu_mac01_sfro_data (efu_niu_mac01_sfro_data), // <= | |
5127 | .efu_niu_mac0_ro_clr (efu_niu_mac0_ro_clr), // <= | |
5128 | .efu_niu_mac0_ro_xfer_en (efu_niu_mac0_ro_xfer_en), // <= | |
5129 | .efu_niu_mac0_sf_clr (efu_niu_mac0_sf_clr), // <= | |
5130 | .efu_niu_mac0_sf_xfer_en (efu_niu_mac0_sf_xfer_en), // <= | |
5131 | .efu_niu_mac1_ro_clr (efu_niu_mac1_ro_clr), // <= | |
5132 | .efu_niu_mac1_ro_xfer_en (efu_niu_mac1_ro_xfer_en), // <= | |
5133 | .efu_niu_mac1_sf_clr (efu_niu_mac1_sf_clr), // <= | |
5134 | .efu_niu_mac1_sf_xfer_en (efu_niu_mac1_sf_xfer_en), // <= | |
5135 | .gl_rtx_io2x_out (gl_io2x_out_c1b), // <= | |
5136 | .gl_rtx_io_out (gl_io_out_c1b), // <= | |
5137 | .mac_rxc_ack0 (mac_rxc_ack0), // <= | |
5138 | .mac_rxc_ack1 (mac_rxc_ack1), // <= | |
5139 | .mac_rxc_ctrl0 (mac_rxc_ctrl0), // <= | |
5140 | .mac_rxc_ctrl1 (mac_rxc_ctrl1), // <= | |
5141 | .mac_rxc_data0 (mac_rxc_data0[ 63 : 0 ]), // <= | |
5142 | .mac_rxc_data1 (mac_rxc_data1[ 63 : 0 ]), // <= | |
5143 | .mac_rxc_stat0 (mac_rxc_stat0[ 22 : 0 ]), // <= | |
5144 | .mac_rxc_stat1 (mac_rxc_stat1[ 22 : 0 ]), // <= | |
5145 | .mac_rxc_tag0 (mac_rxc_tag0), // <= | |
5146 | .mac_rxc_tag1 (mac_rxc_tag1), // <= | |
5147 | .mac_txc_req0 (mac_txc_req0), // <= | |
5148 | .mac_txc_req1 (mac_txc_req1), // <= | |
5149 | .meta_dmc_data (meta_dmc_data[ 127 : 0 ]), // <= | |
5150 | .meta_dmc_data_valid (meta_dmc_data_valid_txc), // <= | |
5151 | .meta_dmc_resp_address (meta_dmc_resp_address[ 63 : 0 ]), // <= | |
5152 | .meta_dmc_resp_byteenable (meta_dmc_resp_byteenable[ 15 : 0 ]), // <= | |
5153 | .meta_dmc_resp_client (meta_dmc_resp_client_txc), // <= | |
5154 | .meta_dmc_resp_cmd (meta_dmc_resp_cmd[ 7 : 0 ]), // <= | |
5155 | .meta_dmc_resp_cmd_status (meta_dmc_resp_cmd_status[ 3 : 0 ]), // <= | |
5156 | .meta_dmc_resp_complete (meta_dmc_resp_complete_txc), // <= | |
5157 | .meta_dmc_resp_data_status (meta_dmc_data_status[ 3 : 0 ]), // <= | |
5158 | .meta_dmc_resp_dma_num (meta_dmc_resp_dma_num[ 4 : 0 ]), // <= | |
5159 | .meta_dmc_resp_length (meta_dmc_resp_length[ 13 : 0 ]), // <= | |
5160 | .meta_dmc_resp_port_num (meta_dmc_resp_port_num[ 1 : 0 ]), // <= | |
5161 | .meta_dmc_resp_ready (meta_dmc_resp_ready), // <= | |
5162 | .meta_dmc_resp_trans_id (meta_dmc_resp_trans_id[ 5 : 0 ]), // <= | |
5163 | .meta_dmc_resp_transfer_cmpl (meta_dmc_resp_transfer_cmpl_txc), // <= | |
5164 | .pio_clients_addr (pio_clients_addr[ 19 : 0 ]), // <= | |
5165 | .pio_clients_rd (pio_clients_rd), // <= | |
5166 | .pio_clients_wdata (pio_clients_wdata[ 63 : 0 ]), // <= | |
5167 | .pio_fflp_sel (pio_fflp_sel), // <= | |
5168 | .pio_ipp_sel (pio_ipp_sel), // <= | |
5169 | .pio_txc_sel (pio_txc_sel), // <= | |
5170 | .pio_zcp_sel (pio_zcp_sel), // <= | |
5171 | .rst_por_ (gl_rst_niu_wmr_c1b), // <= | |
5172 | .rtx_mbist_scan_in (rtx_mbist_scan_in), // <= | |
5173 | .scan_in (tcu_socf_scan_out), // <= | |
5174 | .tcu_aclk (tcu_asic_aclk), // <= | |
5175 | .tcu_bclk (tcu_asic_bclk), // <= | |
5176 | .tcu_div_bypass (tcu_div_bypass), // <= | |
5177 | .tcu_mbist_bisi_en (tcu_mbist_bisi_en), // <= | |
5178 | .tcu_mbist_user_mode (tcu_mbist_user_mode), // <= | |
5179 | .tcu_pce_ov (tcu_pce_ov), // <= | |
5180 | .tcu_rtx_dmo_ctl (tcu_rtx_dmo_ctl[ 2 : 0 ]), // <= | |
5181 | .tcu_rtx_io_clk_stop (gl_rtx_io_clk_stop), // <= | |
5182 | .tcu_rtx_rxc_ipp0_mbist_start (tcu_rtx_rxc_ipp0_mbist_start), // <= | |
5183 | .tcu_rtx_rxc_ipp1_mbist_start (tcu_rtx_rxc_ipp1_mbist_start), // <= | |
5184 | .tcu_rtx_rxc_mb5_mbist_start (tcu_rtx_rxc_mb5_mbist_start), // <= | |
5185 | .tcu_rtx_rxc_mb6_mbist_start (tcu_rtx_rxc_mb6_mbist_start), // <= | |
5186 | .tcu_rtx_rxc_zcp0_mbist_start (tcu_rtx_rxc_zcp0_mbist_start), // <= | |
5187 | .tcu_rtx_rxc_zcp1_mbist_start (tcu_rtx_rxc_zcp1_mbist_start), // <= | |
5188 | .tcu_rtx_txc_txe0_mbist_start (tcu_rtx_txc_txe0_mbist_start), // <= | |
5189 | .tcu_rtx_txc_txe1_mbist_start (tcu_rtx_txc_txe1_mbist_start), // <= | |
5190 | .tcu_scan_en (tcu_asic_scan_en), // <= | |
5191 | .tcu_se_scancollar_in (tcu_asic_se_scancollar_in), // <= | |
5192 | .tcu_se_scancollar_out (tcu_asic_se_scancollar_out), // <= | |
5193 | .tcu_wr_inhibit (tcu_asic_array_wr_inhibit), // <= | |
5194 | .dmc_meta_resp_accept (txc_meta_resp_accept), // => | |
5195 | .fflp_debug_port (fflp_debug_port[ 31 : 0 ]), // => | |
5196 | .fflp_pio_ack (fflp_pio_ack), // => | |
5197 | .fflp_pio_err (fflp_pio_err), // => | |
5198 | .fflp_pio_intr (fflp_pio_intr), // => | |
5199 | .fflp_pio_rdata (fflp_pio_rdata[ 63 : 0 ]), // => | |
5200 | .ipp_debug_port (ipp_debug_port[ 31 : 0 ]), // => | |
5201 | .ipp_dmc_dat_ack0 (ipp_dmc_dat_ack0), // => | |
5202 | .ipp_dmc_dat_ack1 (ipp_dmc_dat_ack1), // => | |
5203 | .ipp_dmc_dat_err0 (ipp_dmc_dat_err0), // => | |
5204 | .ipp_dmc_dat_err1 (ipp_dmc_dat_err1), // => | |
5205 | .ipp_dmc_data0 (ipp_dmc_data0[ 129 : 0 ]), // => | |
5206 | .ipp_dmc_data1 (ipp_dmc_data1[ 129 : 0 ]), // => | |
5207 | .ipp_dmc_ful_pkt0 (ipp_dmc_ful_pkt0), // => | |
5208 | .ipp_dmc_ful_pkt1 (ipp_dmc_ful_pkt1), // => | |
5209 | .ipp_pio_ack (ipp_pio_ack), // => | |
5210 | .ipp_pio_err (ipp_pio_err), // => | |
5211 | .ipp_pio_intr (ipp_pio_intr), // => | |
5212 | .ipp_pio_rdata (ipp_pio_rdata[ 63 : 0 ]), // => | |
5213 | .niu_efu_4k_data (niu_efu_4k_data), // => | |
5214 | .niu_efu_4k_xfer_en (niu_efu_4k_xfer_en), // => | |
5215 | .niu_efu_cfifo0_data (niu_efu_cfifo0_data), // => | |
5216 | .niu_efu_cfifo0_xfer_en (niu_efu_cfifo0_xfer_en), // => | |
5217 | .niu_efu_cfifo1_data (niu_efu_cfifo1_data), // => | |
5218 | .niu_efu_cfifo1_xfer_en (niu_efu_cfifo1_xfer_en), // => | |
5219 | .niu_efu_ipp0_data (niu_efu_ipp0_data), // => | |
5220 | .niu_efu_ipp0_xfer_en (niu_efu_ipp0_xfer_en), // => | |
5221 | .niu_efu_ipp1_data (niu_efu_ipp1_data), // => | |
5222 | .niu_efu_ipp1_xfer_en (niu_efu_ipp1_xfer_en), // => | |
5223 | .niu_efu_mac0_ro_data (niu_efu_mac0_ro_data), // => | |
5224 | .niu_efu_mac0_ro_xfer_en (niu_efu_mac0_ro_xfer_en), // => | |
5225 | .niu_efu_mac0_sf_data (niu_efu_mac0_sf_data), // => | |
5226 | .niu_efu_mac0_sf_xfer_en (niu_efu_mac0_sf_xfer_en), // => | |
5227 | .niu_efu_mac1_ro_data (niu_efu_mac1_ro_data), // => | |
5228 | .niu_efu_mac1_ro_xfer_en (niu_efu_mac1_ro_xfer_en), // => | |
5229 | .niu_efu_mac1_sf_data (niu_efu_mac1_sf_data), // => | |
5230 | .niu_efu_mac1_sf_xfer_en (niu_efu_mac1_sf_xfer_en), // => | |
5231 | .niu_txc_interrupts (niu_txc_interrupts), // => | |
5232 | .rtx_mbist_scan_out (rtx_mbist_scan_out), // => | |
5233 | .rtx_rxc_ipp0_tcu_mbist_done (rtx_rxc_ipp0_tcu_mbist_done), // => | |
5234 | .rtx_rxc_ipp0_tcu_mbist_fail (rtx_rxc_ipp0_tcu_mbist_fail), // => | |
5235 | .rtx_rxc_ipp1_tcu_mbist_done (rtx_rxc_ipp1_tcu_mbist_done), // => | |
5236 | .rtx_rxc_ipp1_tcu_mbist_fail (rtx_rxc_ipp1_tcu_mbist_fail), // => | |
5237 | .rtx_rxc_mb5_tcu_mbist_done (rtx_rxc_mb5_tcu_mbist_done), // => | |
5238 | .rtx_rxc_mb5_tcu_mbist_fail (rtx_rxc_mb5_tcu_mbist_fail), // => | |
5239 | .rtx_rxc_mb6_tcu_mbist_done (rtx_rxc_mb6_tcu_mbist_done), // => | |
5240 | .rtx_rxc_mb6_tcu_mbist_fail (rtx_rxc_mb6_tcu_mbist_fail), // => | |
5241 | .rtx_rxc_zcp0_tcu_mbist_done (rtx_rxc_zcp0_tcu_mbist_done), // => | |
5242 | .rtx_rxc_zcp0_tcu_mbist_fail (rtx_rxc_zcp0_tcu_mbist_fail), // => | |
5243 | .rtx_rxc_zcp1_tcu_mbist_done (rtx_rxc_zcp1_tcu_mbist_done), // => | |
5244 | .rtx_rxc_zcp1_tcu_mbist_fail (rtx_rxc_zcp1_tcu_mbist_fail), // => | |
5245 | .rtx_tcu_dmo_data_out (rtx_tcu_dmo_data_out[ 39 : 0 ]), // => | |
5246 | .rtx_txc_txe0_tcu_mbist_done (rtx_txc_txe0_tcu_mbist_done), // => | |
5247 | .rtx_txc_txe0_tcu_mbist_fail (rtx_txc_txe0_tcu_mbist_fail), // => | |
5248 | .rtx_txc_txe1_tcu_mbist_done (rtx_txc_txe1_tcu_mbist_done), // => | |
5249 | .rtx_txc_txe1_tcu_mbist_fail (rtx_txc_txe1_tcu_mbist_fail), // => | |
5250 | .rxc_mac_req0 (rxc_mac_req0), // => | |
5251 | .rxc_mac_req1 (rxc_mac_req1), // => | |
5252 | .scan_out (rtx_scan_out), // => | |
5253 | .txc_arb1_req (txc_arb1_req), // => | |
5254 | .txc_arb1_req_address (txc_arb1_req_address[ 63 : 0 ]), // => | |
5255 | .txc_arb1_req_cmd (txc_arb1_req_cmd[ 7 : 0 ]), // => | |
5256 | .txc_arb1_req_dma_num (txc_arb1_req_dma_num[ 4 : 0 ]), // => | |
5257 | .txc_arb1_req_func_num (txc_arb1_req_func_num[ 1 : 0 ]), // => | |
5258 | .txc_arb1_req_length (txc_arb1_req_length[ 13 : 0 ]), // => | |
5259 | .txc_arb1_req_port_num (txc_arb1_req_port_num[ 1 : 0 ]), // => | |
5260 | .txc_debug_port (txc_debug_port[ 31 : 0 ]), // => | |
5261 | .txc_dmc_dma0_getnxtdesc (txc_dmc_dma0_getnxtdesc), // => | |
5262 | .txc_dmc_dma0_inc_head (txc_dmc_dma0_inc_head), // => | |
5263 | .txc_dmc_dma0_inc_pkt_cnt (txc_dmc_dma0_inc_pkt_cnt), // => | |
5264 | .txc_dmc_dma0_mark_bit (txc_dmc_dma0_mark_bit), // => | |
5265 | .txc_dmc_dma0_reset_done (txc_dmc_dma0_reset_done), // => | |
5266 | .txc_dmc_dma10_getnxtdesc (txc_dmc_dma10_getnxtdesc), // => | |
5267 | .txc_dmc_dma10_inc_head (txc_dmc_dma10_inc_head), // => | |
5268 | .txc_dmc_dma10_inc_pkt_cnt (txc_dmc_dma10_inc_pkt_cnt), // => | |
5269 | .txc_dmc_dma10_mark_bit (txc_dmc_dma10_mark_bit), // => | |
5270 | .txc_dmc_dma10_reset_done (txc_dmc_dma10_reset_done), // => | |
5271 | .txc_dmc_dma11_getnxtdesc (txc_dmc_dma11_getnxtdesc), // => | |
5272 | .txc_dmc_dma11_inc_head (txc_dmc_dma11_inc_head), // => | |
5273 | .txc_dmc_dma11_inc_pkt_cnt (txc_dmc_dma11_inc_pkt_cnt), // => | |
5274 | .txc_dmc_dma11_mark_bit (txc_dmc_dma11_mark_bit), // => | |
5275 | .txc_dmc_dma11_reset_done (txc_dmc_dma11_reset_done), // => | |
5276 | .txc_dmc_dma12_getnxtdesc (txc_dmc_dma12_getnxtdesc), // => | |
5277 | .txc_dmc_dma12_inc_head (txc_dmc_dma12_inc_head), // => | |
5278 | .txc_dmc_dma12_inc_pkt_cnt (txc_dmc_dma12_inc_pkt_cnt), // => | |
5279 | .txc_dmc_dma12_mark_bit (txc_dmc_dma12_mark_bit), // => | |
5280 | .txc_dmc_dma12_reset_done (txc_dmc_dma12_reset_done), // => | |
5281 | .txc_dmc_dma13_getnxtdesc (txc_dmc_dma13_getnxtdesc), // => | |
5282 | .txc_dmc_dma13_inc_head (txc_dmc_dma13_inc_head), // => | |
5283 | .txc_dmc_dma13_inc_pkt_cnt (txc_dmc_dma13_inc_pkt_cnt), // => | |
5284 | .txc_dmc_dma13_mark_bit (txc_dmc_dma13_mark_bit), // => | |
5285 | .txc_dmc_dma13_reset_done (txc_dmc_dma13_reset_done), // => | |
5286 | .txc_dmc_dma14_getnxtdesc (txc_dmc_dma14_getnxtdesc), // => | |
5287 | .txc_dmc_dma14_inc_head (txc_dmc_dma14_inc_head), // => | |
5288 | .txc_dmc_dma14_inc_pkt_cnt (txc_dmc_dma14_inc_pkt_cnt), // => | |
5289 | .txc_dmc_dma14_mark_bit (txc_dmc_dma14_mark_bit), // => | |
5290 | .txc_dmc_dma14_reset_done (txc_dmc_dma14_reset_done), // => | |
5291 | .txc_dmc_dma15_getnxtdesc (txc_dmc_dma15_getnxtdesc), // => | |
5292 | .txc_dmc_dma15_inc_head (txc_dmc_dma15_inc_head), // => | |
5293 | .txc_dmc_dma15_inc_pkt_cnt (txc_dmc_dma15_inc_pkt_cnt), // => | |
5294 | .txc_dmc_dma15_mark_bit (txc_dmc_dma15_mark_bit), // => | |
5295 | .txc_dmc_dma15_reset_done (txc_dmc_dma15_reset_done), // => | |
5296 | .txc_dmc_dma1_getnxtdesc (txc_dmc_dma1_getnxtdesc), // => | |
5297 | .txc_dmc_dma1_inc_head (txc_dmc_dma1_inc_head), // => | |
5298 | .txc_dmc_dma1_inc_pkt_cnt (txc_dmc_dma1_inc_pkt_cnt), // => | |
5299 | .txc_dmc_dma1_mark_bit (txc_dmc_dma1_mark_bit), // => | |
5300 | .txc_dmc_dma1_reset_done (txc_dmc_dma1_reset_done), // => | |
5301 | .txc_dmc_dma2_getnxtdesc (txc_dmc_dma2_getnxtdesc), // => | |
5302 | .txc_dmc_dma2_inc_head (txc_dmc_dma2_inc_head), // => | |
5303 | .txc_dmc_dma2_inc_pkt_cnt (txc_dmc_dma2_inc_pkt_cnt), // => | |
5304 | .txc_dmc_dma2_mark_bit (txc_dmc_dma2_mark_bit), // => | |
5305 | .txc_dmc_dma2_reset_done (txc_dmc_dma2_reset_done), // => | |
5306 | .txc_dmc_dma3_getnxtdesc (txc_dmc_dma3_getnxtdesc), // => | |
5307 | .txc_dmc_dma3_inc_head (txc_dmc_dma3_inc_head), // => | |
5308 | .txc_dmc_dma3_inc_pkt_cnt (txc_dmc_dma3_inc_pkt_cnt), // => | |
5309 | .txc_dmc_dma3_mark_bit (txc_dmc_dma3_mark_bit), // => | |
5310 | .txc_dmc_dma3_reset_done (txc_dmc_dma3_reset_done), // => | |
5311 | .txc_dmc_dma4_getnxtdesc (txc_dmc_dma4_getnxtdesc), // => | |
5312 | .txc_dmc_dma4_inc_head (txc_dmc_dma4_inc_head), // => | |
5313 | .txc_dmc_dma4_inc_pkt_cnt (txc_dmc_dma4_inc_pkt_cnt), // => | |
5314 | .txc_dmc_dma4_mark_bit (txc_dmc_dma4_mark_bit), // => | |
5315 | .txc_dmc_dma4_reset_done (txc_dmc_dma4_reset_done), // => | |
5316 | .txc_dmc_dma5_getnxtdesc (txc_dmc_dma5_getnxtdesc), // => | |
5317 | .txc_dmc_dma5_inc_head (txc_dmc_dma5_inc_head), // => | |
5318 | .txc_dmc_dma5_inc_pkt_cnt (txc_dmc_dma5_inc_pkt_cnt), // => | |
5319 | .txc_dmc_dma5_mark_bit (txc_dmc_dma5_mark_bit), // => | |
5320 | .txc_dmc_dma5_reset_done (txc_dmc_dma5_reset_done), // => | |
5321 | .txc_dmc_dma6_getnxtdesc (txc_dmc_dma6_getnxtdesc), // => | |
5322 | .txc_dmc_dma6_inc_head (txc_dmc_dma6_inc_head), // => | |
5323 | .txc_dmc_dma6_inc_pkt_cnt (txc_dmc_dma6_inc_pkt_cnt), // => | |
5324 | .txc_dmc_dma6_mark_bit (txc_dmc_dma6_mark_bit), // => | |
5325 | .txc_dmc_dma6_reset_done (txc_dmc_dma6_reset_done), // => | |
5326 | .txc_dmc_dma7_getnxtdesc (txc_dmc_dma7_getnxtdesc), // => | |
5327 | .txc_dmc_dma7_inc_head (txc_dmc_dma7_inc_head), // => | |
5328 | .txc_dmc_dma7_inc_pkt_cnt (txc_dmc_dma7_inc_pkt_cnt), // => | |
5329 | .txc_dmc_dma7_mark_bit (txc_dmc_dma7_mark_bit), // => | |
5330 | .txc_dmc_dma7_reset_done (txc_dmc_dma7_reset_done), // => | |
5331 | .txc_dmc_dma8_getnxtdesc (txc_dmc_dma8_getnxtdesc), // => | |
5332 | .txc_dmc_dma8_inc_head (txc_dmc_dma8_inc_head), // => | |
5333 | .txc_dmc_dma8_inc_pkt_cnt (txc_dmc_dma8_inc_pkt_cnt), // => | |
5334 | .txc_dmc_dma8_mark_bit (txc_dmc_dma8_mark_bit), // => | |
5335 | .txc_dmc_dma8_reset_done (txc_dmc_dma8_reset_done), // => | |
5336 | .txc_dmc_dma9_getnxtdesc (txc_dmc_dma9_getnxtdesc), // => | |
5337 | .txc_dmc_dma9_inc_head (txc_dmc_dma9_inc_head), // => | |
5338 | .txc_dmc_dma9_inc_pkt_cnt (txc_dmc_dma9_inc_pkt_cnt), // => | |
5339 | .txc_dmc_dma9_mark_bit (txc_dmc_dma9_mark_bit), // => | |
5340 | .txc_dmc_dma9_reset_done (txc_dmc_dma9_reset_done), // => | |
5341 | .txc_dmc_dma_nack_pkt_rd (txc_dmc_dma_nack_pkt_rd[ 15 : 0 ]), // => | |
5342 | .txc_dmc_nack_pkt_rd (txc_dmc_nack_pkt_rd), // => | |
5343 | .txc_dmc_nack_pkt_rd_addr (txc_dmc_nack_pkt_rd_addr[ 43 : 0 ]), // => | |
5344 | .txc_dmc_p0_dma_pkt_size_err (txc_dmc_p0_dma_pkt_size_err[ 15 : 0 ]), // => | |
5345 | .txc_dmc_p0_pkt_size_err (txc_dmc_p0_pkt_size_err), // => | |
5346 | .txc_dmc_p0_pkt_size_err_addr (txc_dmc_p0_pkt_size_err_addr[ 43 : 0 ]), // => | |
5347 | .txc_dmc_p1_dma_pkt_size_err (txc_dmc_p1_dma_pkt_size_err[ 15 : 0 ]), // => | |
5348 | .txc_dmc_p1_pkt_size_err (txc_dmc_p1_pkt_size_err), // => | |
5349 | .txc_dmc_p1_pkt_size_err_addr (txc_dmc_p1_pkt_size_err_addr[ 43 : 0 ]), // => | |
5350 | .txc_mac_abort0 (txc_mac_abort0), // => | |
5351 | .txc_mac_abort1 (txc_mac_abort1), // => | |
5352 | .txc_mac_ack0 (txc_mac_ack0), // => | |
5353 | .txc_mac_ack1 (txc_mac_ack1), // => | |
5354 | .txc_mac_data0 (txc_mac_data0[ 63 : 0 ]), // => | |
5355 | .txc_mac_data1 (txc_mac_data1[ 63 : 0 ]), // => | |
5356 | .txc_mac_stat0 (txc_mac_stat0[ 3 : 0 ]), // => | |
5357 | .txc_mac_stat1 (txc_mac_stat1[ 3 : 0 ]), // => | |
5358 | .txc_mac_tag0 (txc_mac_tag0), // => | |
5359 | .txc_mac_tag1 (txc_mac_tag1), // => | |
5360 | .txc_pio_ack (txc_pio_ack), // => | |
5361 | .txc_pio_err (txc_pio_err), // => | |
5362 | .txc_pio_rdata (txc_pio_rdata[ 63 : 0 ]), // => | |
5363 | .zcp_debug_port (zcp_debug_port[ 31 : 0 ]), // => | |
5364 | .zcp_dmc_ack0 (zcp_dmc_ack0), // => | |
5365 | .zcp_dmc_ack1 (zcp_dmc_ack1), // => | |
5366 | .zcp_dmc_dat0 (zcp_dmc_dat0[ 129 : 0 ]), // => | |
5367 | .zcp_dmc_dat1 (zcp_dmc_dat1[ 129 : 0 ]), // => | |
5368 | .zcp_dmc_dat_err0 (zcp_dmc_dat_err0), // => | |
5369 | .zcp_dmc_dat_err1 (zcp_dmc_dat_err1), // => | |
5370 | .zcp_dmc_ful_pkt0 (zcp_dmc_ful_pkt0), // => | |
5371 | .zcp_dmc_ful_pkt1 (zcp_dmc_ful_pkt1), // => | |
5372 | .zcp_pio_ack (zcp_pio_ack), // => | |
5373 | .zcp_pio_err (zcp_pio_err), // => | |
5374 | .zcp_pio_intr (zcp_pio_intr), // => | |
5375 | .zcp_pio_rdata (zcp_pio_rdata[ 63 : 0 ]), | |
5376 | .tcu_atpg_mode(tcu_atpg_mode) // => | |
5377 | ); | |
5378 | `endif // OPENSPARC_CMP | |
5379 | ||
5380 | ||
5381 | ||
5382 | // leave this instance out of cmp model | |
5383 | `ifdef OPENSPARC_CMP | |
5384 | `else | |
5385 | mac mac ( | |
5386 | .gl_mac_io_out (gl_io_out_c1b), // <= | |
5387 | .cluster_arst_l (cluster_arst_l), // <= | |
5388 | .esr_mac_rclk_0 (esr_mac_rclk_0[ 3 : 0 ]), // <= | |
5389 | .esr_mac_rclk_1 (esr_mac_rclk_1[ 3 : 0 ]), // <= | |
5390 | .esr_mac_rxd0_0 (esr_mac_rxd0_0[ 9 : 0 ]), // <= | |
5391 | .esr_mac_rxd0_1 (esr_mac_rxd0_1[ 9 : 0 ]), // <= | |
5392 | .esr_mac_rxd1_0 (esr_mac_rxd1_0[ 9 : 0 ]), // <= | |
5393 | .esr_mac_rxd1_1 (esr_mac_rxd1_1[ 9 : 0 ]), // <= | |
5394 | .esr_mac_rxd2_0 (esr_mac_rxd2_0[ 9 : 0 ]), // <= | |
5395 | .esr_mac_rxd2_1 (esr_mac_rxd2_1[ 9 : 0 ]), // <= | |
5396 | .esr_mac_rxd3_0 (esr_mac_rxd3_0[ 9 : 0 ]), // <= | |
5397 | .esr_mac_rxd3_1 (esr_mac_rxd3_1[ 9 : 0 ]), // <= | |
5398 | .esr_mac_tclk_0 (esr_mac_tclk_0), // <= | |
5399 | .esr_mac_tclk_1 (esr_mac_tclk_1), // <= | |
5400 | .cmp_gclk_c1_mac (cmp_gclk_c1_mac), // <= | |
5401 | .gl_mac_io_clk_stop (gl_mac_io_clk_stop), // <= | |
5402 | .mac_125rx_test_clk (mac_125rx_test_clk), // <= | |
5403 | .mac_125tx_test_clk (mac_125tx_test_clk), // <= | |
5404 | .mac_156rx_test_clk (mac_156rx_test_clk), // <= | |
5405 | .mac_156tx_test_clk (mac_156tx_test_clk), // <= | |
5406 | .mac_312rx_test_clk (mac_312rx_test_clk), // <= | |
5407 | .mac_312tx_test_clk (mac_312tx_test_clk), // <= | |
5408 | .mac_reset0 (mac_reset0), // <= | |
5409 | .mac_reset1 (mac_reset1), // <= | |
5410 | .mdi (mdi), // <= | |
5411 | .peu_mac_sbs_input (peu_mac_sbs_input), // <= | |
5412 | .pio_clients_addr (pio_clients_addr[ 19 : 0 ]), // <= | |
5413 | .pio_clients_rd (pio_clients_rd), // <= | |
5414 | .pio_clients_wdata (pio_clients_wdata[ 31 : 0 ]), // <= | |
5415 | .pio_mac_sel (pio_mac_sel), // <= | |
5416 | .gl_mac_ (gl_rst_mac_c1b), // <= | |
5417 | .rxc_mac_req0 (rxc_mac_req0), // <= | |
5418 | .rxc_mac_req1 (rxc_mac_req1), // <= | |
5419 | .scan_in (tcu_soc5_scan_out), // <= | |
5420 | .stspll_0 (stspll_0[ 3 : 0 ]), // <= | |
5421 | .stspll_1 (stspll_1[ 3 : 0 ]), // <= | |
5422 | .stsrx0_0 (stsrx0_0[ 7 : 0 ]), // <= | |
5423 | .stsrx0_1 (stsrx0_1[ 7 : 0 ]), // <= | |
5424 | .stsrx1_0 (stsrx1_0[ 7 : 0 ]), // <= | |
5425 | .stsrx1_1 (stsrx1_1[ 7 : 0 ]), // <= | |
5426 | .stsrx2_0 (stsrx2_0[ 7 : 0 ]), // <= | |
5427 | .stsrx2_1 (stsrx2_1[ 7 : 0 ]), // <= | |
5428 | .stsrx3_0 (stsrx3_0[ 7 : 0 ]), // <= | |
5429 | .stsrx3_1 (stsrx3_1[ 7 : 0 ]), // <= | |
5430 | .ststx0_0 (ststx0_0[ 3 : 0 ]), // <= | |
5431 | .ststx0_1 (ststx0_1[ 3 : 0 ]), // <= | |
5432 | .ststx1_0 (ststx1_0[ 3 : 0 ]), // <= | |
5433 | .ststx1_1 (ststx1_1[ 3 : 0 ]), // <= | |
5434 | .ststx2_0 (ststx2_0[ 3 : 0 ]), // <= | |
5435 | .ststx2_1 (ststx2_1[ 3 : 0 ]), // <= | |
5436 | .ststx3_0 (ststx3_0[ 3 : 0 ]), // <= | |
5437 | .ststx3_1 (ststx3_1[ 3 : 0 ]), // <= | |
5438 | .tcu_wr_inhibit (tcu_asic_array_wr_inhibit), // <= | |
5439 | .tcu_aclk (tcu_asic_aclk), // <= | |
5440 | .tcu_bclk (tcu_asic_bclk), // <= | |
5441 | .tcu_div_bypass (tcu_div_bypass), // <= | |
5442 | .tcu_pce_ov (tcu_pce_ov), // <= | |
5443 | .tcu_sbs_acmode (tcu_sbs_acmode), // <= | |
5444 | .tcu_sbs_actestsignal (tcu_sbs_actestsignal), // <= | |
5445 | .tcu_sbs_aclk (tcu_sbs_aclk), // <= | |
5446 | .tcu_sbs_bclk (tcu_sbs_bclk), // <= | |
5447 | .tcu_sbs_clk (tcu_sbs_clk), // <= | |
5448 | .tcu_sbs_enbspt (tcu_sbs_enbspt), // <= | |
5449 | .tcu_sbs_enbsrx (tcu_sbs_enbsrx), // <= | |
5450 | .tcu_sbs_enbstx (tcu_sbs_enbstx), // <= | |
5451 | .tcu_sbs_scan_en (tcu_sbs_scan_en), // <= | |
5452 | .tcu_sbs_uclk (tcu_sbs_uclk), // <= | |
5453 | .tcu_scan_en (tcu_asic_scan_en), // <= | |
5454 | .tcu_scan_mode (tcu_mac_testmode), // <= | |
5455 | .txc_mac_abort0 (txc_mac_abort0), // <= | |
5456 | .txc_mac_abort1 (txc_mac_abort1), // <= | |
5457 | .txc_mac_ack0 (txc_mac_ack0), // <= | |
5458 | .txc_mac_ack1 (txc_mac_ack1), // <= | |
5459 | .txc_mac_data0 (txc_mac_data0[ 63 : 0 ]), // <= | |
5460 | .txc_mac_data1 (txc_mac_data1[ 63 : 0 ]), // <= | |
5461 | .txc_mac_stat0 (txc_mac_stat0[ 3 : 0 ]), // <= | |
5462 | .txc_mac_stat1 (txc_mac_stat1[ 3 : 0 ]), // <= | |
5463 | .txc_mac_tag0 (txc_mac_tag0), // <= | |
5464 | .txc_mac_tag1 (txc_mac_tag1), // <= | |
5465 | .cfgpll_0 (cfgpll_0[ 11 : 0 ]), // => | |
5466 | .cfgpll_1 (cfgpll_1[ 11 : 0 ]), // => | |
5467 | .cfgrx0_0 (cfgrx0_0[ 27 : 0 ]), // => | |
5468 | .cfgrx0_1 (cfgrx0_1[ 27 : 0 ]), // => | |
5469 | .cfgrx1_0 (cfgrx1_0[ 27 : 0 ]), // => | |
5470 | .cfgrx1_1 (cfgrx1_1[ 27 : 0 ]), // => | |
5471 | .cfgrx2_0 (cfgrx2_0[ 27 : 0 ]), // => | |
5472 | .cfgrx2_1 (cfgrx2_1[ 27 : 0 ]), // => | |
5473 | .cfgrx3_0 (cfgrx3_0[ 27 : 0 ]), // => | |
5474 | .cfgrx3_1 (cfgrx3_1[ 27 : 0 ]), // => | |
5475 | .cfgtx0_0 (cfgtx0_0[ 19 : 0 ]), // => | |
5476 | .cfgtx0_1 (cfgtx0_1[ 19 : 0 ]), // => | |
5477 | .cfgtx1_0 (cfgtx1_0[ 19 : 0 ]), // => | |
5478 | .cfgtx1_1 (cfgtx1_1[ 19 : 0 ]), // => | |
5479 | .cfgtx2_0 (cfgtx2_0[ 19 : 0 ]), // => | |
5480 | .cfgtx2_1 (cfgtx2_1[ 19 : 0 ]), // => | |
5481 | .cfgtx3_0 (cfgtx3_0[ 19 : 0 ]), // => | |
5482 | .cfgtx3_1 (cfgtx3_1[ 19 : 0 ]), // => | |
5483 | .mac_debug_port (mac_debug_port[ 31 : 0 ]), // => | |
5484 | .mac_esr_tclk_0 (mac_esr_tclk_0[ 3 : 0 ]), // => | |
5485 | .mac_esr_tclk_1 (mac_esr_tclk_1[ 3 : 0 ]), // => | |
5486 | .mac_esr_txd0_0 (mac_esr_txd0_0[ 9 : 0 ]), // => | |
5487 | .mac_esr_txd0_1 (mac_esr_txd0_1[ 9 : 0 ]), // => | |
5488 | .mac_esr_txd1_0 (mac_esr_txd1_0[ 9 : 0 ]), // => | |
5489 | .mac_esr_txd1_1 (mac_esr_txd1_1[ 9 : 0 ]), // => | |
5490 | .mac_esr_txd2_0 (mac_esr_txd2_0[ 9 : 0 ]), // => | |
5491 | .mac_esr_txd2_1 (mac_esr_txd2_1[ 9 : 0 ]), // => | |
5492 | .mac_esr_txd3_0 (mac_esr_txd3_0[ 9 : 0 ]), // => | |
5493 | .mac_esr_txd3_1 (mac_esr_txd3_1[ 9 : 0 ]), // => | |
5494 | .mac_mcu_3_sbs_output (mac_mcu_3_sbs_output), // => | |
5495 | .mac_pio_ack (mac_pio_ack), // => | |
5496 | .mac_pio_err (mac_pio_err), // => | |
5497 | .mac_pio_intr0 (mac_pio_intr0), // => | |
5498 | .mac_pio_intr1 (mac_pio_intr1), // => | |
5499 | .mac_pio_rdata (mac_pio_rdata[ 63 : 0 ]), // => | |
5500 | .mac_rxc_ack0 (mac_rxc_ack0), // => | |
5501 | .mac_rxc_ack1 (mac_rxc_ack1), // => | |
5502 | .mac_rxc_ctrl0 (mac_rxc_ctrl0), // => | |
5503 | .mac_rxc_ctrl1 (mac_rxc_ctrl1), // => | |
5504 | .mac_rxc_data0 (mac_rxc_data0[ 63 : 0 ]), // => | |
5505 | .mac_rxc_data1 (mac_rxc_data1[ 63 : 0 ]), // => | |
5506 | .mac_rxc_stat0 (mac_rxc_stat0[ 22 : 0 ]), // => | |
5507 | .mac_rxc_stat1 (mac_rxc_stat1[ 22 : 0 ]), // => | |
5508 | .mac_rxc_tag0 (mac_rxc_tag0), // => | |
5509 | .mac_rxc_tag1 (mac_rxc_tag1), // => | |
5510 | .mac_txc_req0 (mac_txc_req0), // => | |
5511 | .mac_txc_req1 (mac_txc_req1), // => | |
5512 | .mdoe (mdoe), // => | |
5513 | .mif_pio_intr (mif_pio_intr), // => | |
5514 | .scan_out (mac_scan_out), // => | |
5515 | .testcfg_0 (testcfg_0[ 15 : 0 ]), // => | |
5516 | .testcfg_1 (testcfg_1[ 15 : 0 ]), // => | |
5517 | .xaui_act_led_0 (xaui_act_led_0), // => | |
5518 | .xaui_act_led_1 (xaui_act_led_1), // => | |
5519 | .xaui_link_led_0 (xaui_link_led_0), // => | |
5520 | .xaui_link_led_1 (xaui_link_led_1), // => | |
5521 | .xaui_mdint1_l(mio_mac_xaui_mdint1_l), | |
5522 | .xaui_mdint0_l(mio_mac_xaui_mdint0_l), | |
5523 | .mdclk (mdc), | |
5524 | .tcu_atpg_mode(tcu_atpg_mode) // => | |
5525 | ); | |
5526 | `endif // OPENSPARC_CMP | |
5527 | ||
5528 | ||
5529 | // leave this instance out of cmp model | |
5530 | `ifdef OPENSPARC_CMP | |
5531 | `else | |
5532 | esr esr ( | |
5533 | .XAUI0_AMUX (XAUI0_AMUX), // => | |
5534 | .XAUI0_TX_N (XAUI0_TX_N[ 3 : 0 ]), // => | |
5535 | .XAUI0_TX_P (XAUI0_TX_P[ 3 : 0 ]), // => | |
5536 | .XAUI0_REFCLK_N (XAUI0_REFCLK_N), // <= | |
5537 | .XAUI0_REFCLK_P (XAUI0_REFCLK_P), // <= | |
5538 | .XAUI0_RX_N (XAUI0_RX_N[ 3 : 0 ]), // <= | |
5539 | .XAUI0_RX_P (XAUI0_RX_P[ 3 : 0 ]), // <= | |
5540 | .esr_mac_tclk_0 (esr_mac_tclk_0), // => | |
5541 | .esr_mac_rclk_0 (esr_mac_rclk_0[ 3 : 0 ]), // => | |
5542 | .esr_mac_rxd0_0 (esr_mac_rxd0_0[ 9 : 0 ]), // => | |
5543 | .esr_mac_rxd1_0 (esr_mac_rxd1_0[ 9 : 0 ]), // => | |
5544 | .esr_mac_rxd2_0 (esr_mac_rxd2_0[ 9 : 0 ]), // => | |
5545 | .esr_mac_rxd3_0 (esr_mac_rxd3_0[ 9 : 0 ]), // => | |
5546 | .mac_esr_tclk_0 (mac_esr_tclk_0[ 3 : 0 ]), // <= | |
5547 | .mac_esr_txd0_0 (mac_esr_txd0_0[ 9 : 0 ]), // <= | |
5548 | .mac_esr_txd1_0 (mac_esr_txd1_0[ 9 : 0 ]), // <= | |
5549 | .mac_esr_txd2_0 (mac_esr_txd2_0[ 9 : 0 ]), // <= | |
5550 | .mac_esr_txd3_0 (mac_esr_txd3_0[ 9 : 0 ]), // <= | |
5551 | .stcicfg_0 (tcu_stcicfg[ 1 : 0 ]), // <= | |
5552 | .stciclk_0 (tcu_stciclk), // <= | |
5553 | .stcid_0 (esr_stcid), // <= | |
5554 | .stciq_0 (stcid_1), // => | |
5555 | .rxbclkin_0 (esr_mac_rclk_0[ 3 : 0 ]), // => | |
5556 | .testclkr_0 (mio_esr_testclkr), // <= | |
5557 | .testclkt_0 (mio_esr_testclkt), // <= | |
5558 | .cfgtx0_0 (cfgtx0_0[ 19 : 0 ]), // <= | |
5559 | .cfgtx1_0 (cfgtx1_0[ 19 : 0 ]), // <= | |
5560 | .cfgtx2_0 (cfgtx2_0[ 19 : 0 ]), // <= | |
5561 | .cfgtx3_0 (cfgtx3_0[ 19 : 0 ]), // <= | |
5562 | .cfgrx0_0 (cfgrx0_0[ 27 : 0 ]), // <= | |
5563 | .cfgrx1_0 (cfgrx1_0[ 27 : 0 ]), // <= | |
5564 | .cfgrx2_0 (cfgrx2_0[ 27 : 0 ]), // <= | |
5565 | .cfgrx3_0 (cfgrx3_0[ 27 : 0 ]), // <= | |
5566 | .cfgpll_0 (cfgpll_0[ 11 : 0 ]), // <= | |
5567 | .testcfg_0 (testcfg_0[ 15 : 0 ]), // <= | |
5568 | .ststx0_0 (ststx0_0[ 3 : 0 ]), // => | |
5569 | .ststx1_0 (ststx1_0[ 3 : 0 ]), // => | |
5570 | .ststx2_0 (ststx2_0[ 3 : 0 ]), // => | |
5571 | .ststx3_0 (ststx3_0[ 3 : 0 ]), // => | |
5572 | .stsrx0_0 (stsrx0_0[ 7 : 0 ]), // => | |
5573 | .stsrx1_0 (stsrx1_0[ 7 : 0 ]), // => | |
5574 | .stsrx2_0 (stsrx2_0[ 7 : 0 ]), // => | |
5575 | .stsrx3_0 (stsrx3_0[ 7 : 0 ]), // => | |
5576 | .stspll_0 (stspll_0[ 3 : 0 ]), // => | |
5577 | .fdo_0 (fdi_1), // => | |
5578 | .fclk_0 (efu_niu_fclk), // <= | |
5579 | .fclrz_0 (efu_niu_fclrz), // <= | |
5580 | .fdi_0 (efu_niu_fdi), // <= | |
5581 | .XAUI1_AMUX (XAUI1_AMUX), // => | |
5582 | .XAUI1_TX_N (XAUI1_TX_N[ 3 : 0 ]), // => | |
5583 | .XAUI1_TX_P (XAUI1_TX_P[ 3 : 0 ]), // => | |
5584 | .XAUI1_RX_N (XAUI1_RX_N[ 3 : 0 ]), // <= | |
5585 | .XAUI1_RX_P (XAUI1_RX_P[ 3 : 0 ]), // <= | |
5586 | .esr_mac_tclk_1 (esr_mac_tclk_1), // => | |
5587 | .esr_mac_rclk_1 (esr_mac_rclk_1[ 3 : 0 ]), // => | |
5588 | .esr_mac_rxd0_1 (esr_mac_rxd0_1[ 9 : 0 ]), // => | |
5589 | .esr_mac_rxd1_1 (esr_mac_rxd1_1[ 9 : 0 ]), // => | |
5590 | .esr_mac_rxd2_1 (esr_mac_rxd2_1[ 9 : 0 ]), // => | |
5591 | .esr_mac_rxd3_1 (esr_mac_rxd3_1[ 9 : 0 ]), // => | |
5592 | .mac_esr_tclk_1 (mac_esr_tclk_1[ 3 : 0 ]), // <= | |
5593 | .mac_esr_txd0_1 (mac_esr_txd0_1[ 9 : 0 ]), // <= | |
5594 | .mac_esr_txd1_1 (mac_esr_txd1_1[ 9 : 0 ]), // <= | |
5595 | .mac_esr_txd2_1 (mac_esr_txd2_1[ 9 : 0 ]), // <= | |
5596 | .mac_esr_txd3_1 (mac_esr_txd3_1[ 9 : 0 ]), // <= | |
5597 | .stcicfg_1 (tcu_stcicfg[ 1 : 0 ]), // <= | |
5598 | .stciclk_1 (tcu_stciclk), // <= | |
5599 | .stcid_1 (stcid_1), // <= | |
5600 | .stciq_1 (esr_stciq), // => | |
5601 | .rxbclkin_1 (esr_mac_rclk_1[ 3 : 0 ]), // => | |
5602 | .testclkr_1 (mio_esr_testclkr), // <= | |
5603 | .testclkt_1 (mio_esr_testclkt), // <= | |
5604 | .cfgtx0_1 (cfgtx0_1[ 19 : 0 ]), // <= | |
5605 | .cfgtx1_1 (cfgtx1_1[ 19 : 0 ]), // <= | |
5606 | .cfgtx2_1 (cfgtx2_1[ 19 : 0 ]), // <= | |
5607 | .cfgtx3_1 (cfgtx3_1[ 19 : 0 ]), // <= | |
5608 | .cfgrx0_1 (cfgrx0_1[ 27 : 0 ]), // <= | |
5609 | .cfgrx1_1 (cfgrx1_1[ 27 : 0 ]), // <= | |
5610 | .cfgrx2_1 (cfgrx2_1[ 27 : 0 ]), // <= | |
5611 | .cfgrx3_1 (cfgrx3_1[ 27 : 0 ]), // <= | |
5612 | .cfgpll_1 (cfgpll_1[ 11 : 0 ]), // <= | |
5613 | .testcfg_1 (testcfg_1[ 15 : 0 ]), // <= | |
5614 | .ststx0_1 (ststx0_1[ 3 : 0 ]), // => | |
5615 | .ststx1_1 (ststx1_1[ 3 : 0 ]), // => | |
5616 | .ststx2_1 (ststx2_1[ 3 : 0 ]), // => | |
5617 | .ststx3_1 (ststx3_1[ 3 : 0 ]), // => | |
5618 | .stsrx0_1 (stsrx0_1[ 7 : 0 ]), // => | |
5619 | .stsrx1_1 (stsrx1_1[ 7 : 0 ]), // => | |
5620 | .stsrx2_1 (stsrx2_1[ 7 : 0 ]), // => | |
5621 | .stsrx3_1 (stsrx3_1[ 7 : 0 ]), // => | |
5622 | .stspll_1 (stspll_1[ 3 : 0 ]), // => | |
5623 | .fdo_1 (niu_efu_fdo), // => | |
5624 | .fclk_1 (efu_niu_fclk), // <= | |
5625 | .fclrz_1 (efu_niu_fclrz), // <= | |
5626 | .fdi_1 (fdi_1), // <= | |
5627 | .tcu_sbs_bsinitclk_0 (tcu_sbs_bsinitclk), // <= | |
5628 | .tcu_sbs_bsinitclk_1 (tcu_sbs_bsinitclk), // <= | |
5629 | .tcu_esr_atpgse_0 (tcu_srd_atpgse), // <= | |
5630 | .tcu_esr_atpgse_1 (tcu_srd_atpgse), // <= | |
5631 | .tcu_esr_atpgmode_0 (tcu_srd_atpgmode[ 2 : 0 ]), // <= | |
5632 | .tcu_esr_atpgmode_1 (tcu_srd_atpgmode[ 2 : 0 ]), // <= | |
5633 | .esr_atpgd (esr_atpgd), // <= | |
5634 | .esr_atpgq (esr_atpgq), // => | |
5635 | .VDDT (VDDT_ESR), // <= | |
5636 | .VDDA (VDDA_ESR), // <= | |
5637 | .VDDD (VDDD_ESR), // <= | |
5638 | .VDDR (VDDR_ESR), // <= | |
5639 | .VSSA (VSSA_ESR) // <= | |
5640 | ); | |
5641 | ||
5642 | `endif // NIU_SYSTEMC_T2 | |
5643 | ||
5644 | `endif // OPENSPARC_CMP | |
5645 | ||
5646 | `endif // `ifndef FC_NO_NIU_T2 | |
5647 | ||
5648 | ||
5649 | // NIU END | |
5650 | ||
5651 | ||
5652 | ||
5653 | input PLL_CMP_CLK_P; // Reference clock input, either 133.333, 166.666, or 200 MHz. | |
5654 | input PLL_CMP_CLK_N; // Differential signal. | |
5655 | inout [ 2 : 0 ] DIODE_TOP; | |
5656 | inout [ 2 : 0 ] DIODE_BOT; | |
5657 | input VDD_PLL_CMP_REG; // TBD - mh157021 | |
5658 | input VDD_RNG_HV; // TBD - mh157021 | |
5659 | output VDD_SENSE; | |
5660 | output VSS_SENSE; | |
5661 | output RNG_ANLG_CHAR_OUT; | |
5662 | ||
5663 | input PWRON_RST_L; // Power On Reset | |
5664 | input BUTTON_XIR_L; // Externally Initiated Reset | |
5665 | input PB_RST_L; // Like Niagara J_RST_L | |
5666 | output PEX_RESET_L; // To External PCI Express switch and | |
5667 | // PCI Express Devices | |
5668 | //output FATAL_ERROR; // Fatal Error has ocurred in N2 | |
5669 | output SSI_SYNC_L; // SSI SYNC signal to FPGA PLL | |
5670 | ||
5671 | inout VPP; // High powered programming pin (efu) | |
5672 | ||
5673 | //test | |
5674 | // input [ 30:0] io_scan_in; | |
5675 | // input io_srdes_scan_in; | |
5676 | // output [ 30:0] tcu_pins_scan_out; | |
5677 | // output tcu_pin_srdes_scan_out; | |
5678 | ||
5679 | //input scan_in; | |
5680 | ||
5681 | //jtag and test | |
5682 | input TMS; | |
5683 | input TDI; | |
5684 | input TRST_L; | |
5685 | input TCK; | |
5686 | input TESTMODE; | |
5687 | output TDO; | |
5688 | ||
5689 | input DIVIDER_BYPASS; // Bypasses Clock Tree Dividers | |
5690 | ||
5691 | //debug | |
5692 | inout [ 165 : 0 ] DBG_DQ; // Debug Outputs | |
5693 | // DBG_DQ[113:0] also shares | |
5694 | // function as following pins: | |
5695 | // CMP_CLK_EXT | |
5696 | // IO_CLK_EXT | |
5697 | // IO2X_CLK_EXT | |
5698 | // ACLK | |
5699 | // BCLK | |
5700 | // SCAN_EN | |
5701 | // AC_TESTMODE | |
5702 | // AC_TESTRIG | |
5703 | // SCAN_IN[31:0] | |
5704 | // SCAN_OUT[31:0] | |
5705 | // DMA_DATA[39:0] | |
5706 | // MBIST_DONE | |
5707 | // MBIST_FAIL | |
5708 | ||
5709 | output DBG_CK0; // Debug Output CLK Unit 0 | |
5710 | input TRIGIN; // Stop clock based on external event; | |
5711 | // TRIGIN controls BISI/BIST selection | |
5712 | ||
5713 | output TRIGOUT; // DBG event signal to logic analyzer | |
5714 | ||
5715 | // SSI | |
5716 | ||
5717 | input SSI_MISO; // SSI Master In, Slave Out | |
5718 | input SSI_EXT_INT_L; // SSI External Interrupt | |
5719 | output SSI_SCK; // SSI Clock | |
5720 | output SSI_MOSI; // SSI Master Out, Slave In | |
5721 | ||
5722 | ||
5723 | ||
5724 | ||
5725 | // misc pads | |
5726 | ||
5727 | input [ 1 : 0 ] PMI; // process control monitor input | |
5728 | input VREG_SELBG_L; // Bandgap Select | |
5729 | output [ 1 : 0 ] PLL_CHAR_OUT; // PLL Char Out | |
5730 | input PLL_TESTMODE; // PLL Testmode Pin | |
5731 | input [ 2 : 0 ] PWR_THRTTL_0; // Power Throttle pins grp 0 | |
5732 | input [ 2 : 0 ] PWR_THRTTL_1; // Power Throttle pins grp 1 | |
5733 | output PMO; // process control monitor output | |
5734 | input BURNIN; // Sets Burnin Mode for PCM Modules | |
5735 | ||
5736 | ||
5737 | n2_esd_core_cust esd_core0 ( | |
5738 | .supply_node (VDD_SENSE) | |
5739 | ); | |
5740 | ||
5741 | n2_esd_core_cust esd_core1 ( | |
5742 | .supply_node (VSS_SENSE) | |
5743 | ); | |
5744 | ||
5745 | // leave this instance out of cmp model | |
5746 | `ifdef OPENSPARC_CMP | |
5747 | `else | |
5748 | mio mio( | |
5749 | ||
5750 | // Inputs | |
5751 | .scan_in(db0_scan_out), | |
5752 | .gclk_0( cmp_gclk_c3_mio ), // cmp_gclk_c2_mio_left ), mh157021: n2 eco bug id 110392 | |
5753 | .gclk_1( cmp_gclk_c2_mio_left ), // cmp_gclk_c2_mio_right ), mh157021: n2 eco bug id 110392 | |
5754 | .gclk_2( cmp_gclk_c2_mio_right ), // cmp_gclk_c3_mio ), mh157021: n2 eco bug id 110392 | |
5755 | .gclk_3( cmp_gclk_c1_mio ), // cmp_gclk_c1_mio ), mh157021: n2 eco bug id 110392 | |
5756 | .gl_mio_clk_stop_c3 (gl_mio_clk_stop_c3t), | |
5757 | .gl_mio_clk_stop_c2_left (gl_mio_clk_stop_c2t), | |
5758 | .gl_mio_clk_stop_c2_right (gl_mio_clk_stop_c2t), | |
5759 | .gl_mio_clk_stop_c1 (gl_mio_clk_stop_c1t), | |
5760 | .gl_mio_io2x_sync_en_c3 (gl_io2x_sync_en_c3t0), // (gl_io2x_sync_en_c3t), - for int6.1 | |
5761 | .gl_mio_io2x_sync_en_c2_left (gl_io2x_sync_en_c2t), | |
5762 | .gl_mio_io2x_sync_en_c2_right (gl_io2x_sync_en_c2t), | |
5763 | .gl_mio_io2x_sync_en_c1 (gl_mio_io2x_sync_en_c1t ), | |
5764 | .ccu_io_out( gl_io_out_c3t), | |
5765 | .ro_in(pcmb0_mio_ro_in), | |
5766 | // Outputs | |
5767 | .mio_tcu_tms(mio_tcu_tms), | |
5768 | .mio_tcu_tdi(mio_tcu_tdi), | |
5769 | .mio_tcu_trst_l(mio_tcu_trst_l), | |
5770 | .mio_tcu_tck(mio_tcu_tck), | |
5771 | .mio_tcu_testmode(mio_tcu_testmode), | |
5772 | .mio_psr_testclkt(mio_psr_testclkt), | |
5773 | .mio_psr_testclkr(mio_psr_testclkr), | |
5774 | .mio_esr_testclkt(mio_esr_testclkt), | |
5775 | .mio_esr_testclkr(mio_esr_testclkr), | |
5776 | .mio_spc_pwr_throttle_0(mio_spc_pwr_throttle_0[ 2 : 0 ]), | |
5777 | .mio_spc_pwr_throttle_1(mio_spc_pwr_throttle_1[ 2 : 0 ]), | |
5778 | .sel59(mio_pcmb0_sel59), | |
5779 | .sel60(mio_pcmb1_sel60), | |
5780 | .sel61(mio_pcma_sel61), | |
5781 | .io_burnin(mio_pcm_burnin), | |
5782 | .mio_efu_prgm_en(mio_efu_prgm_en), | |
5783 | `ifndef FC_NO_NIU_T2 | |
5784 | .mio_mac_xaui_mdint1_l(mio_mac_xaui_mdint1_l), | |
5785 | .mio_mac_xaui_mdint0_l(mio_mac_xaui_mdint0_l), | |
5786 | `endif | |
5787 | .scan_out(mio_scan_out), | |
5788 | .cluster_arst_l(cluster_arst_l), | |
5789 | .tcu_div_bypass(tcu_div_bypass), | |
5790 | .tcu_atpg_mode(tcu_atpg_mode), | |
5791 | .ccu_mio_serdes_dtm(ccu_mio_serdes_dtm), | |
5792 | `ifndef FC_NO_NIU_T2 | |
5793 | .XAUI_MDINT0_L(XAUI_MDINT0_L), | |
5794 | .XAUI_MDINT1_L(XAUI_MDINT1_L), | |
5795 | .XAUI0_ACT_LED(XAUI0_ACT_LED), | |
5796 | .XAUI0_LINK_LED(XAUI0_LINK_LED), | |
5797 | .XAUI1_ACT_LED(XAUI1_ACT_LED), | |
5798 | .XAUI1_LINK_LED(XAUI1_LINK_LED), | |
5799 | .XAUI_MDC(XAUI_MDC), | |
5800 | .XAUI_MDIO(XAUI_MDIO), | |
5801 | .xaui_act_led_0(xaui_act_led_0), | |
5802 | .xaui_link_led_0(xaui_link_led_0), | |
5803 | .xaui_act_led_1(xaui_act_led_1), | |
5804 | .xaui_link_led_1(xaui_link_led_1), | |
5805 | .mdc(mdc), | |
5806 | .mdoe(mdoe), | |
5807 | .mdi(mdi), | |
5808 | `endif | |
5809 | .TCK(TCK), | |
5810 | .TDI(TDI), | |
5811 | .TDO(TDO), | |
5812 | .TMS(TMS), | |
5813 | .TRST_L(TRST_L), | |
5814 | .TESTMODE(TESTMODE), | |
5815 | .STCIQ(STCIQ), | |
5816 | .STCID(STCID), | |
5817 | .STCICFG(STCICFG[1:0]), | |
5818 | .STCICLK(STCICLK), | |
5819 | .TESTCLKT(TESTCLKT), | |
5820 | .TESTCLKR(TESTCLKR), | |
5821 | .VDDO_PCM(VDDO_PCM), | |
5822 | .DIVIDER_BYPASS(DIVIDER_BYPASS), | |
5823 | .PLL_CMP_BYPASS(PLL_CMP_BYPASS), | |
5824 | .tcu_mio_tdo(tcu_mio_tdo), | |
5825 | .tcu_mio_tdo_en(tcu_mio_tdo_en), | |
5826 | .tcu_mio_stciq(tcu_mio_stciq), | |
5827 | .mio_tcu_stcid(mio_tcu_stcid), | |
5828 | .mio_tcu_stcicfg(mio_tcu_stcicfg[1:0]), | |
5829 | .mio_tcu_stciclk(mio_tcu_stciclk), | |
5830 | .mio_fsr_testclkt(mio_fsr_testclkt[7:0]), | |
5831 | .mio_fsr_testclkr(mio_fsr_testclkr[7:0]), | |
5832 | .mio_tcu_divider_bypass(mio_tcu_divider_bypass), | |
5833 | .mio_tcu_pll_cmp_bypass(mio_tcu_pll_cmp_bypass), | |
5834 | .DBG_DQ(DBG_DQ[165:0]), | |
5835 | .DBG_CK0(DBG_CK0), | |
5836 | .TRIGIN(TRIGIN), | |
5837 | .TRIGOUT(TRIGOUT), | |
5838 | .mio_tcu_scan_in31(mio_tcu_scan_in31), | |
5839 | .tcu_mio_scan_out31(tcu_mio_scan_out31), | |
5840 | .niu_mio_debug_data(niu_mio_debug_data[31:0]), | |
5841 | .niu_mio_debug_clock(niu_mio_debug_clock[1:0]), | |
5842 | .dbg0_mio_debug_bus_a(dbg0_mio_debug_bus_a[7:0]), | |
5843 | .dbg0_mio_debug_bus_b(dbg0_mio_debug_bus_b[7:0]), | |
5844 | .peu_mio_debug_bus_a(peu_mio_debug_bus_a[7:0]), | |
5845 | .peu_mio_debug_bus_b(peu_mio_debug_bus_b[7:0]), | |
5846 | .peu_mio_pipe_txdata(peu_mio_pipe_txdata[63:0]), | |
5847 | .peu_mio_pipe_txdatak(peu_mio_pipe_txdatak[7:0]), | |
5848 | .peu_mio_debug_clk(peu_mio_debug_clk), | |
5849 | .mio_pll_testmode(mio_pll_testmode), | |
5850 | .mio_ccu_pll_char_in(mio_ccu_pll_char_in), | |
5851 | .mio_ccu_pll_div2(mio_ccu_pll_div2[5:0]), | |
5852 | .mio_ccu_pll_trst_l(mio_ccu_pll_trst_l), | |
5853 | .mio_ccu_pll_clamp_fltr(mio_ccu_pll_clamp_fltr), | |
5854 | .mio_ccu_pll_div4(mio_ccu_pll_div4[6:0]), | |
5855 | .mio_ext_dr_clk(mio_ext_dr_clk), | |
5856 | .mio_ext_cmp_clk(mio_ext_cmp_clk), | |
5857 | .ccu_mio_pll_char_out(ccu_mio_pll_char_out[1:0]), | |
5858 | .mio_ccu_vreg_selbg_l(mio_ccu_vreg_selbg_l), | |
5859 | .mio_tcu_io_ac_testmode(mio_tcu_io_ac_testmode), | |
5860 | .mio_tcu_io_ac_testtrig(mio_tcu_io_ac_testtrig), | |
5861 | .mio_tcu_io_aclk(mio_tcu_io_aclk), | |
5862 | .mio_tcu_io_bclk(mio_tcu_io_bclk), | |
5863 | .mio_tcu_io_scan_in(mio_tcu_io_scan_in[30:0]), | |
5864 | .mio_tcu_peu_clk_ext(mio_tcu_peu_clk_ext), | |
5865 | .mio_tcu_niu_clk_ext(mio_tcu_niu_clk_ext[5:0]), | |
5866 | .mio_tcu_io_scan_en(mio_tcu_io_scan_en), | |
5867 | .tcu_mio_pins_scan_out(tcu_mio_pins_scan_out[30:0]), | |
5868 | .tcu_mio_dmo_data(tcu_mio_dmo_data[39:0]), | |
5869 | .tcu_mio_mbist_done(tcu_mio_mbist_done), | |
5870 | .tcu_mio_mbist_fail(tcu_mio_mbist_fail), | |
5871 | .tcu_mio_dmo_sync(tcu_mio_dmo_sync), | |
5872 | .dbg1_mio_dbg_dq(dbg1_mio_dbg_dq[165:0]), | |
5873 | .mio_tcu_trigin(mio_tcu_trigin), | |
5874 | .tcu_mio_trigout(tcu_mio_trigout), | |
5875 | .dbg1_mio_drv_en_op_only(dbg1_mio_drv_en_op_only), | |
5876 | .dbg1_mio_drv_en_muxtest_inp(dbg1_mio_drv_en_muxtest_inp), | |
5877 | .dbg1_mio_drv_en_muxtestpll_inp(dbg1_mio_drv_en_muxtestpll_inp), | |
5878 | .dbg1_mio_drv_en_muxtest_op(dbg1_mio_drv_en_muxtest_op), | |
5879 | .dbg1_mio_drv_en_muxbist_op(dbg1_mio_drv_en_muxbist_op), | |
5880 | .PMI(PMI[1:0]), | |
5881 | .PMO(PMO), | |
5882 | .PGRM_EN(PGRM_EN), | |
5883 | .BURNIN(BURNIN), | |
5884 | .PEX_RESET_L(PEX_RESET_L), | |
5885 | .PB_RST_L(PB_RST_L), | |
5886 | .BUTTON_XIR_L(BUTTON_XIR_L), | |
5887 | .PWRON_RST_L(PWRON_RST_L), | |
5888 | .SSI_MOSI(SSI_MOSI), | |
5889 | .SSI_MISO(SSI_MISO), | |
5890 | .SSI_SCK(SSI_SCK), | |
5891 | .SSI_EXT_INT_L(SSI_EXT_INT_L), | |
5892 | .SSI_SYNC_L(SSI_SYNC_L), | |
5893 | .VREG_SELBG_L(VREG_SELBG_L), | |
5894 | .PLL_CHAR_OUT(PLL_CHAR_OUT[1:0]), | |
5895 | .PLL_TESTMODE(PLL_TESTMODE), | |
5896 | .PWR_THRTTL_0(PWR_THRTTL_0[2:0]), | |
5897 | .PWR_THRTTL_1(PWR_THRTTL_1[2:0]), | |
5898 | .rst_mio_pex_reset_l(rst_mio_pex_reset_l), | |
5899 | .rst_mio_rst_state(rst_mio_rst_state[5:0]), | |
5900 | .mio_rst_pb_rst_l(mio_rst_pb_rst_l), | |
5901 | .mio_rst_button_xir_l(mio_rst_button_xir_l), | |
5902 | .mio_rst_pwron_rst_l(mio_rst_pwron_rst_l), | |
5903 | .ncu_mio_ssi_mosi(ncu_mio_ssi_mosi), | |
5904 | .mio_ncu_ssi_miso(mio_ncu_ssi_miso), | |
5905 | .ncu_mio_ssi_sck(ncu_mio_ssi_sck), | |
5906 | .mio_ncu_ext_int_l(mio_ncu_ext_int_l), | |
5907 | .rst_mio_ssi_sync_l(rst_mio_ssi_sync_l), | |
5908 | .tcu_mio_jtag_membist_mode(tcu_mio_jtag_membist_mode), | |
5909 | .dbg1_mio_sel_niu_debug_mode(dbg1_mio_sel_niu_debug_mode), | |
5910 | .dbg1_mio_sel_pcix_debug_mode(dbg1_mio_sel_pcix_debug_mode), | |
5911 | .dbg1_mio_sel_soc_obs_mode(dbg1_mio_sel_soc_obs_mode), | |
5912 | .dbg1_mio_drv_imped(dbg1_mio_drv_imped[1:0]), | |
5913 | .tcu_aclk(tcu_aclk), | |
5914 | .tcu_bclk(tcu_bclk), | |
5915 | .tcu_scan_en(tcu_scan_en), | |
5916 | .tcu_pce_ov(tcu_pce_ov), | |
5917 | .tcu_mio_bs_scan_in(tcu_mio_bs_scan_in), | |
5918 | .tcu_mio_bs_highz_l(tcu_mio_bs_highz_l), | |
5919 | .mio_tcu_bs_scan_out(mio_tcu_bs_scan_out), | |
5920 | .tcu_mio_bs_scan_en(tcu_mio_bs_scan_en), | |
5921 | .tcu_mio_bs_clk(tcu_mio_bs_clk), | |
5922 | .tcu_mio_bs_aclk(tcu_mio_bs_aclk), | |
5923 | .tcu_mio_bs_bclk(tcu_mio_bs_bclk), | |
5924 | .tcu_mio_bs_uclk(tcu_mio_bs_uclk), | |
5925 | .tcu_mio_bs_mode_ctl(tcu_mio_bs_mode_ctl) | |
5926 | ); | |
5927 | `endif // OPENSPARC_CMP | |
5928 | ||
5929 | // leave this instance out of cmp model | |
5930 | `ifdef OPENSPARC_CMP | |
5931 | `else | |
5932 | db0 dbg0 ( | |
5933 | ||
5934 | //.rst_por_(rst_por_ ), // Remove. March 8 '05. | |
5935 | //.rst_wmr_(rst_wmr_ ), // Remove. March 8 '05. | |
5936 | .scan_in(db1_scan_out), | |
5937 | .scan_out(db0_scan_out), | |
5938 | .dmu_dbg0_debug_bus_a (dmu_mio_debug_bus_a[ 7 : 0 ]), | |
5939 | .dmu_dbg0_debug_bus_b (dmu_mio_debug_bus_b[ 7 : 0 ]), | |
5940 | .gclk( cmp_gclk_c3_db0 ), // cmp_gclk_c0_r[0]), // temporary | |
5941 | .tcu_clk_stop ( gl_db0_clk_stop ), // staged clk_stop | |
5942 | .ccu_io_out ( gl_io_out_c3b0 ), // ECO c3b -> c3b0 - mh157021 | |
5943 | .cmp_io2x_sync_en( gl_io2x_sync_en_c3t ), // ( gl_io2x_sync_en_c3t0 ), for int6.1 | |
5944 | .io_cmp_sync_en( gl_io_cmp_sync_en_c3b ), | |
5945 | .tcu_pce_ov(tcu_pce_ov), | |
5946 | .tcu_aclk(tcu_aclk), | |
5947 | .tcu_bclk(tcu_bclk), | |
5948 | .tcu_scan_en(tcu_scan_en), | |
5949 | .tcu_div_bypass(tcu_div_bypass), | |
5950 | .dmu_ncu_wrack_vld(dmu_ncu_wrack_vld), | |
5951 | .dmu_ncu_wrack_tag(dmu_ncu_wrack_tag[ 3 : 0 ]), | |
5952 | .dmu_ncu_data(dmu_ncu_data[ 31 : 0 ]), | |
5953 | .dmu_ncu_vld(dmu_ncu_vld), | |
5954 | .dmu_ncu_stall(dmu_ncu_stall), | |
5955 | .dmu_sii_hdr_vld(dmu_sii_hdr_vld), | |
5956 | .dmu_sii_reqbypass(dmu_sii_reqbypass), | |
5957 | .dmu_sii_datareq(dmu_sii_datareq), | |
5958 | .dmu_sii_datareq16(dmu_sii_datareq16), | |
5959 | .dmu_sii_data(dmu_sii_data[ 127 : 0 ]), | |
5960 | .dmu_sii_be(dmu_sii_be[ 15 : 0 ]), | |
5961 | .niu_ncu_vld(niu_ncu_vld), | |
5962 | .niu_ncu_data(niu_ncu_data[ 31 : 0 ]), | |
5963 | .niu_ncu_stall(niu_ncu_stall), | |
5964 | .niu_sii_hdr_vld(niu_sii_hdr_vld), | |
5965 | .niu_sii_reqbypass(niu_sii_reqbypass), | |
5966 | .niu_sii_datareq(niu_sii_datareq), | |
5967 | .niu_sii_data(niu_sii_data[ 127 : 0 ]), | |
5968 | .niu_sio_dq(niu_sio_dq), | |
5969 | .l2t0_dbg0_sii_iq_dequeue(l2t0_dbg0_sii_iq_dequeue), | |
5970 | .l2t2_dbg0_sii_iq_dequeue(l2t2_dbg0_sii_iq_dequeue), | |
5971 | .l2t0_dbg0_sii_wib_dequeue(l2t0_dbg0_sii_wib_dequeue), | |
5972 | .l2t2_dbg0_sii_wib_dequeue(l2t2_dbg0_sii_wib_dequeue), | |
5973 | .l2t0_dbg0_err_event(l2t0_dbg0_err_event), | |
5974 | .l2t2_dbg0_err_event(l2t2_dbg0_err_event), | |
5975 | .l2t0_dbg0_pa_match(l2t0_dbg0_pa_match), | |
5976 | .l2t2_dbg0_pa_match(l2t2_dbg0_pa_match), | |
5977 | .l2t0_dbg0_xbar_vcid(l2t0_dbg0_xbar_vcid[ 5 : 0 ]), | |
5978 | .l2t2_dbg0_xbar_vcid(l2t2_dbg0_xbar_vcid[ 5 : 0 ]), | |
5979 | .l2b0_dbg0_sio_ctag_vld(l2b0_dbg0_sio_ctag_vld), | |
5980 | .l2b1_dbg0_sio_ctag_vld(l2b1_dbg0_sio_ctag_vld), | |
5981 | .l2b2_dbg0_sio_ctag_vld(l2b2_dbg0_sio_ctag_vld), | |
5982 | .l2b3_dbg0_sio_ctag_vld(l2b3_dbg0_sio_ctag_vld), | |
5983 | .l2b0_dbg0_sio_ack_type(l2b0_dbg0_sio_ack_type), | |
5984 | .l2b1_dbg0_sio_ack_type(l2b1_dbg0_sio_ack_type), | |
5985 | .l2b2_dbg0_sio_ack_type(l2b2_dbg0_sio_ack_type), | |
5986 | .l2b3_dbg0_sio_ack_type(l2b3_dbg0_sio_ack_type), | |
5987 | .l2b0_dbg0_sio_ack_dest(l2b0_dbg0_sio_ack_dest), | |
5988 | .l2b1_dbg0_sio_ack_dest(l2b1_dbg0_sio_ack_dest), | |
5989 | .l2b2_dbg0_sio_ack_dest(l2b2_dbg0_sio_ack_dest), | |
5990 | .l2b3_dbg0_sio_ack_dest(l2b3_dbg0_sio_ack_dest), | |
5991 | .spc0_dbg0_instr_cmt_grp0(spc0_dbg0_instr_cmt_grp0[ 1 : 0 ]), | |
5992 | .spc0_dbg0_instr_cmt_grp1(spc0_dbg0_instr_cmt_grp1[ 1 : 0 ]), | |
5993 | .spc2_dbg0_instr_cmt_grp0(spc2_dbg0_instr_cmt_grp0[ 1 : 0 ]), | |
5994 | .spc2_dbg0_instr_cmt_grp1(spc2_dbg0_instr_cmt_grp1[ 1 : 0 ]), | |
5995 | .dbg0_dbg1_debug_data(dbg0_dbg1_debug_data[ 165 : 0 ]), | |
5996 | .dbg0_dbg1_l2t0_sii_iq_dequeue(dbg0_dbg1_l2t0_sii_iq_dequeue), | |
5997 | .dbg0_dbg1_l2t2_sii_iq_dequeue(dbg0_dbg1_l2t2_sii_iq_dequeue), | |
5998 | .dbg0_dbg1_l2t0_sii_wib_dequeue(dbg0_dbg1_l2t0_sii_wib_dequeue), | |
5999 | .dbg0_dbg1_l2t2_sii_wib_dequeue(dbg0_dbg1_l2t2_sii_wib_dequeue), | |
6000 | .dbg0_dbg1_l2t0_err_event(dbg0_dbg1_l2t0_err_event), | |
6001 | .dbg0_dbg1_l2t2_err_event(dbg0_dbg1_l2t2_err_event), | |
6002 | .dbg0_dbg1_l2t0_pa_match(dbg0_dbg1_l2t0_pa_match), | |
6003 | .dbg0_dbg1_l2t2_pa_match(dbg0_dbg1_l2t2_pa_match), | |
6004 | .dbg0_dbg1_l2t0_xbar_vcid(dbg0_dbg1_l2t0_xbar_vcid[ 5 : 0 ]), | |
6005 | .dbg0_dbg1_l2t2_xbar_vcid(dbg0_dbg1_l2t2_xbar_vcid[ 5 : 0 ]), | |
6006 | .dbg0_dbg1_l2b0_sio_ctag_vld(dbg0_dbg1_l2b0_sio_ctag_vld), | |
6007 | .dbg0_dbg1_l2b1_sio_ctag_vld(dbg0_dbg1_l2b1_sio_ctag_vld), | |
6008 | .dbg0_dbg1_l2b2_sio_ctag_vld(dbg0_dbg1_l2b2_sio_ctag_vld), | |
6009 | .dbg0_dbg1_l2b3_sio_ctag_vld(dbg0_dbg1_l2b3_sio_ctag_vld), | |
6010 | .dbg0_dbg1_l2b0_sio_ack_type(dbg0_dbg1_l2b0_sio_ack_type), | |
6011 | .dbg0_dbg1_l2b1_sio_ack_type(dbg0_dbg1_l2b1_sio_ack_type), | |
6012 | .dbg0_dbg1_l2b2_sio_ack_type(dbg0_dbg1_l2b2_sio_ack_type), | |
6013 | .dbg0_dbg1_l2b3_sio_ack_type(dbg0_dbg1_l2b3_sio_ack_type), | |
6014 | .dbg0_dbg1_l2b0_sio_ack_dest(dbg0_dbg1_l2b0_sio_ack_dest), | |
6015 | .dbg0_dbg1_l2b1_sio_ack_dest(dbg0_dbg1_l2b1_sio_ack_dest), | |
6016 | .dbg0_dbg1_l2b2_sio_ack_dest(dbg0_dbg1_l2b2_sio_ack_dest), | |
6017 | .dbg0_dbg1_l2b3_sio_ack_dest(dbg0_dbg1_l2b3_sio_ack_dest), | |
6018 | .dbg0_dbg1_spc0_instr_cmt_grp0(dbg0_dbg1_spc0_instr_cmt_grp0[ 1 : 0 ]), | |
6019 | .dbg0_dbg1_spc0_instr_cmt_grp1(dbg0_dbg1_spc0_instr_cmt_grp1[ 1 : 0 ]), | |
6020 | .dbg0_dbg1_spc2_instr_cmt_grp0(dbg0_dbg1_spc2_instr_cmt_grp0[ 1 : 0 ]), | |
6021 | .dbg0_dbg1_spc2_instr_cmt_grp1(dbg0_dbg1_spc2_instr_cmt_grp1[ 1 : 0 ]), | |
6022 | .dbg0_mio_debug_bus_a(dbg0_mio_debug_bus_a[ 7 : 0 ]), | |
6023 | .dbg0_mio_debug_bus_b(dbg0_mio_debug_bus_b[ 7 : 0 ]), | |
6024 | .tcu_atpg_mode(tcu_atpg_mode), | |
6025 | .cluster_arst_l(cluster_arst_l) // ccu_io_cmp_sync_en), | |
6026 | ); | |
6027 | `endif // OPENSPARC_CMP | |
6028 | ||
6029 | // leave this instance out of cmp model | |
6030 | `ifdef OPENSPARC_CMP | |
6031 | `else | |
6032 | db1 dbg1 ( | |
6033 | ||
6034 | //.rst_por_(rst_por_ ), // Remove. March 8 '05. | |
6035 | //.rst_wmr_(rst_wmr_ ), // Remove. March 8 '05. | |
6036 | .scan_in(tcu_soc6_scan_out ), | |
6037 | .scan_out(db1_scan_out), | |
6038 | .dmu_dbg1_err_event(dmu_dbg_err_event), | |
6039 | .gclk( cmp_gclk_c1_db1 ), // cmp_gclk_c0_r[0]), // temporary | |
6040 | .tcu_clk_stop ( gl_db1_clk_stop ), // staged clk_stop | |
6041 | .ccu_io_out ( gl_io_out_c1m ), // staged div phase | |
6042 | .cmp_io2x_sync_en( gl_io2x_sync_en_c1m ), | |
6043 | .io_cmp_sync_en( gl_io_cmp_sync_en_c1m ), | |
6044 | .cmp_io_sync_en( gl_cmp_io_sync_en_c1m ), | |
6045 | .mio_dbg1_testmode(mio_tcu_testmode), | |
6046 | .tcu_pce_ov(tcu_pce_ov), | |
6047 | .tcu_aclk(tcu_aclk), | |
6048 | .tcu_bclk(tcu_bclk), | |
6049 | .tcu_scan_en(tcu_scan_en), | |
6050 | .rst_wmr_protect(rst_wmr_protect), | |
6051 | .tcu_div_bypass(tcu_div_bypass), | |
6052 | .ccu_dbg1_serdes_dtm(ccu_dbg1_serdes_dtm), | |
6053 | .l2t1_dbg1_sii_iq_dequeue(l2t1_dbg1_sii_iq_dequeue), | |
6054 | .l2t3_dbg1_sii_iq_dequeue(l2t3_dbg1_sii_iq_dequeue), | |
6055 | .l2t4_dbg1_sii_iq_dequeue(l2t4_dbg1_sii_iq_dequeue), | |
6056 | .l2t5_dbg1_sii_iq_dequeue(l2t5_dbg1_sii_iq_dequeue), | |
6057 | .l2t6_dbg1_sii_iq_dequeue(l2t6_dbg1_sii_iq_dequeue), | |
6058 | .l2t7_dbg1_sii_iq_dequeue(l2t7_dbg1_sii_iq_dequeue), | |
6059 | .l2t1_dbg1_sii_wib_dequeue(l2t1_dbg1_sii_wib_dequeue), | |
6060 | .l2t3_dbg1_sii_wib_dequeue(l2t3_dbg1_sii_wib_dequeue), | |
6061 | .l2t4_dbg1_sii_wib_dequeue(l2t4_dbg1_sii_wib_dequeue), | |
6062 | .l2t5_dbg1_sii_wib_dequeue(l2t5_dbg1_sii_wib_dequeue), | |
6063 | .l2t6_dbg1_sii_wib_dequeue(l2t6_dbg1_sii_wib_dequeue), | |
6064 | .l2t7_dbg1_sii_wib_dequeue(l2t7_dbg1_sii_wib_dequeue), | |
6065 | .l2t1_dbg1_err_event(l2t1_dbg1_err_event), | |
6066 | .l2t3_dbg1_err_event(l2t3_dbg1_err_event), | |
6067 | .l2t4_dbg1_err_event(l2t4_dbg1_err_event), | |
6068 | .l2t6_dbg1_err_event(l2t6_dbg1_err_event), | |
6069 | .l2t7_dbg1_err_event(l2t7_dbg1_err_event), | |
6070 | .l2t1_dbg1_pa_match(l2t1_dbg1_pa_match), | |
6071 | .l2t3_dbg1_pa_match(l2t3_dbg1_pa_match), | |
6072 | .l2t4_dbg1_pa_match(l2t4_dbg1_pa_match), | |
6073 | .l2t5_dbg1_pa_match(l2t5_dbg1_pa_match), | |
6074 | .l2t6_dbg1_pa_match(l2t6_dbg1_pa_match), | |
6075 | .l2t7_dbg1_pa_match(l2t7_dbg1_pa_match), | |
6076 | .l2t1_dbg1_xbar_vcid(l2t1_dbg1_xbar_vcid[ 5 : 0 ]), | |
6077 | .l2t3_dbg1_xbar_vcid(l2t3_dbg1_xbar_vcid[ 5 : 0 ]), | |
6078 | .l2t4_dbg1_xbar_vcid(l2t4_dbg1_xbar_vcid[ 5 : 0 ]), | |
6079 | .l2t5_dbg1_xbar_vcid(l2t5_dbg1_xbar_vcid[ 5 : 0 ]), | |
6080 | .l2t6_dbg1_xbar_vcid(l2t6_dbg1_xbar_vcid[ 5 : 0 ]), | |
6081 | .l2t7_dbg1_xbar_vcid(l2t7_dbg1_xbar_vcid[ 5 : 0 ]), | |
6082 | .l2b4_dbg1_sio_ctag_vld(l2b4_dbg1_sio_ctag_vld), | |
6083 | .l2b5_dbg1_sio_ctag_vld(l2b5_dbg1_sio_ctag_vld), | |
6084 | .l2b6_dbg1_sio_ctag_vld(l2b6_dbg1_sio_ctag_vld), | |
6085 | .l2b7_dbg1_sio_ctag_vld(l2b7_dbg1_sio_ctag_vld), | |
6086 | .l2b4_dbg1_sio_ack_type(l2b4_dbg1_sio_ack_type), | |
6087 | .l2b5_dbg1_sio_ack_type(l2b5_dbg1_sio_ack_type), | |
6088 | .l2b6_dbg1_sio_ack_type(l2b6_dbg1_sio_ack_type), | |
6089 | .l2b7_dbg1_sio_ack_type(l2b7_dbg1_sio_ack_type), | |
6090 | .l2b4_dbg1_sio_ack_dest(l2b4_dbg1_sio_ack_dest), | |
6091 | .l2b5_dbg1_sio_ack_dest(l2b5_dbg1_sio_ack_dest), | |
6092 | .l2b6_dbg1_sio_ack_dest(l2b6_dbg1_sio_ack_dest), | |
6093 | .l2b7_dbg1_sio_ack_dest(l2b7_dbg1_sio_ack_dest), | |
6094 | .spc1_dbg1_instr_cmt_grp0(spc1_dbg1_instr_cmt_grp0[ 1 : 0 ]), | |
6095 | .spc1_dbg1_instr_cmt_grp1(spc1_dbg1_instr_cmt_grp1[ 1 : 0 ]), | |
6096 | .spc3_dbg1_instr_cmt_grp0(spc3_dbg1_instr_cmt_grp0[ 1 : 0 ]), | |
6097 | .spc3_dbg1_instr_cmt_grp1(spc3_dbg1_instr_cmt_grp1[ 1 : 0 ]), | |
6098 | .spc4_dbg1_instr_cmt_grp0(spc4_dbg1_instr_cmt_grp0[ 1 : 0 ]), | |
6099 | .spc4_dbg1_instr_cmt_grp1(spc4_dbg1_instr_cmt_grp1[ 1 : 0 ]), | |
6100 | .spc5_dbg1_instr_cmt_grp0(spc5_dbg1_instr_cmt_grp0[ 1 : 0 ]), | |
6101 | .spc5_dbg1_instr_cmt_grp1(spc5_dbg1_instr_cmt_grp1[ 1 : 0 ]), | |
6102 | .spc6_dbg1_instr_cmt_grp0(spc6_dbg1_instr_cmt_grp0[ 1 : 0 ]), | |
6103 | .spc6_dbg1_instr_cmt_grp1(spc6_dbg1_instr_cmt_grp1[ 1 : 0 ]), | |
6104 | .spc7_dbg1_instr_cmt_grp0(spc7_dbg1_instr_cmt_grp0[ 1 : 0 ]), | |
6105 | .spc7_dbg1_instr_cmt_grp1(spc7_dbg1_instr_cmt_grp1[ 1 : 0 ]), | |
6106 | .mcu0_dbg1_crc21(mcu0_dbg1_crc21), | |
6107 | .mcu0_dbg1_rd_req_in_0(mcu0_dbg1_rd_req_in_0[ 3 : 0 ]), | |
6108 | .mcu0_dbg1_rd_req_in_1(mcu0_dbg1_rd_req_in_1[ 3 : 0 ]), | |
6109 | .mcu0_dbg1_rd_req_out(mcu0_dbg1_rd_req_out[ 4 : 0 ]), | |
6110 | .mcu0_dbg1_wr_req_in_0(mcu0_dbg1_wr_req_in_0), | |
6111 | .mcu0_dbg1_wr_req_in_1(mcu0_dbg1_wr_req_in_1), | |
6112 | .mcu0_dbg1_wr_req_out(mcu0_dbg1_wr_req_out[ 1 : 0 ]), | |
6113 | .mcu0_dbg1_mecc_err(mcu0_dbg1_mecc_err), | |
6114 | .mcu0_dbg1_secc_err(mcu0_dbg1_secc_err), | |
6115 | .mcu0_dbg1_fbd_err(mcu0_dbg1_fbd_err), | |
6116 | .mcu0_dbg1_err_mode(mcu0_dbg1_err_mode), | |
6117 | .mcu0_dbg1_err_event(mcu0_dbg1_err_event), | |
6118 | .mcu1_dbg1_crc21(mcu1_dbg1_crc21), | |
6119 | .mcu1_dbg1_rd_req_in_0(mcu1_dbg1_rd_req_in_0[ 3 : 0 ]), | |
6120 | .mcu1_dbg1_rd_req_in_1(mcu1_dbg1_rd_req_in_1[ 3 : 0 ]), | |
6121 | .mcu1_dbg1_rd_req_out(mcu1_dbg1_rd_req_out[ 4 : 0 ]), | |
6122 | .mcu1_dbg1_wr_req_in_0(mcu1_dbg1_wr_req_in_0), | |
6123 | .mcu1_dbg1_wr_req_in_1(mcu1_dbg1_wr_req_in_1), | |
6124 | .mcu1_dbg1_wr_req_out(mcu1_dbg1_wr_req_out[ 1 : 0 ]), | |
6125 | .mcu1_dbg1_mecc_err(mcu1_dbg1_mecc_err), | |
6126 | .mcu1_dbg1_secc_err(mcu1_dbg1_secc_err), | |
6127 | .mcu1_dbg1_fbd_err(mcu1_dbg1_fbd_err), | |
6128 | .mcu1_dbg1_err_mode(mcu1_dbg1_err_mode), | |
6129 | .mcu1_dbg1_err_event(mcu1_dbg1_err_event), | |
6130 | .mcu2_dbg1_crc21(mcu2_dbg1_crc21), | |
6131 | .mcu2_dbg1_rd_req_in_0(mcu2_dbg1_rd_req_in_0[ 3 : 0 ]), | |
6132 | .mcu2_dbg1_rd_req_in_1(mcu2_dbg1_rd_req_in_1[ 3 : 0 ]), | |
6133 | .mcu2_dbg1_rd_req_out(mcu2_dbg1_rd_req_out[ 4 : 0 ]), | |
6134 | .mcu2_dbg1_wr_req_in_0(mcu2_dbg1_wr_req_in_0), | |
6135 | .mcu2_dbg1_wr_req_in_1(mcu2_dbg1_wr_req_in_1), | |
6136 | .mcu2_dbg1_wr_req_out(mcu2_dbg1_wr_req_out[ 1 : 0 ]), | |
6137 | .mcu2_dbg1_mecc_err(mcu2_dbg1_mecc_err), | |
6138 | .mcu2_dbg1_secc_err(mcu2_dbg1_secc_err), | |
6139 | .mcu2_dbg1_fbd_err(mcu2_dbg1_fbd_err), | |
6140 | .mcu2_dbg1_err_mode(mcu2_dbg1_err_mode), | |
6141 | .mcu2_dbg1_err_event(mcu2_dbg1_err_event), | |
6142 | .mcu3_dbg1_crc21(mcu3_dbg1_crc21), | |
6143 | .mcu3_dbg1_rd_req_in_0(mcu3_dbg1_rd_req_in_0[ 3 : 0 ]), | |
6144 | .mcu3_dbg1_rd_req_in_1(mcu3_dbg1_rd_req_in_1[ 3 : 0 ]), | |
6145 | .mcu3_dbg1_rd_req_out(mcu3_dbg1_rd_req_out[ 4 : 0 ]), | |
6146 | .mcu3_dbg1_wr_req_in_0(mcu3_dbg1_wr_req_in_0), | |
6147 | .mcu3_dbg1_wr_req_in_1(mcu3_dbg1_wr_req_in_1), | |
6148 | .mcu3_dbg1_wr_req_out(mcu3_dbg1_wr_req_out[ 1 : 0 ]), | |
6149 | .mcu3_dbg1_mecc_err(mcu3_dbg1_mecc_err), | |
6150 | .mcu3_dbg1_secc_err(mcu3_dbg1_secc_err), | |
6151 | .mcu3_dbg1_fbd_err(mcu3_dbg1_fbd_err), | |
6152 | .mcu3_dbg1_err_mode(mcu3_dbg1_err_mode), | |
6153 | .mcu3_dbg1_err_event(mcu3_dbg1_err_event), | |
6154 | .dbg1_niu_stall(dbg1_niu_stall), | |
6155 | .niu_dbg1_stall_ack(niu_dbg1_stall_ack), | |
6156 | .dbg1_niu_resume(dbg1_niu_resume), | |
6157 | .dbg1_dmu_stall(dbg1_dmu_stall), | |
6158 | .dmu_dbg1_stall_ack(dmu_dbg1_stall_ack), | |
6159 | .dbg1_dmu_resume(dbg1_dmu_resume), | |
6160 | .sii_dbg1_l2t0_req(sii_dbg1_l2t0_req_ccxrff[ 1 : 0 ]), | |
6161 | .sii_dbg1_l2t1_req(sii_dbg1_l2t1_req_ccxrff[ 1 : 0 ]), | |
6162 | .sii_dbg1_l2t2_req(sii_dbg1_l2t2_req_ccxrff[ 1 : 0 ]), | |
6163 | .sii_dbg1_l2t3_req(sii_dbg1_l2t3_req_ccxrff[ 1 : 0 ]), | |
6164 | .sii_dbg1_l2t4_req(sii_dbg1_l2t4_req_ccxrff[ 1 : 0 ]), | |
6165 | .sii_dbg1_l2t5_req(sii_dbg1_l2t5_req_ccxrff[ 1 : 0 ]), | |
6166 | .sii_dbg1_l2t6_req(sii_dbg1_l2t6_req_ccxrff[ 1 : 0 ]), | |
6167 | .sii_dbg1_l2t7_req(sii_dbg1_l2t7_req_ccxrff[ 1 : 0 ]), | |
6168 | .ncu_dbg1_error_event(ncu_dbg1_error_event), | |
6169 | .ncu_dbg1_stall(ncu_dbg1_stall), | |
6170 | .ncu_dbg1_vld(ncu_dbg1_vld), | |
6171 | .ncu_dbg1_data(ncu_dbg1_data[ 3 : 0 ]), | |
6172 | .dbg1_ncu_stall(dbg1_ncu_stall), | |
6173 | .dbg1_ncu_vld(dbg1_ncu_vld), | |
6174 | .dbg1_ncu_data(dbg1_ncu_data[ 3 : 0 ]), | |
6175 | .dbg1_tcu_soc_hard_stop(dbg1_tcu_soc_hard_stop), | |
6176 | .dbg1_tcu_soc_asrt_trigout(dbg1_tcu_soc_asrt_trigout), | |
6177 | .tcu_mio_jtag_membist_mode(tcu_mio_jtag_membist_mode), | |
6178 | .dbg1_niu_dbg_sel(dbg1_niu_dbg_sel[ 4 : 0 ]), | |
6179 | .mio_pll_testmode(mio_pll_testmode), | |
6180 | .dbg1_mio_dbg_dq(dbg1_mio_dbg_dq[ 165 : 0 ]), | |
6181 | .dbg1_mio_drv_en_op_only(dbg1_mio_drv_en_op_only), | |
6182 | .dbg1_mio_drv_en_muxtest_op(dbg1_mio_drv_en_muxtest_op), | |
6183 | .dbg1_mio_drv_en_muxbist_op(dbg1_mio_drv_en_muxbist_op), | |
6184 | .dbg1_mio_drv_en_muxtest_inp(dbg1_mio_drv_en_muxtest_inp), | |
6185 | .dbg1_mio_drv_en_muxtestpll_inp(dbg1_mio_drv_en_muxtestpll_inp), | |
6186 | .dbg1_mio_sel_niu_debug_mode(dbg1_mio_sel_niu_debug_mode), | |
6187 | .dbg1_mio_sel_pcix_debug_mode(dbg1_mio_sel_pcix_debug_mode), | |
6188 | .dbg1_mio_sel_soc_obs_mode(dbg1_mio_sel_soc_obs_mode), | |
6189 | .dbg1_mio_drv_imped(dbg1_mio_drv_imped[ 1 : 0 ]), | |
6190 | .dbg0_dbg1_l2b0_sio_ack_dest(dbg0_dbg1_l2b0_sio_ack_dest_ccxlff), | |
6191 | .dbg0_dbg1_l2b0_sio_ack_type(dbg0_dbg1_l2b0_sio_ack_type_ccxlff), | |
6192 | .dbg0_dbg1_l2b0_sio_ctag_vld(dbg0_dbg1_l2b0_sio_ctag_vld_ccxlff), | |
6193 | .dbg0_dbg1_l2b1_sio_ack_dest(dbg0_dbg1_l2b1_sio_ack_dest_ccxlff), | |
6194 | .dbg0_dbg1_l2b1_sio_ack_type(dbg0_dbg1_l2b1_sio_ack_type_ccxlff), | |
6195 | .dbg0_dbg1_l2b1_sio_ctag_vld(dbg0_dbg1_l2b1_sio_ctag_vld_ccxlff), | |
6196 | .dbg0_dbg1_l2b2_sio_ack_dest(dbg0_dbg1_l2b2_sio_ack_dest_ccxlff), | |
6197 | .dbg0_dbg1_l2b2_sio_ack_type(dbg0_dbg1_l2b2_sio_ack_type_ccxlff), | |
6198 | .dbg0_dbg1_l2b2_sio_ctag_vld(dbg0_dbg1_l2b2_sio_ctag_vld_ccxlff), | |
6199 | .dbg0_dbg1_l2b3_sio_ack_dest(dbg0_dbg1_l2b3_sio_ack_dest_ccxlff), | |
6200 | .dbg0_dbg1_l2b3_sio_ack_type(dbg0_dbg1_l2b3_sio_ack_type_ccxlff), | |
6201 | .dbg0_dbg1_l2b3_sio_ctag_vld(dbg0_dbg1_l2b3_sio_ctag_vld_ccxlff), | |
6202 | .dbg0_dbg1_l2t0_err_event(dbg0_dbg1_l2t0_err_event_ccxlff), | |
6203 | .dbg0_dbg1_l2t0_pa_match(dbg0_dbg1_l2t0_pa_match_ccxlff), | |
6204 | .dbg0_dbg1_l2t0_sii_iq_dequeue(dbg0_dbg1_l2t0_sii_iq_dequeue_ccxlff), | |
6205 | .dbg0_dbg1_l2t0_sii_wib_dequeue(dbg0_dbg1_l2t0_sii_wib_dequeue_ccxlff), | |
6206 | .dbg0_dbg1_l2t0_xbar_vcid(dbg0_dbg1_l2t0_xbar_vcid_ccxlff[ 5 : 0 ]), | |
6207 | .dbg0_dbg1_l2t2_err_event(dbg0_dbg1_l2t2_err_event_ccxlff), | |
6208 | .dbg0_dbg1_l2t2_pa_match(dbg0_dbg1_l2t2_pa_match_ccxlff), | |
6209 | .dbg0_dbg1_l2t2_sii_iq_dequeue(dbg0_dbg1_l2t2_sii_iq_dequeue_ccxlff), | |
6210 | .dbg0_dbg1_l2t2_sii_wib_dequeue(dbg0_dbg1_l2t2_sii_wib_dequeue_ccxlff), | |
6211 | .dbg0_dbg1_l2t2_xbar_vcid(dbg0_dbg1_l2t2_xbar_vcid_ccxlff[ 5 : 0 ]), | |
6212 | .dbg0_dbg1_spc0_instr_cmt_grp0({dbg0_dbg1_spc0_instr_cmt_grp0_ccxlff_1,dbg0_dbg1_spc0_instr_cmt_grp0_ccxlff_0}), | |
6213 | .dbg0_dbg1_spc0_instr_cmt_grp1({dbg0_dbg1_spc0_instr_cmt_grp1_ccxlff_1,dbg0_dbg1_spc0_instr_cmt_grp1_ccxlff_0}), | |
6214 | .dbg0_dbg1_spc2_instr_cmt_grp0({dbg0_dbg1_spc2_instr_cmt_grp0_ccxlff_1,dbg0_dbg1_spc2_instr_cmt_grp0_ccxlff_0}), | |
6215 | .dbg0_dbg1_spc2_instr_cmt_grp1({dbg0_dbg1_spc2_instr_cmt_grp1_ccxlff_1,dbg0_dbg1_spc2_instr_cmt_grp1_ccxlff_0}), | |
6216 | .dbg0_dbg1_debug_data(dbg0_dbg1_debug_data[ 165 : 0 ]), | |
6217 | .tcu_atpg_mode(tcu_atpg_mode), | |
6218 | .tcu_dbr_gateoff(tcu_dbr_gateoff), | |
6219 | .cluster_arst_l(cluster_arst_l), | |
6220 | .l2t5_dbg1_err_event(l2t5_dbg1_err_event) | |
6221 | ); | |
6222 | `endif // OPENSPARC_CMP | |
6223 | ||
6224 | //________________________________________________________________ | |
6225 | ||
6226 | ||
6227 | `ifndef RTL_NO_SPC0 | |
6228 | spc spc0( | |
6229 | .vnw_ary0 (SPC_VNW[ 0 ]), | |
6230 | .vnw_ary1 (SPC_VNW[ 0 ]), | |
6231 | .gclk ( cmp_gclk_c3_spc0 ), // cmp_gclk_c1_r[1]) , | |
6232 | .tcu_clk_stop ( gl_spc0_clk_stop ), // staged clk_stop | |
6233 | .cpx_spc_data_cx (cpx_spc0_data_cx2[ 145 : 0 ] ),// sparc core | |
6234 | .pcx_spc_grant_px (pcx_spc0_grant_px[ 8 : 0 ] ), | |
6235 | .spc_pcx_req_pq (spc0_pcx_req_pq[ 8 : 0 ] ), | |
6236 | .spc_pcx_atm_pq (spc0_pcx_atm_pq[ 8 : 0 ] ), | |
6237 | .spc_pcx_data_pa (spc0_pcx_data_pa[ 129 : 0 ] ), | |
6238 | .spc_hardstop_request (spc0_hardstop_request), | |
6239 | .spc_softstop_request (spc0_softstop_request), | |
6240 | .spc_trigger_pulse (spc0_trigger_pulse), | |
6241 | .tcu_ss_mode (tcu_ss_mode[ 0 ]), | |
6242 | .tcu_do_mode (tcu_do_mode[ 0 ]), | |
6243 | .tcu_ss_request (tcu_ss_request_t1lff_0), | |
6244 | .spc_ss_complete (spc0_ss_complete), | |
6245 | .tcu_aclk (tcu_spc0_aclk ), | |
6246 | .tcu_bclk (tcu_spc0_bclk ), | |
6247 | .tcu_scan_en (tcu_spc0_scan_en ), | |
6248 | .tcu_se_scancollar_in (tcu_spc0_se_scancollar_in ), | |
6249 | .tcu_se_scancollar_out (tcu_spc0_se_scancollar_out ), | |
6250 | .tcu_array_wr_inhibit (tcu_spc0_array_wr_inhibit ), | |
6251 | .tcu_core_running (ncu_spc0_core_running[ 7 : 0 ] ), | |
6252 | .spc_core_running_status (spc0_ncu_core_running_status[ 7 : 0 ]), | |
6253 | .const_cpuid ({1'b0, 1'b0, 1'b0} ),//No 3'b101 to Astro. | |
6254 | .power_throttle (mio_spc_pwr_throttle_0[ 2 : 0 ]), | |
6255 | .scan_out (spc0_tcu_scan_in[ 1 : 0 ] ), | |
6256 | .scan_in (tcu_spc0_scan_out[ 1 : 0 ] ), | |
6257 | .spc_dbg_instr_cmt_grp0 (spc0_dbg0_instr_cmt_grp0[ 1 : 0 ]), | |
6258 | .spc_dbg_instr_cmt_grp1 (spc0_dbg0_instr_cmt_grp1[ 1 : 0 ]), | |
6259 | .tcu_spc_mbist_start (tcu_spc0_mbist_start_t1lff_0), | |
6260 | .spc_mbist_done (spc0_tcu_mbist_done ), | |
6261 | .spc_mbist_fail (spc0_tcu_mbist_fail ), | |
6262 | .tcu_spc_mbist_scan_in (tcu_spc0_mbist_scan_in ), | |
6263 | .spc_tcu_mbist_scan_out (spc0_tcu_mbist_scan_out ), | |
6264 | .dmo_din (36'b0 ), | |
6265 | .dmo_dout (spc0_dmo_dout[ 35 : 0 ] ), | |
6266 | .dmo_coresel (1'b0 ), | |
6267 | .tcu_spc_lbist_start (tcu_spc_lbist_start[ 0 ] ), | |
6268 | .tcu_spc_lbist_scan_in (tcu_spc_lbist_scan_in[ 0 ] ), | |
6269 | .spc_tcu_lbist_done (spc0_tcu_lbist_done ), | |
6270 | .spc_tcu_lbist_scan_out (spc0_tcu_lbist_scan_out ), | |
6271 | .tcu_shscan_pce_ov (tcu_spc_shscan_pce_ov ), | |
6272 | .tcu_shscan_aclk (tcu_spc_shscan_aclk ), | |
6273 | .tcu_shscan_bclk (tcu_spc_shscan_bclk ), | |
6274 | .tcu_shscan_scan_en (tcu_spc_shscan_scan_en ), | |
6275 | .tcu_shscanid (tcu_spc_shscanid[ 2 : 0 ] ), | |
6276 | .tcu_shscan_scan_in (tcu_spc0_shscan_scan_out ), | |
6277 | .spc_shscan_scan_out (spc0_tcu_shscan_scan_in ), | |
6278 | .tcu_shscan_clk_stop (tcu_spc0_shscan_clk_stop ), | |
6279 | .efu_spc_fuse_data (efu_spc0246_fuse_data ), | |
6280 | .efu_spc_fuse_ixfer_en (efu_spc0_fuse_ixfer_en ), | |
6281 | .efu_spc_fuse_iclr (efu_spc0_fuse_iclr ), | |
6282 | .efu_spc_fuse_dxfer_en (efu_spc0_fuse_dxfer_en ), | |
6283 | .efu_spc_fuse_dclr (efu_spc0_fuse_dclr ), | |
6284 | .spc_efu_fuse_dxfer_en (spc0_efu_fuse_dxfer_en ), | |
6285 | .spc_efu_fuse_ixfer_en (spc0_efu_fuse_ixfer_en ), | |
6286 | .spc_efu_fuse_ddata (spc0_efu_fuse_ddata ), | |
6287 | .spc_efu_fuse_idata (spc0_efu_fuse_idata ), | |
6288 | .ccu_slow_cmp_sync_en ( gl_io_cmp_sync_en_c3t0 ), // gl_io_cmp_sync_en_c3t - for int6.1 | |
6289 | .ccu_cmp_slow_sync_en ( gl_cmp_io_sync_en_c3t0 ), // gl_cmp_io_sync_en_c3t - for int6.1 | |
6290 | .hver_mask_minor_rev (spc_revid_out[ 3 : 0 ] ), | |
6291 | .tcu_pce_ov(tcu_pce_ov), | |
6292 | .tcu_dectest(tcu_dectest), | |
6293 | .tcu_muxtest(tcu_muxtest), | |
6294 | .rst_wmr_protect(rst_wmr_protect), | |
6295 | .cluster_arst_l(cluster_arst_l), | |
6296 | .tcu_mbist_bisi_en(tcu_mbist_bisi_en), | |
6297 | .tcu_mbist_user_mode(tcu_mbist_user_mode), | |
6298 | .ncu_cmp_tick_enable(ncu_cmp_tick_enable), | |
6299 | .ncu_wmr_vec_mask(ncu_wmr_vec_mask), | |
6300 | .ncu_spc_pm(ncu_spc_pm), | |
6301 | .ncu_spc_ba01(ncu_spc_ba01), | |
6302 | .ncu_spc_ba23(ncu_spc_ba23), | |
6303 | .ncu_spc_ba45(ncu_spc_ba45), | |
6304 | .ncu_spc_ba67(ncu_spc_ba67), | |
6305 | .tcu_spc_lbist_pgm(tcu_spc_lbist_pgm), | |
6306 | .tcu_spc_test_mode(tcu_spc0_test_mode), | |
6307 | .dmo_icmuxctl(dmo_icmuxctl), | |
6308 | .dmo_dcmuxctl(dmo_dcmuxctl), | |
6309 | .tcu_atpg_mode(tcu_atpg_mode), | |
6310 | .ncu_spc_l2_idx_hash_en(ncu_spc_l2_idx_hash_en) | |
6311 | ); | |
6312 | `else | |
6313 | `ifndef CMP | |
6314 | assign spc0_pcx_req_pq[8:0] = 9'bz; | |
6315 | assign spc0_pcx_atm_pq[8:0] = 9'bz; | |
6316 | assign spc0_pcx_data_pa[129:0] = 130'bz; | |
6317 | assign spc0_tcu_scan_in[1:0] = 2'b0; | |
6318 | assign spc0_ncu_core_running_status[7:0] = 8'b0; | |
6319 | assign spc0_tcu_shscan_scan_in = 1'b0; | |
6320 | assign spc0_tcu_mbist_done = 1'b0; | |
6321 | assign spc0_tcu_mbist_fail = 1'b0; | |
6322 | assign spc0_tcu_mbist_scan_out = 1'b0; | |
6323 | assign spc0_dmo_dout = 36'b0; | |
6324 | assign spc0_tcu_lbist_done = 1'b0; | |
6325 | assign spc0_tcu_lbist_scan_out = 1'b0; | |
6326 | assign spc0_hardstop_request = 1'b0; | |
6327 | assign spc0_softstop_request = 1'b0; | |
6328 | assign spc0_trigger_pulse = 1'b0; | |
6329 | assign spc0_ss_complete = 1'b0; | |
6330 | assign spc0_dbg0_instr_cmt_grp0[1:0] = 2'b0; | |
6331 | assign spc0_dbg0_instr_cmt_grp1[1:0] = 2'b0; | |
6332 | assign spc0_efu_fuse_ddata =1'b0; | |
6333 | assign spc0_efu_fuse_dxfer_en =1'b0; | |
6334 | assign spc0_efu_fuse_idata =1'b0; | |
6335 | assign spc0_efu_fuse_ixfer_en =1'b0; | |
6336 | `endif | |
6337 | `endif | |
6338 | ||
6339 | ||
6340 | //________________________________________________________________ | |
6341 | ||
6342 | ||
6343 | `ifndef RTL_NO_SPC1 | |
6344 | spc spc1( | |
6345 | .vnw_ary0 (SPC_VNW[ 1 ]), | |
6346 | .vnw_ary1 (SPC_VNW[ 1 ]), | |
6347 | .gclk ( cmp_gclk_c2_spc1 ), // cmp_gclk_c1_r[1]) , | |
6348 | .tcu_clk_stop ( gl_spc1_clk_stop ), // staged clk_stop | |
6349 | ||
6350 | .cpx_spc_data_cx (cpx_spc1_data_cx2[ 145 : 0 ] ),// sparc core | |
6351 | .pcx_spc_grant_px (pcx_spc1_grant_px[ 8 : 0 ] ), | |
6352 | .spc_pcx_req_pq (spc1_pcx_req_pq[ 8 : 0 ] ), | |
6353 | .spc_pcx_atm_pq (spc1_pcx_atm_pq[ 8 : 0 ] ), | |
6354 | .spc_pcx_data_pa (spc1_pcx_data_pa[ 129 : 0 ] ), | |
6355 | .spc_hardstop_request (spc1_hardstop_request), | |
6356 | .spc_softstop_request (spc1_softstop_request), | |
6357 | .spc_trigger_pulse (spc1_trigger_pulse), | |
6358 | .tcu_ss_mode (tcu_ss_mode[ 1 ]), | |
6359 | .tcu_do_mode (tcu_do_mode[ 1 ]), | |
6360 | .tcu_ss_request (tcu_ss_request[ 1 ]), | |
6361 | .spc_ss_complete (spc1_ss_complete), | |
6362 | .tcu_aclk (tcu_spc1_aclk ), | |
6363 | .tcu_bclk (tcu_spc1_bclk ), | |
6364 | .tcu_scan_en (tcu_spc1_scan_en ), | |
6365 | .tcu_se_scancollar_in (tcu_spc1_se_scancollar_in ), | |
6366 | .tcu_se_scancollar_out (tcu_spc1_se_scancollar_out ), | |
6367 | .tcu_array_wr_inhibit (tcu_spc1_array_wr_inhibit ), | |
6368 | .tcu_core_running (ncu_spc1_core_running[ 7 : 0 ] ), | |
6369 | .spc_core_running_status (spc1_ncu_core_running_status[ 7 : 0 ]), | |
6370 | .const_cpuid ({1'b0, 1'b0, 1'b1} ),//No 3'b101 to Astro. | |
6371 | .power_throttle (mio_spc_pwr_throttle_0[ 2 : 0 ]), | |
6372 | .scan_out (spc1_tcu_scan_in[ 1 : 0 ] ), | |
6373 | .scan_in (tcu_spc1_scan_out[ 1 : 0 ] ), | |
6374 | .spc_dbg_instr_cmt_grp0 (spc1_dbg1_instr_cmt_grp0[ 1 : 0 ]), | |
6375 | .spc_dbg_instr_cmt_grp1 (spc1_dbg1_instr_cmt_grp1[ 1 : 0 ]), | |
6376 | .tcu_spc_mbist_start (tcu_spc_mbist_start[ 1 ] ), | |
6377 | .spc_mbist_done (spc1_tcu_mbist_done ), | |
6378 | .spc_mbist_fail (spc1_tcu_mbist_fail ), | |
6379 | .tcu_spc_mbist_scan_in (tcu_spc1_mbist_scan_in ), | |
6380 | .spc_tcu_mbist_scan_out (spc1_tcu_mbist_scan_out ), | |
6381 | .dmo_din (spc0_dmo_dout[ 35 : 0 ] ), | |
6382 | .dmo_dout (spc1_dmo_dout[ 35 : 0 ] ), | |
6383 | .dmo_coresel (dmo_coresel[ 5 ] ), | |
6384 | .tcu_spc_lbist_start (tcu_spc_lbist_start[ 1 ] ), | |
6385 | .tcu_spc_lbist_scan_in (tcu_spc_lbist_scan_in[ 1 ] ), | |
6386 | .spc_tcu_lbist_done (spc1_tcu_lbist_done ), | |
6387 | .spc_tcu_lbist_scan_out (spc1_tcu_lbist_scan_out ), | |
6388 | .tcu_shscan_pce_ov (tcu_spc_shscan_pce_ov ), | |
6389 | .tcu_shscan_aclk (tcu_spc_shscan_aclk ), | |
6390 | .tcu_shscan_bclk (tcu_spc_shscan_bclk ), | |
6391 | .tcu_shscan_scan_en (tcu_spc_shscan_scan_en ), | |
6392 | .tcu_shscanid (tcu_spc_shscanid[ 2 : 0 ] ), | |
6393 | .tcu_shscan_scan_in (tcu_spc1_shscan_scan_out ), | |
6394 | .spc_shscan_scan_out (spc1_tcu_shscan_scan_in ), | |
6395 | .tcu_shscan_clk_stop (tcu_spc1_shscan_clk_stop ), | |
6396 | .efu_spc_fuse_data (efu_spc1357_fuse_data ), | |
6397 | .efu_spc_fuse_ixfer_en (efu_spc1_fuse_ixfer_en ), | |
6398 | .efu_spc_fuse_iclr (efu_spc1_fuse_iclr ), | |
6399 | .efu_spc_fuse_dxfer_en (efu_spc1_fuse_dxfer_en ), | |
6400 | .efu_spc_fuse_dclr (efu_spc1_fuse_dclr ), | |
6401 | .spc_efu_fuse_dxfer_en (spc1_efu_fuse_dxfer_en ), | |
6402 | .spc_efu_fuse_ixfer_en (spc1_efu_fuse_ixfer_en ), | |
6403 | .spc_efu_fuse_ddata (spc1_efu_fuse_ddata ), | |
6404 | .spc_efu_fuse_idata (spc1_efu_fuse_idata ), | |
6405 | .ccu_slow_cmp_sync_en ( gl_io_cmp_sync_en_c2t ), | |
6406 | .ccu_cmp_slow_sync_en ( gl_cmp_io_sync_en_c2t ), | |
6407 | .hver_mask_minor_rev (spc_revid_out[ 3 : 0 ] ), | |
6408 | .tcu_spc_test_mode (tcu_spc1_test_mode), | |
6409 | .tcu_pce_ov(tcu_pce_ov), | |
6410 | .tcu_dectest(tcu_dectest), | |
6411 | .tcu_muxtest(tcu_muxtest), | |
6412 | .tcu_atpg_mode(tcu_atpg_mode), | |
6413 | .rst_wmr_protect(rst_wmr_protect), | |
6414 | .cluster_arst_l(cluster_arst_l), | |
6415 | .tcu_mbist_bisi_en(tcu_mbist_bisi_en), | |
6416 | .tcu_mbist_user_mode(tcu_mbist_user_mode), | |
6417 | .ncu_cmp_tick_enable(ncu_cmp_tick_enable), | |
6418 | .ncu_wmr_vec_mask(ncu_wmr_vec_mask), | |
6419 | .ncu_spc_pm(ncu_spc_pm), | |
6420 | .ncu_spc_ba01(ncu_spc_ba01), | |
6421 | .ncu_spc_ba23(ncu_spc_ba23), | |
6422 | .ncu_spc_ba45(ncu_spc_ba45), | |
6423 | .ncu_spc_ba67(ncu_spc_ba67), | |
6424 | .tcu_spc_lbist_pgm(tcu_spc_lbist_pgm), | |
6425 | .dmo_icmuxctl(dmo_icmuxctl), | |
6426 | .dmo_dcmuxctl(dmo_dcmuxctl), | |
6427 | .ncu_spc_l2_idx_hash_en(ncu_spc_l2_idx_hash_en) | |
6428 | ); | |
6429 | `else | |
6430 | `ifndef CMP | |
6431 | assign spc1_pcx_req_pq[8:0] = 9'bz; | |
6432 | assign spc1_pcx_atm_pq[8:0] = 9'bz; | |
6433 | assign spc1_pcx_data_pa[129:0] = 130'bz; | |
6434 | assign spc1_tcu_scan_in[1:0] = 2'b0; | |
6435 | assign spc1_ncu_core_running_status[7:0] = 8'b0; | |
6436 | assign spc1_tcu_shscan_scan_in = 1'b0; | |
6437 | assign spc1_tcu_mbist_done = 1'b0; | |
6438 | assign spc1_tcu_mbist_fail = 1'b0; | |
6439 | assign spc1_tcu_mbist_scan_out = 1'b0; | |
6440 | assign spc1_dmo_dout = 36'b0; | |
6441 | assign spc1_tcu_lbist_done = 1'b0; | |
6442 | assign spc1_tcu_lbist_scan_out = 1'b0; | |
6443 | assign spc1_hardstop_request = 1'b0; | |
6444 | assign spc1_softstop_request = 1'b0; | |
6445 | assign spc1_trigger_pulse = 1'b0; | |
6446 | assign spc1_ss_complete = 1'b0; | |
6447 | assign spc1_dbg1_instr_cmt_grp0[1:0] = 2'b0; | |
6448 | assign spc1_dbg1_instr_cmt_grp1[1:0] = 2'b0; | |
6449 | assign spc1_efu_fuse_ddata =1'b0; | |
6450 | assign spc1_efu_fuse_dxfer_en =1'b0; | |
6451 | assign spc1_efu_fuse_idata =1'b0; | |
6452 | assign spc1_efu_fuse_ixfer_en =1'b0; | |
6453 | `endif | |
6454 | `endif | |
6455 | ||
6456 | ||
6457 | //________________________________________________________________ | |
6458 | ||
6459 | ||
6460 | ||
6461 | `ifndef RTL_NO_SPC2 | |
6462 | spc spc2( | |
6463 | .vnw_ary0 (SPC_VNW[ 2 ]), | |
6464 | .vnw_ary1 (SPC_VNW[ 2 ]), | |
6465 | .gclk ( cmp_gclk_c3_spc2 ), // cmp_gclk_c1_r[6]) , | |
6466 | .tcu_clk_stop ( gl_spc2_clk_stop ), // staged clk_stop | |
6467 | ||
6468 | .cpx_spc_data_cx (cpx_spc2_data_cx2[ 145 : 0 ] ),// sparc core | |
6469 | .pcx_spc_grant_px (pcx_spc2_grant_px[ 8 : 0 ] ), | |
6470 | .spc_pcx_req_pq (spc2_pcx_req_pq[ 8 : 0 ] ), | |
6471 | .spc_pcx_atm_pq (spc2_pcx_atm_pq[ 8 : 0 ] ), | |
6472 | .spc_pcx_data_pa (spc2_pcx_data_pa[ 129 : 0 ] ), | |
6473 | .spc_hardstop_request (spc2_hardstop_request), | |
6474 | .spc_softstop_request (spc2_softstop_request), | |
6475 | .spc_trigger_pulse (spc2_trigger_pulse), | |
6476 | .tcu_ss_mode (tcu_ss_mode[ 2 ]), | |
6477 | .tcu_do_mode (tcu_do_mode[ 2 ]), | |
6478 | .tcu_ss_request (tcu_ss_request_t3lff_2), | |
6479 | .spc_ss_complete (spc2_ss_complete), | |
6480 | .tcu_aclk (tcu_spc2_aclk ), | |
6481 | .tcu_bclk (tcu_spc2_bclk ), | |
6482 | .tcu_scan_en (tcu_spc2_scan_en ), | |
6483 | .tcu_se_scancollar_in (tcu_spc2_se_scancollar_in ), | |
6484 | .tcu_se_scancollar_out (tcu_spc2_se_scancollar_out ), | |
6485 | .tcu_array_wr_inhibit (tcu_spc2_array_wr_inhibit ), | |
6486 | .tcu_core_running (ncu_spc2_core_running[ 7 : 0 ] ), | |
6487 | .spc_core_running_status (spc2_ncu_core_running_status[ 7 : 0 ]), | |
6488 | .const_cpuid ({1'b0, 1'b1, 1'b0} ),//No 3'b101 to Astro. | |
6489 | .power_throttle (mio_spc_pwr_throttle_1[ 2 : 0 ]), | |
6490 | .scan_out (spc2_tcu_scan_in[ 1 : 0 ] ), | |
6491 | .scan_in (tcu_spc2_scan_out[ 1 : 0 ] ), | |
6492 | .spc_dbg_instr_cmt_grp0 (spc2_dbg0_instr_cmt_grp0[ 1 : 0 ]), | |
6493 | .spc_dbg_instr_cmt_grp1 (spc2_dbg0_instr_cmt_grp1[ 1 : 0 ]), | |
6494 | .tcu_spc_mbist_start (tcu_spc_mbist_start_t3lff_2 ), | |
6495 | .spc_mbist_done (spc2_tcu_mbist_done ), | |
6496 | .spc_mbist_fail (spc2_tcu_mbist_fail ), | |
6497 | .tcu_spc_mbist_scan_in (tcu_spc2_mbist_scan_in ), | |
6498 | .spc_tcu_mbist_scan_out (spc2_tcu_mbist_scan_out ), | |
6499 | .dmo_din (36'b0 ), | |
6500 | .dmo_dout (spc2_dmo_dout[ 35 : 0 ] ), | |
6501 | .dmo_coresel (1'b0 ), | |
6502 | .tcu_spc_lbist_start (tcu_spc_lbist_start[ 2 ] ), | |
6503 | .tcu_spc_lbist_scan_in (tcu_spc_lbist_scan_in[ 2 ] ), | |
6504 | .spc_tcu_lbist_done (spc2_tcu_lbist_done ), | |
6505 | .spc_tcu_lbist_scan_out (spc2_tcu_lbist_scan_out ), | |
6506 | .tcu_shscan_pce_ov (tcu_spc_shscan_pce_ov ), | |
6507 | .tcu_shscan_aclk (tcu_spc_shscan_aclk ), | |
6508 | .tcu_shscan_bclk (tcu_spc_shscan_bclk ), | |
6509 | .tcu_shscan_scan_en (tcu_spc_shscan_scan_en ), | |
6510 | .tcu_shscanid (tcu_spc_shscanid[ 2 : 0 ] ), | |
6511 | .tcu_shscan_scan_in (tcu_spc2_shscan_scan_out ), | |
6512 | .spc_shscan_scan_out (spc2_tcu_shscan_scan_in ), | |
6513 | .tcu_shscan_clk_stop (tcu_spc2_shscan_clk_stop ), | |
6514 | .efu_spc_fuse_data (efu_spc0246_fuse_data ), | |
6515 | .efu_spc_fuse_ixfer_en (efu_spc2_fuse_ixfer_en ), | |
6516 | .efu_spc_fuse_iclr (efu_spc2_fuse_iclr ), | |
6517 | .efu_spc_fuse_dxfer_en (efu_spc2_fuse_dxfer_en ), | |
6518 | .efu_spc_fuse_dclr (efu_spc2_fuse_dclr ), | |
6519 | .spc_efu_fuse_dxfer_en (spc2_efu_fuse_dxfer_en ), | |
6520 | .spc_efu_fuse_ixfer_en (spc2_efu_fuse_ixfer_en ), | |
6521 | .spc_efu_fuse_ddata (spc2_efu_fuse_ddata ), | |
6522 | .spc_efu_fuse_idata (spc2_efu_fuse_idata ), | |
6523 | .ccu_slow_cmp_sync_en ( gl_io_cmp_sync_en_c3b ), | |
6524 | .ccu_cmp_slow_sync_en ( gl_cmp_io_sync_en_c3b ), | |
6525 | .hver_mask_minor_rev (spc_revid_out[ 3 : 0 ] ), | |
6526 | .tcu_spc_test_mode (tcu_spc2_test_mode), | |
6527 | .tcu_pce_ov(tcu_pce_ov), | |
6528 | .tcu_dectest(tcu_dectest), | |
6529 | .tcu_muxtest(tcu_muxtest), | |
6530 | .tcu_atpg_mode(tcu_atpg_mode), | |
6531 | .rst_wmr_protect(rst_wmr_protect), | |
6532 | .cluster_arst_l(cluster_arst_l), | |
6533 | .tcu_mbist_bisi_en(tcu_mbist_bisi_en), | |
6534 | .tcu_mbist_user_mode(tcu_mbist_user_mode), | |
6535 | .ncu_cmp_tick_enable(ncu_cmp_tick_enable), | |
6536 | .ncu_wmr_vec_mask(ncu_wmr_vec_mask), | |
6537 | .ncu_spc_pm(ncu_spc_pm), | |
6538 | .ncu_spc_ba01(ncu_spc_ba01), | |
6539 | .ncu_spc_ba23(ncu_spc_ba23), | |
6540 | .ncu_spc_ba45(ncu_spc_ba45), | |
6541 | .ncu_spc_ba67(ncu_spc_ba67), | |
6542 | .tcu_spc_lbist_pgm(tcu_spc_lbist_pgm), | |
6543 | .dmo_icmuxctl(dmo_icmuxctl), | |
6544 | .dmo_dcmuxctl(dmo_dcmuxctl), | |
6545 | .ncu_spc_l2_idx_hash_en(ncu_spc_l2_idx_hash_en) | |
6546 | ); | |
6547 | `else | |
6548 | `ifndef CMP | |
6549 | assign spc2_pcx_req_pq[8:0] = 9'bz; | |
6550 | assign spc2_pcx_atm_pq[8:0] = 9'bz; | |
6551 | assign spc2_pcx_data_pa[129:0] = 130'bz; | |
6552 | assign spc2_tcu_scan_in[1:0] = 2'b0; | |
6553 | assign spc2_ncu_core_running_status[7:0] = 8'b0; | |
6554 | assign spc2_tcu_shscan_scan_in = 1'b0; | |
6555 | assign spc2_tcu_mbist_done = 1'b0; | |
6556 | assign spc2_tcu_mbist_fail = 1'b0; | |
6557 | assign spc2_tcu_mbist_scan_out = 1'b0; | |
6558 | assign spc2_dmo_dout = 36'b0; | |
6559 | assign spc2_tcu_lbist_done = 1'b0; | |
6560 | assign spc2_tcu_lbist_scan_out = 1'b0; | |
6561 | assign spc2_hardstop_request = 1'b0; | |
6562 | assign spc2_softstop_request = 1'b0; | |
6563 | assign spc2_trigger_pulse = 1'b0; | |
6564 | assign spc2_ss_complete = 1'b0; | |
6565 | assign spc2_dbg0_instr_cmt_grp0[1:0] = 2'b0; | |
6566 | assign spc2_dbg0_instr_cmt_grp1[1:0] = 2'b0; | |
6567 | assign spc2_efu_fuse_ddata =1'b0; | |
6568 | assign spc2_efu_fuse_dxfer_en =1'b0; | |
6569 | assign spc2_efu_fuse_idata =1'b0; | |
6570 | assign spc2_efu_fuse_ixfer_en =1'b0; | |
6571 | `endif | |
6572 | `endif | |
6573 | ||
6574 | ||
6575 | //________________________________________________________________ | |
6576 | ||
6577 | ||
6578 | `ifndef RTL_NO_SPC3 | |
6579 | spc spc3( | |
6580 | .vnw_ary0 (SPC_VNW[ 3 ]), | |
6581 | .vnw_ary1 (SPC_VNW[ 3 ]), | |
6582 | .gclk ( cmp_gclk_c2_spc3 ), // cmp_gclk_c1_r[6]) , | |
6583 | .tcu_clk_stop ( gl_spc3_clk_stop ), // staged clk_stop | |
6584 | ||
6585 | .cpx_spc_data_cx (cpx_spc3_data_cx2[ 145 : 0 ] ),// sparc core | |
6586 | .pcx_spc_grant_px (pcx_spc3_grant_px[ 8 : 0 ] ), | |
6587 | .spc_pcx_req_pq (spc3_pcx_req_pq[ 8 : 0 ] ), | |
6588 | .spc_pcx_atm_pq (spc3_pcx_atm_pq[ 8 : 0 ] ), | |
6589 | .spc_pcx_data_pa (spc3_pcx_data_pa[ 129 : 0 ] ), | |
6590 | .spc_hardstop_request (spc3_hardstop_request), | |
6591 | .spc_softstop_request (spc3_softstop_request), | |
6592 | .spc_trigger_pulse (spc3_trigger_pulse), | |
6593 | .tcu_ss_mode (tcu_ss_mode[ 3 ]), | |
6594 | .tcu_do_mode (tcu_do_mode[ 3 ]), | |
6595 | .tcu_ss_request (tcu_ss_request[ 3 ]), | |
6596 | .spc_ss_complete (spc3_ss_complete), | |
6597 | .tcu_aclk (tcu_spc3_aclk ), | |
6598 | .tcu_bclk (tcu_spc3_bclk ), | |
6599 | .tcu_scan_en (tcu_spc3_scan_en ), | |
6600 | .tcu_se_scancollar_in (tcu_spc3_se_scancollar_in ), | |
6601 | .tcu_se_scancollar_out (tcu_spc3_se_scancollar_out ), | |
6602 | .tcu_array_wr_inhibit (tcu_spc3_array_wr_inhibit ), | |
6603 | .tcu_core_running (ncu_spc3_core_running[ 7 : 0 ] ), | |
6604 | .spc_core_running_status (spc3_ncu_core_running_status[ 7 : 0 ]), | |
6605 | .const_cpuid ({1'b0, 1'b1, 1'b1} ),//No 3'b101 to Astro. | |
6606 | .power_throttle (mio_spc_pwr_throttle_1[ 2 : 0 ]), | |
6607 | .scan_out (spc3_tcu_scan_in[ 1 : 0 ] ), | |
6608 | .scan_in (tcu_spc3_scan_out[ 1 : 0 ] ), | |
6609 | .spc_dbg_instr_cmt_grp0 (spc3_dbg1_instr_cmt_grp0[ 1 : 0 ]), | |
6610 | .spc_dbg_instr_cmt_grp1 (spc3_dbg1_instr_cmt_grp1[ 1 : 0 ]), | |
6611 | .tcu_spc_mbist_start (tcu_spc_mbist_start[ 3 ] ), | |
6612 | .spc_mbist_done (spc3_tcu_mbist_done ), | |
6613 | .spc_mbist_fail (spc3_tcu_mbist_fail ), | |
6614 | .tcu_spc_mbist_scan_in (tcu_spc3_mbist_scan_in ), | |
6615 | .spc_tcu_mbist_scan_out (spc3_tcu_mbist_scan_out ), | |
6616 | .dmo_din (spc2_dmo_dout[ 35 : 0 ] ), | |
6617 | .dmo_dout (spc3_dmo_dout[ 35 : 0 ] ), | |
6618 | .dmo_coresel (dmo_coresel[ 2 ] ), | |
6619 | .tcu_spc_lbist_start (tcu_spc_lbist_start[ 3 ] ), | |
6620 | .tcu_spc_lbist_scan_in (tcu_spc_lbist_scan_in[ 3 ] ), | |
6621 | .spc_tcu_lbist_done (spc3_tcu_lbist_done ), | |
6622 | .spc_tcu_lbist_scan_out (spc3_tcu_lbist_scan_out ), | |
6623 | .tcu_shscan_pce_ov (tcu_spc_shscan_pce_ov ), | |
6624 | .tcu_shscan_aclk (tcu_spc_shscan_aclk ), | |
6625 | .tcu_shscan_bclk (tcu_spc_shscan_bclk ), | |
6626 | .tcu_shscan_scan_en (tcu_spc_shscan_scan_en ), | |
6627 | .tcu_shscanid (tcu_spc_shscanid[ 2 : 0 ] ), | |
6628 | .tcu_shscan_scan_in (tcu_spc3_shscan_scan_out ), | |
6629 | .spc_shscan_scan_out (spc3_tcu_shscan_scan_in ), | |
6630 | .tcu_shscan_clk_stop (tcu_spc3_shscan_clk_stop ), | |
6631 | .efu_spc_fuse_data (efu_spc1357_fuse_data ), | |
6632 | .efu_spc_fuse_ixfer_en (efu_spc3_fuse_ixfer_en ), | |
6633 | .efu_spc_fuse_iclr (efu_spc3_fuse_iclr ), | |
6634 | .efu_spc_fuse_dxfer_en (efu_spc3_fuse_dxfer_en ), | |
6635 | .efu_spc_fuse_dclr (efu_spc3_fuse_dclr ), | |
6636 | .spc_efu_fuse_dxfer_en (spc3_efu_fuse_dxfer_en ), | |
6637 | .spc_efu_fuse_ixfer_en (spc3_efu_fuse_ixfer_en ), | |
6638 | .spc_efu_fuse_ddata (spc3_efu_fuse_ddata ), | |
6639 | .spc_efu_fuse_idata (spc3_efu_fuse_idata ), | |
6640 | .ccu_slow_cmp_sync_en ( gl_io_cmp_sync_en_c2b ), | |
6641 | .ccu_cmp_slow_sync_en ( gl_cmp_io_sync_en_c2b ), | |
6642 | .hver_mask_minor_rev (spc_revid_out[ 3 : 0 ] ), | |
6643 | .tcu_spc_test_mode (tcu_spc3_test_mode), | |
6644 | .tcu_pce_ov(tcu_pce_ov), | |
6645 | .tcu_dectest(tcu_dectest), | |
6646 | .tcu_muxtest(tcu_muxtest), | |
6647 | .tcu_atpg_mode(tcu_atpg_mode), | |
6648 | .rst_wmr_protect(rst_wmr_protect), | |
6649 | .cluster_arst_l(cluster_arst_l), | |
6650 | .tcu_mbist_bisi_en(tcu_mbist_bisi_en), | |
6651 | .tcu_mbist_user_mode(tcu_mbist_user_mode), | |
6652 | .ncu_cmp_tick_enable(ncu_cmp_tick_enable), | |
6653 | .ncu_wmr_vec_mask(ncu_wmr_vec_mask), | |
6654 | .ncu_spc_pm(ncu_spc_pm), | |
6655 | .ncu_spc_ba01(ncu_spc_ba01), | |
6656 | .ncu_spc_ba23(ncu_spc_ba23), | |
6657 | .ncu_spc_ba45(ncu_spc_ba45), | |
6658 | .ncu_spc_ba67(ncu_spc_ba67), | |
6659 | .tcu_spc_lbist_pgm(tcu_spc_lbist_pgm), | |
6660 | .dmo_icmuxctl(dmo_icmuxctl), | |
6661 | .dmo_dcmuxctl(dmo_dcmuxctl), | |
6662 | .ncu_spc_l2_idx_hash_en(ncu_spc_l2_idx_hash_en) | |
6663 | ); | |
6664 | `else | |
6665 | `ifndef CMP | |
6666 | assign spc3_pcx_req_pq[8:0] = 9'bz; | |
6667 | assign spc3_pcx_atm_pq[8:0] = 9'bz; | |
6668 | assign spc3_pcx_data_pa[129:0] = 130'bz; | |
6669 | assign spc3_tcu_scan_in[1:0] = 2'b0; | |
6670 | assign spc3_ncu_core_running_status[7:0] = 8'b0; | |
6671 | assign spc3_tcu_shscan_scan_in = 1'b0; | |
6672 | assign spc3_tcu_mbist_done = 1'b0; | |
6673 | assign spc3_tcu_mbist_fail = 1'b0; | |
6674 | assign spc3_tcu_mbist_scan_out = 1'b0; | |
6675 | assign spc3_dmo_dout = 36'b0; | |
6676 | assign spc3_tcu_lbist_done = 1'b0; | |
6677 | assign spc3_tcu_lbist_scan_out = 1'b0; | |
6678 | assign spc3_hardstop_request = 1'b0; | |
6679 | assign spc3_softstop_request = 1'b0; | |
6680 | assign spc3_trigger_pulse = 1'b0; | |
6681 | assign spc3_ss_complete = 1'b0; | |
6682 | assign spc3_dbg1_instr_cmt_grp0[1:0] = 2'b0; | |
6683 | assign spc3_dbg1_instr_cmt_grp1[1:0] = 2'b0; | |
6684 | assign spc3_efu_fuse_ddata =1'b0; | |
6685 | assign spc3_efu_fuse_dxfer_en =1'b0; | |
6686 | assign spc3_efu_fuse_idata =1'b0; | |
6687 | assign spc3_efu_fuse_ixfer_en =1'b0; | |
6688 | `endif | |
6689 | `endif | |
6690 | ||
6691 | ||
6692 | //________________________________________________________________ | |
6693 | ||
6694 | ||
6695 | `ifndef RTL_NO_SPC4 | |
6696 | spc spc4( | |
6697 | .vnw_ary0 (SPC_VNW[ 4 ]), | |
6698 | .vnw_ary1 (SPC_VNW[ 4 ]), | |
6699 | .gclk ( cmp_gclk_c1_spc4 ), // cmp_gclk_c2_r[1]) , | |
6700 | .tcu_clk_stop ( gl_spc4_clk_stop ), // staged clk_stop | |
6701 | .cpx_spc_data_cx (cpx_spc4_data_cx2[ 145 : 0 ] ),// sparc core | |
6702 | .pcx_spc_grant_px (pcx_spc4_grant_px[ 8 : 0 ] ), | |
6703 | .spc_pcx_req_pq (spc4_pcx_req_pq[ 8 : 0 ] ), | |
6704 | .spc_pcx_atm_pq (spc4_pcx_atm_pq[ 8 : 0 ] ), | |
6705 | .spc_pcx_data_pa (spc4_pcx_data_pa[ 129 : 0 ] ), | |
6706 | .spc_hardstop_request (spc4_hardstop_request), | |
6707 | .spc_softstop_request (spc4_softstop_request), | |
6708 | .spc_trigger_pulse (spc4_trigger_pulse), | |
6709 | .tcu_ss_mode (tcu_ss_mode[ 4 ]), | |
6710 | .tcu_do_mode (tcu_do_mode[ 4 ]), | |
6711 | .tcu_ss_request (tcu_ss_request[ 4 ]), | |
6712 | .spc_ss_complete (spc4_ss_complete), | |
6713 | .tcu_aclk (tcu_spc4_aclk ), | |
6714 | .tcu_bclk (tcu_spc4_bclk ), | |
6715 | .tcu_scan_en (tcu_spc4_scan_en ), | |
6716 | .tcu_se_scancollar_in (tcu_spc4_se_scancollar_in ), | |
6717 | .tcu_se_scancollar_out (tcu_spc4_se_scancollar_out ), | |
6718 | .tcu_array_wr_inhibit (tcu_spc4_array_wr_inhibit ), | |
6719 | .tcu_core_running (ncu_spc4_core_running[ 7 : 0 ] ), | |
6720 | .spc_core_running_status (spc4_ncu_core_running_status[ 7 : 0 ]), | |
6721 | .const_cpuid ({1'b1, 1'b0, 1'b0} ),//No 3'b101 to Astro. | |
6722 | .power_throttle (mio_spc_pwr_throttle_0[ 2 : 0 ]), | |
6723 | .scan_out (spc4_tcu_scan_in[ 1 : 0 ] ), | |
6724 | .scan_in (tcu_spc4_scan_out[ 1 : 0 ] ), | |
6725 | .spc_dbg_instr_cmt_grp0 (spc4_dbg1_instr_cmt_grp0[ 1 : 0 ]), | |
6726 | .spc_dbg_instr_cmt_grp1 (spc4_dbg1_instr_cmt_grp1[ 1 : 0 ]), | |
6727 | .tcu_spc_mbist_start (tcu_spc_mbist_start[ 4 ] ), | |
6728 | .spc_mbist_done (spc4_tcu_mbist_done ), | |
6729 | .spc_mbist_fail (spc4_tcu_mbist_fail ), | |
6730 | .tcu_spc_mbist_scan_in (tcu_spc4_mbist_scan_in ), | |
6731 | .spc_tcu_mbist_scan_out (spc4_tcu_mbist_scan_out ), | |
6732 | .dmo_din (spc5_dmo_dout[ 35 : 0 ] ), | |
6733 | .dmo_dout (spc4_dmo_dout[ 35 : 0 ] ), | |
6734 | .dmo_coresel (dmo_coresel[ 3 ] ), | |
6735 | .tcu_spc_lbist_start (tcu_spc_lbist_start[ 4 ] ), | |
6736 | .tcu_spc_lbist_scan_in (tcu_spc_lbist_scan_in[ 4 ] ), | |
6737 | .spc_tcu_lbist_done (spc4_tcu_lbist_done ), | |
6738 | .spc_tcu_lbist_scan_out (spc4_tcu_lbist_scan_out ), | |
6739 | .tcu_shscan_pce_ov (tcu_spc_shscan_pce_ov ), | |
6740 | .tcu_shscan_aclk (tcu_spc_shscan_aclk ), | |
6741 | .tcu_shscan_bclk (tcu_spc_shscan_bclk ), | |
6742 | .tcu_shscan_scan_en (tcu_spc_shscan_scan_en ), | |
6743 | .tcu_shscanid (tcu_spc_shscanid[ 2 : 0 ] ), | |
6744 | .tcu_shscan_scan_in (tcu_spc4_shscan_scan_out ), | |
6745 | .spc_shscan_scan_out (spc4_tcu_shscan_scan_in ), | |
6746 | .tcu_shscan_clk_stop (tcu_spc4_shscan_clk_stop ), | |
6747 | .efu_spc_fuse_data (efu_spc0246_fuse_data ), | |
6748 | .efu_spc_fuse_ixfer_en (efu_spc4_fuse_ixfer_en ), | |
6749 | .efu_spc_fuse_iclr (efu_spc4_fuse_iclr ), | |
6750 | .efu_spc_fuse_dxfer_en (efu_spc4_fuse_dxfer_en ), | |
6751 | .efu_spc_fuse_dclr (efu_spc4_fuse_dclr ), | |
6752 | .spc_efu_fuse_dxfer_en (spc4_efu_fuse_dxfer_en ), | |
6753 | .spc_efu_fuse_ixfer_en (spc4_efu_fuse_ixfer_en ), | |
6754 | .spc_efu_fuse_ddata (spc4_efu_fuse_ddata ), | |
6755 | .spc_efu_fuse_idata (spc4_efu_fuse_idata ), | |
6756 | .ccu_slow_cmp_sync_en ( gl_io_cmp_sync_en_c1t ), | |
6757 | .ccu_cmp_slow_sync_en ( gl_cmp_io_sync_en_c1t ), | |
6758 | .hver_mask_minor_rev (spc_revid_out[ 3 : 0 ] ), | |
6759 | .tcu_spc_test_mode (tcu_spc4_test_mode), | |
6760 | .tcu_pce_ov(tcu_pce_ov), | |
6761 | .tcu_dectest(tcu_dectest), | |
6762 | .tcu_muxtest(tcu_muxtest), | |
6763 | .tcu_atpg_mode(tcu_atpg_mode), | |
6764 | .rst_wmr_protect(rst_wmr_protect), | |
6765 | .cluster_arst_l(cluster_arst_l), | |
6766 | .tcu_mbist_bisi_en(tcu_mbist_bisi_en), | |
6767 | .tcu_mbist_user_mode(tcu_mbist_user_mode), | |
6768 | .ncu_cmp_tick_enable(ncu_cmp_tick_enable), | |
6769 | .ncu_wmr_vec_mask(ncu_wmr_vec_mask), | |
6770 | .ncu_spc_pm(ncu_spc_pm), | |
6771 | .ncu_spc_ba01(ncu_spc_ba01), | |
6772 | .ncu_spc_ba23(ncu_spc_ba23), | |
6773 | .ncu_spc_ba45(ncu_spc_ba45), | |
6774 | .ncu_spc_ba67(ncu_spc_ba67), | |
6775 | .tcu_spc_lbist_pgm(tcu_spc_lbist_pgm), | |
6776 | .dmo_icmuxctl(dmo_icmuxctl), | |
6777 | .dmo_dcmuxctl(dmo_dcmuxctl), | |
6778 | .ncu_spc_l2_idx_hash_en(ncu_spc_l2_idx_hash_en) | |
6779 | ); | |
6780 | `else | |
6781 | `ifndef CMP | |
6782 | assign spc4_pcx_req_pq[8:0] = 9'bz; | |
6783 | assign spc4_pcx_atm_pq[8:0] = 9'bz; | |
6784 | assign spc4_pcx_data_pa[129:0] = 130'bz; | |
6785 | assign spc4_tcu_scan_in[1:0] = 2'b0; | |
6786 | assign spc4_ncu_core_running_status[7:0] = 8'b0; | |
6787 | assign spc4_tcu_shscan_scan_in = 1'b0; | |
6788 | assign spc4_tcu_mbist_done = 1'b0; | |
6789 | assign spc4_tcu_mbist_fail = 1'b0; | |
6790 | assign spc4_tcu_mbist_scan_out = 1'b0; | |
6791 | assign spc4_dmo_dout = 36'b0; | |
6792 | assign spc4_tcu_lbist_done = 1'b0; | |
6793 | assign spc4_tcu_lbist_scan_out = 1'b0; | |
6794 | assign spc4_hardstop_request = 1'b0; | |
6795 | assign spc4_softstop_request = 1'b0; | |
6796 | assign spc4_trigger_pulse = 1'b0; | |
6797 | assign spc4_ss_complete = 1'b0; | |
6798 | assign spc4_dbg1_instr_cmt_grp0[1:0] = 2'b0; | |
6799 | assign spc4_dbg1_instr_cmt_grp1[1:0] = 2'b0; | |
6800 | assign spc4_efu_fuse_ddata =1'b0; | |
6801 | assign spc4_efu_fuse_dxfer_en =1'b0; | |
6802 | assign spc4_efu_fuse_idata =1'b0; | |
6803 | assign spc4_efu_fuse_ixfer_en =1'b0; | |
6804 | `endif | |
6805 | `endif | |
6806 | ||
6807 | ||
6808 | //________________________________________________________________ | |
6809 | ||
6810 | ||
6811 | `ifndef RTL_NO_SPC5 | |
6812 | spc spc5( | |
6813 | .vnw_ary0 (SPC_VNW[ 5 ]), | |
6814 | .vnw_ary1 (SPC_VNW[ 5 ]), | |
6815 | .gclk ( cmp_gclk_c2_spc5 ), // cmp_gclk_c2_r[1]) , | |
6816 | .tcu_clk_stop ( gl_spc5_clk_stop ), // staged clk_stop | |
6817 | ||
6818 | .cpx_spc_data_cx (cpx_spc5_data_cx2[ 145 : 0 ] ),// sparc core | |
6819 | .pcx_spc_grant_px (pcx_spc5_grant_px[ 8 : 0 ] ), | |
6820 | .spc_pcx_req_pq (spc5_pcx_req_pq[ 8 : 0 ] ), | |
6821 | .spc_pcx_atm_pq (spc5_pcx_atm_pq[ 8 : 0 ] ), | |
6822 | .spc_pcx_data_pa (spc5_pcx_data_pa[ 129 : 0 ] ), | |
6823 | .spc_hardstop_request (spc5_hardstop_request), | |
6824 | .spc_softstop_request (spc5_softstop_request), | |
6825 | .spc_trigger_pulse (spc5_trigger_pulse), | |
6826 | .tcu_ss_mode (tcu_ss_mode[ 5 ]), | |
6827 | .tcu_do_mode (tcu_do_mode[ 5 ]), | |
6828 | .tcu_ss_request (tcu_ss_request[ 5 ]), | |
6829 | .spc_ss_complete (spc5_ss_complete), | |
6830 | .tcu_aclk (tcu_spc5_aclk ), | |
6831 | .tcu_bclk (tcu_spc5_bclk ), | |
6832 | .tcu_scan_en (tcu_spc5_scan_en ), | |
6833 | .tcu_se_scancollar_in (tcu_spc5_se_scancollar_in ), | |
6834 | .tcu_se_scancollar_out (tcu_spc5_se_scancollar_out ), | |
6835 | .tcu_array_wr_inhibit (tcu_spc5_array_wr_inhibit ), | |
6836 | .tcu_core_running (ncu_spc5_core_running[ 7 : 0 ] ), | |
6837 | .spc_core_running_status (spc5_ncu_core_running_status[ 7 : 0 ]), | |
6838 | .const_cpuid ({1'b1, 1'b0, 1'b1} ),//No 3'b101 to Astro. | |
6839 | .power_throttle (mio_spc_pwr_throttle_0[ 2 : 0 ]), | |
6840 | .scan_out (spc5_tcu_scan_in[ 1 : 0 ] ), | |
6841 | .scan_in (tcu_spc5_scan_out[ 1 : 0 ] ), | |
6842 | .spc_dbg_instr_cmt_grp0 (spc5_dbg1_instr_cmt_grp0[ 1 : 0 ]), | |
6843 | .spc_dbg_instr_cmt_grp1 (spc5_dbg1_instr_cmt_grp1[ 1 : 0 ]), | |
6844 | .tcu_spc_mbist_start (tcu_spc_mbist_start[ 5 ] ), | |
6845 | .spc_mbist_done (spc5_tcu_mbist_done ), | |
6846 | .spc_mbist_fail (spc5_tcu_mbist_fail ), | |
6847 | .tcu_spc_mbist_scan_in (tcu_spc5_mbist_scan_in ), | |
6848 | .spc_tcu_mbist_scan_out (spc5_tcu_mbist_scan_out ), | |
6849 | .dmo_din (spc1_dmo_dout[ 35 : 0 ] ), | |
6850 | .dmo_dout (spc5_dmo_dout[ 35 : 0 ] ), | |
6851 | .dmo_coresel (dmo_coresel[ 4 ] ), | |
6852 | .tcu_spc_lbist_start (tcu_spc_lbist_start[ 5 ] ), | |
6853 | .tcu_spc_lbist_scan_in (tcu_spc_lbist_scan_in[ 5 ] ), | |
6854 | .spc_tcu_lbist_done (spc5_tcu_lbist_done ), | |
6855 | .spc_tcu_lbist_scan_out (spc5_tcu_lbist_scan_out ), | |
6856 | .tcu_shscan_pce_ov (tcu_spc_shscan_pce_ov ), | |
6857 | .tcu_shscan_aclk (tcu_spc_shscan_aclk ), | |
6858 | .tcu_shscan_bclk (tcu_spc_shscan_bclk ), | |
6859 | .tcu_shscan_scan_en (tcu_spc_shscan_scan_en ), | |
6860 | .tcu_shscanid (tcu_spc_shscanid[ 2 : 0 ] ), | |
6861 | .tcu_shscan_scan_in (tcu_spc5_shscan_scan_out ), | |
6862 | .spc_shscan_scan_out (spc5_tcu_shscan_scan_in ), | |
6863 | .tcu_shscan_clk_stop (tcu_spc5_shscan_clk_stop ), | |
6864 | .efu_spc_fuse_data (efu_spc1357_fuse_data ), | |
6865 | .efu_spc_fuse_ixfer_en (efu_spc5_fuse_ixfer_en ), | |
6866 | .efu_spc_fuse_iclr (efu_spc5_fuse_iclr ), | |
6867 | .efu_spc_fuse_dxfer_en (efu_spc5_fuse_dxfer_en ), | |
6868 | .efu_spc_fuse_dclr (efu_spc5_fuse_dclr ), | |
6869 | .spc_efu_fuse_dxfer_en (spc5_efu_fuse_dxfer_en ), | |
6870 | .spc_efu_fuse_ixfer_en (spc5_efu_fuse_ixfer_en ), | |
6871 | .spc_efu_fuse_ddata (spc5_efu_fuse_ddata ), | |
6872 | .spc_efu_fuse_idata (spc5_efu_fuse_idata ), | |
6873 | .ccu_slow_cmp_sync_en ( gl_io_cmp_sync_en_c2t ), | |
6874 | .ccu_cmp_slow_sync_en ( gl_cmp_io_sync_en_c2t ), | |
6875 | .hver_mask_minor_rev (spc_revid_out[ 3 : 0 ] ), | |
6876 | .tcu_spc_test_mode (tcu_spc5_test_mode), | |
6877 | .tcu_pce_ov(tcu_pce_ov), | |
6878 | .tcu_dectest(tcu_dectest), | |
6879 | .tcu_muxtest(tcu_muxtest), | |
6880 | .tcu_atpg_mode(tcu_atpg_mode), | |
6881 | .rst_wmr_protect(rst_wmr_protect), | |
6882 | .cluster_arst_l(cluster_arst_l), | |
6883 | .tcu_mbist_bisi_en(tcu_mbist_bisi_en), | |
6884 | .tcu_mbist_user_mode(tcu_mbist_user_mode), | |
6885 | .ncu_cmp_tick_enable(ncu_cmp_tick_enable), | |
6886 | .ncu_wmr_vec_mask(ncu_wmr_vec_mask), | |
6887 | .ncu_spc_pm(ncu_spc_pm), | |
6888 | .ncu_spc_ba01(ncu_spc_ba01), | |
6889 | .ncu_spc_ba23(ncu_spc_ba23), | |
6890 | .ncu_spc_ba45(ncu_spc_ba45), | |
6891 | .ncu_spc_ba67(ncu_spc_ba67), | |
6892 | .tcu_spc_lbist_pgm(tcu_spc_lbist_pgm), | |
6893 | .dmo_icmuxctl(dmo_icmuxctl), | |
6894 | .dmo_dcmuxctl(dmo_dcmuxctl), | |
6895 | .ncu_spc_l2_idx_hash_en(ncu_spc_l2_idx_hash_en) | |
6896 | ); | |
6897 | `else | |
6898 | `ifndef CMP | |
6899 | assign spc5_pcx_req_pq[8:0] = 9'bz; | |
6900 | assign spc5_pcx_atm_pq[8:0] = 9'bz; | |
6901 | assign spc5_pcx_data_pa[129:0] = 130'bz; | |
6902 | assign spc5_tcu_scan_in[1:0] = 2'b0; | |
6903 | assign spc5_ncu_core_running_status[7:0] = 8'b0; | |
6904 | assign spc5_tcu_shscan_scan_in = 1'b0; | |
6905 | assign spc5_tcu_mbist_done = 1'b0; | |
6906 | assign spc5_tcu_mbist_fail = 1'b0; | |
6907 | assign spc5_tcu_mbist_scan_out = 1'b0; | |
6908 | assign spc5_dmo_dout = 36'b0; | |
6909 | assign spc5_tcu_lbist_done = 1'b0; | |
6910 | assign spc5_tcu_lbist_scan_out = 1'b0; | |
6911 | assign spc5_hardstop_request = 1'b0; | |
6912 | assign spc5_softstop_request = 1'b0; | |
6913 | assign spc5_trigger_pulse = 1'b0; | |
6914 | assign spc5_ss_complete = 1'b0; | |
6915 | assign spc5_dbg1_instr_cmt_grp0[1:0] = 2'b0; | |
6916 | assign spc5_dbg1_instr_cmt_grp1[1:0] = 2'b0; | |
6917 | assign spc5_efu_fuse_ddata =1'b0; | |
6918 | assign spc5_efu_fuse_dxfer_en =1'b0; | |
6919 | assign spc5_efu_fuse_idata =1'b0; | |
6920 | assign spc5_efu_fuse_ixfer_en =1'b0; | |
6921 | `endif | |
6922 | `endif | |
6923 | ||
6924 | ||
6925 | //________________________________________________________________ | |
6926 | ||
6927 | ||
6928 | `ifndef RTL_NO_SPC6 | |
6929 | spc spc6( | |
6930 | .vnw_ary0 (SPC_VNW[ 6 ]), | |
6931 | .vnw_ary1 (SPC_VNW[ 6 ]), | |
6932 | .gclk ( cmp_gclk_c1_spc6 ), // cmp_gclk_c2_r[6]) , | |
6933 | .tcu_clk_stop ( gl_spc6_clk_stop ), // staged clk_stop | |
6934 | ||
6935 | .cpx_spc_data_cx (cpx_spc6_data_cx2[ 145 : 0 ] ),// sparc core | |
6936 | .pcx_spc_grant_px (pcx_spc6_grant_px[ 8 : 0 ] ), | |
6937 | .spc_pcx_req_pq (spc6_pcx_req_pq[ 8 : 0 ] ), | |
6938 | .spc_pcx_atm_pq (spc6_pcx_atm_pq[ 8 : 0 ] ), | |
6939 | .spc_pcx_data_pa (spc6_pcx_data_pa[ 129 : 0 ] ), | |
6940 | .spc_hardstop_request (spc6_hardstop_request), | |
6941 | .spc_softstop_request (spc6_softstop_request), | |
6942 | .spc_trigger_pulse (spc6_trigger_pulse), | |
6943 | .tcu_ss_mode (tcu_ss_mode[ 6 ]), | |
6944 | .tcu_do_mode (tcu_do_mode[ 6 ]), | |
6945 | .tcu_ss_request (tcu_ss_request[ 6 ]), | |
6946 | .spc_ss_complete (spc6_ss_complete), | |
6947 | .tcu_aclk (tcu_spc6_aclk ), | |
6948 | .tcu_bclk (tcu_spc6_bclk ), | |
6949 | .tcu_scan_en (tcu_spc6_scan_en ), | |
6950 | .tcu_se_scancollar_in (tcu_spc6_se_scancollar_in ), | |
6951 | .tcu_se_scancollar_out (tcu_spc6_se_scancollar_out ), | |
6952 | .tcu_array_wr_inhibit (tcu_spc6_array_wr_inhibit ), | |
6953 | .tcu_core_running (ncu_spc6_core_running[ 7 : 0 ] ), | |
6954 | .spc_core_running_status (spc6_ncu_core_running_status[ 7 : 0 ]), | |
6955 | .const_cpuid ({1'b1, 1'b1, 1'b0} ),//No 3'b101 to Astro. | |
6956 | .power_throttle (mio_spc_pwr_throttle_1[ 2 : 0 ]), | |
6957 | .scan_out (spc6_tcu_scan_in[ 1 : 0 ] ), | |
6958 | .scan_in (tcu_spc6_scan_out[ 1 : 0 ] ), | |
6959 | .spc_dbg_instr_cmt_grp0 (spc6_dbg1_instr_cmt_grp0[ 1 : 0 ]), | |
6960 | .spc_dbg_instr_cmt_grp1 (spc6_dbg1_instr_cmt_grp1[ 1 : 0 ]), | |
6961 | .tcu_spc_mbist_start (tcu_spc_mbist_start[ 6 ] ), | |
6962 | .spc_mbist_done (spc6_tcu_mbist_done ), | |
6963 | .spc_mbist_fail (spc6_tcu_mbist_fail ), | |
6964 | .tcu_spc_mbist_scan_in (tcu_spc6_mbist_scan_in ), | |
6965 | .spc_tcu_mbist_scan_out (spc6_tcu_mbist_scan_out ), | |
6966 | .dmo_din (spc7_dmo_dout[ 35 : 0 ] ), | |
6967 | .dmo_dout (spc6_dmo_dout[ 35 : 0 ] ), | |
6968 | .dmo_coresel (dmo_coresel[ 0 ] ), | |
6969 | .tcu_spc_lbist_start (tcu_spc_lbist_start[ 6 ] ), | |
6970 | .tcu_spc_lbist_scan_in (tcu_spc_lbist_scan_in[ 6 ] ), | |
6971 | .spc_tcu_lbist_done (spc6_tcu_lbist_done ), | |
6972 | .spc_tcu_lbist_scan_out (spc6_tcu_lbist_scan_out ), | |
6973 | .tcu_shscan_pce_ov (tcu_spc_shscan_pce_ov ), | |
6974 | .tcu_shscan_aclk (tcu_spc_shscan_aclk ), | |
6975 | .tcu_shscan_bclk (tcu_spc_shscan_bclk ), | |
6976 | .tcu_shscan_scan_en (tcu_spc_shscan_scan_en ), | |
6977 | .tcu_shscanid (tcu_spc_shscanid[ 2 : 0 ] ), | |
6978 | .tcu_shscan_scan_in (tcu_spc6_shscan_scan_out ), | |
6979 | .spc_shscan_scan_out (spc6_tcu_shscan_scan_in ), | |
6980 | .tcu_shscan_clk_stop (tcu_spc6_shscan_clk_stop ), | |
6981 | .efu_spc_fuse_data (efu_spc0246_fuse_data ), | |
6982 | .efu_spc_fuse_ixfer_en (efu_spc6_fuse_ixfer_en ), | |
6983 | .efu_spc_fuse_iclr (efu_spc6_fuse_iclr ), | |
6984 | .efu_spc_fuse_dxfer_en (efu_spc6_fuse_dxfer_en ), | |
6985 | .efu_spc_fuse_dclr (efu_spc6_fuse_dclr ), | |
6986 | .spc_efu_fuse_dxfer_en (spc6_efu_fuse_dxfer_en ), | |
6987 | .spc_efu_fuse_ixfer_en (spc6_efu_fuse_ixfer_en ), | |
6988 | .spc_efu_fuse_ddata (spc6_efu_fuse_ddata ), | |
6989 | .spc_efu_fuse_idata (spc6_efu_fuse_idata ), | |
6990 | .ccu_slow_cmp_sync_en (gl_io_cmp_sync_en_c1b ), | |
6991 | .ccu_cmp_slow_sync_en (gl_cmp_io_sync_en_c1b ), | |
6992 | .hver_mask_minor_rev (spc_revid_out[ 3 : 0 ] ), | |
6993 | .tcu_spc_test_mode (tcu_spc6_test_mode), | |
6994 | .tcu_pce_ov(tcu_pce_ov), | |
6995 | .tcu_dectest(tcu_dectest), | |
6996 | .tcu_muxtest(tcu_muxtest), | |
6997 | .tcu_atpg_mode(tcu_atpg_mode), | |
6998 | .rst_wmr_protect(rst_wmr_protect), | |
6999 | .cluster_arst_l(cluster_arst_l), | |
7000 | .tcu_mbist_bisi_en(tcu_mbist_bisi_en), | |
7001 | .tcu_mbist_user_mode(tcu_mbist_user_mode), | |
7002 | .ncu_cmp_tick_enable(ncu_cmp_tick_enable), | |
7003 | .ncu_wmr_vec_mask(ncu_wmr_vec_mask), | |
7004 | .ncu_spc_pm(ncu_spc_pm), | |
7005 | .ncu_spc_ba01(ncu_spc_ba01), | |
7006 | .ncu_spc_ba23(ncu_spc_ba23), | |
7007 | .ncu_spc_ba45(ncu_spc_ba45), | |
7008 | .ncu_spc_ba67(ncu_spc_ba67), | |
7009 | .tcu_spc_lbist_pgm(tcu_spc_lbist_pgm), | |
7010 | .dmo_icmuxctl(dmo_icmuxctl), | |
7011 | .dmo_dcmuxctl(dmo_dcmuxctl), | |
7012 | .ncu_spc_l2_idx_hash_en(ncu_spc_l2_idx_hash_en) | |
7013 | ); | |
7014 | `else | |
7015 | `ifndef CMP | |
7016 | assign spc6_pcx_req_pq[8:0] = 9'bz; | |
7017 | assign spc6_pcx_atm_pq[8:0] = 9'bz; | |
7018 | assign spc6_pcx_data_pa[129:0] = 130'bz; | |
7019 | assign spc6_tcu_scan_in[1:0] = 2'b0; | |
7020 | assign spc6_ncu_core_running_status[7:0] = 8'b0; | |
7021 | assign spc6_tcu_shscan_scan_in = 1'b0; | |
7022 | assign spc6_tcu_mbist_done = 1'b0; | |
7023 | assign spc6_tcu_mbist_fail = 1'b0; | |
7024 | assign spc6_tcu_mbist_scan_out = 1'b0; | |
7025 | assign spc6_dmo_dout = 36'b0; | |
7026 | assign spc6_tcu_lbist_done = 1'b0; | |
7027 | assign spc6_tcu_lbist_scan_out = 1'b0; | |
7028 | assign spc6_hardstop_request = 1'b0; | |
7029 | assign spc6_softstop_request = 1'b0; | |
7030 | assign spc6_trigger_pulse = 1'b0; | |
7031 | assign spc6_ss_complete = 1'b0; | |
7032 | assign spc6_dbg1_instr_cmt_grp0[1:0] = 2'b0; | |
7033 | assign spc6_dbg1_instr_cmt_grp1[1:0] = 2'b0; | |
7034 | assign spc6_efu_fuse_ddata =1'b0; | |
7035 | assign spc6_efu_fuse_dxfer_en =1'b0; | |
7036 | assign spc6_efu_fuse_idata =1'b0; | |
7037 | assign spc6_efu_fuse_ixfer_en =1'b0; | |
7038 | `endif | |
7039 | `endif | |
7040 | ||
7041 | ||
7042 | //________________________________________________________________ | |
7043 | ||
7044 | ||
7045 | `ifndef RTL_NO_SPC7 | |
7046 | spc spc7( | |
7047 | .vnw_ary0 (SPC_VNW[ 7 ]), | |
7048 | .vnw_ary1 (SPC_VNW[ 7 ]), | |
7049 | .gclk ( cmp_gclk_c2_spc7 ), // cmp_gclk_c2_r[6]) , | |
7050 | .tcu_clk_stop ( gl_spc7_clk_stop ), // staged clk_stop | |
7051 | ||
7052 | .cpx_spc_data_cx (cpx_spc7_data_cx2[ 145 : 0 ] ),// sparc core | |
7053 | .pcx_spc_grant_px (pcx_spc7_grant_px[ 8 : 0 ] ), | |
7054 | .spc_pcx_req_pq (spc7_pcx_req_pq[ 8 : 0 ] ), | |
7055 | .spc_pcx_atm_pq (spc7_pcx_atm_pq[ 8 : 0 ] ), | |
7056 | .spc_pcx_data_pa (spc7_pcx_data_pa[ 129 : 0 ] ), | |
7057 | .spc_hardstop_request (spc7_hardstop_request), | |
7058 | .spc_softstop_request (spc7_softstop_request), | |
7059 | .spc_trigger_pulse (spc7_trigger_pulse), | |
7060 | .tcu_ss_mode (tcu_ss_mode[ 7 ]), | |
7061 | .tcu_do_mode (tcu_do_mode[ 7 ]), | |
7062 | .tcu_ss_request (tcu_ss_request[ 7 ]), | |
7063 | .spc_ss_complete (spc7_ss_complete), | |
7064 | .tcu_aclk (tcu_spc7_aclk ), | |
7065 | .tcu_bclk (tcu_spc7_bclk ), | |
7066 | .tcu_scan_en (tcu_spc7_scan_en ), | |
7067 | .tcu_se_scancollar_in (tcu_spc7_se_scancollar_in ), | |
7068 | .tcu_se_scancollar_out (tcu_spc7_se_scancollar_out ), | |
7069 | .tcu_array_wr_inhibit (tcu_spc7_array_wr_inhibit ), | |
7070 | .tcu_core_running (ncu_spc7_core_running[ 7 : 0 ] ), | |
7071 | .spc_core_running_status (spc7_ncu_core_running_status[ 7 : 0 ]), | |
7072 | .const_cpuid ({1'b1, 1'b1, 1'b1} ),//No 3'b101 to Astro. | |
7073 | .power_throttle (mio_spc_pwr_throttle_1[ 2 : 0 ]), | |
7074 | .scan_out (spc7_tcu_scan_in[ 1 : 0 ] ), | |
7075 | .scan_in (tcu_spc7_scan_out[ 1 : 0 ] ), | |
7076 | .spc_dbg_instr_cmt_grp0 (spc7_dbg1_instr_cmt_grp0[ 1 : 0 ]), | |
7077 | .spc_dbg_instr_cmt_grp1 (spc7_dbg1_instr_cmt_grp1[ 1 : 0 ]), | |
7078 | .tcu_spc_mbist_start (tcu_spc_mbist_start[ 7 ] ), | |
7079 | .spc_mbist_done (spc7_tcu_mbist_done ), | |
7080 | .spc_mbist_fail (spc7_tcu_mbist_fail ), | |
7081 | .tcu_spc_mbist_scan_in (tcu_spc7_mbist_scan_in ), | |
7082 | .spc_tcu_mbist_scan_out (spc7_tcu_mbist_scan_out ), | |
7083 | .dmo_din (spc3_dmo_dout[ 35 : 0 ] ), | |
7084 | .dmo_dout (spc7_dmo_dout[ 35 : 0 ] ), | |
7085 | .dmo_coresel (dmo_coresel[ 1 ] ), | |
7086 | .tcu_spc_lbist_start (tcu_spc_lbist_start[ 7 ] ), | |
7087 | .tcu_spc_lbist_scan_in (tcu_spc_lbist_scan_in[ 7 ] ), | |
7088 | .spc_tcu_lbist_done (spc7_tcu_lbist_done ), | |
7089 | .spc_tcu_lbist_scan_out (spc7_tcu_lbist_scan_out ), | |
7090 | .tcu_shscan_pce_ov (tcu_spc_shscan_pce_ov ), | |
7091 | .tcu_shscan_aclk (tcu_spc_shscan_aclk ), | |
7092 | .tcu_shscan_bclk (tcu_spc_shscan_bclk ), | |
7093 | .tcu_shscan_scan_en (tcu_spc_shscan_scan_en ), | |
7094 | .tcu_shscanid (tcu_spc_shscanid[ 2 : 0 ] ), | |
7095 | .tcu_shscan_scan_in (tcu_spc7_shscan_scan_out ), | |
7096 | .spc_shscan_scan_out (spc7_tcu_shscan_scan_in ), | |
7097 | .tcu_shscan_clk_stop (tcu_spc7_shscan_clk_stop ), | |
7098 | .efu_spc_fuse_data (efu_spc1357_fuse_data ), | |
7099 | .efu_spc_fuse_ixfer_en (efu_spc7_fuse_ixfer_en ), | |
7100 | .efu_spc_fuse_iclr (efu_spc7_fuse_iclr ), | |
7101 | .efu_spc_fuse_dxfer_en (efu_spc7_fuse_dxfer_en ), | |
7102 | .efu_spc_fuse_dclr (efu_spc7_fuse_dclr ), | |
7103 | .spc_efu_fuse_dxfer_en (spc7_efu_fuse_dxfer_en ), | |
7104 | .spc_efu_fuse_ixfer_en (spc7_efu_fuse_ixfer_en ), | |
7105 | .spc_efu_fuse_ddata (spc7_efu_fuse_ddata ), | |
7106 | .spc_efu_fuse_idata (spc7_efu_fuse_idata ), | |
7107 | .ccu_slow_cmp_sync_en ( gl_io_cmp_sync_en_c2b ), | |
7108 | .ccu_cmp_slow_sync_en ( gl_cmp_io_sync_en_c2b ), | |
7109 | .hver_mask_minor_rev (spc_revid_out[ 3 : 0 ] ), | |
7110 | .tcu_spc_test_mode (tcu_spc7_test_mode), | |
7111 | .tcu_pce_ov(tcu_pce_ov), | |
7112 | .tcu_dectest(tcu_dectest), | |
7113 | .tcu_muxtest(tcu_muxtest), | |
7114 | .tcu_atpg_mode(tcu_atpg_mode), | |
7115 | .rst_wmr_protect(rst_wmr_protect), | |
7116 | .cluster_arst_l(cluster_arst_l), | |
7117 | .tcu_mbist_bisi_en(tcu_mbist_bisi_en), | |
7118 | .tcu_mbist_user_mode(tcu_mbist_user_mode), | |
7119 | .ncu_cmp_tick_enable(ncu_cmp_tick_enable), | |
7120 | .ncu_wmr_vec_mask(ncu_wmr_vec_mask), | |
7121 | .ncu_spc_pm(ncu_spc_pm), | |
7122 | .ncu_spc_ba01(ncu_spc_ba01), | |
7123 | .ncu_spc_ba23(ncu_spc_ba23), | |
7124 | .ncu_spc_ba45(ncu_spc_ba45), | |
7125 | .ncu_spc_ba67(ncu_spc_ba67), | |
7126 | .tcu_spc_lbist_pgm(tcu_spc_lbist_pgm), | |
7127 | .dmo_icmuxctl(dmo_icmuxctl), | |
7128 | .dmo_dcmuxctl(dmo_dcmuxctl), | |
7129 | .ncu_spc_l2_idx_hash_en(ncu_spc_l2_idx_hash_en) | |
7130 | ); | |
7131 | `else | |
7132 | `ifndef CMP | |
7133 | assign spc7_pcx_req_pq[8:0] = 9'bz; | |
7134 | assign spc7_pcx_atm_pq[8:0] = 9'bz; | |
7135 | assign spc7_pcx_data_pa[129:0] = 130'bz; | |
7136 | assign spc7_tcu_scan_in[1:0] = 2'b0; | |
7137 | assign spc7_ncu_core_running_status[7:0] = 8'b0; | |
7138 | assign spc7_tcu_shscan_scan_in = 1'b0; | |
7139 | assign spc7_tcu_mbist_done = 1'b0; | |
7140 | assign spc7_tcu_mbist_fail = 1'b0; | |
7141 | assign spc7_tcu_mbist_scan_out = 1'b0; | |
7142 | assign spc7_dmo_dout = 36'b0; | |
7143 | assign spc7_tcu_lbist_done = 1'b0; | |
7144 | assign spc7_tcu_lbist_scan_out = 1'b0; | |
7145 | assign spc7_hardstop_request = 1'b0; | |
7146 | assign spc7_softstop_request = 1'b0; | |
7147 | assign spc7_trigger_pulse = 1'b0; | |
7148 | assign spc7_ss_complete = 1'b0; | |
7149 | assign spc7_dbg1_instr_cmt_grp0[1:0] = 2'b0; | |
7150 | assign spc7_dbg1_instr_cmt_grp1[1:0] = 2'b0; | |
7151 | assign spc7_efu_fuse_ddata =1'b0; | |
7152 | assign spc7_efu_fuse_dxfer_en =1'b0; | |
7153 | assign spc7_efu_fuse_idata =1'b0; | |
7154 | assign spc7_efu_fuse_ixfer_en =1'b0; | |
7155 | `endif | |
7156 | `endif | |
7157 | ||
7158 | ||
7159 | ||
7160 | //________________________________________________________________ | |
7161 | ||
7162 | ||
7163 | ||
7164 | //// stagging flops | |
7165 | ||
7166 | //assign | |
7167 | ||
7168 | ccx ccx( | |
7169 | ||
7170 | // .gclk ( cmp_gclk_c2_ccx_right ), // cmp_gclk_c1_r[3]) , | |
7171 | .gl_ccx_clk_stop_left ( gl_ccx_clk_stop ), | |
7172 | .gl_ccx_clk_stop_right ( gl_ccx_clk_stop ), | |
7173 | .scan_in (tcu_ccx_scan_out[ 1 : 0 ] ), | |
7174 | .scan_out (ccx_scan_out[ 1 : 0 ] ), | |
7175 | .io_cpx_req_cq (ncu_cpx_req_cq[ 7 : 0 ] ), | |
7176 | .cpx_io_grant_cx (cpx_ncu_grant_cx[ 7 : 0 ] ), | |
7177 | .io_cpx_data_ca ({ncu_cpx_data_ca[ 145 : 0 ]}), | |
7178 | .io_pcx_stall_pq (ncu_pcx_stall_pq ), | |
7179 | .pcx_fpio_data_px2 (pcx_ncu_data_px2[ 129 : 0 ] ), | |
7180 | .sctag0_cpx_data_ca ({sctag0_cpx_data_ca[ 145 : 0 ]}), | |
7181 | .sctag1_cpx_data_ca ({sctag1_cpx_data_ca[ 145 : 0 ]}), | |
7182 | .sctag2_cpx_data_ca ({sctag2_cpx_data_ca[ 145 : 0 ]}), | |
7183 | .sctag3_cpx_data_ca ({sctag3_cpx_data_ca[ 145 : 0 ]}), | |
7184 | .sctag4_cpx_data_ca ({sctag4_cpx_data_ca[ 145 : 0 ]}), | |
7185 | .sctag5_cpx_data_ca ({sctag5_cpx_data_ca[ 145 : 0 ]}), | |
7186 | .sctag6_cpx_data_ca ({sctag6_cpx_data_ca[ 145 : 0 ]}), | |
7187 | .sctag7_cpx_data_ca ({sctag7_cpx_data_ca[ 145 : 0 ]}), | |
7188 | .pcx_fpio_data_rdy_px1 (pcx_ncu_data_rdy_px1 ), | |
7189 | //// .tcu_clk_stop (tcu_soc4cmp_clk_stop ), | |
7190 | ||
7191 | .ccx_lstg_in ( | |
7192 | {dbg0_dbg1_l2b0_sio_ack_dest, | |
7193 | dbg0_dbg1_l2b0_sio_ack_type, | |
7194 | dbg0_dbg1_l2b0_sio_ctag_vld, | |
7195 | dbg0_dbg1_l2b1_sio_ack_dest, | |
7196 | dbg0_dbg1_l2b1_sio_ack_type, | |
7197 | dbg0_dbg1_l2b1_sio_ctag_vld, | |
7198 | dbg0_dbg1_l2b2_sio_ack_dest, | |
7199 | dbg0_dbg1_l2b2_sio_ack_type, | |
7200 | dbg0_dbg1_l2b2_sio_ctag_vld, | |
7201 | dbg0_dbg1_l2b3_sio_ack_dest, | |
7202 | dbg0_dbg1_l2b3_sio_ack_type, | |
7203 | dbg0_dbg1_l2b3_sio_ctag_vld, | |
7204 | dbg0_dbg1_l2t0_err_event, | |
7205 | dbg0_dbg1_l2t0_pa_match, | |
7206 | dbg0_dbg1_l2t0_sii_iq_dequeue, | |
7207 | dbg0_dbg1_l2t0_sii_wib_dequeue, | |
7208 | dbg0_dbg1_l2t0_xbar_vcid[ 5 : 0 ], | |
7209 | dbg0_dbg1_l2t2_err_event, | |
7210 | dbg0_dbg1_l2t2_pa_match, | |
7211 | dbg0_dbg1_l2t2_sii_iq_dequeue, | |
7212 | dbg0_dbg1_l2t2_sii_wib_dequeue, | |
7213 | dbg0_dbg1_l2t2_xbar_vcid[ 5 : 0 ], | |
7214 | dbg0_dbg1_spc0_instr_cmt_grp0[ 0 ], | |
7215 | dbg0_dbg1_spc0_instr_cmt_grp0[ 1 ], | |
7216 | dbg0_dbg1_spc0_instr_cmt_grp1[ 0 ], | |
7217 | dbg0_dbg1_spc0_instr_cmt_grp1[ 1 ], | |
7218 | dbg0_dbg1_spc2_instr_cmt_grp0[ 0 ], | |
7219 | dbg0_dbg1_spc2_instr_cmt_grp0[ 1 ], | |
7220 | dbg0_dbg1_spc2_instr_cmt_grp1[ 0 ], | |
7221 | dbg0_dbg1_spc2_instr_cmt_grp1[ 1 ], | |
7222 | l2b1_sio_data[ 31 : 0 ], | |
7223 | l2b1_sio_parity[ 1 : 0 ], | |
7224 | l2b1_sio_ctag_vld, | |
7225 | l2b1_sio_ue_err, | |
7226 | l2b2_sio_data[ 31 : 0 ], | |
7227 | l2b2_sio_parity[ 1 : 0 ], | |
7228 | l2b2_sio_ctag_vld, | |
7229 | l2b2_sio_ue_err, | |
7230 | l2b3_sio_data[ 31 : 0 ], | |
7231 | l2b3_sio_parity[ 1 : 0 ], | |
7232 | l2b3_sio_ctag_vld, | |
7233 | l2b3_sio_ue_err, | |
7234 | l2b0_tcu_mbist_done, | |
7235 | l2b0_tcu_mbist_fail, | |
7236 | tcu_l2b0_mbist_start, | |
7237 | l2b1_tcu_mbist_done, | |
7238 | l2b1_tcu_mbist_fail, | |
7239 | tcu_l2b1_mbist_start, | |
7240 | l2b2_tcu_mbist_done, | |
7241 | l2b2_tcu_mbist_fail, | |
7242 | tcu_l2b2_mbist_start, | |
7243 | l2b3_tcu_mbist_done, | |
7244 | l2b3_tcu_mbist_fail, | |
7245 | tcu_l2b3_mbist_start | |
7246 | } | |
7247 | ), | |
7248 | .ccx_lstg_out ( | |
7249 | {dbg0_dbg1_l2b0_sio_ack_dest_ccxlff, | |
7250 | dbg0_dbg1_l2b0_sio_ack_type_ccxlff, | |
7251 | dbg0_dbg1_l2b0_sio_ctag_vld_ccxlff, | |
7252 | dbg0_dbg1_l2b1_sio_ack_dest_ccxlff, | |
7253 | dbg0_dbg1_l2b1_sio_ack_type_ccxlff, | |
7254 | dbg0_dbg1_l2b1_sio_ctag_vld_ccxlff, | |
7255 | dbg0_dbg1_l2b2_sio_ack_dest_ccxlff, | |
7256 | dbg0_dbg1_l2b2_sio_ack_type_ccxlff, | |
7257 | dbg0_dbg1_l2b2_sio_ctag_vld_ccxlff, | |
7258 | dbg0_dbg1_l2b3_sio_ack_dest_ccxlff, | |
7259 | dbg0_dbg1_l2b3_sio_ack_type_ccxlff, | |
7260 | dbg0_dbg1_l2b3_sio_ctag_vld_ccxlff, | |
7261 | dbg0_dbg1_l2t0_err_event_ccxlff, | |
7262 | dbg0_dbg1_l2t0_pa_match_ccxlff, | |
7263 | dbg0_dbg1_l2t0_sii_iq_dequeue_ccxlff, | |
7264 | dbg0_dbg1_l2t0_sii_wib_dequeue_ccxlff, | |
7265 | dbg0_dbg1_l2t0_xbar_vcid_ccxlff[ 5 : 0 ], | |
7266 | dbg0_dbg1_l2t2_err_event_ccxlff, | |
7267 | dbg0_dbg1_l2t2_pa_match_ccxlff, | |
7268 | dbg0_dbg1_l2t2_sii_iq_dequeue_ccxlff, | |
7269 | dbg0_dbg1_l2t2_sii_wib_dequeue_ccxlff, | |
7270 | dbg0_dbg1_l2t2_xbar_vcid_ccxlff[ 5 : 0 ], | |
7271 | dbg0_dbg1_spc0_instr_cmt_grp0_ccxlff_0, | |
7272 | dbg0_dbg1_spc0_instr_cmt_grp0_ccxlff_1, | |
7273 | dbg0_dbg1_spc0_instr_cmt_grp1_ccxlff_0, | |
7274 | dbg0_dbg1_spc0_instr_cmt_grp1_ccxlff_1, | |
7275 | dbg0_dbg1_spc2_instr_cmt_grp0_ccxlff_0, | |
7276 | dbg0_dbg1_spc2_instr_cmt_grp0_ccxlff_1, | |
7277 | dbg0_dbg1_spc2_instr_cmt_grp1_ccxlff_0, | |
7278 | dbg0_dbg1_spc2_instr_cmt_grp1_ccxlff_1, | |
7279 | l2b1_sio_data_ccxlff[ 31 : 0 ], | |
7280 | l2b1_sio_parity_ccxlff[ 1 : 0 ], | |
7281 | l2b1_sio_ctag_vld_ccxlff, | |
7282 | l2b1_sio_ue_err_ccxlff, | |
7283 | l2b2_sio_data_ccxlff[ 31 : 0 ], | |
7284 | l2b2_sio_parity_ccxlff[ 1 : 0 ], | |
7285 | l2b2_sio_ctag_vld_ccxlff, | |
7286 | l2b2_sio_ue_err_ccxlff, | |
7287 | l2b3_sio_data_ccxlff[ 31 : 0 ], | |
7288 | l2b3_sio_parity_ccxlff[ 1 : 0 ], | |
7289 | l2b3_sio_ctag_vld_ccxlff, | |
7290 | l2b3_sio_ue_err_ccxlff, | |
7291 | l2b0_tcu_mbist_done_ccxlff, | |
7292 | l2b0_tcu_mbist_fail_ccxlff, | |
7293 | tcu_l2b0_mbist_start_ccxlff, | |
7294 | l2b1_tcu_mbist_done_ccxlff, | |
7295 | l2b1_tcu_mbist_fail_ccxlff, | |
7296 | tcu_l2b1_mbist_start_ccxlff, | |
7297 | l2b2_tcu_mbist_done_ccxlff, | |
7298 | l2b2_tcu_mbist_fail_ccxlff, | |
7299 | tcu_l2b2_mbist_start_ccxlff, | |
7300 | l2b3_tcu_mbist_done_ccxlff, | |
7301 | l2b3_tcu_mbist_fail_ccxlff, | |
7302 | tcu_l2b3_mbist_start_ccxlff | |
7303 | } | |
7304 | ), | |
7305 | .ccx_rstg_in ( | |
7306 | {5'b0, | |
7307 | sii_l2b5_ecc[ 6 : 5 ], | |
7308 | 4'b0, | |
7309 | sii_l2b5_ecc[ 4 : 3 ], | |
7310 | 4'b0, | |
7311 | sii_l2b5_ecc[ 2 : 1 ], | |
7312 | 4'b0, | |
7313 | sii_l2b5_ecc[ 0 ], | |
7314 | 4'b0, | |
7315 | sii_dbg1_l2t0_req[ 1 : 0 ], | |
7316 | 4'b0, | |
7317 | sii_dbg1_l2t1_req[ 1 : 0 ], | |
7318 | 4'b0, | |
7319 | sii_dbg1_l2t2_req[ 1 : 0 ], | |
7320 | 4'b0, | |
7321 | sii_dbg1_l2t3_req[ 1 : 0 ], | |
7322 | 4'b0, | |
7323 | sii_dbg1_l2t4_req[ 1 : 0 ], | |
7324 | 4'b0, | |
7325 | sii_dbg1_l2t5_req[ 1 : 0 ], | |
7326 | 4'b0, | |
7327 | sii_dbg1_l2t6_req[ 1 : 0 ], | |
7328 | 4'b0, | |
7329 | sii_dbg1_l2t7_req[ 1 : 0 ], | |
7330 | 13'b0, | |
7331 | sii_tcu_mbist_done[ 1 : 0 ], | |
7332 | 4'b0, | |
7333 | sii_tcu_mbist_fail[ 1 : 0 ], | |
7334 | 4'b0, | |
7335 | tcu_sii_mbist_start[ 1 : 0 ], | |
7336 | 4'b0, | |
7337 | tcu_sii_data, | |
7338 | tcu_sii_vld, | |
7339 | 13'b0, | |
7340 | sii_l2b6_ecc[ 0 ], | |
7341 | 4'b0, | |
7342 | sii_l2b6_ecc[ 2 : 1 ], | |
7343 | 4'b0, | |
7344 | sii_l2b6_ecc[ 4 : 3 ], | |
7345 | 4'b0, | |
7346 | sii_l2b6_ecc[ 6 : 5 ], | |
7347 | 4'b0, | |
7348 | sii_l2b7_ecc[ 0 ], | |
7349 | 4'b0, | |
7350 | sii_l2b7_ecc[ 2 : 1 ], | |
7351 | 4'b0, | |
7352 | sii_l2b7_ecc[ 4 : 3 ], | |
7353 | 4'b0, | |
7354 | sii_l2b7_ecc[ 6 : 5 ] | |
7355 | } | |
7356 | ), | |
7357 | .ccx_rstg_out ( | |
7358 | {ccx_rstg_out_unconnected[ 159 : 155 ], | |
7359 | sii_l2b5_ecc_ccxrff[ 6 : 5 ], | |
7360 | ccx_rstg_out_unconnected[ 152 : 149 ], | |
7361 | sii_l2b5_ecc_ccxrff[ 4 : 3 ], | |
7362 | ccx_rstg_out_unconnected[ 146 : 143 ], | |
7363 | sii_l2b5_ecc_ccxrff[ 2 : 1 ], | |
7364 | ccx_rstg_out_unconnected[ 140 : 137 ], | |
7365 | sii_l2b5_ecc_ccxrff[ 0 ], | |
7366 | ccx_rstg_out_unconnected[ 135 : 132 ], | |
7367 | sii_dbg1_l2t0_req_ccxrff[ 1 : 0 ], | |
7368 | ccx_rstg_out_unconnected[ 129 : 126 ], | |
7369 | sii_dbg1_l2t1_req_ccxrff[ 1 : 0 ], | |
7370 | ccx_rstg_out_unconnected[ 123 : 120 ], | |
7371 | sii_dbg1_l2t2_req_ccxrff[ 1 : 0 ], | |
7372 | ccx_rstg_out_unconnected[ 117 : 114 ], | |
7373 | sii_dbg1_l2t3_req_ccxrff[ 1 : 0 ], | |
7374 | ccx_rstg_out_unconnected[ 111 : 108 ], | |
7375 | sii_dbg1_l2t4_req_ccxrff[ 1 : 0 ], | |
7376 | ccx_rstg_out_unconnected[ 105 : 102 ], | |
7377 | sii_dbg1_l2t5_req_ccxrff[ 1 : 0 ], | |
7378 | ccx_rstg_out_unconnected[ 99 : 96 ], | |
7379 | sii_dbg1_l2t6_req_ccxrff[ 1 : 0 ], | |
7380 | ccx_rstg_out_unconnected[ 93 : 90 ], | |
7381 | sii_dbg1_l2t7_req_ccxrff[ 1 : 0 ], | |
7382 | ccx_rstg_out_unconnected[ 87 : 75 ], | |
7383 | sii_tcu_mbist_done_ccxrff_1, | |
7384 | sii_tcu_mbist_done_ccxrff_0, | |
7385 | ccx_rstg_out_unconnected[ 72 : 69 ], | |
7386 | sii_tcu_mbist_fail_ccxrff_1, | |
7387 | sii_tcu_mbist_fail_ccxrff_0, | |
7388 | ccx_rstg_out_unconnected[ 66 : 63 ], | |
7389 | tcu_sii_mbist_start_ccxrff_1, | |
7390 | tcu_sii_mbist_start_ccxrff_0, | |
7391 | ccx_rstg_out_unconnected[ 60 : 57 ], | |
7392 | tcu_sii_data_ccxrff, | |
7393 | tcu_sii_vld_ccxrff, | |
7394 | ccx_rstg_out_unconnected[ 54 : 42 ], | |
7395 | sii_l2b6_ecc_ccxrff[ 0 ], | |
7396 | ccx_rstg_out_unconnected[ 40 : 37 ], | |
7397 | sii_l2b6_ecc_ccxrff[ 2 : 1 ], | |
7398 | ccx_rstg_out_unconnected[ 34 : 31 ], | |
7399 | sii_l2b6_ecc_ccxrff[ 4 : 3 ], | |
7400 | ccx_rstg_out_unconnected[ 28 : 25 ], | |
7401 | sii_l2b6_ecc_ccxrff[ 6 : 5 ], | |
7402 | ccx_rstg_out_unconnected[ 22 : 19 ], | |
7403 | sii_l2b7_ecc_ccxrff[ 0 ], | |
7404 | ccx_rstg_out_unconnected[ 17 : 14 ], | |
7405 | sii_l2b7_ecc_ccxrff[ 2 : 1 ], | |
7406 | ccx_rstg_out_unconnected[ 11 : 8 ], | |
7407 | sii_l2b7_ecc_ccxrff[ 4 : 3 ], | |
7408 | ccx_rstg_out_unconnected[ 5 : 2 ], | |
7409 | sii_l2b7_ecc_ccxrff[ 6 : 5 ] | |
7410 | } | |
7411 | ), | |
7412 | .cpu_rep0_in (192'b0 ), | |
7413 | .cpu_rep0_out (cpu_rep0_out_unconnected[ 191 : 0 ]), | |
7414 | .cpu_rep1_in (192'b0 ), | |
7415 | .cpu_rep1_out (cpu_rep1_out_unconnected[ 191 : 0 ]), | |
7416 | .cmp_gclk_c2_ccx_left(cmp_gclk_c2_ccx_left), | |
7417 | .cmp_gclk_c2_ccx_right(cmp_gclk_c2_ccx_right), | |
7418 | .tcu_pce_ov(tcu_pce_ov), | |
7419 | .tcu_aclk(tcu_aclk), | |
7420 | .tcu_bclk(tcu_bclk), | |
7421 | .tcu_scan_en(tcu_scan_en), | |
7422 | .cluster_arst_l(cluster_arst_l), | |
7423 | .tcu_atpg_mode(tcu_atpg_mode), | |
7424 | .spc0_pcx_data_pa(spc0_pcx_data_pa[129:0]), | |
7425 | .spc0_pcx_req_pq(spc0_pcx_req_pq[8:0]), | |
7426 | .spc0_pcx_atm_pq(spc0_pcx_atm_pq[8:0]), | |
7427 | .spc1_pcx_data_pa(spc1_pcx_data_pa[129:0]), | |
7428 | .spc1_pcx_req_pq(spc1_pcx_req_pq[8:0]), | |
7429 | .spc1_pcx_atm_pq(spc1_pcx_atm_pq[8:0]), | |
7430 | .spc2_pcx_data_pa(spc2_pcx_data_pa[129:0]), | |
7431 | .spc2_pcx_req_pq(spc2_pcx_req_pq[8:0]), | |
7432 | .spc2_pcx_atm_pq(spc2_pcx_atm_pq[8:0]), | |
7433 | .spc3_pcx_data_pa(spc3_pcx_data_pa[129:0]), | |
7434 | .spc3_pcx_req_pq(spc3_pcx_req_pq[8:0]), | |
7435 | .spc3_pcx_atm_pq(spc3_pcx_atm_pq[8:0]), | |
7436 | .spc4_pcx_data_pa(spc4_pcx_data_pa[129:0]), | |
7437 | .spc4_pcx_req_pq(spc4_pcx_req_pq[8:0]), | |
7438 | .spc4_pcx_atm_pq(spc4_pcx_atm_pq[8:0]), | |
7439 | .spc5_pcx_data_pa(spc5_pcx_data_pa[129:0]), | |
7440 | .spc5_pcx_req_pq(spc5_pcx_req_pq[8:0]), | |
7441 | .spc5_pcx_atm_pq(spc5_pcx_atm_pq[8:0]), | |
7442 | .spc6_pcx_data_pa(spc6_pcx_data_pa[129:0]), | |
7443 | .spc6_pcx_req_pq(spc6_pcx_req_pq[8:0]), | |
7444 | .spc6_pcx_atm_pq(spc6_pcx_atm_pq[8:0]), | |
7445 | .spc7_pcx_data_pa(spc7_pcx_data_pa[129:0]), | |
7446 | .spc7_pcx_req_pq(spc7_pcx_req_pq[8:0]), | |
7447 | .spc7_pcx_atm_pq(spc7_pcx_atm_pq[8:0]), | |
7448 | .sctag0_pcx_stall_pq(sctag0_pcx_stall_pq), | |
7449 | .sctag1_pcx_stall_pq(sctag1_pcx_stall_pq), | |
7450 | .sctag2_pcx_stall_pq(sctag2_pcx_stall_pq), | |
7451 | .sctag3_pcx_stall_pq(sctag3_pcx_stall_pq), | |
7452 | .sctag4_pcx_stall_pq(sctag4_pcx_stall_pq), | |
7453 | .sctag5_pcx_stall_pq(sctag5_pcx_stall_pq), | |
7454 | .sctag6_pcx_stall_pq(sctag6_pcx_stall_pq), | |
7455 | .sctag7_pcx_stall_pq(sctag7_pcx_stall_pq), | |
7456 | .pcx_spc0_grant_px(pcx_spc0_grant_px[8:0]), | |
7457 | .pcx_spc1_grant_px(pcx_spc1_grant_px[8:0]), | |
7458 | .pcx_spc2_grant_px(pcx_spc2_grant_px[8:0]), | |
7459 | .pcx_spc3_grant_px(pcx_spc3_grant_px[8:0]), | |
7460 | .pcx_spc4_grant_px(pcx_spc4_grant_px[8:0]), | |
7461 | .pcx_spc5_grant_px(pcx_spc5_grant_px[8:0]), | |
7462 | .pcx_spc6_grant_px(pcx_spc6_grant_px[8:0]), | |
7463 | .pcx_spc7_grant_px(pcx_spc7_grant_px[8:0]), | |
7464 | .pcx_sctag0_atm_px1(pcx_sctag0_atm_px1), | |
7465 | .pcx_sctag0_data_px2(pcx_sctag0_data_px2[129:0]), | |
7466 | .pcx_sctag0_data_rdy_px1(pcx_sctag0_data_rdy_px1), | |
7467 | .pcx_sctag1_atm_px1(pcx_sctag1_atm_px1), | |
7468 | .pcx_sctag1_data_px2(pcx_sctag1_data_px2[129:0]), | |
7469 | .pcx_sctag1_data_rdy_px1(pcx_sctag1_data_rdy_px1), | |
7470 | .pcx_sctag2_atm_px1(pcx_sctag2_atm_px1), | |
7471 | .pcx_sctag2_data_px2(pcx_sctag2_data_px2[129:0]), | |
7472 | .pcx_sctag2_data_rdy_px1(pcx_sctag2_data_rdy_px1), | |
7473 | .pcx_sctag3_atm_px1(pcx_sctag3_atm_px1), | |
7474 | .pcx_sctag3_data_px2(pcx_sctag3_data_px2[129:0]), | |
7475 | .pcx_sctag3_data_rdy_px1(pcx_sctag3_data_rdy_px1), | |
7476 | .pcx_sctag4_atm_px1(pcx_sctag4_atm_px1), | |
7477 | .pcx_sctag4_data_px2(pcx_sctag4_data_px2[129:0]), | |
7478 | .pcx_sctag4_data_rdy_px1(pcx_sctag4_data_rdy_px1), | |
7479 | .pcx_sctag5_atm_px1(pcx_sctag5_atm_px1), | |
7480 | .pcx_sctag5_data_px2(pcx_sctag5_data_px2[129:0]), | |
7481 | .pcx_sctag5_data_rdy_px1(pcx_sctag5_data_rdy_px1), | |
7482 | .pcx_sctag6_atm_px1(pcx_sctag6_atm_px1), | |
7483 | .pcx_sctag6_data_px2(pcx_sctag6_data_px2[129:0]), | |
7484 | .pcx_sctag6_data_rdy_px1(pcx_sctag6_data_rdy_px1), | |
7485 | .pcx_sctag7_atm_px1(pcx_sctag7_atm_px1), | |
7486 | .pcx_sctag7_data_px2(pcx_sctag7_data_px2[129:0]), | |
7487 | .pcx_sctag7_data_rdy_px1(pcx_sctag7_data_rdy_px1), | |
7488 | .sctag0_cpx_atom_cq(sctag0_cpx_atom_cq), | |
7489 | .sctag0_cpx_req_cq(sctag0_cpx_req_cq[7:0]), | |
7490 | .sctag1_cpx_atom_cq(sctag1_cpx_atom_cq), | |
7491 | .sctag1_cpx_req_cq(sctag1_cpx_req_cq[7:0]), | |
7492 | .sctag2_cpx_atom_cq(sctag2_cpx_atom_cq), | |
7493 | .sctag2_cpx_req_cq(sctag2_cpx_req_cq[7:0]), | |
7494 | .sctag3_cpx_atom_cq(sctag3_cpx_atom_cq), | |
7495 | .sctag3_cpx_req_cq(sctag3_cpx_req_cq[7:0]), | |
7496 | .sctag4_cpx_atom_cq(sctag4_cpx_atom_cq), | |
7497 | .sctag4_cpx_req_cq(sctag4_cpx_req_cq[7:0]), | |
7498 | .sctag5_cpx_atom_cq(sctag5_cpx_atom_cq), | |
7499 | .sctag5_cpx_req_cq(sctag5_cpx_req_cq[7:0]), | |
7500 | .sctag6_cpx_atom_cq(sctag6_cpx_atom_cq), | |
7501 | .sctag6_cpx_req_cq(sctag6_cpx_req_cq[7:0]), | |
7502 | .sctag7_cpx_atom_cq(sctag7_cpx_atom_cq), | |
7503 | .sctag7_cpx_req_cq(sctag7_cpx_req_cq[7:0]), | |
7504 | .cpx_sctag0_grant_cx(cpx_sctag0_grant_cx[7:0]), | |
7505 | .cpx_sctag1_grant_cx(cpx_sctag1_grant_cx[7:0]), | |
7506 | .cpx_sctag2_grant_cx(cpx_sctag2_grant_cx[7:0]), | |
7507 | .cpx_sctag3_grant_cx(cpx_sctag3_grant_cx[7:0]), | |
7508 | .cpx_sctag4_grant_cx(cpx_sctag4_grant_cx[7:0]), | |
7509 | .cpx_sctag5_grant_cx(cpx_sctag5_grant_cx[7:0]), | |
7510 | .cpx_sctag6_grant_cx(cpx_sctag6_grant_cx[7:0]), | |
7511 | .cpx_sctag7_grant_cx(cpx_sctag7_grant_cx[7:0]), | |
7512 | .cpx_spc0_data_cx2(cpx_spc0_data_cx2[145:0]), | |
7513 | .cpx_spc1_data_cx2(cpx_spc1_data_cx2[145:0]), | |
7514 | .cpx_spc2_data_cx2(cpx_spc2_data_cx2[145:0]), | |
7515 | .cpx_spc3_data_cx2(cpx_spc3_data_cx2[145:0]), | |
7516 | .cpx_spc4_data_cx2(cpx_spc4_data_cx2[145:0]), | |
7517 | .cpx_spc5_data_cx2(cpx_spc5_data_cx2[145:0]), | |
7518 | .cpx_spc6_data_cx2(cpx_spc6_data_cx2[145:0]), | |
7519 | .cpx_spc7_data_cx2(cpx_spc7_data_cx2[145:0]) | |
7520 | ); | |
7521 | //________________________________________________________________ | |
7522 | ||
7523 | ||
7524 | n2_l2d_sp_512kb_cust l2d0( | |
7525 | ||
7526 | .l2b_l2d_en_fill_clk_v0 (1'b1), | |
7527 | .l2b_l2d_en_fill_clk_v1 (1'b1), | |
7528 | .l2t_l2d_en_fill_clk_ov (1'b1), | |
7529 | .l2t_l2d_pwrsav_ov (1'b1), | |
7530 | .vnw_ary0 (L2D_VNW0[ 0 ]), | |
7531 | .vnw_ary1 (L2D_VNW1[ 0 ]), | |
7532 | .gclk ( cmp_gclk_c3_l2d0 ), // cmp_gclk_c0_r[0] ), | |
7533 | .tcu_clk_stop ( gl_l2d0_clk_stop ), // staged clk_stop | |
7534 | .tcu_aclk (tcu_aclk), | |
7535 | .tcu_bclk (tcu_bclk), | |
7536 | .l2t_l2d_way_sel_c2 (l2t0_l2d0_way_sel_c2[ 15 : 0 ]), | |
7537 | .l2t_l2d_col_offset_c2 (l2t0_l2d0_col_offset_c2[ 3 : 0 ]), | |
7538 | .l2t_l2d_fb_hit_c3 (l2t0_l2d0_fb_hit_c3), | |
7539 | .l2t_l2d_fbrd_c3 (l2t0_l2d0_fbrd_c3), | |
7540 | .l2t_l2d_rd_wr_c2 (l2t0_l2d0_rd_wr_c2), | |
7541 | .l2t_l2d_set_c2 (l2t0_l2d0_set_c2[ 8 : 0 ]), | |
7542 | .l2t_l2d_word_en_c2 (l2t0_l2d0_word_en_c2[ 15 : 0 ]), | |
7543 | .l2t_l2d_stdecc_c2 (l2t0_l2d0_stdecc_c2[ 77 : 0 ]), | |
7544 | .l2b_l2d_fbdecc_c4 (l2b0_l2d0_fbdecc_c4[ 623 : 0 ]), | |
7545 | .rst_por_ ( gl_l2_por_c3t0 ), // ( gl_l2_por_c3t ), - for int6.1 | |
7546 | .rst_wmr_ ( gl_l2_wmr_c3t0 ), // ( gl_l2_wmr_c3t ), - for int6.1 | |
7547 | .rst_wmr_protect (rst_wmr_protect ), | |
7548 | .tcu_ce (1'b1), | |
7549 | .tcu_se_scancollar_in (tcu_se_scancollar_in), | |
7550 | .tcu_se_scancollar_out (tcu_se_scancollar_out), | |
7551 | .tcu_array_wr_inhibit (tcu_array_wr_inhibit), | |
7552 | .scan_in (l2t1_scan_out ), | |
7553 | .l2b_l2d_fuse_l2d_data_in (l2b0_l2d0_rvalue[ 9 : 0 ]), | |
7554 | .l2b_l2d_fuse_rid (l2b0_l2d0_rid[ 6 : 0 ]), | |
7555 | .l2b_l2d_fuse_l2d_wren (l2b0_l2d0_wr_en), | |
7556 | .l2b_l2d_fuse_reset (l2b0_l2d0_fuse_clr), | |
7557 | .l2d_l2b_efc_fuse_data (l2d0_l2b0_fuse_data[ 9 : 0 ]), | |
7558 | .scan_out (l2d0_scan_out), | |
7559 | .l2d_l2b_decc_out_c7 (l2d0_l2b0_decc_out_c7[ 623 : 0 ]), | |
7560 | .l2d_l2t_decc_c6 (l2d0_l2t0_decc_c6[ 155 : 0 ]), | |
7561 | .tcu_scan_en(tcu_scan_en), | |
7562 | .tcu_pce_ov(tcu_pce_ov), | |
7563 | .tcu_atpg_mode(tcu_atpg_mode) | |
7564 | ); | |
7565 | ||
7566 | //________________________________________________________________ | |
7567 | ||
7568 | ||
7569 | n2_l2d_sp_512kb_cust l2d1( | |
7570 | ||
7571 | .l2b_l2d_en_fill_clk_v0 (1'b1), | |
7572 | .l2b_l2d_en_fill_clk_v1 (1'b1), | |
7573 | .l2t_l2d_en_fill_clk_ov (1'b1), | |
7574 | .l2t_l2d_pwrsav_ov (1'b1), | |
7575 | .vnw_ary0 (L2D_VNW0[ 1 ]), | |
7576 | .vnw_ary1 (L2D_VNW1[ 1 ]), | |
7577 | .gclk ( cmp_gclk_c3_l2d1 ), // cmp_gclk_c0_r[1]), | |
7578 | .tcu_clk_stop ( gl_l2d1_clk_stop ), // staged clk_stop | |
7579 | .tcu_aclk (tcu_aclk), | |
7580 | .tcu_bclk (tcu_bclk), | |
7581 | .tcu_ce (1'b1 ), | |
7582 | .tcu_se_scancollar_in (tcu_se_scancollar_in), | |
7583 | .tcu_se_scancollar_out (tcu_se_scancollar_out), | |
7584 | .tcu_array_wr_inhibit (tcu_array_wr_inhibit), | |
7585 | .scan_in (l2d0_scan_out ), | |
7586 | .scan_out (l2d1_scan_out), | |
7587 | .l2b_l2d_fbdecc_c4 (l2b1_l2d1_fbdecc_c4[ 623 : 0 ] ),// scdata | |
7588 | .rst_por_ ( gl_l2_por_c3t ), | |
7589 | .rst_wmr_ ( gl_l2_wmr_c3t ), | |
7590 | .rst_wmr_protect (rst_wmr_protect ), | |
7591 | .l2t_l2d_col_offset_c2 (l2t1_l2d1_col_offset_c2[ 3 : 0 ]), | |
7592 | .l2t_l2d_fb_hit_c3 (l2t1_l2d1_fb_hit_c3 ), | |
7593 | .l2t_l2d_fbrd_c3 (l2t1_l2d1_fbrd_c3 ), | |
7594 | .l2t_l2d_rd_wr_c2 (l2t1_l2d1_rd_wr_c2 ), | |
7595 | .l2t_l2d_set_c2 (l2t1_l2d1_set_c2[ 8 : 0 ] ), | |
7596 | .l2t_l2d_stdecc_c2 (l2t1_l2d1_stdecc_c2[ 77 : 0 ] ), | |
7597 | .l2t_l2d_way_sel_c2 (l2t1_l2d1_way_sel_c2[ 15 : 0 ] ), | |
7598 | .l2t_l2d_word_en_c2 (l2t1_l2d1_word_en_c2[ 15 : 0 ] ), | |
7599 | .l2b_l2d_fuse_l2d_data_in (l2b1_l2d1_rvalue[ 9 : 0 ]), | |
7600 | .l2b_l2d_fuse_rid (l2b1_l2d1_rid[ 6 : 0 ]), | |
7601 | .l2b_l2d_fuse_l2d_wren (l2b1_l2d1_wr_en), | |
7602 | .l2b_l2d_fuse_reset (l2b1_l2d1_fuse_clr), | |
7603 | .l2d_l2b_efc_fuse_data (l2d1_l2b1_fuse_data[ 9 : 0 ]), | |
7604 | .l2d_l2b_decc_out_c7 (l2d1_l2b1_decc_out_c7[ 623 : 0 ]), | |
7605 | .l2d_l2t_decc_c6 (l2d1_l2t1_decc_c6[ 155 : 0 ] ), | |
7606 | .tcu_scan_en(tcu_scan_en), | |
7607 | .tcu_pce_ov(tcu_pce_ov), | |
7608 | .tcu_atpg_mode(tcu_atpg_mode) | |
7609 | ); | |
7610 | //________________________________________________________________ | |
7611 | ||
7612 | n2_l2d_sp_512kb_cust l2d2( | |
7613 | ||
7614 | .l2b_l2d_en_fill_clk_v0 (1'b1), | |
7615 | .l2b_l2d_en_fill_clk_v1 (1'b1), | |
7616 | .l2t_l2d_en_fill_clk_ov (1'b1), | |
7617 | .l2t_l2d_pwrsav_ov (1'b1), | |
7618 | .vnw_ary0 (L2D_VNW0[ 2 ]), | |
7619 | .vnw_ary1 (L2D_VNW1[ 2 ]), | |
7620 | .gclk ( cmp_gclk_c3_l2d2 ), // cmp_gclk_c3_r[4] ), | |
7621 | .tcu_clk_stop ( gl_l2d2_clk_stop ), // staged clk_stop | |
7622 | .tcu_aclk (tcu_aclk), | |
7623 | .tcu_bclk (tcu_bclk), | |
7624 | .tcu_ce (1'b1 ), | |
7625 | .tcu_se_scancollar_in (tcu_se_scancollar_in), | |
7626 | .tcu_se_scancollar_out (tcu_se_scancollar_out), | |
7627 | .tcu_array_wr_inhibit (tcu_array_wr_inhibit), | |
7628 | .scan_in (l2t3_scan_out ), | |
7629 | .scan_out (l2d2_scan_out), | |
7630 | .l2b_l2d_fbdecc_c4 (l2b2_l2d2_fbdecc_c4[ 623 : 0 ] ),// scdata | |
7631 | .rst_por_ ( gl_l2_por_c3b0 ), // ECO c3t0 -> c3b0 - mh157021 | |
7632 | .rst_wmr_ ( gl_l2_wmr_c3b ), // ECO c3t0 -> c3b - mh157021 | |
7633 | .rst_wmr_protect (rst_wmr_protect ), | |
7634 | .l2t_l2d_col_offset_c2 (l2t2_l2d2_col_offset_c2[ 3 : 0 ]), | |
7635 | .l2t_l2d_fb_hit_c3 (l2t2_l2d2_fb_hit_c3 ), | |
7636 | .l2t_l2d_fbrd_c3 (l2t2_l2d2_fbrd_c3 ), | |
7637 | .l2t_l2d_rd_wr_c2 (l2t2_l2d2_rd_wr_c2 ), | |
7638 | .l2t_l2d_set_c2 (l2t2_l2d2_set_c2[ 8 : 0 ] ), | |
7639 | .l2t_l2d_stdecc_c2 (l2t2_l2d2_stdecc_c2[ 77 : 0 ] ), | |
7640 | .l2t_l2d_way_sel_c2 (l2t2_l2d2_way_sel_c2[ 15 : 0 ] ), | |
7641 | .l2t_l2d_word_en_c2 (l2t2_l2d2_word_en_c2[ 15 : 0 ] ), | |
7642 | .l2d_l2b_decc_out_c7 (l2d2_l2b2_decc_out_c7[ 623 : 0 ]), | |
7643 | .l2d_l2t_decc_c6 (l2d2_l2t2_decc_c6[ 155 : 0 ] ), | |
7644 | .l2b_l2d_fuse_l2d_data_in (l2b2_l2d2_rvalue[ 9 : 0 ]), | |
7645 | .l2b_l2d_fuse_rid (l2b2_l2d2_rid[ 6 : 0 ]), | |
7646 | .l2b_l2d_fuse_l2d_wren (l2b2_l2d2_wr_en), | |
7647 | .l2b_l2d_fuse_reset (l2b2_l2d2_fuse_clr), | |
7648 | .l2d_l2b_efc_fuse_data (l2d2_l2b2_fuse_data[ 9 : 0 ]), | |
7649 | .tcu_scan_en(tcu_scan_en), | |
7650 | .tcu_pce_ov(tcu_pce_ov), | |
7651 | .tcu_atpg_mode(tcu_atpg_mode) | |
7652 | ); | |
7653 | //________________________________________________________________ | |
7654 | ||
7655 | n2_l2d_sp_512kb_cust l2d3( | |
7656 | ||
7657 | .l2b_l2d_en_fill_clk_v0 (1'b1), | |
7658 | .l2b_l2d_en_fill_clk_v1 (1'b1), | |
7659 | .l2t_l2d_en_fill_clk_ov (1'b1), | |
7660 | .l2t_l2d_pwrsav_ov (1'b1), | |
7661 | .vnw_ary0 (L2D_VNW0[ 3 ]), | |
7662 | .vnw_ary1 (L2D_VNW1[ 3 ]), | |
7663 | .gclk ( cmp_gclk_c3_l2d3 ), // cmp_gclk_c1_r[5]), | |
7664 | .tcu_clk_stop ( gl_l2d3_clk_stop ), // staged clk_stop | |
7665 | .tcu_aclk (tcu_aclk), | |
7666 | .tcu_bclk (tcu_bclk), | |
7667 | .scan_in (l2d2_scan_out ), | |
7668 | .scan_out (l2d3_scan_out), | |
7669 | .tcu_ce (1'b1 ), | |
7670 | .tcu_se_scancollar_in (tcu_se_scancollar_in), | |
7671 | .tcu_se_scancollar_out (tcu_se_scancollar_out), | |
7672 | .tcu_array_wr_inhibit (tcu_array_wr_inhibit), | |
7673 | .l2b_l2d_fuse_l2d_data_in (l2b3_l2d3_rvalue[ 9 : 0 ]), | |
7674 | .l2b_l2d_fuse_rid (l2b3_l2d3_rid[ 6 : 0 ]), | |
7675 | .l2b_l2d_fuse_l2d_wren (l2b3_l2d3_wr_en), | |
7676 | .l2b_l2d_fuse_reset (l2b3_l2d3_fuse_clr), | |
7677 | .l2d_l2b_efc_fuse_data (l2d3_l2b3_fuse_data[ 9 : 0 ]), | |
7678 | .l2b_l2d_fbdecc_c4 (l2b3_l2d3_fbdecc_c4[ 623 : 0 ] ),// scdata | |
7679 | .rst_por_ ( gl_l2_por_c3b0 ), // ECO c3t0 -> c3b0 -mh157021 | |
7680 | .rst_wmr_ ( gl_l2_wmr_c3b ), // ECO c3t0 -> c3b -mh157021 | |
7681 | .rst_wmr_protect (rst_wmr_protect ), | |
7682 | .l2t_l2d_col_offset_c2 (l2t3_l2d3_col_offset_c2[ 3 : 0 ]), | |
7683 | .l2t_l2d_fb_hit_c3 (l2t3_l2d3_fb_hit_c3 ), | |
7684 | .l2t_l2d_fbrd_c3 (l2t3_l2d3_fbrd_c3 ), | |
7685 | .l2t_l2d_rd_wr_c2 (l2t3_l2d3_rd_wr_c2 ), | |
7686 | .l2t_l2d_set_c2 (l2t3_l2d3_set_c2[ 8 : 0 ] ), | |
7687 | .l2t_l2d_stdecc_c2 (l2t3_l2d3_stdecc_c2[ 77 : 0 ] ), | |
7688 | .l2t_l2d_way_sel_c2 (l2t3_l2d3_way_sel_c2[ 15 : 0 ] ), | |
7689 | .l2t_l2d_word_en_c2 (l2t3_l2d3_word_en_c2[ 15 : 0 ] ), | |
7690 | .l2d_l2b_decc_out_c7 (l2d3_l2b3_decc_out_c7[ 623 : 0 ]), | |
7691 | .l2d_l2t_decc_c6 (l2d3_l2t3_decc_c6[ 155 : 0 ] ), | |
7692 | .tcu_scan_en(tcu_scan_en), | |
7693 | .tcu_pce_ov(tcu_pce_ov), | |
7694 | .tcu_atpg_mode(tcu_atpg_mode) | |
7695 | ); | |
7696 | //________________________________________________________________ | |
7697 | ||
7698 | n2_l2d_sp_512kb_cust l2d4( | |
7699 | ||
7700 | .l2b_l2d_en_fill_clk_v0 (1'b1), | |
7701 | .l2b_l2d_en_fill_clk_v1 (1'b1), | |
7702 | .l2t_l2d_en_fill_clk_ov (1'b1), | |
7703 | .l2t_l2d_pwrsav_ov (1'b1), | |
7704 | .vnw_ary0 (L2D_VNW0[ 4 ]), | |
7705 | .vnw_ary1 (L2D_VNW1[ 4 ]), | |
7706 | .gclk ( cmp_gclk_c1_l2d4 ), // cmp_gclk_c3_r[0]), | |
7707 | .tcu_clk_stop ( gl_l2d4_clk_stop ), // staged clk_stop | |
7708 | .tcu_aclk (tcu_aclk), | |
7709 | .tcu_bclk (tcu_bclk), | |
7710 | .scan_in (l2t5_scan_out ), | |
7711 | .scan_out (l2d4_scan_out), | |
7712 | .tcu_ce (1'b1), | |
7713 | .tcu_se_scancollar_in (tcu_se_scancollar_in), | |
7714 | .tcu_se_scancollar_out (tcu_se_scancollar_out), | |
7715 | .tcu_array_wr_inhibit (tcu_array_wr_inhibit), | |
7716 | .l2b_l2d_fuse_l2d_data_in (l2b4_l2d4_rvalue[ 9 : 0 ]), | |
7717 | .l2b_l2d_fuse_rid (l2b4_l2d4_rid[ 6 : 0 ]), | |
7718 | .l2b_l2d_fuse_l2d_wren (l2b4_l2d4_wr_en), | |
7719 | .l2b_l2d_fuse_reset (l2b4_l2d4_fuse_clr), | |
7720 | .l2d_l2b_efc_fuse_data (l2d4_l2b4_fuse_data[ 9 : 0 ]), | |
7721 | .l2b_l2d_fbdecc_c4 (l2b4_l2d4_fbdecc_c4[ 623 : 0 ] ),// scdata | |
7722 | .rst_por_ ( gl_l2_por_c1t ), | |
7723 | .rst_wmr_ ( gl_l2_wmr_c1t ), | |
7724 | .rst_wmr_protect (rst_wmr_protect ), | |
7725 | .l2t_l2d_col_offset_c2 (l2t4_l2d4_col_offset_c2[ 3 : 0 ]), | |
7726 | .l2t_l2d_fb_hit_c3 (l2t4_l2d4_fb_hit_c3 ), | |
7727 | .l2t_l2d_fbrd_c3 (l2t4_l2d4_fbrd_c3 ), | |
7728 | .l2t_l2d_rd_wr_c2 (l2t4_l2d4_rd_wr_c2 ), | |
7729 | .l2t_l2d_set_c2 (l2t4_l2d4_set_c2[ 8 : 0 ] ), | |
7730 | .l2t_l2d_stdecc_c2 (l2t4_l2d4_stdecc_c2[ 77 : 0 ] ), | |
7731 | .l2t_l2d_way_sel_c2 (l2t4_l2d4_way_sel_c2[ 15 : 0 ] ), | |
7732 | .l2t_l2d_word_en_c2 (l2t4_l2d4_word_en_c2[ 15 : 0 ] ), | |
7733 | .l2d_l2b_decc_out_c7 (l2d4_l2b4_decc_out_c7[ 623 : 0 ]), | |
7734 | .l2d_l2t_decc_c6 (l2d4_l2t4_decc_c6[ 155 : 0 ] ), | |
7735 | .tcu_scan_en(tcu_scan_en), | |
7736 | .tcu_pce_ov(tcu_pce_ov), | |
7737 | .tcu_atpg_mode(tcu_atpg_mode) | |
7738 | ); | |
7739 | //________________________________________________________________ | |
7740 | ||
7741 | n2_l2d_sp_512kb_cust l2d5( | |
7742 | ||
7743 | .l2b_l2d_en_fill_clk_v0 (1'b1), | |
7744 | .l2b_l2d_en_fill_clk_v1 (1'b1), | |
7745 | .l2t_l2d_en_fill_clk_ov (1'b1), | |
7746 | .l2t_l2d_pwrsav_ov (1'b1), | |
7747 | .vnw_ary0 (L2D_VNW0[ 5 ]), | |
7748 | .vnw_ary1 (L2D_VNW1[ 5 ]), | |
7749 | .gclk ( cmp_gclk_c1_l2d5 ), // cmp_gclk_c3_r[1]), | |
7750 | .tcu_clk_stop ( gl_l2d5_clk_stop ), // staged clk_stop | |
7751 | .tcu_aclk (tcu_aclk), | |
7752 | .tcu_bclk (tcu_bclk), | |
7753 | .tcu_ce (1'b1 ), | |
7754 | .tcu_se_scancollar_in (tcu_se_scancollar_in), | |
7755 | .tcu_se_scancollar_out (tcu_se_scancollar_out), | |
7756 | .tcu_array_wr_inhibit (tcu_array_wr_inhibit), | |
7757 | .scan_in (l2d4_scan_out ), | |
7758 | .scan_out (l2d5_scan_out), | |
7759 | .l2b_l2d_fbdecc_c4 (l2b5_l2d5_fbdecc_c4[ 623 : 0 ] ),// scdata | |
7760 | .rst_por_ ( gl_l2_por_c1t ), | |
7761 | .rst_wmr_ ( gl_l2_wmr_c1t ), // ECO c1b -> c1t -mh157021 | |
7762 | .rst_wmr_protect (rst_wmr_protect ), | |
7763 | .l2t_l2d_col_offset_c2 (l2t5_l2d5_col_offset_c2[ 3 : 0 ]), | |
7764 | .l2t_l2d_fb_hit_c3 (l2t5_l2d5_fb_hit_c3 ), | |
7765 | .l2t_l2d_fbrd_c3 (l2t5_l2d5_fbrd_c3 ), | |
7766 | .l2t_l2d_rd_wr_c2 (l2t5_l2d5_rd_wr_c2 ), | |
7767 | .l2t_l2d_set_c2 (l2t5_l2d5_set_c2[ 8 : 0 ] ), | |
7768 | .l2t_l2d_stdecc_c2 (l2t5_l2d5_stdecc_c2[ 77 : 0 ] ), | |
7769 | .l2t_l2d_way_sel_c2 (l2t5_l2d5_way_sel_c2[ 15 : 0 ] ), | |
7770 | .l2t_l2d_word_en_c2 (l2t5_l2d5_word_en_c2[ 15 : 0 ] ), | |
7771 | .l2b_l2d_fuse_l2d_data_in (l2b5_l2d5_rvalue[ 9 : 0 ]), | |
7772 | .l2b_l2d_fuse_rid (l2b5_l2d5_rid[ 6 : 0 ]), | |
7773 | .l2b_l2d_fuse_l2d_wren (l2b5_l2d5_wr_en), | |
7774 | .l2b_l2d_fuse_reset (l2b5_l2d5_fuse_clr), | |
7775 | .l2d_l2b_efc_fuse_data (l2d5_l2b5_fuse_data[ 9 : 0 ]), | |
7776 | .l2d_l2b_decc_out_c7 (l2d5_l2b5_decc_out_c7[ 623 : 0 ]), | |
7777 | .l2d_l2t_decc_c6 (l2d5_l2t5_decc_c6[ 155 : 0 ] ), | |
7778 | .tcu_scan_en(tcu_scan_en), | |
7779 | .tcu_pce_ov(tcu_pce_ov), | |
7780 | .tcu_atpg_mode(tcu_atpg_mode) | |
7781 | ); | |
7782 | //________________________________________________________________ | |
7783 | ||
7784 | n2_l2d_sp_512kb_cust l2d6( | |
7785 | ||
7786 | .l2b_l2d_en_fill_clk_v0 (1'b1), | |
7787 | .l2b_l2d_en_fill_clk_v1 (1'b1), | |
7788 | .l2t_l2d_en_fill_clk_ov (1'b1), | |
7789 | .l2t_l2d_pwrsav_ov (1'b1), | |
7790 | .vnw_ary0 (L2D_VNW0[ 6 ]), | |
7791 | .vnw_ary1 (L2D_VNW1[ 6 ]), | |
7792 | .gclk ( cmp_gclk_c1_l2d6 ), // cmp_gclk_c3_r[4]), | |
7793 | .tcu_clk_stop ( gl_l2d6_clk_stop ), // staged clk_stop | |
7794 | .tcu_aclk (tcu_aclk), | |
7795 | .tcu_bclk (tcu_bclk), | |
7796 | .tcu_ce (1'b1 ), | |
7797 | .tcu_se_scancollar_in (tcu_se_scancollar_in), | |
7798 | .tcu_se_scancollar_out (tcu_se_scancollar_out), | |
7799 | .tcu_array_wr_inhibit (tcu_array_wr_inhibit), | |
7800 | .scan_in (l2t7_scan_out ), | |
7801 | .scan_out (l2d6_scan_out), | |
7802 | .l2b_l2d_fuse_l2d_data_in (l2b6_l2d6_rvalue[ 9 : 0 ]), | |
7803 | .l2b_l2d_fuse_rid (l2b6_l2d6_rid[ 6 : 0 ]), | |
7804 | .l2b_l2d_fuse_l2d_wren (l2b6_l2d6_wr_en), | |
7805 | .l2b_l2d_fuse_reset (l2b6_l2d6_fuse_clr), | |
7806 | .l2d_l2b_efc_fuse_data (l2d6_l2b6_fuse_data[ 9 : 0 ]), | |
7807 | .l2b_l2d_fbdecc_c4 (l2b6_l2d6_fbdecc_c4[ 623 : 0 ] ),// scdata | |
7808 | .rst_por_ ( gl_l2_por_c1b ), // ECO c1t -> c1b - mh157021 | |
7809 | .rst_wmr_ ( gl_l2_wmr_c1b ), | |
7810 | .rst_wmr_protect (rst_wmr_protect ), | |
7811 | .l2t_l2d_col_offset_c2 (l2t6_l2d6_col_offset_c2[ 3 : 0 ]), | |
7812 | .l2t_l2d_fb_hit_c3 (l2t6_l2d6_fb_hit_c3 ), | |
7813 | .l2t_l2d_fbrd_c3 (l2t6_l2d6_fbrd_c3 ), | |
7814 | .l2t_l2d_rd_wr_c2 (l2t6_l2d6_rd_wr_c2 ), | |
7815 | .l2t_l2d_set_c2 (l2t6_l2d6_set_c2[ 8 : 0 ] ), | |
7816 | .l2t_l2d_stdecc_c2 (l2t6_l2d6_stdecc_c2[ 77 : 0 ] ), | |
7817 | .l2t_l2d_way_sel_c2 (l2t6_l2d6_way_sel_c2[ 15 : 0 ] ), | |
7818 | .l2t_l2d_word_en_c2 (l2t6_l2d6_word_en_c2[ 15 : 0 ] ), | |
7819 | .l2d_l2b_decc_out_c7 (l2d6_l2b6_decc_out_c7[ 623 : 0 ]), | |
7820 | .l2d_l2t_decc_c6 (l2d6_l2t6_decc_c6[ 155 : 0 ] ), | |
7821 | .tcu_scan_en(tcu_scan_en), | |
7822 | .tcu_pce_ov(tcu_pce_ov), | |
7823 | .tcu_atpg_mode(tcu_atpg_mode) | |
7824 | ); | |
7825 | //________________________________________________________________ | |
7826 | ||
7827 | n2_l2d_sp_512kb_cust l2d7( | |
7828 | ||
7829 | .l2b_l2d_en_fill_clk_v0 (1'b1), | |
7830 | .l2b_l2d_en_fill_clk_v1 (1'b1), | |
7831 | .l2t_l2d_en_fill_clk_ov (1'b1), | |
7832 | .l2t_l2d_pwrsav_ov (1'b1), | |
7833 | .vnw_ary0 (L2D_VNW0[ 7 ]), | |
7834 | .vnw_ary1 (L2D_VNW1[ 7 ]), | |
7835 | .gclk ( cmp_gclk_c1_l2d7 ), // cmp_gclk_c3_r[5]), | |
7836 | .tcu_clk_stop ( gl_l2d7_clk_stop ), // staged clk_stop | |
7837 | .tcu_aclk (tcu_aclk), | |
7838 | .tcu_bclk (tcu_bclk), | |
7839 | .tcu_ce (1'b1 ), | |
7840 | .tcu_se_scancollar_in (tcu_se_scancollar_in), | |
7841 | .tcu_se_scancollar_out (tcu_se_scancollar_out), | |
7842 | .tcu_array_wr_inhibit (tcu_array_wr_inhibit), | |
7843 | .scan_in (l2d6_scan_out ), | |
7844 | .scan_out (l2d7_scan_out), | |
7845 | .l2b_l2d_fuse_l2d_data_in (l2b7_l2d7_rvalue[ 9 : 0 ]), | |
7846 | .l2b_l2d_fuse_rid (l2b7_l2d7_rid[ 6 : 0 ]), | |
7847 | .l2b_l2d_fuse_l2d_wren (l2b7_l2d7_wr_en), | |
7848 | .l2b_l2d_fuse_reset (l2b7_l2d7_fuse_clr), | |
7849 | .l2d_l2b_efc_fuse_data (l2d7_l2b7_fuse_data[ 9 : 0 ]), | |
7850 | .l2b_l2d_fbdecc_c4 (l2b7_l2d7_fbdecc_c4[ 623 : 0 ] ),// scdata | |
7851 | .rst_por_ ( gl_l2_por_c1b ), // ECO c1t -> c1b - mh157021 | |
7852 | .rst_wmr_ ( gl_l2_wmr_c1b ), | |
7853 | .rst_wmr_protect (rst_wmr_protect ), | |
7854 | .l2t_l2d_col_offset_c2 (l2t7_l2d7_col_offset_c2[ 3 : 0 ]), | |
7855 | .l2t_l2d_fb_hit_c3 (l2t7_l2d7_fb_hit_c3 ), | |
7856 | .l2t_l2d_fbrd_c3 (l2t7_l2d7_fbrd_c3 ), | |
7857 | .l2t_l2d_rd_wr_c2 (l2t7_l2d7_rd_wr_c2 ), | |
7858 | .l2t_l2d_set_c2 (l2t7_l2d7_set_c2[ 8 : 0 ] ), | |
7859 | .l2t_l2d_stdecc_c2 (l2t7_l2d7_stdecc_c2[ 77 : 0 ] ), | |
7860 | .l2t_l2d_way_sel_c2 (l2t7_l2d7_way_sel_c2[ 15 : 0 ] ), | |
7861 | .l2t_l2d_word_en_c2 (l2t7_l2d7_word_en_c2[ 15 : 0 ] ), | |
7862 | .l2d_l2b_decc_out_c7 (l2d7_l2b7_decc_out_c7[ 623 : 0 ]), | |
7863 | .l2d_l2t_decc_c6 (l2d7_l2t7_decc_c6[ 155 : 0 ] ), | |
7864 | .tcu_scan_en(tcu_scan_en), | |
7865 | .tcu_pce_ov(tcu_pce_ov), | |
7866 | .tcu_atpg_mode(tcu_atpg_mode) | |
7867 | ); | |
7868 | //________________________________________________________________ | |
7869 | ||
7870 | ||
7871 | ||
7872 | /////// stagging flop | |
7873 | ||
7874 | wire [ 191 : 0 ] unconnectedt0lff; | |
7875 | wire [ 191 : 0 ] unconnectedt1lff; | |
7876 | wire [ 191 : 0 ] unconnectedt2lff; | |
7877 | wire [ 191 : 0 ] unconnectedt3lff; | |
7878 | wire [ 191 : 0 ] unconnectedt4lff; | |
7879 | wire [ 191 : 0 ] unconnectedt5lff; | |
7880 | wire [ 191 : 0 ] unconnectedt6lff; | |
7881 | wire [ 191 : 0 ] unconnectedt7lff; | |
7882 | wire [ 191 : 0 ] unconnectedt0rff; | |
7883 | wire [ 191 : 0 ] unconnectedt1rff; | |
7884 | wire [ 191 : 0 ] unconnectedt2rff; | |
7885 | wire [ 191 : 0 ] unconnectedt3rff; | |
7886 | wire [ 191 : 0 ] unconnectedt4rff; | |
7887 | wire [ 191 : 0 ] unconnectedt5rff; | |
7888 | wire [ 191 : 0 ] unconnectedt6rff; | |
7889 | wire [ 191 : 0 ] unconnectedt7rff; | |
7890 | ||
7891 | l2t l2t0( | |
7892 | .l2t_lstg_in ({ | |
7893 | 148'b0, | |
7894 | l2t1_mcu0_rd_req, | |
7895 | l2t1_mcu0_rd_dummy_req, | |
7896 | l2t1_mcu0_rd_req_id[ 2 : 0 ], | |
7897 | l2t1_mcu0_wr_req, | |
7898 | l2t1_mcu0_addr_5, | |
7899 | l2t1_mcu0_addr[ 39 : 31 ], | |
7900 | 4'b0, | |
7901 | l2t1_mcu0_addr[ 30 : 7 ]} | |
7902 | ), | |
7903 | .l2t_lstg_out ({ | |
7904 | unconnectedt0lff[ 191 : 44 ], | |
7905 | l2t1_mcu0_rd_req_t0lff, | |
7906 | l2t1_mcu0_rd_dummy_req_t0lff, | |
7907 | l2t1_mcu0_rd_req_id_t0lff[ 2 : 0 ], | |
7908 | l2t1_mcu0_wr_req_t0lff, | |
7909 | l2t1_mcu0_addr_5_t0lff, | |
7910 | l2t1_mcu0_addr_t0lff[ 39 : 31 ], | |
7911 | unconnectedt0lff[ 27 : 24 ], | |
7912 | l2t1_mcu0_addr_t0lff[ 30 : 7 ]} | |
7913 | ), | |
7914 | // .l2t_lstg_in (192'b0), | |
7915 | // .l2t_lstg_out (unconnectedt0lff[191:0]), | |
7916 | // .l2t_rstg_in (192'b0), | |
7917 | // .l2t_rstg_out (unconnectedt0rff[191:0]), | |
7918 | .l2t_rstg_in ({111'b0, | |
7919 | l2b0_sio_parity[ 1 : 0 ], | |
7920 | 79'b0 | |
7921 | } | |
7922 | ), | |
7923 | .l2t_rstg_out ({unconnectedt0rff[ 191 : 81 ], | |
7924 | l2b0_sio_parity_t0rff[ 1 : 0 ], | |
7925 | unconnectedt0rff[ 78 : 0 ] | |
7926 | } | |
7927 | ), | |
7928 | .l2t_siu_delay (1'b0), | |
7929 | .l2t_tcu_dmo_out_prev (39'b0 ), | |
7930 | .l2t_tcu_dmo_out (l2t0_dmo_dout[ 38 : 0 ] ), | |
7931 | .tcu_l2t_coresel (1'b0 ), | |
7932 | .tcu_l2t_tag_or_data_sel (dmo_tagmuxctl ), | |
7933 | .ccu_slow_cmp_sync_en ( gl_io_cmp_sync_en_c3t ), | |
7934 | .ccu_cmp_slow_sync_en ( gl_cmp_io_sync_en_c3t ), | |
7935 | .l2t_dbg_sii_iq_dequeue (l2t0_dbg0_sii_iq_dequeue ), | |
7936 | .l2t_dbg_sii_wib_dequeue (l2t0_dbg0_sii_wib_dequeue ), | |
7937 | .l2t_dbg_xbar_vcid (l2t0_dbg0_xbar_vcid[ 5 : 0 ] ), | |
7938 | .l2t_dbg_err_event (l2t0_dbg0_err_event ), | |
7939 | .l2t_dbg_pa_match (l2t0_dbg0_pa_match ), | |
7940 | .l2t_cpx_req_cq (sctag0_cpx_req_cq[ 7 : 0 ] ),// sctag | |
7941 | .l2t_cpx_atom_cq (sctag0_cpx_atom_cq ), | |
7942 | .l2t_cpx_data_ca (sctag0_cpx_data_ca[ 145 : 0 ]), | |
7943 | .l2t_pcx_stall_pq (sctag0_pcx_stall_pq ), | |
7944 | .pcx_l2t_data_rdy_px1 (pcx_sctag0_data_rdy_px1 ), | |
7945 | .pcx_l2t_data_px2 (pcx_sctag0_data_px2[ 129 : 0 ]), | |
7946 | .pcx_l2t_atm_px1 (pcx_sctag0_atm_px1 ), | |
7947 | .cpx_l2t_grant_cx (cpx_sctag0_grant_cx[ 7 : 0 ] ), | |
7948 | .l2t_rst_fatal_error (l2t0_rst_fatal_error ), | |
7949 | .rst_wmr_protect (rst_wmr_protect ), | |
7950 | .l2t_l2d_way_sel_c2 (l2t0_l2d0_way_sel_c2 ), | |
7951 | .l2t_l2d_rd_wr_c2 (l2t0_l2d0_rd_wr_c2 ), | |
7952 | .l2t_l2d_set_c2 (l2t0_l2d0_set_c2[ 8 : 0 ] ), | |
7953 | .l2t_l2d_col_offset_c2 (l2t0_l2d0_col_offset_c2[ 3 : 0 ]), | |
7954 | .l2t_l2d_word_en_c2 (l2t0_l2d0_word_en_c2 ), | |
7955 | .l2t_l2d_fbrd_c3 (l2t0_l2d0_fbrd_c3 ), | |
7956 | .l2t_l2d_fb_hit_c3 (l2t0_l2d0_fb_hit_c3 ), | |
7957 | .l2t_l2d_stdecc_c2 (l2t0_l2d0_stdecc_c2[ 77 : 0 ] ), | |
7958 | .l2d_l2t_decc_c6 (l2d0_l2t0_decc_c6 ), | |
7959 | // .l2t_l2b_stdecc_c3 (l2t0_l2b0_stdecc_c3[77:0] ), | |
7960 | .l2t_l2b_fbrd_en_c3 (l2t0_l2b0_fbrd_en_c3 ), | |
7961 | .l2t_l2b_fbrd_wl_c3 (l2t0_l2b0_fbrd_wl_c3[ 2 : 0 ] ), | |
7962 | .l2t_l2b_fbwr_wen_r2 (l2t0_l2b0_fbwr_wen_r2[ 15 : 0 ] ), | |
7963 | .l2t_l2b_fbwr_wl_r2 (l2t0_l2b0_fbwr_wl_r2[ 2 : 0 ] ), | |
7964 | .l2t_l2b_fbd_stdatasel_c3 (l2t0_l2b0_fbd_stdatasel_c3 ), | |
7965 | .l2t_l2b_wbwr_wen_c6 (l2t0_l2b0_wbwr_wen_c6[ 3 : 0 ] ), | |
7966 | .l2t_l2b_wbwr_wl_c6 (l2t0_l2b0_wbwr_wl_c6[ 2 : 0 ] ), | |
7967 | .l2t_l2b_wbrd_en_r0 (l2t0_l2b0_wbrd_en_r0 ), | |
7968 | .l2t_l2b_wbrd_wl_r0 (l2t0_l2b0_wbrd_wl_r0[ 2 : 0 ] ), | |
7969 | .l2t_l2b_ev_dword_r0 (l2t0_l2b0_ev_dword_r0[ 2 : 0 ] ), | |
7970 | .l2t_l2b_evict_en_r0 (l2t0_l2b0_evict_en_r0 ), | |
7971 | .l2b_l2t_ev_uerr_r5 (l2b0_l2t0_ev_uerr_r5 ), | |
7972 | .l2b_l2t_ev_cerr_r5 (l2b0_l2t0_ev_cerr_r5 ), | |
7973 | .l2t_l2b_rdma_wren_s2 (l2t0_l2b0_rdma_wren_s2[ 15 : 0 ]), | |
7974 | .l2t_l2b_rdma_wrwl_s2 (l2t0_l2b0_rdma_wrwl_s2[ 1 : 0 ] ), | |
7975 | .l2t_l2b_rdma_rdwl_r0 (l2t0_l2b0_rdma_rdwl_r0[ 1 : 0 ] ), | |
7976 | .l2t_l2b_rdma_rden_r0 (l2t0_l2b0_rdma_rden_r0 ), | |
7977 | .l2t_l2b_ctag_en_c7 (l2t0_l2b0_ctag_en_c7 ), | |
7978 | .l2t_l2b_ctag_c7 (l2t0_l2b0_ctag_c7[ 31 : 0 ] ), | |
7979 | .l2t_l2b_word_c7 (l2t0_l2b0_word_c7[ 3 : 0 ] ), | |
7980 | .l2t_l2b_req_en_c7 (l2t0_l2b0_req_en_c7 ), | |
7981 | .l2t_l2b_word_vld_c7 (l2t0_l2b0_word_vld_c7 ), | |
7982 | .l2b_l2t_rdma_uerr_c10 (l2b0_l2t0_rdma_uerr_c10 ), | |
7983 | .l2b_l2t_rdma_cerr_c10 (l2b0_l2t0_rdma_cerr_c10 ), | |
7984 | .l2b_l2t_rdma_notdata_c10 (l2b0_l2t0_rdma_notdata_c10 ), | |
7985 | .l2t_mcu_rd_req (l2t0_mcu0_rd_req ), | |
7986 | .l2t_mcu_rd_dummy_req (l2t0_mcu0_rd_dummy_req ), | |
7987 | .l2t_mcu_rd_req_id (l2t0_mcu0_rd_req_id[ 2 : 0 ] ), | |
7988 | .l2t_mcu_addr (l2t0_mcu0_addr[ 39 : 7 ] ), | |
7989 | .l2t_mcu_addr_5 (l2t0_mcu0_addr_5 ), | |
7990 | .l2t_mcu_wr_req (l2t0_mcu0_wr_req ), | |
7991 | .mcu_l2t_rd_ack (mcu0_l2t0_rd_ack ), | |
7992 | .mcu_l2t_wr_ack (mcu0_l2t0_wr_ack ), | |
7993 | .mcu_l2t_chunk_id_r0 (mcu0_l2t0_qword_id_r0[ 1 : 0 ] ), | |
7994 | .mcu_l2t_data_vld_r0 (mcu0_l2t0_data_vld_r0 ), | |
7995 | .mcu_l2t_rd_req_id_r0 (mcu0_l2t0_rd_req_id_r0[ 2 : 0 ] ), | |
7996 | .mcu_l2t_secc_err_r2 (mcu0_l2t0_secc_err_r2 ), | |
7997 | .mcu_l2t_mecc_err_r2 (mcu0_l2t0_mecc_err_r2 ), | |
7998 | .mcu_l2t_scb_mecc_err (mcu0_l2t0_scb_mecc_err ), | |
7999 | .mcu_l2t_scb_secc_err (mcu0_l2t0_scb_secc_err ), | |
8000 | .sii_l2t_req_vld (sii_l2t0_req_vld ), | |
8001 | .sii_l2t_req (sii_l2t0_req[ 31 : 0 ] ), | |
8002 | .sii_l2b_ecc (sii_l2b0_ecc[ 6 : 0 ] ), | |
8003 | .l2t_sii_iq_dequeue (l2t0_sii_iq_dequeue ), | |
8004 | .l2t_sii_wib_dequeue (l2t0_sii_wib_dequeue ), | |
8005 | .rst_por_ ( gl_l2_por_c3t ), | |
8006 | .rst_wmr_ ( gl_l2_wmr_c3t ), | |
8007 | .scan_in (tcu_soc0_scan_out ), | |
8008 | .scan_out (l2t0_scan_out ), | |
8009 | .efu_l2t_fuse_clr (efu_l2t0_fuse_clr ), | |
8010 | .efu_l2t_fuse_xfer_en (efu_l2t0_fuse_xfer_en ), | |
8011 | .efu_l2t_fuse_data (efu_l2t0246_fuse_data ), | |
8012 | .l2t_efu_fuse_data (l2t0_efu_fuse_data ), | |
8013 | .l2t_efu_fuse_xfer_en (l2t0_efu_fuse_xfer_en ), | |
8014 | .tcu_mbist_bisi_en (tcu_mbist_bisi_en), | |
8015 | .tcu_l2t_mbist_start (tcu_l2t0_mbist_start_t1lff), | |
8016 | .tcu_l2t_mbist_scan_in (tcu_l2t0_mbist_scan_in), | |
8017 | .l2t_tcu_mbist_done (l2t0_tcu_mbist_done), | |
8018 | .l2t_tcu_mbist_fail (l2t0_tcu_mbist_fail), | |
8019 | .l2t_tcu_mbist_scan_out (l2t0_tcu_mbist_scan_out), | |
8020 | .gclk ( cmp_gclk_c3_l2t0 ), // cmp_gclk_c1_r[2] ), | |
8021 | .tcu_clk_stop ( gl_l2t0_clk_stop ), // staged clk_stop | |
8022 | .tcu_l2t_shscan_scan_in (tcu_l2t0_shscan_scan_in ), | |
8023 | .tcu_l2t_shscan_aclk (tcu_l2t_shscan_aclk ), | |
8024 | .tcu_l2t_shscan_bclk (tcu_l2t_shscan_bclk ), | |
8025 | .tcu_l2t_shscan_scan_en (tcu_l2t_shscan_scan_en ), | |
8026 | .tcu_l2t_shscan_pce_ov (tcu_l2t_shscan_pce_ov ), | |
8027 | .l2t_tcu_shscan_scan_out (l2t0_tcu_shscan_scan_out), | |
8028 | .tcu_l2t_shscan_clk_stop (tcu_l2t0_shscan_clk_stop), | |
8029 | .vnw_ary (L2T_VNW[ 0 ]), | |
8030 | .l2t_rep_in0 (24'b0), | |
8031 | .l2t_rep_in1 (24'b0), | |
8032 | .l2t_rep_in2 (24'b0), | |
8033 | .l2t_rep_in3 (24'b0), | |
8034 | .l2t_rep_in4 (24'b0), | |
8035 | .l2t_rep_in5 (24'b0), | |
8036 | .l2t_rep_in6 (24'b0), | |
8037 | .l2t_rep_in7 (24'b0), | |
8038 | .l2t_rep_in8 (24'b0), | |
8039 | .l2t_rep_in9 (24'b0), | |
8040 | .l2t_rep_in10 (24'b0), | |
8041 | .l2t_rep_in11 (24'b0), | |
8042 | .l2t_rep_in12 (24'b0), | |
8043 | .l2t_rep_in13 (24'b0), | |
8044 | .l2t_rep_in14 (24'b0), | |
8045 | .l2t_rep_in15 (24'b0), | |
8046 | .l2t_rep_in16 (24'b0), | |
8047 | .l2t_rep_in17 (24'b0), | |
8048 | .l2t_rep_in18 (24'b0), | |
8049 | .l2t_rep_in19 (24'b0), | |
8050 | .l2t_rep_out0 (l2t0_rep_out0_unused[ 23 : 0 ]), | |
8051 | .l2t_rep_out1 (l2t0_rep_out1_unused[ 23 : 0 ]), | |
8052 | .l2t_rep_out2 (l2t0_rep_out2_unused[ 23 : 0 ]), | |
8053 | .l2t_rep_out3 (l2t0_rep_out3_unused[ 23 : 0 ]), | |
8054 | .l2t_rep_out4 (l2t0_rep_out4_unused[ 23 : 0 ]), | |
8055 | .l2t_rep_out5 (l2t0_rep_out5_unused[ 23 : 0 ]), | |
8056 | .l2t_rep_out6 (l2t0_rep_out6_unused[ 23 : 0 ]), | |
8057 | .l2t_rep_out7 (l2t0_rep_out7_unused[ 23 : 0 ]), | |
8058 | .l2t_rep_out8 (l2t0_rep_out8_unused[ 23 : 0 ]), | |
8059 | .l2t_rep_out9 (l2t0_rep_out9_unused[ 23 : 0 ]), | |
8060 | .l2t_rep_out10 (l2t0_rep_out10_unused[ 23 : 0 ]), | |
8061 | .l2t_rep_out11 (l2t0_rep_out11_unused[ 23 : 0 ]), | |
8062 | .l2t_rep_out12 (l2t0_rep_out12_unused[ 23 : 0 ]), | |
8063 | .l2t_rep_out13 (l2t0_rep_out13_unused[ 23 : 0 ]), | |
8064 | .l2t_rep_out14 (l2t0_rep_out14_unused[ 23 : 0 ]), | |
8065 | .l2t_rep_out15 (l2t0_rep_out15_unused[ 23 : 0 ]), | |
8066 | .l2t_rep_out16 (l2t0_rep_out16_unused[ 23 : 0 ]), | |
8067 | .l2t_rep_out17 (l2t0_rep_out17_unused[ 23 : 0 ]), | |
8068 | .l2t_rep_out18 (l2t0_rep_out18_unused[ 23 : 0 ]), | |
8069 | .l2t_rep_out19 (l2t0_rep_out19_unused[ 23 : 0 ]), | |
8070 | .ncu_l2t_pm(ncu_l2t_pm), | |
8071 | .ncu_l2t_ba01(ncu_l2t_ba01), | |
8072 | .ncu_l2t_ba23(ncu_l2t_ba23), | |
8073 | .ncu_l2t_ba45(ncu_l2t_ba45), | |
8074 | .ncu_l2t_ba67(ncu_l2t_ba67), | |
8075 | .ncu_spc0_core_enable_status(ncu_spc0_core_enable_status), | |
8076 | .ncu_spc1_core_enable_status(ncu_spc1_core_enable_status), | |
8077 | .ncu_spc2_core_enable_status(ncu_spc2_core_enable_status), | |
8078 | .ncu_spc3_core_enable_status(ncu_spc3_core_enable_status), | |
8079 | .ncu_spc4_core_enable_status(ncu_spc4_core_enable_status), | |
8080 | .ncu_spc5_core_enable_status(ncu_spc5_core_enable_status), | |
8081 | .ncu_spc6_core_enable_status(ncu_spc6_core_enable_status), | |
8082 | .ncu_spc7_core_enable_status(ncu_spc7_core_enable_status), | |
8083 | .tcu_pce_ov(tcu_pce_ov), | |
8084 | .tcu_aclk(tcu_aclk), | |
8085 | .tcu_bclk(tcu_bclk), | |
8086 | .tcu_scan_en(tcu_scan_en), | |
8087 | .tcu_muxtest(tcu_muxtest), | |
8088 | .tcu_dectest(tcu_dectest), | |
8089 | .tcu_atpg_mode(tcu_atpg_mode), | |
8090 | .tcu_se_scancollar_in(tcu_se_scancollar_in), | |
8091 | .tcu_se_scancollar_out(tcu_se_scancollar_out), | |
8092 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit), | |
8093 | .tcu_array_bypass(tcu_array_bypass), | |
8094 | .cluster_arst_l(cluster_arst_l), | |
8095 | .tcu_mbist_user_mode(tcu_mbist_user_mode) | |
8096 | ); | |
8097 | //________________________________________________________________ | |
8098 | ||
8099 | /////// stagging flop | |
8100 | ||
8101 | //assign | |
8102 | ||
8103 | l2t l2t1( | |
8104 | .l2t_lstg_in ( | |
8105 | {5'b0, | |
8106 | 1'b0, tcu_ncu_mbist_start[ 0 ], | |
8107 | 59'b0, | |
8108 | l2t4_sii_iq_dequeue, | |
8109 | l2t4_sii_wib_dequeue, | |
8110 | l2t5_sii_iq_dequeue, | |
8111 | l2t5_sii_wib_dequeue, | |
8112 | 48'b0, | |
8113 | tcu_l2t0_mbist_start, | |
8114 | tcu_spc_mbist_start[ 0 ], | |
8115 | tcu_ss_request[ 0 ], | |
8116 | 6'b0, | |
8117 | tcu_mcu0_mbist_start, | |
8118 | tcu_mcu1_mbist_start, | |
8119 | 63'b0} | |
8120 | ), | |
8121 | .l2t_rstg_in ( | |
8122 | {77'b0, | |
8123 | l2b0_sio_data[ 31 : 0 ], | |
8124 | // l2b0_sio_parity[1:0], | |
8125 | l2b0_sio_ctag_vld, | |
8126 | l2b0_sio_ue_err, | |
8127 | 25'b0, | |
8128 | mcu0_l2t1_rd_ack, | |
8129 | mcu0_l2t1_wr_ack, | |
8130 | mcu0_l2t1_qword_id_r0[ 1 : 0 ], | |
8131 | mcu0_l2t1_data_vld_r0, | |
8132 | mcu0_l2t1_rd_req_id_r0[ 2 : 0 ], | |
8133 | mcu0_l2t1_secc_err_r2, | |
8134 | mcu0_l2t1_mecc_err_r2, | |
8135 | mcu0_l2t1_scb_mecc_err, | |
8136 | mcu0_l2t1_scb_secc_err, | |
8137 | 44'b0} | |
8138 | ), | |
8139 | .l2t_lstg_out ( | |
8140 | {unconnectedt1lff[ 191 : 186 ], | |
8141 | tcu_ncu_mbist_start_t1lff_0, | |
8142 | unconnectedt1lff[ 184 : 126 ], | |
8143 | l2t4_sii_iq_dequeue_t1lff, | |
8144 | l2t4_sii_wib_dequeue_t1lff, | |
8145 | l2t5_sii_iq_dequeue_t1lff, | |
8146 | l2t5_sii_wib_dequeue_t1lff, | |
8147 | unconnectedt1lff[ 121 : 74 ], | |
8148 | tcu_l2t0_mbist_start_t1lff, | |
8149 | tcu_spc0_mbist_start_t1lff_0, | |
8150 | tcu_ss_request_t1lff_0, | |
8151 | unconnectedt1lff[ 70 : 65 ], | |
8152 | tcu_mcu0_mbist_start_t1lff, | |
8153 | tcu_mcu1_mbist_start_t1lff, | |
8154 | unconnectedt1lff_t1lff[ 62 : 0 ] | |
8155 | } | |
8156 | ), | |
8157 | .l2t_rstg_out ( | |
8158 | {unconnectedt1rff[ 191 : 115 ], | |
8159 | l2b0_sio_data_t1rff[ 31 : 0 ], | |
8160 | // l2b0_sio_parity_t1rff[1:0], | |
8161 | l2b0_sio_ctag_vld_t1rff, | |
8162 | l2b0_sio_ue_err_t1rff, | |
8163 | unconnectedt1rff[ 80 : 56 ], | |
8164 | mcu0_l2t1_rd_ack_t1rff, | |
8165 | mcu0_l2t1_wr_ack_t1rff, | |
8166 | mcu0_l2t1_qword_id_r0_t1rff[ 1 : 0 ], | |
8167 | mcu0_l2t1_data_vld_r0_t1rff, | |
8168 | mcu0_l2t1_rd_req_id_r0_t1rff[ 2 : 0 ], | |
8169 | mcu0_l2t1_secc_err_r2_t1rff, | |
8170 | mcu0_l2t1_mecc_err_r2_t1rff, | |
8171 | mcu0_l2t1_scb_mecc_err_t1rff, | |
8172 | mcu0_l2t1_scb_secc_err_t1rff, | |
8173 | unconnectedt1rff[ 43 : 0 ]} | |
8174 | ), | |
8175 | .l2t_siu_delay (1'b0), | |
8176 | .l2t_tcu_dmo_out_prev (l2t0_dmo_dout[ 38 : 0 ] ), | |
8177 | .l2t_tcu_dmo_out (l2t1_dmo_dout[ 38 : 0 ] ), | |
8178 | .tcu_l2t_coresel (dmo_l2tsel[ 5 ] ), | |
8179 | .tcu_l2t_tag_or_data_sel (dmo_tagmuxctl ), | |
8180 | .ccu_slow_cmp_sync_en ( gl_io_cmp_sync_en_c2t ), | |
8181 | .ccu_cmp_slow_sync_en ( gl_cmp_io_sync_en_c2t ), | |
8182 | .l2t_dbg_sii_iq_dequeue (l2t1_dbg1_sii_iq_dequeue ), | |
8183 | .l2t_dbg_sii_wib_dequeue (l2t1_dbg1_sii_wib_dequeue ), | |
8184 | .l2t_dbg_xbar_vcid (l2t1_dbg1_xbar_vcid[ 5 : 0 ] ), | |
8185 | .l2t_dbg_err_event (l2t1_dbg1_err_event ), | |
8186 | .l2t_dbg_pa_match (l2t1_dbg1_pa_match ), | |
8187 | .l2t_cpx_req_cq (sctag1_cpx_req_cq[ 7 : 0 ] ),// sctag | |
8188 | .l2t_cpx_atom_cq (sctag1_cpx_atom_cq ), | |
8189 | .l2t_cpx_data_ca (sctag1_cpx_data_ca[ 145 : 0 ]), | |
8190 | .l2t_pcx_stall_pq (sctag1_pcx_stall_pq ), | |
8191 | .pcx_l2t_data_rdy_px1 (pcx_sctag1_data_rdy_px1 ), | |
8192 | .pcx_l2t_data_px2 (pcx_sctag1_data_px2[ 129 : 0 ]), | |
8193 | .pcx_l2t_atm_px1 (pcx_sctag1_atm_px1 ), | |
8194 | .cpx_l2t_grant_cx (cpx_sctag1_grant_cx[ 7 : 0 ] ), | |
8195 | .l2t_rst_fatal_error (l2t1_rst_fatal_error), | |
8196 | .rst_wmr_protect (rst_wmr_protect ), | |
8197 | .l2t_l2d_way_sel_c2 (l2t1_l2d1_way_sel_c2 ), | |
8198 | .l2t_l2d_rd_wr_c2 (l2t1_l2d1_rd_wr_c2 ), | |
8199 | .l2t_l2d_set_c2 (l2t1_l2d1_set_c2[ 8 : 0 ] ), | |
8200 | .l2t_l2d_col_offset_c2 (l2t1_l2d1_col_offset_c2[ 3 : 0 ]), | |
8201 | .l2t_l2d_word_en_c2 (l2t1_l2d1_word_en_c2 ), | |
8202 | .l2t_l2d_fbrd_c3 (l2t1_l2d1_fbrd_c3 ), | |
8203 | .l2t_l2d_fb_hit_c3 (l2t1_l2d1_fb_hit_c3 ), | |
8204 | .l2t_l2d_stdecc_c2 (l2t1_l2d1_stdecc_c2[ 77 : 0 ] ), | |
8205 | .l2d_l2t_decc_c6 (l2d1_l2t1_decc_c6 ), | |
8206 | // .l2t_l2b_stdecc_c3 (l2t1_l2b1_stdecc_c3[77:0] ), | |
8207 | .l2t_l2b_fbrd_en_c3 (l2t1_l2b1_fbrd_en_c3 ), | |
8208 | .l2t_l2b_fbrd_wl_c3 (l2t1_l2b1_fbrd_wl_c3[ 2 : 0 ] ), | |
8209 | .l2t_l2b_fbwr_wen_r2 (l2t1_l2b1_fbwr_wen_r2[ 15 : 0 ] ), | |
8210 | .l2t_l2b_fbwr_wl_r2 (l2t1_l2b1_fbwr_wl_r2[ 2 : 0 ] ), | |
8211 | .l2t_l2b_fbd_stdatasel_c3 (l2t1_l2b1_fbd_stdatasel_c3 ), | |
8212 | .l2t_l2b_wbwr_wen_c6 (l2t1_l2b1_wbwr_wen_c6[ 3 : 0 ] ), | |
8213 | .l2t_l2b_wbwr_wl_c6 (l2t1_l2b1_wbwr_wl_c6[ 2 : 0 ] ), | |
8214 | .l2t_l2b_wbrd_en_r0 (l2t1_l2b1_wbrd_en_r0 ), | |
8215 | .l2t_l2b_wbrd_wl_r0 (l2t1_l2b1_wbrd_wl_r0[ 2 : 0 ] ), | |
8216 | .l2t_l2b_ev_dword_r0 (l2t1_l2b1_ev_dword_r0[ 2 : 0 ] ), | |
8217 | .l2t_l2b_evict_en_r0 (l2t1_l2b1_evict_en_r0 ), | |
8218 | .l2b_l2t_ev_uerr_r5 (l2b1_l2t1_ev_uerr_r5 ), | |
8219 | .l2b_l2t_ev_cerr_r5 (l2b1_l2t1_ev_cerr_r5 ), | |
8220 | .l2t_l2b_rdma_wren_s2 (l2t1_l2b1_rdma_wren_s2[ 15 : 0 ]), | |
8221 | .l2t_l2b_rdma_wrwl_s2 (l2t1_l2b1_rdma_wrwl_s2[ 1 : 0 ] ), | |
8222 | .l2t_l2b_rdma_rdwl_r0 (l2t1_l2b1_rdma_rdwl_r0[ 1 : 0 ] ), | |
8223 | .l2t_l2b_rdma_rden_r0 (l2t1_l2b1_rdma_rden_r0 ), | |
8224 | .l2t_l2b_ctag_en_c7 (l2t1_l2b1_ctag_en_c7 ), | |
8225 | .l2t_l2b_ctag_c7 (l2t1_l2b1_ctag_c7[ 31 : 0 ] ), | |
8226 | .l2t_l2b_word_c7 (l2t1_l2b1_word_c7[ 3 : 0 ] ), | |
8227 | .l2t_l2b_req_en_c7 (l2t1_l2b1_req_en_c7 ), | |
8228 | .l2t_l2b_word_vld_c7 (l2t1_l2b1_word_vld_c7 ), | |
8229 | .l2b_l2t_rdma_uerr_c10 (l2b1_l2t1_rdma_uerr_c10 ), | |
8230 | .l2b_l2t_rdma_cerr_c10 (l2b1_l2t1_rdma_cerr_c10 ), | |
8231 | .l2b_l2t_rdma_notdata_c10 (l2b1_l2t1_rdma_notdata_c10 ), | |
8232 | .l2t_mcu_rd_req (l2t1_mcu0_rd_req ), | |
8233 | .l2t_mcu_rd_dummy_req (l2t1_mcu0_rd_dummy_req ), | |
8234 | .l2t_mcu_rd_req_id (l2t1_mcu0_rd_req_id[ 2 : 0 ] ), | |
8235 | .l2t_mcu_addr (l2t1_mcu0_addr[ 39 : 7 ] ), | |
8236 | .l2t_mcu_addr_5 (l2t1_mcu0_addr_5 ), | |
8237 | .l2t_mcu_wr_req (l2t1_mcu0_wr_req ), | |
8238 | .mcu_l2t_rd_ack (mcu0_l2t1_rd_ack_t1rff ), | |
8239 | .mcu_l2t_wr_ack (mcu0_l2t1_wr_ack_t1rff ), | |
8240 | .mcu_l2t_chunk_id_r0 (mcu0_l2t1_qword_id_r0_t1rff[ 1 : 0 ] ), | |
8241 | .mcu_l2t_data_vld_r0 (mcu0_l2t1_data_vld_r0_t1rff ), | |
8242 | .mcu_l2t_rd_req_id_r0 (mcu0_l2t1_rd_req_id_r0_t1rff[ 2 : 0 ] ), | |
8243 | .mcu_l2t_secc_err_r2 (mcu0_l2t1_secc_err_r2_t1rff ), | |
8244 | .mcu_l2t_mecc_err_r2 (mcu0_l2t1_mecc_err_r2_t1rff ), | |
8245 | .mcu_l2t_scb_mecc_err (mcu0_l2t1_scb_mecc_err_t1rff ), | |
8246 | .mcu_l2t_scb_secc_err (mcu0_l2t1_scb_secc_err_t1rff ), | |
8247 | .sii_l2t_req_vld (sii_l2t1_req_vld ), | |
8248 | .sii_l2t_req (sii_l2t1_req[ 31 : 0 ] ), | |
8249 | .sii_l2b_ecc (sii_l2b1_ecc[ 6 : 0 ] ), | |
8250 | .l2t_sii_iq_dequeue (l2t1_sii_iq_dequeue ), | |
8251 | .l2t_sii_wib_dequeue (l2t1_sii_wib_dequeue ), | |
8252 | .scan_out (l2t1_scan_out ), | |
8253 | .rst_por_ ( gl_l2_por_c2t ), | |
8254 | .rst_wmr_ ( gl_l2_wmr_c2t ), | |
8255 | .scan_in (l2t0_scan_out ), | |
8256 | .efu_l2t_fuse_clr (efu_l2t1_fuse_clr ), | |
8257 | .efu_l2t_fuse_xfer_en (efu_l2t1_fuse_xfer_en ), | |
8258 | .efu_l2t_fuse_data (efu_l2t1357_fuse_data ), | |
8259 | .l2t_efu_fuse_data (l2t1_efu_fuse_data ), | |
8260 | .l2t_efu_fuse_xfer_en (l2t1_efu_fuse_xfer_en ), | |
8261 | .tcu_mbist_bisi_en (tcu_mbist_bisi_en), | |
8262 | .tcu_l2t_mbist_start (tcu_l2t1_mbist_start), | |
8263 | .tcu_l2t_mbist_scan_in (tcu_l2t1_mbist_scan_in), | |
8264 | .l2t_tcu_mbist_done (l2t1_tcu_mbist_done), | |
8265 | .l2t_tcu_mbist_fail (l2t1_tcu_mbist_fail), | |
8266 | .l2t_tcu_mbist_scan_out (l2t1_tcu_mbist_scan_out), | |
8267 | .gclk ( cmp_gclk_c2_l2t1 ), // cmp_gclk_c1_r[2] ), | |
8268 | .tcu_clk_stop ( gl_l2t1_clk_stop ), // staged clk_stop | |
8269 | .tcu_l2t_shscan_scan_in (tcu_l2t1_shscan_scan_in ), | |
8270 | .tcu_l2t_shscan_aclk (tcu_l2t_shscan_aclk ), | |
8271 | .tcu_l2t_shscan_bclk (tcu_l2t_shscan_bclk ), | |
8272 | .tcu_l2t_shscan_scan_en (tcu_l2t_shscan_scan_en ), | |
8273 | .tcu_l2t_shscan_pce_ov (tcu_l2t_shscan_pce_ov ), | |
8274 | .l2t_tcu_shscan_scan_out (l2t1_tcu_shscan_scan_out), | |
8275 | .tcu_l2t_shscan_clk_stop (tcu_l2t1_shscan_clk_stop), | |
8276 | .vnw_ary (L2T_VNW[ 1 ]), | |
8277 | .l2t_rep_in0 (24'b0), | |
8278 | .l2t_rep_in1 (24'b0), | |
8279 | .l2t_rep_in2 (24'b0), | |
8280 | .l2t_rep_in3 (24'b0), | |
8281 | .l2t_rep_in4 (24'b0), | |
8282 | .l2t_rep_in5 (24'b0), | |
8283 | .l2t_rep_in6 (24'b0), | |
8284 | .l2t_rep_in7 (24'b0), | |
8285 | .l2t_rep_in8 (24'b0), | |
8286 | .l2t_rep_in9 (24'b0), | |
8287 | .l2t_rep_in10 (24'b0), | |
8288 | .l2t_rep_in11 (24'b0), | |
8289 | .l2t_rep_in12 (24'b0), | |
8290 | .l2t_rep_in13 (24'b0), | |
8291 | .l2t_rep_in14 (24'b0), | |
8292 | .l2t_rep_in15 (24'b0), | |
8293 | .l2t_rep_in16 (24'b0), | |
8294 | .l2t_rep_in17 (24'b0), | |
8295 | .l2t_rep_in18 (24'b0), | |
8296 | .l2t_rep_in19 (24'b0), | |
8297 | .l2t_rep_out0 (l2t1_rep_out0_unused[ 23 : 0 ]), | |
8298 | .l2t_rep_out1 (l2t1_rep_out1_unused[ 23 : 0 ]), | |
8299 | .l2t_rep_out2 (l2t1_rep_out2_unused[ 23 : 0 ]), | |
8300 | .l2t_rep_out3 (l2t1_rep_out3_unused[ 23 : 0 ]), | |
8301 | .l2t_rep_out4 (l2t1_rep_out4_unused[ 23 : 0 ]), | |
8302 | .l2t_rep_out5 (l2t1_rep_out5_unused[ 23 : 0 ]), | |
8303 | .l2t_rep_out6 (l2t1_rep_out6_unused[ 23 : 0 ]), | |
8304 | .l2t_rep_out7 (l2t1_rep_out7_unused[ 23 : 0 ]), | |
8305 | .l2t_rep_out8 (l2t1_rep_out8_unused[ 23 : 0 ]), | |
8306 | .l2t_rep_out9 (l2t1_rep_out9_unused[ 23 : 0 ]), | |
8307 | .l2t_rep_out10 (l2t1_rep_out10_unused[ 23 : 0 ]), | |
8308 | .l2t_rep_out11 (l2t1_rep_out11_unused[ 23 : 0 ]), | |
8309 | .l2t_rep_out12 (l2t1_rep_out12_unused[ 23 : 0 ]), | |
8310 | .l2t_rep_out13 (l2t1_rep_out13_unused[ 23 : 0 ]), | |
8311 | .l2t_rep_out14 (l2t1_rep_out14_unused[ 23 : 0 ]), | |
8312 | .l2t_rep_out15 (l2t1_rep_out15_unused[ 23 : 0 ]), | |
8313 | .l2t_rep_out16 (l2t1_rep_out16_unused[ 23 : 0 ]), | |
8314 | .l2t_rep_out17 (l2t1_rep_out17_unused[ 23 : 0 ]), | |
8315 | .l2t_rep_out18 (l2t1_rep_out18_unused[ 23 : 0 ]), | |
8316 | .l2t_rep_out19 (l2t1_rep_out19_unused[ 23 : 0 ]), | |
8317 | .ncu_l2t_pm(ncu_l2t_pm), | |
8318 | .ncu_l2t_ba01(ncu_l2t_ba01), | |
8319 | .ncu_l2t_ba23(ncu_l2t_ba23), | |
8320 | .ncu_l2t_ba45(ncu_l2t_ba45), | |
8321 | .ncu_l2t_ba67(ncu_l2t_ba67), | |
8322 | .ncu_spc0_core_enable_status(ncu_spc0_core_enable_status), | |
8323 | .ncu_spc1_core_enable_status(ncu_spc1_core_enable_status), | |
8324 | .ncu_spc2_core_enable_status(ncu_spc2_core_enable_status), | |
8325 | .ncu_spc3_core_enable_status(ncu_spc3_core_enable_status), | |
8326 | .ncu_spc4_core_enable_status(ncu_spc4_core_enable_status), | |
8327 | .ncu_spc5_core_enable_status(ncu_spc5_core_enable_status), | |
8328 | .ncu_spc6_core_enable_status(ncu_spc6_core_enable_status), | |
8329 | .ncu_spc7_core_enable_status(ncu_spc7_core_enable_status), | |
8330 | .tcu_pce_ov(tcu_pce_ov), | |
8331 | .tcu_aclk(tcu_aclk), | |
8332 | .tcu_bclk(tcu_bclk), | |
8333 | .tcu_scan_en(tcu_scan_en), | |
8334 | .tcu_muxtest(tcu_muxtest), | |
8335 | .tcu_dectest(tcu_dectest), | |
8336 | .tcu_atpg_mode(tcu_atpg_mode), | |
8337 | .tcu_se_scancollar_in(tcu_se_scancollar_in), | |
8338 | .tcu_se_scancollar_out(tcu_se_scancollar_out), | |
8339 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit), | |
8340 | .tcu_array_bypass(tcu_array_bypass), | |
8341 | .cluster_arst_l(cluster_arst_l), | |
8342 | .tcu_mbist_user_mode(tcu_mbist_user_mode) | |
8343 | ); | |
8344 | //________________________________________________________________ | |
8345 | ||
8346 | /////// stagging flop | |
8347 | ||
8348 | //assign | |
8349 | ||
8350 | l2t l2t2( | |
8351 | .ccu_slow_cmp_sync_en ( gl_io_cmp_sync_en_c3b ), | |
8352 | .ccu_cmp_slow_sync_en ( gl_cmp_io_sync_en_c3b ), | |
8353 | .l2t_lstg_in ({ | |
8354 | 148'b0, | |
8355 | l2t3_mcu1_rd_req, | |
8356 | l2t3_mcu1_rd_dummy_req, | |
8357 | l2t3_mcu1_rd_req_id[ 2 : 0 ], | |
8358 | l2t3_mcu1_wr_req, | |
8359 | l2t3_mcu1_addr_5, | |
8360 | l2t3_mcu1_addr[ 39 : 31 ], | |
8361 | 4'b0, | |
8362 | l2t3_mcu1_addr[ 30 : 7 ]} | |
8363 | ), | |
8364 | .l2t_lstg_out ({ | |
8365 | unconnectedt2lff[ 191 : 44 ], | |
8366 | l2t3_mcu1_rd_req_t2lff, | |
8367 | l2t3_mcu1_rd_dummy_req_t2lff, | |
8368 | l2t3_mcu1_rd_req_id_t2lff[ 2 : 0 ], | |
8369 | l2t3_mcu1_wr_req_t2lff, | |
8370 | l2t3_mcu1_addr_5_t2lff, | |
8371 | l2t3_mcu1_addr_t2lff[ 39 : 31 ], | |
8372 | unconnectedt2lff[ 27 : 24 ], | |
8373 | l2t3_mcu1_addr_t2lff[ 30 : 7 ]} | |
8374 | ), | |
8375 | // .l2t_lstg_in (192'b0), | |
8376 | // .l2t_lstg_out (unconnectedt2lff[191:0]), | |
8377 | .l2t_rstg_in (192'b0), | |
8378 | .l2t_rstg_out (unconnectedt2rff[ 191 : 0 ]), | |
8379 | .l2t_siu_delay (1'b0), | |
8380 | .l2t_tcu_dmo_out_prev (39'b0 ), | |
8381 | .l2t_tcu_dmo_out (l2t2_dmo_dout[ 38 : 0 ] ), | |
8382 | .tcu_l2t_coresel (1'b0 ), | |
8383 | .tcu_l2t_tag_or_data_sel (dmo_tagmuxctl ), | |
8384 | .l2t_dbg_sii_iq_dequeue (l2t2_dbg0_sii_iq_dequeue ), | |
8385 | .l2t_dbg_sii_wib_dequeue (l2t2_dbg0_sii_wib_dequeue ), | |
8386 | .l2t_dbg_xbar_vcid (l2t2_dbg0_xbar_vcid[ 5 : 0 ] ), | |
8387 | .l2t_dbg_err_event (l2t2_dbg0_err_event ), | |
8388 | .l2t_dbg_pa_match (l2t2_dbg0_pa_match ), | |
8389 | .l2t_cpx_req_cq (sctag2_cpx_req_cq[ 7 : 0 ] ),// sctag | |
8390 | .l2t_cpx_atom_cq (sctag2_cpx_atom_cq ), | |
8391 | .l2t_cpx_data_ca (sctag2_cpx_data_ca[ 145 : 0 ]), | |
8392 | .l2t_pcx_stall_pq (sctag2_pcx_stall_pq ), | |
8393 | .pcx_l2t_data_rdy_px1 (pcx_sctag2_data_rdy_px1 ), | |
8394 | .pcx_l2t_data_px2 (pcx_sctag2_data_px2[ 129 : 0 ]), | |
8395 | .pcx_l2t_atm_px1 (pcx_sctag2_atm_px1 ), | |
8396 | .cpx_l2t_grant_cx (cpx_sctag2_grant_cx[ 7 : 0 ] ), | |
8397 | .l2t_rst_fatal_error (l2t2_rst_fatal_error), | |
8398 | .rst_wmr_protect (rst_wmr_protect ), | |
8399 | .l2t_l2d_way_sel_c2 (l2t2_l2d2_way_sel_c2 ), | |
8400 | .l2t_l2d_rd_wr_c2 (l2t2_l2d2_rd_wr_c2 ), | |
8401 | .l2t_l2d_set_c2 (l2t2_l2d2_set_c2[ 8 : 0 ] ), | |
8402 | .l2t_l2d_col_offset_c2 (l2t2_l2d2_col_offset_c2[ 3 : 0 ]), | |
8403 | .l2t_l2d_word_en_c2 (l2t2_l2d2_word_en_c2 ), | |
8404 | .l2t_l2d_fbrd_c3 (l2t2_l2d2_fbrd_c3 ), | |
8405 | .l2t_l2d_fb_hit_c3 (l2t2_l2d2_fb_hit_c3 ), | |
8406 | .l2t_l2d_stdecc_c2 (l2t2_l2d2_stdecc_c2[ 77 : 0 ] ), | |
8407 | .l2d_l2t_decc_c6 (l2d2_l2t2_decc_c6 ), | |
8408 | // .l2t_l2b_stdecc_c3 (l2t2_l2b2_stdecc_c3[77:0] ), | |
8409 | .l2t_l2b_fbrd_en_c3 (l2t2_l2b2_fbrd_en_c3 ), | |
8410 | .l2t_l2b_fbrd_wl_c3 (l2t2_l2b2_fbrd_wl_c3[ 2 : 0 ] ), | |
8411 | .l2t_l2b_fbwr_wen_r2 (l2t2_l2b2_fbwr_wen_r2[ 15 : 0 ] ), | |
8412 | .l2t_l2b_fbwr_wl_r2 (l2t2_l2b2_fbwr_wl_r2[ 2 : 0 ] ), | |
8413 | .l2t_l2b_fbd_stdatasel_c3 (l2t2_l2b2_fbd_stdatasel_c3 ), | |
8414 | .l2t_l2b_wbwr_wen_c6 (l2t2_l2b2_wbwr_wen_c6[ 3 : 0 ] ), | |
8415 | .l2t_l2b_wbwr_wl_c6 (l2t2_l2b2_wbwr_wl_c6[ 2 : 0 ] ), | |
8416 | .l2t_l2b_wbrd_en_r0 (l2t2_l2b2_wbrd_en_r0 ), | |
8417 | .l2t_l2b_wbrd_wl_r0 (l2t2_l2b2_wbrd_wl_r0[ 2 : 0 ] ), | |
8418 | .l2t_l2b_ev_dword_r0 (l2t2_l2b2_ev_dword_r0[ 2 : 0 ] ), | |
8419 | .l2t_l2b_evict_en_r0 (l2t2_l2b2_evict_en_r0 ), | |
8420 | .l2b_l2t_ev_uerr_r5 (l2b2_l2t2_ev_uerr_r5 ), | |
8421 | .l2b_l2t_ev_cerr_r5 (l2b2_l2t2_ev_cerr_r5 ), | |
8422 | .l2t_l2b_rdma_wren_s2 (l2t2_l2b2_rdma_wren_s2[ 15 : 0 ]), | |
8423 | .l2t_l2b_rdma_wrwl_s2 (l2t2_l2b2_rdma_wrwl_s2[ 1 : 0 ] ), | |
8424 | .l2t_l2b_rdma_rdwl_r0 (l2t2_l2b2_rdma_rdwl_r0[ 1 : 0 ] ), | |
8425 | .l2t_l2b_rdma_rden_r0 (l2t2_l2b2_rdma_rden_r0 ), | |
8426 | .l2t_l2b_ctag_en_c7 (l2t2_l2b2_ctag_en_c7 ), | |
8427 | .l2t_l2b_ctag_c7 (l2t2_l2b2_ctag_c7[ 31 : 0 ] ), | |
8428 | .l2t_l2b_word_c7 (l2t2_l2b2_word_c7[ 3 : 0 ] ), | |
8429 | .l2t_l2b_req_en_c7 (l2t2_l2b2_req_en_c7 ), | |
8430 | .l2t_l2b_word_vld_c7 (l2t2_l2b2_word_vld_c7 ), | |
8431 | .l2b_l2t_rdma_uerr_c10 (l2b2_l2t2_rdma_uerr_c10 ), | |
8432 | .l2b_l2t_rdma_cerr_c10 (l2b2_l2t2_rdma_cerr_c10 ), | |
8433 | .l2b_l2t_rdma_notdata_c10 (l2b2_l2t2_rdma_notdata_c10 ), | |
8434 | .l2t_mcu_rd_req (l2t2_mcu1_rd_req ), | |
8435 | .l2t_mcu_rd_dummy_req (l2t2_mcu1_rd_dummy_req ), | |
8436 | .l2t_mcu_rd_req_id (l2t2_mcu1_rd_req_id[ 2 : 0 ] ), | |
8437 | .l2t_mcu_addr (l2t2_mcu1_addr[ 39 : 7 ] ), | |
8438 | .l2t_mcu_addr_5 (l2t2_mcu1_addr_5 ), | |
8439 | .l2t_mcu_wr_req (l2t2_mcu1_wr_req ), | |
8440 | .mcu_l2t_rd_ack (mcu1_l2t2_rd_ack ), | |
8441 | .mcu_l2t_wr_ack (mcu1_l2t2_wr_ack ), | |
8442 | .mcu_l2t_chunk_id_r0 (mcu1_l2t2_qword_id_r0[ 1 : 0 ] ), | |
8443 | .mcu_l2t_data_vld_r0 (mcu1_l2t2_data_vld_r0 ), | |
8444 | .mcu_l2t_rd_req_id_r0 (mcu1_l2t2_rd_req_id_r0[ 2 : 0 ] ), | |
8445 | .mcu_l2t_secc_err_r2 (mcu1_l2t2_secc_err_r2 ), | |
8446 | .mcu_l2t_mecc_err_r2 (mcu1_l2t2_mecc_err_r2 ), | |
8447 | .mcu_l2t_scb_mecc_err (mcu1_l2t2_scb_mecc_err ), | |
8448 | .mcu_l2t_scb_secc_err (mcu1_l2t2_scb_secc_err ), | |
8449 | .sii_l2t_req_vld (sii_l2t2_req_vld ), | |
8450 | .sii_l2t_req (sii_l2t2_req[ 31 : 0 ] ), | |
8451 | .sii_l2b_ecc (sii_l2b2_ecc[ 6 : 0 ] ), | |
8452 | .l2t_sii_iq_dequeue (l2t2_sii_iq_dequeue ), | |
8453 | .l2t_sii_wib_dequeue (l2t2_sii_wib_dequeue ), | |
8454 | .rst_por_ ( gl_l2_por_c3b0 ), | |
8455 | .rst_wmr_ ( gl_l2_wmr_c3b ), | |
8456 | .scan_in (tcu_soc1_scan_out ), | |
8457 | .scan_out (l2t2_scan_out ), | |
8458 | .tcu_mbist_bisi_en (tcu_mbist_bisi_en ), | |
8459 | .tcu_l2t_mbist_start (tcu_l2t2_mbist_start_t3lff), | |
8460 | .tcu_l2t_mbist_scan_in (tcu_l2t2_mbist_scan_in ), | |
8461 | .l2t_tcu_mbist_done (l2t2_tcu_mbist_done), | |
8462 | .l2t_tcu_mbist_fail (l2t2_tcu_mbist_fail), | |
8463 | .l2t_tcu_mbist_scan_out (l2t2_tcu_mbist_scan_out ), | |
8464 | .efu_l2t_fuse_clr (efu_l2t2_fuse_clr ), | |
8465 | .efu_l2t_fuse_xfer_en (efu_l2t2_fuse_xfer_en ), | |
8466 | .efu_l2t_fuse_data (efu_l2t0246_fuse_data ), | |
8467 | .l2t_efu_fuse_data (l2t2_efu_fuse_data ), | |
8468 | .l2t_efu_fuse_xfer_en (l2t2_efu_fuse_xfer_en ), | |
8469 | .gclk ( cmp_gclk_c3_l2t2 ), // cmp_gclk_c1_r[5] ), | |
8470 | .tcu_clk_stop ( gl_l2t2_clk_stop ), // staged clk_stop | |
8471 | .tcu_l2t_shscan_scan_in (tcu_l2t2_shscan_scan_in ), | |
8472 | .tcu_l2t_shscan_aclk (tcu_l2t_shscan_aclk ), | |
8473 | .tcu_l2t_shscan_bclk (tcu_l2t_shscan_bclk ), | |
8474 | .tcu_l2t_shscan_scan_en (tcu_l2t_shscan_scan_en ), | |
8475 | .tcu_l2t_shscan_pce_ov (tcu_l2t_shscan_pce_ov ), | |
8476 | .l2t_tcu_shscan_scan_out (l2t2_tcu_shscan_scan_out), | |
8477 | .tcu_l2t_shscan_clk_stop (tcu_l2t2_shscan_clk_stop), | |
8478 | .vnw_ary (L2T_VNW[ 2 ]), | |
8479 | .l2t_rep_in0 (24'b0), | |
8480 | .l2t_rep_in1 (24'b0), | |
8481 | .l2t_rep_in2 (24'b0), | |
8482 | .l2t_rep_in3 (24'b0), | |
8483 | .l2t_rep_in4 (24'b0), | |
8484 | .l2t_rep_in5 (24'b0), | |
8485 | .l2t_rep_in6 (24'b0), | |
8486 | .l2t_rep_in7 (24'b0), | |
8487 | .l2t_rep_in8 (24'b0), | |
8488 | .l2t_rep_in9 (24'b0), | |
8489 | .l2t_rep_in10 (24'b0), | |
8490 | .l2t_rep_in11 (24'b0), | |
8491 | .l2t_rep_in12 (24'b0), | |
8492 | .l2t_rep_in13 (24'b0), | |
8493 | .l2t_rep_in14 (24'b0), | |
8494 | .l2t_rep_in15 (24'b0), | |
8495 | .l2t_rep_in16 (24'b0), | |
8496 | .l2t_rep_in17 (24'b0), | |
8497 | .l2t_rep_in18 (24'b0), | |
8498 | .l2t_rep_in19 (24'b0), | |
8499 | .l2t_rep_out0 (l2t2_rep_out0_unused[ 23 : 0 ]), | |
8500 | .l2t_rep_out1 (l2t2_rep_out1_unused[ 23 : 0 ]), | |
8501 | .l2t_rep_out2 (l2t2_rep_out2_unused[ 23 : 0 ]), | |
8502 | .l2t_rep_out3 (l2t2_rep_out3_unused[ 23 : 0 ]), | |
8503 | .l2t_rep_out4 (l2t2_rep_out4_unused[ 23 : 0 ]), | |
8504 | .l2t_rep_out5 (l2t2_rep_out5_unused[ 23 : 0 ]), | |
8505 | .l2t_rep_out6 (l2t2_rep_out6_unused[ 23 : 0 ]), | |
8506 | .l2t_rep_out7 (l2t2_rep_out7_unused[ 23 : 0 ]), | |
8507 | .l2t_rep_out8 (l2t2_rep_out8_unused[ 23 : 0 ]), | |
8508 | .l2t_rep_out9 (l2t2_rep_out9_unused[ 23 : 0 ]), | |
8509 | .l2t_rep_out10 (l2t2_rep_out10_unused[ 23 : 0 ]), | |
8510 | .l2t_rep_out11 (l2t2_rep_out11_unused[ 23 : 0 ]), | |
8511 | .l2t_rep_out12 (l2t2_rep_out12_unused[ 23 : 0 ]), | |
8512 | .l2t_rep_out13 (l2t2_rep_out13_unused[ 23 : 0 ]), | |
8513 | .l2t_rep_out14 (l2t2_rep_out14_unused[ 23 : 0 ]), | |
8514 | .l2t_rep_out15 (l2t2_rep_out15_unused[ 23 : 0 ]), | |
8515 | .l2t_rep_out16 (l2t2_rep_out16_unused[ 23 : 0 ]), | |
8516 | .l2t_rep_out17 (l2t2_rep_out17_unused[ 23 : 0 ]), | |
8517 | .l2t_rep_out18 (l2t2_rep_out18_unused[ 23 : 0 ]), | |
8518 | .l2t_rep_out19 (l2t2_rep_out19_unused[ 23 : 0 ]), | |
8519 | .ncu_l2t_pm(ncu_l2t_pm), | |
8520 | .ncu_l2t_ba01(ncu_l2t_ba01), | |
8521 | .ncu_l2t_ba23(ncu_l2t_ba23), | |
8522 | .ncu_l2t_ba45(ncu_l2t_ba45), | |
8523 | .ncu_l2t_ba67(ncu_l2t_ba67), | |
8524 | .ncu_spc0_core_enable_status(ncu_spc0_core_enable_status), | |
8525 | .ncu_spc1_core_enable_status(ncu_spc1_core_enable_status), | |
8526 | .ncu_spc2_core_enable_status(ncu_spc2_core_enable_status), | |
8527 | .ncu_spc3_core_enable_status(ncu_spc3_core_enable_status), | |
8528 | .ncu_spc4_core_enable_status(ncu_spc4_core_enable_status), | |
8529 | .ncu_spc5_core_enable_status(ncu_spc5_core_enable_status), | |
8530 | .ncu_spc6_core_enable_status(ncu_spc6_core_enable_status), | |
8531 | .ncu_spc7_core_enable_status(ncu_spc7_core_enable_status), | |
8532 | .tcu_pce_ov(tcu_pce_ov), | |
8533 | .tcu_aclk(tcu_aclk), | |
8534 | .tcu_bclk(tcu_bclk), | |
8535 | .tcu_scan_en(tcu_scan_en), | |
8536 | .tcu_muxtest(tcu_muxtest), | |
8537 | .tcu_dectest(tcu_dectest), | |
8538 | .tcu_atpg_mode(tcu_atpg_mode), | |
8539 | .tcu_se_scancollar_in(tcu_se_scancollar_in), | |
8540 | .tcu_se_scancollar_out(tcu_se_scancollar_out), | |
8541 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit), | |
8542 | .tcu_array_bypass(tcu_array_bypass), | |
8543 | .cluster_arst_l(cluster_arst_l), | |
8544 | .tcu_mbist_user_mode(tcu_mbist_user_mode) | |
8545 | ); | |
8546 | //________________________________________________________________ | |
8547 | ||
8548 | /////// stagging flop | |
8549 | ||
8550 | //assign | |
8551 | ||
8552 | l2t l2t3( | |
8553 | .ccu_slow_cmp_sync_en ( gl_io_cmp_sync_en_c2b ), | |
8554 | .ccu_cmp_slow_sync_en ( gl_cmp_io_sync_en_c2b ), | |
8555 | .l2t_lstg_in ( | |
8556 | { 66'b0, | |
8557 | l2t6_sii_iq_dequeue, | |
8558 | l2t6_sii_wib_dequeue, | |
8559 | l2t7_sii_iq_dequeue, | |
8560 | l2t7_sii_wib_dequeue, | |
8561 | 48'b0, | |
8562 | tcu_l2t2_mbist_start, | |
8563 | tcu_spc_mbist_start[ 2 ], | |
8564 | tcu_ss_request[ 2 ], | |
8565 | 71'b0 | |
8566 | } | |
8567 | ), | |
8568 | .l2t_rstg_in ( | |
8569 | {136'b0, | |
8570 | mcu1_l2t3_rd_ack, | |
8571 | mcu1_l2t3_wr_ack, | |
8572 | mcu1_l2t3_qword_id_r0[ 1 : 0 ], | |
8573 | mcu1_l2t3_data_vld_r0, | |
8574 | mcu1_l2t3_rd_req_id_r0[ 2 : 0 ], | |
8575 | mcu1_l2t3_secc_err_r2, | |
8576 | mcu1_l2t3_mecc_err_r2, | |
8577 | mcu1_l2t3_scb_mecc_err, | |
8578 | mcu1_l2t3_scb_secc_err, | |
8579 | 44'b0 | |
8580 | } | |
8581 | ), | |
8582 | .l2t_lstg_out ( | |
8583 | {unconnectedt3lff[ 191 : 126 ], | |
8584 | l2t6_sii_iq_dequeue_t3lff, | |
8585 | l2t6_sii_wib_dequeue_t3lff, | |
8586 | l2t7_sii_iq_dequeue_t3lff, | |
8587 | l2t7_sii_wib_dequeue_t3lff, | |
8588 | unconnectedt3lff[ 121 : 74 ], | |
8589 | tcu_l2t2_mbist_start_t3lff, | |
8590 | tcu_spc_mbist_start_t3lff_2, | |
8591 | tcu_ss_request_t3lff_2, | |
8592 | unconnectedt3lff[ 70 : 0 ] | |
8593 | } | |
8594 | ), | |
8595 | .l2t_rstg_out ( | |
8596 | {unconnectedt3rff[ 191 : 56 ], | |
8597 | mcu1_l2t3_rd_ack_t3rff, | |
8598 | mcu1_l2t3_wr_ack_t3rff, | |
8599 | mcu1_l2t3_qword_id_r0_t3rff[ 1 : 0 ], | |
8600 | mcu1_l2t3_data_vld_r0_t3rff, | |
8601 | mcu1_l2t3_rd_req_id_r0_t3rff[ 2 : 0 ], | |
8602 | mcu1_l2t3_secc_err_r2_t3rff, | |
8603 | mcu1_l2t3_mecc_err_r2_t3rff, | |
8604 | mcu1_l2t3_scb_mecc_err_t3rff, | |
8605 | mcu1_l2t3_scb_secc_err_t3rff, | |
8606 | unconnectedt3rff[ 43 : 0 ] | |
8607 | } | |
8608 | ), | |
8609 | .l2t_siu_delay (1'b0), | |
8610 | .l2t_tcu_dmo_out_prev (l2t2_dmo_dout[ 38 : 0 ] ), | |
8611 | .l2t_tcu_dmo_out (l2t3_dmo_dout[ 38 : 0 ] ), | |
8612 | .tcu_l2t_coresel (dmo_l2tsel[ 2 ] ), | |
8613 | .tcu_l2t_tag_or_data_sel (dmo_tagmuxctl ), | |
8614 | .l2t_dbg_sii_iq_dequeue (l2t3_dbg1_sii_iq_dequeue ), | |
8615 | .l2t_dbg_sii_wib_dequeue (l2t3_dbg1_sii_wib_dequeue ), | |
8616 | .l2t_dbg_xbar_vcid (l2t3_dbg1_xbar_vcid[ 5 : 0 ] ), | |
8617 | .l2t_dbg_err_event (l2t3_dbg1_err_event ), | |
8618 | .l2t_dbg_pa_match (l2t3_dbg1_pa_match ), | |
8619 | .l2t_cpx_req_cq (sctag3_cpx_req_cq[ 7 : 0 ] ),// sctag | |
8620 | .l2t_cpx_atom_cq (sctag3_cpx_atom_cq ), | |
8621 | .l2t_cpx_data_ca (sctag3_cpx_data_ca[ 145 : 0 ]), | |
8622 | .l2t_pcx_stall_pq (sctag3_pcx_stall_pq ), | |
8623 | .pcx_l2t_data_rdy_px1 (pcx_sctag3_data_rdy_px1 ), | |
8624 | .pcx_l2t_data_px2 (pcx_sctag3_data_px2[ 129 : 0 ]), | |
8625 | .pcx_l2t_atm_px1 (pcx_sctag3_atm_px1 ), | |
8626 | .cpx_l2t_grant_cx (cpx_sctag3_grant_cx[ 7 : 0 ] ), | |
8627 | .l2t_rst_fatal_error (l2t3_rst_fatal_error), | |
8628 | .rst_wmr_protect (rst_wmr_protect ), | |
8629 | .l2t_l2d_way_sel_c2 (l2t3_l2d3_way_sel_c2 ), | |
8630 | .l2t_l2d_rd_wr_c2 (l2t3_l2d3_rd_wr_c2 ), | |
8631 | .l2t_l2d_set_c2 (l2t3_l2d3_set_c2[ 8 : 0 ] ), | |
8632 | .l2t_l2d_col_offset_c2 (l2t3_l2d3_col_offset_c2[ 3 : 0 ]), | |
8633 | .l2t_l2d_word_en_c2 (l2t3_l2d3_word_en_c2 ), | |
8634 | .l2t_l2d_fbrd_c3 (l2t3_l2d3_fbrd_c3 ), | |
8635 | .l2t_l2d_fb_hit_c3 (l2t3_l2d3_fb_hit_c3 ), | |
8636 | .l2t_l2d_stdecc_c2 (l2t3_l2d3_stdecc_c2[ 77 : 0 ] ), | |
8637 | .l2d_l2t_decc_c6 (l2d3_l2t3_decc_c6 ), | |
8638 | // .l2t_l2b_stdecc_c3 (l2t3_l2b3_stdecc_c3[77:0] ), | |
8639 | .l2t_l2b_fbrd_en_c3 (l2t3_l2b3_fbrd_en_c3 ), | |
8640 | .l2t_l2b_fbrd_wl_c3 (l2t3_l2b3_fbrd_wl_c3[ 2 : 0 ] ), | |
8641 | .l2t_l2b_fbwr_wen_r2 (l2t3_l2b3_fbwr_wen_r2[ 15 : 0 ] ), | |
8642 | .l2t_l2b_fbwr_wl_r2 (l2t3_l2b3_fbwr_wl_r2[ 2 : 0 ] ), | |
8643 | .l2t_l2b_fbd_stdatasel_c3 (l2t3_l2b3_fbd_stdatasel_c3 ), | |
8644 | .l2t_l2b_wbwr_wen_c6 (l2t3_l2b3_wbwr_wen_c6[ 3 : 0 ] ), | |
8645 | .l2t_l2b_wbwr_wl_c6 (l2t3_l2b3_wbwr_wl_c6[ 2 : 0 ] ), | |
8646 | .l2t_l2b_wbrd_en_r0 (l2t3_l2b3_wbrd_en_r0 ), | |
8647 | .l2t_l2b_wbrd_wl_r0 (l2t3_l2b3_wbrd_wl_r0[ 2 : 0 ] ), | |
8648 | .l2t_l2b_ev_dword_r0 (l2t3_l2b3_ev_dword_r0[ 2 : 0 ] ), | |
8649 | .l2t_l2b_evict_en_r0 (l2t3_l2b3_evict_en_r0 ), | |
8650 | .l2b_l2t_ev_uerr_r5 (l2b3_l2t3_ev_uerr_r5 ), | |
8651 | .l2b_l2t_ev_cerr_r5 (l2b3_l2t3_ev_cerr_r5 ), | |
8652 | .l2t_l2b_rdma_wren_s2 (l2t3_l2b3_rdma_wren_s2[ 15 : 0 ]), | |
8653 | .l2t_l2b_rdma_wrwl_s2 (l2t3_l2b3_rdma_wrwl_s2[ 1 : 0 ] ), | |
8654 | .l2t_l2b_rdma_rdwl_r0 (l2t3_l2b3_rdma_rdwl_r0[ 1 : 0 ] ), | |
8655 | .l2t_l2b_rdma_rden_r0 (l2t3_l2b3_rdma_rden_r0 ), | |
8656 | .l2t_l2b_ctag_en_c7 (l2t3_l2b3_ctag_en_c7 ), | |
8657 | .l2t_l2b_ctag_c7 (l2t3_l2b3_ctag_c7[ 31 : 0 ] ), | |
8658 | .l2t_l2b_word_c7 (l2t3_l2b3_word_c7[ 3 : 0 ] ), | |
8659 | .l2t_l2b_req_en_c7 (l2t3_l2b3_req_en_c7 ), | |
8660 | .l2t_l2b_word_vld_c7 (l2t3_l2b3_word_vld_c7 ), | |
8661 | .l2b_l2t_rdma_uerr_c10 (l2b3_l2t3_rdma_uerr_c10 ), | |
8662 | .l2b_l2t_rdma_cerr_c10 (l2b3_l2t3_rdma_cerr_c10 ), | |
8663 | .l2b_l2t_rdma_notdata_c10 (l2b3_l2t3_rdma_notdata_c10 ), | |
8664 | .l2t_mcu_rd_req (l2t3_mcu1_rd_req ), | |
8665 | .l2t_mcu_rd_dummy_req (l2t3_mcu1_rd_dummy_req ), | |
8666 | .l2t_mcu_rd_req_id (l2t3_mcu1_rd_req_id[ 2 : 0 ] ), | |
8667 | .l2t_mcu_addr (l2t3_mcu1_addr[ 39 : 7 ] ), | |
8668 | .l2t_mcu_addr_5 (l2t3_mcu1_addr_5 ), | |
8669 | .l2t_mcu_wr_req (l2t3_mcu1_wr_req ), | |
8670 | .mcu_l2t_rd_ack (mcu1_l2t3_rd_ack_t3rff ), | |
8671 | .mcu_l2t_wr_ack (mcu1_l2t3_wr_ack_t3rff ), | |
8672 | .mcu_l2t_chunk_id_r0 (mcu1_l2t3_qword_id_r0_t3rff[ 1 : 0 ] ), | |
8673 | .mcu_l2t_data_vld_r0 (mcu1_l2t3_data_vld_r0_t3rff ), | |
8674 | .mcu_l2t_rd_req_id_r0 (mcu1_l2t3_rd_req_id_r0_t3rff[ 2 : 0 ] ), | |
8675 | .mcu_l2t_secc_err_r2 (mcu1_l2t3_secc_err_r2_t3rff ), | |
8676 | .mcu_l2t_mecc_err_r2 (mcu1_l2t3_mecc_err_r2_t3rff ), | |
8677 | .mcu_l2t_scb_mecc_err (mcu1_l2t3_scb_mecc_err_t3rff ), | |
8678 | .mcu_l2t_scb_secc_err (mcu1_l2t3_scb_secc_err_t3rff ), | |
8679 | .sii_l2t_req_vld (sii_l2t3_req_vld ), | |
8680 | .sii_l2t_req (sii_l2t3_req[ 31 : 0 ] ), | |
8681 | .sii_l2b_ecc (sii_l2b3_ecc[ 6 : 0 ] ), | |
8682 | .l2t_sii_iq_dequeue (l2t3_sii_iq_dequeue ), | |
8683 | .l2t_sii_wib_dequeue (l2t3_sii_wib_dequeue ), | |
8684 | .rst_por_ ( gl_l2_por_c2b ), | |
8685 | .rst_wmr_ ( gl_l2_wmr_c2b ), | |
8686 | .scan_in (l2t2_scan_out ), | |
8687 | .scan_out (l2t3_scan_out ), | |
8688 | .tcu_mbist_bisi_en (tcu_mbist_bisi_en ), | |
8689 | .tcu_l2t_mbist_start (tcu_l2t3_mbist_start), | |
8690 | .tcu_l2t_mbist_scan_in (tcu_l2t3_mbist_scan_in ), | |
8691 | .l2t_tcu_mbist_done (l2t3_tcu_mbist_done), | |
8692 | .l2t_tcu_mbist_fail (l2t3_tcu_mbist_fail), | |
8693 | .l2t_tcu_mbist_scan_out (l2t3_tcu_mbist_scan_out ), | |
8694 | .efu_l2t_fuse_clr (efu_l2t3_fuse_clr ), | |
8695 | .efu_l2t_fuse_xfer_en (efu_l2t3_fuse_xfer_en ), | |
8696 | .efu_l2t_fuse_data (efu_l2t1357_fuse_data ), | |
8697 | .l2t_efu_fuse_data (l2t3_efu_fuse_data ), | |
8698 | .l2t_efu_fuse_xfer_en (l2t3_efu_fuse_xfer_en ), | |
8699 | .gclk ( cmp_gclk_c2_l2t3 ), // cmp_gclk_c1_r[5]), | |
8700 | .tcu_clk_stop ( gl_l2t3_clk_stop ), // staged clk_stop | |
8701 | .tcu_l2t_shscan_scan_in (tcu_l2t3_shscan_scan_in ), | |
8702 | .tcu_l2t_shscan_aclk (tcu_l2t_shscan_aclk ), | |
8703 | .tcu_l2t_shscan_bclk (tcu_l2t_shscan_bclk ), | |
8704 | .tcu_l2t_shscan_scan_en (tcu_l2t_shscan_scan_en ), | |
8705 | .tcu_l2t_shscan_pce_ov (tcu_l2t_shscan_pce_ov ), | |
8706 | .l2t_tcu_shscan_scan_out (l2t3_tcu_shscan_scan_out), | |
8707 | .tcu_l2t_shscan_clk_stop (tcu_l2t3_shscan_clk_stop), | |
8708 | .vnw_ary (L2T_VNW[ 3 ]), | |
8709 | .l2t_rep_in0 (24'b0), | |
8710 | .l2t_rep_in1 (24'b0), | |
8711 | .l2t_rep_in2 (24'b0), | |
8712 | .l2t_rep_in3 (24'b0), | |
8713 | .l2t_rep_in4 (24'b0), | |
8714 | .l2t_rep_in5 (24'b0), | |
8715 | .l2t_rep_in6 (24'b0), | |
8716 | .l2t_rep_in7 (24'b0), | |
8717 | .l2t_rep_in8 (24'b0), | |
8718 | .l2t_rep_in9 (24'b0), | |
8719 | .l2t_rep_in10 (24'b0), | |
8720 | .l2t_rep_in11 (24'b0), | |
8721 | .l2t_rep_in12 (24'b0), | |
8722 | .l2t_rep_in13 (24'b0), | |
8723 | .l2t_rep_in14 (24'b0), | |
8724 | .l2t_rep_in15 (24'b0), | |
8725 | .l2t_rep_in16 (24'b0), | |
8726 | .l2t_rep_in17 (24'b0), | |
8727 | .l2t_rep_in18 (24'b0), | |
8728 | .l2t_rep_in19 (24'b0), | |
8729 | .l2t_rep_out0 (l2t3_rep_out0_unused[ 23 : 0 ]), | |
8730 | .l2t_rep_out1 (l2t3_rep_out1_unused[ 23 : 0 ]), | |
8731 | .l2t_rep_out2 (l2t3_rep_out2_unused[ 23 : 0 ]), | |
8732 | .l2t_rep_out3 (l2t3_rep_out3_unused[ 23 : 0 ]), | |
8733 | .l2t_rep_out4 (l2t3_rep_out4_unused[ 23 : 0 ]), | |
8734 | .l2t_rep_out5 (l2t3_rep_out5_unused[ 23 : 0 ]), | |
8735 | .l2t_rep_out6 (l2t3_rep_out6_unused[ 23 : 0 ]), | |
8736 | .l2t_rep_out7 (l2t3_rep_out7_unused[ 23 : 0 ]), | |
8737 | .l2t_rep_out8 (l2t3_rep_out8_unused[ 23 : 0 ]), | |
8738 | .l2t_rep_out9 (l2t3_rep_out9_unused[ 23 : 0 ]), | |
8739 | .l2t_rep_out10 (l2t3_rep_out10_unused[ 23 : 0 ]), | |
8740 | .l2t_rep_out11 (l2t3_rep_out11_unused[ 23 : 0 ]), | |
8741 | .l2t_rep_out12 (l2t3_rep_out12_unused[ 23 : 0 ]), | |
8742 | .l2t_rep_out13 (l2t3_rep_out13_unused[ 23 : 0 ]), | |
8743 | .l2t_rep_out14 (l2t3_rep_out14_unused[ 23 : 0 ]), | |
8744 | .l2t_rep_out15 (l2t3_rep_out15_unused[ 23 : 0 ]), | |
8745 | .l2t_rep_out16 (l2t3_rep_out16_unused[ 23 : 0 ]), | |
8746 | .l2t_rep_out17 (l2t3_rep_out17_unused[ 23 : 0 ]), | |
8747 | .l2t_rep_out18 (l2t3_rep_out18_unused[ 23 : 0 ]), | |
8748 | .l2t_rep_out19 (l2t3_rep_out19_unused[ 23 : 0 ]), | |
8749 | .ncu_l2t_pm(ncu_l2t_pm), | |
8750 | .ncu_l2t_ba01(ncu_l2t_ba01), | |
8751 | .ncu_l2t_ba23(ncu_l2t_ba23), | |
8752 | .ncu_l2t_ba45(ncu_l2t_ba45), | |
8753 | .ncu_l2t_ba67(ncu_l2t_ba67), | |
8754 | .ncu_spc0_core_enable_status(ncu_spc0_core_enable_status), | |
8755 | .ncu_spc1_core_enable_status(ncu_spc1_core_enable_status), | |
8756 | .ncu_spc2_core_enable_status(ncu_spc2_core_enable_status), | |
8757 | .ncu_spc3_core_enable_status(ncu_spc3_core_enable_status), | |
8758 | .ncu_spc4_core_enable_status(ncu_spc4_core_enable_status), | |
8759 | .ncu_spc5_core_enable_status(ncu_spc5_core_enable_status), | |
8760 | .ncu_spc6_core_enable_status(ncu_spc6_core_enable_status), | |
8761 | .ncu_spc7_core_enable_status(ncu_spc7_core_enable_status), | |
8762 | .tcu_pce_ov(tcu_pce_ov), | |
8763 | .tcu_aclk(tcu_aclk), | |
8764 | .tcu_bclk(tcu_bclk), | |
8765 | .tcu_scan_en(tcu_scan_en), | |
8766 | .tcu_muxtest(tcu_muxtest), | |
8767 | .tcu_dectest(tcu_dectest), | |
8768 | .tcu_atpg_mode(tcu_atpg_mode), | |
8769 | .tcu_se_scancollar_in(tcu_se_scancollar_in), | |
8770 | .tcu_se_scancollar_out(tcu_se_scancollar_out), | |
8771 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit), | |
8772 | .tcu_array_bypass(tcu_array_bypass), | |
8773 | .cluster_arst_l(cluster_arst_l), | |
8774 | .tcu_mbist_user_mode(tcu_mbist_user_mode) | |
8775 | ); | |
8776 | //________________________________________________________________ | |
8777 | ||
8778 | /////// stagging flop | |
8779 | ||
8780 | //assign | |
8781 | ||
8782 | l2t l2t4( | |
8783 | .ccu_slow_cmp_sync_en ( gl_io_cmp_sync_en_c1t ), | |
8784 | .ccu_cmp_slow_sync_en ( gl_cmp_io_sync_en_c1t ), | |
8785 | .l2t_lstg_in ( | |
8786 | {sii_l2t4_req[ 31 : 0 ], | |
8787 | sii_l2t4_req_vld, | |
8788 | sii_l2t5_req[ 31 : 0 ], | |
8789 | sii_l2t5_req_vld, | |
8790 | 4'b0, | |
8791 | sii_l2b4_ecc[ 6 : 0 ], | |
8792 | l2b0_sio_data_t1rff[ 31 : 0 ], | |
8793 | // l2b0_sio_parity_t1rff[1:0], | |
8794 | l2b0_sio_ctag_vld_t1rff, | |
8795 | l2b0_sio_ue_err_t1rff, | |
8796 | 37'b0, | |
8797 | l2t5_mcu2_rd_req, | |
8798 | l2t5_mcu2_rd_dummy_req, | |
8799 | l2t5_mcu2_rd_req_id[ 2 : 0 ], | |
8800 | l2t5_mcu2_wr_req, | |
8801 | l2t5_mcu2_addr_5, | |
8802 | l2t5_mcu2_addr[ 39 : 31 ], | |
8803 | 4'b0, | |
8804 | l2t5_mcu2_addr[ 30 : 7 ] | |
8805 | } | |
8806 | ), | |
8807 | .l2t_rstg_in ( | |
8808 | {77'b0, | |
8809 | l2b4_sio_data[ 31 : 0 ], | |
8810 | l2b4_sio_parity[ 1 : 0 ], | |
8811 | l2b4_sio_ctag_vld, | |
8812 | l2b4_sio_ue_err, | |
8813 | 79'b0 | |
8814 | } | |
8815 | ), | |
8816 | .l2t_lstg_out ( | |
8817 | {sii_l2t4_req_t4lff[ 31 : 0 ], | |
8818 | sii_l2t4_req_vld_t4lff, | |
8819 | sii_l2t5_req_t4lff[ 31 : 0 ], | |
8820 | sii_l2t5_req_vld_t4lff, | |
8821 | unconnectedt4lff[ 125 : 122 ], | |
8822 | sii_l2b4_ecc_t4lff[ 6 : 0 ], | |
8823 | l2b0_sio_data_t4lff[ 31 : 0 ], | |
8824 | // l2b0_sio_parity_t4lff[1:0], | |
8825 | l2b0_sio_ctag_vld_t4lff, | |
8826 | l2b0_sio_ue_err_t4lff, | |
8827 | unconnectedt4lff[ 80 : 44 ], | |
8828 | l2t5_mcu2_rd_req_t4lff, | |
8829 | l2t5_mcu2_rd_dummy_req_t4lff, | |
8830 | l2t5_mcu2_rd_req_id_t4lff[ 2 : 0 ], | |
8831 | l2t5_mcu2_wr_req_t4lff, | |
8832 | l2t5_mcu2_addr_5_t4lff, | |
8833 | l2t5_mcu2_addr_t4lff[ 39 : 31 ], | |
8834 | unconnectedt4lff[ 27 : 24 ], | |
8835 | l2t5_mcu2_addr_t4lff[ 30 : 7 ] | |
8836 | } | |
8837 | ), | |
8838 | .l2t_rstg_out ( | |
8839 | {unconnectedt4rff[ 191 : 115 ], | |
8840 | l2b4_sio_data_t4rff[ 31 : 0 ], | |
8841 | l2b4_sio_parity_t4rff[ 1 : 0 ], | |
8842 | l2b4_sio_ctag_vld_t4rff, | |
8843 | l2b4_sio_ue_err_t4rff, | |
8844 | unconnectedt4rff[ 78 : 0 ] | |
8845 | } | |
8846 | ), | |
8847 | .l2t_siu_delay (1'b0), | |
8848 | .l2t_tcu_dmo_out_prev (l2t5_dmo_dout[ 38 : 0 ] ), | |
8849 | .l2t_tcu_dmo_out (l2t4_dmo_dout[ 38 : 0 ] ), | |
8850 | .tcu_l2t_coresel (dmo_l2tsel[ 3 ] ), | |
8851 | .tcu_l2t_tag_or_data_sel (dmo_tagmuxctl ), | |
8852 | .l2t_dbg_sii_iq_dequeue (l2t4_dbg1_sii_iq_dequeue ), | |
8853 | .l2t_dbg_sii_wib_dequeue (l2t4_dbg1_sii_wib_dequeue ), | |
8854 | .l2t_dbg_xbar_vcid (l2t4_dbg1_xbar_vcid[ 5 : 0 ] ), | |
8855 | .l2t_dbg_err_event (l2t4_dbg1_err_event ), | |
8856 | .l2t_dbg_pa_match (l2t4_dbg1_pa_match ), | |
8857 | .l2t_cpx_req_cq (sctag4_cpx_req_cq[ 7 : 0 ] ),// sctag | |
8858 | .l2t_cpx_atom_cq (sctag4_cpx_atom_cq ), | |
8859 | .l2t_cpx_data_ca (sctag4_cpx_data_ca[ 145 : 0 ]), | |
8860 | .l2t_pcx_stall_pq (sctag4_pcx_stall_pq ), | |
8861 | .pcx_l2t_data_rdy_px1 (pcx_sctag4_data_rdy_px1 ), | |
8862 | .pcx_l2t_data_px2 (pcx_sctag4_data_px2[ 129 : 0 ]), | |
8863 | .pcx_l2t_atm_px1 (pcx_sctag4_atm_px1 ), | |
8864 | .cpx_l2t_grant_cx (cpx_sctag4_grant_cx[ 7 : 0 ] ), | |
8865 | .l2t_rst_fatal_error (l2t4_rst_fatal_error), | |
8866 | .rst_wmr_protect (rst_wmr_protect ), | |
8867 | .l2t_l2d_way_sel_c2 (l2t4_l2d4_way_sel_c2 ), | |
8868 | .l2t_l2d_rd_wr_c2 (l2t4_l2d4_rd_wr_c2 ), | |
8869 | .l2t_l2d_set_c2 (l2t4_l2d4_set_c2[ 8 : 0 ] ), | |
8870 | .l2t_l2d_col_offset_c2 (l2t4_l2d4_col_offset_c2[ 3 : 0 ]), | |
8871 | .l2t_l2d_word_en_c2 (l2t4_l2d4_word_en_c2 ), | |
8872 | .l2t_l2d_fbrd_c3 (l2t4_l2d4_fbrd_c3 ), | |
8873 | .l2t_l2d_fb_hit_c3 (l2t4_l2d4_fb_hit_c3 ), | |
8874 | .l2t_l2d_stdecc_c2 (l2t4_l2d4_stdecc_c2[ 77 : 0 ] ), | |
8875 | .l2d_l2t_decc_c6 (l2d4_l2t4_decc_c6 ), | |
8876 | // .l2t_l2b_stdecc_c3 (l2t4_l2b4_stdecc_c3[77:0] ), | |
8877 | .l2t_l2b_fbrd_en_c3 (l2t4_l2b4_fbrd_en_c3 ), | |
8878 | .l2t_l2b_fbrd_wl_c3 (l2t4_l2b4_fbrd_wl_c3[ 2 : 0 ] ), | |
8879 | .l2t_l2b_fbwr_wen_r2 (l2t4_l2b4_fbwr_wen_r2[ 15 : 0 ] ), | |
8880 | .l2t_l2b_fbwr_wl_r2 (l2t4_l2b4_fbwr_wl_r2[ 2 : 0 ] ), | |
8881 | .l2t_l2b_fbd_stdatasel_c3 (l2t4_l2b4_fbd_stdatasel_c3 ), | |
8882 | .l2t_l2b_wbwr_wen_c6 (l2t4_l2b4_wbwr_wen_c6[ 3 : 0 ] ), | |
8883 | .l2t_l2b_wbwr_wl_c6 (l2t4_l2b4_wbwr_wl_c6[ 2 : 0 ] ), | |
8884 | .l2t_l2b_wbrd_en_r0 (l2t4_l2b4_wbrd_en_r0 ), | |
8885 | .l2t_l2b_wbrd_wl_r0 (l2t4_l2b4_wbrd_wl_r0[ 2 : 0 ] ), | |
8886 | .l2t_l2b_ev_dword_r0 (l2t4_l2b4_ev_dword_r0[ 2 : 0 ] ), | |
8887 | .l2t_l2b_evict_en_r0 (l2t4_l2b4_evict_en_r0 ), | |
8888 | .l2b_l2t_ev_uerr_r5 (l2b4_l2t4_ev_uerr_r5 ), | |
8889 | .l2b_l2t_ev_cerr_r5 (l2b4_l2t4_ev_cerr_r5 ), | |
8890 | .l2t_l2b_rdma_wren_s2 (l2t4_l2b4_rdma_wren_s2[ 15 : 0 ]), | |
8891 | .l2t_l2b_rdma_wrwl_s2 (l2t4_l2b4_rdma_wrwl_s2[ 1 : 0 ] ), | |
8892 | .l2t_l2b_rdma_rdwl_r0 (l2t4_l2b4_rdma_rdwl_r0[ 1 : 0 ] ), | |
8893 | .l2t_l2b_rdma_rden_r0 (l2t4_l2b4_rdma_rden_r0 ), | |
8894 | .l2t_l2b_ctag_en_c7 (l2t4_l2b4_ctag_en_c7 ), | |
8895 | .l2t_l2b_ctag_c7 (l2t4_l2b4_ctag_c7[ 31 : 0 ] ), | |
8896 | .l2t_l2b_word_c7 (l2t4_l2b4_word_c7[ 3 : 0 ] ), | |
8897 | .l2t_l2b_req_en_c7 (l2t4_l2b4_req_en_c7 ), | |
8898 | .l2t_l2b_word_vld_c7 (l2t4_l2b4_word_vld_c7 ), | |
8899 | .l2b_l2t_rdma_uerr_c10 (l2b4_l2t4_rdma_uerr_c10 ), | |
8900 | .l2b_l2t_rdma_cerr_c10 (l2b4_l2t4_rdma_cerr_c10 ), | |
8901 | .l2b_l2t_rdma_notdata_c10 (l2b4_l2t4_rdma_notdata_c10 ), | |
8902 | .l2t_mcu_rd_req (l2t4_mcu2_rd_req ), | |
8903 | .l2t_mcu_rd_dummy_req (l2t4_mcu2_rd_dummy_req ), | |
8904 | .l2t_mcu_rd_req_id (l2t4_mcu2_rd_req_id[ 2 : 0 ] ), | |
8905 | .l2t_mcu_addr (l2t4_mcu2_addr[ 39 : 7 ] ), | |
8906 | .l2t_mcu_addr_5 (l2t4_mcu2_addr_5 ), | |
8907 | .l2t_mcu_wr_req (l2t4_mcu2_wr_req ), | |
8908 | .mcu_l2t_rd_ack (mcu2_l2t4_rd_ack ), | |
8909 | .mcu_l2t_wr_ack (mcu2_l2t4_wr_ack ), | |
8910 | .mcu_l2t_chunk_id_r0 (mcu2_l2t4_qword_id_r0[ 1 : 0 ] ), | |
8911 | .mcu_l2t_data_vld_r0 (mcu2_l2t4_data_vld_r0 ), | |
8912 | .mcu_l2t_rd_req_id_r0 (mcu2_l2t4_rd_req_id_r0[ 2 : 0 ] ), | |
8913 | .mcu_l2t_secc_err_r2 (mcu2_l2t4_secc_err_r2 ), | |
8914 | .mcu_l2t_mecc_err_r2 (mcu2_l2t4_mecc_err_r2 ), | |
8915 | .mcu_l2t_scb_mecc_err (mcu2_l2t4_scb_mecc_err ), | |
8916 | .mcu_l2t_scb_secc_err (mcu2_l2t4_scb_secc_err ), | |
8917 | .sii_l2t_req_vld (sii_l2t4_req_vld_t4lff ), | |
8918 | .sii_l2t_req (sii_l2t4_req_t4lff[ 31 : 0 ] ), | |
8919 | .sii_l2b_ecc (sii_l2b4_ecc_t4lff[ 6 : 0 ] ), | |
8920 | .l2t_sii_iq_dequeue (l2t4_sii_iq_dequeue ), | |
8921 | .l2t_sii_wib_dequeue (l2t4_sii_wib_dequeue ), | |
8922 | .rst_por_ ( gl_rst_l2_por_c1m ), // ( gl_l2_por_c1t ), - for int6.1 | |
8923 | .rst_wmr_ ( gl_rst_l2_wmr_c1m ), // ( gl_l2_wmr_c1t ), - for int6.1 | |
8924 | .scan_in (tcu_soc2_scan_out ), | |
8925 | .scan_out (l2t4_scan_out ), | |
8926 | .tcu_mbist_bisi_en (tcu_mbist_bisi_en ), | |
8927 | .tcu_l2t_mbist_start (tcu_l2t4_mbist_start), | |
8928 | .tcu_l2t_mbist_scan_in (tcu_l2t4_mbist_scan_in ), | |
8929 | .l2t_tcu_mbist_done (l2t4_tcu_mbist_done), | |
8930 | .l2t_tcu_mbist_fail (l2t4_tcu_mbist_fail), | |
8931 | .l2t_tcu_mbist_scan_out (l2t4_tcu_mbist_scan_out ), | |
8932 | .efu_l2t_fuse_clr (efu_l2t4_fuse_clr ), | |
8933 | .efu_l2t_fuse_xfer_en (efu_l2t4_fuse_xfer_en ), | |
8934 | .efu_l2t_fuse_data (efu_l2t0246_fuse_data ), | |
8935 | .l2t_efu_fuse_data (l2t4_efu_fuse_data ), | |
8936 | .l2t_efu_fuse_xfer_en (l2t4_efu_fuse_xfer_en ), | |
8937 | .gclk ( cmp_gclk_c1_l2t4 ), // cmp_gclk_c2_r[2]), | |
8938 | .tcu_clk_stop ( gl_l2t4_clk_stop ), // staged clk_stop | |
8939 | .tcu_l2t_shscan_scan_in (tcu_l2t4_shscan_scan_in ), | |
8940 | .tcu_l2t_shscan_aclk (tcu_l2t_shscan_aclk ), | |
8941 | .tcu_l2t_shscan_bclk (tcu_l2t_shscan_bclk ), | |
8942 | .tcu_l2t_shscan_scan_en (tcu_l2t_shscan_scan_en ), | |
8943 | .tcu_l2t_shscan_pce_ov (tcu_l2t_shscan_pce_ov ), | |
8944 | .l2t_tcu_shscan_scan_out (l2t4_tcu_shscan_scan_out), | |
8945 | .tcu_l2t_shscan_clk_stop (tcu_l2t4_shscan_clk_stop), | |
8946 | .vnw_ary (L2T_VNW[ 4 ]), | |
8947 | .l2t_rep_in0 (24'b0), | |
8948 | .l2t_rep_in1 (24'b0), | |
8949 | .l2t_rep_in2 (24'b0), | |
8950 | .l2t_rep_in3 (24'b0), | |
8951 | .l2t_rep_in4 (24'b0), | |
8952 | .l2t_rep_in5 (24'b0), | |
8953 | .l2t_rep_in6 (24'b0), | |
8954 | .l2t_rep_in7 (24'b0), | |
8955 | .l2t_rep_in8 (24'b0), | |
8956 | .l2t_rep_in9 (24'b0), | |
8957 | .l2t_rep_in10 (24'b0), | |
8958 | .l2t_rep_in11 (24'b0), | |
8959 | .l2t_rep_in12 (24'b0), | |
8960 | .l2t_rep_in13 (24'b0), | |
8961 | .l2t_rep_in14 (24'b0), | |
8962 | .l2t_rep_in15 (24'b0), | |
8963 | .l2t_rep_in16 (24'b0), | |
8964 | .l2t_rep_in17 (24'b0), | |
8965 | .l2t_rep_in18 (24'b0), | |
8966 | .l2t_rep_in19 (24'b0), | |
8967 | .l2t_rep_out0 (l2t4_rep_out0_unused[ 23 : 0 ]), | |
8968 | .l2t_rep_out1 (l2t4_rep_out1_unused[ 23 : 0 ]), | |
8969 | .l2t_rep_out2 (l2t4_rep_out2_unused[ 23 : 0 ]), | |
8970 | .l2t_rep_out3 (l2t4_rep_out3_unused[ 23 : 0 ]), | |
8971 | .l2t_rep_out4 (l2t4_rep_out4_unused[ 23 : 0 ]), | |
8972 | .l2t_rep_out5 (l2t4_rep_out5_unused[ 23 : 0 ]), | |
8973 | .l2t_rep_out6 (l2t4_rep_out6_unused[ 23 : 0 ]), | |
8974 | .l2t_rep_out7 (l2t4_rep_out7_unused[ 23 : 0 ]), | |
8975 | .l2t_rep_out8 (l2t4_rep_out8_unused[ 23 : 0 ]), | |
8976 | .l2t_rep_out9 (l2t4_rep_out9_unused[ 23 : 0 ]), | |
8977 | .l2t_rep_out10 (l2t4_rep_out10_unused[ 23 : 0 ]), | |
8978 | .l2t_rep_out11 (l2t4_rep_out11_unused[ 23 : 0 ]), | |
8979 | .l2t_rep_out12 (l2t4_rep_out12_unused[ 23 : 0 ]), | |
8980 | .l2t_rep_out13 (l2t4_rep_out13_unused[ 23 : 0 ]), | |
8981 | .l2t_rep_out14 (l2t4_rep_out14_unused[ 23 : 0 ]), | |
8982 | .l2t_rep_out15 (l2t4_rep_out15_unused[ 23 : 0 ]), | |
8983 | .l2t_rep_out16 (l2t4_rep_out16_unused[ 23 : 0 ]), | |
8984 | .l2t_rep_out17 (l2t4_rep_out17_unused[ 23 : 0 ]), | |
8985 | .l2t_rep_out18 (l2t4_rep_out18_unused[ 23 : 0 ]), | |
8986 | .l2t_rep_out19 (l2t4_rep_out19_unused[ 23 : 0 ]), | |
8987 | .ncu_l2t_pm(ncu_l2t_pm), | |
8988 | .ncu_l2t_ba01(ncu_l2t_ba01), | |
8989 | .ncu_l2t_ba23(ncu_l2t_ba23), | |
8990 | .ncu_l2t_ba45(ncu_l2t_ba45), | |
8991 | .ncu_l2t_ba67(ncu_l2t_ba67), | |
8992 | .ncu_spc0_core_enable_status(ncu_spc0_core_enable_status), | |
8993 | .ncu_spc1_core_enable_status(ncu_spc1_core_enable_status), | |
8994 | .ncu_spc2_core_enable_status(ncu_spc2_core_enable_status), | |
8995 | .ncu_spc3_core_enable_status(ncu_spc3_core_enable_status), | |
8996 | .ncu_spc4_core_enable_status(ncu_spc4_core_enable_status), | |
8997 | .ncu_spc5_core_enable_status(ncu_spc5_core_enable_status), | |
8998 | .ncu_spc6_core_enable_status(ncu_spc6_core_enable_status), | |
8999 | .ncu_spc7_core_enable_status(ncu_spc7_core_enable_status), | |
9000 | .tcu_pce_ov(tcu_pce_ov), | |
9001 | .tcu_aclk(tcu_aclk), | |
9002 | .tcu_bclk(tcu_bclk), | |
9003 | .tcu_scan_en(tcu_scan_en), | |
9004 | .tcu_muxtest(tcu_muxtest), | |
9005 | .tcu_dectest(tcu_dectest), | |
9006 | .tcu_atpg_mode(tcu_atpg_mode), | |
9007 | .tcu_se_scancollar_in(tcu_se_scancollar_in), | |
9008 | .tcu_se_scancollar_out(tcu_se_scancollar_out), | |
9009 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit), | |
9010 | .tcu_array_bypass(tcu_array_bypass), | |
9011 | .cluster_arst_l(cluster_arst_l), | |
9012 | .tcu_mbist_user_mode(tcu_mbist_user_mode) | |
9013 | ); | |
9014 | //________________________________________________________________ | |
9015 | ||
9016 | /////// stagging flop | |
9017 | ||
9018 | //assign | |
9019 | ||
9020 | l2t l2t5( | |
9021 | .ccu_slow_cmp_sync_en ( gl_io_cmp_sync_en_c2t ), | |
9022 | .ccu_cmp_slow_sync_en ( gl_cmp_io_sync_en_c2t ), | |
9023 | .l2t_lstg_in ( | |
9024 | {mcu1_tcu_mbist_fail, | |
9025 | 1'b0, ncu_tcu_mbist_done[ 0 ], | |
9026 | 1'b0, ncu_tcu_mbist_fail[ 0 ], | |
9027 | 106'b0, | |
9028 | l2b0_sio_parity_t0rff[ 1 : 0 ], | |
9029 | l2t0_tcu_mbist_done, | |
9030 | l2t0_tcu_mbist_fail, | |
9031 | spc0_tcu_mbist_done, | |
9032 | spc0_tcu_mbist_fail, | |
9033 | 6'b0, | |
9034 | mcu0_tcu_mbist_done, | |
9035 | mcu0_tcu_mbist_fail, | |
9036 | mcu1_tcu_mbist_done, | |
9037 | // mcu1_tcu_mbist_fail, | |
9038 | 16'b0, | |
9039 | 22'b0, | |
9040 | spc0_softstop_request, | |
9041 | spc0_hardstop_request, | |
9042 | spc0_trigger_pulse, | |
9043 | spc0_ss_complete, | |
9044 | 24'b0 | |
9045 | } | |
9046 | ), | |
9047 | .l2t_rstg_in ( | |
9048 | {136'b0, | |
9049 | mcu2_l2t5_rd_ack, | |
9050 | mcu2_l2t5_wr_ack, | |
9051 | mcu2_l2t5_qword_id_r0[ 1 : 0 ], | |
9052 | mcu2_l2t5_data_vld_r0, | |
9053 | mcu2_l2t5_rd_req_id_r0[ 2 : 0 ], | |
9054 | mcu2_l2t5_secc_err_r2, | |
9055 | mcu2_l2t5_mecc_err_r2, | |
9056 | mcu2_l2t5_scb_mecc_err, | |
9057 | mcu2_l2t5_scb_secc_err, | |
9058 | 44'b0 | |
9059 | } | |
9060 | ), | |
9061 | .l2t_lstg_out ( | |
9062 | {mcu1_tcu_mbist_fail_t5lff, | |
9063 | unconnectedt5lff[ 190 ], | |
9064 | ncu_tcu_mbist_done_t5lff_0, | |
9065 | unconnectedt5lff[ 188 ], | |
9066 | ncu_tcu_mbist_fail_t5lff_0, | |
9067 | unconnectedt5lff[ 186 : 81 ], | |
9068 | l2b0_sio_parity_t5lff[ 1 : 0 ], | |
9069 | l2t0_tcu_mbist_done_t5lff, | |
9070 | l2t0_tcu_mbist_fail_t5lff, | |
9071 | spc0_tcu_mbist_done_t5lff, | |
9072 | spc0_tcu_mbist_fail_t5lff, | |
9073 | unconnectedt5lff[ 74 : 69 ], | |
9074 | mcu0_tcu_mbist_done_t5lff, | |
9075 | mcu0_tcu_mbist_fail_t5lff, | |
9076 | mcu1_tcu_mbist_done_t5lff, | |
9077 | // mcu1_tcu_mbist_fail_t5lff, | |
9078 | unconnectedt5lff[ 65 : 28 ], | |
9079 | spc0_softstop_request_t5lff, | |
9080 | spc0_hardstop_request_t5lff, | |
9081 | spc0_trigger_pulse_t5lff, | |
9082 | spc0_ss_complete_t5lff, | |
9083 | unconnectedt5lff[ 23 : 0 ] | |
9084 | } | |
9085 | ), | |
9086 | .l2t_rstg_out ( | |
9087 | {unconnectedt5rff[ 191 : 56 ], | |
9088 | mcu2_l2t5_rd_ack_t5rff, | |
9089 | mcu2_l2t5_wr_ack_t5rff, | |
9090 | mcu2_l2t5_qword_id_r0_t5rff[ 1 : 0 ], | |
9091 | mcu2_l2t5_data_vld_r0_t5rff, | |
9092 | mcu2_l2t5_rd_req_id_r0_t5rff[ 2 : 0 ], | |
9093 | mcu2_l2t5_secc_err_r2_t5rff, | |
9094 | mcu2_l2t5_mecc_err_r2_t5rff, | |
9095 | mcu2_l2t5_scb_mecc_err_t5rff, | |
9096 | mcu2_l2t5_scb_secc_err_t5rff, | |
9097 | unconnectedt5rff[ 43 : 0 ] | |
9098 | } | |
9099 | ), | |
9100 | .l2t_siu_delay (1'b0), | |
9101 | .l2t_tcu_dmo_out_prev (l2t1_dmo_dout[ 38 : 0 ] ), | |
9102 | .l2t_tcu_dmo_out (l2t5_dmo_dout[ 38 : 0 ] ), | |
9103 | .tcu_l2t_coresel (dmo_l2tsel[ 4 ] ), | |
9104 | .tcu_l2t_tag_or_data_sel (dmo_tagmuxctl ), | |
9105 | .l2t_dbg_sii_iq_dequeue (l2t5_dbg1_sii_iq_dequeue ), | |
9106 | .l2t_dbg_sii_wib_dequeue (l2t5_dbg1_sii_wib_dequeue ), | |
9107 | .l2t_dbg_xbar_vcid (l2t5_dbg1_xbar_vcid[ 5 : 0 ] ), | |
9108 | .l2t_dbg_err_event (l2t5_dbg1_err_event ), | |
9109 | .l2t_dbg_pa_match (l2t5_dbg1_pa_match ), | |
9110 | .l2t_cpx_req_cq (sctag5_cpx_req_cq[ 7 : 0 ] ),// sctag | |
9111 | .l2t_cpx_atom_cq (sctag5_cpx_atom_cq ), | |
9112 | .l2t_cpx_data_ca (sctag5_cpx_data_ca[ 145 : 0 ]), | |
9113 | .l2t_pcx_stall_pq (sctag5_pcx_stall_pq ), | |
9114 | .pcx_l2t_data_rdy_px1 (pcx_sctag5_data_rdy_px1 ), | |
9115 | .pcx_l2t_data_px2 (pcx_sctag5_data_px2[ 129 : 0 ]), | |
9116 | .pcx_l2t_atm_px1 (pcx_sctag5_atm_px1 ), | |
9117 | .cpx_l2t_grant_cx (cpx_sctag5_grant_cx[ 7 : 0 ] ), | |
9118 | .l2t_rst_fatal_error (l2t5_rst_fatal_error), | |
9119 | .rst_wmr_protect (rst_wmr_protect ), | |
9120 | .l2t_l2d_way_sel_c2 (l2t5_l2d5_way_sel_c2 ), | |
9121 | .l2t_l2d_rd_wr_c2 (l2t5_l2d5_rd_wr_c2 ), | |
9122 | .l2t_l2d_set_c2 (l2t5_l2d5_set_c2[ 8 : 0 ] ), | |
9123 | .l2t_l2d_col_offset_c2 (l2t5_l2d5_col_offset_c2[ 3 : 0 ]), | |
9124 | .l2t_l2d_word_en_c2 (l2t5_l2d5_word_en_c2 ), | |
9125 | .l2t_l2d_fbrd_c3 (l2t5_l2d5_fbrd_c3 ), | |
9126 | .l2t_l2d_fb_hit_c3 (l2t5_l2d5_fb_hit_c3 ), | |
9127 | .l2t_l2d_stdecc_c2 (l2t5_l2d5_stdecc_c2[ 77 : 0 ] ), | |
9128 | .l2d_l2t_decc_c6 (l2d5_l2t5_decc_c6 ), | |
9129 | // .l2t_l2b_stdecc_c3 (l2t5_l2b5_stdecc_c3[77:0] ), | |
9130 | .l2t_l2b_fbrd_en_c3 (l2t5_l2b5_fbrd_en_c3 ), | |
9131 | .l2t_l2b_fbrd_wl_c3 (l2t5_l2b5_fbrd_wl_c3[ 2 : 0 ] ), | |
9132 | .l2t_l2b_fbwr_wen_r2 (l2t5_l2b5_fbwr_wen_r2[ 15 : 0 ] ), | |
9133 | .l2t_l2b_fbwr_wl_r2 (l2t5_l2b5_fbwr_wl_r2[ 2 : 0 ] ), | |
9134 | .l2t_l2b_fbd_stdatasel_c3 (l2t5_l2b5_fbd_stdatasel_c3 ), | |
9135 | .l2t_l2b_wbwr_wen_c6 (l2t5_l2b5_wbwr_wen_c6[ 3 : 0 ] ), | |
9136 | .l2t_l2b_wbwr_wl_c6 (l2t5_l2b5_wbwr_wl_c6[ 2 : 0 ] ), | |
9137 | .l2t_l2b_wbrd_en_r0 (l2t5_l2b5_wbrd_en_r0 ), | |
9138 | .l2t_l2b_wbrd_wl_r0 (l2t5_l2b5_wbrd_wl_r0[ 2 : 0 ] ), | |
9139 | .l2t_l2b_ev_dword_r0 (l2t5_l2b5_ev_dword_r0[ 2 : 0 ] ), | |
9140 | .l2t_l2b_evict_en_r0 (l2t5_l2b5_evict_en_r0 ), | |
9141 | .l2b_l2t_ev_uerr_r5 (l2b5_l2t5_ev_uerr_r5 ), | |
9142 | .l2b_l2t_ev_cerr_r5 (l2b5_l2t5_ev_cerr_r5 ), | |
9143 | .l2t_l2b_rdma_wren_s2 (l2t5_l2b5_rdma_wren_s2[ 15 : 0 ]), | |
9144 | .l2t_l2b_rdma_wrwl_s2 (l2t5_l2b5_rdma_wrwl_s2[ 1 : 0 ] ), | |
9145 | .l2t_l2b_rdma_rdwl_r0 (l2t5_l2b5_rdma_rdwl_r0[ 1 : 0 ] ), | |
9146 | .l2t_l2b_rdma_rden_r0 (l2t5_l2b5_rdma_rden_r0 ), | |
9147 | .l2t_l2b_ctag_en_c7 (l2t5_l2b5_ctag_en_c7 ), | |
9148 | .l2t_l2b_ctag_c7 (l2t5_l2b5_ctag_c7[ 31 : 0 ] ), | |
9149 | .l2t_l2b_word_c7 (l2t5_l2b5_word_c7[ 3 : 0 ] ), | |
9150 | .l2t_l2b_req_en_c7 (l2t5_l2b5_req_en_c7 ), | |
9151 | .l2t_l2b_word_vld_c7 (l2t5_l2b5_word_vld_c7 ), | |
9152 | .l2b_l2t_rdma_uerr_c10 (l2b5_l2t5_rdma_uerr_c10 ), | |
9153 | .l2b_l2t_rdma_cerr_c10 (l2b5_l2t5_rdma_cerr_c10 ), | |
9154 | .l2b_l2t_rdma_notdata_c10 (l2b5_l2t5_rdma_notdata_c10 ), | |
9155 | .l2t_mcu_rd_req (l2t5_mcu2_rd_req ), | |
9156 | .l2t_mcu_rd_dummy_req (l2t5_mcu2_rd_dummy_req ), | |
9157 | .l2t_mcu_rd_req_id (l2t5_mcu2_rd_req_id[ 2 : 0 ] ), | |
9158 | .l2t_mcu_addr (l2t5_mcu2_addr[ 39 : 7 ] ), | |
9159 | .l2t_mcu_addr_5 (l2t5_mcu2_addr_5 ), | |
9160 | .l2t_mcu_wr_req (l2t5_mcu2_wr_req ), | |
9161 | .mcu_l2t_rd_ack (mcu2_l2t5_rd_ack_t5rff ), | |
9162 | .mcu_l2t_wr_ack (mcu2_l2t5_wr_ack_t5rff ), | |
9163 | .mcu_l2t_chunk_id_r0 (mcu2_l2t5_qword_id_r0_t5rff[ 1 : 0 ] ), | |
9164 | .mcu_l2t_data_vld_r0 (mcu2_l2t5_data_vld_r0_t5rff ), | |
9165 | .mcu_l2t_rd_req_id_r0 (mcu2_l2t5_rd_req_id_r0_t5rff[ 2 : 0 ] ), | |
9166 | .mcu_l2t_secc_err_r2 (mcu2_l2t5_secc_err_r2_t5rff ), | |
9167 | .mcu_l2t_mecc_err_r2 (mcu2_l2t5_mecc_err_r2_t5rff ), | |
9168 | .mcu_l2t_scb_mecc_err (mcu2_l2t5_scb_mecc_err_t5rff ), | |
9169 | .mcu_l2t_scb_secc_err (mcu2_l2t5_scb_secc_err_t5rff ), | |
9170 | .sii_l2t_req_vld (sii_l2t5_req_vld_t4lff ), | |
9171 | .sii_l2t_req (sii_l2t5_req_t4lff[ 31 : 0 ] ), | |
9172 | .sii_l2b_ecc (sii_l2b5_ecc_ccxrff[ 6 : 0 ] ), | |
9173 | .l2t_sii_iq_dequeue (l2t5_sii_iq_dequeue ), | |
9174 | .l2t_sii_wib_dequeue (l2t5_sii_wib_dequeue ), | |
9175 | .rst_por_ ( gl_l2_por_c2t ), | |
9176 | .rst_wmr_ ( gl_l2_wmr_c2t ), | |
9177 | .scan_in (l2t4_scan_out ), | |
9178 | .scan_out (l2t5_scan_out ), | |
9179 | .tcu_mbist_bisi_en (tcu_mbist_bisi_en ), | |
9180 | .tcu_l2t_mbist_start (tcu_l2t5_mbist_start), | |
9181 | .tcu_l2t_mbist_scan_in (tcu_l2t5_mbist_scan_in ), | |
9182 | .l2t_tcu_mbist_done (l2t5_tcu_mbist_done), | |
9183 | .l2t_tcu_mbist_fail (l2t5_tcu_mbist_fail), | |
9184 | .l2t_tcu_mbist_scan_out (l2t5_tcu_mbist_scan_out ), | |
9185 | .efu_l2t_fuse_clr (efu_l2t5_fuse_clr ), | |
9186 | .efu_l2t_fuse_xfer_en (efu_l2t5_fuse_xfer_en ), | |
9187 | .efu_l2t_fuse_data (efu_l2t1357_fuse_data ), | |
9188 | .l2t_efu_fuse_data (l2t5_efu_fuse_data ), | |
9189 | .l2t_efu_fuse_xfer_en (l2t5_efu_fuse_xfer_en ), | |
9190 | .gclk ( cmp_gclk_c2_l2t5 ), | |
9191 | .tcu_clk_stop ( gl_l2t5_clk_stop ), // staged clk_stop | |
9192 | .tcu_l2t_shscan_scan_in (tcu_l2t5_shscan_scan_in ), | |
9193 | .tcu_l2t_shscan_aclk (tcu_l2t_shscan_aclk ), | |
9194 | .tcu_l2t_shscan_bclk (tcu_l2t_shscan_bclk ), | |
9195 | .tcu_l2t_shscan_scan_en (tcu_l2t_shscan_scan_en ), | |
9196 | .tcu_l2t_shscan_pce_ov (tcu_l2t_shscan_pce_ov ), | |
9197 | .l2t_tcu_shscan_scan_out (l2t5_tcu_shscan_scan_out), | |
9198 | .tcu_l2t_shscan_clk_stop (tcu_l2t5_shscan_clk_stop), | |
9199 | .vnw_ary (L2T_VNW[ 5 ]), | |
9200 | .l2t_rep_in0 (24'b0), | |
9201 | .l2t_rep_in1 (24'b0), | |
9202 | .l2t_rep_in2 (24'b0), | |
9203 | .l2t_rep_in3 (24'b0), | |
9204 | .l2t_rep_in4 (24'b0), | |
9205 | .l2t_rep_in5 (24'b0), | |
9206 | .l2t_rep_in6 (24'b0), | |
9207 | .l2t_rep_in7 (24'b0), | |
9208 | .l2t_rep_in8 (24'b0), | |
9209 | .l2t_rep_in9 (24'b0), | |
9210 | .l2t_rep_in10 (24'b0), | |
9211 | .l2t_rep_in11 (24'b0), | |
9212 | .l2t_rep_in12 (24'b0), | |
9213 | .l2t_rep_in13 (24'b0), | |
9214 | .l2t_rep_in14 (24'b0), | |
9215 | .l2t_rep_in15 (24'b0), | |
9216 | .l2t_rep_in16 (24'b0), | |
9217 | .l2t_rep_in17 (24'b0), | |
9218 | .l2t_rep_in18 (24'b0), | |
9219 | .l2t_rep_in19 (24'b0), | |
9220 | .l2t_rep_out0 (l2t5_rep_out0_unused[ 23 : 0 ]), | |
9221 | .l2t_rep_out1 (l2t5_rep_out1_unused[ 23 : 0 ]), | |
9222 | .l2t_rep_out2 (l2t5_rep_out2_unused[ 23 : 0 ]), | |
9223 | .l2t_rep_out3 (l2t5_rep_out3_unused[ 23 : 0 ]), | |
9224 | .l2t_rep_out4 (l2t5_rep_out4_unused[ 23 : 0 ]), | |
9225 | .l2t_rep_out5 (l2t5_rep_out5_unused[ 23 : 0 ]), | |
9226 | .l2t_rep_out6 (l2t5_rep_out6_unused[ 23 : 0 ]), | |
9227 | .l2t_rep_out7 (l2t5_rep_out7_unused[ 23 : 0 ]), | |
9228 | .l2t_rep_out8 (l2t5_rep_out8_unused[ 23 : 0 ]), | |
9229 | .l2t_rep_out9 (l2t5_rep_out9_unused[ 23 : 0 ]), | |
9230 | .l2t_rep_out10 (l2t5_rep_out10_unused[ 23 : 0 ]), | |
9231 | .l2t_rep_out11 (l2t5_rep_out11_unused[ 23 : 0 ]), | |
9232 | .l2t_rep_out12 (l2t5_rep_out12_unused[ 23 : 0 ]), | |
9233 | .l2t_rep_out13 (l2t5_rep_out13_unused[ 23 : 0 ]), | |
9234 | .l2t_rep_out14 (l2t5_rep_out14_unused[ 23 : 0 ]), | |
9235 | .l2t_rep_out15 (l2t5_rep_out15_unused[ 23 : 0 ]), | |
9236 | .l2t_rep_out16 (l2t5_rep_out16_unused[ 23 : 0 ]), | |
9237 | .l2t_rep_out17 (l2t5_rep_out17_unused[ 23 : 0 ]), | |
9238 | .l2t_rep_out18 (l2t5_rep_out18_unused[ 23 : 0 ]), | |
9239 | .l2t_rep_out19 (l2t5_rep_out19_unused[ 23 : 0 ]), | |
9240 | .ncu_l2t_pm(ncu_l2t_pm), | |
9241 | .ncu_l2t_ba01(ncu_l2t_ba01), | |
9242 | .ncu_l2t_ba23(ncu_l2t_ba23), | |
9243 | .ncu_l2t_ba45(ncu_l2t_ba45), | |
9244 | .ncu_l2t_ba67(ncu_l2t_ba67), | |
9245 | .ncu_spc0_core_enable_status(ncu_spc0_core_enable_status), | |
9246 | .ncu_spc1_core_enable_status(ncu_spc1_core_enable_status), | |
9247 | .ncu_spc2_core_enable_status(ncu_spc2_core_enable_status), | |
9248 | .ncu_spc3_core_enable_status(ncu_spc3_core_enable_status), | |
9249 | .ncu_spc4_core_enable_status(ncu_spc4_core_enable_status), | |
9250 | .ncu_spc5_core_enable_status(ncu_spc5_core_enable_status), | |
9251 | .ncu_spc6_core_enable_status(ncu_spc6_core_enable_status), | |
9252 | .ncu_spc7_core_enable_status(ncu_spc7_core_enable_status), | |
9253 | .tcu_pce_ov(tcu_pce_ov), | |
9254 | .tcu_aclk(tcu_aclk), | |
9255 | .tcu_bclk(tcu_bclk), | |
9256 | .tcu_scan_en(tcu_scan_en), | |
9257 | .tcu_muxtest(tcu_muxtest), | |
9258 | .tcu_dectest(tcu_dectest), | |
9259 | .tcu_atpg_mode(tcu_atpg_mode), | |
9260 | .tcu_se_scancollar_in(tcu_se_scancollar_in), | |
9261 | .tcu_se_scancollar_out(tcu_se_scancollar_out), | |
9262 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit), | |
9263 | .tcu_array_bypass(tcu_array_bypass), | |
9264 | .cluster_arst_l(cluster_arst_l), | |
9265 | .tcu_mbist_user_mode(tcu_mbist_user_mode) | |
9266 | ); | |
9267 | //________________________________________________________________ | |
9268 | ||
9269 | /////// stagging flop | |
9270 | ||
9271 | //assign | |
9272 | ||
9273 | l2t l2t6( | |
9274 | .ccu_slow_cmp_sync_en ( gl_io_cmp_sync_en_c1b ), | |
9275 | .ccu_cmp_slow_sync_en ( gl_cmp_io_sync_en_c1b ), | |
9276 | .l2t_lstg_in ({sii_l2t6_req[ 31 : 0 ], | |
9277 | sii_l2t6_req_vld, | |
9278 | sii_l2t7_req[ 31 : 0 ], | |
9279 | sii_l2t7_req_vld, | |
9280 | 82'b0, | |
9281 | l2t7_mcu3_rd_req, | |
9282 | l2t7_mcu3_rd_dummy_req, | |
9283 | l2t7_mcu3_rd_req_id[ 2 : 0 ], | |
9284 | l2t7_mcu3_wr_req, | |
9285 | l2t7_mcu3_addr_5, | |
9286 | l2t7_mcu3_addr[ 39 : 31 ], | |
9287 | 4'b0, | |
9288 | l2t7_mcu3_addr[ 30 : 7 ] | |
9289 | } | |
9290 | ), | |
9291 | .l2t_rstg_in (192'b0), | |
9292 | .l2t_lstg_out ( | |
9293 | {sii_l2t6_req_t6lff[ 31 : 0 ], | |
9294 | sii_l2t6_req_vld_t6lff, | |
9295 | sii_l2t7_req_t6lff[ 31 : 0 ], | |
9296 | sii_l2t7_req_vld_t6lff, | |
9297 | unconnectedt6lff[ 125 : 44 ], | |
9298 | l2t7_mcu3_rd_req_t6lff, | |
9299 | l2t7_mcu3_rd_dummy_req_t6lff, | |
9300 | l2t7_mcu3_rd_req_id_t6lff[ 2 : 0 ], | |
9301 | l2t7_mcu3_wr_req_t6lff, | |
9302 | l2t7_mcu3_addr_5_t6lff, | |
9303 | l2t7_mcu3_addr_t6lff[ 39 : 31 ], | |
9304 | unconnectedt6lff[ 27 : 24 ], | |
9305 | l2t7_mcu3_addr_t6lff[ 30 : 7 ] | |
9306 | } | |
9307 | ), | |
9308 | .l2t_rstg_out ({unconnectedt6rff[ 191 : 0 ]}), | |
9309 | .l2t_siu_delay (1'b0), | |
9310 | .l2t_tcu_dmo_out_prev (l2t7_dmo_dout[ 38 : 0 ] ), | |
9311 | .l2t_tcu_dmo_out (l2t6_dmo_dout[ 38 : 0 ] ), | |
9312 | .tcu_l2t_coresel (dmo_l2tsel[ 0 ] ), | |
9313 | .tcu_l2t_tag_or_data_sel (dmo_tagmuxctl ), | |
9314 | .l2t_dbg_sii_iq_dequeue (l2t6_dbg1_sii_iq_dequeue ), | |
9315 | .l2t_dbg_sii_wib_dequeue (l2t6_dbg1_sii_wib_dequeue ), | |
9316 | .l2t_dbg_xbar_vcid (l2t6_dbg1_xbar_vcid[ 5 : 0 ] ), | |
9317 | .l2t_dbg_err_event (l2t6_dbg1_err_event ), | |
9318 | .l2t_dbg_pa_match (l2t6_dbg1_pa_match ), | |
9319 | .l2t_cpx_req_cq (sctag6_cpx_req_cq[ 7 : 0 ] ),// sctag | |
9320 | .l2t_cpx_atom_cq (sctag6_cpx_atom_cq ), | |
9321 | .l2t_cpx_data_ca (sctag6_cpx_data_ca[ 145 : 0 ]), | |
9322 | .l2t_pcx_stall_pq (sctag6_pcx_stall_pq ), | |
9323 | .pcx_l2t_data_rdy_px1 (pcx_sctag6_data_rdy_px1 ), | |
9324 | .pcx_l2t_data_px2 (pcx_sctag6_data_px2[ 129 : 0 ]), | |
9325 | .pcx_l2t_atm_px1 (pcx_sctag6_atm_px1 ), | |
9326 | .cpx_l2t_grant_cx (cpx_sctag6_grant_cx[ 7 : 0 ] ), | |
9327 | .l2t_rst_fatal_error (l2t6_rst_fatal_error), | |
9328 | .rst_wmr_protect (rst_wmr_protect ), | |
9329 | .l2t_l2d_way_sel_c2 (l2t6_l2d6_way_sel_c2 ), | |
9330 | .l2t_l2d_rd_wr_c2 (l2t6_l2d6_rd_wr_c2 ), | |
9331 | .l2t_l2d_set_c2 (l2t6_l2d6_set_c2[ 8 : 0 ] ), | |
9332 | .l2t_l2d_col_offset_c2 (l2t6_l2d6_col_offset_c2[ 3 : 0 ]), | |
9333 | .l2t_l2d_word_en_c2 (l2t6_l2d6_word_en_c2 ), | |
9334 | .l2t_l2d_fbrd_c3 (l2t6_l2d6_fbrd_c3 ), | |
9335 | .l2t_l2d_fb_hit_c3 (l2t6_l2d6_fb_hit_c3 ), | |
9336 | .l2t_l2d_stdecc_c2 (l2t6_l2d6_stdecc_c2[ 77 : 0 ] ), | |
9337 | .l2d_l2t_decc_c6 (l2d6_l2t6_decc_c6 ), | |
9338 | // .l2t_l2b_stdecc_c3 (l2t6_l2b6_stdecc_c3[77:0] ), | |
9339 | .l2t_l2b_fbrd_en_c3 (l2t6_l2b6_fbrd_en_c3 ), | |
9340 | .l2t_l2b_fbrd_wl_c3 (l2t6_l2b6_fbrd_wl_c3[ 2 : 0 ] ), | |
9341 | .l2t_l2b_fbwr_wen_r2 (l2t6_l2b6_fbwr_wen_r2[ 15 : 0 ] ), | |
9342 | .l2t_l2b_fbwr_wl_r2 (l2t6_l2b6_fbwr_wl_r2[ 2 : 0 ] ), | |
9343 | .l2t_l2b_fbd_stdatasel_c3 (l2t6_l2b6_fbd_stdatasel_c3 ), | |
9344 | .l2t_l2b_wbwr_wen_c6 (l2t6_l2b6_wbwr_wen_c6[ 3 : 0 ] ), | |
9345 | .l2t_l2b_wbwr_wl_c6 (l2t6_l2b6_wbwr_wl_c6[ 2 : 0 ] ), | |
9346 | .l2t_l2b_wbrd_en_r0 (l2t6_l2b6_wbrd_en_r0 ), | |
9347 | .l2t_l2b_wbrd_wl_r0 (l2t6_l2b6_wbrd_wl_r0[ 2 : 0 ] ), | |
9348 | .l2t_l2b_ev_dword_r0 (l2t6_l2b6_ev_dword_r0[ 2 : 0 ] ), | |
9349 | .l2t_l2b_evict_en_r0 (l2t6_l2b6_evict_en_r0 ), | |
9350 | .l2b_l2t_ev_uerr_r5 (l2b6_l2t6_ev_uerr_r5 ), | |
9351 | .l2b_l2t_ev_cerr_r5 (l2b6_l2t6_ev_cerr_r5 ), | |
9352 | .l2t_l2b_rdma_wren_s2 (l2t6_l2b6_rdma_wren_s2[ 15 : 0 ]), | |
9353 | .l2t_l2b_rdma_wrwl_s2 (l2t6_l2b6_rdma_wrwl_s2[ 1 : 0 ] ), | |
9354 | .l2t_l2b_rdma_rdwl_r0 (l2t6_l2b6_rdma_rdwl_r0[ 1 : 0 ] ), | |
9355 | .l2t_l2b_rdma_rden_r0 (l2t6_l2b6_rdma_rden_r0 ), | |
9356 | .l2t_l2b_ctag_en_c7 (l2t6_l2b6_ctag_en_c7 ), | |
9357 | .l2t_l2b_ctag_c7 (l2t6_l2b6_ctag_c7[ 31 : 0 ] ), | |
9358 | .l2t_l2b_word_c7 (l2t6_l2b6_word_c7[ 3 : 0 ] ), | |
9359 | .l2t_l2b_req_en_c7 (l2t6_l2b6_req_en_c7 ), | |
9360 | .l2t_l2b_word_vld_c7 (l2t6_l2b6_word_vld_c7 ), | |
9361 | .l2b_l2t_rdma_uerr_c10 (l2b6_l2t6_rdma_uerr_c10 ), | |
9362 | .l2b_l2t_rdma_cerr_c10 (l2b6_l2t6_rdma_cerr_c10 ), | |
9363 | .l2b_l2t_rdma_notdata_c10 (l2b6_l2t6_rdma_notdata_c10 ), | |
9364 | .l2t_mcu_rd_req (l2t6_mcu3_rd_req ), | |
9365 | .l2t_mcu_rd_dummy_req (l2t6_mcu3_rd_dummy_req ), | |
9366 | .l2t_mcu_rd_req_id (l2t6_mcu3_rd_req_id[ 2 : 0 ] ), | |
9367 | .l2t_mcu_addr (l2t6_mcu3_addr[ 39 : 7 ] ), | |
9368 | .l2t_mcu_addr_5 (l2t6_mcu3_addr_5 ), | |
9369 | .l2t_mcu_wr_req (l2t6_mcu3_wr_req ), | |
9370 | .mcu_l2t_rd_ack (mcu3_l2t6_rd_ack ), | |
9371 | .mcu_l2t_wr_ack (mcu3_l2t6_wr_ack ), | |
9372 | .mcu_l2t_chunk_id_r0 (mcu3_l2t6_qword_id_r0[ 1 : 0 ] ), | |
9373 | .mcu_l2t_data_vld_r0 (mcu3_l2t6_data_vld_r0 ), | |
9374 | .mcu_l2t_rd_req_id_r0 (mcu3_l2t6_rd_req_id_r0[ 2 : 0 ] ), | |
9375 | .mcu_l2t_secc_err_r2 (mcu3_l2t6_secc_err_r2 ), | |
9376 | .mcu_l2t_mecc_err_r2 (mcu3_l2t6_mecc_err_r2 ), | |
9377 | .mcu_l2t_scb_mecc_err (mcu3_l2t6_scb_mecc_err ), | |
9378 | .mcu_l2t_scb_secc_err (mcu3_l2t6_scb_secc_err ), | |
9379 | .sii_l2t_req_vld (sii_l2t6_req_vld_t6lff ), | |
9380 | .sii_l2t_req (sii_l2t6_req_t6lff[ 31 : 0 ] ), | |
9381 | .sii_l2b_ecc (sii_l2b6_ecc_ccxrff[ 6 : 0 ] ), | |
9382 | .l2t_sii_iq_dequeue (l2t6_sii_iq_dequeue ), | |
9383 | .l2t_sii_wib_dequeue (l2t6_sii_wib_dequeue ), | |
9384 | .rst_por_ ( gl_l2_por_c1b ), // ( gl_l2_por_c1t ), - for int6.1 | |
9385 | .rst_wmr_ ( gl_l2_wmr_c1b ), | |
9386 | .scan_in (tcu_soc3_scan_out ), | |
9387 | .scan_out (l2t6_scan_out ), | |
9388 | .tcu_mbist_bisi_en (tcu_mbist_bisi_en ), | |
9389 | .tcu_l2t_mbist_start (tcu_l2t6_mbist_start), | |
9390 | .tcu_l2t_mbist_scan_in (tcu_l2t6_mbist_scan_in ), | |
9391 | .l2t_tcu_mbist_done (l2t6_tcu_mbist_done), | |
9392 | .l2t_tcu_mbist_fail (l2t6_tcu_mbist_fail), | |
9393 | .l2t_tcu_mbist_scan_out (l2t6_tcu_mbist_scan_out ), | |
9394 | .efu_l2t_fuse_clr (efu_l2t6_fuse_clr ), | |
9395 | .efu_l2t_fuse_xfer_en (efu_l2t6_fuse_xfer_en ), | |
9396 | .efu_l2t_fuse_data (efu_l2t0246_fuse_data ), | |
9397 | .l2t_efu_fuse_data (l2t6_efu_fuse_data ), | |
9398 | .l2t_efu_fuse_xfer_en (l2t6_efu_fuse_xfer_en ), | |
9399 | .gclk ( cmp_gclk_c1_l2t6 ), | |
9400 | .tcu_clk_stop ( gl_l2t6_clk_stop ), // staged clk_stop | |
9401 | .tcu_l2t_shscan_scan_in (tcu_l2t6_shscan_scan_in ), | |
9402 | .tcu_l2t_shscan_aclk (tcu_l2t_shscan_aclk ), | |
9403 | .tcu_l2t_shscan_bclk (tcu_l2t_shscan_bclk ), | |
9404 | .tcu_l2t_shscan_scan_en (tcu_l2t_shscan_scan_en ), | |
9405 | .tcu_l2t_shscan_pce_ov (tcu_l2t_shscan_pce_ov ), | |
9406 | .l2t_tcu_shscan_scan_out (l2t6_tcu_shscan_scan_out), | |
9407 | .tcu_l2t_shscan_clk_stop (tcu_l2t6_shscan_clk_stop), | |
9408 | .vnw_ary (L2T_VNW[ 6 ]), | |
9409 | .l2t_rep_in0 (24'b0), | |
9410 | .l2t_rep_in1 (24'b0), | |
9411 | .l2t_rep_in2 (24'b0), | |
9412 | .l2t_rep_in3 (24'b0), | |
9413 | .l2t_rep_in4 (24'b0), | |
9414 | .l2t_rep_in5 (24'b0), | |
9415 | .l2t_rep_in6 (24'b0), | |
9416 | .l2t_rep_in7 (24'b0), | |
9417 | .l2t_rep_in8 (24'b0), | |
9418 | .l2t_rep_in9 (24'b0), | |
9419 | .l2t_rep_in10 (24'b0), | |
9420 | .l2t_rep_in11 (24'b0), | |
9421 | .l2t_rep_in12 (24'b0), | |
9422 | .l2t_rep_in13 (24'b0), | |
9423 | .l2t_rep_in14 (24'b0), | |
9424 | .l2t_rep_in15 (24'b0), | |
9425 | .l2t_rep_in16 (24'b0), | |
9426 | .l2t_rep_in17 (24'b0), | |
9427 | .l2t_rep_in18 (24'b0), | |
9428 | .l2t_rep_in19 (24'b0), | |
9429 | .l2t_rep_out0 (l2t6_rep_out0_unused[ 23 : 0 ]), | |
9430 | .l2t_rep_out1 (l2t6_rep_out1_unused[ 23 : 0 ]), | |
9431 | .l2t_rep_out2 (l2t6_rep_out2_unused[ 23 : 0 ]), | |
9432 | .l2t_rep_out3 (l2t6_rep_out3_unused[ 23 : 0 ]), | |
9433 | .l2t_rep_out4 (l2t6_rep_out4_unused[ 23 : 0 ]), | |
9434 | .l2t_rep_out5 (l2t6_rep_out5_unused[ 23 : 0 ]), | |
9435 | .l2t_rep_out6 (l2t6_rep_out6_unused[ 23 : 0 ]), | |
9436 | .l2t_rep_out7 (l2t6_rep_out7_unused[ 23 : 0 ]), | |
9437 | .l2t_rep_out8 (l2t6_rep_out8_unused[ 23 : 0 ]), | |
9438 | .l2t_rep_out9 (l2t6_rep_out9_unused[ 23 : 0 ]), | |
9439 | .l2t_rep_out10 (l2t6_rep_out10_unused[ 23 : 0 ]), | |
9440 | .l2t_rep_out11 (l2t6_rep_out11_unused[ 23 : 0 ]), | |
9441 | .l2t_rep_out12 (l2t6_rep_out12_unused[ 23 : 0 ]), | |
9442 | .l2t_rep_out13 (l2t6_rep_out13_unused[ 23 : 0 ]), | |
9443 | .l2t_rep_out14 (l2t6_rep_out14_unused[ 23 : 0 ]), | |
9444 | .l2t_rep_out15 (l2t6_rep_out15_unused[ 23 : 0 ]), | |
9445 | .l2t_rep_out16 (l2t6_rep_out16_unused[ 23 : 0 ]), | |
9446 | .l2t_rep_out17 (l2t6_rep_out17_unused[ 23 : 0 ]), | |
9447 | .l2t_rep_out18 (l2t6_rep_out18_unused[ 23 : 0 ]), | |
9448 | .l2t_rep_out19 (l2t6_rep_out19_unused[ 23 : 0 ]), | |
9449 | .ncu_l2t_pm(ncu_l2t_pm), | |
9450 | .ncu_l2t_ba01(ncu_l2t_ba01), | |
9451 | .ncu_l2t_ba23(ncu_l2t_ba23), | |
9452 | .ncu_l2t_ba45(ncu_l2t_ba45), | |
9453 | .ncu_l2t_ba67(ncu_l2t_ba67), | |
9454 | .ncu_spc0_core_enable_status(ncu_spc0_core_enable_status), | |
9455 | .ncu_spc1_core_enable_status(ncu_spc1_core_enable_status), | |
9456 | .ncu_spc2_core_enable_status(ncu_spc2_core_enable_status), | |
9457 | .ncu_spc3_core_enable_status(ncu_spc3_core_enable_status), | |
9458 | .ncu_spc4_core_enable_status(ncu_spc4_core_enable_status), | |
9459 | .ncu_spc5_core_enable_status(ncu_spc5_core_enable_status), | |
9460 | .ncu_spc6_core_enable_status(ncu_spc6_core_enable_status), | |
9461 | .ncu_spc7_core_enable_status(ncu_spc7_core_enable_status), | |
9462 | .tcu_pce_ov(tcu_pce_ov), | |
9463 | .tcu_aclk(tcu_aclk), | |
9464 | .tcu_bclk(tcu_bclk), | |
9465 | .tcu_scan_en(tcu_scan_en), | |
9466 | .tcu_muxtest(tcu_muxtest), | |
9467 | .tcu_dectest(tcu_dectest), | |
9468 | .tcu_atpg_mode(tcu_atpg_mode), | |
9469 | .tcu_se_scancollar_in(tcu_se_scancollar_in), | |
9470 | .tcu_se_scancollar_out(tcu_se_scancollar_out), | |
9471 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit), | |
9472 | .tcu_array_bypass(tcu_array_bypass), | |
9473 | .cluster_arst_l(cluster_arst_l), | |
9474 | .tcu_mbist_user_mode(tcu_mbist_user_mode) | |
9475 | ); | |
9476 | //________________________________________________________________ | |
9477 | ||
9478 | /////// stagging flop | |
9479 | ||
9480 | //assign | |
9481 | ||
9482 | l2t l2t7( | |
9483 | .ccu_slow_cmp_sync_en ( gl_io_cmp_sync_en_c2b ), | |
9484 | .ccu_cmp_slow_sync_en ( gl_cmp_io_sync_en_c2b ), | |
9485 | .l2t_lstg_in ( | |
9486 | {113'b0, | |
9487 | l2t2_tcu_mbist_done, | |
9488 | l2t2_tcu_mbist_fail, | |
9489 | spc2_tcu_mbist_done, | |
9490 | spc2_tcu_mbist_fail, | |
9491 | 21'b0, | |
9492 | 26'b0, | |
9493 | spc2_softstop_request, | |
9494 | spc2_hardstop_request, | |
9495 | spc2_trigger_pulse, | |
9496 | spc2_ss_complete, | |
9497 | 24'b0 | |
9498 | } | |
9499 | ), | |
9500 | .l2t_rstg_in ( | |
9501 | {136'b0, | |
9502 | mcu3_l2t7_rd_ack, | |
9503 | mcu3_l2t7_wr_ack, | |
9504 | mcu3_l2t7_qword_id_r0[ 1 : 0 ], | |
9505 | mcu3_l2t7_data_vld_r0, | |
9506 | mcu3_l2t7_rd_req_id_r0[ 2 : 0 ], | |
9507 | mcu3_l2t7_secc_err_r2, | |
9508 | mcu3_l2t7_mecc_err_r2, | |
9509 | mcu3_l2t7_scb_mecc_err, | |
9510 | mcu3_l2t7_scb_secc_err, | |
9511 | 44'b0 | |
9512 | } | |
9513 | ), | |
9514 | .l2t_lstg_out ( | |
9515 | {unconnectedt7lff[ 191 : 79 ], | |
9516 | l2t2_tcu_mbist_done_t7lff, | |
9517 | l2t2_tcu_mbist_fail_t7lff, | |
9518 | spc2_tcu_mbist_done_t7lff, | |
9519 | spc2_tcu_mbist_fail_t7lff, | |
9520 | unconnectedt7lff[ 74 : 28 ], | |
9521 | spc2_softstop_request_t7lff, | |
9522 | spc2_hardstop_request_t7lff, | |
9523 | spc2_trigger_pulse_t7lff, | |
9524 | spc2_ss_complete_t7lff, | |
9525 | unconnectedt7lff[ 23 : 0 ] | |
9526 | } | |
9527 | ), | |
9528 | .l2t_rstg_out ( | |
9529 | {unconnectedt7rff[ 191 : 56 ], | |
9530 | mcu3_l2t7_rd_ack_t7rff, | |
9531 | mcu3_l2t7_wr_ack_t7rff, | |
9532 | mcu3_l2t7_qword_id_r0_t7rff[ 1 : 0 ], | |
9533 | mcu3_l2t7_data_vld_r0_t7rff, | |
9534 | mcu3_l2t7_rd_req_id_r0_t7rff[ 2 : 0 ], | |
9535 | mcu3_l2t7_secc_err_r2_t7rff, | |
9536 | mcu3_l2t7_mecc_err_r2_t7rff, | |
9537 | mcu3_l2t7_scb_mecc_err_t7rff, | |
9538 | mcu3_l2t7_scb_secc_err_t7rff, | |
9539 | unconnectedt7rff[ 43 : 0 ] | |
9540 | } | |
9541 | ), | |
9542 | .l2t_siu_delay (1'b0), | |
9543 | .l2t_tcu_dmo_out_prev (l2t3_dmo_dout[ 38 : 0 ] ), | |
9544 | .l2t_tcu_dmo_out (l2t7_dmo_dout[ 38 : 0 ] ), | |
9545 | .tcu_l2t_coresel (dmo_l2tsel[ 1 ] ), | |
9546 | .tcu_l2t_tag_or_data_sel (dmo_tagmuxctl ), | |
9547 | .l2t_dbg_sii_iq_dequeue (l2t7_dbg1_sii_iq_dequeue ), | |
9548 | .l2t_dbg_sii_wib_dequeue (l2t7_dbg1_sii_wib_dequeue ), | |
9549 | .l2t_dbg_xbar_vcid (l2t7_dbg1_xbar_vcid[ 5 : 0 ] ), | |
9550 | .l2t_dbg_err_event (l2t7_dbg1_err_event ), | |
9551 | .l2t_dbg_pa_match (l2t7_dbg1_pa_match ), | |
9552 | .l2t_cpx_req_cq (sctag7_cpx_req_cq[ 7 : 0 ] ),// sctag | |
9553 | .l2t_cpx_atom_cq (sctag7_cpx_atom_cq ), | |
9554 | .l2t_cpx_data_ca (sctag7_cpx_data_ca[ 145 : 0 ]), | |
9555 | .l2t_pcx_stall_pq (sctag7_pcx_stall_pq ), | |
9556 | .pcx_l2t_data_rdy_px1 (pcx_sctag7_data_rdy_px1 ), | |
9557 | .pcx_l2t_data_px2 (pcx_sctag7_data_px2[ 129 : 0 ]), | |
9558 | .pcx_l2t_atm_px1 (pcx_sctag7_atm_px1 ), | |
9559 | .cpx_l2t_grant_cx (cpx_sctag7_grant_cx[ 7 : 0 ] ), | |
9560 | .l2t_rst_fatal_error (l2t7_rst_fatal_error), | |
9561 | .rst_wmr_protect (rst_wmr_protect ), | |
9562 | .l2t_l2d_way_sel_c2 (l2t7_l2d7_way_sel_c2 ), | |
9563 | .l2t_l2d_rd_wr_c2 (l2t7_l2d7_rd_wr_c2 ), | |
9564 | .l2t_l2d_set_c2 (l2t7_l2d7_set_c2[ 8 : 0 ] ), | |
9565 | .l2t_l2d_col_offset_c2 (l2t7_l2d7_col_offset_c2[ 3 : 0 ]), | |
9566 | .l2t_l2d_word_en_c2 (l2t7_l2d7_word_en_c2 ), | |
9567 | .l2t_l2d_fbrd_c3 (l2t7_l2d7_fbrd_c3 ), | |
9568 | .l2t_l2d_fb_hit_c3 (l2t7_l2d7_fb_hit_c3 ), | |
9569 | .l2t_l2d_stdecc_c2 (l2t7_l2d7_stdecc_c2[ 77 : 0 ] ), | |
9570 | .l2d_l2t_decc_c6 (l2d7_l2t7_decc_c6 ), | |
9571 | // .l2t_l2b_stdecc_c3 (l2t7_l2b7_stdecc_c3[77:0] ), | |
9572 | .l2t_l2b_fbrd_en_c3 (l2t7_l2b7_fbrd_en_c3 ), | |
9573 | .l2t_l2b_fbrd_wl_c3 (l2t7_l2b7_fbrd_wl_c3[ 2 : 0 ] ), | |
9574 | .l2t_l2b_fbwr_wen_r2 (l2t7_l2b7_fbwr_wen_r2[ 15 : 0 ] ), | |
9575 | .l2t_l2b_fbwr_wl_r2 (l2t7_l2b7_fbwr_wl_r2[ 2 : 0 ] ), | |
9576 | .l2t_l2b_fbd_stdatasel_c3 (l2t7_l2b7_fbd_stdatasel_c3 ), | |
9577 | .l2t_l2b_wbwr_wen_c6 (l2t7_l2b7_wbwr_wen_c6[ 3 : 0 ] ), | |
9578 | .l2t_l2b_wbwr_wl_c6 (l2t7_l2b7_wbwr_wl_c6[ 2 : 0 ] ), | |
9579 | .l2t_l2b_wbrd_en_r0 (l2t7_l2b7_wbrd_en_r0 ), | |
9580 | .l2t_l2b_wbrd_wl_r0 (l2t7_l2b7_wbrd_wl_r0[ 2 : 0 ] ), | |
9581 | .l2t_l2b_ev_dword_r0 (l2t7_l2b7_ev_dword_r0[ 2 : 0 ] ), | |
9582 | .l2t_l2b_evict_en_r0 (l2t7_l2b7_evict_en_r0 ), | |
9583 | .l2b_l2t_ev_uerr_r5 (l2b7_l2t7_ev_uerr_r5 ), | |
9584 | .l2b_l2t_ev_cerr_r5 (l2b7_l2t7_ev_cerr_r5 ), | |
9585 | .l2t_l2b_rdma_wren_s2 (l2t7_l2b7_rdma_wren_s2[ 15 : 0 ]), | |
9586 | .l2t_l2b_rdma_wrwl_s2 (l2t7_l2b7_rdma_wrwl_s2[ 1 : 0 ] ), | |
9587 | .l2t_l2b_rdma_rdwl_r0 (l2t7_l2b7_rdma_rdwl_r0[ 1 : 0 ] ), | |
9588 | .l2t_l2b_rdma_rden_r0 (l2t7_l2b7_rdma_rden_r0 ), | |
9589 | .l2t_l2b_ctag_en_c7 (l2t7_l2b7_ctag_en_c7 ), | |
9590 | .l2t_l2b_ctag_c7 (l2t7_l2b7_ctag_c7[ 31 : 0 ] ), | |
9591 | .l2t_l2b_word_c7 (l2t7_l2b7_word_c7[ 3 : 0 ] ), | |
9592 | .l2t_l2b_req_en_c7 (l2t7_l2b7_req_en_c7 ), | |
9593 | .l2t_l2b_word_vld_c7 (l2t7_l2b7_word_vld_c7 ), | |
9594 | .l2b_l2t_rdma_uerr_c10 (l2b7_l2t7_rdma_uerr_c10 ), | |
9595 | .l2b_l2t_rdma_cerr_c10 (l2b7_l2t7_rdma_cerr_c10 ), | |
9596 | .l2b_l2t_rdma_notdata_c10 (l2b7_l2t7_rdma_notdata_c10 ), | |
9597 | .l2t_mcu_rd_req (l2t7_mcu3_rd_req ), | |
9598 | .l2t_mcu_rd_dummy_req (l2t7_mcu3_rd_dummy_req ), | |
9599 | .l2t_mcu_rd_req_id (l2t7_mcu3_rd_req_id[ 2 : 0 ] ), | |
9600 | .l2t_mcu_addr (l2t7_mcu3_addr[ 39 : 7 ] ), | |
9601 | .l2t_mcu_addr_5 (l2t7_mcu3_addr_5 ), | |
9602 | .l2t_mcu_wr_req (l2t7_mcu3_wr_req ), | |
9603 | .mcu_l2t_rd_ack (mcu3_l2t7_rd_ack_t7rff ), | |
9604 | .mcu_l2t_wr_ack (mcu3_l2t7_wr_ack_t7rff ), | |
9605 | .mcu_l2t_chunk_id_r0 (mcu3_l2t7_qword_id_r0_t7rff[ 1 : 0 ] ), | |
9606 | .mcu_l2t_data_vld_r0 (mcu3_l2t7_data_vld_r0_t7rff ), | |
9607 | .mcu_l2t_rd_req_id_r0 (mcu3_l2t7_rd_req_id_r0_t7rff[ 2 : 0 ] ), | |
9608 | .mcu_l2t_secc_err_r2 (mcu3_l2t7_secc_err_r2_t7rff ), | |
9609 | .mcu_l2t_mecc_err_r2 (mcu3_l2t7_mecc_err_r2_t7rff ), | |
9610 | .mcu_l2t_scb_mecc_err (mcu3_l2t7_scb_mecc_err_t7rff ), | |
9611 | .mcu_l2t_scb_secc_err (mcu3_l2t7_scb_secc_err_t7rff ), | |
9612 | .sii_l2t_req_vld (sii_l2t7_req_vld_t6lff ), | |
9613 | .sii_l2t_req (sii_l2t7_req_t6lff[ 31 : 0 ] ), | |
9614 | .sii_l2b_ecc (sii_l2b7_ecc_ccxrff[ 6 : 0 ] ), | |
9615 | .l2t_sii_iq_dequeue (l2t7_sii_iq_dequeue ), | |
9616 | .l2t_sii_wib_dequeue (l2t7_sii_wib_dequeue ), | |
9617 | .rst_por_ ( gl_l2_por_c2b ), | |
9618 | .rst_wmr_ ( gl_l2_wmr_c2b ), | |
9619 | .scan_in (l2t6_scan_out ), | |
9620 | .scan_out (l2t7_scan_out ), | |
9621 | .tcu_mbist_bisi_en (tcu_mbist_bisi_en ), | |
9622 | .tcu_l2t_mbist_start (tcu_l2t7_mbist_start), | |
9623 | .tcu_l2t_mbist_scan_in (tcu_l2t7_mbist_scan_in ), | |
9624 | .l2t_tcu_mbist_done (l2t7_tcu_mbist_done), | |
9625 | .l2t_tcu_mbist_fail (l2t7_tcu_mbist_fail), | |
9626 | .l2t_tcu_mbist_scan_out (l2t7_tcu_mbist_scan_out ), | |
9627 | .efu_l2t_fuse_clr (efu_l2t7_fuse_clr ), | |
9628 | .efu_l2t_fuse_xfer_en (efu_l2t7_fuse_xfer_en ), | |
9629 | .efu_l2t_fuse_data (efu_l2t1357_fuse_data ), | |
9630 | .l2t_efu_fuse_data (l2t7_efu_fuse_data ), | |
9631 | .l2t_efu_fuse_xfer_en (l2t7_efu_fuse_xfer_en ), | |
9632 | .gclk ( cmp_gclk_c2_l2t7 ), | |
9633 | .tcu_clk_stop ( gl_l2t7_clk_stop ), // staged clk_stop | |
9634 | .tcu_l2t_shscan_scan_in (tcu_l2t7_shscan_scan_in ), | |
9635 | .tcu_l2t_shscan_aclk (tcu_l2t_shscan_aclk ), | |
9636 | .tcu_l2t_shscan_bclk (tcu_l2t_shscan_bclk ), | |
9637 | .tcu_l2t_shscan_scan_en (tcu_l2t_shscan_scan_en ), | |
9638 | .tcu_l2t_shscan_pce_ov (tcu_l2t_shscan_pce_ov ), | |
9639 | .l2t_tcu_shscan_scan_out (l2t7_tcu_shscan_scan_out), | |
9640 | .tcu_l2t_shscan_clk_stop (tcu_l2t7_shscan_clk_stop), | |
9641 | .vnw_ary (L2T_VNW[ 7 ]), | |
9642 | .l2t_rep_in0 (24'b0), | |
9643 | .l2t_rep_in1 (24'b0), | |
9644 | .l2t_rep_in2 (24'b0), | |
9645 | .l2t_rep_in3 (24'b0), | |
9646 | .l2t_rep_in4 (24'b0), | |
9647 | .l2t_rep_in5 (24'b0), | |
9648 | .l2t_rep_in6 (24'b0), | |
9649 | .l2t_rep_in7 (24'b0), | |
9650 | .l2t_rep_in8 (24'b0), | |
9651 | .l2t_rep_in9 (24'b0), | |
9652 | .l2t_rep_in10 (24'b0), | |
9653 | .l2t_rep_in11 (24'b0), | |
9654 | .l2t_rep_in12 (24'b0), | |
9655 | .l2t_rep_in13 (24'b0), | |
9656 | .l2t_rep_in14 (24'b0), | |
9657 | .l2t_rep_in15 (24'b0), | |
9658 | .l2t_rep_in16 (24'b0), | |
9659 | .l2t_rep_in17 (24'b0), | |
9660 | .l2t_rep_in18 (24'b0), | |
9661 | .l2t_rep_in19 (24'b0), | |
9662 | .l2t_rep_out0 (l2t7_rep_out0_unused[ 23 : 0 ]), | |
9663 | .l2t_rep_out1 (l2t7_rep_out1_unused[ 23 : 0 ]), | |
9664 | .l2t_rep_out2 (l2t7_rep_out2_unused[ 23 : 0 ]), | |
9665 | .l2t_rep_out3 (l2t7_rep_out3_unused[ 23 : 0 ]), | |
9666 | .l2t_rep_out4 (l2t7_rep_out4_unused[ 23 : 0 ]), | |
9667 | .l2t_rep_out5 (l2t7_rep_out5_unused[ 23 : 0 ]), | |
9668 | .l2t_rep_out6 (l2t7_rep_out6_unused[ 23 : 0 ]), | |
9669 | .l2t_rep_out7 (l2t7_rep_out7_unused[ 23 : 0 ]), | |
9670 | .l2t_rep_out8 (l2t7_rep_out8_unused[ 23 : 0 ]), | |
9671 | .l2t_rep_out9 (l2t7_rep_out9_unused[ 23 : 0 ]), | |
9672 | .l2t_rep_out10 (l2t7_rep_out10_unused[ 23 : 0 ]), | |
9673 | .l2t_rep_out11 (l2t7_rep_out11_unused[ 23 : 0 ]), | |
9674 | .l2t_rep_out12 (l2t7_rep_out12_unused[ 23 : 0 ]), | |
9675 | .l2t_rep_out13 (l2t7_rep_out13_unused[ 23 : 0 ]), | |
9676 | .l2t_rep_out14 (l2t7_rep_out14_unused[ 23 : 0 ]), | |
9677 | .l2t_rep_out15 (l2t7_rep_out15_unused[ 23 : 0 ]), | |
9678 | .l2t_rep_out16 (l2t7_rep_out16_unused[ 23 : 0 ]), | |
9679 | .l2t_rep_out17 (l2t7_rep_out17_unused[ 23 : 0 ]), | |
9680 | .l2t_rep_out18 (l2t7_rep_out18_unused[ 23 : 0 ]), | |
9681 | .l2t_rep_out19 (l2t7_rep_out19_unused[ 23 : 0 ]), | |
9682 | .ncu_l2t_pm(ncu_l2t_pm), | |
9683 | .ncu_l2t_ba01(ncu_l2t_ba01), | |
9684 | .ncu_l2t_ba23(ncu_l2t_ba23), | |
9685 | .ncu_l2t_ba45(ncu_l2t_ba45), | |
9686 | .ncu_l2t_ba67(ncu_l2t_ba67), | |
9687 | .ncu_spc0_core_enable_status(ncu_spc0_core_enable_status), | |
9688 | .ncu_spc1_core_enable_status(ncu_spc1_core_enable_status), | |
9689 | .ncu_spc2_core_enable_status(ncu_spc2_core_enable_status), | |
9690 | .ncu_spc3_core_enable_status(ncu_spc3_core_enable_status), | |
9691 | .ncu_spc4_core_enable_status(ncu_spc4_core_enable_status), | |
9692 | .ncu_spc5_core_enable_status(ncu_spc5_core_enable_status), | |
9693 | .ncu_spc6_core_enable_status(ncu_spc6_core_enable_status), | |
9694 | .ncu_spc7_core_enable_status(ncu_spc7_core_enable_status), | |
9695 | .tcu_pce_ov(tcu_pce_ov), | |
9696 | .tcu_aclk(tcu_aclk), | |
9697 | .tcu_bclk(tcu_bclk), | |
9698 | .tcu_scan_en(tcu_scan_en), | |
9699 | .tcu_muxtest(tcu_muxtest), | |
9700 | .tcu_dectest(tcu_dectest), | |
9701 | .tcu_atpg_mode(tcu_atpg_mode), | |
9702 | .tcu_se_scancollar_in(tcu_se_scancollar_in), | |
9703 | .tcu_se_scancollar_out(tcu_se_scancollar_out), | |
9704 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit), | |
9705 | .tcu_array_bypass(tcu_array_bypass), | |
9706 | .cluster_arst_l(cluster_arst_l), | |
9707 | .tcu_mbist_user_mode(tcu_mbist_user_mode) | |
9708 | ); | |
9709 | //________________________________________________________________ | |
9710 | ||
9711 | l2b l2b0( | |
9712 | .ccu_slow_cmp_sync_en ( gl_io_cmp_sync_en_c3t0 ), // ( gl_io_cmp_sync_en_c3t ), - for int6.1 | |
9713 | .ccu_cmp_slow_sync_en ( gl_cmp_io_sync_en_c3t0 ), // ( gl_cmp_io_sync_en_c3t ), - for int6.1 | |
9714 | .select_delay_mcu ( 1'b0 ), | |
9715 | ||
9716 | .gclk ( cmp_gclk_c3_l2b0 ), // cmp_gclk_c0_r[1]), | |
9717 | .tcu_clk_stop ( gl_l2b0_clk_stop ), // staged clk_stop | |
9718 | .rst_por_ (gl_l2_por_c3t0 ), // ( gl_l2_por_c3t ), - for int6.1 | |
9719 | .rst_wmr_ (gl_l2_wmr_c3t0 ), // ( gl_l2_wmr_c3t ), - for int6.1 | |
9720 | .l2t_l2b_fbrd_en_c3 (l2t0_l2b0_fbrd_en_c3 ),// scbuf | |
9721 | .l2t_l2b_fbrd_wl_c3 (l2t0_l2b0_fbrd_wl_c3 ), | |
9722 | .l2t_l2b_fbwr_wen_r2 (l2t0_l2b0_fbwr_wen_r2 ), | |
9723 | .l2t_l2b_fbwr_wl_r2 (l2t0_l2b0_fbwr_wl_r2 ), | |
9724 | .l2t_l2b_fbd_stdatasel_c3 (l2t0_l2b0_fbd_stdatasel_c3 ), | |
9725 | .l2t_l2b_stdecc_c2 (l2t0_l2d0_stdecc_c2[ 77 : 0 ] ), | |
9726 | .l2t_l2b_evict_en_r0 (l2t0_l2b0_evict_en_r0 ), | |
9727 | .l2t_l2b_wbwr_wen_c6 (l2t0_l2b0_wbwr_wen_c6 ), | |
9728 | .l2t_l2b_wbwr_wl_c6 (l2t0_l2b0_wbwr_wl_c6 ), | |
9729 | .l2t_l2b_wbrd_en_r0 (l2t0_l2b0_wbrd_en_r0 ), | |
9730 | .l2t_l2b_wbrd_wl_r0 (l2t0_l2b0_wbrd_wl_r0 ), | |
9731 | .l2t_l2b_ev_dword_r0 (l2t0_l2b0_ev_dword_r0 ), | |
9732 | .l2t_l2b_rdma_wren_s2 (l2t0_l2b0_rdma_wren_s2 ), | |
9733 | .l2t_l2b_rdma_wrwl_s2 (l2t0_l2b0_rdma_wrwl_s2 ), | |
9734 | .l2t_l2b_rdma_rden_r0 (l2t0_l2b0_rdma_rden_r0 ), | |
9735 | .l2t_l2b_rdma_rdwl_r0 (l2t0_l2b0_rdma_rdwl_r0 ), | |
9736 | .l2t_l2b_ctag_en_c7 (l2t0_l2b0_ctag_en_c7 ), | |
9737 | .l2t_l2b_ctag_c7 (l2t0_l2b0_ctag_c7[ 31 : 0 ] ), | |
9738 | .l2t_l2b_req_en_c7 (l2t0_l2b0_req_en_c7 ), | |
9739 | .l2t_l2b_word_c7 (l2t0_l2b0_word_c7 ), | |
9740 | .l2t_l2b_word_vld_c7 (l2t0_l2b0_word_vld_c7 ), | |
9741 | .sii_l2t_req (sii_l2t0_req ), | |
9742 | .sii_l2b_ecc (sii_l2b0_ecc[ 6 : 0 ] ), | |
9743 | .l2b_l2d_rvalue (l2b0_l2d0_rvalue[ 9 : 0 ]), | |
9744 | .l2b_l2d_rid (l2b0_l2d0_rid[ 6 : 0 ]), | |
9745 | .l2b_l2d_wr_en (l2b0_l2d0_wr_en), | |
9746 | .l2b_l2d_fuse_clr (l2b0_l2d0_fuse_clr), | |
9747 | .l2d_l2b_fuse_read_data (l2d0_l2b0_fuse_data[ 9 : 0 ]), | |
9748 | .efu_l2b_fuse_data (efu_l2b0246_fuse_data), | |
9749 | .efu_l2b_fuse_xfer_en (efu_l2b0_fuse_xfer_en), | |
9750 | .efu_l2b_fuse_clr (efu_l2b0_fuse_clr), | |
9751 | .l2b_efu_fuse_xfer_en (l2b0_efu_fuse_xfer_en), | |
9752 | .l2b_efu_fuse_data (l2b0_efu_fuse_data), | |
9753 | .l2b_dbg_sio_ctag_vld (l2b0_dbg0_sio_ctag_vld ), | |
9754 | .l2b_dbg_sio_ack_type (l2b0_dbg0_sio_ack_type ), | |
9755 | .l2b_dbg_sio_ack_dest (l2b0_dbg0_sio_ack_dest ), | |
9756 | .l2b_sio_ctag_vld (l2b0_sio_ctag_vld ), | |
9757 | .l2b_sio_data (l2b0_sio_data[ 31 : 0 ] ), | |
9758 | .l2b_sio_parity (l2b0_sio_parity[ 1 : 0 ] ), | |
9759 | .l2b_sio_ue_err (l2b0_sio_ue_err ), | |
9760 | .l2b_l2t_rdma_uerr_c10 (l2b0_l2t0_rdma_uerr_c10 ), | |
9761 | .l2b_l2t_rdma_cerr_c10 (l2b0_l2t0_rdma_cerr_c10 ), | |
9762 | .l2b_l2t_rdma_notdata_c10 (l2b0_l2t0_rdma_notdata_c10 ), | |
9763 | .l2b_l2t_ev_uerr_r5 (l2b0_l2t0_ev_uerr_r5 ), | |
9764 | .l2b_l2t_ev_cerr_r5 (l2b0_l2t0_ev_cerr_r5 ), | |
9765 | .l2d_l2b_decc_out_c7 (l2d0_l2b0_decc_out_c7 ), | |
9766 | .l2b_l2d_fbdecc_c4 (l2b0_l2d0_fbdecc_c4 ), | |
9767 | .mcu_l2b_data_r2 (mcu0_l2b01_data_r2[ 127 : 0 ] ), | |
9768 | .mcu_l2b_ecc_r2 (mcu0_l2b01_ecc_r2[ 27 : 0 ] ), | |
9769 | .tcu_mbist_bisi_en (tcu_mbist_bisi_en ), | |
9770 | .tcu_l2b_mbist_start (tcu_l2b0_mbist_start_ccxlff ), | |
9771 | .l2b_tcu_mbist_done (l2b0_tcu_mbist_done ), | |
9772 | .l2b_tcu_mbist_fail (l2b0_tcu_mbist_fail ), | |
9773 | .tcu_l2b_mbist_scan_in (tcu_l2b0_mbist_scan_in ), | |
9774 | .l2b_tcu_mbist_scan_out (l2b0_tcu_mbist_scan_out ), | |
9775 | .l2b_evict_l2b_mcu_data_mecc_r5 | |
9776 | (l2b0_mcu0_data_mecc_r5 ), | |
9777 | .evict_l2b_mcu_wr_data_r5 (l2b0_mcu0_wr_data_r5[ 63 : 0 ] ), | |
9778 | .evict_l2b_mcu_data_vld_r5(l2b0_mcu0_data_vld_r5 ), | |
9779 | .scan_in (tcu_soch_scan_out ), | |
9780 | .scan_out (l2b0_scan_out ), | |
9781 | .rst_wmr_protect(rst_wmr_protect), | |
9782 | .tcu_pce_ov(tcu_pce_ov), | |
9783 | .tcu_aclk(tcu_aclk), | |
9784 | .tcu_bclk(tcu_bclk), | |
9785 | .tcu_scan_en(tcu_scan_en), | |
9786 | .tcu_muxtest(tcu_muxtest), | |
9787 | .tcu_dectest(tcu_dectest), | |
9788 | .tcu_se_scancollar_in(tcu_se_scancollar_in), | |
9789 | .tcu_se_scancollar_out(tcu_se_scancollar_out), | |
9790 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit), | |
9791 | .tcu_atpg_mode(tcu_atpg_mode), | |
9792 | .tcu_array_bypass(tcu_array_bypass), | |
9793 | .cluster_arst_l(cluster_arst_l), | |
9794 | .tcu_mbist_user_mode(tcu_mbist_user_mode) | |
9795 | //.so ( ) | |
9796 | ); | |
9797 | //________________________________________________________________ | |
9798 | ||
9799 | l2b l2b1( | |
9800 | .ccu_slow_cmp_sync_en ( gl_io_cmp_sync_en_c3t ), | |
9801 | .ccu_cmp_slow_sync_en ( gl_cmp_io_sync_en_c3t ), | |
9802 | .select_delay_mcu ( 1'b1 ), | |
9803 | ||
9804 | ||
9805 | .gclk ( cmp_gclk_c3_l2b1 ), // cmp_gclk_c0_r[2] ), | |
9806 | .tcu_clk_stop ( gl_l2b1_clk_stop ), // staged clk_stop | |
9807 | .rst_por_ ( gl_l2_por_c3t ), | |
9808 | .rst_wmr_ ( gl_l2_wmr_c3t ), | |
9809 | .l2t_l2b_fbrd_en_c3 (l2t1_l2b1_fbrd_en_c3 ),// scbuf | |
9810 | .l2t_l2b_fbrd_wl_c3 (l2t1_l2b1_fbrd_wl_c3 ), | |
9811 | .l2t_l2b_fbwr_wen_r2 (l2t1_l2b1_fbwr_wen_r2 ), | |
9812 | .l2t_l2b_fbwr_wl_r2 (l2t1_l2b1_fbwr_wl_r2 ), | |
9813 | .l2t_l2b_fbd_stdatasel_c3 (l2t1_l2b1_fbd_stdatasel_c3 ), | |
9814 | .l2t_l2b_stdecc_c2 (l2t1_l2d1_stdecc_c2[ 77 : 0 ] ), | |
9815 | .l2t_l2b_evict_en_r0 (l2t1_l2b1_evict_en_r0 ), | |
9816 | .l2t_l2b_wbwr_wen_c6 (l2t1_l2b1_wbwr_wen_c6 ), | |
9817 | .l2t_l2b_wbwr_wl_c6 (l2t1_l2b1_wbwr_wl_c6 ), | |
9818 | .l2t_l2b_wbrd_en_r0 (l2t1_l2b1_wbrd_en_r0 ), | |
9819 | .l2t_l2b_wbrd_wl_r0 (l2t1_l2b1_wbrd_wl_r0 ), | |
9820 | .l2t_l2b_ev_dword_r0 (l2t1_l2b1_ev_dword_r0 ), | |
9821 | .l2t_l2b_rdma_wren_s2 (l2t1_l2b1_rdma_wren_s2 ), | |
9822 | .l2t_l2b_rdma_wrwl_s2 (l2t1_l2b1_rdma_wrwl_s2 ), | |
9823 | .l2t_l2b_rdma_rden_r0 (l2t1_l2b1_rdma_rden_r0 ), | |
9824 | .l2t_l2b_rdma_rdwl_r0 (l2t1_l2b1_rdma_rdwl_r0 ), | |
9825 | .l2t_l2b_ctag_en_c7 (l2t1_l2b1_ctag_en_c7 ), | |
9826 | .l2t_l2b_ctag_c7 (l2t1_l2b1_ctag_c7[ 31 : 0 ] ), | |
9827 | .l2t_l2b_req_en_c7 (l2t1_l2b1_req_en_c7 ), | |
9828 | .l2t_l2b_word_c7 (l2t1_l2b1_word_c7 ), | |
9829 | .l2t_l2b_word_vld_c7 (l2t1_l2b1_word_vld_c7 ), | |
9830 | .sii_l2t_req (sii_l2t1_req ), | |
9831 | .sii_l2b_ecc (sii_l2b1_ecc[ 6 : 0 ] ), | |
9832 | .l2b_l2d_rvalue (l2b1_l2d1_rvalue[ 9 : 0 ]), | |
9833 | .l2b_l2d_rid (l2b1_l2d1_rid[ 6 : 0 ]), | |
9834 | .l2b_l2d_wr_en (l2b1_l2d1_wr_en), | |
9835 | .l2b_l2d_fuse_clr (l2b1_l2d1_fuse_clr), | |
9836 | .l2d_l2b_fuse_read_data (l2d1_l2b1_fuse_data[ 9 : 0 ]), | |
9837 | .efu_l2b_fuse_data (efu_l2b1357_fuse_data), | |
9838 | .efu_l2b_fuse_xfer_en (efu_l2b1_fuse_xfer_en), | |
9839 | .efu_l2b_fuse_clr (efu_l2b1_fuse_clr), | |
9840 | .l2b_efu_fuse_xfer_en (l2b1_efu_fuse_xfer_en), | |
9841 | .l2b_efu_fuse_data (l2b1_efu_fuse_data), | |
9842 | .l2b_dbg_sio_ctag_vld (l2b1_dbg0_sio_ctag_vld ), | |
9843 | .l2b_dbg_sio_ack_type (l2b1_dbg0_sio_ack_type ), | |
9844 | .l2b_dbg_sio_ack_dest (l2b1_dbg0_sio_ack_dest ), | |
9845 | .l2b_sio_ctag_vld (l2b1_sio_ctag_vld ), | |
9846 | .l2b_sio_data (l2b1_sio_data[ 31 : 0 ] ), | |
9847 | .l2b_sio_parity (l2b1_sio_parity[ 1 : 0 ] ), | |
9848 | .l2b_sio_ue_err (l2b1_sio_ue_err ), | |
9849 | .l2b_l2t_rdma_uerr_c10 (l2b1_l2t1_rdma_uerr_c10 ), | |
9850 | .l2b_l2t_rdma_cerr_c10 (l2b1_l2t1_rdma_cerr_c10 ), | |
9851 | .l2b_l2t_rdma_notdata_c10 (l2b1_l2t1_rdma_notdata_c10 ), | |
9852 | .l2b_l2t_ev_uerr_r5 (l2b1_l2t1_ev_uerr_r5 ), | |
9853 | .l2b_l2t_ev_cerr_r5 (l2b1_l2t1_ev_cerr_r5 ), | |
9854 | .l2d_l2b_decc_out_c7 (l2d1_l2b1_decc_out_c7 ), | |
9855 | .l2b_l2d_fbdecc_c4 (l2b1_l2d1_fbdecc_c4 ), | |
9856 | .mcu_l2b_data_r2 (mcu0_l2b01_data_r2[ 127 : 0 ] ), | |
9857 | .mcu_l2b_ecc_r2 (mcu0_l2b01_ecc_r2[ 27 : 0 ] ), | |
9858 | .tcu_mbist_bisi_en (tcu_mbist_bisi_en ), | |
9859 | .tcu_l2b_mbist_start (tcu_l2b1_mbist_start_ccxlff ), | |
9860 | .l2b_tcu_mbist_done (l2b1_tcu_mbist_done ), | |
9861 | .l2b_tcu_mbist_fail (l2b1_tcu_mbist_fail ), | |
9862 | .tcu_l2b_mbist_scan_in (tcu_l2b1_mbist_scan_in ), | |
9863 | .l2b_tcu_mbist_scan_out (l2b1_tcu_mbist_scan_out ), | |
9864 | .l2b_evict_l2b_mcu_data_mecc_r5 | |
9865 | (l2b1_mcu0_data_mecc_r5 ), | |
9866 | .evict_l2b_mcu_wr_data_r5 (l2b1_mcu0_wr_data_r5[ 63 : 0 ] ), | |
9867 | .evict_l2b_mcu_data_vld_r5(l2b1_mcu0_data_vld_r5 ), | |
9868 | .scan_in (l2b0_scan_out ), | |
9869 | .scan_out (l2b1_scan_out ), | |
9870 | .rst_wmr_protect(rst_wmr_protect), | |
9871 | .tcu_pce_ov(tcu_pce_ov), | |
9872 | .tcu_aclk(tcu_aclk), | |
9873 | .tcu_bclk(tcu_bclk), | |
9874 | .tcu_scan_en(tcu_scan_en), | |
9875 | .tcu_muxtest(tcu_muxtest), | |
9876 | .tcu_dectest(tcu_dectest), | |
9877 | .tcu_se_scancollar_in(tcu_se_scancollar_in), | |
9878 | .tcu_se_scancollar_out(tcu_se_scancollar_out), | |
9879 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit), | |
9880 | .tcu_atpg_mode(tcu_atpg_mode), | |
9881 | .tcu_array_bypass(tcu_array_bypass), | |
9882 | .cluster_arst_l(cluster_arst_l), | |
9883 | .tcu_mbist_user_mode(tcu_mbist_user_mode) | |
9884 | //.so ( ) | |
9885 | ); | |
9886 | //________________________________________________________________ | |
9887 | ||
9888 | l2b l2b2( | |
9889 | .ccu_slow_cmp_sync_en ( gl_io_cmp_sync_en_c3b ), // gl_io_cmp_sync_en_c3t0 - for int6.1 | |
9890 | .ccu_cmp_slow_sync_en ( gl_cmp_io_sync_en_c3b ), // gl_cmp_io_sync_en_c3t0 - for int6.1 | |
9891 | .select_delay_mcu ( 1'b0 ), | |
9892 | ||
9893 | ||
9894 | .gclk ( cmp_gclk_c3_l2b2 ), // cmp_gclk_c0_r[4] ), | |
9895 | .tcu_clk_stop ( gl_l2b2_clk_stop ), // staged clk_stop | |
9896 | .rst_por_ ( gl_l2_por_c3b0 ), // ( gl_l2_por_c3t0 ), - for int6.1 | |
9897 | .rst_wmr_ ( gl_l2_wmr_c3b ), // ( gl_l2_wmr_c3t0 ), - for int6.1 | |
9898 | .l2t_l2b_fbrd_en_c3 (l2t2_l2b2_fbrd_en_c3 ),// scbuf | |
9899 | .l2t_l2b_fbrd_wl_c3 (l2t2_l2b2_fbrd_wl_c3 ), | |
9900 | .l2t_l2b_fbwr_wen_r2 (l2t2_l2b2_fbwr_wen_r2 ), | |
9901 | .l2t_l2b_fbwr_wl_r2 (l2t2_l2b2_fbwr_wl_r2 ), | |
9902 | .l2t_l2b_fbd_stdatasel_c3 (l2t2_l2b2_fbd_stdatasel_c3 ), | |
9903 | .l2t_l2b_stdecc_c2 (l2t2_l2d2_stdecc_c2[ 77 : 0 ] ), | |
9904 | .l2t_l2b_evict_en_r0 (l2t2_l2b2_evict_en_r0 ), | |
9905 | .l2t_l2b_wbwr_wen_c6 (l2t2_l2b2_wbwr_wen_c6 ), | |
9906 | .l2t_l2b_wbwr_wl_c6 (l2t2_l2b2_wbwr_wl_c6 ), | |
9907 | .l2t_l2b_wbrd_en_r0 (l2t2_l2b2_wbrd_en_r0 ), | |
9908 | .l2t_l2b_wbrd_wl_r0 (l2t2_l2b2_wbrd_wl_r0 ), | |
9909 | .l2t_l2b_ev_dword_r0 (l2t2_l2b2_ev_dword_r0 ), | |
9910 | .l2t_l2b_rdma_wren_s2 (l2t2_l2b2_rdma_wren_s2 ), | |
9911 | .l2t_l2b_rdma_wrwl_s2 (l2t2_l2b2_rdma_wrwl_s2 ), | |
9912 | .l2t_l2b_rdma_rden_r0 (l2t2_l2b2_rdma_rden_r0 ), | |
9913 | .l2t_l2b_rdma_rdwl_r0 (l2t2_l2b2_rdma_rdwl_r0 ), | |
9914 | .l2t_l2b_ctag_en_c7 (l2t2_l2b2_ctag_en_c7 ), | |
9915 | .l2t_l2b_ctag_c7 (l2t2_l2b2_ctag_c7[ 31 : 0 ] ), | |
9916 | .l2t_l2b_req_en_c7 (l2t2_l2b2_req_en_c7 ), | |
9917 | .l2t_l2b_word_c7 (l2t2_l2b2_word_c7 ), | |
9918 | .l2t_l2b_word_vld_c7 (l2t2_l2b2_word_vld_c7 ), | |
9919 | .sii_l2t_req (sii_l2t2_req ), | |
9920 | .sii_l2b_ecc (sii_l2b2_ecc[ 6 : 0 ] ), | |
9921 | .l2b_l2d_rvalue (l2b2_l2d2_rvalue[ 9 : 0 ]), | |
9922 | .l2b_l2d_rid (l2b2_l2d2_rid[ 6 : 0 ]), | |
9923 | .l2b_l2d_wr_en (l2b2_l2d2_wr_en), | |
9924 | .l2b_l2d_fuse_clr (l2b2_l2d2_fuse_clr), | |
9925 | .l2d_l2b_fuse_read_data (l2d2_l2b2_fuse_data[ 9 : 0 ]), | |
9926 | .efu_l2b_fuse_data (efu_l2b0246_fuse_data), | |
9927 | .efu_l2b_fuse_xfer_en (efu_l2b2_fuse_xfer_en), | |
9928 | .efu_l2b_fuse_clr (efu_l2b2_fuse_clr), | |
9929 | .l2b_efu_fuse_xfer_en (l2b2_efu_fuse_xfer_en), | |
9930 | .l2b_efu_fuse_data (l2b2_efu_fuse_data), | |
9931 | .l2b_dbg_sio_ctag_vld (l2b2_dbg0_sio_ctag_vld ), | |
9932 | .l2b_dbg_sio_ack_type (l2b2_dbg0_sio_ack_type ), | |
9933 | .l2b_dbg_sio_ack_dest (l2b2_dbg0_sio_ack_dest ), | |
9934 | .l2b_sio_ctag_vld (l2b2_sio_ctag_vld ), | |
9935 | .l2b_sio_data (l2b2_sio_data[ 31 : 0 ] ), | |
9936 | .l2b_sio_parity (l2b2_sio_parity[ 1 : 0 ] ), | |
9937 | .l2b_sio_ue_err (l2b2_sio_ue_err ), | |
9938 | .l2b_l2t_rdma_uerr_c10 (l2b2_l2t2_rdma_uerr_c10 ), | |
9939 | .l2b_l2t_rdma_cerr_c10 (l2b2_l2t2_rdma_cerr_c10 ), | |
9940 | .l2b_l2t_rdma_notdata_c10 (l2b2_l2t2_rdma_notdata_c10 ), | |
9941 | .l2b_l2t_ev_uerr_r5 (l2b2_l2t2_ev_uerr_r5 ), | |
9942 | .l2b_l2t_ev_cerr_r5 (l2b2_l2t2_ev_cerr_r5 ), | |
9943 | .l2d_l2b_decc_out_c7 (l2d2_l2b2_decc_out_c7 ), | |
9944 | .l2b_l2d_fbdecc_c4 (l2b2_l2d2_fbdecc_c4 ), | |
9945 | .mcu_l2b_data_r2 (mcu1_l2b23_data_r2[ 127 : 0 ] ), | |
9946 | .mcu_l2b_ecc_r2 (mcu1_l2b23_ecc_r2[ 27 : 0 ] ), | |
9947 | .tcu_mbist_bisi_en (tcu_mbist_bisi_en ), | |
9948 | .tcu_l2b_mbist_start (tcu_l2b2_mbist_start_ccxlff ), | |
9949 | .l2b_tcu_mbist_done (l2b2_tcu_mbist_done ), | |
9950 | .l2b_tcu_mbist_fail (l2b2_tcu_mbist_fail ), | |
9951 | .tcu_l2b_mbist_scan_in (tcu_l2b2_mbist_scan_in ), | |
9952 | .l2b_tcu_mbist_scan_out (l2b2_tcu_mbist_scan_out ), | |
9953 | .l2b_evict_l2b_mcu_data_mecc_r5 | |
9954 | (l2b2_mcu1_data_mecc_r5 ), | |
9955 | .evict_l2b_mcu_wr_data_r5 (l2b2_mcu1_wr_data_r5[ 63 : 0 ] ), | |
9956 | .evict_l2b_mcu_data_vld_r5(l2b2_mcu1_data_vld_r5 ), | |
9957 | .scan_in (l2b1_scan_out ), | |
9958 | .scan_out (l2b2_scan_out ), | |
9959 | .rst_wmr_protect(rst_wmr_protect), | |
9960 | .tcu_pce_ov(tcu_pce_ov), | |
9961 | .tcu_aclk(tcu_aclk), | |
9962 | .tcu_bclk(tcu_bclk), | |
9963 | .tcu_scan_en(tcu_scan_en), | |
9964 | .tcu_muxtest(tcu_muxtest), | |
9965 | .tcu_dectest(tcu_dectest), | |
9966 | .tcu_se_scancollar_in(tcu_se_scancollar_in), | |
9967 | .tcu_se_scancollar_out(tcu_se_scancollar_out), | |
9968 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit), | |
9969 | .tcu_atpg_mode(tcu_atpg_mode), | |
9970 | .tcu_array_bypass(tcu_array_bypass), | |
9971 | .cluster_arst_l(cluster_arst_l), | |
9972 | .tcu_mbist_user_mode(tcu_mbist_user_mode) | |
9973 | //.so ( ) | |
9974 | ); | |
9975 | //________________________________________________________________ | |
9976 | ||
9977 | l2b l2b3( | |
9978 | ||
9979 | ||
9980 | .select_delay_mcu ( 1'b1 ), | |
9981 | .ccu_slow_cmp_sync_en ( gl_io_cmp_sync_en_c3b ), // ( gl_io_cmp_sync_en_c3t0 ), - for int6.1 | |
9982 | .ccu_cmp_slow_sync_en ( gl_cmp_io_sync_en_c3b ), // ( gl_cmp_io_sync_en_c3t0 ), - for int6.1 | |
9983 | .gclk ( cmp_gclk_c3_l2b3 ), // cmp_gclk_c0_r[5] ), | |
9984 | .tcu_clk_stop ( gl_l2b3_clk_stop ), // staged clk_stop | |
9985 | .rst_por_ ( gl_l2_por_c3b0 ), // ( gl_l2_por_c3t0 ), - for int6.1 | |
9986 | .rst_wmr_ ( gl_l2_wmr_c3b ), // ( gl_l2_wmr_c3t0 ), - for int6.1 | |
9987 | .l2t_l2b_fbrd_en_c3 (l2t3_l2b3_fbrd_en_c3 ),// scbuf | |
9988 | .l2t_l2b_fbrd_wl_c3 (l2t3_l2b3_fbrd_wl_c3 ), | |
9989 | .l2t_l2b_fbwr_wen_r2 (l2t3_l2b3_fbwr_wen_r2 ), | |
9990 | .l2t_l2b_fbwr_wl_r2 (l2t3_l2b3_fbwr_wl_r2 ), | |
9991 | .l2t_l2b_fbd_stdatasel_c3 (l2t3_l2b3_fbd_stdatasel_c3 ), | |
9992 | .l2t_l2b_stdecc_c2 (l2t3_l2d3_stdecc_c2[ 77 : 0 ] ), | |
9993 | .l2t_l2b_evict_en_r0 (l2t3_l2b3_evict_en_r0 ), | |
9994 | .l2t_l2b_wbwr_wen_c6 (l2t3_l2b3_wbwr_wen_c6 ), | |
9995 | .l2t_l2b_wbwr_wl_c6 (l2t3_l2b3_wbwr_wl_c6 ), | |
9996 | .l2t_l2b_wbrd_en_r0 (l2t3_l2b3_wbrd_en_r0 ), | |
9997 | .l2t_l2b_wbrd_wl_r0 (l2t3_l2b3_wbrd_wl_r0 ), | |
9998 | .l2t_l2b_ev_dword_r0 (l2t3_l2b3_ev_dword_r0 ), | |
9999 | .l2t_l2b_rdma_wren_s2 (l2t3_l2b3_rdma_wren_s2 ), | |
10000 | .l2t_l2b_rdma_wrwl_s2 (l2t3_l2b3_rdma_wrwl_s2 ), | |
10001 | .l2t_l2b_rdma_rden_r0 (l2t3_l2b3_rdma_rden_r0 ), | |
10002 | .l2t_l2b_rdma_rdwl_r0 (l2t3_l2b3_rdma_rdwl_r0 ), | |
10003 | .l2t_l2b_ctag_en_c7 (l2t3_l2b3_ctag_en_c7 ), | |
10004 | .l2t_l2b_ctag_c7 (l2t3_l2b3_ctag_c7[ 31 : 0 ] ), | |
10005 | .l2t_l2b_req_en_c7 (l2t3_l2b3_req_en_c7 ), | |
10006 | .l2t_l2b_word_c7 (l2t3_l2b3_word_c7 ), | |
10007 | .l2t_l2b_word_vld_c7 (l2t3_l2b3_word_vld_c7 ), | |
10008 | .sii_l2t_req (sii_l2t3_req ), | |
10009 | .sii_l2b_ecc (sii_l2b3_ecc[ 6 : 0 ] ), | |
10010 | .l2b_l2d_rvalue (l2b3_l2d3_rvalue[ 9 : 0 ]), | |
10011 | .l2b_l2d_rid (l2b3_l2d3_rid[ 6 : 0 ]), | |
10012 | .l2b_l2d_wr_en (l2b3_l2d3_wr_en), | |
10013 | .l2b_l2d_fuse_clr (l2b3_l2d3_fuse_clr), | |
10014 | .l2d_l2b_fuse_read_data (l2d3_l2b3_fuse_data[ 9 : 0 ]), | |
10015 | .efu_l2b_fuse_data (efu_l2b1357_fuse_data), | |
10016 | .efu_l2b_fuse_xfer_en (efu_l2b3_fuse_xfer_en), | |
10017 | .efu_l2b_fuse_clr (efu_l2b3_fuse_clr), | |
10018 | .l2b_efu_fuse_xfer_en (l2b3_efu_fuse_xfer_en), | |
10019 | .l2b_efu_fuse_data (l2b3_efu_fuse_data), | |
10020 | .l2b_dbg_sio_ctag_vld (l2b3_dbg0_sio_ctag_vld ), | |
10021 | .l2b_dbg_sio_ack_type (l2b3_dbg0_sio_ack_type ), | |
10022 | .l2b_dbg_sio_ack_dest (l2b3_dbg0_sio_ack_dest ), | |
10023 | .l2b_sio_ctag_vld (l2b3_sio_ctag_vld ), | |
10024 | .l2b_sio_data (l2b3_sio_data[ 31 : 0 ] ), | |
10025 | .l2b_sio_parity (l2b3_sio_parity[ 1 : 0 ] ), | |
10026 | .l2b_sio_ue_err (l2b3_sio_ue_err ), | |
10027 | .l2b_l2t_rdma_uerr_c10 (l2b3_l2t3_rdma_uerr_c10 ), | |
10028 | .l2b_l2t_rdma_cerr_c10 (l2b3_l2t3_rdma_cerr_c10 ), | |
10029 | .l2b_l2t_rdma_notdata_c10 (l2b3_l2t3_rdma_notdata_c10 ), | |
10030 | .l2b_l2t_ev_uerr_r5 (l2b3_l2t3_ev_uerr_r5 ), | |
10031 | .l2b_l2t_ev_cerr_r5 (l2b3_l2t3_ev_cerr_r5 ), | |
10032 | .l2d_l2b_decc_out_c7 (l2d3_l2b3_decc_out_c7 ), | |
10033 | .l2b_l2d_fbdecc_c4 (l2b3_l2d3_fbdecc_c4 ), | |
10034 | .mcu_l2b_data_r2 (mcu1_l2b23_data_r2[ 127 : 0 ] ), | |
10035 | .mcu_l2b_ecc_r2 (mcu1_l2b23_ecc_r2[ 27 : 0 ] ), | |
10036 | .tcu_mbist_bisi_en (tcu_mbist_bisi_en ), | |
10037 | .tcu_l2b_mbist_start (tcu_l2b3_mbist_start_ccxlff ), | |
10038 | .l2b_tcu_mbist_done (l2b3_tcu_mbist_done ), | |
10039 | .l2b_tcu_mbist_fail (l2b3_tcu_mbist_fail ), | |
10040 | .tcu_l2b_mbist_scan_in (tcu_l2b3_mbist_scan_in ), | |
10041 | .l2b_tcu_mbist_scan_out (l2b3_tcu_mbist_scan_out ), | |
10042 | .l2b_evict_l2b_mcu_data_mecc_r5 | |
10043 | (l2b3_mcu1_data_mecc_r5 ), | |
10044 | .evict_l2b_mcu_wr_data_r5 (l2b3_mcu1_wr_data_r5[ 63 : 0 ] ), | |
10045 | .evict_l2b_mcu_data_vld_r5(l2b3_mcu1_data_vld_r5 ), | |
10046 | .scan_in (l2b2_scan_out ), | |
10047 | .scan_out (l2b3_scan_out ), | |
10048 | .rst_wmr_protect(rst_wmr_protect), | |
10049 | .tcu_pce_ov(tcu_pce_ov), | |
10050 | .tcu_aclk(tcu_aclk), | |
10051 | .tcu_bclk(tcu_bclk), | |
10052 | .tcu_scan_en(tcu_scan_en), | |
10053 | .tcu_muxtest(tcu_muxtest), | |
10054 | .tcu_dectest(tcu_dectest), | |
10055 | .tcu_se_scancollar_in(tcu_se_scancollar_in), | |
10056 | .tcu_se_scancollar_out(tcu_se_scancollar_out), | |
10057 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit), | |
10058 | .tcu_atpg_mode(tcu_atpg_mode), | |
10059 | .tcu_array_bypass(tcu_array_bypass), | |
10060 | .cluster_arst_l(cluster_arst_l), | |
10061 | .tcu_mbist_user_mode(tcu_mbist_user_mode) | |
10062 | //.so ( ) | |
10063 | ); | |
10064 | //________________________________________________________________ | |
10065 | ||
10066 | l2b l2b4( | |
10067 | .ccu_slow_cmp_sync_en ( gl_io_cmp_sync_en_c1t ), | |
10068 | .ccu_cmp_slow_sync_en ( gl_cmp_io_sync_en_c1t ), | |
10069 | .select_delay_mcu ( 1'b0 ), | |
10070 | ||
10071 | ||
10072 | .gclk ( cmp_gclk_c1_l2b4 ), // cmp_gclk_c3_r[1] ), | |
10073 | .tcu_clk_stop ( gl_l2b4_clk_stop ), // staged clk_stop | |
10074 | .rst_por_ ( gl_l2_por_c1t ), | |
10075 | .rst_wmr_ ( gl_l2_wmr_c1t ), | |
10076 | .l2t_l2b_fbrd_en_c3 (l2t4_l2b4_fbrd_en_c3 ),// scbuf | |
10077 | .l2t_l2b_fbrd_wl_c3 (l2t4_l2b4_fbrd_wl_c3 ), | |
10078 | .l2t_l2b_fbwr_wen_r2 (l2t4_l2b4_fbwr_wen_r2 ), | |
10079 | .l2t_l2b_fbwr_wl_r2 (l2t4_l2b4_fbwr_wl_r2 ), | |
10080 | .l2t_l2b_fbd_stdatasel_c3 (l2t4_l2b4_fbd_stdatasel_c3 ), | |
10081 | .l2t_l2b_stdecc_c2 (l2t4_l2d4_stdecc_c2[ 77 : 0 ] ), | |
10082 | .l2t_l2b_evict_en_r0 (l2t4_l2b4_evict_en_r0 ), | |
10083 | .l2t_l2b_wbwr_wen_c6 (l2t4_l2b4_wbwr_wen_c6 ), | |
10084 | .l2t_l2b_wbwr_wl_c6 (l2t4_l2b4_wbwr_wl_c6 ), | |
10085 | .l2t_l2b_wbrd_en_r0 (l2t4_l2b4_wbrd_en_r0 ), | |
10086 | .l2t_l2b_wbrd_wl_r0 (l2t4_l2b4_wbrd_wl_r0 ), | |
10087 | .l2t_l2b_ev_dword_r0 (l2t4_l2b4_ev_dword_r0 ), | |
10088 | .l2t_l2b_rdma_wren_s2 (l2t4_l2b4_rdma_wren_s2 ), | |
10089 | .l2t_l2b_rdma_wrwl_s2 (l2t4_l2b4_rdma_wrwl_s2 ), | |
10090 | .l2t_l2b_rdma_rden_r0 (l2t4_l2b4_rdma_rden_r0 ), | |
10091 | .l2t_l2b_rdma_rdwl_r0 (l2t4_l2b4_rdma_rdwl_r0 ), | |
10092 | .l2t_l2b_ctag_en_c7 (l2t4_l2b4_ctag_en_c7 ), | |
10093 | .l2t_l2b_ctag_c7 (l2t4_l2b4_ctag_c7[ 31 : 0 ] ), | |
10094 | .l2t_l2b_req_en_c7 (l2t4_l2b4_req_en_c7 ), | |
10095 | .l2t_l2b_word_c7 (l2t4_l2b4_word_c7 ), | |
10096 | .l2t_l2b_word_vld_c7 (l2t4_l2b4_word_vld_c7 ), | |
10097 | .sii_l2t_req (sii_l2t4_req_t4lff[ 31 : 0 ] ), | |
10098 | .sii_l2b_ecc (sii_l2b4_ecc_t4lff[ 6 : 0 ] ), | |
10099 | .l2b_l2d_rvalue (l2b4_l2d4_rvalue[ 9 : 0 ]), | |
10100 | .l2b_l2d_rid (l2b4_l2d4_rid[ 6 : 0 ]), | |
10101 | .l2b_l2d_wr_en (l2b4_l2d4_wr_en), | |
10102 | .l2b_l2d_fuse_clr (l2b4_l2d4_fuse_clr), | |
10103 | .l2d_l2b_fuse_read_data (l2d4_l2b4_fuse_data[ 9 : 0 ]), | |
10104 | .efu_l2b_fuse_data (efu_l2b0246_fuse_data), | |
10105 | .efu_l2b_fuse_xfer_en (efu_l2b4_fuse_xfer_en), | |
10106 | .efu_l2b_fuse_clr (efu_l2b4_fuse_clr), | |
10107 | .l2b_efu_fuse_xfer_en (l2b4_efu_fuse_xfer_en), | |
10108 | .l2b_efu_fuse_data (l2b4_efu_fuse_data), | |
10109 | .l2b_dbg_sio_ctag_vld (l2b4_dbg1_sio_ctag_vld ), | |
10110 | .l2b_dbg_sio_ack_type (l2b4_dbg1_sio_ack_type ), | |
10111 | .l2b_dbg_sio_ack_dest (l2b4_dbg1_sio_ack_dest ), | |
10112 | .l2b_sio_ctag_vld (l2b4_sio_ctag_vld ), | |
10113 | .l2b_sio_data (l2b4_sio_data[ 31 : 0 ] ), | |
10114 | .l2b_sio_parity (l2b4_sio_parity[ 1 : 0 ] ), | |
10115 | .l2b_sio_ue_err (l2b4_sio_ue_err ), | |
10116 | .l2b_l2t_rdma_uerr_c10 (l2b4_l2t4_rdma_uerr_c10 ), | |
10117 | .l2b_l2t_rdma_cerr_c10 (l2b4_l2t4_rdma_cerr_c10 ), | |
10118 | .l2b_l2t_rdma_notdata_c10 (l2b4_l2t4_rdma_notdata_c10 ), | |
10119 | .l2b_l2t_ev_uerr_r5 (l2b4_l2t4_ev_uerr_r5 ), | |
10120 | .l2b_l2t_ev_cerr_r5 (l2b4_l2t4_ev_cerr_r5 ), | |
10121 | .l2d_l2b_decc_out_c7 (l2d4_l2b4_decc_out_c7 ), | |
10122 | .l2b_l2d_fbdecc_c4 (l2b4_l2d4_fbdecc_c4 ), | |
10123 | .mcu_l2b_data_r2 (mcu2_l2b45_data_r2[ 127 : 0 ] ), | |
10124 | .mcu_l2b_ecc_r2 (mcu2_l2b45_ecc_r2[ 27 : 0 ] ), | |
10125 | .tcu_mbist_bisi_en (tcu_mbist_bisi_en ), | |
10126 | .tcu_l2b_mbist_start (tcu_l2b4_mbist_start ), | |
10127 | .l2b_tcu_mbist_done (l2b4_tcu_mbist_done ), | |
10128 | .l2b_tcu_mbist_fail (l2b4_tcu_mbist_fail ), | |
10129 | .tcu_l2b_mbist_scan_in (tcu_l2b4_mbist_scan_in ), | |
10130 | .l2b_tcu_mbist_scan_out (l2b4_tcu_mbist_scan_out ), | |
10131 | .l2b_evict_l2b_mcu_data_mecc_r5 | |
10132 | (l2b4_mcu2_data_mecc_r5 ), | |
10133 | .evict_l2b_mcu_wr_data_r5 (l2b4_mcu2_wr_data_r5[ 63 : 0 ] ), | |
10134 | .evict_l2b_mcu_data_vld_r5(l2b4_mcu2_data_vld_r5 ), | |
10135 | .scan_in (l2b3_scan_out ), | |
10136 | .scan_out (l2b4_scan_out ), | |
10137 | .rst_wmr_protect(rst_wmr_protect), | |
10138 | .tcu_pce_ov(tcu_pce_ov), | |
10139 | .tcu_aclk(tcu_aclk), | |
10140 | .tcu_bclk(tcu_bclk), | |
10141 | .tcu_scan_en(tcu_scan_en), | |
10142 | .tcu_muxtest(tcu_muxtest), | |
10143 | .tcu_dectest(tcu_dectest), | |
10144 | .tcu_se_scancollar_in(tcu_se_scancollar_in), | |
10145 | .tcu_se_scancollar_out(tcu_se_scancollar_out), | |
10146 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit), | |
10147 | .tcu_atpg_mode(tcu_atpg_mode), | |
10148 | .tcu_array_bypass(tcu_array_bypass), | |
10149 | .cluster_arst_l(cluster_arst_l), | |
10150 | .tcu_mbist_user_mode(tcu_mbist_user_mode) | |
10151 | //.so ( ) | |
10152 | ); | |
10153 | //________________________________________________________________ | |
10154 | ||
10155 | l2b l2b5( | |
10156 | .ccu_slow_cmp_sync_en ( gl_io_cmp_sync_en_c1t ), | |
10157 | .ccu_cmp_slow_sync_en ( gl_cmp_io_sync_en_c1t ), | |
10158 | .select_delay_mcu ( 1'b1 ), | |
10159 | ||
10160 | ||
10161 | .gclk ( cmp_gclk_c1_l2b5 ), // cmp_gclk_c3_r[2] ), | |
10162 | .tcu_clk_stop ( gl_l2b5_clk_stop ), // staged clk_stop | |
10163 | .rst_por_ ( gl_rst_l2_por_c1m ), // ( gl_l2_por_c1t ), - for int6.1 | |
10164 | .rst_wmr_ ( gl_rst_l2_wmr_c1m ), // ( gl_l2_wmr_c1b ), - for int6.1 | |
10165 | .l2t_l2b_fbrd_en_c3 (l2t5_l2b5_fbrd_en_c3 ),// scbuf | |
10166 | .l2t_l2b_fbrd_wl_c3 (l2t5_l2b5_fbrd_wl_c3 ), | |
10167 | .l2t_l2b_fbwr_wen_r2 (l2t5_l2b5_fbwr_wen_r2 ), | |
10168 | .l2t_l2b_fbwr_wl_r2 (l2t5_l2b5_fbwr_wl_r2 ), | |
10169 | .l2t_l2b_fbd_stdatasel_c3 (l2t5_l2b5_fbd_stdatasel_c3 ), | |
10170 | .l2t_l2b_stdecc_c2 (l2t5_l2d5_stdecc_c2[ 77 : 0 ] ), | |
10171 | .l2t_l2b_evict_en_r0 (l2t5_l2b5_evict_en_r0 ), | |
10172 | .l2t_l2b_wbwr_wen_c6 (l2t5_l2b5_wbwr_wen_c6 ), | |
10173 | .l2t_l2b_wbwr_wl_c6 (l2t5_l2b5_wbwr_wl_c6 ), | |
10174 | .l2t_l2b_wbrd_en_r0 (l2t5_l2b5_wbrd_en_r0 ), | |
10175 | .l2t_l2b_wbrd_wl_r0 (l2t5_l2b5_wbrd_wl_r0 ), | |
10176 | .l2t_l2b_ev_dword_r0 (l2t5_l2b5_ev_dword_r0 ), | |
10177 | .l2t_l2b_rdma_wren_s2 (l2t5_l2b5_rdma_wren_s2 ), | |
10178 | .l2t_l2b_rdma_wrwl_s2 (l2t5_l2b5_rdma_wrwl_s2 ), | |
10179 | .l2t_l2b_rdma_rden_r0 (l2t5_l2b5_rdma_rden_r0 ), | |
10180 | .l2t_l2b_rdma_rdwl_r0 (l2t5_l2b5_rdma_rdwl_r0 ), | |
10181 | .l2t_l2b_ctag_en_c7 (l2t5_l2b5_ctag_en_c7 ), | |
10182 | .l2t_l2b_ctag_c7 (l2t5_l2b5_ctag_c7[ 31 : 0 ] ), | |
10183 | .l2t_l2b_req_en_c7 (l2t5_l2b5_req_en_c7 ), | |
10184 | .l2t_l2b_word_c7 (l2t5_l2b5_word_c7 ), | |
10185 | .l2t_l2b_word_vld_c7 (l2t5_l2b5_word_vld_c7 ), | |
10186 | .sii_l2t_req (sii_l2t5_req_t4lff[ 31 : 0 ] ), | |
10187 | .sii_l2b_ecc (sii_l2b5_ecc_ccxrff[ 6 : 0 ] ), | |
10188 | .l2b_l2d_rvalue (l2b5_l2d5_rvalue[ 9 : 0 ]), | |
10189 | .l2b_l2d_rid (l2b5_l2d5_rid[ 6 : 0 ]), | |
10190 | .l2b_l2d_wr_en (l2b5_l2d5_wr_en), | |
10191 | .l2b_l2d_fuse_clr (l2b5_l2d5_fuse_clr), | |
10192 | .l2d_l2b_fuse_read_data (l2d5_l2b5_fuse_data[ 9 : 0 ]), | |
10193 | .efu_l2b_fuse_data (efu_l2b1357_fuse_data), | |
10194 | .efu_l2b_fuse_xfer_en (efu_l2b5_fuse_xfer_en), | |
10195 | .efu_l2b_fuse_clr (efu_l2b5_fuse_clr), | |
10196 | .l2b_efu_fuse_xfer_en (l2b5_efu_fuse_xfer_en), | |
10197 | .l2b_efu_fuse_data (l2b5_efu_fuse_data), | |
10198 | .l2b_dbg_sio_ctag_vld (l2b5_dbg1_sio_ctag_vld ), | |
10199 | .l2b_dbg_sio_ack_type (l2b5_dbg1_sio_ack_type ), | |
10200 | .l2b_dbg_sio_ack_dest (l2b5_dbg1_sio_ack_dest ), | |
10201 | .l2b_sio_ctag_vld (l2b5_sio_ctag_vld ), | |
10202 | .l2b_sio_data (l2b5_sio_data[ 31 : 0 ] ), | |
10203 | .l2b_sio_parity (l2b5_sio_parity[ 1 : 0 ] ), | |
10204 | .l2b_sio_ue_err (l2b5_sio_ue_err ), | |
10205 | .l2b_l2t_rdma_uerr_c10 (l2b5_l2t5_rdma_uerr_c10 ), | |
10206 | .l2b_l2t_rdma_cerr_c10 (l2b5_l2t5_rdma_cerr_c10 ), | |
10207 | .l2b_l2t_rdma_notdata_c10 (l2b5_l2t5_rdma_notdata_c10 ), | |
10208 | .l2b_l2t_ev_uerr_r5 (l2b5_l2t5_ev_uerr_r5 ), | |
10209 | .l2b_l2t_ev_cerr_r5 (l2b5_l2t5_ev_cerr_r5 ), | |
10210 | .l2d_l2b_decc_out_c7 (l2d5_l2b5_decc_out_c7 ), | |
10211 | .l2b_l2d_fbdecc_c4 (l2b5_l2d5_fbdecc_c4 ), | |
10212 | .mcu_l2b_data_r2 (mcu2_l2b45_data_r2[ 127 : 0 ] ), | |
10213 | .mcu_l2b_ecc_r2 (mcu2_l2b45_ecc_r2[ 27 : 0 ] ), | |
10214 | .tcu_mbist_bisi_en (tcu_mbist_bisi_en ), | |
10215 | .tcu_l2b_mbist_start (tcu_l2b5_mbist_start ), | |
10216 | .l2b_tcu_mbist_done (l2b5_tcu_mbist_done ), | |
10217 | .l2b_tcu_mbist_fail (l2b5_tcu_mbist_fail ), | |
10218 | .tcu_l2b_mbist_scan_in (tcu_l2b5_mbist_scan_in ), | |
10219 | .l2b_tcu_mbist_scan_out (l2b5_tcu_mbist_scan_out ), | |
10220 | .l2b_evict_l2b_mcu_data_mecc_r5 | |
10221 | (l2b5_mcu2_data_mecc_r5 ), | |
10222 | .evict_l2b_mcu_wr_data_r5 (l2b5_mcu2_wr_data_r5[ 63 : 0 ] ), | |
10223 | .evict_l2b_mcu_data_vld_r5(l2b5_mcu2_data_vld_r5 ), | |
10224 | .scan_in (l2b4_scan_out ), | |
10225 | .scan_out (l2b5_scan_out ), | |
10226 | .rst_wmr_protect(rst_wmr_protect), | |
10227 | .tcu_pce_ov(tcu_pce_ov), | |
10228 | .tcu_aclk(tcu_aclk), | |
10229 | .tcu_bclk(tcu_bclk), | |
10230 | .tcu_scan_en(tcu_scan_en), | |
10231 | .tcu_muxtest(tcu_muxtest), | |
10232 | .tcu_dectest(tcu_dectest), | |
10233 | .tcu_se_scancollar_in(tcu_se_scancollar_in), | |
10234 | .tcu_se_scancollar_out(tcu_se_scancollar_out), | |
10235 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit), | |
10236 | .tcu_atpg_mode(tcu_atpg_mode), | |
10237 | .tcu_array_bypass(tcu_array_bypass), | |
10238 | .cluster_arst_l(cluster_arst_l), | |
10239 | .tcu_mbist_user_mode(tcu_mbist_user_mode) | |
10240 | //.so ( ) | |
10241 | ); | |
10242 | //________________________________________________________________ | |
10243 | ||
10244 | l2b l2b6( | |
10245 | .ccu_slow_cmp_sync_en ( gl_io_cmp_sync_en_c1m ), | |
10246 | .ccu_cmp_slow_sync_en ( gl_cmp_io_sync_en_c1m ), | |
10247 | .select_delay_mcu ( 1'b0 ), | |
10248 | ||
10249 | ||
10250 | .gclk ( cmp_gclk_c1_l2b6 ), // cmp_gclk_c3_r[4] ), | |
10251 | .tcu_clk_stop ( gl_l2b6_clk_stop ), // staged clk_stop | |
10252 | .rst_por_ ( gl_l2_por_c1b ), // ( gl_l2_por_c1t ), - for int6.1 | |
10253 | .rst_wmr_ ( gl_l2_wmr_c1b ), | |
10254 | .l2t_l2b_fbrd_en_c3 (l2t6_l2b6_fbrd_en_c3 ),// scbuf | |
10255 | .l2t_l2b_fbrd_wl_c3 (l2t6_l2b6_fbrd_wl_c3 ), | |
10256 | .l2t_l2b_fbwr_wen_r2 (l2t6_l2b6_fbwr_wen_r2 ), | |
10257 | .l2t_l2b_fbwr_wl_r2 (l2t6_l2b6_fbwr_wl_r2 ), | |
10258 | .l2t_l2b_fbd_stdatasel_c3 (l2t6_l2b6_fbd_stdatasel_c3 ), | |
10259 | .l2t_l2b_stdecc_c2 (l2t6_l2d6_stdecc_c2[ 77 : 0 ] ), | |
10260 | .l2t_l2b_evict_en_r0 (l2t6_l2b6_evict_en_r0 ), | |
10261 | .l2t_l2b_wbwr_wen_c6 (l2t6_l2b6_wbwr_wen_c6 ), | |
10262 | .l2t_l2b_wbwr_wl_c6 (l2t6_l2b6_wbwr_wl_c6 ), | |
10263 | .l2t_l2b_wbrd_en_r0 (l2t6_l2b6_wbrd_en_r0 ), | |
10264 | .l2t_l2b_wbrd_wl_r0 (l2t6_l2b6_wbrd_wl_r0 ), | |
10265 | .l2t_l2b_ev_dword_r0 (l2t6_l2b6_ev_dword_r0 ), | |
10266 | .l2t_l2b_rdma_wren_s2 (l2t6_l2b6_rdma_wren_s2 ), | |
10267 | .l2t_l2b_rdma_wrwl_s2 (l2t6_l2b6_rdma_wrwl_s2 ), | |
10268 | .l2t_l2b_rdma_rden_r0 (l2t6_l2b6_rdma_rden_r0 ), | |
10269 | .l2t_l2b_rdma_rdwl_r0 (l2t6_l2b6_rdma_rdwl_r0 ), | |
10270 | .l2t_l2b_ctag_en_c7 (l2t6_l2b6_ctag_en_c7 ), | |
10271 | .l2t_l2b_ctag_c7 (l2t6_l2b6_ctag_c7[ 31 : 0 ] ), | |
10272 | .l2t_l2b_req_en_c7 (l2t6_l2b6_req_en_c7 ), | |
10273 | .l2t_l2b_word_c7 (l2t6_l2b6_word_c7 ), | |
10274 | .l2t_l2b_word_vld_c7 (l2t6_l2b6_word_vld_c7 ), | |
10275 | .sii_l2t_req (sii_l2t6_req_t6lff ), | |
10276 | .sii_l2b_ecc (sii_l2b6_ecc_ccxrff[ 6 : 0 ] ), | |
10277 | .l2b_l2d_rvalue (l2b6_l2d6_rvalue[ 9 : 0 ]), | |
10278 | .l2b_l2d_rid (l2b6_l2d6_rid[ 6 : 0 ]), | |
10279 | .l2b_l2d_wr_en (l2b6_l2d6_wr_en), | |
10280 | .l2b_l2d_fuse_clr (l2b6_l2d6_fuse_clr), | |
10281 | .l2d_l2b_fuse_read_data (l2d6_l2b6_fuse_data[ 9 : 0 ]), | |
10282 | .efu_l2b_fuse_data (efu_l2b0246_fuse_data), | |
10283 | .efu_l2b_fuse_xfer_en (efu_l2b6_fuse_xfer_en), | |
10284 | .efu_l2b_fuse_clr (efu_l2b6_fuse_clr), | |
10285 | .l2b_efu_fuse_xfer_en (l2b6_efu_fuse_xfer_en), | |
10286 | .l2b_efu_fuse_data (l2b6_efu_fuse_data), | |
10287 | .l2b_dbg_sio_ctag_vld (l2b6_dbg1_sio_ctag_vld ), | |
10288 | .l2b_dbg_sio_ack_type (l2b6_dbg1_sio_ack_type ), | |
10289 | .l2b_dbg_sio_ack_dest (l2b6_dbg1_sio_ack_dest ), | |
10290 | .l2b_sio_ctag_vld (l2b6_sio_ctag_vld ), | |
10291 | .l2b_sio_data (l2b6_sio_data[ 31 : 0 ] ), | |
10292 | .l2b_sio_parity (l2b6_sio_parity[ 1 : 0 ] ), | |
10293 | .l2b_sio_ue_err (l2b6_sio_ue_err ), | |
10294 | .l2b_l2t_rdma_uerr_c10 (l2b6_l2t6_rdma_uerr_c10 ), | |
10295 | .l2b_l2t_rdma_cerr_c10 (l2b6_l2t6_rdma_cerr_c10 ), | |
10296 | .l2b_l2t_rdma_notdata_c10 (l2b6_l2t6_rdma_notdata_c10 ), | |
10297 | .l2b_l2t_ev_uerr_r5 (l2b6_l2t6_ev_uerr_r5 ), | |
10298 | .l2b_l2t_ev_cerr_r5 (l2b6_l2t6_ev_cerr_r5 ), | |
10299 | .l2d_l2b_decc_out_c7 (l2d6_l2b6_decc_out_c7 ), | |
10300 | .l2b_l2d_fbdecc_c4 (l2b6_l2d6_fbdecc_c4 ), | |
10301 | .mcu_l2b_data_r2 (mcu3_l2b67_data_r2[ 127 : 0 ] ), | |
10302 | .mcu_l2b_ecc_r2 (mcu3_l2b67_ecc_r2[ 27 : 0 ] ), | |
10303 | .tcu_mbist_bisi_en (tcu_mbist_bisi_en ), | |
10304 | .tcu_l2b_mbist_start (tcu_l2b6_mbist_start ), | |
10305 | .l2b_tcu_mbist_done (l2b6_tcu_mbist_done ), | |
10306 | .l2b_tcu_mbist_fail (l2b6_tcu_mbist_fail ), | |
10307 | .tcu_l2b_mbist_scan_in (tcu_l2b6_mbist_scan_in ), | |
10308 | .l2b_tcu_mbist_scan_out (l2b6_tcu_mbist_scan_out ), | |
10309 | .l2b_evict_l2b_mcu_data_mecc_r5 | |
10310 | (l2b6_mcu3_data_mecc_r5 ), | |
10311 | .evict_l2b_mcu_wr_data_r5 (l2b6_mcu3_wr_data_r5[ 63 : 0 ] ), | |
10312 | .evict_l2b_mcu_data_vld_r5(l2b6_mcu3_data_vld_r5 ), | |
10313 | .scan_in (l2b5_scan_out ), | |
10314 | .scan_out (l2b6_scan_out ), | |
10315 | .rst_wmr_protect(rst_wmr_protect), | |
10316 | .tcu_pce_ov(tcu_pce_ov), | |
10317 | .tcu_aclk(tcu_aclk), | |
10318 | .tcu_bclk(tcu_bclk), | |
10319 | .tcu_scan_en(tcu_scan_en), | |
10320 | .tcu_muxtest(tcu_muxtest), | |
10321 | .tcu_dectest(tcu_dectest), | |
10322 | .tcu_se_scancollar_in(tcu_se_scancollar_in), | |
10323 | .tcu_se_scancollar_out(tcu_se_scancollar_out), | |
10324 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit), | |
10325 | .tcu_atpg_mode(tcu_atpg_mode), | |
10326 | .tcu_array_bypass(tcu_array_bypass), | |
10327 | .cluster_arst_l(cluster_arst_l), | |
10328 | .tcu_mbist_user_mode(tcu_mbist_user_mode) | |
10329 | //.so ( ) | |
10330 | ); | |
10331 | //________________________________________________________________ | |
10332 | ||
10333 | l2b l2b7( | |
10334 | .ccu_slow_cmp_sync_en ( gl_io_cmp_sync_en_c1b ), // ECO c1m -> c1b - mh157021 | |
10335 | .ccu_cmp_slow_sync_en ( gl_cmp_io_sync_en_c1b ), // ECO c1m -> c1b - mh157021 | |
10336 | .select_delay_mcu ( 1'b1 ), | |
10337 | ||
10338 | ||
10339 | .gclk ( cmp_gclk_c1_l2b7 ), // cmp_gclk_c3_r[5] ), | |
10340 | .tcu_clk_stop ( gl_l2b7_clk_stop ), // staged clk_stop | |
10341 | .rst_por_ ( gl_l2_por_c1b ), // ECO again c1m -> c1b mh157021 // ( gl_l2_por_c1t ), - for int6.1 | |
10342 | .rst_wmr_ ( gl_l2_wmr_c1b ), // ECO again c1m -> c1b mh157021 // ( gl_l2_wmr_c1b ), - for int6.1 | |
10343 | .l2t_l2b_fbrd_en_c3 (l2t7_l2b7_fbrd_en_c3 ),// scbuf | |
10344 | .l2t_l2b_fbrd_wl_c3 (l2t7_l2b7_fbrd_wl_c3 ), | |
10345 | .l2t_l2b_fbwr_wen_r2 (l2t7_l2b7_fbwr_wen_r2 ), | |
10346 | .l2t_l2b_fbwr_wl_r2 (l2t7_l2b7_fbwr_wl_r2 ), | |
10347 | .l2t_l2b_fbd_stdatasel_c3 (l2t7_l2b7_fbd_stdatasel_c3 ), | |
10348 | .l2t_l2b_stdecc_c2 (l2t7_l2d7_stdecc_c2[ 77 : 0 ] ), | |
10349 | .l2t_l2b_evict_en_r0 (l2t7_l2b7_evict_en_r0 ), | |
10350 | .l2t_l2b_wbwr_wen_c6 (l2t7_l2b7_wbwr_wen_c6 ), | |
10351 | .l2t_l2b_wbwr_wl_c6 (l2t7_l2b7_wbwr_wl_c6 ), | |
10352 | .l2t_l2b_wbrd_en_r0 (l2t7_l2b7_wbrd_en_r0 ), | |
10353 | .l2t_l2b_wbrd_wl_r0 (l2t7_l2b7_wbrd_wl_r0 ), | |
10354 | .l2t_l2b_ev_dword_r0 (l2t7_l2b7_ev_dword_r0 ), | |
10355 | .l2t_l2b_rdma_wren_s2 (l2t7_l2b7_rdma_wren_s2 ), | |
10356 | .l2t_l2b_rdma_wrwl_s2 (l2t7_l2b7_rdma_wrwl_s2 ), | |
10357 | .l2t_l2b_rdma_rden_r0 (l2t7_l2b7_rdma_rden_r0 ), | |
10358 | .l2t_l2b_rdma_rdwl_r0 (l2t7_l2b7_rdma_rdwl_r0 ), | |
10359 | .l2t_l2b_ctag_en_c7 (l2t7_l2b7_ctag_en_c7 ), | |
10360 | .l2t_l2b_ctag_c7 (l2t7_l2b7_ctag_c7[ 31 : 0 ] ), | |
10361 | .l2t_l2b_req_en_c7 (l2t7_l2b7_req_en_c7 ), | |
10362 | .l2t_l2b_word_c7 (l2t7_l2b7_word_c7 ), | |
10363 | .l2t_l2b_word_vld_c7 (l2t7_l2b7_word_vld_c7 ), | |
10364 | .sii_l2t_req (sii_l2t7_req_t6lff ), | |
10365 | .sii_l2b_ecc (sii_l2b7_ecc_ccxrff[ 6 : 0 ] ), | |
10366 | .l2b_l2d_rvalue (l2b7_l2d7_rvalue[ 9 : 0 ]), | |
10367 | .l2b_l2d_rid (l2b7_l2d7_rid[ 6 : 0 ]), | |
10368 | .l2b_l2d_wr_en (l2b7_l2d7_wr_en), | |
10369 | .l2b_l2d_fuse_clr (l2b7_l2d7_fuse_clr), | |
10370 | .l2d_l2b_fuse_read_data (l2d7_l2b7_fuse_data[ 9 : 0 ]), | |
10371 | .efu_l2b_fuse_data (efu_l2b1357_fuse_data), | |
10372 | .efu_l2b_fuse_xfer_en (efu_l2b7_fuse_xfer_en), | |
10373 | .efu_l2b_fuse_clr (efu_l2b7_fuse_clr), | |
10374 | .l2b_efu_fuse_xfer_en (l2b7_efu_fuse_xfer_en), | |
10375 | .l2b_efu_fuse_data (l2b7_efu_fuse_data), | |
10376 | .l2b_dbg_sio_ctag_vld (l2b7_dbg1_sio_ctag_vld ), | |
10377 | .l2b_dbg_sio_ack_type (l2b7_dbg1_sio_ack_type ), | |
10378 | .l2b_dbg_sio_ack_dest (l2b7_dbg1_sio_ack_dest ), | |
10379 | .l2b_sio_ctag_vld (l2b7_sio_ctag_vld ), | |
10380 | .l2b_sio_data (l2b7_sio_data[ 31 : 0 ] ), | |
10381 | .l2b_sio_parity (l2b7_sio_parity[ 1 : 0 ] ), | |
10382 | .l2b_sio_ue_err (l2b7_sio_ue_err ), | |
10383 | .l2b_l2t_rdma_uerr_c10 (l2b7_l2t7_rdma_uerr_c10 ), | |
10384 | .l2b_l2t_rdma_cerr_c10 (l2b7_l2t7_rdma_cerr_c10 ), | |
10385 | .l2b_l2t_rdma_notdata_c10 (l2b7_l2t7_rdma_notdata_c10 ), | |
10386 | .l2b_l2t_ev_uerr_r5 (l2b7_l2t7_ev_uerr_r5 ), | |
10387 | .l2b_l2t_ev_cerr_r5 (l2b7_l2t7_ev_cerr_r5 ), | |
10388 | .l2d_l2b_decc_out_c7 (l2d7_l2b7_decc_out_c7 ), | |
10389 | .l2b_l2d_fbdecc_c4 (l2b7_l2d7_fbdecc_c4 ), | |
10390 | .mcu_l2b_data_r2 (mcu3_l2b67_data_r2[ 127 : 0 ] ), | |
10391 | .mcu_l2b_ecc_r2 (mcu3_l2b67_ecc_r2[ 27 : 0 ] ), | |
10392 | .tcu_mbist_bisi_en (tcu_mbist_bisi_en ), | |
10393 | .tcu_l2b_mbist_start (tcu_l2b7_mbist_start ), | |
10394 | .l2b_tcu_mbist_done (l2b7_tcu_mbist_done ), | |
10395 | .l2b_tcu_mbist_fail (l2b7_tcu_mbist_fail ), | |
10396 | .tcu_l2b_mbist_scan_in (tcu_l2b7_mbist_scan_in ), | |
10397 | .l2b_tcu_mbist_scan_out (l2b7_tcu_mbist_scan_out ), | |
10398 | .l2b_evict_l2b_mcu_data_mecc_r5 | |
10399 | (l2b7_mcu3_data_mecc_r5 ), | |
10400 | .evict_l2b_mcu_wr_data_r5 (l2b7_mcu3_wr_data_r5[ 63 : 0 ] ), | |
10401 | .evict_l2b_mcu_data_vld_r5(l2b7_mcu3_data_vld_r5 ), | |
10402 | .scan_in (l2b6_scan_out ), | |
10403 | .scan_out (l2b7_scan_out ), | |
10404 | .rst_wmr_protect(rst_wmr_protect), | |
10405 | .tcu_pce_ov(tcu_pce_ov), | |
10406 | .tcu_aclk(tcu_aclk), | |
10407 | .tcu_bclk(tcu_bclk), | |
10408 | .tcu_scan_en(tcu_scan_en), | |
10409 | .tcu_muxtest(tcu_muxtest), | |
10410 | .tcu_dectest(tcu_dectest), | |
10411 | .tcu_se_scancollar_in(tcu_se_scancollar_in), | |
10412 | .tcu_se_scancollar_out(tcu_se_scancollar_out), | |
10413 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit), | |
10414 | .tcu_atpg_mode(tcu_atpg_mode), | |
10415 | .tcu_array_bypass(tcu_array_bypass), | |
10416 | .cluster_arst_l(cluster_arst_l), | |
10417 | .tcu_mbist_user_mode(tcu_mbist_user_mode) | |
10418 | //.so ( ) | |
10419 | ); | |
10420 | //________________________________________________________________ | |
10421 | ||
10422 | // leave this instance out of cmp model | |
10423 | `ifdef OPENSPARC_CMP | |
10424 | `else | |
10425 | mcu mcu0( | |
10426 | .gclk ( cmp_gclk_c4_mcu0 ), // cmp_gclk_c0_r[2] ) , | |
10427 | .tcu_mcu_clk_stop ( gl_mcu0_clk_stop ), // staged clk_stop | |
10428 | .tcu_mcu_dr_clk_stop ( gl_mcu0_dr_clk_stop ), // staged clk_stop | |
10429 | .tcu_mcu_io_clk_stop ( gl_mcu0_io_clk_stop ), // staged clk_stop | |
10430 | .ccu_io_out ( gl_io_out_c3t ), // staged div phase | |
10431 | .dr_gclk ( dr_gclk_c4_mcu0 ), // dr_gclk_c0_r[2] ) , | |
10432 | .ccu_dr_sync_en (gl_dr_sync_en_c3t), | |
10433 | .ccu_io_cmp_sync_en ( gl_io_cmp_sync_en_c3t ), | |
10434 | .ccu_cmp_io_sync_en ( gl_cmp_io_sync_en_c3t ), | |
10435 | .tcu_mcu_fbd_clk_stop (tcu_mcu0_fbd_clk_stop ), | |
10436 | .mcu_dbg1_rd_req_in_0 (mcu0_dbg1_rd_req_in_0[ 3 : 0 ] ), | |
10437 | .mcu_dbg1_rd_req_in_1 (mcu0_dbg1_rd_req_in_1[ 3 : 0 ] ), | |
10438 | .mcu_dbg1_rd_req_out (mcu0_dbg1_rd_req_out[ 4 : 0 ] ), | |
10439 | .mcu_dbg1_wr_req_in_0 (mcu0_dbg1_wr_req_in_0 ), | |
10440 | .mcu_dbg1_wr_req_in_1 (mcu0_dbg1_wr_req_in_1 ), | |
10441 | .mcu_dbg1_wr_req_out (mcu0_dbg1_wr_req_out[ 1 : 0 ] ), | |
10442 | .mcu_dbg1_mecc_err (mcu0_dbg1_mecc_err ), | |
10443 | .mcu_dbg1_secc_err (mcu0_dbg1_secc_err ), | |
10444 | .mcu_dbg1_fbd_err (mcu0_dbg1_fbd_err ), | |
10445 | .mcu_dbg1_err_mode (mcu0_dbg1_err_mode ), | |
10446 | .mcu_dbg1_err_event (mcu0_dbg1_err_event ), | |
10447 | .mcu_dbg1_crc21 (mcu0_dbg1_crc21 ), | |
10448 | .l2t0_mcu_rd_req (l2t0_mcu0_rd_req ), | |
10449 | .l2t0_mcu_wr_req (l2t0_mcu0_wr_req ), | |
10450 | .l2t0_mcu_rd_dummy_req (l2t0_mcu0_rd_dummy_req ), | |
10451 | .l2t0_mcu_rd_req_id (l2t0_mcu0_rd_req_id[ 2 : 0 ] ), | |
10452 | .l2t0_mcu_addr_39to7 (l2t0_mcu0_addr[ 39 : 7 ] ), | |
10453 | .l2t0_mcu_addr_5 (l2t0_mcu0_addr_5 ), | |
10454 | .mcu_l2t0_rd_ack (mcu0_l2t0_rd_ack ), | |
10455 | .mcu_l2t0_wr_ack (mcu0_l2t0_wr_ack ), | |
10456 | .mcu_l2t0_data_vld_r0 (mcu0_l2t0_data_vld_r0 ), | |
10457 | .mcu_l2t0_rd_req_id_r0 (mcu0_l2t0_rd_req_id_r0[ 2 : 0 ] ), | |
10458 | .mcu_l2t0_secc_err_r3 (mcu0_l2t0_secc_err_r2 ), | |
10459 | .mcu_l2t0_mecc_err_r3 (mcu0_l2t0_mecc_err_r2 ), | |
10460 | .mcu_l2t0_scb_secc_err (mcu0_l2t0_scb_secc_err ), | |
10461 | .mcu_l2t0_scb_mecc_err (mcu0_l2t0_scb_mecc_err ), | |
10462 | .mcu_l2t0_qword_id_r0 (mcu0_l2t0_qword_id_r0[ 1 : 0 ] ), | |
10463 | .l2t1_mcu_rd_req (l2t1_mcu0_rd_req_t0lff ), | |
10464 | .l2t1_mcu_wr_req (l2t1_mcu0_wr_req_t0lff ), | |
10465 | .l2t1_mcu_rd_dummy_req (l2t1_mcu0_rd_dummy_req_t0lff ), | |
10466 | .l2t1_mcu_rd_req_id (l2t1_mcu0_rd_req_id_t0lff[ 2 : 0 ] ), | |
10467 | .l2t1_mcu_addr_39to7 (l2t1_mcu0_addr_t0lff[ 39 : 7 ] ), | |
10468 | .l2t1_mcu_addr_5 (l2t1_mcu0_addr_5_t0lff ), | |
10469 | .mcu_l2t1_rd_ack (mcu0_l2t1_rd_ack ), | |
10470 | .mcu_l2t1_wr_ack (mcu0_l2t1_wr_ack ), | |
10471 | .mcu_l2t1_data_vld_r0 (mcu0_l2t1_data_vld_r0 ), | |
10472 | .mcu_l2t1_rd_req_id_r0 (mcu0_l2t1_rd_req_id_r0[ 2 : 0 ] ), | |
10473 | .mcu_l2t1_secc_err_r3 (mcu0_l2t1_secc_err_r2 ), | |
10474 | .mcu_l2t1_mecc_err_r3 (mcu0_l2t1_mecc_err_r2 ), | |
10475 | .mcu_l2t1_scb_secc_err (mcu0_l2t1_scb_secc_err ), | |
10476 | .mcu_l2t1_scb_mecc_err (mcu0_l2t1_scb_mecc_err ), | |
10477 | .mcu_l2t1_qword_id_r0 (mcu0_l2t1_qword_id_r0[ 1 : 0 ] ), | |
10478 | .mcu_l2b_data_r3 (mcu0_l2b01_data_r2[ 127 : 0 ] ), | |
10479 | .mcu_l2b_ecc_r3 (mcu0_l2b01_ecc_r2[ 27 : 0 ] ), | |
10480 | .l2b0_mcu_data_mecc_r5 (l2b0_mcu0_data_mecc_r5 ), | |
10481 | .l2b0_mcu_wr_data_r5 (l2b0_mcu0_wr_data_r5[ 63 : 0 ] ), | |
10482 | .l2b0_mcu_data_vld_r5 (l2b0_mcu0_data_vld_r5 ), | |
10483 | .l2b1_mcu_data_mecc_r5 (l2b1_mcu0_data_mecc_r5 ), | |
10484 | .l2b1_mcu_wr_data_r5 (l2b1_mcu0_wr_data_r5[ 63 : 0 ] ), | |
10485 | .l2b1_mcu_data_vld_r5 (l2b1_mcu0_data_vld_r5 ), | |
10486 | .mcu_pt_sync_out (mcu0_pt_sync_out ), | |
10487 | .mcu_pt_sync_in0 (mcu1_pt_sync_out ), | |
10488 | .mcu_pt_sync_in1 (mcu2_pt_sync_out ), | |
10489 | .mcu_pt_sync_in2 (mcu3_pt_sync_out ), | |
10490 | .mcu_ncu_data (mcu0_ncu_data[ 3 : 0 ] ), | |
10491 | .mcu_ncu_stall (mcu0_ncu_stall ), | |
10492 | .mcu_ncu_vld (mcu0_ncu_vld ), | |
10493 | .ncu_mcu_data (ncu_mcu0_data[ 3 : 0 ] ), | |
10494 | .ncu_mcu_stall (ncu_mcu0_stall ), | |
10495 | .ncu_mcu_vld (ncu_mcu0_vld ), | |
10496 | .mcu_ncu_ecc (mcu0_ncu_ecc ), | |
10497 | .mcu_ncu_fbr (mcu0_ncu_fbr ), | |
10498 | .ncu_mcu_ecci (ncu_mcu0_ecci ), | |
10499 | .ncu_mcu_fbui (ncu_mcu0_fbui ), | |
10500 | .ncu_mcu_fbri (ncu_mcu0_fbri ), | |
10501 | .mcu_fsr0_data (mcu0_fsr0_data[ 119 : 0 ] ), | |
10502 | .mcu_fsr1_data (mcu0_fsr1_data[ 119 : 0 ] ), | |
10503 | .mcu_fsr0_cfgpll_enpll (mcu0_fsr0_cfgpll_enpll ), | |
10504 | .mcu_fsr1_cfgpll_enpll (mcu0_fsr1_cfgpll_enpll ), | |
10505 | .mcu_fsr01_cfgpll_lb (mcu0_fsr01_cfgpll_lb[ 1 : 0 ] ), | |
10506 | .mcu_fsr01_cfgpll_mpy (mcu0_fsr01_cfgpll_mpy[ 3 : 0 ] ), | |
10507 | .mcu_fsr0_cfgrx_enrx (mcu0_fsr0_cfgrx_enrx ), | |
10508 | .mcu_fsr1_cfgrx_enrx (mcu0_fsr1_cfgrx_enrx ), | |
10509 | .mcu_fsr0_cfgrx_align (mcu0_fsr0_cfgrx_align ), | |
10510 | .mcu_fsr1_cfgrx_align (mcu0_fsr1_cfgrx_align ), | |
10511 | .mcu_fsr0_cfgrx_invpair (mcu0_fsr0_cfgrx_invpair[ 13 : 0 ]), | |
10512 | .mcu_fsr1_cfgrx_invpair (mcu0_fsr1_cfgrx_invpair[ 13 : 0 ]), | |
10513 | .mcu_fsr01_cfgrx_eq (mcu0_fsr01_cfgrx_eq[ 3 : 0 ] ), | |
10514 | .mcu_fsr01_cfgrx_cdr (mcu0_fsr01_cfgrx_cdr[ 2 : 0 ] ), | |
10515 | .mcu_fsr01_cfgrx_term (mcu0_fsr01_cfgrx_term[ 2 : 0 ] ), | |
10516 | .mcu_fsr0_cfgtx_entx (mcu0_fsr0_cfgtx_entx ), | |
10517 | .mcu_fsr1_cfgtx_entx (mcu0_fsr1_cfgtx_entx ), | |
10518 | .mcu_fsr0_cfgtx_enidl (mcu0_fsr0_cfgtx_enidl ), | |
10519 | .mcu_fsr1_cfgtx_enidl (mcu0_fsr1_cfgtx_enidl ), | |
10520 | .mcu_fsr0_cfgtx_invpair (mcu0_fsr0_cfgtx_invpair[ 9 : 0 ]), | |
10521 | .mcu_fsr1_cfgtx_invpair (mcu0_fsr1_cfgtx_invpair[ 9 : 0 ]), | |
10522 | .mcu_fsr01_cfgtx_enftp (mcu0_fsr01_cfgtx_enftp ), | |
10523 | .mcu_fsr01_cfgtx_de (mcu0_fsr01_cfgtx_de[ 3 : 0 ] ), | |
10524 | .mcu_fsr01_cfgtx_swing (mcu0_fsr01_cfgtx_swing[ 2 : 0 ] ), | |
10525 | .mcu_fsr01_cfgtx_cm (mcu0_fsr01_cfgtx_cm ), | |
10526 | .mcu_fsr01_cfgrtx_rate (mcu0_fsr01_cfgrtx_rate[ 1 : 0 ] ), | |
10527 | .mcu_fsr0_cfgrx_entest (mcu0_fsr0_cfgrx_entest ), | |
10528 | .mcu_fsr1_cfgrx_entest (mcu0_fsr1_cfgrx_entest ), | |
10529 | .mcu_fsr0_cfgtx_entest (mcu0_fsr0_cfgtx_entest ), | |
10530 | .mcu_fsr1_cfgtx_entest (mcu0_fsr1_cfgtx_entest ), | |
10531 | .mcu_fsr0_cfgtx_bstx (mcu0_fsr0_cfgtx_bstx[ 9 : 0 ] ), | |
10532 | .mcu_fsr1_cfgtx_bstx (mcu0_fsr1_cfgtx_bstx[ 9 : 0 ] ), | |
10533 | .fsr0_mcu_data (fsr0_mcu0_data[ 167 : 0 ] ), | |
10534 | .fsr1_mcu_data (fsr1_mcu0_data[ 167 : 0 ] ), | |
10535 | .fsr0_mcu_rxbclk (fsr0_mcu0_rxbclk[ 13 : 0 ] ), | |
10536 | .fsr1_mcu_rxbclk (fsr1_mcu0_rxbclk[ 13 : 0 ] ), | |
10537 | .fsr0_mcu_stspll_lock (fsr0_mcu0_stspll_lock[ 2 : 0 ] ), | |
10538 | .fsr1_mcu_stspll_lock (fsr1_mcu0_stspll_lock[ 2 : 0 ] ), | |
10539 | .mcu_fsr0_testcfg (mcu0_fsr0_testcfg[ 11 : 0 ] ), | |
10540 | .mcu_fsr1_testcfg (mcu0_fsr1_testcfg[ 11 : 0 ] ), | |
10541 | .fsr0_mcu_stsrx_sync ({fsr0_mcu0_stsrx_sync[ 8 ], fsr0_mcu0_stsrx_sync[ 9 ], | |
10542 | fsr0_mcu0_stsrx_sync[ 13 : 10 ],fsr0_mcu0_stsrx_sync[ 7 : 0 ]}), | |
10543 | .fsr1_mcu_stsrx_sync ({fsr1_mcu0_stsrx_sync[ 8 ], fsr1_mcu0_stsrx_sync[ 9 ], | |
10544 | fsr1_mcu0_stsrx_sync[ 13 : 10 ],fsr1_mcu0_stsrx_sync[ 7 : 0 ]}), | |
10545 | .fsr0_mcu_stsrx_losdtct ({fsr0_mcu0_stsrx_losdtct[ 8 ], fsr0_mcu0_stsrx_losdtct[ 9 ], | |
10546 | fsr0_mcu0_stsrx_losdtct[ 13 : 10 ],fsr0_mcu0_stsrx_losdtct[ 7 : 0 ]}), | |
10547 | .fsr1_mcu_stsrx_losdtct ({fsr1_mcu0_stsrx_losdtct[ 8 ], fsr1_mcu0_stsrx_losdtct[ 9 ], | |
10548 | fsr1_mcu0_stsrx_losdtct[ 13 : 10 ],fsr1_mcu0_stsrx_losdtct[ 7 : 0 ]}), | |
10549 | .fsr0_mcu_stsrx_testfail (fsr0_mcu0_stsrx_testfail[ 13 : 0 ]), | |
10550 | .fsr1_mcu_stsrx_testfail (fsr1_mcu0_stsrx_testfail[ 13 : 0 ]), | |
10551 | .fsr0_mcu_stsrx_bsrxp (fsr0_mcu0_stsrx_bsrxp[ 13 : 0 ] ), | |
10552 | .fsr1_mcu_stsrx_bsrxp (fsr1_mcu0_stsrx_bsrxp[ 13 : 0 ] ), | |
10553 | .fsr0_mcu_stsrx_bsrxn (fsr0_mcu0_stsrx_bsrxn[ 13 : 0 ] ), | |
10554 | .fsr1_mcu_stsrx_bsrxn (fsr1_mcu0_stsrx_bsrxn[ 13 : 0 ] ), | |
10555 | .fsr0_mcu_ststx_testfail (fsr0_mcu0_ststx_testfail[ 9 : 0 ]), | |
10556 | .fsr1_mcu_ststx_testfail (fsr1_mcu0_ststx_testfail[ 9 : 0 ]), | |
10557 | .mcu_id ({1'b0,1'b0} ), | |
10558 | .tcu_mcu_mbist_start (tcu_mcu0_mbist_start_t1lff ), | |
10559 | .mcu_tcu_mbist_done (mcu0_tcu_mbist_done ), | |
10560 | .mcu_tcu_mbist_fail (mcu0_tcu_mbist_fail ), | |
10561 | .tcu_mcu_mbist_scan_in (tcu_mcu0_mbist_scan_in ), | |
10562 | .mcu_tcu_mbist_scan_out (mcu0_tcu_mbist_scan_out ), | |
10563 | .mcu_sbs_scan_in (tcu_sbs_scan_in ), | |
10564 | .mcu_sbs_scan_out (mcu0_sbs_scan_out ), | |
10565 | .scan_in (ccx_scan_out[ 0 ] ), | |
10566 | .scan_out (mcu0_scan_out ), | |
10567 | .ncu_mcu_pm(ncu_mcu_pm), | |
10568 | .ncu_mcu_ba01(ncu_mcu_ba01), | |
10569 | .ncu_mcu_ba23(ncu_mcu_ba23), | |
10570 | .ncu_mcu_ba45(ncu_mcu_ba45), | |
10571 | .ncu_mcu_ba67(ncu_mcu_ba67), | |
10572 | .tcu_mbist_bisi_en(tcu_mbist_bisi_en), | |
10573 | .tcu_mbist_user_mode(tcu_mbist_user_mode), | |
10574 | .tcu_sbs_scan_en(tcu_sbs_scan_en), | |
10575 | .tcu_sbs_aclk(tcu_sbs_aclk), | |
10576 | .tcu_sbs_bclk(tcu_sbs_bclk), | |
10577 | .tcu_sbs_clk(tcu_sbs_clk), | |
10578 | .tcu_sbs_uclk(tcu_sbs_uclk), | |
10579 | .rst_mcu_selfrsh(rst_mcu_selfrsh), | |
10580 | .rst_wmr_protect(rst_wmr_protect), | |
10581 | .tcu_aclk(tcu_aclk), | |
10582 | .tcu_bclk(tcu_bclk), | |
10583 | .tcu_pce_ov(tcu_pce_ov), | |
10584 | .tcu_dectest(tcu_dectest), | |
10585 | .tcu_muxtest(tcu_muxtest), | |
10586 | .tcu_mcu_testmode(tcu_mcu_testmode), | |
10587 | .tcu_scan_en(tcu_scan_en), | |
10588 | .tcu_se_scancollar_in(tcu_se_scancollar_in), | |
10589 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit), | |
10590 | .tcu_array_bypass(tcu_array_bypass), | |
10591 | .tcu_atpg_mode(tcu_atpg_mode), | |
10592 | .tcu_div_bypass(tcu_div_bypass), | |
10593 | .ccu_serdes_dtm(ccu_serdes_dtm) | |
10594 | ); | |
10595 | `endif // OPENSPARC_CMP | |
10596 | //________________________________________________________________ | |
10597 | ||
10598 | // leave this instance out of cmp model | |
10599 | `ifdef OPENSPARC_CMP | |
10600 | `else | |
10601 | mcu mcu1( | |
10602 | .gclk ( cmp_gclk_c4_mcu1 ), // cmp_gclk_c0_r[3] ) , | |
10603 | .tcu_mcu_dr_clk_stop ( gl_mcu1_dr_clk_stop ), // staged clk_stop | |
10604 | .tcu_mcu_clk_stop ( gl_mcu1_clk_stop ), // staged clk_stop | |
10605 | .tcu_mcu_io_clk_stop ( gl_mcu1_io_clk_stop ), // staged clk_stop | |
10606 | .ccu_io_out ( gl_io_out_c3t ), // staged div phase | |
10607 | .ccu_dr_sync_en (gl_dr_sync_en_c3t), | |
10608 | .ccu_io_cmp_sync_en ( gl_io_cmp_sync_en_c3t ), | |
10609 | .ccu_cmp_io_sync_en ( gl_cmp_io_sync_en_c3t ), | |
10610 | .dr_gclk ( dr_gclk_c4_mcu1 ), // dr_gclk_c0_r[3] ) , | |
10611 | .tcu_mcu_fbd_clk_stop (tcu_mcu1_fbd_clk_stop ), | |
10612 | .mcu_dbg1_rd_req_in_0 (mcu1_dbg1_rd_req_in_0[ 3 : 0 ] ), | |
10613 | .mcu_dbg1_rd_req_in_1 (mcu1_dbg1_rd_req_in_1[ 3 : 0 ] ), | |
10614 | .mcu_dbg1_rd_req_out (mcu1_dbg1_rd_req_out[ 4 : 0 ] ), | |
10615 | .mcu_dbg1_wr_req_in_0 (mcu1_dbg1_wr_req_in_0 ), | |
10616 | .mcu_dbg1_wr_req_in_1 (mcu1_dbg1_wr_req_in_1 ), | |
10617 | .mcu_dbg1_wr_req_out (mcu1_dbg1_wr_req_out[ 1 : 0 ] ), | |
10618 | .mcu_dbg1_mecc_err (mcu1_dbg1_mecc_err ), | |
10619 | .mcu_dbg1_secc_err (mcu1_dbg1_secc_err ), | |
10620 | .mcu_dbg1_fbd_err (mcu1_dbg1_fbd_err ), | |
10621 | .mcu_dbg1_err_mode (mcu1_dbg1_err_mode ), | |
10622 | .mcu_dbg1_err_event (mcu1_dbg1_err_event ), | |
10623 | .mcu_dbg1_crc21 (mcu1_dbg1_crc21 ), | |
10624 | .l2t0_mcu_rd_req (l2t2_mcu1_rd_req ), | |
10625 | .l2t0_mcu_wr_req (l2t2_mcu1_wr_req ), | |
10626 | .l2t0_mcu_rd_dummy_req (l2t2_mcu1_rd_dummy_req ), | |
10627 | .l2t0_mcu_rd_req_id (l2t2_mcu1_rd_req_id[ 2 : 0 ] ), | |
10628 | .l2t0_mcu_addr_39to7 (l2t2_mcu1_addr[ 39 : 7 ] ), | |
10629 | .l2t0_mcu_addr_5 (l2t2_mcu1_addr_5 ), | |
10630 | .mcu_l2t0_rd_ack (mcu1_l2t2_rd_ack ), | |
10631 | .mcu_l2t0_wr_ack (mcu1_l2t2_wr_ack ), | |
10632 | .mcu_l2t0_data_vld_r0 (mcu1_l2t2_data_vld_r0 ), | |
10633 | .mcu_l2t0_rd_req_id_r0 (mcu1_l2t2_rd_req_id_r0[ 2 : 0 ] ), | |
10634 | .mcu_l2t0_secc_err_r3 (mcu1_l2t2_secc_err_r2 ), | |
10635 | .mcu_l2t0_mecc_err_r3 (mcu1_l2t2_mecc_err_r2 ), | |
10636 | .mcu_l2t0_scb_secc_err (mcu1_l2t2_scb_secc_err ), | |
10637 | .mcu_l2t0_scb_mecc_err (mcu1_l2t2_scb_mecc_err ), | |
10638 | .mcu_l2t0_qword_id_r0 (mcu1_l2t2_qword_id_r0[ 1 : 0 ] ), | |
10639 | .l2t1_mcu_rd_req (l2t3_mcu1_rd_req_t2lff ), | |
10640 | .l2t1_mcu_wr_req (l2t3_mcu1_wr_req_t2lff ), | |
10641 | .l2t1_mcu_rd_dummy_req (l2t3_mcu1_rd_dummy_req_t2lff ), | |
10642 | .l2t1_mcu_rd_req_id (l2t3_mcu1_rd_req_id_t2lff[ 2 : 0 ] ), | |
10643 | .l2t1_mcu_addr_39to7 (l2t3_mcu1_addr_t2lff[ 39 : 7 ] ), | |
10644 | .l2t1_mcu_addr_5 (l2t3_mcu1_addr_5_t2lff ), | |
10645 | .mcu_l2t1_rd_ack (mcu1_l2t3_rd_ack ), | |
10646 | .mcu_l2t1_wr_ack (mcu1_l2t3_wr_ack ), | |
10647 | .mcu_l2t1_data_vld_r0 (mcu1_l2t3_data_vld_r0 ), | |
10648 | .mcu_l2t1_rd_req_id_r0 (mcu1_l2t3_rd_req_id_r0[ 2 : 0 ] ), | |
10649 | .mcu_l2t1_secc_err_r3 (mcu1_l2t3_secc_err_r2 ), | |
10650 | .mcu_l2t1_mecc_err_r3 (mcu1_l2t3_mecc_err_r2 ), | |
10651 | .mcu_l2t1_scb_secc_err (mcu1_l2t3_scb_secc_err ), | |
10652 | .mcu_l2t1_scb_mecc_err (mcu1_l2t3_scb_mecc_err ), | |
10653 | .mcu_l2t1_qword_id_r0 (mcu1_l2t3_qword_id_r0[ 1 : 0 ] ), | |
10654 | .mcu_l2b_data_r3 (mcu1_l2b23_data_r2[ 127 : 0 ] ), | |
10655 | .mcu_l2b_ecc_r3 (mcu1_l2b23_ecc_r2[ 27 : 0 ] ), | |
10656 | .l2b0_mcu_data_mecc_r5 (l2b2_mcu1_data_mecc_r5 ), | |
10657 | .l2b0_mcu_wr_data_r5 (l2b2_mcu1_wr_data_r5[ 63 : 0 ] ), | |
10658 | .l2b0_mcu_data_vld_r5 (l2b2_mcu1_data_vld_r5 ), | |
10659 | .l2b1_mcu_data_mecc_r5 (l2b3_mcu1_data_mecc_r5 ), | |
10660 | .l2b1_mcu_wr_data_r5 (l2b3_mcu1_wr_data_r5[ 63 : 0 ] ), | |
10661 | .l2b1_mcu_data_vld_r5 (l2b3_mcu1_data_vld_r5 ), | |
10662 | .mcu_pt_sync_out (mcu1_pt_sync_out ), | |
10663 | .mcu_pt_sync_in0 (mcu2_pt_sync_out ), | |
10664 | .mcu_pt_sync_in1 (mcu3_pt_sync_out ), | |
10665 | .mcu_pt_sync_in2 (mcu0_pt_sync_out ), | |
10666 | .mcu_ncu_data (mcu1_ncu_data[ 3 : 0 ] ), | |
10667 | .mcu_ncu_stall (mcu1_ncu_stall ), | |
10668 | .mcu_ncu_vld (mcu1_ncu_vld ), | |
10669 | .ncu_mcu_data (ncu_mcu1_data[ 3 : 0 ] ), | |
10670 | .ncu_mcu_stall (ncu_mcu1_stall ), | |
10671 | .ncu_mcu_vld (ncu_mcu1_vld ), | |
10672 | .mcu_ncu_ecc (mcu1_ncu_ecc ), | |
10673 | .mcu_ncu_fbr (mcu1_ncu_fbr ), | |
10674 | .ncu_mcu_ecci (ncu_mcu1_ecci ), | |
10675 | .ncu_mcu_fbui (ncu_mcu1_fbui ), | |
10676 | .ncu_mcu_fbri (ncu_mcu1_fbri ), | |
10677 | .mcu_fsr0_data (mcu1_fsr2_data[ 119 : 0 ] ), | |
10678 | .mcu_fsr1_data (mcu1_fsr3_data[ 119 : 0 ] ), | |
10679 | .mcu_fsr0_cfgpll_enpll (mcu1_fsr2_cfgpll_enpll ), | |
10680 | .mcu_fsr1_cfgpll_enpll (mcu1_fsr3_cfgpll_enpll ), | |
10681 | .mcu_fsr01_cfgpll_lb (mcu1_fsr23_cfgpll_lb[ 1 : 0 ] ), | |
10682 | .mcu_fsr01_cfgpll_mpy (mcu1_fsr23_cfgpll_mpy[ 3 : 0 ] ), | |
10683 | .mcu_fsr0_cfgrx_enrx (mcu1_fsr2_cfgrx_enrx ), | |
10684 | .mcu_fsr1_cfgrx_enrx (mcu1_fsr3_cfgrx_enrx ), | |
10685 | .mcu_fsr0_cfgrx_align (mcu1_fsr2_cfgrx_align ), | |
10686 | .mcu_fsr1_cfgrx_align (mcu1_fsr3_cfgrx_align ), | |
10687 | .mcu_fsr0_cfgrx_invpair (mcu1_fsr2_cfgrx_invpair[ 13 : 0 ]), | |
10688 | .mcu_fsr1_cfgrx_invpair (mcu1_fsr3_cfgrx_invpair[ 13 : 0 ]), | |
10689 | .mcu_fsr01_cfgrx_eq (mcu1_fsr23_cfgrx_eq[ 3 : 0 ] ), | |
10690 | .mcu_fsr01_cfgrx_cdr (mcu1_fsr23_cfgrx_cdr[ 2 : 0 ] ), | |
10691 | .mcu_fsr01_cfgrx_term (mcu1_fsr23_cfgrx_term[ 2 : 0 ] ), | |
10692 | .mcu_fsr0_cfgtx_entx (mcu1_fsr2_cfgtx_entx ), | |
10693 | .mcu_fsr1_cfgtx_entx (mcu1_fsr3_cfgtx_entx ), | |
10694 | .mcu_fsr0_cfgtx_enidl (mcu1_fsr2_cfgtx_enidl ), | |
10695 | .mcu_fsr1_cfgtx_enidl (mcu1_fsr3_cfgtx_enidl ), | |
10696 | .mcu_fsr0_cfgtx_invpair (mcu1_fsr2_cfgtx_invpair[ 9 : 0 ]), | |
10697 | .mcu_fsr1_cfgtx_invpair (mcu1_fsr3_cfgtx_invpair[ 9 : 0 ]), | |
10698 | .mcu_fsr01_cfgtx_enftp (mcu1_fsr23_cfgtx_enftp ), | |
10699 | .mcu_fsr01_cfgtx_de (mcu1_fsr23_cfgtx_de[ 3 : 0 ] ), | |
10700 | .mcu_fsr01_cfgtx_swing (mcu1_fsr23_cfgtx_swing[ 2 : 0 ] ), | |
10701 | .mcu_fsr01_cfgtx_cm (mcu1_fsr23_cfgtx_cm ), | |
10702 | .mcu_fsr01_cfgrtx_rate (mcu1_fsr23_cfgrtx_rate[ 1 : 0 ] ), | |
10703 | .mcu_fsr0_cfgrx_entest (mcu1_fsr2_cfgrx_entest ), | |
10704 | .mcu_fsr1_cfgrx_entest (mcu1_fsr3_cfgrx_entest ), | |
10705 | .mcu_fsr0_cfgtx_entest (mcu1_fsr2_cfgtx_entest ), | |
10706 | .mcu_fsr1_cfgtx_entest (mcu1_fsr3_cfgtx_entest ), | |
10707 | .mcu_fsr0_cfgtx_bstx (mcu1_fsr2_cfgtx_bstx[ 9 : 0 ] ), | |
10708 | .mcu_fsr1_cfgtx_bstx (mcu1_fsr3_cfgtx_bstx[ 9 : 0 ] ), | |
10709 | .fsr0_mcu_data (fsr2_mcu1_data[ 167 : 0 ] ), | |
10710 | .fsr1_mcu_data (fsr3_mcu1_data[ 167 : 0 ] ), | |
10711 | .fsr0_mcu_rxbclk (fsr2_mcu1_rxbclk[ 13 : 0 ] ), | |
10712 | .fsr1_mcu_rxbclk (fsr3_mcu1_rxbclk[ 13 : 0 ] ), | |
10713 | .fsr0_mcu_stspll_lock (fsr2_mcu1_stspll_lock[ 2 : 0 ] ), | |
10714 | .fsr1_mcu_stspll_lock (fsr3_mcu1_stspll_lock[ 2 : 0 ] ), | |
10715 | .mcu_fsr0_testcfg (mcu1_fsr2_testcfg[ 11 : 0 ] ), | |
10716 | .mcu_fsr1_testcfg (mcu1_fsr3_testcfg[ 11 : 0 ] ), | |
10717 | .fsr0_mcu_stsrx_sync ({fsr2_mcu1_stsrx_sync[ 8 ], fsr2_mcu1_stsrx_sync[ 9 ], | |
10718 | fsr2_mcu1_stsrx_sync[ 13 : 10 ],fsr2_mcu1_stsrx_sync[ 7 : 0 ]}), | |
10719 | .fsr1_mcu_stsrx_sync ({fsr3_mcu1_stsrx_sync[ 8 ], fsr3_mcu1_stsrx_sync[ 9 ], | |
10720 | fsr3_mcu1_stsrx_sync[ 13 : 10 ],fsr3_mcu1_stsrx_sync[ 7 : 0 ]}), | |
10721 | .fsr0_mcu_stsrx_losdtct ({fsr2_mcu1_stsrx_losdtct[ 8 ], fsr2_mcu1_stsrx_losdtct[ 9 ], | |
10722 | fsr2_mcu1_stsrx_losdtct[ 13 : 10 ],fsr2_mcu1_stsrx_losdtct[ 7 : 0 ]}), | |
10723 | .fsr1_mcu_stsrx_losdtct ({fsr3_mcu1_stsrx_losdtct[ 8 ], fsr3_mcu1_stsrx_losdtct[ 9 ], | |
10724 | fsr3_mcu1_stsrx_losdtct[ 13 : 10 ],fsr3_mcu1_stsrx_losdtct[ 7 : 0 ]}), | |
10725 | .fsr0_mcu_stsrx_testfail (fsr2_mcu1_stsrx_testfail[ 13 : 0 ]), | |
10726 | .fsr1_mcu_stsrx_testfail (fsr3_mcu1_stsrx_testfail[ 13 : 0 ]), | |
10727 | .fsr0_mcu_stsrx_bsrxp (fsr2_mcu1_stsrx_bsrxp[ 13 : 0 ] ), | |
10728 | .fsr1_mcu_stsrx_bsrxp (fsr3_mcu1_stsrx_bsrxp[ 13 : 0 ] ), | |
10729 | .fsr0_mcu_stsrx_bsrxn (fsr2_mcu1_stsrx_bsrxn[ 13 : 0 ] ), | |
10730 | .fsr1_mcu_stsrx_bsrxn (fsr3_mcu1_stsrx_bsrxn[ 13 : 0 ] ), | |
10731 | .fsr0_mcu_ststx_testfail (fsr2_mcu1_ststx_testfail[ 9 : 0 ]), | |
10732 | .fsr1_mcu_ststx_testfail (fsr3_mcu1_ststx_testfail[ 9 : 0 ]), | |
10733 | .mcu_id ({1'b0,1'b1} ), | |
10734 | .tcu_mcu_mbist_start (tcu_mcu1_mbist_start_t1lff ), | |
10735 | .mcu_tcu_mbist_done (mcu1_tcu_mbist_done ), | |
10736 | .mcu_tcu_mbist_fail (mcu1_tcu_mbist_fail ), | |
10737 | .tcu_mcu_mbist_scan_in (tcu_mcu1_mbist_scan_in ), | |
10738 | .mcu_tcu_mbist_scan_out (mcu1_tcu_mbist_scan_out ), | |
10739 | .mcu_sbs_scan_in (mcu0_sbs_scan_out ), | |
10740 | .mcu_sbs_scan_out (mcu1_sbs_scan_out ), | |
10741 | .scan_in (tcu_socc_scan_out ), | |
10742 | .scan_out (mcu1_scan_out ), | |
10743 | .ncu_mcu_pm(ncu_mcu_pm), | |
10744 | .ncu_mcu_ba01(ncu_mcu_ba01), | |
10745 | .ncu_mcu_ba23(ncu_mcu_ba23), | |
10746 | .ncu_mcu_ba45(ncu_mcu_ba45), | |
10747 | .ncu_mcu_ba67(ncu_mcu_ba67), | |
10748 | .tcu_mbist_bisi_en(tcu_mbist_bisi_en), | |
10749 | .tcu_mbist_user_mode(tcu_mbist_user_mode), | |
10750 | .tcu_sbs_scan_en(tcu_sbs_scan_en), | |
10751 | .tcu_sbs_aclk(tcu_sbs_aclk), | |
10752 | .tcu_sbs_bclk(tcu_sbs_bclk), | |
10753 | .tcu_sbs_clk(tcu_sbs_clk), | |
10754 | .tcu_sbs_uclk(tcu_sbs_uclk), | |
10755 | .rst_mcu_selfrsh(rst_mcu_selfrsh), | |
10756 | .rst_wmr_protect(rst_wmr_protect), | |
10757 | .tcu_aclk(tcu_aclk), | |
10758 | .tcu_bclk(tcu_bclk), | |
10759 | .tcu_pce_ov(tcu_pce_ov), | |
10760 | .tcu_dectest(tcu_dectest), | |
10761 | .tcu_muxtest(tcu_muxtest), | |
10762 | .tcu_mcu_testmode(tcu_mcu_testmode), | |
10763 | .tcu_scan_en(tcu_scan_en), | |
10764 | .tcu_se_scancollar_in(tcu_se_scancollar_in), | |
10765 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit), | |
10766 | .tcu_array_bypass(tcu_array_bypass), | |
10767 | .tcu_atpg_mode(tcu_atpg_mode), | |
10768 | .tcu_div_bypass(tcu_div_bypass), | |
10769 | .ccu_serdes_dtm(ccu_serdes_dtm) | |
10770 | ); | |
10771 | `endif // OPENSPARC_CMP | |
10772 | //________________________________________________________________ | |
10773 | ||
10774 | // leave this instance out of cmp model | |
10775 | `ifdef OPENSPARC_CMP | |
10776 | `else | |
10777 | mcu mcu2( | |
10778 | .gclk ( cmp_gclk_c0_mcu2 ), // cmp_gclk_c3_r[2] ) , | |
10779 | .tcu_mcu_dr_clk_stop ( gl_mcu2_dr_clk_stop ), // staged clk_stop | |
10780 | .tcu_mcu_io_clk_stop ( gl_mcu2_io_clk_stop ), // staged clk_stop | |
10781 | .tcu_mcu_clk_stop ( gl_mcu2_clk_stop ), // staged clk_stop | |
10782 | .ccu_io_out ( gl_io_out_c1m ), // staged div phase | |
10783 | .dr_gclk ( dr_gclk_c0_mcu2 ), // dr_gclk_c3_r[2] ) , | |
10784 | .ccu_dr_sync_en (gl_dr_sync_en_c1m), | |
10785 | .ccu_io_cmp_sync_en ( gl_io_cmp_sync_en_c1m ), | |
10786 | .ccu_cmp_io_sync_en ( gl_cmp_io_sync_en_c1m ), | |
10787 | .tcu_mcu_fbd_clk_stop (tcu_mcu2_fbd_clk_stop ), | |
10788 | .mcu_dbg1_rd_req_in_0 (mcu2_dbg1_rd_req_in_0[ 3 : 0 ] ), | |
10789 | .mcu_dbg1_rd_req_in_1 (mcu2_dbg1_rd_req_in_1[ 3 : 0 ] ), | |
10790 | .mcu_dbg1_rd_req_out (mcu2_dbg1_rd_req_out[ 4 : 0 ] ), | |
10791 | .mcu_dbg1_wr_req_in_0 (mcu2_dbg1_wr_req_in_0 ), | |
10792 | .mcu_dbg1_wr_req_in_1 (mcu2_dbg1_wr_req_in_1 ), | |
10793 | .mcu_dbg1_wr_req_out (mcu2_dbg1_wr_req_out[ 1 : 0 ] ), | |
10794 | .mcu_dbg1_mecc_err (mcu2_dbg1_mecc_err ), | |
10795 | .mcu_dbg1_secc_err (mcu2_dbg1_secc_err ), | |
10796 | .mcu_dbg1_fbd_err (mcu2_dbg1_fbd_err ), | |
10797 | .mcu_dbg1_err_mode (mcu2_dbg1_err_mode ), | |
10798 | .mcu_dbg1_err_event (mcu2_dbg1_err_event ), | |
10799 | .mcu_dbg1_crc21 (mcu2_dbg1_crc21 ), | |
10800 | .l2t0_mcu_rd_req (l2t4_mcu2_rd_req ), | |
10801 | .l2t0_mcu_wr_req (l2t4_mcu2_wr_req ), | |
10802 | .l2t0_mcu_rd_dummy_req (l2t4_mcu2_rd_dummy_req ), | |
10803 | .l2t0_mcu_rd_req_id (l2t4_mcu2_rd_req_id[ 2 : 0 ] ), | |
10804 | .l2t0_mcu_addr_39to7 (l2t4_mcu2_addr[ 39 : 7 ] ), | |
10805 | .l2t0_mcu_addr_5 (l2t4_mcu2_addr_5 ), | |
10806 | .mcu_l2t0_rd_ack (mcu2_l2t4_rd_ack ), | |
10807 | .mcu_l2t0_wr_ack (mcu2_l2t4_wr_ack ), | |
10808 | .mcu_l2t0_data_vld_r0 (mcu2_l2t4_data_vld_r0 ), | |
10809 | .mcu_l2t0_rd_req_id_r0 (mcu2_l2t4_rd_req_id_r0[ 2 : 0 ] ), | |
10810 | .mcu_l2t0_secc_err_r3 (mcu2_l2t4_secc_err_r2 ), | |
10811 | .mcu_l2t0_mecc_err_r3 (mcu2_l2t4_mecc_err_r2 ), | |
10812 | .mcu_l2t0_scb_secc_err (mcu2_l2t4_scb_secc_err ), | |
10813 | .mcu_l2t0_scb_mecc_err (mcu2_l2t4_scb_mecc_err ), | |
10814 | .mcu_l2t0_qword_id_r0 (mcu2_l2t4_qword_id_r0[ 1 : 0 ] ), | |
10815 | .l2t1_mcu_rd_req (l2t5_mcu2_rd_req_t4lff ), | |
10816 | .l2t1_mcu_wr_req (l2t5_mcu2_wr_req_t4lff ), | |
10817 | .l2t1_mcu_rd_dummy_req (l2t5_mcu2_rd_dummy_req_t4lff ), | |
10818 | .l2t1_mcu_rd_req_id (l2t5_mcu2_rd_req_id_t4lff[ 2 : 0 ] ), | |
10819 | .l2t1_mcu_addr_39to7 (l2t5_mcu2_addr_t4lff[ 39 : 7 ] ), | |
10820 | .l2t1_mcu_addr_5 (l2t5_mcu2_addr_5_t4lff ), | |
10821 | .mcu_l2t1_rd_ack (mcu2_l2t5_rd_ack ), | |
10822 | .mcu_l2t1_wr_ack (mcu2_l2t5_wr_ack ), | |
10823 | .mcu_l2t1_data_vld_r0 (mcu2_l2t5_data_vld_r0 ), | |
10824 | .mcu_l2t1_rd_req_id_r0 (mcu2_l2t5_rd_req_id_r0[ 2 : 0 ] ), | |
10825 | .mcu_l2t1_secc_err_r3 (mcu2_l2t5_secc_err_r2 ), | |
10826 | .mcu_l2t1_mecc_err_r3 (mcu2_l2t5_mecc_err_r2 ), | |
10827 | .mcu_l2t1_scb_secc_err (mcu2_l2t5_scb_secc_err ), | |
10828 | .mcu_l2t1_scb_mecc_err (mcu2_l2t5_scb_mecc_err ), | |
10829 | .mcu_l2t1_qword_id_r0 (mcu2_l2t5_qword_id_r0[ 1 : 0 ] ), | |
10830 | .mcu_l2b_data_r3 (mcu2_l2b45_data_r2[ 127 : 0 ] ), | |
10831 | .mcu_l2b_ecc_r3 (mcu2_l2b45_ecc_r2[ 27 : 0 ] ), | |
10832 | .l2b0_mcu_data_mecc_r5 (l2b4_mcu2_data_mecc_r5 ), | |
10833 | .l2b0_mcu_wr_data_r5 (l2b4_mcu2_wr_data_r5[ 63 : 0 ] ), | |
10834 | .l2b0_mcu_data_vld_r5 (l2b4_mcu2_data_vld_r5 ), | |
10835 | .l2b1_mcu_data_mecc_r5 (l2b5_mcu2_data_mecc_r5 ), | |
10836 | .l2b1_mcu_wr_data_r5 (l2b5_mcu2_wr_data_r5[ 63 : 0 ] ), | |
10837 | .l2b1_mcu_data_vld_r5 (l2b5_mcu2_data_vld_r5 ), | |
10838 | .mcu_pt_sync_out (mcu2_pt_sync_out ), | |
10839 | .mcu_pt_sync_in0 (mcu3_pt_sync_out ), | |
10840 | .mcu_pt_sync_in1 (mcu0_pt_sync_out ), | |
10841 | .mcu_pt_sync_in2 (mcu1_pt_sync_out ), | |
10842 | .mcu_ncu_data (mcu2_ncu_data[ 3 : 0 ] ), | |
10843 | .mcu_ncu_stall (mcu2_ncu_stall ), | |
10844 | .mcu_ncu_vld (mcu2_ncu_vld ), | |
10845 | .ncu_mcu_data (ncu_mcu2_data[ 3 : 0 ] ), | |
10846 | .ncu_mcu_stall (ncu_mcu2_stall ), | |
10847 | .ncu_mcu_vld (ncu_mcu2_vld ), | |
10848 | .mcu_ncu_ecc (mcu2_ncu_ecc ), | |
10849 | .mcu_ncu_fbr (mcu2_ncu_fbr ), | |
10850 | .ncu_mcu_ecci (ncu_mcu2_ecci ), | |
10851 | .ncu_mcu_fbui (ncu_mcu2_fbui ), | |
10852 | .ncu_mcu_fbri (ncu_mcu2_fbri ), | |
10853 | .mcu_fsr0_data (mcu2_fsr4_data[ 119 : 0 ] ), | |
10854 | .mcu_fsr1_data (mcu2_fsr5_data[ 119 : 0 ] ), | |
10855 | .mcu_fsr0_cfgpll_enpll (mcu2_fsr4_cfgpll_enpll ), | |
10856 | .mcu_fsr1_cfgpll_enpll (mcu2_fsr5_cfgpll_enpll ), | |
10857 | .mcu_fsr01_cfgpll_lb (mcu2_fsr45_cfgpll_lb[ 1 : 0 ] ), | |
10858 | .mcu_fsr01_cfgpll_mpy (mcu2_fsr45_cfgpll_mpy[ 3 : 0 ] ), | |
10859 | .mcu_fsr0_cfgrx_enrx (mcu2_fsr4_cfgrx_enrx ), | |
10860 | .mcu_fsr1_cfgrx_enrx (mcu2_fsr5_cfgrx_enrx ), | |
10861 | .mcu_fsr0_cfgrx_align (mcu2_fsr4_cfgrx_align ), | |
10862 | .mcu_fsr1_cfgrx_align (mcu2_fsr5_cfgrx_align ), | |
10863 | .mcu_fsr0_cfgrx_invpair (mcu2_fsr4_cfgrx_invpair[ 13 : 0 ]), | |
10864 | .mcu_fsr1_cfgrx_invpair (mcu2_fsr5_cfgrx_invpair[ 13 : 0 ]), | |
10865 | .mcu_fsr01_cfgrx_eq (mcu2_fsr45_cfgrx_eq[ 3 : 0 ] ), | |
10866 | .mcu_fsr01_cfgrx_cdr (mcu2_fsr45_cfgrx_cdr[ 2 : 0 ] ), | |
10867 | .mcu_fsr01_cfgrx_term (mcu2_fsr45_cfgrx_term[ 2 : 0 ] ), | |
10868 | .mcu_fsr0_cfgtx_entx (mcu2_fsr4_cfgtx_entx ), | |
10869 | .mcu_fsr1_cfgtx_entx (mcu2_fsr5_cfgtx_entx ), | |
10870 | .mcu_fsr0_cfgtx_enidl (mcu2_fsr4_cfgtx_enidl ), | |
10871 | .mcu_fsr1_cfgtx_enidl (mcu2_fsr5_cfgtx_enidl ), | |
10872 | .mcu_fsr0_cfgtx_invpair (mcu2_fsr4_cfgtx_invpair[ 9 : 0 ]), | |
10873 | .mcu_fsr1_cfgtx_invpair (mcu2_fsr5_cfgtx_invpair[ 9 : 0 ]), | |
10874 | .mcu_fsr01_cfgtx_enftp (mcu2_fsr45_cfgtx_enftp ), | |
10875 | .mcu_fsr01_cfgtx_de (mcu2_fsr45_cfgtx_de[ 3 : 0 ] ), | |
10876 | .mcu_fsr01_cfgtx_swing (mcu2_fsr45_cfgtx_swing[ 2 : 0 ] ), | |
10877 | .mcu_fsr01_cfgtx_cm (mcu2_fsr45_cfgtx_cm ), | |
10878 | .mcu_fsr01_cfgrtx_rate (mcu2_fsr45_cfgrtx_rate[ 1 : 0 ] ), | |
10879 | .mcu_fsr0_cfgrx_entest (mcu2_fsr4_cfgrx_entest ), | |
10880 | .mcu_fsr1_cfgrx_entest (mcu2_fsr5_cfgrx_entest ), | |
10881 | .mcu_fsr0_cfgtx_entest (mcu2_fsr4_cfgtx_entest ), | |
10882 | .mcu_fsr1_cfgtx_entest (mcu2_fsr5_cfgtx_entest ), | |
10883 | .mcu_fsr0_cfgtx_bstx (mcu2_fsr4_cfgtx_bstx[ 9 : 0 ] ), | |
10884 | .mcu_fsr1_cfgtx_bstx (mcu2_fsr5_cfgtx_bstx[ 9 : 0 ] ), | |
10885 | .fsr0_mcu_data (fsr4_mcu2_data[ 167 : 0 ] ), | |
10886 | .fsr1_mcu_data (fsr5_mcu2_data[ 167 : 0 ] ), | |
10887 | .fsr0_mcu_rxbclk (fsr4_mcu2_rxbclk[ 13 : 0 ] ), | |
10888 | .fsr1_mcu_rxbclk (fsr5_mcu2_rxbclk[ 13 : 0 ] ), | |
10889 | .fsr0_mcu_stspll_lock (fsr4_mcu2_stspll_lock[ 2 : 0 ] ), | |
10890 | .fsr1_mcu_stspll_lock (fsr5_mcu2_stspll_lock[ 2 : 0 ] ), | |
10891 | .mcu_fsr0_testcfg (mcu2_fsr4_testcfg[ 11 : 0 ] ), | |
10892 | .mcu_fsr1_testcfg (mcu2_fsr5_testcfg[ 11 : 0 ] ), | |
10893 | .fsr0_mcu_stsrx_sync ({fsr4_mcu2_stsrx_sync[ 9 : 8 ],fsr4_mcu2_stsrx_sync[ 0 ], fsr4_mcu2_stsrx_sync[ 1 ], | |
10894 | fsr4_mcu2_stsrx_sync[ 2 ], fsr4_mcu2_stsrx_sync[ 3 ], fsr4_mcu2_stsrx_sync[ 4 ], | |
10895 | fsr4_mcu2_stsrx_sync[ 5 ], fsr4_mcu2_stsrx_sync[ 6 ], fsr4_mcu2_stsrx_sync[ 7 ], | |
10896 | fsr4_mcu2_stsrx_sync[ 10 ], fsr4_mcu2_stsrx_sync[ 11 ],fsr4_mcu2_stsrx_sync[ 12 ], | |
10897 | fsr4_mcu2_stsrx_sync[ 13 ]}), | |
10898 | .fsr1_mcu_stsrx_sync ({fsr5_mcu2_stsrx_sync[ 9 : 8 ],fsr5_mcu2_stsrx_sync[ 0 ], fsr5_mcu2_stsrx_sync[ 1 ], | |
10899 | fsr5_mcu2_stsrx_sync[ 2 ], fsr5_mcu2_stsrx_sync[ 3 ], fsr5_mcu2_stsrx_sync[ 4 ], | |
10900 | fsr5_mcu2_stsrx_sync[ 5 ], fsr5_mcu2_stsrx_sync[ 6 ], fsr5_mcu2_stsrx_sync[ 7 ], | |
10901 | fsr5_mcu2_stsrx_sync[ 10 ], fsr5_mcu2_stsrx_sync[ 11 ],fsr5_mcu2_stsrx_sync[ 12 ], | |
10902 | fsr5_mcu2_stsrx_sync[ 13 ]}), | |
10903 | .fsr0_mcu_stsrx_losdtct ({fsr4_mcu2_stsrx_losdtct[ 9 : 8 ],fsr4_mcu2_stsrx_losdtct[ 0 ], fsr4_mcu2_stsrx_losdtct[ 1 ], | |
10904 | fsr4_mcu2_stsrx_losdtct[ 2 ], fsr4_mcu2_stsrx_losdtct[ 3 ], fsr4_mcu2_stsrx_losdtct[ 4 ], | |
10905 | fsr4_mcu2_stsrx_losdtct[ 5 ], fsr4_mcu2_stsrx_losdtct[ 6 ], fsr4_mcu2_stsrx_losdtct[ 7 ], | |
10906 | fsr4_mcu2_stsrx_losdtct[ 10 ], fsr4_mcu2_stsrx_losdtct[ 11 ],fsr4_mcu2_stsrx_losdtct[ 12 ], | |
10907 | fsr4_mcu2_stsrx_losdtct[ 13 ]}), | |
10908 | .fsr1_mcu_stsrx_losdtct ({fsr5_mcu2_stsrx_losdtct[ 9 : 8 ],fsr5_mcu2_stsrx_losdtct[ 0 ], fsr5_mcu2_stsrx_losdtct[ 1 ], | |
10909 | fsr5_mcu2_stsrx_losdtct[ 2 ], fsr5_mcu2_stsrx_losdtct[ 3 ], fsr5_mcu2_stsrx_losdtct[ 4 ], | |
10910 | fsr5_mcu2_stsrx_losdtct[ 5 ], fsr5_mcu2_stsrx_losdtct[ 6 ], fsr5_mcu2_stsrx_losdtct[ 7 ], | |
10911 | fsr5_mcu2_stsrx_losdtct[ 10 ], fsr5_mcu2_stsrx_losdtct[ 11 ],fsr5_mcu2_stsrx_losdtct[ 12 ], | |
10912 | fsr5_mcu2_stsrx_losdtct[ 13 ]}), | |
10913 | .fsr0_mcu_stsrx_testfail (fsr4_mcu2_stsrx_testfail[ 13 : 0 ]), | |
10914 | .fsr1_mcu_stsrx_testfail (fsr5_mcu2_stsrx_testfail[ 13 : 0 ]), | |
10915 | .fsr0_mcu_stsrx_bsrxp (fsr4_mcu2_stsrx_bsrxp[ 13 : 0 ] ), | |
10916 | .fsr1_mcu_stsrx_bsrxp (fsr5_mcu2_stsrx_bsrxp[ 13 : 0 ] ), | |
10917 | .fsr0_mcu_stsrx_bsrxn (fsr4_mcu2_stsrx_bsrxn[ 13 : 0 ] ), | |
10918 | .fsr1_mcu_stsrx_bsrxn (fsr5_mcu2_stsrx_bsrxn[ 13 : 0 ] ), | |
10919 | .fsr0_mcu_ststx_testfail (fsr4_mcu2_ststx_testfail[ 9 : 0 ]), | |
10920 | .fsr1_mcu_ststx_testfail (fsr5_mcu2_ststx_testfail[ 9 : 0 ]), | |
10921 | .mcu_id ({1'b1,1'b0} ), | |
10922 | .tcu_mcu_mbist_start (tcu_mcu2_mbist_start ), | |
10923 | .mcu_tcu_mbist_done (mcu2_tcu_mbist_done ), | |
10924 | .mcu_tcu_mbist_fail (mcu2_tcu_mbist_fail ), | |
10925 | .tcu_mcu_mbist_scan_in (tcu_mcu2_mbist_scan_in ), | |
10926 | .mcu_tcu_mbist_scan_out (mcu2_tcu_mbist_scan_out ), | |
10927 | .mcu_sbs_scan_in (mcu3_sbs_scan_out ), | |
10928 | .mcu_sbs_scan_out (mcu2_sbs_scan_out ), | |
10929 | .scan_in (mcu1_scan_out ), | |
10930 | .scan_out (mcu2_scan_out ), | |
10931 | .ncu_mcu_pm(ncu_mcu_pm), | |
10932 | .ncu_mcu_ba01(ncu_mcu_ba01), | |
10933 | .ncu_mcu_ba23(ncu_mcu_ba23), | |
10934 | .ncu_mcu_ba45(ncu_mcu_ba45), | |
10935 | .ncu_mcu_ba67(ncu_mcu_ba67), | |
10936 | .tcu_mbist_bisi_en(tcu_mbist_bisi_en), | |
10937 | .tcu_mbist_user_mode(tcu_mbist_user_mode), | |
10938 | .tcu_sbs_scan_en(tcu_sbs_scan_en), | |
10939 | .tcu_sbs_aclk(tcu_sbs_aclk), | |
10940 | .tcu_sbs_bclk(tcu_sbs_bclk), | |
10941 | .tcu_sbs_clk(tcu_sbs_clk), | |
10942 | .tcu_sbs_uclk(tcu_sbs_uclk), | |
10943 | .rst_mcu_selfrsh(rst_mcu_selfrsh), | |
10944 | .rst_wmr_protect(rst_wmr_protect), | |
10945 | .tcu_aclk(tcu_aclk), | |
10946 | .tcu_bclk(tcu_bclk), | |
10947 | .tcu_pce_ov(tcu_pce_ov), | |
10948 | .tcu_dectest(tcu_dectest), | |
10949 | .tcu_muxtest(tcu_muxtest), | |
10950 | .tcu_mcu_testmode(tcu_mcu_testmode), | |
10951 | .tcu_scan_en(tcu_scan_en), | |
10952 | .tcu_se_scancollar_in(tcu_se_scancollar_in), | |
10953 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit), | |
10954 | .tcu_array_bypass(tcu_array_bypass), | |
10955 | .tcu_atpg_mode(tcu_atpg_mode), | |
10956 | .tcu_div_bypass(tcu_div_bypass), | |
10957 | .ccu_serdes_dtm(ccu_serdes_dtm) | |
10958 | ); | |
10959 | `endif // OPENSPARC_CMP | |
10960 | //________________________________________________________________ | |
10961 | ||
10962 | // leave this instance out of cmp model | |
10963 | `ifdef OPENSPARC_CMP | |
10964 | `else | |
10965 | mcu mcu3( | |
10966 | .gclk ( cmp_gclk_c0_mcu3 ), // cmp_gclk_c3_r[3] ) , | |
10967 | .tcu_mcu_dr_clk_stop ( gl_mcu3_dr_clk_stop ), // staged clk_stop | |
10968 | .tcu_mcu_io_clk_stop ( gl_mcu3_io_clk_stop ), // staged clk_stop | |
10969 | .tcu_mcu_clk_stop ( gl_mcu3_clk_stop ), // staged clk_stop | |
10970 | .ccu_io_out ( gl_io_out_c1m ), // staged div phase | |
10971 | .dr_gclk ( dr_gclk_c0_mcu3 ), // dr_gclk_c3_r[3] ) , | |
10972 | .ccu_dr_sync_en (gl_dr_sync_en_c1m), | |
10973 | .ccu_io_cmp_sync_en ( gl_io_cmp_sync_en_c1m ), | |
10974 | .ccu_cmp_io_sync_en ( gl_cmp_io_sync_en_c1m ), | |
10975 | .tcu_mcu_fbd_clk_stop (tcu_mcu3_fbd_clk_stop ), | |
10976 | .mcu_dbg1_rd_req_in_0 (mcu3_dbg1_rd_req_in_0[ 3 : 0 ] ), | |
10977 | .mcu_dbg1_rd_req_in_1 (mcu3_dbg1_rd_req_in_1[ 3 : 0 ] ), | |
10978 | .mcu_dbg1_rd_req_out (mcu3_dbg1_rd_req_out[ 4 : 0 ] ), | |
10979 | .mcu_dbg1_wr_req_in_0 (mcu3_dbg1_wr_req_in_0 ), | |
10980 | .mcu_dbg1_wr_req_in_1 (mcu3_dbg1_wr_req_in_1 ), | |
10981 | .mcu_dbg1_wr_req_out (mcu3_dbg1_wr_req_out[ 1 : 0 ] ), | |
10982 | .mcu_dbg1_mecc_err (mcu3_dbg1_mecc_err ), | |
10983 | .mcu_dbg1_secc_err (mcu3_dbg1_secc_err ), | |
10984 | .mcu_dbg1_fbd_err (mcu3_dbg1_fbd_err ), | |
10985 | .mcu_dbg1_err_mode (mcu3_dbg1_err_mode ), | |
10986 | .mcu_dbg1_err_event (mcu3_dbg1_err_event ), | |
10987 | .mcu_dbg1_crc21 (mcu3_dbg1_crc21 ), | |
10988 | .l2t0_mcu_rd_req (l2t6_mcu3_rd_req ), | |
10989 | .l2t0_mcu_wr_req (l2t6_mcu3_wr_req ), | |
10990 | .l2t0_mcu_rd_dummy_req (l2t6_mcu3_rd_dummy_req ), | |
10991 | .l2t0_mcu_rd_req_id (l2t6_mcu3_rd_req_id[ 2 : 0 ] ), | |
10992 | .l2t0_mcu_addr_39to7 (l2t6_mcu3_addr[ 39 : 7 ] ), | |
10993 | .l2t0_mcu_addr_5 (l2t6_mcu3_addr_5 ), | |
10994 | .mcu_l2t0_rd_ack (mcu3_l2t6_rd_ack ), | |
10995 | .mcu_l2t0_wr_ack (mcu3_l2t6_wr_ack ), | |
10996 | .mcu_l2t0_data_vld_r0 (mcu3_l2t6_data_vld_r0 ), | |
10997 | .mcu_l2t0_rd_req_id_r0 (mcu3_l2t6_rd_req_id_r0[ 2 : 0 ] ), | |
10998 | .mcu_l2t0_secc_err_r3 (mcu3_l2t6_secc_err_r2 ), | |
10999 | .mcu_l2t0_mecc_err_r3 (mcu3_l2t6_mecc_err_r2 ), | |
11000 | .mcu_l2t0_scb_secc_err (mcu3_l2t6_scb_secc_err ), | |
11001 | .mcu_l2t0_scb_mecc_err (mcu3_l2t6_scb_mecc_err ), | |
11002 | .mcu_l2t0_qword_id_r0 (mcu3_l2t6_qword_id_r0[ 1 : 0 ] ), | |
11003 | .l2t1_mcu_rd_req (l2t7_mcu3_rd_req_t6lff ), | |
11004 | .l2t1_mcu_wr_req (l2t7_mcu3_wr_req_t6lff ), | |
11005 | .l2t1_mcu_rd_dummy_req (l2t7_mcu3_rd_dummy_req_t6lff ), | |
11006 | .l2t1_mcu_rd_req_id (l2t7_mcu3_rd_req_id_t6lff[ 2 : 0 ] ), | |
11007 | .l2t1_mcu_addr_39to7 (l2t7_mcu3_addr_t6lff[ 39 : 7 ] ), | |
11008 | .l2t1_mcu_addr_5 (l2t7_mcu3_addr_5_t6lff ), | |
11009 | .mcu_l2t1_rd_ack (mcu3_l2t7_rd_ack ), | |
11010 | .mcu_l2t1_wr_ack (mcu3_l2t7_wr_ack ), | |
11011 | .mcu_l2t1_data_vld_r0 (mcu3_l2t7_data_vld_r0 ), | |
11012 | .mcu_l2t1_rd_req_id_r0 (mcu3_l2t7_rd_req_id_r0[ 2 : 0 ] ), | |
11013 | .mcu_l2t1_secc_err_r3 (mcu3_l2t7_secc_err_r2 ), | |
11014 | .mcu_l2t1_mecc_err_r3 (mcu3_l2t7_mecc_err_r2 ), | |
11015 | .mcu_l2t1_scb_secc_err (mcu3_l2t7_scb_secc_err ), | |
11016 | .mcu_l2t1_scb_mecc_err (mcu3_l2t7_scb_mecc_err ), | |
11017 | .mcu_l2t1_qword_id_r0 (mcu3_l2t7_qword_id_r0[ 1 : 0 ] ), | |
11018 | .mcu_l2b_data_r3 (mcu3_l2b67_data_r2[ 127 : 0 ] ), | |
11019 | .mcu_l2b_ecc_r3 (mcu3_l2b67_ecc_r2[ 27 : 0 ] ), | |
11020 | .l2b0_mcu_data_mecc_r5 (l2b6_mcu3_data_mecc_r5 ), | |
11021 | .l2b0_mcu_wr_data_r5 (l2b6_mcu3_wr_data_r5[ 63 : 0 ] ), | |
11022 | .l2b0_mcu_data_vld_r5 (l2b6_mcu3_data_vld_r5 ), | |
11023 | .l2b1_mcu_data_mecc_r5 (l2b7_mcu3_data_mecc_r5 ), | |
11024 | .l2b1_mcu_wr_data_r5 (l2b7_mcu3_wr_data_r5[ 63 : 0 ] ), | |
11025 | .l2b1_mcu_data_vld_r5 (l2b7_mcu3_data_vld_r5 ), | |
11026 | .mcu_pt_sync_out (mcu3_pt_sync_out ), | |
11027 | .mcu_pt_sync_in0 (mcu0_pt_sync_out ), | |
11028 | .mcu_pt_sync_in1 (mcu1_pt_sync_out ), | |
11029 | .mcu_pt_sync_in2 (mcu2_pt_sync_out ), | |
11030 | .mcu_ncu_data (mcu3_ncu_data[ 3 : 0 ] ), | |
11031 | .mcu_ncu_stall (mcu3_ncu_stall ), | |
11032 | .mcu_ncu_vld (mcu3_ncu_vld ), | |
11033 | .ncu_mcu_data (ncu_mcu3_data[ 3 : 0 ] ), | |
11034 | .ncu_mcu_stall (ncu_mcu3_stall ), | |
11035 | .ncu_mcu_vld (ncu_mcu3_vld ), | |
11036 | .mcu_ncu_ecc (mcu3_ncu_ecc ), | |
11037 | .mcu_ncu_fbr (mcu3_ncu_fbr ), | |
11038 | .ncu_mcu_ecci (ncu_mcu3_ecci ), | |
11039 | .ncu_mcu_fbui (ncu_mcu3_fbui ), | |
11040 | .ncu_mcu_fbri (ncu_mcu3_fbri ), | |
11041 | .mcu_fsr0_data (mcu3_fsr6_data[ 119 : 0 ] ), | |
11042 | .mcu_fsr1_data (mcu3_fsr7_data[ 119 : 0 ] ), | |
11043 | .mcu_fsr0_cfgpll_enpll (mcu3_fsr6_cfgpll_enpll ), | |
11044 | .mcu_fsr1_cfgpll_enpll (mcu3_fsr7_cfgpll_enpll ), | |
11045 | .mcu_fsr01_cfgpll_lb (mcu3_fsr67_cfgpll_lb[ 1 : 0 ] ), | |
11046 | .mcu_fsr01_cfgpll_mpy (mcu3_fsr67_cfgpll_mpy[ 3 : 0 ] ), | |
11047 | .mcu_fsr0_cfgrx_enrx (mcu3_fsr6_cfgrx_enrx ), | |
11048 | .mcu_fsr1_cfgrx_enrx (mcu3_fsr7_cfgrx_enrx ), | |
11049 | .mcu_fsr0_cfgrx_align (mcu3_fsr6_cfgrx_align ), | |
11050 | .mcu_fsr1_cfgrx_align (mcu3_fsr7_cfgrx_align ), | |
11051 | .mcu_fsr0_cfgrx_invpair (mcu3_fsr6_cfgrx_invpair[ 13 : 0 ]), | |
11052 | .mcu_fsr1_cfgrx_invpair (mcu3_fsr7_cfgrx_invpair[ 13 : 0 ]), | |
11053 | .mcu_fsr01_cfgrx_eq (mcu3_fsr67_cfgrx_eq[ 3 : 0 ] ), | |
11054 | .mcu_fsr01_cfgrx_cdr (mcu3_fsr67_cfgrx_cdr[ 2 : 0 ] ), | |
11055 | .mcu_fsr01_cfgrx_term (mcu3_fsr67_cfgrx_term[ 2 : 0 ] ), | |
11056 | .mcu_fsr0_cfgtx_entx (mcu3_fsr6_cfgtx_entx ), | |
11057 | .mcu_fsr1_cfgtx_entx (mcu3_fsr7_cfgtx_entx ), | |
11058 | .mcu_fsr0_cfgtx_enidl (mcu3_fsr6_cfgtx_enidl ), | |
11059 | .mcu_fsr1_cfgtx_enidl (mcu3_fsr7_cfgtx_enidl ), | |
11060 | .mcu_fsr0_cfgtx_invpair (mcu3_fsr6_cfgtx_invpair[ 9 : 0 ]), | |
11061 | .mcu_fsr1_cfgtx_invpair (mcu3_fsr7_cfgtx_invpair[ 9 : 0 ]), | |
11062 | .mcu_fsr01_cfgtx_enftp (mcu3_fsr67_cfgtx_enftp ), | |
11063 | .mcu_fsr01_cfgtx_de (mcu3_fsr67_cfgtx_de[ 3 : 0 ] ), | |
11064 | .mcu_fsr01_cfgtx_swing (mcu3_fsr67_cfgtx_swing[ 2 : 0 ] ), | |
11065 | .mcu_fsr01_cfgtx_cm (mcu3_fsr67_cfgtx_cm ), | |
11066 | .mcu_fsr01_cfgrtx_rate (mcu3_fsr67_cfgrtx_rate[ 1 : 0 ] ), | |
11067 | .mcu_fsr0_cfgrx_entest (mcu3_fsr6_cfgrx_entest ), | |
11068 | .mcu_fsr1_cfgrx_entest (mcu3_fsr7_cfgrx_entest ), | |
11069 | .mcu_fsr0_cfgtx_entest (mcu3_fsr6_cfgtx_entest ), | |
11070 | .mcu_fsr1_cfgtx_entest (mcu3_fsr7_cfgtx_entest ), | |
11071 | .mcu_fsr0_cfgtx_bstx (mcu3_fsr6_cfgtx_bstx[ 9 : 0 ] ), | |
11072 | .mcu_fsr1_cfgtx_bstx (mcu3_fsr7_cfgtx_bstx[ 9 : 0 ] ), | |
11073 | .fsr0_mcu_data (fsr6_mcu3_data[ 167 : 0 ] ), | |
11074 | .fsr1_mcu_data (fsr7_mcu3_data[ 167 : 0 ] ), | |
11075 | .fsr0_mcu_rxbclk (fsr6_mcu3_rxbclk[ 13 : 0 ] ), | |
11076 | .fsr1_mcu_rxbclk (fsr7_mcu3_rxbclk[ 13 : 0 ] ), | |
11077 | .fsr0_mcu_stspll_lock (fsr6_mcu3_stspll_lock[ 2 : 0 ] ), | |
11078 | .fsr1_mcu_stspll_lock (fsr7_mcu3_stspll_lock[ 2 : 0 ] ), | |
11079 | .mcu_fsr0_testcfg (mcu3_fsr6_testcfg[ 11 : 0 ] ), | |
11080 | .mcu_fsr1_testcfg (mcu3_fsr7_testcfg[ 11 : 0 ] ), | |
11081 | .fsr0_mcu_stsrx_sync ({fsr6_mcu3_stsrx_sync[ 9 : 8 ],fsr6_mcu3_stsrx_sync[ 0 ], fsr6_mcu3_stsrx_sync[ 1 ], | |
11082 | fsr6_mcu3_stsrx_sync[ 2 ], fsr6_mcu3_stsrx_sync[ 3 ], fsr6_mcu3_stsrx_sync[ 4 ], | |
11083 | fsr6_mcu3_stsrx_sync[ 5 ], fsr6_mcu3_stsrx_sync[ 6 ], fsr6_mcu3_stsrx_sync[ 7 ], | |
11084 | fsr6_mcu3_stsrx_sync[ 10 ], fsr6_mcu3_stsrx_sync[ 11 ],fsr6_mcu3_stsrx_sync[ 12 ], | |
11085 | fsr6_mcu3_stsrx_sync[ 13 ]}), | |
11086 | .fsr1_mcu_stsrx_sync ({fsr7_mcu3_stsrx_sync[ 8 ], fsr7_mcu3_stsrx_sync[ 9 ], | |
11087 | fsr7_mcu3_stsrx_sync[ 13 : 10 ],fsr7_mcu3_stsrx_sync[ 7 : 0 ]}), | |
11088 | .fsr0_mcu_stsrx_losdtct ({fsr6_mcu3_stsrx_losdtct[ 9 : 8 ],fsr6_mcu3_stsrx_losdtct[ 0 ], fsr6_mcu3_stsrx_losdtct[ 1 ], | |
11089 | fsr6_mcu3_stsrx_losdtct[ 2 ], fsr6_mcu3_stsrx_losdtct[ 3 ], fsr6_mcu3_stsrx_losdtct[ 4 ], | |
11090 | fsr6_mcu3_stsrx_losdtct[ 5 ], fsr6_mcu3_stsrx_losdtct[ 6 ], fsr6_mcu3_stsrx_losdtct[ 7 ], | |
11091 | fsr6_mcu3_stsrx_losdtct[ 10 ], fsr6_mcu3_stsrx_losdtct[ 11 ],fsr6_mcu3_stsrx_losdtct[ 12 ], | |
11092 | fsr6_mcu3_stsrx_losdtct[ 13 ]}), | |
11093 | .fsr1_mcu_stsrx_losdtct ({fsr7_mcu3_stsrx_losdtct[ 8 ], fsr7_mcu3_stsrx_losdtct[ 9 ], | |
11094 | fsr7_mcu3_stsrx_losdtct[ 13 : 10 ],fsr7_mcu3_stsrx_losdtct[ 7 : 0 ]}), | |
11095 | .fsr0_mcu_stsrx_testfail (fsr6_mcu3_stsrx_testfail[ 13 : 0 ]), | |
11096 | .fsr1_mcu_stsrx_testfail (fsr7_mcu3_stsrx_testfail[ 13 : 0 ]), | |
11097 | .fsr0_mcu_stsrx_bsrxp (fsr6_mcu3_stsrx_bsrxp[ 13 : 0 ] ), | |
11098 | .fsr1_mcu_stsrx_bsrxp (fsr7_mcu3_stsrx_bsrxp[ 13 : 0 ] ), | |
11099 | .fsr0_mcu_stsrx_bsrxn (fsr6_mcu3_stsrx_bsrxn[ 13 : 0 ] ), | |
11100 | .fsr1_mcu_stsrx_bsrxn (fsr7_mcu3_stsrx_bsrxn[ 13 : 0 ] ), | |
11101 | .fsr0_mcu_ststx_testfail (fsr6_mcu3_ststx_testfail[ 9 : 0 ]), | |
11102 | .fsr1_mcu_ststx_testfail (fsr7_mcu3_ststx_testfail[ 9 : 0 ]), | |
11103 | .mcu_id ({1'b1,1'b1} ), | |
11104 | .tcu_mcu_mbist_start (tcu_mcu3_mbist_start ), | |
11105 | .mcu_tcu_mbist_done (mcu3_tcu_mbist_done ), | |
11106 | .mcu_tcu_mbist_fail (mcu3_tcu_mbist_fail ), | |
11107 | .tcu_mcu_mbist_scan_in (tcu_mcu3_mbist_scan_in ), | |
11108 | .mcu_tcu_mbist_scan_out (mcu3_tcu_mbist_scan_out ), | |
11109 | .mcu_sbs_scan_in (mac_mcu_3_sbs_output ), // 03/24 | |
11110 | .mcu_sbs_scan_out (mcu3_sbs_scan_out ), | |
11111 | .scan_in (ncu_scan_out ), | |
11112 | .scan_out (mcu3_scan_out ), | |
11113 | .ncu_mcu_pm(ncu_mcu_pm), | |
11114 | .ncu_mcu_ba01(ncu_mcu_ba01), | |
11115 | .ncu_mcu_ba23(ncu_mcu_ba23), | |
11116 | .ncu_mcu_ba45(ncu_mcu_ba45), | |
11117 | .ncu_mcu_ba67(ncu_mcu_ba67), | |
11118 | .tcu_mbist_bisi_en(tcu_mbist_bisi_en), | |
11119 | .tcu_mbist_user_mode(tcu_mbist_user_mode), | |
11120 | .tcu_sbs_scan_en(tcu_sbs_scan_en), | |
11121 | .tcu_sbs_aclk(tcu_sbs_aclk), | |
11122 | .tcu_sbs_bclk(tcu_sbs_bclk), | |
11123 | .tcu_sbs_clk(tcu_sbs_clk), | |
11124 | .tcu_sbs_uclk(tcu_sbs_uclk), | |
11125 | .rst_mcu_selfrsh(rst_mcu_selfrsh), | |
11126 | .rst_wmr_protect(rst_wmr_protect), | |
11127 | .tcu_aclk(tcu_aclk), | |
11128 | .tcu_bclk(tcu_bclk), | |
11129 | .tcu_pce_ov(tcu_pce_ov), | |
11130 | .tcu_dectest(tcu_dectest), | |
11131 | .tcu_muxtest(tcu_muxtest), | |
11132 | .tcu_mcu_testmode(tcu_mcu_testmode), | |
11133 | .tcu_scan_en(tcu_scan_en), | |
11134 | .tcu_se_scancollar_in(tcu_se_scancollar_in), | |
11135 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit), | |
11136 | .tcu_array_bypass(tcu_array_bypass), | |
11137 | .tcu_atpg_mode(tcu_atpg_mode), | |
11138 | .tcu_div_bypass(tcu_div_bypass), | |
11139 | .ccu_serdes_dtm(ccu_serdes_dtm) | |
11140 | ); | |
11141 | `endif // OPENSPARC_CMP | |
11142 | ||
11143 | //________________________________________________________________ | |
11144 | ||
11145 | // leave this instance out of cmp model | |
11146 | `ifdef OPENSPARC_CMP | |
11147 | `else | |
11148 | fsr_left fsr_left ( | |
11149 | .FBDIMM0A_RX_P ({FBDIMM0A_RX_P[ 11 : 8 ],FBDIMM0A_RX_P[ 12 ],FBDIMM0A_RX_P[ 13 ],FBDIMM0A_RX_P[ 7 : 0 ]}), | |
11150 | .FBDIMM0A_RX_N ({FBDIMM0A_RX_N[ 11 : 8 ],FBDIMM0A_RX_N[ 12 ],FBDIMM0A_RX_N[ 13 ],FBDIMM0A_RX_N[ 7 : 0 ]}), | |
11151 | .FBDIMM0A_TX_P ({FBDIMM0A_TX_P[ 8 : 5 ],FBDIMM0A_TX_P[ 9 ],FBDIMM0A_TX_P[ 4 : 0 ]}), | |
11152 | .FBDIMM0A_TX_N ({FBDIMM0A_TX_N[ 8 : 5 ],FBDIMM0A_TX_N[ 9 ],FBDIMM0A_TX_N[ 4 : 0 ]}), | |
11153 | .FBDIMM0B_RX_P ({FBDIMM0B_RX_P[ 11 : 8 ],FBDIMM0B_RX_P[ 12 ],FBDIMM0B_RX_P[ 13 ],FBDIMM0B_RX_P[ 7 : 0 ]}), | |
11154 | .FBDIMM0B_RX_N ({FBDIMM0B_RX_N[ 11 : 8 ],FBDIMM0B_RX_N[ 12 ],FBDIMM0B_RX_N[ 13 ],FBDIMM0B_RX_N[ 7 : 0 ]}), | |
11155 | .FBDIMM0B_TX_P ({FBDIMM0B_TX_P[ 8 : 5 ],FBDIMM0B_TX_P[ 9 ],FBDIMM0B_TX_P[ 4 : 0 ]}), | |
11156 | .FBDIMM0B_TX_N ({FBDIMM0B_TX_N[ 8 : 5 ],FBDIMM0B_TX_N[ 9 ],FBDIMM0B_TX_N[ 4 : 0 ]}), | |
11157 | .FBDIMM1A_RX_P ({FBDIMM1A_RX_P[ 11 : 8 ],FBDIMM1A_RX_P[ 12 ],FBDIMM1A_RX_P[ 13 ],FBDIMM1A_RX_P[ 7 : 0 ]}), | |
11158 | .FBDIMM1A_RX_N ({FBDIMM1A_RX_N[ 11 : 8 ],FBDIMM1A_RX_N[ 12 ],FBDIMM1A_RX_N[ 13 ],FBDIMM1A_RX_N[ 7 : 0 ]}), | |
11159 | .FBDIMM1A_TX_P ({FBDIMM1A_TX_P[ 8 : 5 ],FBDIMM1A_TX_P[ 9 ],FBDIMM1A_TX_P[ 4 : 0 ]}), | |
11160 | .FBDIMM1A_TX_N ({FBDIMM1A_TX_N[ 8 : 5 ],FBDIMM1A_TX_N[ 9 ],FBDIMM1A_TX_N[ 4 : 0 ]}), | |
11161 | .FBDIMM1B_RX_P ({FBDIMM1B_RX_P[ 11 : 8 ],FBDIMM1B_RX_P[ 12 ],FBDIMM1B_RX_P[ 13 ],FBDIMM1B_RX_P[ 7 : 0 ]}), | |
11162 | .FBDIMM1B_RX_N ({FBDIMM1B_RX_N[ 11 : 8 ],FBDIMM1B_RX_N[ 12 ],FBDIMM1B_RX_N[ 13 ],FBDIMM1B_RX_N[ 7 : 0 ]}), | |
11163 | .FBDIMM1B_TX_P ({FBDIMM1B_TX_P[ 8 : 5 ],FBDIMM1B_TX_P[ 9 ],FBDIMM1B_TX_P[ 4 : 0 ]}), | |
11164 | .FBDIMM1B_TX_N ({FBDIMM1B_TX_N[ 8 : 5 ],FBDIMM1B_TX_N[ 9 ],FBDIMM1B_TX_N[ 4 : 0 ]}), | |
11165 | .mcu0_fsr0_td0 (mcu0_fsr0_data[ 11 : 0 ]), | |
11166 | .mcu0_fsr0_td1 (mcu0_fsr0_data[ 23 : 12 ]), | |
11167 | .mcu0_fsr0_td2 (mcu0_fsr0_data[ 35 : 24 ]), | |
11168 | .mcu0_fsr0_td3 (mcu0_fsr0_data[ 47 : 36 ]), | |
11169 | .mcu0_fsr0_td4 (mcu0_fsr0_data[ 59 : 48 ]), | |
11170 | .mcu0_fsr0_td6 (mcu0_fsr0_data[ 71 : 60 ]), | |
11171 | .mcu0_fsr0_td7 (mcu0_fsr0_data[ 83 : 72 ]), | |
11172 | .mcu0_fsr0_td8 (mcu0_fsr0_data[ 95 : 84 ]), | |
11173 | .mcu0_fsr0_td9 (mcu0_fsr0_data[ 107 : 96 ]), | |
11174 | .mcu0_fsr0_td5 (mcu0_fsr0_data[ 119 : 108 ]), | |
11175 | .fsr0_mcu0_rd0 (fsr0_mcu0_data[ 11 : 0 ]), | |
11176 | .fsr0_mcu0_rd1 (fsr0_mcu0_data[ 23 : 12 ]), | |
11177 | .fsr0_mcu0_rd2 (fsr0_mcu0_data[ 35 : 24 ]), | |
11178 | .fsr0_mcu0_rd3 (fsr0_mcu0_data[ 47 : 36 ]), | |
11179 | .fsr0_mcu0_rd4 (fsr0_mcu0_data[ 59 : 48 ]), | |
11180 | .fsr0_mcu0_rd5 (fsr0_mcu0_data[ 71 : 60 ]), | |
11181 | .fsr0_mcu0_rd6 (fsr0_mcu0_data[ 83 : 72 ]), | |
11182 | .fsr0_mcu0_rd7 (fsr0_mcu0_data[ 95 : 84 ]), | |
11183 | .fsr0_mcu0_rd10 (fsr0_mcu0_data[ 107 : 96 ]), | |
11184 | .fsr0_mcu0_rd11 (fsr0_mcu0_data[ 119 : 108 ]), | |
11185 | .fsr0_mcu0_rd12 (fsr0_mcu0_data[ 131 : 120 ]), | |
11186 | .fsr0_mcu0_rd13 (fsr0_mcu0_data[ 143 : 132 ]), | |
11187 | .fsr0_mcu0_rd9 (fsr0_mcu0_data[ 155 : 144 ]), | |
11188 | .fsr0_mcu0_rd8 (fsr0_mcu0_data[ 167 : 156 ]), | |
11189 | .mcu0_fsr0_cfgpll0 ({mcu0_fsr01_cfgpll_lb[ 1 : 0 ], mcu0_fsr01_cfgpll_mpy[ 3 : 0 ], mcu0_fsr0_cfgpll_enpll}), | |
11190 | .mcu0_fsr0_cfgpll1 ({mcu0_fsr01_cfgpll_lb[ 1 : 0 ], mcu0_fsr01_cfgpll_mpy[ 3 : 0 ], mcu0_fsr0_cfgpll_enpll}), | |
11191 | .mcu0_fsr0_cfgpll2 ({mcu0_fsr01_cfgpll_lb[ 1 : 0 ], mcu0_fsr01_cfgpll_mpy[ 3 : 0 ], mcu0_fsr0_cfgpll_enpll}), | |
11192 | .mcu0_fsr0_cfgrx0 ({1'b0, 1'b0, mcu0_fsr01_cfgrx_eq[ 3 : 0 ], | |
11193 | mcu0_fsr01_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu0_fsr0_cfgrx_align, | |
11194 | mcu0_fsr01_cfgrx_term[ 2 : 0 ], mcu0_fsr0_cfgrx_invpair[ 0 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], | |
11195 | mcu0_fsr0_cfgrx_entest, mcu0_fsr0_cfgrx_enrx}), | |
11196 | .mcu0_fsr0_cfgrx1 ({1'b0, 1'b0, mcu0_fsr01_cfgrx_eq[ 3 : 0 ], | |
11197 | mcu0_fsr01_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu0_fsr0_cfgrx_align, | |
11198 | mcu0_fsr01_cfgrx_term[ 2 : 0 ], mcu0_fsr0_cfgrx_invpair[ 1 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], | |
11199 | mcu0_fsr0_cfgrx_entest, mcu0_fsr0_cfgrx_enrx}), | |
11200 | .mcu0_fsr0_cfgrx2 ({1'b0, 1'b0, mcu0_fsr01_cfgrx_eq[ 3 : 0 ], | |
11201 | mcu0_fsr01_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu0_fsr0_cfgrx_align, | |
11202 | mcu0_fsr01_cfgrx_term[ 2 : 0 ], mcu0_fsr0_cfgrx_invpair[ 2 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], | |
11203 | mcu0_fsr0_cfgrx_entest, mcu0_fsr0_cfgrx_enrx}), | |
11204 | .mcu0_fsr0_cfgrx3 ({1'b0, 1'b0, mcu0_fsr01_cfgrx_eq[ 3 : 0 ], | |
11205 | mcu0_fsr01_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu0_fsr0_cfgrx_align, | |
11206 | mcu0_fsr01_cfgrx_term[ 2 : 0 ], mcu0_fsr0_cfgrx_invpair[ 3 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], | |
11207 | mcu0_fsr0_cfgrx_entest, mcu0_fsr0_cfgrx_enrx}), | |
11208 | .mcu0_fsr0_cfgrx4 ({1'b0, 1'b0, mcu0_fsr01_cfgrx_eq[ 3 : 0 ], | |
11209 | mcu0_fsr01_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu0_fsr0_cfgrx_align, | |
11210 | mcu0_fsr01_cfgrx_term[ 2 : 0 ], mcu0_fsr0_cfgrx_invpair[ 4 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], | |
11211 | mcu0_fsr0_cfgrx_entest, mcu0_fsr0_cfgrx_enrx}), | |
11212 | .mcu0_fsr0_cfgrx5 ({1'b0, 1'b0, mcu0_fsr01_cfgrx_eq[ 3 : 0 ], | |
11213 | mcu0_fsr01_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu0_fsr0_cfgrx_align, | |
11214 | mcu0_fsr01_cfgrx_term[ 2 : 0 ], mcu0_fsr0_cfgrx_invpair[ 5 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], | |
11215 | mcu0_fsr0_cfgrx_entest, mcu0_fsr0_cfgrx_enrx}), | |
11216 | .mcu0_fsr0_cfgrx6 ({1'b0, 1'b0, mcu0_fsr01_cfgrx_eq[ 3 : 0 ], | |
11217 | mcu0_fsr01_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu0_fsr0_cfgrx_align, | |
11218 | mcu0_fsr01_cfgrx_term[ 2 : 0 ], mcu0_fsr0_cfgrx_invpair[ 6 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], | |
11219 | mcu0_fsr0_cfgrx_entest, mcu0_fsr0_cfgrx_enrx}), | |
11220 | .mcu0_fsr0_cfgrx7 ({1'b0, 1'b0, mcu0_fsr01_cfgrx_eq[ 3 : 0 ], | |
11221 | mcu0_fsr01_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu0_fsr0_cfgrx_align, | |
11222 | mcu0_fsr01_cfgrx_term[ 2 : 0 ], mcu0_fsr0_cfgrx_invpair[ 7 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], | |
11223 | mcu0_fsr0_cfgrx_entest, mcu0_fsr0_cfgrx_enrx}), | |
11224 | .mcu0_fsr0_cfgrx10 ({1'b0, 1'b0, mcu0_fsr01_cfgrx_eq[ 3 : 0 ], | |
11225 | mcu0_fsr01_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu0_fsr0_cfgrx_align, | |
11226 | mcu0_fsr01_cfgrx_term[ 2 : 0 ], mcu0_fsr0_cfgrx_invpair[ 8 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], | |
11227 | mcu0_fsr0_cfgrx_entest, mcu0_fsr0_cfgrx_enrx}), | |
11228 | .mcu0_fsr0_cfgrx11 ({1'b0, 1'b0, mcu0_fsr01_cfgrx_eq[ 3 : 0 ], | |
11229 | mcu0_fsr01_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu0_fsr0_cfgrx_align, | |
11230 | mcu0_fsr01_cfgrx_term[ 2 : 0 ], mcu0_fsr0_cfgrx_invpair[ 9 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], | |
11231 | mcu0_fsr0_cfgrx_entest, mcu0_fsr0_cfgrx_enrx}), | |
11232 | .mcu0_fsr0_cfgrx12 ({1'b0, 1'b0, mcu0_fsr01_cfgrx_eq[ 3 : 0 ], | |
11233 | mcu0_fsr01_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu0_fsr0_cfgrx_align, | |
11234 | mcu0_fsr01_cfgrx_term[ 2 : 0 ], mcu0_fsr0_cfgrx_invpair[ 10 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], | |
11235 | mcu0_fsr0_cfgrx_entest, mcu0_fsr0_cfgrx_enrx}), | |
11236 | .mcu0_fsr0_cfgrx13 ({1'b0, 1'b0, mcu0_fsr01_cfgrx_eq[ 3 : 0 ], | |
11237 | mcu0_fsr01_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu0_fsr0_cfgrx_align, | |
11238 | mcu0_fsr01_cfgrx_term[ 2 : 0 ], mcu0_fsr0_cfgrx_invpair[ 11 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], | |
11239 | mcu0_fsr0_cfgrx_entest, mcu0_fsr0_cfgrx_enrx}), | |
11240 | .mcu0_fsr0_cfgrx9 ({1'b0, 1'b0, mcu0_fsr01_cfgrx_eq[ 3 : 0 ], | |
11241 | mcu0_fsr01_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu0_fsr0_cfgrx_align, | |
11242 | mcu0_fsr01_cfgrx_term[ 2 : 0 ], mcu0_fsr0_cfgrx_invpair[ 12 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], | |
11243 | mcu0_fsr0_cfgrx_entest, mcu0_fsr0_cfgrx_enrx}), | |
11244 | .mcu0_fsr0_cfgrx8 ({1'b0, 1'b0, mcu0_fsr01_cfgrx_eq[ 3 : 0 ], | |
11245 | mcu0_fsr01_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu0_fsr0_cfgrx_align, | |
11246 | mcu0_fsr01_cfgrx_term[ 2 : 0 ], mcu0_fsr0_cfgrx_invpair[ 13 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], | |
11247 | mcu0_fsr0_cfgrx_entest, mcu0_fsr0_cfgrx_enrx}), | |
11248 | .mcu0_fsr0_cfgtx0 ({mcu0_fsr0_cfgtx_enidl, mcu0_fsr0_cfgtx_bstx[ 0 ], mcu0_fsr01_cfgtx_enftp, | |
11249 | mcu0_fsr01_cfgtx_de[ 3 : 0 ], mcu0_fsr01_cfgtx_swing[ 2 : 0 ], mcu0_fsr01_cfgtx_cm, | |
11250 | mcu0_fsr0_cfgtx_invpair[ 0 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], mcu0_fsr0_cfgtx_entest, | |
11251 | mcu0_fsr0_cfgtx_entx}), | |
11252 | .mcu0_fsr0_cfgtx1 ({mcu0_fsr0_cfgtx_enidl, mcu0_fsr0_cfgtx_bstx[ 1 ], mcu0_fsr01_cfgtx_enftp, | |
11253 | mcu0_fsr01_cfgtx_de[ 3 : 0 ], mcu0_fsr01_cfgtx_swing[ 2 : 0 ], mcu0_fsr01_cfgtx_cm, | |
11254 | mcu0_fsr0_cfgtx_invpair[ 1 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], mcu0_fsr0_cfgtx_entest, | |
11255 | mcu0_fsr0_cfgtx_entx}), | |
11256 | .mcu0_fsr0_cfgtx2 ({mcu0_fsr0_cfgtx_enidl, mcu0_fsr0_cfgtx_bstx[ 2 ], mcu0_fsr01_cfgtx_enftp, | |
11257 | mcu0_fsr01_cfgtx_de[ 3 : 0 ], mcu0_fsr01_cfgtx_swing[ 2 : 0 ], mcu0_fsr01_cfgtx_cm, | |
11258 | mcu0_fsr0_cfgtx_invpair[ 2 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], mcu0_fsr0_cfgtx_entest, | |
11259 | mcu0_fsr0_cfgtx_entx}), | |
11260 | .mcu0_fsr0_cfgtx3 ({mcu0_fsr0_cfgtx_enidl, mcu0_fsr0_cfgtx_bstx[ 3 ], mcu0_fsr01_cfgtx_enftp, | |
11261 | mcu0_fsr01_cfgtx_de[ 3 : 0 ], mcu0_fsr01_cfgtx_swing[ 2 : 0 ], mcu0_fsr01_cfgtx_cm, | |
11262 | mcu0_fsr0_cfgtx_invpair[ 3 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], mcu0_fsr0_cfgtx_entest, | |
11263 | mcu0_fsr0_cfgtx_entx}), | |
11264 | .mcu0_fsr0_cfgtx4 ({mcu0_fsr0_cfgtx_enidl, mcu0_fsr0_cfgtx_bstx[ 4 ], mcu0_fsr01_cfgtx_enftp, | |
11265 | mcu0_fsr01_cfgtx_de[ 3 : 0 ], mcu0_fsr01_cfgtx_swing[ 2 : 0 ], mcu0_fsr01_cfgtx_cm, | |
11266 | mcu0_fsr0_cfgtx_invpair[ 4 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], mcu0_fsr0_cfgtx_entest, | |
11267 | mcu0_fsr0_cfgtx_entx}), | |
11268 | .mcu0_fsr0_cfgtx6 ({mcu0_fsr0_cfgtx_enidl, mcu0_fsr0_cfgtx_bstx[ 5 ], mcu0_fsr01_cfgtx_enftp, | |
11269 | mcu0_fsr01_cfgtx_de[ 3 : 0 ], mcu0_fsr01_cfgtx_swing[ 2 : 0 ], mcu0_fsr01_cfgtx_cm, | |
11270 | mcu0_fsr0_cfgtx_invpair[ 5 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], mcu0_fsr0_cfgtx_entest, | |
11271 | mcu0_fsr0_cfgtx_entx}), | |
11272 | .mcu0_fsr0_cfgtx7 ({mcu0_fsr0_cfgtx_enidl, mcu0_fsr0_cfgtx_bstx[ 6 ], mcu0_fsr01_cfgtx_enftp, | |
11273 | mcu0_fsr01_cfgtx_de[ 3 : 0 ], mcu0_fsr01_cfgtx_swing[ 2 : 0 ], mcu0_fsr01_cfgtx_cm, | |
11274 | mcu0_fsr0_cfgtx_invpair[ 6 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], mcu0_fsr0_cfgtx_entest, | |
11275 | mcu0_fsr0_cfgtx_entx}), | |
11276 | .mcu0_fsr0_cfgtx8 ({mcu0_fsr0_cfgtx_enidl, mcu0_fsr0_cfgtx_bstx[ 7 ], mcu0_fsr01_cfgtx_enftp, | |
11277 | mcu0_fsr01_cfgtx_de[ 3 : 0 ], mcu0_fsr01_cfgtx_swing[ 2 : 0 ], mcu0_fsr01_cfgtx_cm, | |
11278 | mcu0_fsr0_cfgtx_invpair[ 7 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], mcu0_fsr0_cfgtx_entest, | |
11279 | mcu0_fsr0_cfgtx_entx}), | |
11280 | .mcu0_fsr0_cfgtx9 ({mcu0_fsr0_cfgtx_enidl, mcu0_fsr0_cfgtx_bstx[ 8 ], mcu0_fsr01_cfgtx_enftp, | |
11281 | mcu0_fsr01_cfgtx_de[ 3 : 0 ], mcu0_fsr01_cfgtx_swing[ 2 : 0 ], mcu0_fsr01_cfgtx_cm, | |
11282 | mcu0_fsr0_cfgtx_invpair[ 8 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], mcu0_fsr0_cfgtx_entest, | |
11283 | mcu0_fsr0_cfgtx_entx}), | |
11284 | .mcu0_fsr0_cfgtx5 ({mcu0_fsr0_cfgtx_enidl, mcu0_fsr0_cfgtx_bstx[ 9 ], mcu0_fsr01_cfgtx_enftp, | |
11285 | mcu0_fsr01_cfgtx_de[ 3 : 0 ], mcu0_fsr01_cfgtx_swing[ 2 : 0 ], mcu0_fsr01_cfgtx_cm, | |
11286 | mcu0_fsr0_cfgtx_invpair[ 9 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], mcu0_fsr0_cfgtx_entest, | |
11287 | mcu0_fsr0_cfgtx_entx}), | |
11288 | .mcu0_fsr0_testcfg0 ({tcu_srd_atpgse, tcu_srd_atpgmode[ 2 : 0 ], mcu0_fsr0_testcfg[ 11 : 8 ], tcu_sbs_enbsrx, tcu_sbs_enbstx, mcu0_fsr0_testcfg[ 7 : 0 ]}), | |
11289 | .mcu0_fsr0_testcfg1 ({tcu_srd_atpgse, tcu_srd_atpgmode[ 2 : 0 ], mcu0_fsr0_testcfg[ 11 : 8 ], tcu_sbs_enbsrx, tcu_sbs_enbstx, mcu0_fsr0_testcfg[ 7 : 0 ]}), | |
11290 | .mcu0_fsr0_testcfg2 ({tcu_srd_atpgse, tcu_srd_atpgmode[ 2 : 0 ], mcu0_fsr0_testcfg[ 11 : 8 ], tcu_sbs_enbsrx, tcu_sbs_enbstx, mcu0_fsr0_testcfg[ 7 : 0 ]}), | |
11291 | .fsr0_txbclkin ({dr_gclk_c4_fsr0_2,dr_gclk_c4_fsr0_1,dr_gclk_c4_fsr0_0}), | |
11292 | .fsr0_mcu0_rxbclk ({fsr0_mcu0_rxbclk[ 11 : 8 ],fsr0_mcu0_rxbclk[ 12 ],fsr0_mcu0_rxbclk[ 13 ],fsr0_mcu0_rxbclk[ 7 : 0 ]}), | |
11293 | .fsr0_rxbclkin ({fsr0_mcu0_rxbclk[ 11 : 8 ],fsr0_mcu0_rxbclk[ 12 ],fsr0_mcu0_rxbclk[ 13 ],fsr0_mcu0_rxbclk[ 7 : 0 ]}), | |
11294 | .fsr0_bsinitclk ({tcu_sbs_bsinitclk, tcu_sbs_bsinitclk, tcu_sbs_bsinitclk}), | |
11295 | .fsr0_fclk ({efu_mcu_fclk, efu_mcu_fclk, efu_mcu_fclk}), | |
11296 | .fsr0_fclrz ({efu_mcu_fclrz, efu_mcu_fclrz, efu_mcu_fclrz}), | |
11297 | .fsr0_fdi ({efu_mcu_fdi,fsr0_fdo[ 2 : 1 ]}), | |
11298 | .fsr0_fdo (fsr0_fdo[ 2 : 0 ]), | |
11299 | .fsr0_stcicfg ({tcu_stcicfg[ 1 : 0 ], tcu_stcicfg[ 1 : 0 ], tcu_stcicfg[ 1 : 0 ]}), | |
11300 | .fsr0_stciclk ({tcu_stciclk, tcu_stciclk, tcu_stciclk}), | |
11301 | .fsr0_stcid ({fsr0_stciq[ 1 : 0 ],tcu_stcid}), | |
11302 | .fsr0_stciq (fsr0_stciq[ 2 : 0 ]), | |
11303 | .fsr0_testclkr ({mio_fsr_testclkr[ 0 ],mio_fsr_testclkr[ 0 ],mio_fsr_testclkr[ 0 ]}), | |
11304 | .fsr0_testclkt ({mio_fsr_testclkt[ 0 ],mio_fsr_testclkt[ 0 ],mio_fsr_testclkt[ 0 ]}), | |
11305 | .mcu0_fsr1_td0 (mcu0_fsr1_data[ 11 : 0 ]), | |
11306 | .mcu0_fsr1_td1 (mcu0_fsr1_data[ 23 : 12 ]), | |
11307 | .mcu0_fsr1_td2 (mcu0_fsr1_data[ 35 : 24 ]), | |
11308 | .mcu0_fsr1_td3 (mcu0_fsr1_data[ 47 : 36 ]), | |
11309 | .mcu0_fsr1_td4 (mcu0_fsr1_data[ 59 : 48 ]), | |
11310 | .mcu0_fsr1_td6 (mcu0_fsr1_data[ 71 : 60 ]), | |
11311 | .mcu0_fsr1_td7 (mcu0_fsr1_data[ 83 : 72 ]), | |
11312 | .mcu0_fsr1_td8 (mcu0_fsr1_data[ 95 : 84 ]), | |
11313 | .mcu0_fsr1_td9 (mcu0_fsr1_data[ 107 : 96 ]), | |
11314 | .mcu0_fsr1_td5 (mcu0_fsr1_data[ 119 : 108 ]), | |
11315 | .fsr1_mcu0_rd0 (fsr1_mcu0_data[ 11 : 0 ]), | |
11316 | .fsr1_mcu0_rd1 (fsr1_mcu0_data[ 23 : 12 ]), | |
11317 | .fsr1_mcu0_rd2 (fsr1_mcu0_data[ 35 : 24 ]), | |
11318 | .fsr1_mcu0_rd3 (fsr1_mcu0_data[ 47 : 36 ]), | |
11319 | .fsr1_mcu0_rd4 (fsr1_mcu0_data[ 59 : 48 ]), | |
11320 | .fsr1_mcu0_rd5 (fsr1_mcu0_data[ 71 : 60 ]), | |
11321 | .fsr1_mcu0_rd6 (fsr1_mcu0_data[ 83 : 72 ]), | |
11322 | .fsr1_mcu0_rd7 (fsr1_mcu0_data[ 95 : 84 ]), | |
11323 | .fsr1_mcu0_rd10 (fsr1_mcu0_data[ 107 : 96 ]), | |
11324 | .fsr1_mcu0_rd11 (fsr1_mcu0_data[ 119 : 108 ]), | |
11325 | .fsr1_mcu0_rd12 (fsr1_mcu0_data[ 131 : 120 ]), | |
11326 | .fsr1_mcu0_rd13 (fsr1_mcu0_data[ 143 : 132 ]), | |
11327 | .fsr1_mcu0_rd9 (fsr1_mcu0_data[ 155 : 144 ]), | |
11328 | .fsr1_mcu0_rd8 (fsr1_mcu0_data[ 167 : 156 ]), | |
11329 | .mcu0_fsr1_cfgpll0 ({mcu0_fsr01_cfgpll_lb[ 1 : 0 ], mcu0_fsr01_cfgpll_mpy[ 3 : 0 ], mcu0_fsr1_cfgpll_enpll}), | |
11330 | .mcu0_fsr1_cfgpll1 ({mcu0_fsr01_cfgpll_lb[ 1 : 0 ], mcu0_fsr01_cfgpll_mpy[ 3 : 0 ], mcu0_fsr1_cfgpll_enpll}), | |
11331 | .mcu0_fsr1_cfgpll2 ({mcu0_fsr01_cfgpll_lb[ 1 : 0 ], mcu0_fsr01_cfgpll_mpy[ 3 : 0 ], mcu0_fsr1_cfgpll_enpll}), | |
11332 | .mcu0_fsr1_cfgrx0 ({1'b0, 1'b0, mcu0_fsr01_cfgrx_eq[ 3 : 0 ], | |
11333 | mcu0_fsr01_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu0_fsr1_cfgrx_align, | |
11334 | mcu0_fsr01_cfgrx_term[ 2 : 0 ], mcu0_fsr1_cfgrx_invpair[ 0 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], | |
11335 | mcu0_fsr1_cfgrx_entest, mcu0_fsr1_cfgrx_enrx}), | |
11336 | .mcu0_fsr1_cfgrx1 ({1'b0, 1'b0, mcu0_fsr01_cfgrx_eq[ 3 : 0 ], | |
11337 | mcu0_fsr01_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu0_fsr1_cfgrx_align, | |
11338 | mcu0_fsr01_cfgrx_term[ 2 : 0 ], mcu0_fsr1_cfgrx_invpair[ 1 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], | |
11339 | mcu0_fsr1_cfgrx_entest, mcu0_fsr1_cfgrx_enrx}), | |
11340 | .mcu0_fsr1_cfgrx2 ({1'b0, 1'b0, mcu0_fsr01_cfgrx_eq[ 3 : 0 ], | |
11341 | mcu0_fsr01_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu0_fsr1_cfgrx_align, | |
11342 | mcu0_fsr01_cfgrx_term[ 2 : 0 ], mcu0_fsr1_cfgrx_invpair[ 2 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], | |
11343 | mcu0_fsr1_cfgrx_entest, mcu0_fsr1_cfgrx_enrx}), | |
11344 | .mcu0_fsr1_cfgrx3 ({1'b0, 1'b0, mcu0_fsr01_cfgrx_eq[ 3 : 0 ], | |
11345 | mcu0_fsr01_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu0_fsr1_cfgrx_align, | |
11346 | mcu0_fsr01_cfgrx_term[ 2 : 0 ], mcu0_fsr1_cfgrx_invpair[ 3 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], | |
11347 | mcu0_fsr1_cfgrx_entest, mcu0_fsr1_cfgrx_enrx}), | |
11348 | .mcu0_fsr1_cfgrx4 ({1'b0, 1'b0, mcu0_fsr01_cfgrx_eq[ 3 : 0 ], | |
11349 | mcu0_fsr01_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu0_fsr1_cfgrx_align, | |
11350 | mcu0_fsr01_cfgrx_term[ 2 : 0 ], mcu0_fsr1_cfgrx_invpair[ 4 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], | |
11351 | mcu0_fsr1_cfgrx_entest, mcu0_fsr1_cfgrx_enrx}), | |
11352 | .mcu0_fsr1_cfgrx5 ({1'b0, 1'b0, mcu0_fsr01_cfgrx_eq[ 3 : 0 ], | |
11353 | mcu0_fsr01_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu0_fsr1_cfgrx_align, | |
11354 | mcu0_fsr01_cfgrx_term[ 2 : 0 ], mcu0_fsr1_cfgrx_invpair[ 5 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], | |
11355 | mcu0_fsr1_cfgrx_entest, mcu0_fsr1_cfgrx_enrx}), | |
11356 | .mcu0_fsr1_cfgrx6 ({1'b0, 1'b0, mcu0_fsr01_cfgrx_eq[ 3 : 0 ], | |
11357 | mcu0_fsr01_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu0_fsr1_cfgrx_align, | |
11358 | mcu0_fsr01_cfgrx_term[ 2 : 0 ], mcu0_fsr1_cfgrx_invpair[ 6 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], | |
11359 | mcu0_fsr1_cfgrx_entest, mcu0_fsr1_cfgrx_enrx}), | |
11360 | .mcu0_fsr1_cfgrx7 ({1'b0, 1'b0, mcu0_fsr01_cfgrx_eq[ 3 : 0 ], | |
11361 | mcu0_fsr01_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu0_fsr1_cfgrx_align, | |
11362 | mcu0_fsr01_cfgrx_term[ 2 : 0 ], mcu0_fsr1_cfgrx_invpair[ 7 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], | |
11363 | mcu0_fsr1_cfgrx_entest, mcu0_fsr1_cfgrx_enrx}), | |
11364 | .mcu0_fsr1_cfgrx10 ({1'b0, 1'b0, mcu0_fsr01_cfgrx_eq[ 3 : 0 ], | |
11365 | mcu0_fsr01_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu0_fsr1_cfgrx_align, | |
11366 | mcu0_fsr01_cfgrx_term[ 2 : 0 ], mcu0_fsr1_cfgrx_invpair[ 8 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], | |
11367 | mcu0_fsr1_cfgrx_entest, mcu0_fsr1_cfgrx_enrx}), | |
11368 | .mcu0_fsr1_cfgrx11 ({1'b0, 1'b0, mcu0_fsr01_cfgrx_eq[ 3 : 0 ], | |
11369 | mcu0_fsr01_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu0_fsr1_cfgrx_align, | |
11370 | mcu0_fsr01_cfgrx_term[ 2 : 0 ], mcu0_fsr1_cfgrx_invpair[ 9 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], | |
11371 | mcu0_fsr1_cfgrx_entest, mcu0_fsr1_cfgrx_enrx}), | |
11372 | .mcu0_fsr1_cfgrx12 ({1'b0, 1'b0, mcu0_fsr01_cfgrx_eq[ 3 : 0 ], | |
11373 | mcu0_fsr01_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu0_fsr1_cfgrx_align, | |
11374 | mcu0_fsr01_cfgrx_term[ 2 : 0 ], mcu0_fsr1_cfgrx_invpair[ 10 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], | |
11375 | mcu0_fsr1_cfgrx_entest, mcu0_fsr1_cfgrx_enrx}), | |
11376 | .mcu0_fsr1_cfgrx13 ({1'b0, 1'b0, mcu0_fsr01_cfgrx_eq[ 3 : 0 ], | |
11377 | mcu0_fsr01_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu0_fsr1_cfgrx_align, | |
11378 | mcu0_fsr01_cfgrx_term[ 2 : 0 ], mcu0_fsr1_cfgrx_invpair[ 11 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], | |
11379 | mcu0_fsr1_cfgrx_entest, mcu0_fsr1_cfgrx_enrx}), | |
11380 | .mcu0_fsr1_cfgrx9 ({1'b0, 1'b0, mcu0_fsr01_cfgrx_eq[ 3 : 0 ], | |
11381 | mcu0_fsr01_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu0_fsr1_cfgrx_align, | |
11382 | mcu0_fsr01_cfgrx_term[ 2 : 0 ], mcu0_fsr1_cfgrx_invpair[ 12 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], | |
11383 | mcu0_fsr1_cfgrx_entest, mcu0_fsr1_cfgrx_enrx}), | |
11384 | .mcu0_fsr1_cfgrx8 ({1'b0, 1'b0, mcu0_fsr01_cfgrx_eq[ 3 : 0 ], | |
11385 | mcu0_fsr01_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu0_fsr1_cfgrx_align, | |
11386 | mcu0_fsr01_cfgrx_term[ 2 : 0 ], mcu0_fsr1_cfgrx_invpair[ 13 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], | |
11387 | mcu0_fsr1_cfgrx_entest, mcu0_fsr1_cfgrx_enrx}), | |
11388 | .mcu0_fsr1_cfgtx0 ({mcu0_fsr1_cfgtx_enidl, mcu0_fsr1_cfgtx_bstx[ 0 ], mcu0_fsr01_cfgtx_enftp, | |
11389 | mcu0_fsr01_cfgtx_de[ 3 : 0 ], mcu0_fsr01_cfgtx_swing[ 2 : 0 ], mcu0_fsr01_cfgtx_cm, | |
11390 | mcu0_fsr1_cfgtx_invpair[ 0 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], mcu0_fsr1_cfgtx_entest, | |
11391 | mcu0_fsr1_cfgtx_entx}), | |
11392 | .mcu0_fsr1_cfgtx1 ({mcu0_fsr1_cfgtx_enidl, mcu0_fsr1_cfgtx_bstx[ 1 ], mcu0_fsr01_cfgtx_enftp, | |
11393 | mcu0_fsr01_cfgtx_de[ 3 : 0 ], mcu0_fsr01_cfgtx_swing[ 2 : 0 ], mcu0_fsr01_cfgtx_cm, | |
11394 | mcu0_fsr1_cfgtx_invpair[ 1 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], mcu0_fsr1_cfgtx_entest, | |
11395 | mcu0_fsr1_cfgtx_entx}), | |
11396 | .mcu0_fsr1_cfgtx2 ({mcu0_fsr1_cfgtx_enidl, mcu0_fsr1_cfgtx_bstx[ 2 ], mcu0_fsr01_cfgtx_enftp, | |
11397 | mcu0_fsr01_cfgtx_de[ 3 : 0 ], mcu0_fsr01_cfgtx_swing[ 2 : 0 ], mcu0_fsr01_cfgtx_cm, | |
11398 | mcu0_fsr1_cfgtx_invpair[ 2 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], mcu0_fsr1_cfgtx_entest, | |
11399 | mcu0_fsr1_cfgtx_entx}), | |
11400 | .mcu0_fsr1_cfgtx3 ({mcu0_fsr1_cfgtx_enidl, mcu0_fsr1_cfgtx_bstx[ 3 ], mcu0_fsr01_cfgtx_enftp, | |
11401 | mcu0_fsr01_cfgtx_de[ 3 : 0 ], mcu0_fsr01_cfgtx_swing[ 2 : 0 ], mcu0_fsr01_cfgtx_cm, | |
11402 | mcu0_fsr1_cfgtx_invpair[ 3 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], mcu0_fsr1_cfgtx_entest, | |
11403 | mcu0_fsr1_cfgtx_entx}), | |
11404 | .mcu0_fsr1_cfgtx4 ({mcu0_fsr1_cfgtx_enidl, mcu0_fsr1_cfgtx_bstx[ 4 ], mcu0_fsr01_cfgtx_enftp, | |
11405 | mcu0_fsr01_cfgtx_de[ 3 : 0 ], mcu0_fsr01_cfgtx_swing[ 2 : 0 ], mcu0_fsr01_cfgtx_cm, | |
11406 | mcu0_fsr1_cfgtx_invpair[ 4 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], mcu0_fsr1_cfgtx_entest, | |
11407 | mcu0_fsr1_cfgtx_entx}), | |
11408 | .mcu0_fsr1_cfgtx6 ({mcu0_fsr1_cfgtx_enidl, mcu0_fsr1_cfgtx_bstx[ 5 ], mcu0_fsr01_cfgtx_enftp, | |
11409 | mcu0_fsr01_cfgtx_de[ 3 : 0 ], mcu0_fsr01_cfgtx_swing[ 2 : 0 ], mcu0_fsr01_cfgtx_cm, | |
11410 | mcu0_fsr1_cfgtx_invpair[ 5 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], mcu0_fsr1_cfgtx_entest, | |
11411 | mcu0_fsr1_cfgtx_entx}), | |
11412 | .mcu0_fsr1_cfgtx7 ({mcu0_fsr1_cfgtx_enidl, mcu0_fsr1_cfgtx_bstx[ 6 ], mcu0_fsr01_cfgtx_enftp, | |
11413 | mcu0_fsr01_cfgtx_de[ 3 : 0 ], mcu0_fsr01_cfgtx_swing[ 2 : 0 ], mcu0_fsr01_cfgtx_cm, | |
11414 | mcu0_fsr1_cfgtx_invpair[ 6 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], mcu0_fsr1_cfgtx_entest, | |
11415 | mcu0_fsr1_cfgtx_entx}), | |
11416 | .mcu0_fsr1_cfgtx8 ({mcu0_fsr1_cfgtx_enidl, mcu0_fsr1_cfgtx_bstx[ 7 ], mcu0_fsr01_cfgtx_enftp, | |
11417 | mcu0_fsr01_cfgtx_de[ 3 : 0 ], mcu0_fsr01_cfgtx_swing[ 2 : 0 ], mcu0_fsr01_cfgtx_cm, | |
11418 | mcu0_fsr1_cfgtx_invpair[ 7 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], mcu0_fsr1_cfgtx_entest, | |
11419 | mcu0_fsr1_cfgtx_entx}), | |
11420 | .mcu0_fsr1_cfgtx9 ({mcu0_fsr1_cfgtx_enidl, mcu0_fsr1_cfgtx_bstx[ 8 ], mcu0_fsr01_cfgtx_enftp, | |
11421 | mcu0_fsr01_cfgtx_de[ 3 : 0 ], mcu0_fsr01_cfgtx_swing[ 2 : 0 ], mcu0_fsr01_cfgtx_cm, | |
11422 | mcu0_fsr1_cfgtx_invpair[ 8 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], mcu0_fsr1_cfgtx_entest, | |
11423 | mcu0_fsr1_cfgtx_entx}), | |
11424 | .mcu0_fsr1_cfgtx5 ({mcu0_fsr1_cfgtx_enidl, mcu0_fsr1_cfgtx_bstx[ 9 ], mcu0_fsr01_cfgtx_enftp, | |
11425 | mcu0_fsr01_cfgtx_de[ 3 : 0 ], mcu0_fsr01_cfgtx_swing[ 2 : 0 ], mcu0_fsr01_cfgtx_cm, | |
11426 | mcu0_fsr1_cfgtx_invpair[ 9 ], mcu0_fsr01_cfgrtx_rate[ 1 : 0 ], mcu0_fsr1_cfgtx_entest, | |
11427 | mcu0_fsr1_cfgtx_entx}), | |
11428 | .mcu0_fsr1_testcfg0 ({tcu_srd_atpgse, tcu_srd_atpgmode[ 2 : 0 ], mcu0_fsr1_testcfg[ 11 : 8 ], tcu_sbs_enbsrx, tcu_sbs_enbstx, mcu0_fsr1_testcfg[ 7 : 0 ]}), | |
11429 | .mcu0_fsr1_testcfg1 ({tcu_srd_atpgse, tcu_srd_atpgmode[ 2 : 0 ], mcu0_fsr1_testcfg[ 11 : 8 ], tcu_sbs_enbsrx, tcu_sbs_enbstx, mcu0_fsr1_testcfg[ 7 : 0 ]}), | |
11430 | .mcu0_fsr1_testcfg2 ({tcu_srd_atpgse, tcu_srd_atpgmode[ 2 : 0 ], mcu0_fsr1_testcfg[ 11 : 8 ], tcu_sbs_enbsrx, tcu_sbs_enbstx, mcu0_fsr1_testcfg[ 7 : 0 ]}), | |
11431 | .fsr1_txbclkin ({dr_gclk_c4_fsr1_2,dr_gclk_c4_fsr1_1,dr_gclk_c4_fsr1_0}), | |
11432 | .fsr1_mcu0_rxbclk ({fsr1_mcu0_rxbclk[ 11 : 8 ],fsr1_mcu0_rxbclk[ 12 ],fsr1_mcu0_rxbclk[ 13 ],fsr1_mcu0_rxbclk[ 7 : 0 ]}), | |
11433 | .fsr1_rxbclkin ({fsr1_mcu0_rxbclk[ 11 : 8 ],fsr1_mcu0_rxbclk[ 12 ],fsr1_mcu0_rxbclk[ 13 ],fsr1_mcu0_rxbclk[ 7 : 0 ]}), | |
11434 | .fsr1_bsinitclk ({tcu_sbs_bsinitclk, tcu_sbs_bsinitclk, tcu_sbs_bsinitclk}), | |
11435 | .fsr1_fclk ({efu_mcu_fclk, efu_mcu_fclk, efu_mcu_fclk}), | |
11436 | .fsr1_fclrz ({efu_mcu_fclrz, efu_mcu_fclrz, efu_mcu_fclrz}), | |
11437 | .fsr1_fdi ({fsr0_fdo[ 0 ],fsr1_fdo[ 2 : 1 ]}), | |
11438 | .fsr1_fdo (fsr1_fdo[ 2 : 0 ]), | |
11439 | .fsr1_stcicfg ({tcu_stcicfg[ 1 : 0 ], tcu_stcicfg[ 1 : 0 ], tcu_stcicfg[ 1 : 0 ]}), | |
11440 | .fsr1_stciclk ({tcu_stciclk, tcu_stciclk, tcu_stciclk}), | |
11441 | .fsr1_stcid ({fsr1_stciq[ 1 : 0 ],fsr0_stciq[ 2 ]}), | |
11442 | .fsr1_stciq (fsr1_stciq[ 2 : 0 ]), | |
11443 | .fsr1_testclkr ({mio_fsr_testclkr[ 1 ], mio_fsr_testclkr[ 1 ], mio_fsr_testclkr[ 1 ]}), | |
11444 | .fsr1_testclkt ({mio_fsr_testclkt[ 1 ], mio_fsr_testclkt[ 1 ], mio_fsr_testclkt[ 1 ]}), | |
11445 | .mcu1_fsr2_td0 (mcu1_fsr2_data[ 11 : 0 ]), | |
11446 | .mcu1_fsr2_td1 (mcu1_fsr2_data[ 23 : 12 ]), | |
11447 | .mcu1_fsr2_td2 (mcu1_fsr2_data[ 35 : 24 ]), | |
11448 | .mcu1_fsr2_td3 (mcu1_fsr2_data[ 47 : 36 ]), | |
11449 | .mcu1_fsr2_td4 (mcu1_fsr2_data[ 59 : 48 ]), | |
11450 | .mcu1_fsr2_td6 (mcu1_fsr2_data[ 71 : 60 ]), | |
11451 | .mcu1_fsr2_td7 (mcu1_fsr2_data[ 83 : 72 ]), | |
11452 | .mcu1_fsr2_td8 (mcu1_fsr2_data[ 95 : 84 ]), | |
11453 | .mcu1_fsr2_td9 (mcu1_fsr2_data[ 107 : 96 ]), | |
11454 | .mcu1_fsr2_td5 (mcu1_fsr2_data[ 119 : 108 ]), | |
11455 | .fsr2_mcu1_rd0 (fsr2_mcu1_data[ 11 : 0 ]), | |
11456 | .fsr2_mcu1_rd1 (fsr2_mcu1_data[ 23 : 12 ]), | |
11457 | .fsr2_mcu1_rd2 (fsr2_mcu1_data[ 35 : 24 ]), | |
11458 | .fsr2_mcu1_rd3 (fsr2_mcu1_data[ 47 : 36 ]), | |
11459 | .fsr2_mcu1_rd4 (fsr2_mcu1_data[ 59 : 48 ]), | |
11460 | .fsr2_mcu1_rd5 (fsr2_mcu1_data[ 71 : 60 ]), | |
11461 | .fsr2_mcu1_rd6 (fsr2_mcu1_data[ 83 : 72 ]), | |
11462 | .fsr2_mcu1_rd7 (fsr2_mcu1_data[ 95 : 84 ]), | |
11463 | .fsr2_mcu1_rd10 (fsr2_mcu1_data[ 107 : 96 ]), | |
11464 | .fsr2_mcu1_rd11 (fsr2_mcu1_data[ 119 : 108 ]), | |
11465 | .fsr2_mcu1_rd12 (fsr2_mcu1_data[ 131 : 120 ]), | |
11466 | .fsr2_mcu1_rd13 (fsr2_mcu1_data[ 143 : 132 ]), | |
11467 | .fsr2_mcu1_rd9 (fsr2_mcu1_data[ 155 : 144 ]), | |
11468 | .fsr2_mcu1_rd8 (fsr2_mcu1_data[ 167 : 156 ]), | |
11469 | .mcu1_fsr2_cfgpll0 ({mcu1_fsr23_cfgpll_lb[ 1 : 0 ], mcu1_fsr23_cfgpll_mpy[ 3 : 0 ], mcu1_fsr2_cfgpll_enpll}), | |
11470 | .mcu1_fsr2_cfgpll1 ({mcu1_fsr23_cfgpll_lb[ 1 : 0 ], mcu1_fsr23_cfgpll_mpy[ 3 : 0 ], mcu1_fsr2_cfgpll_enpll}), | |
11471 | .mcu1_fsr2_cfgpll2 ({mcu1_fsr23_cfgpll_lb[ 1 : 0 ], mcu1_fsr23_cfgpll_mpy[ 3 : 0 ], mcu1_fsr2_cfgpll_enpll}), | |
11472 | .mcu1_fsr2_cfgrx0 ({1'b0, 1'b0, mcu1_fsr23_cfgrx_eq[ 3 : 0 ], | |
11473 | mcu1_fsr23_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu1_fsr2_cfgrx_align, | |
11474 | mcu1_fsr23_cfgrx_term[ 2 : 0 ], mcu1_fsr2_cfgrx_invpair[ 0 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], | |
11475 | mcu1_fsr2_cfgrx_entest, mcu1_fsr2_cfgrx_enrx}), | |
11476 | .mcu1_fsr2_cfgrx1 ({1'b0, 1'b0, mcu1_fsr23_cfgrx_eq[ 3 : 0 ], | |
11477 | mcu1_fsr23_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu1_fsr2_cfgrx_align, | |
11478 | mcu1_fsr23_cfgrx_term[ 2 : 0 ], mcu1_fsr2_cfgrx_invpair[ 1 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], | |
11479 | mcu1_fsr2_cfgrx_entest, mcu1_fsr2_cfgrx_enrx}), | |
11480 | .mcu1_fsr2_cfgrx2 ({1'b0, 1'b0, mcu1_fsr23_cfgrx_eq[ 3 : 0 ], | |
11481 | mcu1_fsr23_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu1_fsr2_cfgrx_align, | |
11482 | mcu1_fsr23_cfgrx_term[ 2 : 0 ], mcu1_fsr2_cfgrx_invpair[ 2 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], | |
11483 | mcu1_fsr2_cfgrx_entest, mcu1_fsr2_cfgrx_enrx}), | |
11484 | .mcu1_fsr2_cfgrx3 ({1'b0, 1'b0, mcu1_fsr23_cfgrx_eq[ 3 : 0 ], | |
11485 | mcu1_fsr23_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu1_fsr2_cfgrx_align, | |
11486 | mcu1_fsr23_cfgrx_term[ 2 : 0 ], mcu1_fsr2_cfgrx_invpair[ 3 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], | |
11487 | mcu1_fsr2_cfgrx_entest, mcu1_fsr2_cfgrx_enrx}), | |
11488 | .mcu1_fsr2_cfgrx4 ({1'b0, 1'b0, mcu1_fsr23_cfgrx_eq[ 3 : 0 ], | |
11489 | mcu1_fsr23_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu1_fsr2_cfgrx_align, | |
11490 | mcu1_fsr23_cfgrx_term[ 2 : 0 ], mcu1_fsr2_cfgrx_invpair[ 4 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], | |
11491 | mcu1_fsr2_cfgrx_entest, mcu1_fsr2_cfgrx_enrx}), | |
11492 | .mcu1_fsr2_cfgrx5 ({1'b0, 1'b0, mcu1_fsr23_cfgrx_eq[ 3 : 0 ], | |
11493 | mcu1_fsr23_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu1_fsr2_cfgrx_align, | |
11494 | mcu1_fsr23_cfgrx_term[ 2 : 0 ], mcu1_fsr2_cfgrx_invpair[ 5 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], | |
11495 | mcu1_fsr2_cfgrx_entest, mcu1_fsr2_cfgrx_enrx}), | |
11496 | .mcu1_fsr2_cfgrx6 ({1'b0, 1'b0, mcu1_fsr23_cfgrx_eq[ 3 : 0 ], | |
11497 | mcu1_fsr23_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu1_fsr2_cfgrx_align, | |
11498 | mcu1_fsr23_cfgrx_term[ 2 : 0 ], mcu1_fsr2_cfgrx_invpair[ 6 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], | |
11499 | mcu1_fsr2_cfgrx_entest, mcu1_fsr2_cfgrx_enrx}), | |
11500 | .mcu1_fsr2_cfgrx7 ({1'b0, 1'b0, mcu1_fsr23_cfgrx_eq[ 3 : 0 ], | |
11501 | mcu1_fsr23_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu1_fsr2_cfgrx_align, | |
11502 | mcu1_fsr23_cfgrx_term[ 2 : 0 ], mcu1_fsr2_cfgrx_invpair[ 7 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], | |
11503 | mcu1_fsr2_cfgrx_entest, mcu1_fsr2_cfgrx_enrx}), | |
11504 | .mcu1_fsr2_cfgrx10 ({1'b0, 1'b0, mcu1_fsr23_cfgrx_eq[ 3 : 0 ], | |
11505 | mcu1_fsr23_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu1_fsr2_cfgrx_align, | |
11506 | mcu1_fsr23_cfgrx_term[ 2 : 0 ], mcu1_fsr2_cfgrx_invpair[ 8 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], | |
11507 | mcu1_fsr2_cfgrx_entest, mcu1_fsr2_cfgrx_enrx}), | |
11508 | .mcu1_fsr2_cfgrx11 ({1'b0, 1'b0, mcu1_fsr23_cfgrx_eq[ 3 : 0 ], | |
11509 | mcu1_fsr23_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu1_fsr2_cfgrx_align, | |
11510 | mcu1_fsr23_cfgrx_term[ 2 : 0 ], mcu1_fsr2_cfgrx_invpair[ 9 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], | |
11511 | mcu1_fsr2_cfgrx_entest, mcu1_fsr2_cfgrx_enrx}), | |
11512 | .mcu1_fsr2_cfgrx12 ({1'b0, 1'b0, mcu1_fsr23_cfgrx_eq[ 3 : 0 ], | |
11513 | mcu1_fsr23_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu1_fsr2_cfgrx_align, | |
11514 | mcu1_fsr23_cfgrx_term[ 2 : 0 ], mcu1_fsr2_cfgrx_invpair[ 10 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], | |
11515 | mcu1_fsr2_cfgrx_entest, mcu1_fsr2_cfgrx_enrx}), | |
11516 | .mcu1_fsr2_cfgrx13 ({1'b0, 1'b0, mcu1_fsr23_cfgrx_eq[ 3 : 0 ], | |
11517 | mcu1_fsr23_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu1_fsr2_cfgrx_align, | |
11518 | mcu1_fsr23_cfgrx_term[ 2 : 0 ], mcu1_fsr2_cfgrx_invpair[ 11 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], | |
11519 | mcu1_fsr2_cfgrx_entest, mcu1_fsr2_cfgrx_enrx}), | |
11520 | .mcu1_fsr2_cfgrx9 ({1'b0, 1'b0, mcu1_fsr23_cfgrx_eq[ 3 : 0 ], | |
11521 | mcu1_fsr23_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu1_fsr2_cfgrx_align, | |
11522 | mcu1_fsr23_cfgrx_term[ 2 : 0 ], mcu1_fsr2_cfgrx_invpair[ 12 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], | |
11523 | mcu1_fsr2_cfgrx_entest, mcu1_fsr2_cfgrx_enrx}), | |
11524 | .mcu1_fsr2_cfgrx8 ({1'b0, 1'b0, mcu1_fsr23_cfgrx_eq[ 3 : 0 ], | |
11525 | mcu1_fsr23_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu1_fsr2_cfgrx_align, | |
11526 | mcu1_fsr23_cfgrx_term[ 2 : 0 ], mcu1_fsr2_cfgrx_invpair[ 13 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], | |
11527 | mcu1_fsr2_cfgrx_entest, mcu1_fsr2_cfgrx_enrx}), | |
11528 | .mcu1_fsr2_cfgtx0 ({mcu1_fsr2_cfgtx_enidl, mcu1_fsr2_cfgtx_bstx[ 0 ], mcu1_fsr23_cfgtx_enftp, | |
11529 | mcu1_fsr23_cfgtx_de[ 3 : 0 ], mcu1_fsr23_cfgtx_swing[ 2 : 0 ], mcu1_fsr23_cfgtx_cm, | |
11530 | mcu1_fsr2_cfgtx_invpair[ 0 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], mcu1_fsr2_cfgtx_entest, | |
11531 | mcu1_fsr2_cfgtx_entx}), | |
11532 | .mcu1_fsr2_cfgtx1 ({mcu1_fsr2_cfgtx_enidl, mcu1_fsr2_cfgtx_bstx[ 1 ], mcu1_fsr23_cfgtx_enftp, | |
11533 | mcu1_fsr23_cfgtx_de[ 3 : 0 ], mcu1_fsr23_cfgtx_swing[ 2 : 0 ], mcu1_fsr23_cfgtx_cm, | |
11534 | mcu1_fsr2_cfgtx_invpair[ 1 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], mcu1_fsr2_cfgtx_entest, | |
11535 | mcu1_fsr2_cfgtx_entx}), | |
11536 | .mcu1_fsr2_cfgtx2 ({mcu1_fsr2_cfgtx_enidl, mcu1_fsr2_cfgtx_bstx[ 2 ], mcu1_fsr23_cfgtx_enftp, | |
11537 | mcu1_fsr23_cfgtx_de[ 3 : 0 ], mcu1_fsr23_cfgtx_swing[ 2 : 0 ], mcu1_fsr23_cfgtx_cm, | |
11538 | mcu1_fsr2_cfgtx_invpair[ 2 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], mcu1_fsr2_cfgtx_entest, | |
11539 | mcu1_fsr2_cfgtx_entx}), | |
11540 | .mcu1_fsr2_cfgtx3 ({mcu1_fsr2_cfgtx_enidl, mcu1_fsr2_cfgtx_bstx[ 3 ], mcu1_fsr23_cfgtx_enftp, | |
11541 | mcu1_fsr23_cfgtx_de[ 3 : 0 ], mcu1_fsr23_cfgtx_swing[ 2 : 0 ], mcu1_fsr23_cfgtx_cm, | |
11542 | mcu1_fsr2_cfgtx_invpair[ 3 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], mcu1_fsr2_cfgtx_entest, | |
11543 | mcu1_fsr2_cfgtx_entx}), | |
11544 | .mcu1_fsr2_cfgtx4 ({mcu1_fsr2_cfgtx_enidl, mcu1_fsr2_cfgtx_bstx[ 4 ], mcu1_fsr23_cfgtx_enftp, | |
11545 | mcu1_fsr23_cfgtx_de[ 3 : 0 ], mcu1_fsr23_cfgtx_swing[ 2 : 0 ], mcu1_fsr23_cfgtx_cm, | |
11546 | mcu1_fsr2_cfgtx_invpair[ 4 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], mcu1_fsr2_cfgtx_entest, | |
11547 | mcu1_fsr2_cfgtx_entx}), | |
11548 | .mcu1_fsr2_cfgtx6 ({mcu1_fsr2_cfgtx_enidl, mcu1_fsr2_cfgtx_bstx[ 5 ], mcu1_fsr23_cfgtx_enftp, | |
11549 | mcu1_fsr23_cfgtx_de[ 3 : 0 ], mcu1_fsr23_cfgtx_swing[ 2 : 0 ], mcu1_fsr23_cfgtx_cm, | |
11550 | mcu1_fsr2_cfgtx_invpair[ 5 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], mcu1_fsr2_cfgtx_entest, | |
11551 | mcu1_fsr2_cfgtx_entx}), | |
11552 | .mcu1_fsr2_cfgtx7 ({mcu1_fsr2_cfgtx_enidl, mcu1_fsr2_cfgtx_bstx[ 6 ], mcu1_fsr23_cfgtx_enftp, | |
11553 | mcu1_fsr23_cfgtx_de[ 3 : 0 ], mcu1_fsr23_cfgtx_swing[ 2 : 0 ], mcu1_fsr23_cfgtx_cm, | |
11554 | mcu1_fsr2_cfgtx_invpair[ 6 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], mcu1_fsr2_cfgtx_entest, | |
11555 | mcu1_fsr2_cfgtx_entx}), | |
11556 | .mcu1_fsr2_cfgtx8 ({mcu1_fsr2_cfgtx_enidl, mcu1_fsr2_cfgtx_bstx[ 7 ], mcu1_fsr23_cfgtx_enftp, | |
11557 | mcu1_fsr23_cfgtx_de[ 3 : 0 ], mcu1_fsr23_cfgtx_swing[ 2 : 0 ], mcu1_fsr23_cfgtx_cm, | |
11558 | mcu1_fsr2_cfgtx_invpair[ 7 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], mcu1_fsr2_cfgtx_entest, | |
11559 | mcu1_fsr2_cfgtx_entx}), | |
11560 | .mcu1_fsr2_cfgtx9 ({mcu1_fsr2_cfgtx_enidl, mcu1_fsr2_cfgtx_bstx[ 8 ], mcu1_fsr23_cfgtx_enftp, | |
11561 | mcu1_fsr23_cfgtx_de[ 3 : 0 ], mcu1_fsr23_cfgtx_swing[ 2 : 0 ], mcu1_fsr23_cfgtx_cm, | |
11562 | mcu1_fsr2_cfgtx_invpair[ 8 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], mcu1_fsr2_cfgtx_entest, | |
11563 | mcu1_fsr2_cfgtx_entx}), | |
11564 | .mcu1_fsr2_cfgtx5 ({mcu1_fsr2_cfgtx_enidl, mcu1_fsr2_cfgtx_bstx[ 9 ], mcu1_fsr23_cfgtx_enftp, | |
11565 | mcu1_fsr23_cfgtx_de[ 3 : 0 ], mcu1_fsr23_cfgtx_swing[ 2 : 0 ], mcu1_fsr23_cfgtx_cm, | |
11566 | mcu1_fsr2_cfgtx_invpair[ 9 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], mcu1_fsr2_cfgtx_entest, | |
11567 | mcu1_fsr2_cfgtx_entx}), | |
11568 | .mcu1_fsr2_testcfg0 ({tcu_srd_atpgse, tcu_srd_atpgmode[ 2 : 0 ], mcu1_fsr2_testcfg[ 11 : 8 ], tcu_sbs_enbsrx, tcu_sbs_enbstx, mcu1_fsr2_testcfg[ 7 : 0 ]}), | |
11569 | .mcu1_fsr2_testcfg1 ({tcu_srd_atpgse, tcu_srd_atpgmode[ 2 : 0 ], mcu1_fsr2_testcfg[ 11 : 8 ], tcu_sbs_enbsrx, tcu_sbs_enbstx, mcu1_fsr2_testcfg[ 7 : 0 ]}), | |
11570 | .mcu1_fsr2_testcfg2 ({tcu_srd_atpgse, tcu_srd_atpgmode[ 2 : 0 ], mcu1_fsr2_testcfg[ 11 : 8 ], tcu_sbs_enbsrx, tcu_sbs_enbstx, mcu1_fsr2_testcfg[ 7 : 0 ]}), | |
11571 | .fsr2_txbclkin ({dr_gclk_c4_fsr2_2,dr_gclk_c4_fsr2_1,dr_gclk_c4_fsr2_0}), | |
11572 | .fsr2_mcu1_rxbclk ({fsr2_mcu1_rxbclk[ 11 : 8 ],fsr2_mcu1_rxbclk[ 12 ],fsr2_mcu1_rxbclk[ 13 ],fsr2_mcu1_rxbclk[ 7 : 0 ]}), | |
11573 | .fsr2_rxbclkin ({fsr2_mcu1_rxbclk[ 11 : 8 ],fsr2_mcu1_rxbclk[ 12 ],fsr2_mcu1_rxbclk[ 13 ],fsr2_mcu1_rxbclk[ 7 : 0 ]}), | |
11574 | .fsr2_bsinitclk ({tcu_sbs_bsinitclk, tcu_sbs_bsinitclk, tcu_sbs_bsinitclk}), | |
11575 | .fsr2_fclk ({efu_mcu_fclk, efu_mcu_fclk, efu_mcu_fclk}), | |
11576 | .fsr2_fclrz ({efu_mcu_fclrz, efu_mcu_fclrz, efu_mcu_fclrz}), | |
11577 | .fsr2_fdi ({fsr1_fdo[ 0 ],fsr2_fdo[ 2 : 1 ]}), | |
11578 | .fsr2_fdo (fsr2_fdo[ 2 : 0 ]), | |
11579 | .fsr2_stcicfg ({tcu_stcicfg[ 1 : 0 ], tcu_stcicfg[ 1 : 0 ], tcu_stcicfg[ 1 : 0 ]}), | |
11580 | .fsr2_stciclk ({tcu_stciclk, tcu_stciclk, tcu_stciclk}), | |
11581 | .fsr2_stcid ({fsr2_stciq[ 1 : 0 ],fsr1_stciq[ 2 ]}), | |
11582 | .fsr2_stciq (fsr2_stciq[ 2 : 0 ]), | |
11583 | .fsr2_testclkr ({mio_fsr_testclkr[ 2 ], mio_fsr_testclkr[ 2 ], mio_fsr_testclkr[ 2 ]}), | |
11584 | .fsr2_testclkt ({mio_fsr_testclkt[ 2 ], mio_fsr_testclkt[ 2 ], mio_fsr_testclkt[ 2 ]}), | |
11585 | .mcu1_fsr3_td0 (mcu1_fsr3_data[ 11 : 0 ]), | |
11586 | .mcu1_fsr3_td1 (mcu1_fsr3_data[ 23 : 12 ]), | |
11587 | .mcu1_fsr3_td2 (mcu1_fsr3_data[ 35 : 24 ]), | |
11588 | .mcu1_fsr3_td3 (mcu1_fsr3_data[ 47 : 36 ]), | |
11589 | .mcu1_fsr3_td4 (mcu1_fsr3_data[ 59 : 48 ]), | |
11590 | .mcu1_fsr3_td6 (mcu1_fsr3_data[ 71 : 60 ]), | |
11591 | .mcu1_fsr3_td7 (mcu1_fsr3_data[ 83 : 72 ]), | |
11592 | .mcu1_fsr3_td8 (mcu1_fsr3_data[ 95 : 84 ]), | |
11593 | .mcu1_fsr3_td9 (mcu1_fsr3_data[ 107 : 96 ]), | |
11594 | .mcu1_fsr3_td5 (mcu1_fsr3_data[ 119 : 108 ]), | |
11595 | .fsr3_mcu1_rd0 (fsr3_mcu1_data[ 11 : 0 ]), | |
11596 | .fsr3_mcu1_rd1 (fsr3_mcu1_data[ 23 : 12 ]), | |
11597 | .fsr3_mcu1_rd2 (fsr3_mcu1_data[ 35 : 24 ]), | |
11598 | .fsr3_mcu1_rd3 (fsr3_mcu1_data[ 47 : 36 ]), | |
11599 | .fsr3_mcu1_rd4 (fsr3_mcu1_data[ 59 : 48 ]), | |
11600 | .fsr3_mcu1_rd5 (fsr3_mcu1_data[ 71 : 60 ]), | |
11601 | .fsr3_mcu1_rd6 (fsr3_mcu1_data[ 83 : 72 ]), | |
11602 | .fsr3_mcu1_rd7 (fsr3_mcu1_data[ 95 : 84 ]), | |
11603 | .fsr3_mcu1_rd10 (fsr3_mcu1_data[ 107 : 96 ]), | |
11604 | .fsr3_mcu1_rd11 (fsr3_mcu1_data[ 119 : 108 ]), | |
11605 | .fsr3_mcu1_rd12 (fsr3_mcu1_data[ 131 : 120 ]), | |
11606 | .fsr3_mcu1_rd13 (fsr3_mcu1_data[ 143 : 132 ]), | |
11607 | .fsr3_mcu1_rd9 (fsr3_mcu1_data[ 155 : 144 ]), | |
11608 | .fsr3_mcu1_rd8 (fsr3_mcu1_data[ 167 : 156 ]), | |
11609 | .mcu1_fsr3_cfgpll0 ({mcu1_fsr23_cfgpll_lb[ 1 : 0 ], mcu1_fsr23_cfgpll_mpy[ 3 : 0 ], mcu1_fsr3_cfgpll_enpll}), | |
11610 | .mcu1_fsr3_cfgpll1 ({mcu1_fsr23_cfgpll_lb[ 1 : 0 ], mcu1_fsr23_cfgpll_mpy[ 3 : 0 ], mcu1_fsr3_cfgpll_enpll}), | |
11611 | .mcu1_fsr3_cfgpll2 ({mcu1_fsr23_cfgpll_lb[ 1 : 0 ], mcu1_fsr23_cfgpll_mpy[ 3 : 0 ], mcu1_fsr3_cfgpll_enpll}), | |
11612 | .mcu1_fsr3_cfgrx0 ({1'b0, 1'b0, mcu1_fsr23_cfgrx_eq[ 3 : 0 ], | |
11613 | mcu1_fsr23_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu1_fsr3_cfgrx_align, | |
11614 | mcu1_fsr23_cfgrx_term[ 2 : 0 ], mcu1_fsr3_cfgrx_invpair[ 0 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], | |
11615 | mcu1_fsr3_cfgrx_entest, mcu1_fsr3_cfgrx_enrx}), | |
11616 | .mcu1_fsr3_cfgrx1 ({1'b0, 1'b0, mcu1_fsr23_cfgrx_eq[ 3 : 0 ], | |
11617 | mcu1_fsr23_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu1_fsr3_cfgrx_align, | |
11618 | mcu1_fsr23_cfgrx_term[ 2 : 0 ], mcu1_fsr3_cfgrx_invpair[ 1 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], | |
11619 | mcu1_fsr3_cfgrx_entest, mcu1_fsr3_cfgrx_enrx}), | |
11620 | .mcu1_fsr3_cfgrx2 ({1'b0, 1'b0, mcu1_fsr23_cfgrx_eq[ 3 : 0 ], | |
11621 | mcu1_fsr23_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu1_fsr3_cfgrx_align, | |
11622 | mcu1_fsr23_cfgrx_term[ 2 : 0 ], mcu1_fsr3_cfgrx_invpair[ 2 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], | |
11623 | mcu1_fsr3_cfgrx_entest, mcu1_fsr3_cfgrx_enrx}), | |
11624 | .mcu1_fsr3_cfgrx3 ({1'b0, 1'b0, mcu1_fsr23_cfgrx_eq[ 3 : 0 ], | |
11625 | mcu1_fsr23_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu1_fsr3_cfgrx_align, | |
11626 | mcu1_fsr23_cfgrx_term[ 2 : 0 ], mcu1_fsr3_cfgrx_invpair[ 3 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], | |
11627 | mcu1_fsr3_cfgrx_entest, mcu1_fsr3_cfgrx_enrx}), | |
11628 | .mcu1_fsr3_cfgrx4 ({1'b0, 1'b0, mcu1_fsr23_cfgrx_eq[ 3 : 0 ], | |
11629 | mcu1_fsr23_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu1_fsr3_cfgrx_align, | |
11630 | mcu1_fsr23_cfgrx_term[ 2 : 0 ], mcu1_fsr3_cfgrx_invpair[ 4 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], | |
11631 | mcu1_fsr3_cfgrx_entest, mcu1_fsr3_cfgrx_enrx}), | |
11632 | .mcu1_fsr3_cfgrx5 ({1'b0, 1'b0, mcu1_fsr23_cfgrx_eq[ 3 : 0 ], | |
11633 | mcu1_fsr23_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu1_fsr3_cfgrx_align, | |
11634 | mcu1_fsr23_cfgrx_term[ 2 : 0 ], mcu1_fsr3_cfgrx_invpair[ 5 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], | |
11635 | mcu1_fsr3_cfgrx_entest, mcu1_fsr3_cfgrx_enrx}), | |
11636 | .mcu1_fsr3_cfgrx6 ({1'b0, 1'b0, mcu1_fsr23_cfgrx_eq[ 3 : 0 ], | |
11637 | mcu1_fsr23_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu1_fsr3_cfgrx_align, | |
11638 | mcu1_fsr23_cfgrx_term[ 2 : 0 ], mcu1_fsr3_cfgrx_invpair[ 6 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], | |
11639 | mcu1_fsr3_cfgrx_entest, mcu1_fsr3_cfgrx_enrx}), | |
11640 | .mcu1_fsr3_cfgrx7 ({1'b0, 1'b0, mcu1_fsr23_cfgrx_eq[ 3 : 0 ], | |
11641 | mcu1_fsr23_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu1_fsr3_cfgrx_align, | |
11642 | mcu1_fsr23_cfgrx_term[ 2 : 0 ], mcu1_fsr3_cfgrx_invpair[ 7 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], | |
11643 | mcu1_fsr3_cfgrx_entest, mcu1_fsr3_cfgrx_enrx}), | |
11644 | .mcu1_fsr3_cfgrx10 ({1'b0, 1'b0, mcu1_fsr23_cfgrx_eq[ 3 : 0 ], | |
11645 | mcu1_fsr23_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu1_fsr3_cfgrx_align, | |
11646 | mcu1_fsr23_cfgrx_term[ 2 : 0 ], mcu1_fsr3_cfgrx_invpair[ 8 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], | |
11647 | mcu1_fsr3_cfgrx_entest, mcu1_fsr3_cfgrx_enrx}), | |
11648 | .mcu1_fsr3_cfgrx11 ({1'b0, 1'b0, mcu1_fsr23_cfgrx_eq[ 3 : 0 ], | |
11649 | mcu1_fsr23_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu1_fsr3_cfgrx_align, | |
11650 | mcu1_fsr23_cfgrx_term[ 2 : 0 ], mcu1_fsr3_cfgrx_invpair[ 9 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], | |
11651 | mcu1_fsr3_cfgrx_entest, mcu1_fsr3_cfgrx_enrx}), | |
11652 | .mcu1_fsr3_cfgrx12 ({1'b0, 1'b0, mcu1_fsr23_cfgrx_eq[ 3 : 0 ], | |
11653 | mcu1_fsr23_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu1_fsr3_cfgrx_align, | |
11654 | mcu1_fsr23_cfgrx_term[ 2 : 0 ], mcu1_fsr3_cfgrx_invpair[ 10 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], | |
11655 | mcu1_fsr3_cfgrx_entest, mcu1_fsr3_cfgrx_enrx}), | |
11656 | .mcu1_fsr3_cfgrx13 ({1'b0, 1'b0, mcu1_fsr23_cfgrx_eq[ 3 : 0 ], | |
11657 | mcu1_fsr23_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu1_fsr3_cfgrx_align, | |
11658 | mcu1_fsr23_cfgrx_term[ 2 : 0 ], mcu1_fsr3_cfgrx_invpair[ 11 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], | |
11659 | mcu1_fsr3_cfgrx_entest, mcu1_fsr3_cfgrx_enrx}), | |
11660 | .mcu1_fsr3_cfgrx9 ({1'b0, 1'b0, mcu1_fsr23_cfgrx_eq[ 3 : 0 ], | |
11661 | mcu1_fsr23_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu1_fsr3_cfgrx_align, | |
11662 | mcu1_fsr23_cfgrx_term[ 2 : 0 ], mcu1_fsr3_cfgrx_invpair[ 12 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], | |
11663 | mcu1_fsr3_cfgrx_entest, mcu1_fsr3_cfgrx_enrx}), | |
11664 | .mcu1_fsr3_cfgrx8 ({1'b0, 1'b0, mcu1_fsr23_cfgrx_eq[ 3 : 0 ], | |
11665 | mcu1_fsr23_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu1_fsr3_cfgrx_align, | |
11666 | mcu1_fsr23_cfgrx_term[ 2 : 0 ], mcu1_fsr3_cfgrx_invpair[ 13 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], | |
11667 | mcu1_fsr3_cfgrx_entest, mcu1_fsr3_cfgrx_enrx}), | |
11668 | .mcu1_fsr3_cfgtx0 ({mcu1_fsr3_cfgtx_enidl, mcu1_fsr3_cfgtx_bstx[ 0 ], mcu1_fsr23_cfgtx_enftp, | |
11669 | mcu1_fsr23_cfgtx_de[ 3 : 0 ], mcu1_fsr23_cfgtx_swing[ 2 : 0 ], mcu1_fsr23_cfgtx_cm, | |
11670 | mcu1_fsr3_cfgtx_invpair[ 0 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], mcu1_fsr3_cfgtx_entest, | |
11671 | mcu1_fsr3_cfgtx_entx}), | |
11672 | .mcu1_fsr3_cfgtx1 ({mcu1_fsr3_cfgtx_enidl, mcu1_fsr3_cfgtx_bstx[ 1 ], mcu1_fsr23_cfgtx_enftp, | |
11673 | mcu1_fsr23_cfgtx_de[ 3 : 0 ], mcu1_fsr23_cfgtx_swing[ 2 : 0 ], mcu1_fsr23_cfgtx_cm, | |
11674 | mcu1_fsr3_cfgtx_invpair[ 1 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], mcu1_fsr3_cfgtx_entest, | |
11675 | mcu1_fsr3_cfgtx_entx}), | |
11676 | .mcu1_fsr3_cfgtx2 ({mcu1_fsr3_cfgtx_enidl, mcu1_fsr3_cfgtx_bstx[ 2 ], mcu1_fsr23_cfgtx_enftp, | |
11677 | mcu1_fsr23_cfgtx_de[ 3 : 0 ], mcu1_fsr23_cfgtx_swing[ 2 : 0 ], mcu1_fsr23_cfgtx_cm, | |
11678 | mcu1_fsr3_cfgtx_invpair[ 2 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], mcu1_fsr3_cfgtx_entest, | |
11679 | mcu1_fsr3_cfgtx_entx}), | |
11680 | .mcu1_fsr3_cfgtx3 ({mcu1_fsr3_cfgtx_enidl, mcu1_fsr3_cfgtx_bstx[ 3 ], mcu1_fsr23_cfgtx_enftp, | |
11681 | mcu1_fsr23_cfgtx_de[ 3 : 0 ], mcu1_fsr23_cfgtx_swing[ 2 : 0 ], mcu1_fsr23_cfgtx_cm, | |
11682 | mcu1_fsr3_cfgtx_invpair[ 3 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], mcu1_fsr3_cfgtx_entest, | |
11683 | mcu1_fsr3_cfgtx_entx}), | |
11684 | .mcu1_fsr3_cfgtx4 ({mcu1_fsr3_cfgtx_enidl, mcu1_fsr3_cfgtx_bstx[ 4 ], mcu1_fsr23_cfgtx_enftp, | |
11685 | mcu1_fsr23_cfgtx_de[ 3 : 0 ], mcu1_fsr23_cfgtx_swing[ 2 : 0 ], mcu1_fsr23_cfgtx_cm, | |
11686 | mcu1_fsr3_cfgtx_invpair[ 4 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], mcu1_fsr3_cfgtx_entest, | |
11687 | mcu1_fsr3_cfgtx_entx}), | |
11688 | .mcu1_fsr3_cfgtx6 ({mcu1_fsr3_cfgtx_enidl, mcu1_fsr3_cfgtx_bstx[ 5 ], mcu1_fsr23_cfgtx_enftp, | |
11689 | mcu1_fsr23_cfgtx_de[ 3 : 0 ], mcu1_fsr23_cfgtx_swing[ 2 : 0 ], mcu1_fsr23_cfgtx_cm, | |
11690 | mcu1_fsr3_cfgtx_invpair[ 5 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], mcu1_fsr3_cfgtx_entest, | |
11691 | mcu1_fsr3_cfgtx_entx}), | |
11692 | .mcu1_fsr3_cfgtx7 ({mcu1_fsr3_cfgtx_enidl, mcu1_fsr3_cfgtx_bstx[ 6 ], mcu1_fsr23_cfgtx_enftp, | |
11693 | mcu1_fsr23_cfgtx_de[ 3 : 0 ], mcu1_fsr23_cfgtx_swing[ 2 : 0 ], mcu1_fsr23_cfgtx_cm, | |
11694 | mcu1_fsr3_cfgtx_invpair[ 6 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], mcu1_fsr3_cfgtx_entest, | |
11695 | mcu1_fsr3_cfgtx_entx}), | |
11696 | .mcu1_fsr3_cfgtx8 ({mcu1_fsr3_cfgtx_enidl, mcu1_fsr3_cfgtx_bstx[ 7 ], mcu1_fsr23_cfgtx_enftp, | |
11697 | mcu1_fsr23_cfgtx_de[ 3 : 0 ], mcu1_fsr23_cfgtx_swing[ 2 : 0 ], mcu1_fsr23_cfgtx_cm, | |
11698 | mcu1_fsr3_cfgtx_invpair[ 7 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], mcu1_fsr3_cfgtx_entest, | |
11699 | mcu1_fsr3_cfgtx_entx}), | |
11700 | .mcu1_fsr3_cfgtx9 ({mcu1_fsr3_cfgtx_enidl, mcu1_fsr3_cfgtx_bstx[ 8 ], mcu1_fsr23_cfgtx_enftp, | |
11701 | mcu1_fsr23_cfgtx_de[ 3 : 0 ], mcu1_fsr23_cfgtx_swing[ 2 : 0 ], mcu1_fsr23_cfgtx_cm, | |
11702 | mcu1_fsr3_cfgtx_invpair[ 8 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], mcu1_fsr3_cfgtx_entest, | |
11703 | mcu1_fsr3_cfgtx_entx}), | |
11704 | .mcu1_fsr3_cfgtx5 ({mcu1_fsr3_cfgtx_enidl, mcu1_fsr3_cfgtx_bstx[ 9 ], mcu1_fsr23_cfgtx_enftp, | |
11705 | mcu1_fsr23_cfgtx_de[ 3 : 0 ], mcu1_fsr23_cfgtx_swing[ 2 : 0 ], mcu1_fsr23_cfgtx_cm, | |
11706 | mcu1_fsr3_cfgtx_invpair[ 9 ], mcu1_fsr23_cfgrtx_rate[ 1 : 0 ], mcu1_fsr3_cfgtx_entest, | |
11707 | mcu1_fsr3_cfgtx_entx}), | |
11708 | .mcu1_fsr3_testcfg0 ({tcu_srd_atpgse, tcu_srd_atpgmode[ 2 : 0 ], mcu1_fsr3_testcfg[ 11 : 8 ], tcu_sbs_enbsrx, tcu_sbs_enbstx, mcu1_fsr3_testcfg[ 7 : 0 ]}), | |
11709 | .mcu1_fsr3_testcfg1 ({tcu_srd_atpgse, tcu_srd_atpgmode[ 2 : 0 ], mcu1_fsr3_testcfg[ 11 : 8 ], tcu_sbs_enbsrx, tcu_sbs_enbstx, mcu1_fsr3_testcfg[ 7 : 0 ]}), | |
11710 | .mcu1_fsr3_testcfg2 ({tcu_srd_atpgse, tcu_srd_atpgmode[ 2 : 0 ], mcu1_fsr3_testcfg[ 11 : 8 ], tcu_sbs_enbsrx, tcu_sbs_enbstx, mcu1_fsr3_testcfg[ 7 : 0 ]}), | |
11711 | .fsr3_txbclkin ({dr_gclk_c4_fsr3_2,dr_gclk_c4_fsr3_1,dr_gclk_c4_fsr3_0}), | |
11712 | .fsr3_mcu1_rxbclk ({fsr3_mcu1_rxbclk[ 11 : 8 ],fsr3_mcu1_rxbclk[ 12 ],fsr3_mcu1_rxbclk[ 13 ],fsr3_mcu1_rxbclk[ 7 : 0 ]}), | |
11713 | .fsr3_rxbclkin ({fsr3_mcu1_rxbclk[ 11 : 8 ],fsr3_mcu1_rxbclk[ 12 ],fsr3_mcu1_rxbclk[ 13 ],fsr3_mcu1_rxbclk[ 7 : 0 ]}), | |
11714 | .fsr3_bsinitclk ({tcu_sbs_bsinitclk, tcu_sbs_bsinitclk, tcu_sbs_bsinitclk}), | |
11715 | .fsr3_fclk ({efu_mcu_fclk, efu_mcu_fclk, efu_mcu_fclk}), | |
11716 | .fsr3_fclrz ({efu_mcu_fclrz, efu_mcu_fclrz, efu_mcu_fclrz}), | |
11717 | .fsr3_fdi ({fsr2_fdo[ 0 ],fsr3_fdo[ 2 : 1 ]}), | |
11718 | .fsr3_fdo (fsr3_fdo[ 2 : 0 ]), | |
11719 | .fsr3_stcicfg ({tcu_stcicfg[ 1 : 0 ], tcu_stcicfg[ 1 : 0 ], tcu_stcicfg[ 1 : 0 ]}), | |
11720 | .fsr3_stciclk ({tcu_stciclk, tcu_stciclk, tcu_stciclk}), | |
11721 | .fsr3_stcid ({fsr3_stciq[ 1 : 0 ],fsr2_stciq[ 2 ]}), | |
11722 | .fsr3_stciq (fsr3_stciq[ 2 : 0 ]), | |
11723 | .fsr3_testclkr ({mio_fsr_testclkr[ 3 ], mio_fsr_testclkr[ 3 ], mio_fsr_testclkr[ 3 ]}), | |
11724 | .fsr3_testclkt ({mio_fsr_testclkt[ 3 ], mio_fsr_testclkt[ 3 ], mio_fsr_testclkt[ 3 ]}), | |
11725 | .fsr_left_atpgd (tcu_srd_atpgd), | |
11726 | .fsr_left_atpgq (fsr_left_atpgq), | |
11727 | .VDDA (VDDA_FSRL), | |
11728 | .VDDD (VDDD_FSRL), | |
11729 | .VDDR (VDDR_FSRL), | |
11730 | .VDDT (VDDT_FSRL), | |
11731 | .VSSA (VSSA_FSRL), | |
11732 | .fsr0_mcu0_ststx_testfail(fsr0_mcu0_ststx_testfail[9:0]), | |
11733 | .fsr0_mcu0_stspll_lock(fsr0_mcu0_stspll_lock[2:0]), | |
11734 | .fsr0_mcu0_stsrx_testfail(fsr0_mcu0_stsrx_testfail[13:0]), | |
11735 | .fsr0_mcu0_stsrx_sync(fsr0_mcu0_stsrx_sync[13:0]), | |
11736 | .fsr0_mcu0_stsrx_losdtct(fsr0_mcu0_stsrx_losdtct[13:0]), | |
11737 | .fsr0_mcu0_stsrx_bsrxp(fsr0_mcu0_stsrx_bsrxp[13:0]), | |
11738 | .fsr0_mcu0_stsrx_bsrxn(fsr0_mcu0_stsrx_bsrxn[13:0]), | |
11739 | .FBDIMM0A_AMUX(FBDIMM0A_AMUX[2:0]), | |
11740 | .fsr1_mcu0_ststx_testfail(fsr1_mcu0_ststx_testfail[9:0]), | |
11741 | .fsr1_mcu0_stspll_lock(fsr1_mcu0_stspll_lock[2:0]), | |
11742 | .fsr1_mcu0_stsrx_testfail(fsr1_mcu0_stsrx_testfail[13:0]), | |
11743 | .fsr1_mcu0_stsrx_sync(fsr1_mcu0_stsrx_sync[13:0]), | |
11744 | .fsr1_mcu0_stsrx_losdtct(fsr1_mcu0_stsrx_losdtct[13:0]), | |
11745 | .fsr1_mcu0_stsrx_bsrxp(fsr1_mcu0_stsrx_bsrxp[13:0]), | |
11746 | .fsr1_mcu0_stsrx_bsrxn(fsr1_mcu0_stsrx_bsrxn[13:0]), | |
11747 | .FBDIMM0B_AMUX(FBDIMM0B_AMUX[2:0]), | |
11748 | .fsr2_mcu1_ststx_testfail(fsr2_mcu1_ststx_testfail[9:0]), | |
11749 | .fsr2_mcu1_stspll_lock(fsr2_mcu1_stspll_lock[2:0]), | |
11750 | .fsr2_mcu1_stsrx_testfail(fsr2_mcu1_stsrx_testfail[13:0]), | |
11751 | .fsr2_mcu1_stsrx_sync(fsr2_mcu1_stsrx_sync[13:0]), | |
11752 | .fsr2_mcu1_stsrx_losdtct(fsr2_mcu1_stsrx_losdtct[13:0]), | |
11753 | .fsr2_mcu1_stsrx_bsrxp(fsr2_mcu1_stsrx_bsrxp[13:0]), | |
11754 | .fsr2_mcu1_stsrx_bsrxn(fsr2_mcu1_stsrx_bsrxn[13:0]), | |
11755 | .FBDIMM1A_AMUX(FBDIMM1A_AMUX[2:0]), | |
11756 | .fsr3_mcu1_ststx_testfail(fsr3_mcu1_ststx_testfail[9:0]), | |
11757 | .fsr3_mcu1_stspll_lock(fsr3_mcu1_stspll_lock[2:0]), | |
11758 | .fsr3_mcu1_stsrx_testfail(fsr3_mcu1_stsrx_testfail[13:0]), | |
11759 | .fsr3_mcu1_stsrx_sync(fsr3_mcu1_stsrx_sync[13:0]), | |
11760 | .fsr3_mcu1_stsrx_losdtct(fsr3_mcu1_stsrx_losdtct[13:0]), | |
11761 | .fsr3_mcu1_stsrx_bsrxp(fsr3_mcu1_stsrx_bsrxp[13:0]), | |
11762 | .fsr3_mcu1_stsrx_bsrxn(fsr3_mcu1_stsrx_bsrxn[13:0]), | |
11763 | .FBDIMM1B_AMUX(FBDIMM1B_AMUX[2:0]), | |
11764 | .FBDIMM1_REFCLK_N(FBDIMM1_REFCLK_N), | |
11765 | .FBDIMM1_REFCLK_P(FBDIMM1_REFCLK_P) | |
11766 | ); | |
11767 | `endif // OPENSPARC_CMP | |
11768 | ||
11769 | //________________________________________________________________ | |
11770 | ||
11771 | // leave this instance out of cmp model | |
11772 | `ifdef OPENSPARC_CMP | |
11773 | `else | |
11774 | fsr_right fsr_right ( | |
11775 | .FBDIMM2A_RX_P ({FBDIMM2A_RX_P[ 0 ], FBDIMM2A_RX_P[ 1 ], FBDIMM2A_RX_P[ 2 ], FBDIMM2A_RX_P[ 3 ], | |
11776 | FBDIMM2A_RX_P[ 13 : 12 ], FBDIMM2A_RX_P[ 4 ], FBDIMM2A_RX_P[ 5 ], FBDIMM2A_RX_P[ 6 ], | |
11777 | FBDIMM2A_RX_P[ 7 ], FBDIMM2A_RX_P[ 8 ], FBDIMM2A_RX_P[ 9 ], FBDIMM2A_RX_P[ 10 ], | |
11778 | FBDIMM2A_RX_P[ 11 ]}), | |
11779 | .FBDIMM2A_RX_N ({FBDIMM2A_RX_N[ 0 ], FBDIMM2A_RX_N[ 1 ], FBDIMM2A_RX_N[ 2 ], FBDIMM2A_RX_N[ 3 ], | |
11780 | FBDIMM2A_RX_N[ 13 : 12 ], FBDIMM2A_RX_N[ 4 ], FBDIMM2A_RX_N[ 5 ], FBDIMM2A_RX_N[ 6 ], | |
11781 | FBDIMM2A_RX_N[ 7 ], FBDIMM2A_RX_N[ 8 ], FBDIMM2A_RX_N[ 9 ], FBDIMM2A_RX_N[ 10 ], | |
11782 | FBDIMM2A_RX_N[ 11 ]}), | |
11783 | .FBDIMM2A_TX_P ({FBDIMM2A_TX_P[ 0 ], FBDIMM2A_TX_P[ 1 ], FBDIMM2A_TX_P[ 2 ], FBDIMM2A_TX_P[ 3 ], | |
11784 | FBDIMM2A_TX_P[ 4 ], FBDIMM2A_TX_P[ 9 ], FBDIMM2A_TX_P[ 5 ], FBDIMM2A_TX_P[ 6 ], | |
11785 | FBDIMM2A_TX_P[ 7 ], FBDIMM2A_TX_P[ 8 ]}), | |
11786 | .FBDIMM2A_TX_N ({FBDIMM2A_TX_N[ 0 ], FBDIMM2A_TX_N[ 1 ], FBDIMM2A_TX_N[ 2 ], FBDIMM2A_TX_N[ 3 ], | |
11787 | FBDIMM2A_TX_N[ 4 ], FBDIMM2A_TX_N[ 9 ], FBDIMM2A_TX_N[ 5 ], FBDIMM2A_TX_N[ 6 ], | |
11788 | FBDIMM2A_TX_N[ 7 ], FBDIMM2A_TX_N[ 8 ]}), | |
11789 | .FBDIMM2B_RX_P ({FBDIMM2B_RX_P[ 0 ], FBDIMM2B_RX_P[ 1 ], FBDIMM2B_RX_P[ 2 ], FBDIMM2B_RX_P[ 3 ], | |
11790 | FBDIMM2B_RX_P[ 13 : 12 ], FBDIMM2B_RX_P[ 4 ], FBDIMM2B_RX_P[ 5 ], FBDIMM2B_RX_P[ 6 ], | |
11791 | FBDIMM2B_RX_P[ 7 ],FBDIMM2B_RX_P[ 8 ],FBDIMM2B_RX_P[ 9 ],FBDIMM2B_RX_P[ 10 ], | |
11792 | FBDIMM2B_RX_P[ 11 ]}), | |
11793 | .FBDIMM2B_RX_N ({FBDIMM2B_RX_N[ 0 ], FBDIMM2B_RX_N[ 1 ], FBDIMM2B_RX_N[ 2 ], FBDIMM2B_RX_N[ 3 ], | |
11794 | FBDIMM2B_RX_N[ 13 : 12 ], FBDIMM2B_RX_N[ 4 ], FBDIMM2B_RX_N[ 5 ], FBDIMM2B_RX_N[ 6 ], | |
11795 | FBDIMM2B_RX_N[ 7 ],FBDIMM2B_RX_N[ 8 ],FBDIMM2B_RX_N[ 9 ],FBDIMM2B_RX_N[ 10 ], | |
11796 | FBDIMM2B_RX_N[ 11 ]}), | |
11797 | .FBDIMM2B_TX_P ({FBDIMM2B_TX_P[ 0 ], FBDIMM2B_TX_P[ 1 ], FBDIMM2B_TX_P[ 2 ], FBDIMM2B_TX_P[ 3 ], | |
11798 | FBDIMM2B_TX_P[ 4 ], FBDIMM2B_TX_P[ 9 ], FBDIMM2B_TX_P[ 5 ], FBDIMM2B_TX_P[ 6 ], | |
11799 | FBDIMM2B_TX_P[ 7 ], FBDIMM2B_TX_P[ 8 ]}), | |
11800 | .FBDIMM2B_TX_N ({FBDIMM2B_TX_N[ 0 ], FBDIMM2B_TX_N[ 1 ], FBDIMM2B_TX_N[ 2 ], FBDIMM2B_TX_N[ 3 ], | |
11801 | FBDIMM2B_TX_N[ 4 ], FBDIMM2B_TX_N[ 9 ], FBDIMM2B_TX_N[ 5 ], FBDIMM2B_TX_N[ 6 ], | |
11802 | FBDIMM2B_TX_N[ 7 ], FBDIMM2B_TX_N[ 8 ]}), | |
11803 | .FBDIMM3A_RX_P ({FBDIMM3A_RX_P[ 0 ], FBDIMM3A_RX_P[ 1 ], FBDIMM3A_RX_P[ 2 ], FBDIMM3A_RX_P[ 3 ], | |
11804 | FBDIMM3A_RX_P[ 13 : 12 ], FBDIMM3A_RX_P[ 4 ], FBDIMM3A_RX_P[ 5 ], FBDIMM3A_RX_P[ 6 ], | |
11805 | FBDIMM3A_RX_P[ 7 ],FBDIMM3A_RX_P[ 8 ],FBDIMM3A_RX_P[ 9 ],FBDIMM3A_RX_P[ 10 ], | |
11806 | FBDIMM3A_RX_P[ 11 ]}), | |
11807 | .FBDIMM3A_RX_N ({FBDIMM3A_RX_N[ 0 ], FBDIMM3A_RX_N[ 1 ], FBDIMM3A_RX_N[ 2 ], FBDIMM3A_RX_N[ 3 ], | |
11808 | FBDIMM3A_RX_N[ 13 : 12 ], FBDIMM3A_RX_N[ 4 ], FBDIMM3A_RX_N[ 5 ], FBDIMM3A_RX_N[ 6 ], | |
11809 | FBDIMM3A_RX_N[ 7 ],FBDIMM3A_RX_N[ 8 ],FBDIMM3A_RX_N[ 9 ],FBDIMM3A_RX_N[ 10 ], | |
11810 | FBDIMM3A_RX_N[ 11 ]}), | |
11811 | .FBDIMM3A_TX_P ({FBDIMM3A_TX_P[ 0 ], FBDIMM3A_TX_P[ 1 ], FBDIMM3A_TX_P[ 2 ], FBDIMM3A_TX_P[ 3 ], | |
11812 | FBDIMM3A_TX_P[ 4 ], FBDIMM3A_TX_P[ 9 ], FBDIMM3A_TX_P[ 5 ], FBDIMM3A_TX_P[ 6 ], | |
11813 | FBDIMM3A_TX_P[ 7 ], FBDIMM3A_TX_P[ 8 ]}), | |
11814 | .FBDIMM3A_TX_N ({FBDIMM3A_TX_N[ 0 ], FBDIMM3A_TX_N[ 1 ], FBDIMM3A_TX_N[ 2 ], FBDIMM3A_TX_N[ 3 ], | |
11815 | FBDIMM3A_TX_N[ 4 ], FBDIMM3A_TX_N[ 9 ], FBDIMM3A_TX_N[ 5 ], FBDIMM3A_TX_N[ 6 ], | |
11816 | FBDIMM3A_TX_N[ 7 ], FBDIMM3A_TX_N[ 8 ]}), | |
11817 | .mcu2_fsr4_td9 (mcu2_fsr4_data[ 11 : 0 ]), | |
11818 | .mcu2_fsr4_td8 (mcu2_fsr4_data[ 23 : 12 ]), | |
11819 | .mcu2_fsr4_td7 (mcu2_fsr4_data[ 35 : 24 ]), | |
11820 | .mcu2_fsr4_td6 (mcu2_fsr4_data[ 47 : 36 ]), | |
11821 | .mcu2_fsr4_td5 (mcu2_fsr4_data[ 59 : 48 ]), | |
11822 | .mcu2_fsr4_td3 (mcu2_fsr4_data[ 71 : 60 ]), | |
11823 | .mcu2_fsr4_td2 (mcu2_fsr4_data[ 83 : 72 ]), | |
11824 | .mcu2_fsr4_td1 (mcu2_fsr4_data[ 95 : 84 ]), | |
11825 | .mcu2_fsr4_td0 (mcu2_fsr4_data[ 107 : 96 ]), | |
11826 | .mcu2_fsr4_td4 (mcu2_fsr4_data[ 119 : 108 ]), | |
11827 | .fsr4_mcu2_rd13 (fsr4_mcu2_data[ 11 : 0 ]), | |
11828 | .fsr4_mcu2_rd12 (fsr4_mcu2_data[ 23 : 12 ]), | |
11829 | .fsr4_mcu2_rd11 (fsr4_mcu2_data[ 35 : 24 ]), | |
11830 | .fsr4_mcu2_rd10 (fsr4_mcu2_data[ 47 : 36 ]), | |
11831 | .fsr4_mcu2_rd7 (fsr4_mcu2_data[ 59 : 48 ]), | |
11832 | .fsr4_mcu2_rd6 (fsr4_mcu2_data[ 71 : 60 ]), | |
11833 | .fsr4_mcu2_rd5 (fsr4_mcu2_data[ 83 : 72 ]), | |
11834 | .fsr4_mcu2_rd4 (fsr4_mcu2_data[ 95 : 84 ]), | |
11835 | .fsr4_mcu2_rd3 (fsr4_mcu2_data[ 107 : 96 ]), | |
11836 | .fsr4_mcu2_rd2 (fsr4_mcu2_data[ 119 : 108 ]), | |
11837 | .fsr4_mcu2_rd1 (fsr4_mcu2_data[ 131 : 120 ]), | |
11838 | .fsr4_mcu2_rd0 (fsr4_mcu2_data[ 143 : 132 ]), | |
11839 | .fsr4_mcu2_rd8 (fsr4_mcu2_data[ 155 : 144 ]), | |
11840 | .fsr4_mcu2_rd9 (fsr4_mcu2_data[ 167 : 156 ]), | |
11841 | .mcu2_fsr4_cfgpll0 ({mcu2_fsr45_cfgpll_lb[ 1 : 0 ], mcu2_fsr45_cfgpll_mpy[ 3 : 0 ], mcu2_fsr4_cfgpll_enpll}), | |
11842 | .mcu2_fsr4_cfgpll1 ({mcu2_fsr45_cfgpll_lb[ 1 : 0 ], mcu2_fsr45_cfgpll_mpy[ 3 : 0 ], mcu2_fsr4_cfgpll_enpll}), | |
11843 | .mcu2_fsr4_cfgpll2 ({mcu2_fsr45_cfgpll_lb[ 1 : 0 ], mcu2_fsr45_cfgpll_mpy[ 3 : 0 ], mcu2_fsr4_cfgpll_enpll}), | |
11844 | .mcu2_fsr4_cfgrx13 ({1'b0, 1'b0, mcu2_fsr45_cfgrx_eq[ 3 : 0 ], | |
11845 | mcu2_fsr45_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu2_fsr4_cfgrx_align, | |
11846 | mcu2_fsr45_cfgrx_term[ 2 : 0 ], mcu2_fsr4_cfgrx_invpair[ 0 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], | |
11847 | mcu2_fsr4_cfgrx_entest, mcu2_fsr4_cfgrx_enrx}), | |
11848 | .mcu2_fsr4_cfgrx12 ({1'b0, 1'b0, mcu2_fsr45_cfgrx_eq[ 3 : 0 ], | |
11849 | mcu2_fsr45_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu2_fsr4_cfgrx_align, | |
11850 | mcu2_fsr45_cfgrx_term[ 2 : 0 ], mcu2_fsr4_cfgrx_invpair[ 1 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], | |
11851 | mcu2_fsr4_cfgrx_entest, mcu2_fsr4_cfgrx_enrx}), | |
11852 | .mcu2_fsr4_cfgrx11 ({1'b0, 1'b0, mcu2_fsr45_cfgrx_eq[ 3 : 0 ], | |
11853 | mcu2_fsr45_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu2_fsr4_cfgrx_align, | |
11854 | mcu2_fsr45_cfgrx_term[ 2 : 0 ], mcu2_fsr4_cfgrx_invpair[ 2 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], | |
11855 | mcu2_fsr4_cfgrx_entest, mcu2_fsr4_cfgrx_enrx}), | |
11856 | .mcu2_fsr4_cfgrx10 ({1'b0, 1'b0, mcu2_fsr45_cfgrx_eq[ 3 : 0 ], | |
11857 | mcu2_fsr45_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu2_fsr4_cfgrx_align, | |
11858 | mcu2_fsr45_cfgrx_term[ 2 : 0 ], mcu2_fsr4_cfgrx_invpair[ 3 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], | |
11859 | mcu2_fsr4_cfgrx_entest, mcu2_fsr4_cfgrx_enrx}), | |
11860 | .mcu2_fsr4_cfgrx7 ({1'b0, 1'b0, mcu2_fsr45_cfgrx_eq[ 3 : 0 ], | |
11861 | mcu2_fsr45_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu2_fsr4_cfgrx_align, | |
11862 | mcu2_fsr45_cfgrx_term[ 2 : 0 ], mcu2_fsr4_cfgrx_invpair[ 4 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], | |
11863 | mcu2_fsr4_cfgrx_entest, mcu2_fsr4_cfgrx_enrx}), | |
11864 | .mcu2_fsr4_cfgrx6 ({1'b0, 1'b0, mcu2_fsr45_cfgrx_eq[ 3 : 0 ], | |
11865 | mcu2_fsr45_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu2_fsr4_cfgrx_align, | |
11866 | mcu2_fsr45_cfgrx_term[ 2 : 0 ], mcu2_fsr4_cfgrx_invpair[ 5 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], | |
11867 | mcu2_fsr4_cfgrx_entest, mcu2_fsr4_cfgrx_enrx}), | |
11868 | .mcu2_fsr4_cfgrx5 ({1'b0, 1'b0, mcu2_fsr45_cfgrx_eq[ 3 : 0 ], | |
11869 | mcu2_fsr45_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu2_fsr4_cfgrx_align, | |
11870 | mcu2_fsr45_cfgrx_term[ 2 : 0 ], mcu2_fsr4_cfgrx_invpair[ 6 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], | |
11871 | mcu2_fsr4_cfgrx_entest, mcu2_fsr4_cfgrx_enrx}), | |
11872 | .mcu2_fsr4_cfgrx4 ({1'b0, 1'b0, mcu2_fsr45_cfgrx_eq[ 3 : 0 ], | |
11873 | mcu2_fsr45_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu2_fsr4_cfgrx_align, | |
11874 | mcu2_fsr45_cfgrx_term[ 2 : 0 ], mcu2_fsr4_cfgrx_invpair[ 7 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], | |
11875 | mcu2_fsr4_cfgrx_entest, mcu2_fsr4_cfgrx_enrx}), | |
11876 | .mcu2_fsr4_cfgrx3 ({1'b0, 1'b0, mcu2_fsr45_cfgrx_eq[ 3 : 0 ], | |
11877 | mcu2_fsr45_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu2_fsr4_cfgrx_align, | |
11878 | mcu2_fsr45_cfgrx_term[ 2 : 0 ], mcu2_fsr4_cfgrx_invpair[ 8 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], | |
11879 | mcu2_fsr4_cfgrx_entest, mcu2_fsr4_cfgrx_enrx}), | |
11880 | .mcu2_fsr4_cfgrx2 ({1'b0, 1'b0, mcu2_fsr45_cfgrx_eq[ 3 : 0 ], | |
11881 | mcu2_fsr45_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu2_fsr4_cfgrx_align, | |
11882 | mcu2_fsr45_cfgrx_term[ 2 : 0 ], mcu2_fsr4_cfgrx_invpair[ 9 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], | |
11883 | mcu2_fsr4_cfgrx_entest, mcu2_fsr4_cfgrx_enrx}), | |
11884 | .mcu2_fsr4_cfgrx1 ({1'b0, 1'b0, mcu2_fsr45_cfgrx_eq[ 3 : 0 ], | |
11885 | mcu2_fsr45_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu2_fsr4_cfgrx_align, | |
11886 | mcu2_fsr45_cfgrx_term[ 2 : 0 ], mcu2_fsr4_cfgrx_invpair[ 10 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], | |
11887 | mcu2_fsr4_cfgrx_entest, mcu2_fsr4_cfgrx_enrx}), | |
11888 | .mcu2_fsr4_cfgrx0 ({1'b0, 1'b0, mcu2_fsr45_cfgrx_eq[ 3 : 0 ], | |
11889 | mcu2_fsr45_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu2_fsr4_cfgrx_align, | |
11890 | mcu2_fsr45_cfgrx_term[ 2 : 0 ], mcu2_fsr4_cfgrx_invpair[ 11 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], | |
11891 | mcu2_fsr4_cfgrx_entest, mcu2_fsr4_cfgrx_enrx}), | |
11892 | .mcu2_fsr4_cfgrx8 ({1'b0, 1'b0, mcu2_fsr45_cfgrx_eq[ 3 : 0 ], | |
11893 | mcu2_fsr45_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu2_fsr4_cfgrx_align, | |
11894 | mcu2_fsr45_cfgrx_term[ 2 : 0 ], mcu2_fsr4_cfgrx_invpair[ 12 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], | |
11895 | mcu2_fsr4_cfgrx_entest, mcu2_fsr4_cfgrx_enrx}), | |
11896 | .mcu2_fsr4_cfgrx9 ({1'b0, 1'b0, mcu2_fsr45_cfgrx_eq[ 3 : 0 ], | |
11897 | mcu2_fsr45_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu2_fsr4_cfgrx_align, | |
11898 | mcu2_fsr45_cfgrx_term[ 2 : 0 ], mcu2_fsr4_cfgrx_invpair[ 13 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], | |
11899 | mcu2_fsr4_cfgrx_entest, mcu2_fsr4_cfgrx_enrx}), | |
11900 | .mcu2_fsr4_cfgtx9 ({mcu2_fsr4_cfgtx_enidl, mcu2_fsr4_cfgtx_bstx[ 0 ], mcu2_fsr45_cfgtx_enftp, | |
11901 | mcu2_fsr45_cfgtx_de[ 3 : 0 ], mcu2_fsr45_cfgtx_swing[ 2 : 0 ], mcu2_fsr45_cfgtx_cm, | |
11902 | mcu2_fsr4_cfgtx_invpair[ 0 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], mcu2_fsr4_cfgtx_entest, | |
11903 | mcu2_fsr4_cfgtx_entx}), | |
11904 | .mcu2_fsr4_cfgtx8 ({mcu2_fsr4_cfgtx_enidl, mcu2_fsr4_cfgtx_bstx[ 1 ], mcu2_fsr45_cfgtx_enftp, | |
11905 | mcu2_fsr45_cfgtx_de[ 3 : 0 ], mcu2_fsr45_cfgtx_swing[ 2 : 0 ], mcu2_fsr45_cfgtx_cm, | |
11906 | mcu2_fsr4_cfgtx_invpair[ 1 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], mcu2_fsr4_cfgtx_entest, | |
11907 | mcu2_fsr4_cfgtx_entx}), | |
11908 | .mcu2_fsr4_cfgtx7 ({mcu2_fsr4_cfgtx_enidl, mcu2_fsr4_cfgtx_bstx[ 2 ], mcu2_fsr45_cfgtx_enftp, | |
11909 | mcu2_fsr45_cfgtx_de[ 3 : 0 ], mcu2_fsr45_cfgtx_swing[ 2 : 0 ], mcu2_fsr45_cfgtx_cm, | |
11910 | mcu2_fsr4_cfgtx_invpair[ 2 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], mcu2_fsr4_cfgtx_entest, | |
11911 | mcu2_fsr4_cfgtx_entx}), | |
11912 | .mcu2_fsr4_cfgtx6 ({mcu2_fsr4_cfgtx_enidl, mcu2_fsr4_cfgtx_bstx[ 3 ], mcu2_fsr45_cfgtx_enftp, | |
11913 | mcu2_fsr45_cfgtx_de[ 3 : 0 ], mcu2_fsr45_cfgtx_swing[ 2 : 0 ], mcu2_fsr45_cfgtx_cm, | |
11914 | mcu2_fsr4_cfgtx_invpair[ 3 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], mcu2_fsr4_cfgtx_entest, | |
11915 | mcu2_fsr4_cfgtx_entx}), | |
11916 | .mcu2_fsr4_cfgtx5 ({mcu2_fsr4_cfgtx_enidl, mcu2_fsr4_cfgtx_bstx[ 4 ], mcu2_fsr45_cfgtx_enftp, | |
11917 | mcu2_fsr45_cfgtx_de[ 3 : 0 ], mcu2_fsr45_cfgtx_swing[ 2 : 0 ], mcu2_fsr45_cfgtx_cm, | |
11918 | mcu2_fsr4_cfgtx_invpair[ 4 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], mcu2_fsr4_cfgtx_entest, | |
11919 | mcu2_fsr4_cfgtx_entx}), | |
11920 | .mcu2_fsr4_cfgtx3 ({mcu2_fsr4_cfgtx_enidl, mcu2_fsr4_cfgtx_bstx[ 5 ], mcu2_fsr45_cfgtx_enftp, | |
11921 | mcu2_fsr45_cfgtx_de[ 3 : 0 ], mcu2_fsr45_cfgtx_swing[ 2 : 0 ], mcu2_fsr45_cfgtx_cm, | |
11922 | mcu2_fsr4_cfgtx_invpair[ 5 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], mcu2_fsr4_cfgtx_entest, | |
11923 | mcu2_fsr4_cfgtx_entx}), | |
11924 | .mcu2_fsr4_cfgtx2 ({mcu2_fsr4_cfgtx_enidl, mcu2_fsr4_cfgtx_bstx[ 6 ], mcu2_fsr45_cfgtx_enftp, | |
11925 | mcu2_fsr45_cfgtx_de[ 3 : 0 ], mcu2_fsr45_cfgtx_swing[ 2 : 0 ], mcu2_fsr45_cfgtx_cm, | |
11926 | mcu2_fsr4_cfgtx_invpair[ 6 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], mcu2_fsr4_cfgtx_entest, | |
11927 | mcu2_fsr4_cfgtx_entx}), | |
11928 | .mcu2_fsr4_cfgtx1 ({mcu2_fsr4_cfgtx_enidl, mcu2_fsr4_cfgtx_bstx[ 7 ], mcu2_fsr45_cfgtx_enftp, | |
11929 | mcu2_fsr45_cfgtx_de[ 3 : 0 ], mcu2_fsr45_cfgtx_swing[ 2 : 0 ], mcu2_fsr45_cfgtx_cm, | |
11930 | mcu2_fsr4_cfgtx_invpair[ 7 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], mcu2_fsr4_cfgtx_entest, | |
11931 | mcu2_fsr4_cfgtx_entx}), | |
11932 | .mcu2_fsr4_cfgtx0 ({mcu2_fsr4_cfgtx_enidl, mcu2_fsr4_cfgtx_bstx[ 8 ], mcu2_fsr45_cfgtx_enftp, | |
11933 | mcu2_fsr45_cfgtx_de[ 3 : 0 ], mcu2_fsr45_cfgtx_swing[ 2 : 0 ], mcu2_fsr45_cfgtx_cm, | |
11934 | mcu2_fsr4_cfgtx_invpair[ 8 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], mcu2_fsr4_cfgtx_entest, | |
11935 | mcu2_fsr4_cfgtx_entx}), | |
11936 | .mcu2_fsr4_cfgtx4 ({mcu2_fsr4_cfgtx_enidl, mcu2_fsr4_cfgtx_bstx[ 9 ], mcu2_fsr45_cfgtx_enftp, | |
11937 | mcu2_fsr45_cfgtx_de[ 3 : 0 ], mcu2_fsr45_cfgtx_swing[ 2 : 0 ], mcu2_fsr45_cfgtx_cm, | |
11938 | mcu2_fsr4_cfgtx_invpair[ 9 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], mcu2_fsr4_cfgtx_entest, | |
11939 | mcu2_fsr4_cfgtx_entx}), | |
11940 | .mcu2_fsr4_testcfg0 ({tcu_srd_atpgse, tcu_srd_atpgmode[ 2 : 0 ], mcu2_fsr4_testcfg[ 11 : 8 ], tcu_sbs_enbsrx, tcu_sbs_enbstx, mcu2_fsr4_testcfg[ 7 : 0 ]}), | |
11941 | .mcu2_fsr4_testcfg1 ({tcu_srd_atpgse, tcu_srd_atpgmode[ 2 : 0 ], mcu2_fsr4_testcfg[ 11 : 8 ], tcu_sbs_enbsrx, tcu_sbs_enbstx, mcu2_fsr4_testcfg[ 7 : 0 ]}), | |
11942 | .mcu2_fsr4_testcfg2 ({tcu_srd_atpgse, tcu_srd_atpgmode[ 2 : 0 ], mcu2_fsr4_testcfg[ 11 : 8 ], tcu_sbs_enbsrx, tcu_sbs_enbstx, mcu2_fsr4_testcfg[ 7 : 0 ]}), | |
11943 | .fsr4_txbclkin ({dr_gclk_c0_fsr4_2,dr_gclk_c0_fsr4_1,dr_gclk_c0_fsr4_0}), | |
11944 | .fsr4_mcu2_rxbclk ({fsr4_mcu2_rxbclk[ 0 ], fsr4_mcu2_rxbclk[ 1 ], fsr4_mcu2_rxbclk[ 2 ], fsr4_mcu2_rxbclk[ 3 ], | |
11945 | fsr4_mcu2_rxbclk[ 13 : 12 ], fsr4_mcu2_rxbclk[ 4 ], fsr4_mcu2_rxbclk[ 5 ], fsr4_mcu2_rxbclk[ 6 ], | |
11946 | fsr4_mcu2_rxbclk[ 7 ], fsr4_mcu2_rxbclk[ 8 ], fsr4_mcu2_rxbclk[ 9 ], fsr4_mcu2_rxbclk[ 10 ], | |
11947 | fsr4_mcu2_rxbclk[ 11 ]}), | |
11948 | .fsr4_rxbclkin ({fsr4_mcu2_rxbclk[ 0 ], fsr4_mcu2_rxbclk[ 1 ], fsr4_mcu2_rxbclk[ 2 ], fsr4_mcu2_rxbclk[ 3 ], | |
11949 | fsr4_mcu2_rxbclk[ 13 : 12 ], fsr4_mcu2_rxbclk[ 4 ], fsr4_mcu2_rxbclk[ 5 ], fsr4_mcu2_rxbclk[ 6 ], | |
11950 | fsr4_mcu2_rxbclk[ 7 ], fsr4_mcu2_rxbclk[ 8 ], fsr4_mcu2_rxbclk[ 9 ], fsr4_mcu2_rxbclk[ 10 ], | |
11951 | fsr4_mcu2_rxbclk[ 11 ]}), | |
11952 | .fsr4_bsinitclk ({tcu_sbs_bsinitclk, tcu_sbs_bsinitclk, tcu_sbs_bsinitclk}), | |
11953 | .fsr4_fclk ({efu_mcu_fclk, efu_mcu_fclk, efu_mcu_fclk}), | |
11954 | .fsr4_fclrz ({efu_mcu_fclrz, efu_mcu_fclrz, efu_mcu_fclrz}), | |
11955 | .fsr4_fdi ({fsr3_fdo[ 0 ],fsr4_fdo[ 2 : 1 ]}), | |
11956 | .fsr4_fdo (fsr4_fdo[ 2 : 0 ]), | |
11957 | .fsr4_stcicfg ({tcu_stcicfg[ 1 : 0 ], tcu_stcicfg[ 1 : 0 ], tcu_stcicfg[ 1 : 0 ]}), | |
11958 | .fsr4_stciclk ({tcu_stciclk, tcu_stciclk, tcu_stciclk}), | |
11959 | .fsr4_stcid ({fsr5_stciq[ 0 ],fsr4_stciq[ 2 : 1 ]}), | |
11960 | .fsr4_stciq (fsr4_stciq[ 2 : 0 ]), | |
11961 | .fsr4_testclkr ({mio_fsr_testclkr[ 4 ], mio_fsr_testclkr[ 4 ], mio_fsr_testclkr[ 4 ]}), | |
11962 | .fsr4_testclkt ({mio_fsr_testclkt[ 4 ], mio_fsr_testclkt[ 4 ], mio_fsr_testclkt[ 4 ]}), | |
11963 | .mcu2_fsr5_td9 (mcu2_fsr5_data[ 11 : 0 ]), | |
11964 | .mcu2_fsr5_td8 (mcu2_fsr5_data[ 23 : 12 ]), | |
11965 | .mcu2_fsr5_td7 (mcu2_fsr5_data[ 35 : 24 ]), | |
11966 | .mcu2_fsr5_td6 (mcu2_fsr5_data[ 47 : 36 ]), | |
11967 | .mcu2_fsr5_td5 (mcu2_fsr5_data[ 59 : 48 ]), | |
11968 | .mcu2_fsr5_td3 (mcu2_fsr5_data[ 71 : 60 ]), | |
11969 | .mcu2_fsr5_td2 (mcu2_fsr5_data[ 83 : 72 ]), | |
11970 | .mcu2_fsr5_td1 (mcu2_fsr5_data[ 95 : 84 ]), | |
11971 | .mcu2_fsr5_td0 (mcu2_fsr5_data[ 107 : 96 ]), | |
11972 | .mcu2_fsr5_td4 (mcu2_fsr5_data[ 119 : 108 ]), | |
11973 | .fsr5_mcu2_rd13 (fsr5_mcu2_data[ 11 : 0 ]), | |
11974 | .fsr5_mcu2_rd12 (fsr5_mcu2_data[ 23 : 12 ]), | |
11975 | .fsr5_mcu2_rd11 (fsr5_mcu2_data[ 35 : 24 ]), | |
11976 | .fsr5_mcu2_rd10 (fsr5_mcu2_data[ 47 : 36 ]), | |
11977 | .fsr5_mcu2_rd7 (fsr5_mcu2_data[ 59 : 48 ]), | |
11978 | .fsr5_mcu2_rd6 (fsr5_mcu2_data[ 71 : 60 ]), | |
11979 | .fsr5_mcu2_rd5 (fsr5_mcu2_data[ 83 : 72 ]), | |
11980 | .fsr5_mcu2_rd4 (fsr5_mcu2_data[ 95 : 84 ]), | |
11981 | .fsr5_mcu2_rd3 (fsr5_mcu2_data[ 107 : 96 ]), | |
11982 | .fsr5_mcu2_rd2 (fsr5_mcu2_data[ 119 : 108 ]), | |
11983 | .fsr5_mcu2_rd1 (fsr5_mcu2_data[ 131 : 120 ]), | |
11984 | .fsr5_mcu2_rd0 (fsr5_mcu2_data[ 143 : 132 ]), | |
11985 | .fsr5_mcu2_rd8 (fsr5_mcu2_data[ 155 : 144 ]), | |
11986 | .fsr5_mcu2_rd9 (fsr5_mcu2_data[ 167 : 156 ]), | |
11987 | .mcu2_fsr5_cfgpll0 ({mcu2_fsr45_cfgpll_lb[ 1 : 0 ], mcu2_fsr45_cfgpll_mpy[ 3 : 0 ], mcu2_fsr5_cfgpll_enpll}), | |
11988 | .mcu2_fsr5_cfgpll1 ({mcu2_fsr45_cfgpll_lb[ 1 : 0 ], mcu2_fsr45_cfgpll_mpy[ 3 : 0 ], mcu2_fsr5_cfgpll_enpll}), | |
11989 | .mcu2_fsr5_cfgpll2 ({mcu2_fsr45_cfgpll_lb[ 1 : 0 ], mcu2_fsr45_cfgpll_mpy[ 3 : 0 ], mcu2_fsr5_cfgpll_enpll}), | |
11990 | .mcu2_fsr5_cfgrx13 ({1'b0, 1'b0, mcu2_fsr45_cfgrx_eq[ 3 : 0 ], | |
11991 | mcu2_fsr45_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu2_fsr5_cfgrx_align, | |
11992 | mcu2_fsr45_cfgrx_term[ 2 : 0 ], mcu2_fsr5_cfgrx_invpair[ 0 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], | |
11993 | mcu2_fsr5_cfgrx_entest, mcu2_fsr5_cfgrx_enrx}), | |
11994 | .mcu2_fsr5_cfgrx12 ({1'b0, 1'b0, mcu2_fsr45_cfgrx_eq[ 3 : 0 ], | |
11995 | mcu2_fsr45_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu2_fsr5_cfgrx_align, | |
11996 | mcu2_fsr45_cfgrx_term[ 2 : 0 ], mcu2_fsr5_cfgrx_invpair[ 1 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], | |
11997 | mcu2_fsr5_cfgrx_entest, mcu2_fsr5_cfgrx_enrx}), | |
11998 | .mcu2_fsr5_cfgrx11 ({1'b0, 1'b0, mcu2_fsr45_cfgrx_eq[ 3 : 0 ], | |
11999 | mcu2_fsr45_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu2_fsr5_cfgrx_align, | |
12000 | mcu2_fsr45_cfgrx_term[ 2 : 0 ], mcu2_fsr5_cfgrx_invpair[ 2 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], | |
12001 | mcu2_fsr5_cfgrx_entest, mcu2_fsr5_cfgrx_enrx}), | |
12002 | .mcu2_fsr5_cfgrx10 ({1'b0, 1'b0, mcu2_fsr45_cfgrx_eq[ 3 : 0 ], | |
12003 | mcu2_fsr45_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu2_fsr5_cfgrx_align, | |
12004 | mcu2_fsr45_cfgrx_term[ 2 : 0 ], mcu2_fsr5_cfgrx_invpair[ 3 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], | |
12005 | mcu2_fsr5_cfgrx_entest, mcu2_fsr5_cfgrx_enrx}), | |
12006 | .mcu2_fsr5_cfgrx7 ({1'b0, 1'b0, mcu2_fsr45_cfgrx_eq[ 3 : 0 ], | |
12007 | mcu2_fsr45_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu2_fsr5_cfgrx_align, | |
12008 | mcu2_fsr45_cfgrx_term[ 2 : 0 ], mcu2_fsr5_cfgrx_invpair[ 4 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], | |
12009 | mcu2_fsr5_cfgrx_entest, mcu2_fsr5_cfgrx_enrx}), | |
12010 | .mcu2_fsr5_cfgrx6 ({1'b0, 1'b0, mcu2_fsr45_cfgrx_eq[ 3 : 0 ], | |
12011 | mcu2_fsr45_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu2_fsr5_cfgrx_align, | |
12012 | mcu2_fsr45_cfgrx_term[ 2 : 0 ], mcu2_fsr5_cfgrx_invpair[ 5 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], | |
12013 | mcu2_fsr5_cfgrx_entest, mcu2_fsr5_cfgrx_enrx}), | |
12014 | .mcu2_fsr5_cfgrx5 ({1'b0, 1'b0, mcu2_fsr45_cfgrx_eq[ 3 : 0 ], | |
12015 | mcu2_fsr45_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu2_fsr5_cfgrx_align, | |
12016 | mcu2_fsr45_cfgrx_term[ 2 : 0 ], mcu2_fsr5_cfgrx_invpair[ 6 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], | |
12017 | mcu2_fsr5_cfgrx_entest, mcu2_fsr5_cfgrx_enrx}), | |
12018 | .mcu2_fsr5_cfgrx4 ({1'b0, 1'b0, mcu2_fsr45_cfgrx_eq[ 3 : 0 ], | |
12019 | mcu2_fsr45_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu2_fsr5_cfgrx_align, | |
12020 | mcu2_fsr45_cfgrx_term[ 2 : 0 ], mcu2_fsr5_cfgrx_invpair[ 7 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], | |
12021 | mcu2_fsr5_cfgrx_entest, mcu2_fsr5_cfgrx_enrx}), | |
12022 | .mcu2_fsr5_cfgrx3 ({1'b0, 1'b0, mcu2_fsr45_cfgrx_eq[ 3 : 0 ], | |
12023 | mcu2_fsr45_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu2_fsr5_cfgrx_align, | |
12024 | mcu2_fsr45_cfgrx_term[ 2 : 0 ], mcu2_fsr5_cfgrx_invpair[ 8 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], | |
12025 | mcu2_fsr5_cfgrx_entest, mcu2_fsr5_cfgrx_enrx}), | |
12026 | .mcu2_fsr5_cfgrx2 ({1'b0, 1'b0, mcu2_fsr45_cfgrx_eq[ 3 : 0 ], | |
12027 | mcu2_fsr45_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu2_fsr5_cfgrx_align, | |
12028 | mcu2_fsr45_cfgrx_term[ 2 : 0 ], mcu2_fsr5_cfgrx_invpair[ 9 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], | |
12029 | mcu2_fsr5_cfgrx_entest, mcu2_fsr5_cfgrx_enrx}), | |
12030 | .mcu2_fsr5_cfgrx1 ({1'b0, 1'b0, mcu2_fsr45_cfgrx_eq[ 3 : 0 ], | |
12031 | mcu2_fsr45_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu2_fsr5_cfgrx_align, | |
12032 | mcu2_fsr45_cfgrx_term[ 2 : 0 ], mcu2_fsr5_cfgrx_invpair[ 10 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], | |
12033 | mcu2_fsr5_cfgrx_entest, mcu2_fsr5_cfgrx_enrx}), | |
12034 | .mcu2_fsr5_cfgrx0 ({1'b0, 1'b0, mcu2_fsr45_cfgrx_eq[ 3 : 0 ], | |
12035 | mcu2_fsr45_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu2_fsr5_cfgrx_align, | |
12036 | mcu2_fsr45_cfgrx_term[ 2 : 0 ], mcu2_fsr5_cfgrx_invpair[ 11 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], | |
12037 | mcu2_fsr5_cfgrx_entest, mcu2_fsr5_cfgrx_enrx}), | |
12038 | .mcu2_fsr5_cfgrx8 ({1'b0, 1'b0, mcu2_fsr45_cfgrx_eq[ 3 : 0 ], | |
12039 | mcu2_fsr45_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu2_fsr5_cfgrx_align, | |
12040 | mcu2_fsr45_cfgrx_term[ 2 : 0 ], mcu2_fsr5_cfgrx_invpair[ 12 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], | |
12041 | mcu2_fsr5_cfgrx_entest, mcu2_fsr5_cfgrx_enrx}), | |
12042 | .mcu2_fsr5_cfgrx9 ({1'b0, 1'b0, mcu2_fsr45_cfgrx_eq[ 3 : 0 ], | |
12043 | mcu2_fsr45_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu2_fsr5_cfgrx_align, | |
12044 | mcu2_fsr45_cfgrx_term[ 2 : 0 ], mcu2_fsr5_cfgrx_invpair[ 13 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], | |
12045 | mcu2_fsr5_cfgrx_entest, mcu2_fsr5_cfgrx_enrx}), | |
12046 | .mcu2_fsr5_cfgtx9 ({mcu2_fsr5_cfgtx_enidl, mcu2_fsr5_cfgtx_bstx[ 0 ], mcu2_fsr45_cfgtx_enftp, | |
12047 | mcu2_fsr45_cfgtx_de[ 3 : 0 ], mcu2_fsr45_cfgtx_swing[ 2 : 0 ], mcu2_fsr45_cfgtx_cm, | |
12048 | mcu2_fsr5_cfgtx_invpair[ 0 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], mcu2_fsr5_cfgtx_entest, | |
12049 | mcu2_fsr5_cfgtx_entx}), | |
12050 | .mcu2_fsr5_cfgtx8 ({mcu2_fsr5_cfgtx_enidl, mcu2_fsr5_cfgtx_bstx[ 1 ], mcu2_fsr45_cfgtx_enftp, | |
12051 | mcu2_fsr45_cfgtx_de[ 3 : 0 ], mcu2_fsr45_cfgtx_swing[ 2 : 0 ], mcu2_fsr45_cfgtx_cm, | |
12052 | mcu2_fsr5_cfgtx_invpair[ 1 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], mcu2_fsr5_cfgtx_entest, | |
12053 | mcu2_fsr5_cfgtx_entx}), | |
12054 | .mcu2_fsr5_cfgtx7 ({mcu2_fsr5_cfgtx_enidl, mcu2_fsr5_cfgtx_bstx[ 2 ], mcu2_fsr45_cfgtx_enftp, | |
12055 | mcu2_fsr45_cfgtx_de[ 3 : 0 ], mcu2_fsr45_cfgtx_swing[ 2 : 0 ], mcu2_fsr45_cfgtx_cm, | |
12056 | mcu2_fsr5_cfgtx_invpair[ 2 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], mcu2_fsr5_cfgtx_entest, | |
12057 | mcu2_fsr5_cfgtx_entx}), | |
12058 | .mcu2_fsr5_cfgtx6 ({mcu2_fsr5_cfgtx_enidl, mcu2_fsr5_cfgtx_bstx[ 3 ], mcu2_fsr45_cfgtx_enftp, | |
12059 | mcu2_fsr45_cfgtx_de[ 3 : 0 ], mcu2_fsr45_cfgtx_swing[ 2 : 0 ], mcu2_fsr45_cfgtx_cm, | |
12060 | mcu2_fsr5_cfgtx_invpair[ 3 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], mcu2_fsr5_cfgtx_entest, | |
12061 | mcu2_fsr5_cfgtx_entx}), | |
12062 | .mcu2_fsr5_cfgtx5 ({mcu2_fsr5_cfgtx_enidl, mcu2_fsr5_cfgtx_bstx[ 4 ], mcu2_fsr45_cfgtx_enftp, | |
12063 | mcu2_fsr45_cfgtx_de[ 3 : 0 ], mcu2_fsr45_cfgtx_swing[ 2 : 0 ], mcu2_fsr45_cfgtx_cm, | |
12064 | mcu2_fsr5_cfgtx_invpair[ 4 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], mcu2_fsr5_cfgtx_entest, | |
12065 | mcu2_fsr5_cfgtx_entx}), | |
12066 | .mcu2_fsr5_cfgtx3 ({mcu2_fsr5_cfgtx_enidl, mcu2_fsr5_cfgtx_bstx[ 5 ], mcu2_fsr45_cfgtx_enftp, | |
12067 | mcu2_fsr45_cfgtx_de[ 3 : 0 ], mcu2_fsr45_cfgtx_swing[ 2 : 0 ], mcu2_fsr45_cfgtx_cm, | |
12068 | mcu2_fsr5_cfgtx_invpair[ 5 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], mcu2_fsr5_cfgtx_entest, | |
12069 | mcu2_fsr5_cfgtx_entx}), | |
12070 | .mcu2_fsr5_cfgtx2 ({mcu2_fsr5_cfgtx_enidl, mcu2_fsr5_cfgtx_bstx[ 6 ], mcu2_fsr45_cfgtx_enftp, | |
12071 | mcu2_fsr45_cfgtx_de[ 3 : 0 ], mcu2_fsr45_cfgtx_swing[ 2 : 0 ], mcu2_fsr45_cfgtx_cm, | |
12072 | mcu2_fsr5_cfgtx_invpair[ 6 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], mcu2_fsr5_cfgtx_entest, | |
12073 | mcu2_fsr5_cfgtx_entx}), | |
12074 | .mcu2_fsr5_cfgtx1 ({mcu2_fsr5_cfgtx_enidl, mcu2_fsr5_cfgtx_bstx[ 7 ], mcu2_fsr45_cfgtx_enftp, | |
12075 | mcu2_fsr45_cfgtx_de[ 3 : 0 ], mcu2_fsr45_cfgtx_swing[ 2 : 0 ], mcu2_fsr45_cfgtx_cm, | |
12076 | mcu2_fsr5_cfgtx_invpair[ 7 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], mcu2_fsr5_cfgtx_entest, | |
12077 | mcu2_fsr5_cfgtx_entx}), | |
12078 | .mcu2_fsr5_cfgtx0 ({mcu2_fsr5_cfgtx_enidl, mcu2_fsr5_cfgtx_bstx[ 8 ], mcu2_fsr45_cfgtx_enftp, | |
12079 | mcu2_fsr45_cfgtx_de[ 3 : 0 ], mcu2_fsr45_cfgtx_swing[ 2 : 0 ], mcu2_fsr45_cfgtx_cm, | |
12080 | mcu2_fsr5_cfgtx_invpair[ 8 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], mcu2_fsr5_cfgtx_entest, | |
12081 | mcu2_fsr5_cfgtx_entx}), | |
12082 | .mcu2_fsr5_cfgtx4 ({mcu2_fsr5_cfgtx_enidl, mcu2_fsr5_cfgtx_bstx[ 9 ], mcu2_fsr45_cfgtx_enftp, | |
12083 | mcu2_fsr45_cfgtx_de[ 3 : 0 ], mcu2_fsr45_cfgtx_swing[ 2 : 0 ], mcu2_fsr45_cfgtx_cm, | |
12084 | mcu2_fsr5_cfgtx_invpair[ 9 ], mcu2_fsr45_cfgrtx_rate[ 1 : 0 ], mcu2_fsr5_cfgtx_entest, | |
12085 | mcu2_fsr5_cfgtx_entx}), | |
12086 | .mcu2_fsr5_testcfg0 ({tcu_srd_atpgse, tcu_srd_atpgmode[ 2 : 0 ], mcu2_fsr5_testcfg[ 11 : 8 ], tcu_sbs_enbsrx, tcu_sbs_enbstx, mcu2_fsr5_testcfg[ 7 : 0 ]}), | |
12087 | .mcu2_fsr5_testcfg1 ({tcu_srd_atpgse, tcu_srd_atpgmode[ 2 : 0 ], mcu2_fsr5_testcfg[ 11 : 8 ], tcu_sbs_enbsrx, tcu_sbs_enbstx, mcu2_fsr5_testcfg[ 7 : 0 ]}), | |
12088 | .mcu2_fsr5_testcfg2 ({tcu_srd_atpgse, tcu_srd_atpgmode[ 2 : 0 ], mcu2_fsr5_testcfg[ 11 : 8 ], tcu_sbs_enbsrx, tcu_sbs_enbstx, mcu2_fsr5_testcfg[ 7 : 0 ]}), | |
12089 | .fsr5_txbclkin ({dr_gclk_c0_fsr5_2,dr_gclk_c0_fsr5_1,dr_gclk_c0_fsr5_0}), | |
12090 | .fsr5_mcu2_rxbclk ({fsr5_mcu2_rxbclk[ 0 ], fsr5_mcu2_rxbclk[ 1 ], fsr5_mcu2_rxbclk[ 2 ], fsr5_mcu2_rxbclk[ 3 ], | |
12091 | fsr5_mcu2_rxbclk[ 13 : 12 ], fsr5_mcu2_rxbclk[ 4 ], fsr5_mcu2_rxbclk[ 5 ], fsr5_mcu2_rxbclk[ 6 ], | |
12092 | fsr5_mcu2_rxbclk[ 7 ], fsr5_mcu2_rxbclk[ 8 ], fsr5_mcu2_rxbclk[ 9 ], fsr5_mcu2_rxbclk[ 10 ], | |
12093 | fsr5_mcu2_rxbclk[ 11 ]}), | |
12094 | .fsr5_rxbclkin ({fsr5_mcu2_rxbclk[ 0 ], fsr5_mcu2_rxbclk[ 1 ], fsr5_mcu2_rxbclk[ 2 ], fsr5_mcu2_rxbclk[ 3 ], | |
12095 | fsr5_mcu2_rxbclk[ 13 : 12 ], fsr5_mcu2_rxbclk[ 4 ], fsr5_mcu2_rxbclk[ 5 ], fsr5_mcu2_rxbclk[ 6 ], | |
12096 | fsr5_mcu2_rxbclk[ 7 ], fsr5_mcu2_rxbclk[ 8 ], fsr5_mcu2_rxbclk[ 9 ], fsr5_mcu2_rxbclk[ 10 ], | |
12097 | fsr5_mcu2_rxbclk[ 11 ]}), | |
12098 | .fsr5_bsinitclk ({tcu_sbs_bsinitclk, tcu_sbs_bsinitclk, tcu_sbs_bsinitclk}), | |
12099 | .fsr5_fclk ({efu_mcu_fclk, efu_mcu_fclk, efu_mcu_fclk}), | |
12100 | .fsr5_fclrz ({efu_mcu_fclrz, efu_mcu_fclrz, efu_mcu_fclrz}), | |
12101 | .fsr5_fdi ({fsr4_fdo[ 0 ],fsr5_fdo[ 2 : 1 ]}), | |
12102 | .fsr5_fdo (fsr5_fdo[ 2 : 0 ]), | |
12103 | .fsr5_stcicfg ({tcu_stcicfg[ 1 : 0 ], tcu_stcicfg[ 1 : 0 ], tcu_stcicfg[ 1 : 0 ]}), | |
12104 | .fsr5_stciclk ({tcu_stciclk, tcu_stciclk, tcu_stciclk}), | |
12105 | .fsr5_stcid ({fsr6_stciq[ 0 ],fsr5_stciq[ 2 : 1 ]}), | |
12106 | .fsr5_stciq (fsr5_stciq[ 2 : 0 ]), | |
12107 | .fsr5_testclkr ({mio_fsr_testclkr[ 5 ], mio_fsr_testclkr[ 5 ], mio_fsr_testclkr[ 5 ]}), | |
12108 | .fsr5_testclkt ({mio_fsr_testclkt[ 5 ], mio_fsr_testclkt[ 5 ], mio_fsr_testclkt[ 5 ]}), | |
12109 | .mcu3_fsr6_td9 (mcu3_fsr6_data[ 11 : 0 ]), | |
12110 | .mcu3_fsr6_td8 (mcu3_fsr6_data[ 23 : 12 ]), | |
12111 | .mcu3_fsr6_td7 (mcu3_fsr6_data[ 35 : 24 ]), | |
12112 | .mcu3_fsr6_td6 (mcu3_fsr6_data[ 47 : 36 ]), | |
12113 | .mcu3_fsr6_td5 (mcu3_fsr6_data[ 59 : 48 ]), | |
12114 | .mcu3_fsr6_td3 (mcu3_fsr6_data[ 71 : 60 ]), | |
12115 | .mcu3_fsr6_td2 (mcu3_fsr6_data[ 83 : 72 ]), | |
12116 | .mcu3_fsr6_td1 (mcu3_fsr6_data[ 95 : 84 ]), | |
12117 | .mcu3_fsr6_td0 (mcu3_fsr6_data[ 107 : 96 ]), | |
12118 | .mcu3_fsr6_td4 (mcu3_fsr6_data[ 119 : 108 ]), | |
12119 | .fsr6_mcu3_rd13 (fsr6_mcu3_data[ 11 : 0 ]), | |
12120 | .fsr6_mcu3_rd12 (fsr6_mcu3_data[ 23 : 12 ]), | |
12121 | .fsr6_mcu3_rd11 (fsr6_mcu3_data[ 35 : 24 ]), | |
12122 | .fsr6_mcu3_rd10 (fsr6_mcu3_data[ 47 : 36 ]), | |
12123 | .fsr6_mcu3_rd7 (fsr6_mcu3_data[ 59 : 48 ]), | |
12124 | .fsr6_mcu3_rd6 (fsr6_mcu3_data[ 71 : 60 ]), | |
12125 | .fsr6_mcu3_rd5 (fsr6_mcu3_data[ 83 : 72 ]), | |
12126 | .fsr6_mcu3_rd4 (fsr6_mcu3_data[ 95 : 84 ]), | |
12127 | .fsr6_mcu3_rd3 (fsr6_mcu3_data[ 107 : 96 ]), | |
12128 | .fsr6_mcu3_rd2 (fsr6_mcu3_data[ 119 : 108 ]), | |
12129 | .fsr6_mcu3_rd1 (fsr6_mcu3_data[ 131 : 120 ]), | |
12130 | .fsr6_mcu3_rd0 (fsr6_mcu3_data[ 143 : 132 ]), | |
12131 | .fsr6_mcu3_rd8 (fsr6_mcu3_data[ 155 : 144 ]), | |
12132 | .fsr6_mcu3_rd9 (fsr6_mcu3_data[ 167 : 156 ]), | |
12133 | .mcu3_fsr6_cfgpll0 ({mcu3_fsr67_cfgpll_lb[ 1 : 0 ], mcu3_fsr67_cfgpll_mpy[ 3 : 0 ], mcu3_fsr6_cfgpll_enpll}), | |
12134 | .mcu3_fsr6_cfgpll1 ({mcu3_fsr67_cfgpll_lb[ 1 : 0 ], mcu3_fsr67_cfgpll_mpy[ 3 : 0 ], mcu3_fsr6_cfgpll_enpll}), | |
12135 | .mcu3_fsr6_cfgpll2 ({mcu3_fsr67_cfgpll_lb[ 1 : 0 ], mcu3_fsr67_cfgpll_mpy[ 3 : 0 ], mcu3_fsr6_cfgpll_enpll}), | |
12136 | .mcu3_fsr6_cfgrx13 ({1'b0, 1'b0, mcu3_fsr67_cfgrx_eq[ 3 : 0 ], | |
12137 | mcu3_fsr67_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu3_fsr6_cfgrx_align, | |
12138 | mcu3_fsr67_cfgrx_term[ 2 : 0 ], mcu3_fsr6_cfgrx_invpair[ 0 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], | |
12139 | mcu3_fsr6_cfgrx_entest, mcu3_fsr6_cfgrx_enrx}), | |
12140 | .mcu3_fsr6_cfgrx12 ({1'b0, 1'b0, mcu3_fsr67_cfgrx_eq[ 3 : 0 ], | |
12141 | mcu3_fsr67_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu3_fsr6_cfgrx_align, | |
12142 | mcu3_fsr67_cfgrx_term[ 2 : 0 ], mcu3_fsr6_cfgrx_invpair[ 1 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], | |
12143 | mcu3_fsr6_cfgrx_entest, mcu3_fsr6_cfgrx_enrx}), | |
12144 | .mcu3_fsr6_cfgrx11 ({1'b0, 1'b0, mcu3_fsr67_cfgrx_eq[ 3 : 0 ], | |
12145 | mcu3_fsr67_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu3_fsr6_cfgrx_align, | |
12146 | mcu3_fsr67_cfgrx_term[ 2 : 0 ], mcu3_fsr6_cfgrx_invpair[ 2 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], | |
12147 | mcu3_fsr6_cfgrx_entest, mcu3_fsr6_cfgrx_enrx}), | |
12148 | .mcu3_fsr6_cfgrx10 ({1'b0, 1'b0, mcu3_fsr67_cfgrx_eq[ 3 : 0 ], | |
12149 | mcu3_fsr67_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu3_fsr6_cfgrx_align, | |
12150 | mcu3_fsr67_cfgrx_term[ 2 : 0 ], mcu3_fsr6_cfgrx_invpair[ 3 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], | |
12151 | mcu3_fsr6_cfgrx_entest, mcu3_fsr6_cfgrx_enrx}), | |
12152 | .mcu3_fsr6_cfgrx7 ({1'b0, 1'b0, mcu3_fsr67_cfgrx_eq[ 3 : 0 ], | |
12153 | mcu3_fsr67_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu3_fsr6_cfgrx_align, | |
12154 | mcu3_fsr67_cfgrx_term[ 2 : 0 ], mcu3_fsr6_cfgrx_invpair[ 4 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], | |
12155 | mcu3_fsr6_cfgrx_entest, mcu3_fsr6_cfgrx_enrx}), | |
12156 | .mcu3_fsr6_cfgrx6 ({1'b0, 1'b0, mcu3_fsr67_cfgrx_eq[ 3 : 0 ], | |
12157 | mcu3_fsr67_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu3_fsr6_cfgrx_align, | |
12158 | mcu3_fsr67_cfgrx_term[ 2 : 0 ], mcu3_fsr6_cfgrx_invpair[ 5 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], | |
12159 | mcu3_fsr6_cfgrx_entest, mcu3_fsr6_cfgrx_enrx}), | |
12160 | .mcu3_fsr6_cfgrx5 ({1'b0, 1'b0, mcu3_fsr67_cfgrx_eq[ 3 : 0 ], | |
12161 | mcu3_fsr67_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu3_fsr6_cfgrx_align, | |
12162 | mcu3_fsr67_cfgrx_term[ 2 : 0 ], mcu3_fsr6_cfgrx_invpair[ 6 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], | |
12163 | mcu3_fsr6_cfgrx_entest, mcu3_fsr6_cfgrx_enrx}), | |
12164 | .mcu3_fsr6_cfgrx4 ({1'b0, 1'b0, mcu3_fsr67_cfgrx_eq[ 3 : 0 ], | |
12165 | mcu3_fsr67_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu3_fsr6_cfgrx_align, | |
12166 | mcu3_fsr67_cfgrx_term[ 2 : 0 ], mcu3_fsr6_cfgrx_invpair[ 7 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], | |
12167 | mcu3_fsr6_cfgrx_entest, mcu3_fsr6_cfgrx_enrx}), | |
12168 | .mcu3_fsr6_cfgrx3 ({1'b0, 1'b0, mcu3_fsr67_cfgrx_eq[ 3 : 0 ], | |
12169 | mcu3_fsr67_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu3_fsr6_cfgrx_align, | |
12170 | mcu3_fsr67_cfgrx_term[ 2 : 0 ], mcu3_fsr6_cfgrx_invpair[ 8 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], | |
12171 | mcu3_fsr6_cfgrx_entest, mcu3_fsr6_cfgrx_enrx}), | |
12172 | .mcu3_fsr6_cfgrx2 ({1'b0, 1'b0, mcu3_fsr67_cfgrx_eq[ 3 : 0 ], | |
12173 | mcu3_fsr67_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu3_fsr6_cfgrx_align, | |
12174 | mcu3_fsr67_cfgrx_term[ 2 : 0 ], mcu3_fsr6_cfgrx_invpair[ 9 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], | |
12175 | mcu3_fsr6_cfgrx_entest, mcu3_fsr6_cfgrx_enrx}), | |
12176 | .mcu3_fsr6_cfgrx1 ({1'b0, 1'b0, mcu3_fsr67_cfgrx_eq[ 3 : 0 ], | |
12177 | mcu3_fsr67_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu3_fsr6_cfgrx_align, | |
12178 | mcu3_fsr67_cfgrx_term[ 2 : 0 ], mcu3_fsr6_cfgrx_invpair[ 10 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], | |
12179 | mcu3_fsr6_cfgrx_entest, mcu3_fsr6_cfgrx_enrx}), | |
12180 | .mcu3_fsr6_cfgrx0 ({1'b0, 1'b0, mcu3_fsr67_cfgrx_eq[ 3 : 0 ], | |
12181 | mcu3_fsr67_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu3_fsr6_cfgrx_align, | |
12182 | mcu3_fsr67_cfgrx_term[ 2 : 0 ], mcu3_fsr6_cfgrx_invpair[ 11 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], | |
12183 | mcu3_fsr6_cfgrx_entest, mcu3_fsr6_cfgrx_enrx}), | |
12184 | .mcu3_fsr6_cfgrx8 ({1'b0, 1'b0, mcu3_fsr67_cfgrx_eq[ 3 : 0 ], | |
12185 | mcu3_fsr67_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu3_fsr6_cfgrx_align, | |
12186 | mcu3_fsr67_cfgrx_term[ 2 : 0 ], mcu3_fsr6_cfgrx_invpair[ 12 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], | |
12187 | mcu3_fsr6_cfgrx_entest, mcu3_fsr6_cfgrx_enrx}), | |
12188 | .mcu3_fsr6_cfgrx9 ({1'b0, 1'b0, mcu3_fsr67_cfgrx_eq[ 3 : 0 ], | |
12189 | mcu3_fsr67_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu3_fsr6_cfgrx_align, | |
12190 | mcu3_fsr67_cfgrx_term[ 2 : 0 ], mcu3_fsr6_cfgrx_invpair[ 13 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], | |
12191 | mcu3_fsr6_cfgrx_entest, mcu3_fsr6_cfgrx_enrx}), | |
12192 | .mcu3_fsr6_cfgtx9 ({mcu3_fsr6_cfgtx_enidl, mcu3_fsr6_cfgtx_bstx[ 0 ], mcu3_fsr67_cfgtx_enftp, | |
12193 | mcu3_fsr67_cfgtx_de[ 3 : 0 ], mcu3_fsr67_cfgtx_swing[ 2 : 0 ], mcu3_fsr67_cfgtx_cm, | |
12194 | mcu3_fsr6_cfgtx_invpair[ 0 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], mcu3_fsr6_cfgtx_entest, | |
12195 | mcu3_fsr6_cfgtx_entx}), | |
12196 | .mcu3_fsr6_cfgtx8 ({mcu3_fsr6_cfgtx_enidl, mcu3_fsr6_cfgtx_bstx[ 1 ], mcu3_fsr67_cfgtx_enftp, | |
12197 | mcu3_fsr67_cfgtx_de[ 3 : 0 ], mcu3_fsr67_cfgtx_swing[ 2 : 0 ], mcu3_fsr67_cfgtx_cm, | |
12198 | mcu3_fsr6_cfgtx_invpair[ 1 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], mcu3_fsr6_cfgtx_entest, | |
12199 | mcu3_fsr6_cfgtx_entx}), | |
12200 | .mcu3_fsr6_cfgtx7 ({mcu3_fsr6_cfgtx_enidl, mcu3_fsr6_cfgtx_bstx[ 2 ], mcu3_fsr67_cfgtx_enftp, | |
12201 | mcu3_fsr67_cfgtx_de[ 3 : 0 ], mcu3_fsr67_cfgtx_swing[ 2 : 0 ], mcu3_fsr67_cfgtx_cm, | |
12202 | mcu3_fsr6_cfgtx_invpair[ 2 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], mcu3_fsr6_cfgtx_entest, | |
12203 | mcu3_fsr6_cfgtx_entx}), | |
12204 | .mcu3_fsr6_cfgtx6 ({mcu3_fsr6_cfgtx_enidl, mcu3_fsr6_cfgtx_bstx[ 3 ], mcu3_fsr67_cfgtx_enftp, | |
12205 | mcu3_fsr67_cfgtx_de[ 3 : 0 ], mcu3_fsr67_cfgtx_swing[ 2 : 0 ], mcu3_fsr67_cfgtx_cm, | |
12206 | mcu3_fsr6_cfgtx_invpair[ 3 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], mcu3_fsr6_cfgtx_entest, | |
12207 | mcu3_fsr6_cfgtx_entx}), | |
12208 | .mcu3_fsr6_cfgtx5 ({mcu3_fsr6_cfgtx_enidl, mcu3_fsr6_cfgtx_bstx[ 4 ], mcu3_fsr67_cfgtx_enftp, | |
12209 | mcu3_fsr67_cfgtx_de[ 3 : 0 ], mcu3_fsr67_cfgtx_swing[ 2 : 0 ], mcu3_fsr67_cfgtx_cm, | |
12210 | mcu3_fsr6_cfgtx_invpair[ 4 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], mcu3_fsr6_cfgtx_entest, | |
12211 | mcu3_fsr6_cfgtx_entx}), | |
12212 | .mcu3_fsr6_cfgtx3 ({mcu3_fsr6_cfgtx_enidl, mcu3_fsr6_cfgtx_bstx[ 5 ], mcu3_fsr67_cfgtx_enftp, | |
12213 | mcu3_fsr67_cfgtx_de[ 3 : 0 ], mcu3_fsr67_cfgtx_swing[ 2 : 0 ], mcu3_fsr67_cfgtx_cm, | |
12214 | mcu3_fsr6_cfgtx_invpair[ 5 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], mcu3_fsr6_cfgtx_entest, | |
12215 | mcu3_fsr6_cfgtx_entx}), | |
12216 | .mcu3_fsr6_cfgtx2 ({mcu3_fsr6_cfgtx_enidl, mcu3_fsr6_cfgtx_bstx[ 6 ], mcu3_fsr67_cfgtx_enftp, | |
12217 | mcu3_fsr67_cfgtx_de[ 3 : 0 ], mcu3_fsr67_cfgtx_swing[ 2 : 0 ], mcu3_fsr67_cfgtx_cm, | |
12218 | mcu3_fsr6_cfgtx_invpair[ 6 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], mcu3_fsr6_cfgtx_entest, | |
12219 | mcu3_fsr6_cfgtx_entx}), | |
12220 | .mcu3_fsr6_cfgtx1 ({mcu3_fsr6_cfgtx_enidl, mcu3_fsr6_cfgtx_bstx[ 7 ], mcu3_fsr67_cfgtx_enftp, | |
12221 | mcu3_fsr67_cfgtx_de[ 3 : 0 ], mcu3_fsr67_cfgtx_swing[ 2 : 0 ], mcu3_fsr67_cfgtx_cm, | |
12222 | mcu3_fsr6_cfgtx_invpair[ 7 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], mcu3_fsr6_cfgtx_entest, | |
12223 | mcu3_fsr6_cfgtx_entx}), | |
12224 | .mcu3_fsr6_cfgtx0 ({mcu3_fsr6_cfgtx_enidl, mcu3_fsr6_cfgtx_bstx[ 8 ], mcu3_fsr67_cfgtx_enftp, | |
12225 | mcu3_fsr67_cfgtx_de[ 3 : 0 ], mcu3_fsr67_cfgtx_swing[ 2 : 0 ], mcu3_fsr67_cfgtx_cm, | |
12226 | mcu3_fsr6_cfgtx_invpair[ 8 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], mcu3_fsr6_cfgtx_entest, | |
12227 | mcu3_fsr6_cfgtx_entx}), | |
12228 | .mcu3_fsr6_cfgtx4 ({mcu3_fsr6_cfgtx_enidl, mcu3_fsr6_cfgtx_bstx[ 9 ], mcu3_fsr67_cfgtx_enftp, | |
12229 | mcu3_fsr67_cfgtx_de[ 3 : 0 ], mcu3_fsr67_cfgtx_swing[ 2 : 0 ], mcu3_fsr67_cfgtx_cm, | |
12230 | mcu3_fsr6_cfgtx_invpair[ 9 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], mcu3_fsr6_cfgtx_entest, | |
12231 | mcu3_fsr6_cfgtx_entx}), | |
12232 | .mcu3_fsr6_testcfg0 ({tcu_srd_atpgse, tcu_srd_atpgmode[ 2 : 0 ], mcu3_fsr6_testcfg[ 11 : 8 ], tcu_sbs_enbsrx, tcu_sbs_enbstx, mcu3_fsr6_testcfg[ 7 : 0 ]}), | |
12233 | .mcu3_fsr6_testcfg1 ({tcu_srd_atpgse, tcu_srd_atpgmode[ 2 : 0 ], mcu3_fsr6_testcfg[ 11 : 8 ], tcu_sbs_enbsrx, tcu_sbs_enbstx, mcu3_fsr6_testcfg[ 7 : 0 ]}), | |
12234 | .mcu3_fsr6_testcfg2 ({tcu_srd_atpgse, tcu_srd_atpgmode[ 2 : 0 ], mcu3_fsr6_testcfg[ 11 : 8 ], tcu_sbs_enbsrx, tcu_sbs_enbstx, mcu3_fsr6_testcfg[ 7 : 0 ]}), | |
12235 | .fsr6_txbclkin ({dr_gclk_c0_fsr6_2,dr_gclk_c0_fsr6_1,dr_gclk_c0_fsr6_0}), | |
12236 | .fsr6_mcu3_rxbclk ({fsr6_mcu3_rxbclk[ 0 ], fsr6_mcu3_rxbclk[ 1 ], fsr6_mcu3_rxbclk[ 2 ], fsr6_mcu3_rxbclk[ 3 ], | |
12237 | fsr6_mcu3_rxbclk[ 13 : 12 ], fsr6_mcu3_rxbclk[ 4 ], fsr6_mcu3_rxbclk[ 5 ], fsr6_mcu3_rxbclk[ 6 ], | |
12238 | fsr6_mcu3_rxbclk[ 7 ], fsr6_mcu3_rxbclk[ 8 ], fsr6_mcu3_rxbclk[ 9 ], fsr6_mcu3_rxbclk[ 10 ], | |
12239 | fsr6_mcu3_rxbclk[ 11 ]}), | |
12240 | .fsr6_rxbclkin ({fsr6_mcu3_rxbclk[ 0 ], fsr6_mcu3_rxbclk[ 1 ], fsr6_mcu3_rxbclk[ 2 ], fsr6_mcu3_rxbclk[ 3 ], | |
12241 | fsr6_mcu3_rxbclk[ 13 : 12 ], fsr6_mcu3_rxbclk[ 4 ], fsr6_mcu3_rxbclk[ 5 ], fsr6_mcu3_rxbclk[ 6 ], | |
12242 | fsr6_mcu3_rxbclk[ 7 ], fsr6_mcu3_rxbclk[ 8 ], fsr6_mcu3_rxbclk[ 9 ], fsr6_mcu3_rxbclk[ 10 ], | |
12243 | fsr6_mcu3_rxbclk[ 11 ]}), | |
12244 | .fsr6_bsinitclk ({tcu_sbs_bsinitclk, tcu_sbs_bsinitclk, tcu_sbs_bsinitclk}), | |
12245 | .fsr6_fclk ({efu_mcu_fclk, efu_mcu_fclk, efu_mcu_fclk}), | |
12246 | .fsr6_fclrz ({efu_mcu_fclrz, efu_mcu_fclrz, efu_mcu_fclrz}), | |
12247 | .fsr6_fdi ({fsr5_fdo[ 0 ],fsr6_fdo[ 2 : 1 ]}), | |
12248 | .fsr6_fdo (fsr6_fdo[ 2 : 0 ]), | |
12249 | .fsr6_stcicfg ({tcu_stcicfg[ 1 : 0 ], tcu_stcicfg[ 1 : 0 ], tcu_stcicfg[ 1 : 0 ]}), | |
12250 | .fsr6_stciclk ({tcu_stciclk, tcu_stciclk, tcu_stciclk}), | |
12251 | .fsr6_stcid ({fsr7_stciq[ 2 ],fsr6_stciq[ 2 : 1 ]}), | |
12252 | .fsr6_stciq (fsr6_stciq[ 2 : 0 ]), | |
12253 | .fsr6_testclkr ({mio_fsr_testclkr[ 6 ], mio_fsr_testclkr[ 6 ], mio_fsr_testclkr[ 6 ]}), | |
12254 | .fsr6_testclkt ({mio_fsr_testclkt[ 6 ], mio_fsr_testclkt[ 6 ], mio_fsr_testclkt[ 6 ]}), | |
12255 | .fsr_right_atpgd (fsr_bottom_atpgq), | |
12256 | .fsr_right_atpgq (srd_tcu_atpgq), | |
12257 | .VDDA (VDDA_FSRR), | |
12258 | .VDDD (VDDD_FSRR), | |
12259 | .VDDR (VDDR_FSRR), | |
12260 | .VDDT (VDDT_FSRR), | |
12261 | .VSSA (VSSA_FSRR), | |
12262 | .fsr4_mcu2_ststx_testfail(fsr4_mcu2_ststx_testfail[9:0]), | |
12263 | .fsr4_mcu2_stspll_lock(fsr4_mcu2_stspll_lock[2:0]), | |
12264 | .fsr4_mcu2_stsrx_testfail(fsr4_mcu2_stsrx_testfail[13:0]), | |
12265 | .fsr4_mcu2_stsrx_sync(fsr4_mcu2_stsrx_sync[13:0]), | |
12266 | .fsr4_mcu2_stsrx_losdtct(fsr4_mcu2_stsrx_losdtct[13:0]), | |
12267 | .fsr4_mcu2_stsrx_bsrxp(fsr4_mcu2_stsrx_bsrxp[13:0]), | |
12268 | .fsr4_mcu2_stsrx_bsrxn(fsr4_mcu2_stsrx_bsrxn[13:0]), | |
12269 | .FBDIMM2A_AMUX(FBDIMM2A_AMUX[2:0]), | |
12270 | .fsr5_mcu2_ststx_testfail(fsr5_mcu2_ststx_testfail[9:0]), | |
12271 | .fsr5_mcu2_stspll_lock(fsr5_mcu2_stspll_lock[2:0]), | |
12272 | .fsr5_mcu2_stsrx_testfail(fsr5_mcu2_stsrx_testfail[13:0]), | |
12273 | .fsr5_mcu2_stsrx_sync(fsr5_mcu2_stsrx_sync[13:0]), | |
12274 | .fsr5_mcu2_stsrx_losdtct(fsr5_mcu2_stsrx_losdtct[13:0]), | |
12275 | .fsr5_mcu2_stsrx_bsrxp(fsr5_mcu2_stsrx_bsrxp[13:0]), | |
12276 | .fsr5_mcu2_stsrx_bsrxn(fsr5_mcu2_stsrx_bsrxn[13:0]), | |
12277 | .FBDIMM2B_AMUX(FBDIMM2B_AMUX[2:0]), | |
12278 | .fsr6_mcu3_ststx_testfail(fsr6_mcu3_ststx_testfail[9:0]), | |
12279 | .fsr6_mcu3_stspll_lock(fsr6_mcu3_stspll_lock[2:0]), | |
12280 | .fsr6_mcu3_stsrx_testfail(fsr6_mcu3_stsrx_testfail[13:0]), | |
12281 | .fsr6_mcu3_stsrx_sync(fsr6_mcu3_stsrx_sync[13:0]), | |
12282 | .fsr6_mcu3_stsrx_losdtct(fsr6_mcu3_stsrx_losdtct[13:0]), | |
12283 | .fsr6_mcu3_stsrx_bsrxp(fsr6_mcu3_stsrx_bsrxp[13:0]), | |
12284 | .fsr6_mcu3_stsrx_bsrxn(fsr6_mcu3_stsrx_bsrxn[13:0]), | |
12285 | .FBDIMM3A_AMUX(FBDIMM3A_AMUX[2:0]), | |
12286 | .FBDIMM2_REFCLK_N(FBDIMM2_REFCLK_N), | |
12287 | .FBDIMM2_REFCLK_P(FBDIMM2_REFCLK_P) | |
12288 | ); | |
12289 | `endif // OPENSPARC_CMP | |
12290 | ||
12291 | //________________________________________________________________ | |
12292 | ||
12293 | // leave this instance out of cmp model | |
12294 | `ifdef OPENSPARC_CMP | |
12295 | `else | |
12296 | fsr_bottom fsr_bottom ( | |
12297 | .FBDIMM3B_RX_P ({FBDIMM3B_RX_P[ 11 : 8 ],FBDIMM3B_RX_P[ 12 ],FBDIMM3B_RX_P[ 13 ],FBDIMM3B_RX_P[ 7 : 0 ]}), | |
12298 | .FBDIMM3B_RX_N ({FBDIMM3B_RX_N[ 11 : 8 ],FBDIMM3B_RX_N[ 12 ],FBDIMM3B_RX_N[ 13 ],FBDIMM3B_RX_N[ 7 : 0 ]}), | |
12299 | .FBDIMM3B_TX_P ({FBDIMM3B_TX_P[ 8 : 5 ],FBDIMM3B_TX_P[ 9 ],FBDIMM3B_TX_P[ 4 : 0 ]}), | |
12300 | .FBDIMM3B_TX_N ({FBDIMM3B_TX_N[ 8 : 5 ],FBDIMM3B_TX_N[ 9 ],FBDIMM3B_TX_N[ 4 : 0 ]}), | |
12301 | .mcu3_fsr7_td0 (mcu3_fsr7_data[ 11 : 0 ]), | |
12302 | .mcu3_fsr7_td1 (mcu3_fsr7_data[ 23 : 12 ]), | |
12303 | .mcu3_fsr7_td2 (mcu3_fsr7_data[ 35 : 24 ]), | |
12304 | .mcu3_fsr7_td3 (mcu3_fsr7_data[ 47 : 36 ]), | |
12305 | .mcu3_fsr7_td4 (mcu3_fsr7_data[ 59 : 48 ]), | |
12306 | .mcu3_fsr7_td6 (mcu3_fsr7_data[ 71 : 60 ]), | |
12307 | .mcu3_fsr7_td7 (mcu3_fsr7_data[ 83 : 72 ]), | |
12308 | .mcu3_fsr7_td8 (mcu3_fsr7_data[ 95 : 84 ]), | |
12309 | .mcu3_fsr7_td9 (mcu3_fsr7_data[ 107 : 96 ]), | |
12310 | .mcu3_fsr7_td5 (mcu3_fsr7_data[ 119 : 108 ]), | |
12311 | .fsr7_mcu3_rd0 (fsr7_mcu3_data[ 11 : 0 ]), | |
12312 | .fsr7_mcu3_rd1 (fsr7_mcu3_data[ 23 : 12 ]), | |
12313 | .fsr7_mcu3_rd2 (fsr7_mcu3_data[ 35 : 24 ]), | |
12314 | .fsr7_mcu3_rd3 (fsr7_mcu3_data[ 47 : 36 ]), | |
12315 | .fsr7_mcu3_rd4 (fsr7_mcu3_data[ 59 : 48 ]), | |
12316 | .fsr7_mcu3_rd5 (fsr7_mcu3_data[ 71 : 60 ]), | |
12317 | .fsr7_mcu3_rd6 (fsr7_mcu3_data[ 83 : 72 ]), | |
12318 | .fsr7_mcu3_rd7 (fsr7_mcu3_data[ 95 : 84 ]), | |
12319 | .fsr7_mcu3_rd10 (fsr7_mcu3_data[ 107 : 96 ]), | |
12320 | .fsr7_mcu3_rd11 (fsr7_mcu3_data[ 119 : 108 ]), | |
12321 | .fsr7_mcu3_rd12 (fsr7_mcu3_data[ 131 : 120 ]), | |
12322 | .fsr7_mcu3_rd13 (fsr7_mcu3_data[ 143 : 132 ]), | |
12323 | .fsr7_mcu3_rd9 (fsr7_mcu3_data[ 155 : 144 ]), | |
12324 | .fsr7_mcu3_rd8 (fsr7_mcu3_data[ 167 : 156 ]), | |
12325 | .mcu3_fsr7_cfgpll0 ({mcu3_fsr67_cfgpll_lb[ 1 : 0 ], mcu3_fsr67_cfgpll_mpy[ 3 : 0 ], mcu3_fsr7_cfgpll_enpll}), | |
12326 | .mcu3_fsr7_cfgpll1 ({mcu3_fsr67_cfgpll_lb[ 1 : 0 ], mcu3_fsr67_cfgpll_mpy[ 3 : 0 ], mcu3_fsr7_cfgpll_enpll}), | |
12327 | .mcu3_fsr7_cfgpll2 ({mcu3_fsr67_cfgpll_lb[ 1 : 0 ], mcu3_fsr67_cfgpll_mpy[ 3 : 0 ], mcu3_fsr7_cfgpll_enpll}), | |
12328 | .mcu3_fsr7_cfgrx0 ({1'b0, 1'b0, mcu3_fsr67_cfgrx_eq[ 3 : 0 ], | |
12329 | mcu3_fsr67_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu3_fsr7_cfgrx_align, | |
12330 | mcu3_fsr67_cfgrx_term[ 2 : 0 ], mcu3_fsr7_cfgrx_invpair[ 0 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], | |
12331 | mcu3_fsr7_cfgrx_entest, mcu3_fsr7_cfgrx_enrx}), | |
12332 | .mcu3_fsr7_cfgrx1 ({1'b0, 1'b0, mcu3_fsr67_cfgrx_eq[ 3 : 0 ], | |
12333 | mcu3_fsr67_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu3_fsr7_cfgrx_align, | |
12334 | mcu3_fsr67_cfgrx_term[ 2 : 0 ], mcu3_fsr7_cfgrx_invpair[ 1 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], | |
12335 | mcu3_fsr7_cfgrx_entest, mcu3_fsr7_cfgrx_enrx}), | |
12336 | .mcu3_fsr7_cfgrx2 ({1'b0, 1'b0, mcu3_fsr67_cfgrx_eq[ 3 : 0 ], | |
12337 | mcu3_fsr67_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu3_fsr7_cfgrx_align, | |
12338 | mcu3_fsr67_cfgrx_term[ 2 : 0 ], mcu3_fsr7_cfgrx_invpair[ 2 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], | |
12339 | mcu3_fsr7_cfgrx_entest, mcu3_fsr7_cfgrx_enrx}), | |
12340 | .mcu3_fsr7_cfgrx3 ({1'b0, 1'b0, mcu3_fsr67_cfgrx_eq[ 3 : 0 ], | |
12341 | mcu3_fsr67_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu3_fsr7_cfgrx_align, | |
12342 | mcu3_fsr67_cfgrx_term[ 2 : 0 ], mcu3_fsr7_cfgrx_invpair[ 3 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], | |
12343 | mcu3_fsr7_cfgrx_entest, mcu3_fsr7_cfgrx_enrx}), | |
12344 | .mcu3_fsr7_cfgrx4 ({1'b0, 1'b0, mcu3_fsr67_cfgrx_eq[ 3 : 0 ], | |
12345 | mcu3_fsr67_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu3_fsr7_cfgrx_align, | |
12346 | mcu3_fsr67_cfgrx_term[ 2 : 0 ], mcu3_fsr7_cfgrx_invpair[ 4 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], | |
12347 | mcu3_fsr7_cfgrx_entest, mcu3_fsr7_cfgrx_enrx}), | |
12348 | .mcu3_fsr7_cfgrx5 ({1'b0, 1'b0, mcu3_fsr67_cfgrx_eq[ 3 : 0 ], | |
12349 | mcu3_fsr67_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu3_fsr7_cfgrx_align, | |
12350 | mcu3_fsr67_cfgrx_term[ 2 : 0 ], mcu3_fsr7_cfgrx_invpair[ 5 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], | |
12351 | mcu3_fsr7_cfgrx_entest, mcu3_fsr7_cfgrx_enrx}), | |
12352 | .mcu3_fsr7_cfgrx6 ({1'b0, 1'b0, mcu3_fsr67_cfgrx_eq[ 3 : 0 ], | |
12353 | mcu3_fsr67_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu3_fsr7_cfgrx_align, | |
12354 | mcu3_fsr67_cfgrx_term[ 2 : 0 ], mcu3_fsr7_cfgrx_invpair[ 6 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], | |
12355 | mcu3_fsr7_cfgrx_entest, mcu3_fsr7_cfgrx_enrx}), | |
12356 | .mcu3_fsr7_cfgrx7 ({1'b0, 1'b0, mcu3_fsr67_cfgrx_eq[ 3 : 0 ], | |
12357 | mcu3_fsr67_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu3_fsr7_cfgrx_align, | |
12358 | mcu3_fsr67_cfgrx_term[ 2 : 0 ], mcu3_fsr7_cfgrx_invpair[ 7 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], | |
12359 | mcu3_fsr7_cfgrx_entest, mcu3_fsr7_cfgrx_enrx}), | |
12360 | .mcu3_fsr7_cfgrx10 ({1'b0, 1'b0, mcu3_fsr67_cfgrx_eq[ 3 : 0 ], | |
12361 | mcu3_fsr67_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu3_fsr7_cfgrx_align, | |
12362 | mcu3_fsr67_cfgrx_term[ 2 : 0 ], mcu3_fsr7_cfgrx_invpair[ 8 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], | |
12363 | mcu3_fsr7_cfgrx_entest, mcu3_fsr7_cfgrx_enrx}), | |
12364 | .mcu3_fsr7_cfgrx11 ({1'b0, 1'b0, mcu3_fsr67_cfgrx_eq[ 3 : 0 ], | |
12365 | mcu3_fsr67_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu3_fsr7_cfgrx_align, | |
12366 | mcu3_fsr67_cfgrx_term[ 2 : 0 ], mcu3_fsr7_cfgrx_invpair[ 9 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], | |
12367 | mcu3_fsr7_cfgrx_entest, mcu3_fsr7_cfgrx_enrx}), | |
12368 | .mcu3_fsr7_cfgrx12 ({1'b0, 1'b0, mcu3_fsr67_cfgrx_eq[ 3 : 0 ], | |
12369 | mcu3_fsr67_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu3_fsr7_cfgrx_align, | |
12370 | mcu3_fsr67_cfgrx_term[ 2 : 0 ], mcu3_fsr7_cfgrx_invpair[ 10 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], | |
12371 | mcu3_fsr7_cfgrx_entest, mcu3_fsr7_cfgrx_enrx}), | |
12372 | .mcu3_fsr7_cfgrx13 ({1'b0, 1'b0, mcu3_fsr67_cfgrx_eq[ 3 : 0 ], | |
12373 | mcu3_fsr67_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu3_fsr7_cfgrx_align, | |
12374 | mcu3_fsr67_cfgrx_term[ 2 : 0 ], mcu3_fsr7_cfgrx_invpair[ 11 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], | |
12375 | mcu3_fsr7_cfgrx_entest, mcu3_fsr7_cfgrx_enrx}), | |
12376 | .mcu3_fsr7_cfgrx9 ({1'b0, 1'b0, mcu3_fsr67_cfgrx_eq[ 3 : 0 ], | |
12377 | mcu3_fsr67_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu3_fsr7_cfgrx_align, | |
12378 | mcu3_fsr67_cfgrx_term[ 2 : 0 ], mcu3_fsr7_cfgrx_invpair[ 12 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], | |
12379 | mcu3_fsr7_cfgrx_entest, mcu3_fsr7_cfgrx_enrx}), | |
12380 | .mcu3_fsr7_cfgrx8 ({1'b0, 1'b0, mcu3_fsr67_cfgrx_eq[ 3 : 0 ], | |
12381 | mcu3_fsr67_cfgrx_cdr[ 2 : 0 ], 1'b0, 1'b0, mcu3_fsr7_cfgrx_align, | |
12382 | mcu3_fsr67_cfgrx_term[ 2 : 0 ], mcu3_fsr7_cfgrx_invpair[ 13 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], | |
12383 | mcu3_fsr7_cfgrx_entest, mcu3_fsr7_cfgrx_enrx}), | |
12384 | .mcu3_fsr7_cfgtx0 ({mcu3_fsr7_cfgtx_enidl, mcu3_fsr7_cfgtx_bstx[ 0 ], mcu3_fsr67_cfgtx_enftp, | |
12385 | mcu3_fsr67_cfgtx_de[ 3 : 0 ], mcu3_fsr67_cfgtx_swing[ 2 : 0 ], mcu3_fsr67_cfgtx_cm, | |
12386 | mcu3_fsr7_cfgtx_invpair[ 0 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], mcu3_fsr7_cfgtx_entest, | |
12387 | mcu3_fsr7_cfgtx_entx}), | |
12388 | .mcu3_fsr7_cfgtx1 ({mcu3_fsr7_cfgtx_enidl, mcu3_fsr7_cfgtx_bstx[ 1 ], mcu3_fsr67_cfgtx_enftp, | |
12389 | mcu3_fsr67_cfgtx_de[ 3 : 0 ], mcu3_fsr67_cfgtx_swing[ 2 : 0 ], mcu3_fsr67_cfgtx_cm, | |
12390 | mcu3_fsr7_cfgtx_invpair[ 1 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], mcu3_fsr7_cfgtx_entest, | |
12391 | mcu3_fsr7_cfgtx_entx}), | |
12392 | .mcu3_fsr7_cfgtx2 ({mcu3_fsr7_cfgtx_enidl, mcu3_fsr7_cfgtx_bstx[ 2 ], mcu3_fsr67_cfgtx_enftp, | |
12393 | mcu3_fsr67_cfgtx_de[ 3 : 0 ], mcu3_fsr67_cfgtx_swing[ 2 : 0 ], mcu3_fsr67_cfgtx_cm, | |
12394 | mcu3_fsr7_cfgtx_invpair[ 2 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], mcu3_fsr7_cfgtx_entest, | |
12395 | mcu3_fsr7_cfgtx_entx}), | |
12396 | .mcu3_fsr7_cfgtx3 ({mcu3_fsr7_cfgtx_enidl, mcu3_fsr7_cfgtx_bstx[ 3 ], mcu3_fsr67_cfgtx_enftp, | |
12397 | mcu3_fsr67_cfgtx_de[ 3 : 0 ], mcu3_fsr67_cfgtx_swing[ 2 : 0 ], mcu3_fsr67_cfgtx_cm, | |
12398 | mcu3_fsr7_cfgtx_invpair[ 3 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], mcu3_fsr7_cfgtx_entest, | |
12399 | mcu3_fsr7_cfgtx_entx}), | |
12400 | .mcu3_fsr7_cfgtx4 ({mcu3_fsr7_cfgtx_enidl, mcu3_fsr7_cfgtx_bstx[ 4 ], mcu3_fsr67_cfgtx_enftp, | |
12401 | mcu3_fsr67_cfgtx_de[ 3 : 0 ], mcu3_fsr67_cfgtx_swing[ 2 : 0 ], mcu3_fsr67_cfgtx_cm, | |
12402 | mcu3_fsr7_cfgtx_invpair[ 4 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], mcu3_fsr7_cfgtx_entest, | |
12403 | mcu3_fsr7_cfgtx_entx}), | |
12404 | .mcu3_fsr7_cfgtx6 ({mcu3_fsr7_cfgtx_enidl, mcu3_fsr7_cfgtx_bstx[ 5 ], mcu3_fsr67_cfgtx_enftp, | |
12405 | mcu3_fsr67_cfgtx_de[ 3 : 0 ], mcu3_fsr67_cfgtx_swing[ 2 : 0 ], mcu3_fsr67_cfgtx_cm, | |
12406 | mcu3_fsr7_cfgtx_invpair[ 5 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], mcu3_fsr7_cfgtx_entest, | |
12407 | mcu3_fsr7_cfgtx_entx}), | |
12408 | .mcu3_fsr7_cfgtx7 ({mcu3_fsr7_cfgtx_enidl, mcu3_fsr7_cfgtx_bstx[ 6 ], mcu3_fsr67_cfgtx_enftp, | |
12409 | mcu3_fsr67_cfgtx_de[ 3 : 0 ], mcu3_fsr67_cfgtx_swing[ 2 : 0 ], mcu3_fsr67_cfgtx_cm, | |
12410 | mcu3_fsr7_cfgtx_invpair[ 6 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], mcu3_fsr7_cfgtx_entest, | |
12411 | mcu3_fsr7_cfgtx_entx}), | |
12412 | .mcu3_fsr7_cfgtx8 ({mcu3_fsr7_cfgtx_enidl, mcu3_fsr7_cfgtx_bstx[ 7 ], mcu3_fsr67_cfgtx_enftp, | |
12413 | mcu3_fsr67_cfgtx_de[ 3 : 0 ], mcu3_fsr67_cfgtx_swing[ 2 : 0 ], mcu3_fsr67_cfgtx_cm, | |
12414 | mcu3_fsr7_cfgtx_invpair[ 7 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], mcu3_fsr7_cfgtx_entest, | |
12415 | mcu3_fsr7_cfgtx_entx}), | |
12416 | .mcu3_fsr7_cfgtx9 ({mcu3_fsr7_cfgtx_enidl, mcu3_fsr7_cfgtx_bstx[ 8 ], mcu3_fsr67_cfgtx_enftp, | |
12417 | mcu3_fsr67_cfgtx_de[ 3 : 0 ], mcu3_fsr67_cfgtx_swing[ 2 : 0 ], mcu3_fsr67_cfgtx_cm, | |
12418 | mcu3_fsr7_cfgtx_invpair[ 8 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], mcu3_fsr7_cfgtx_entest, | |
12419 | mcu3_fsr7_cfgtx_entx}), | |
12420 | .mcu3_fsr7_cfgtx5 ({mcu3_fsr7_cfgtx_enidl, mcu3_fsr7_cfgtx_bstx[ 9 ], mcu3_fsr67_cfgtx_enftp, | |
12421 | mcu3_fsr67_cfgtx_de[ 3 : 0 ], mcu3_fsr67_cfgtx_swing[ 2 : 0 ], mcu3_fsr67_cfgtx_cm, | |
12422 | mcu3_fsr7_cfgtx_invpair[ 9 ], mcu3_fsr67_cfgrtx_rate[ 1 : 0 ], mcu3_fsr7_cfgtx_entest, | |
12423 | mcu3_fsr7_cfgtx_entx}), | |
12424 | .mcu3_fsr7_testcfg0 ({tcu_srd_atpgse, tcu_srd_atpgmode[ 2 : 0 ], mcu3_fsr7_testcfg[ 11 : 8 ], tcu_sbs_enbsrx, tcu_sbs_enbstx, mcu3_fsr7_testcfg[ 7 : 0 ]}), | |
12425 | .mcu3_fsr7_testcfg1 ({tcu_srd_atpgse, tcu_srd_atpgmode[ 2 : 0 ], mcu3_fsr7_testcfg[ 11 : 8 ], tcu_sbs_enbsrx, tcu_sbs_enbstx, mcu3_fsr7_testcfg[ 7 : 0 ]}), | |
12426 | .mcu3_fsr7_testcfg2 ({tcu_srd_atpgse, tcu_srd_atpgmode[ 2 : 0 ], mcu3_fsr7_testcfg[ 11 : 8 ], tcu_sbs_enbsrx, tcu_sbs_enbstx, mcu3_fsr7_testcfg[ 7 : 0 ]}), | |
12427 | .fsr7_txbclkin ({dr_gclk_c2_fsr7_2,dr_gclk_c2_fsr7_1,dr_gclk_c2_fsr7_0}), | |
12428 | .fsr7_mcu3_rxbclk ({fsr7_mcu3_rxbclk[ 11 : 8 ],fsr7_mcu3_rxbclk[ 12 ],fsr7_mcu3_rxbclk[ 13 ],fsr7_mcu3_rxbclk[ 7 : 0 ]}), | |
12429 | .fsr7_rxbclkin ({fsr7_mcu3_rxbclk[ 11 : 8 ],fsr7_mcu3_rxbclk[ 12 ],fsr7_mcu3_rxbclk[ 13 ],fsr7_mcu3_rxbclk[ 7 : 0 ]}), | |
12430 | .fsr7_bsinitclk ({tcu_sbs_bsinitclk, tcu_sbs_bsinitclk, tcu_sbs_bsinitclk}), | |
12431 | .fsr7_fclk ({efu_mcu_fclk, efu_mcu_fclk, efu_mcu_fclk}), | |
12432 | .fsr7_fclrz ({efu_mcu_fclrz, efu_mcu_fclrz, efu_mcu_fclrz}), | |
12433 | .fsr7_fdi ({fsr6_fdo[ 0 ], fsr7_fdo[ 1 : 0 ]}), | |
12434 | .fsr7_fdo ({fsr7_fdo[ 1 : 0 ],mcu_efu_fdo}), | |
12435 | .fsr7_stcicfg ({tcu_stcicfg[ 1 : 0 ], tcu_stcicfg[ 1 : 0 ], tcu_stcicfg[ 1 : 0 ]}), | |
12436 | .fsr7_stciclk ({tcu_stciclk, tcu_stciclk, tcu_stciclk}), | |
12437 | .fsr7_stcid ({fsr7_stciq[ 1 : 0 ],esr_stciq}), | |
12438 | .fsr7_stciq (fsr7_stciq[ 2 : 0 ]), | |
12439 | .fsr7_testclkr ({mio_fsr_testclkr[ 7 ], mio_fsr_testclkr[ 7 ], mio_fsr_testclkr[ 7 ]}), | |
12440 | .fsr7_testclkt ({mio_fsr_testclkt[ 7 ], mio_fsr_testclkt[ 7 ], mio_fsr_testclkt[ 7 ]}), | |
12441 | .fsr_bottom_atpgd (esr_atpgq), | |
12442 | .fsr_bottom_atpgq (fsr_bottom_atpgq), | |
12443 | .VDDA (VDDA_FSRB), | |
12444 | .VDDD (VDDD_FSRB), | |
12445 | .VDDR (VDDR_FSRB), | |
12446 | .VDDT (VDDT_FSRB), | |
12447 | .VSSA (VSSA_FSRB), | |
12448 | .fsr7_mcu3_ststx_testfail(fsr7_mcu3_ststx_testfail[9:0]), | |
12449 | .fsr7_mcu3_stspll_lock(fsr7_mcu3_stspll_lock[2:0]), | |
12450 | .fsr7_mcu3_stsrx_testfail(fsr7_mcu3_stsrx_testfail[13:0]), | |
12451 | .fsr7_mcu3_stsrx_sync(fsr7_mcu3_stsrx_sync[13:0]), | |
12452 | .fsr7_mcu3_stsrx_losdtct(fsr7_mcu3_stsrx_losdtct[13:0]), | |
12453 | .fsr7_mcu3_stsrx_bsrxp(fsr7_mcu3_stsrx_bsrxp[13:0]), | |
12454 | .fsr7_mcu3_stsrx_bsrxn(fsr7_mcu3_stsrx_bsrxn[13:0]), | |
12455 | .FBDIMM3B_AMUX(FBDIMM3B_AMUX[2:0]), | |
12456 | .FBDIMM3_REFCLK_N(FBDIMM3_REFCLK_N), | |
12457 | .FBDIMM3_REFCLK_P(FBDIMM3_REFCLK_P) | |
12458 | ); | |
12459 | `endif // OPENSPARC_CMP | |
12460 | //________________________________________________________________ | |
12461 | ||
12462 | // leave this instance out of cmp model | |
12463 | `ifdef OPENSPARC_CMP | |
12464 | `else | |
12465 | sii sii ( | |
12466 | .gclk ( cmp_gclk_c3_sii ), // cmp_gclk_c1_r[4] ) , | |
12467 | .tcu_sii_clk_stop ( gl_sii_clk_stop ), // staged clk_stop | |
12468 | .tcu_sii_io_clk_stop ( gl_sii_io_clk_stop ), // staged clk_stop | |
12469 | .ccu_io_out ( gl_io_out_c3b0 ), // staged div phase | |
12470 | .scan_in (ccx_scan_out[ 1 ] ), | |
12471 | .scan_out (sii_scan_out ), | |
12472 | .ccu_io_cmp_sync_en (gl_io_cmp_sync_en_c3b ), | |
12473 | .ccu_cmp_io_sync_en (gl_cmp_io_sync_en_c3b ), | |
12474 | //.tcu_soc4cmp_clk_stop (tcu_sii_clk_stop ), | |
12475 | //.tcu_soc6io_clk_stop (tcu_sii_io_clk_stop ), | |
12476 | .tcu_pce_ov_in (tcu_pce_ov), | |
12477 | .tcu_sii_mbist_start({tcu_sii_mbist_start_ccxrff_1,tcu_sii_mbist_start_ccxrff_0}), | |
12478 | .tcu_sii_data(tcu_sii_data_ccxrff), | |
12479 | .tcu_sii_vld(tcu_sii_vld_ccxrff), | |
12480 | .l2t4_sii_iq_dequeue(l2t4_sii_iq_dequeue_t1lff), | |
12481 | .l2t4_sii_wib_dequeue(l2t4_sii_wib_dequeue_t1lff), | |
12482 | .l2t5_sii_iq_dequeue(l2t5_sii_iq_dequeue_t1lff), | |
12483 | .l2t5_sii_wib_dequeue(l2t5_sii_wib_dequeue_t1lff), | |
12484 | .l2t6_sii_iq_dequeue(l2t6_sii_iq_dequeue_t3lff), | |
12485 | .l2t6_sii_wib_dequeue(l2t6_sii_wib_dequeue_t3lff), | |
12486 | .l2t7_sii_iq_dequeue(l2t7_sii_iq_dequeue_t3lff), | |
12487 | .l2t7_sii_wib_dequeue(l2t7_sii_wib_dequeue_t3lff), | |
12488 | .tcu_dbr_gateoff(tcu_dbr_gateoff), | |
12489 | .tcu_atpg_mode(tcu_atpg_mode), | |
12490 | .tcu_aclk(tcu_aclk), | |
12491 | .tcu_bclk(tcu_bclk), | |
12492 | .tcu_scan_en(tcu_scan_en), | |
12493 | .tcu_muxtest(tcu_muxtest), | |
12494 | .tcu_dectest(tcu_dectest), | |
12495 | .cluster_arst_l(cluster_arst_l), | |
12496 | .tcu_div_bypass(tcu_div_bypass), | |
12497 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit), | |
12498 | .tcu_se_scancollar_in(tcu_se_scancollar_in), | |
12499 | .tcu_se_scancollar_out(tcu_se_scancollar_out), | |
12500 | .tcu_mbist_bisi_en(tcu_mbist_bisi_en), | |
12501 | .tcu_mbist_user_mode(tcu_mbist_user_mode), | |
12502 | .tcu_sii_mbist_scan_in(tcu_sii_mbist_scan_in), | |
12503 | .sii_tcu_mbist_done(sii_tcu_mbist_done[1:0]), | |
12504 | .sii_tcu_mbist_fail(sii_tcu_mbist_fail[1:0]), | |
12505 | .sii_tcu_mbist_scan_out(sii_tcu_mbist_scan_out), | |
12506 | .l2t0_sii_iq_dequeue(l2t0_sii_iq_dequeue), | |
12507 | .l2t0_sii_wib_dequeue(l2t0_sii_wib_dequeue), | |
12508 | .sii_l2t0_req_vld(sii_l2t0_req_vld), | |
12509 | .sii_l2t0_req(sii_l2t0_req[31:0]), | |
12510 | .sii_l2b0_ecc(sii_l2b0_ecc[6:0]), | |
12511 | .sii_dbg1_l2t0_req(sii_dbg1_l2t0_req[1:0]), | |
12512 | .l2t1_sii_iq_dequeue(l2t1_sii_iq_dequeue), | |
12513 | .l2t1_sii_wib_dequeue(l2t1_sii_wib_dequeue), | |
12514 | .sii_l2t1_req_vld(sii_l2t1_req_vld), | |
12515 | .sii_l2t1_req(sii_l2t1_req[31:0]), | |
12516 | .sii_l2b1_ecc(sii_l2b1_ecc[6:0]), | |
12517 | .sii_dbg1_l2t1_req(sii_dbg1_l2t1_req[1:0]), | |
12518 | .l2t2_sii_iq_dequeue(l2t2_sii_iq_dequeue), | |
12519 | .l2t2_sii_wib_dequeue(l2t2_sii_wib_dequeue), | |
12520 | .sii_l2t2_req_vld(sii_l2t2_req_vld), | |
12521 | .sii_l2t2_req(sii_l2t2_req[31:0]), | |
12522 | .sii_l2b2_ecc(sii_l2b2_ecc[6:0]), | |
12523 | .sii_dbg1_l2t2_req(sii_dbg1_l2t2_req[1:0]), | |
12524 | .l2t3_sii_iq_dequeue(l2t3_sii_iq_dequeue), | |
12525 | .l2t3_sii_wib_dequeue(l2t3_sii_wib_dequeue), | |
12526 | .sii_l2t3_req_vld(sii_l2t3_req_vld), | |
12527 | .sii_l2t3_req(sii_l2t3_req[31:0]), | |
12528 | .sii_l2b3_ecc(sii_l2b3_ecc[6:0]), | |
12529 | .sii_dbg1_l2t3_req(sii_dbg1_l2t3_req[1:0]), | |
12530 | .sii_l2t4_req_vld(sii_l2t4_req_vld), | |
12531 | .sii_l2t4_req(sii_l2t4_req[31:0]), | |
12532 | .sii_l2b4_ecc(sii_l2b4_ecc[6:0]), | |
12533 | .sii_dbg1_l2t4_req(sii_dbg1_l2t4_req[1:0]), | |
12534 | .sii_l2t5_req_vld(sii_l2t5_req_vld), | |
12535 | .sii_l2t5_req(sii_l2t5_req[31:0]), | |
12536 | .sii_l2b5_ecc(sii_l2b5_ecc[6:0]), | |
12537 | .sii_dbg1_l2t5_req(sii_dbg1_l2t5_req[1:0]), | |
12538 | .sii_l2t6_req_vld(sii_l2t6_req_vld), | |
12539 | .sii_l2t6_req(sii_l2t6_req[31:0]), | |
12540 | .sii_l2b6_ecc(sii_l2b6_ecc[6:0]), | |
12541 | .sii_dbg1_l2t6_req(sii_dbg1_l2t6_req[1:0]), | |
12542 | .sii_l2t7_req_vld(sii_l2t7_req_vld), | |
12543 | .sii_l2t7_req(sii_l2t7_req[31:0]), | |
12544 | .sii_l2b7_ecc(sii_l2b7_ecc[6:0]), | |
12545 | .sii_dbg1_l2t7_req(sii_dbg1_l2t7_req[1:0]), | |
12546 | .ncu_sii_niuctag_uei(ncu_sii_niuctag_uei), | |
12547 | .ncu_sii_niuctag_cei(ncu_sii_niuctag_cei), | |
12548 | .ncu_sii_niua_pei(ncu_sii_niua_pei), | |
12549 | .ncu_sii_niud_pei(ncu_sii_niud_pei), | |
12550 | .ncu_sii_dmuctag_uei(ncu_sii_dmuctag_uei), | |
12551 | .ncu_sii_dmuctag_cei(ncu_sii_dmuctag_cei), | |
12552 | .ncu_sii_dmua_pei(ncu_sii_dmua_pei), | |
12553 | .ncu_sii_dmud_pei(ncu_sii_dmud_pei), | |
12554 | .ncu_sii_gnt(ncu_sii_gnt), | |
12555 | .ncu_sii_pm(ncu_sii_pm), | |
12556 | .ncu_sii_ba01(ncu_sii_ba01), | |
12557 | .ncu_sii_ba23(ncu_sii_ba23), | |
12558 | .ncu_sii_ba45(ncu_sii_ba45), | |
12559 | .ncu_sii_ba67(ncu_sii_ba67), | |
12560 | .ncu_sii_l2_idx_hash_en(ncu_sii_l2_idx_hash_en), | |
12561 | .sii_ncu_niuctag_ue(sii_ncu_niuctag_ue), | |
12562 | .sii_ncu_niuctag_ce(sii_ncu_niuctag_ce), | |
12563 | .sii_ncu_niua_pe(sii_ncu_niua_pe), | |
12564 | .sii_ncu_niud_pe(sii_ncu_niud_pe), | |
12565 | .sii_ncu_dmuctag_ue(sii_ncu_dmuctag_ue), | |
12566 | .sii_ncu_dmuctag_ce(sii_ncu_dmuctag_ce), | |
12567 | .sii_ncu_dmua_pe(sii_ncu_dmua_pe), | |
12568 | .sii_ncu_dmud_pe(sii_ncu_dmud_pe), | |
12569 | .sii_ncu_syn_data(sii_ncu_syn_data[3:0]), | |
12570 | .sii_ncu_syn_vld(sii_ncu_syn_vld), | |
12571 | .sii_ncu_dparity(sii_ncu_dparity[1:0]), | |
12572 | .sii_ncu_data(sii_ncu_data[31:0]), | |
12573 | .sii_ncu_req(sii_ncu_req), | |
12574 | .niu_sii_hdr_vld(niu_sii_hdr_vld), | |
12575 | .niu_sii_reqbypass(niu_sii_reqbypass), | |
12576 | .niu_sii_datareq(niu_sii_datareq), | |
12577 | .niu_sii_data(niu_sii_data[127:0]), | |
12578 | .niu_sii_parity(niu_sii_parity[7:0]), | |
12579 | .sii_niu_oqdq(sii_niu_oqdq), | |
12580 | .sii_niu_bqdq(sii_niu_bqdq), | |
12581 | .dmu_sii_hdr_vld(dmu_sii_hdr_vld), | |
12582 | .dmu_sii_reqbypass(dmu_sii_reqbypass), | |
12583 | .dmu_sii_datareq(dmu_sii_datareq), | |
12584 | .dmu_sii_datareq16(dmu_sii_datareq16), | |
12585 | .dmu_sii_data(dmu_sii_data[127:0]), | |
12586 | .dmu_sii_parity(dmu_sii_parity[7:0]), | |
12587 | .dmu_sii_be_parity(dmu_sii_be_parity), | |
12588 | .dmu_sii_be(dmu_sii_be[15:0]), | |
12589 | .sii_dmu_wrack_vld(sii_dmu_wrack_vld), | |
12590 | .sii_dmu_wrack_tag(sii_dmu_wrack_tag[3:0]), | |
12591 | .sii_dmu_wrack_parity(sii_dmu_wrack_parity), | |
12592 | .sio_sii_opcc_ipcc_niu_by_deq(sio_sii_opcc_ipcc_niu_by_deq), | |
12593 | .sio_sii_opcc_ipcc_niu_by_cnt(sio_sii_opcc_ipcc_niu_by_cnt[3:0]), | |
12594 | .sio_sii_opcc_ipcc_niu_or_deq(sio_sii_opcc_ipcc_niu_or_deq), | |
12595 | .sio_sii_opcc_ipcc_dmu_by_deq(sio_sii_opcc_ipcc_dmu_by_deq), | |
12596 | .sio_sii_opcc_ipcc_dmu_by_cnt(sio_sii_opcc_ipcc_dmu_by_cnt[3:0]), | |
12597 | .sio_sii_opcc_ipcc_dmu_or_deq(sio_sii_opcc_ipcc_dmu_or_deq), | |
12598 | .sio_sii_olc0_ilc0_dequeue(sio_sii_olc0_ilc0_dequeue), | |
12599 | .sio_sii_olc1_ilc1_dequeue(sio_sii_olc1_ilc1_dequeue), | |
12600 | .sio_sii_olc2_ilc2_dequeue(sio_sii_olc2_ilc2_dequeue), | |
12601 | .sio_sii_olc3_ilc3_dequeue(sio_sii_olc3_ilc3_dequeue), | |
12602 | .sio_sii_olc4_ilc4_dequeue(sio_sii_olc4_ilc4_dequeue), | |
12603 | .sio_sii_olc5_ilc5_dequeue(sio_sii_olc5_ilc5_dequeue), | |
12604 | .sio_sii_olc6_ilc6_dequeue(sio_sii_olc6_ilc6_dequeue), | |
12605 | .sio_sii_olc7_ilc7_dequeue(sio_sii_olc7_ilc7_dequeue) | |
12606 | ||
12607 | ); | |
12608 | `endif // OPENSPARC_CMP | |
12609 | ||
12610 | //________________________________________________________________ | |
12611 | ||
12612 | // leave this instance out of cmp model | |
12613 | `ifdef OPENSPARC_CMP | |
12614 | `else | |
12615 | sio sio ( | |
12616 | .gclk ( cmp_gclk_c1_sio ), // cmp_gclk_c2_r[4] ) , | |
12617 | .tcu_sio_clk_stop ( gl_sio_clk_stop ), // staged clk_stop | |
12618 | .tcu_sio_io_clk_stop ( gl_sio_io_clk_stop ), // staged clk_stop | |
12619 | .ccu_io_out ( gl_io_out_c1m ), // staged div phase | |
12620 | .scan_in (mcu2_scan_out ), | |
12621 | .scan_out (sio_scan_out ), | |
12622 | .ccu_io_cmp_sync_en ( gl_io_cmp_sync_en_c1m ), | |
12623 | .ccu_cmp_io_sync_en ( gl_cmp_io_sync_en_c1m ), | |
12624 | //.tcu_soc4cmp_clk_stop (tcu_sio_clk_stop ), | |
12625 | //.tcu_soc6io_clk_stop (tcu_sio_io_clk_stop ), | |
12626 | .tcu_pce_ov_in (tcu_pce_ov), | |
12627 | .l2b0_sio_data(l2b0_sio_data_t4lff[ 31 : 0 ]), | |
12628 | .l2b0_sio_parity(l2b0_sio_parity_t5lff[ 1 : 0 ]), | |
12629 | .l2b0_sio_ctag_vld(l2b0_sio_ctag_vld_t4lff), | |
12630 | .l2b0_sio_ue_err(l2b0_sio_ue_err_t4lff), | |
12631 | .l2b1_sio_data(l2b1_sio_data_ccxlff[ 31 : 0 ]), | |
12632 | .l2b1_sio_parity(l2b1_sio_parity_ccxlff[ 1 : 0 ]), | |
12633 | .l2b1_sio_ctag_vld(l2b1_sio_ctag_vld_ccxlff), | |
12634 | .l2b1_sio_ue_err(l2b1_sio_ue_err_ccxlff), | |
12635 | .l2b2_sio_data(l2b2_sio_data_ccxlff[ 31 : 0 ]), | |
12636 | .l2b2_sio_parity(l2b2_sio_parity_ccxlff[ 1 : 0 ]), | |
12637 | .l2b2_sio_ctag_vld(l2b2_sio_ctag_vld_ccxlff), | |
12638 | .l2b2_sio_ue_err(l2b2_sio_ue_err_ccxlff), | |
12639 | .l2b3_sio_data(l2b3_sio_data_ccxlff[ 31 : 0 ]), | |
12640 | .l2b3_sio_parity(l2b3_sio_parity_ccxlff[ 1 : 0 ]), | |
12641 | .l2b3_sio_ctag_vld(l2b3_sio_ctag_vld_ccxlff), | |
12642 | .l2b3_sio_ue_err(l2b3_sio_ue_err_ccxlff), | |
12643 | .l2b4_sio_data(l2b4_sio_data_t4rff[ 31 : 0 ]), | |
12644 | .l2b4_sio_parity(l2b4_sio_parity_t4rff[ 1 : 0 ]), | |
12645 | .l2b4_sio_ctag_vld(l2b4_sio_ctag_vld_t4rff), | |
12646 | .l2b4_sio_ue_err(l2b4_sio_ue_err_t4rff), | |
12647 | .tcu_dbr_gateoff(tcu_dbr_gateoff), | |
12648 | .tcu_scan_en(tcu_scan_en), | |
12649 | .tcu_muxtest(tcu_muxtest), | |
12650 | .tcu_dectest(tcu_dectest), | |
12651 | .tcu_mbist_user_mode(tcu_mbist_user_mode), | |
12652 | .tcu_div_bypass(tcu_div_bypass), | |
12653 | .cluster_arst_l(cluster_arst_l), | |
12654 | .tcu_aclk(tcu_aclk), | |
12655 | .tcu_bclk(tcu_bclk), | |
12656 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit), | |
12657 | .tcu_atpg_mode(tcu_atpg_mode), | |
12658 | .tcu_se_scancollar_in(tcu_se_scancollar_in), | |
12659 | .tcu_se_scancollar_out(tcu_se_scancollar_out), | |
12660 | .sio_tcu_vld(sio_tcu_vld), | |
12661 | .sio_tcu_data(sio_tcu_data), | |
12662 | .tcu_sio_mbist_start(tcu_sio_mbist_start[1:0]), | |
12663 | .tcu_mbist_bisi_en(tcu_mbist_bisi_en), | |
12664 | .sio_tcu_mbist_done(sio_tcu_mbist_done[1:0]), | |
12665 | .sio_tcu_mbist_fail(sio_tcu_mbist_fail[1:0]), | |
12666 | .tcu_sio_mbist_scan_in(tcu_sio_mbist_scan_in), | |
12667 | .sio_tcu_mbist_scan_out(sio_tcu_mbist_scan_out), | |
12668 | .l2b5_sio_ctag_vld(l2b5_sio_ctag_vld), | |
12669 | .l2b5_sio_data(l2b5_sio_data[31:0]), | |
12670 | .l2b5_sio_parity(l2b5_sio_parity[1:0]), | |
12671 | .l2b5_sio_ue_err(l2b5_sio_ue_err), | |
12672 | .l2b6_sio_ctag_vld(l2b6_sio_ctag_vld), | |
12673 | .l2b6_sio_data(l2b6_sio_data[31:0]), | |
12674 | .l2b6_sio_parity(l2b6_sio_parity[1:0]), | |
12675 | .l2b6_sio_ue_err(l2b6_sio_ue_err), | |
12676 | .l2b7_sio_ctag_vld(l2b7_sio_ctag_vld), | |
12677 | .l2b7_sio_data(l2b7_sio_data[31:0]), | |
12678 | .l2b7_sio_parity(l2b7_sio_parity[1:0]), | |
12679 | .l2b7_sio_ue_err(l2b7_sio_ue_err), | |
12680 | .niu_sio_dq(niu_sio_dq), | |
12681 | .sio_niu_hdr_vld(sio_niu_hdr_vld), | |
12682 | .sio_niu_datareq(sio_niu_datareq), | |
12683 | .sio_niu_data(sio_niu_data[127:0]), | |
12684 | .sio_niu_parity(sio_niu_parity[7:0]), | |
12685 | .sio_dmu_hdr_vld(sio_dmu_hdr_vld), | |
12686 | .sio_dmu_data(sio_dmu_data[127:0]), | |
12687 | .sio_dmu_parity(sio_dmu_parity[7:0]), | |
12688 | .sio_sii_opcc_ipcc_niu_by_deq(sio_sii_opcc_ipcc_niu_by_deq), | |
12689 | .sio_sii_opcc_ipcc_niu_by_cnt(sio_sii_opcc_ipcc_niu_by_cnt[3:0]), | |
12690 | .sio_sii_opcc_ipcc_niu_or_deq(sio_sii_opcc_ipcc_niu_or_deq), | |
12691 | .sio_sii_opcc_ipcc_dmu_by_deq(sio_sii_opcc_ipcc_dmu_by_deq), | |
12692 | .sio_sii_opcc_ipcc_dmu_by_cnt(sio_sii_opcc_ipcc_dmu_by_cnt[3:0]), | |
12693 | .sio_sii_opcc_ipcc_dmu_or_deq(sio_sii_opcc_ipcc_dmu_or_deq), | |
12694 | .sio_sii_olc0_ilc0_dequeue(sio_sii_olc0_ilc0_dequeue), | |
12695 | .sio_sii_olc1_ilc1_dequeue(sio_sii_olc1_ilc1_dequeue), | |
12696 | .sio_sii_olc2_ilc2_dequeue(sio_sii_olc2_ilc2_dequeue), | |
12697 | .sio_sii_olc3_ilc3_dequeue(sio_sii_olc3_ilc3_dequeue), | |
12698 | .sio_sii_olc4_ilc4_dequeue(sio_sii_olc4_ilc4_dequeue), | |
12699 | .sio_sii_olc5_ilc5_dequeue(sio_sii_olc5_ilc5_dequeue), | |
12700 | .sio_sii_olc6_ilc6_dequeue(sio_sii_olc6_ilc6_dequeue), | |
12701 | .sio_sii_olc7_ilc7_dequeue(sio_sii_olc7_ilc7_dequeue), | |
12702 | .sio_ncu_ctag_ue(sio_ncu_ctag_ue), | |
12703 | .sio_ncu_ctag_ce(sio_ncu_ctag_ce), | |
12704 | .ncu_sio_ctag_cei(ncu_sio_ctag_cei), | |
12705 | .ncu_sio_ctag_uei(ncu_sio_ctag_uei), | |
12706 | .ncu_sio_d_pei(ncu_sio_d_pei) | |
12707 | ) ; | |
12708 | `endif // OPENSPARC_CMP | |
12709 | ||
12710 | //________________________________________________________________ | |
12711 | ||
12712 | // leave this instance out of cmp model | |
12713 | `ifdef OPENSPARC_CMP | |
12714 | `else | |
12715 | ncu ncu( | |
12716 | ||
12717 | .gclk ( cmp_gclk_c3_ncu ), // cmp_gclk_c0_r[3] ) , | |
12718 | .tcu_ncu_io_clk_stop ( gl_ncu_io_clk_stop ), // staged clk_stop | |
12719 | .tcu_ncu_clk_stop ( gl_ncu_clk_stop ), // staged clk_stop | |
12720 | .ccu_io_out ( gl_io_out_c3t ), // staged div phase | |
12721 | .ccu_io_cmp_sync_en ( gl_io_cmp_sync_en_c3t ), | |
12722 | .ccu_cmp_io_sync_en ( gl_cmp_io_sync_en_c3t ), | |
12723 | .scan_in (tcu_socg_scan_out ), | |
12724 | .scan_out (ncu_scan_out ), | |
12725 | .tcu_scan_en(tcu_scan_en), | |
12726 | .tcu_ncu_mbist_start({tcu_ncu_mbist_start[ 1 ],tcu_ncu_mbist_start_t1lff_0}), | |
12727 | .tcu_se_scancollar_in(tcu_se_scancollar_in), | |
12728 | .tcu_se_scancollar_out(tcu_se_scancollar_out), | |
12729 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit), | |
12730 | .tcu_pce_ov(tcu_pce_ov), | |
12731 | .tcu_aclk(tcu_aclk), | |
12732 | .tcu_bclk(tcu_bclk), | |
12733 | .tcu_dbr_gateoff(tcu_dbr_gateoff), | |
12734 | .ncu_tcu_mbist_done(ncu_tcu_mbist_done[1:0]), | |
12735 | .ncu_tcu_mbist_fail(ncu_tcu_mbist_fail[1:0]), | |
12736 | .tcu_ncu_mbist_scan_in(tcu_ncu_mbist_scan_in), | |
12737 | .ncu_tcu_mbist_scan_out(ncu_tcu_mbist_scan_out), | |
12738 | .tcu_mbist_user_mode(tcu_mbist_user_mode), | |
12739 | .tcu_mbist_bisi_en(tcu_mbist_bisi_en), | |
12740 | .ncu_pcx_stall_pq(ncu_pcx_stall_pq), | |
12741 | .pcx_ncu_data_px2(pcx_ncu_data_px2[129:0]), | |
12742 | .pcx_ncu_data_rdy_px1(pcx_ncu_data_rdy_px1), | |
12743 | .ncu_cpx_data_ca(ncu_cpx_data_ca[145:0]), | |
12744 | .ncu_cpx_req_cq(ncu_cpx_req_cq[7:0]), | |
12745 | .cpx_ncu_grant_cx(cpx_ncu_grant_cx[7:0]), | |
12746 | .ncu_dmu_pio_data(ncu_dmu_pio_data[63:0]), | |
12747 | .ncu_dmu_pio_hdr_vld(ncu_dmu_pio_hdr_vld), | |
12748 | .ncu_dmu_mmu_addr_vld(ncu_dmu_mmu_addr_vld), | |
12749 | .dmu_ncu_wrack_vld(dmu_ncu_wrack_vld), | |
12750 | .dmu_ncu_wrack_tag(dmu_ncu_wrack_tag[3:0]), | |
12751 | .ncu_dmu_mondo_ack(ncu_dmu_mondo_ack), | |
12752 | .ncu_dmu_mondo_nack(ncu_dmu_mondo_nack), | |
12753 | .ncu_dmu_mondo_id(ncu_dmu_mondo_id[5:0]), | |
12754 | .ncu_dmu_vld(ncu_dmu_vld), | |
12755 | .ncu_dmu_data(ncu_dmu_data[31:0]), | |
12756 | .dmu_ncu_stall(dmu_ncu_stall), | |
12757 | .dmu_ncu_vld(dmu_ncu_vld), | |
12758 | .dmu_ncu_data(dmu_ncu_data[31:0]), | |
12759 | .ncu_dmu_stall(ncu_dmu_stall), | |
12760 | .ncu_ccu_vld(ncu_ccu_vld), | |
12761 | .ncu_ccu_data(ncu_ccu_data[3:0]), | |
12762 | .ccu_ncu_data(ccu_ncu_data[3:0]), | |
12763 | .ccu_ncu_vld(ccu_ncu_vld), | |
12764 | .ccu_ncu_stall(ccu_ncu_stall), | |
12765 | .ncu_ccu_stall(ncu_ccu_stall), | |
12766 | .ncu_mcu0_vld(ncu_mcu0_vld), | |
12767 | .ncu_mcu0_data(ncu_mcu0_data[3:0]), | |
12768 | .mcu0_ncu_stall(mcu0_ncu_stall), | |
12769 | .mcu0_ncu_vld(mcu0_ncu_vld), | |
12770 | .mcu0_ncu_data(mcu0_ncu_data[3:0]), | |
12771 | .ncu_mcu0_stall(ncu_mcu0_stall), | |
12772 | .ncu_mcu1_vld(ncu_mcu1_vld), | |
12773 | .ncu_mcu1_data(ncu_mcu1_data[3:0]), | |
12774 | .mcu1_ncu_stall(mcu1_ncu_stall), | |
12775 | .mcu1_ncu_vld(mcu1_ncu_vld), | |
12776 | .mcu1_ncu_data(mcu1_ncu_data[3:0]), | |
12777 | .ncu_mcu1_stall(ncu_mcu1_stall), | |
12778 | .ncu_mcu2_vld(ncu_mcu2_vld), | |
12779 | .ncu_mcu2_data(ncu_mcu2_data[3:0]), | |
12780 | .mcu2_ncu_stall(mcu2_ncu_stall), | |
12781 | .mcu2_ncu_vld(mcu2_ncu_vld), | |
12782 | .mcu2_ncu_data(mcu2_ncu_data[3:0]), | |
12783 | .ncu_mcu2_stall(ncu_mcu2_stall), | |
12784 | .ncu_mcu3_vld(ncu_mcu3_vld), | |
12785 | .ncu_mcu3_data(ncu_mcu3_data[3:0]), | |
12786 | .mcu3_ncu_stall(mcu3_ncu_stall), | |
12787 | .mcu3_ncu_vld(mcu3_ncu_vld), | |
12788 | .mcu3_ncu_data(mcu3_ncu_data[3:0]), | |
12789 | .ncu_mcu3_stall(ncu_mcu3_stall), | |
12790 | .ncu_niu_vld(ncu_niu_vld), | |
12791 | .ncu_niu_data(ncu_niu_data[31:0]), | |
12792 | .niu_ncu_stall(niu_ncu_stall), | |
12793 | .niu_ncu_vld(niu_ncu_vld), | |
12794 | .niu_ncu_data(niu_ncu_data[31:0]), | |
12795 | .ncu_niu_stall(ncu_niu_stall), | |
12796 | .ncu_tcu_vld(ncu_tcu_vld), | |
12797 | .ncu_tcu_data(ncu_tcu_data[7:0]), | |
12798 | .tcu_ncu_stall(tcu_ncu_stall), | |
12799 | .tcu_ncu_vld(tcu_ncu_vld), | |
12800 | .tcu_ncu_data(tcu_ncu_data[7:0]), | |
12801 | .ncu_tcu_stall(ncu_tcu_stall), | |
12802 | .ncu_mio_ssi_mosi(ncu_mio_ssi_mosi), | |
12803 | .ncu_mio_ssi_sck(ncu_mio_ssi_sck), | |
12804 | .mio_ncu_ssi_miso(mio_ncu_ssi_miso), | |
12805 | .mio_ncu_ext_int_l(mio_ncu_ext_int_l), | |
12806 | .ncu_rst_vld(ncu_rst_vld), | |
12807 | .ncu_rst_data(ncu_rst_data[3:0]), | |
12808 | .rst_ncu_stall(rst_ncu_stall), | |
12809 | .rst_ncu_vld(rst_ncu_vld), | |
12810 | .rst_ncu_data(rst_ncu_data[3:0]), | |
12811 | .ncu_rst_stall(ncu_rst_stall), | |
12812 | .efu_ncu_fuse_data(efu_ncu_fuse_data), | |
12813 | .efu_ncu_srlnum0_xfer_en(efu_ncu_srlnum0_xfer_en), | |
12814 | .efu_ncu_srlnum1_xfer_en(efu_ncu_srlnum1_xfer_en), | |
12815 | .efu_ncu_srlnum2_xfer_en(efu_ncu_srlnum2_xfer_en), | |
12816 | .efu_ncu_fusestat_xfer_en(efu_ncu_fusestat_xfer_en), | |
12817 | .efu_ncu_coreavl_xfer_en(efu_ncu_coreavl_xfer_en), | |
12818 | .efu_ncu_bankavl_xfer_en(efu_ncu_bankavl_xfer_en), | |
12819 | .sii_ncu_req(sii_ncu_req), | |
12820 | .ncu_sii_gnt(ncu_sii_gnt), | |
12821 | .sii_ncu_data(sii_ncu_data[31:0]), | |
12822 | .rst_ncu_unpark_thread(rst_ncu_unpark_thread), | |
12823 | .rst_ncu_xir_(rst_ncu_xir_), | |
12824 | .ncu_rst_xir_done(ncu_rst_xir_done), | |
12825 | .ncu_cmp_tick_enable(ncu_cmp_tick_enable), | |
12826 | .ncu_wmr_vec_mask(ncu_wmr_vec_mask), | |
12827 | .ncu_spc0_core_available(ncu_spc0_core_available), | |
12828 | .ncu_spc1_core_available(ncu_spc1_core_available), | |
12829 | .ncu_spc2_core_available(ncu_spc2_core_available), | |
12830 | .ncu_spc3_core_available(ncu_spc3_core_available), | |
12831 | .ncu_spc4_core_available(ncu_spc4_core_available), | |
12832 | .ncu_spc5_core_available(ncu_spc5_core_available), | |
12833 | .ncu_spc6_core_available(ncu_spc6_core_available), | |
12834 | .ncu_spc7_core_available(ncu_spc7_core_available), | |
12835 | .ncu_spc0_core_enable_status(ncu_spc0_core_enable_status), | |
12836 | .ncu_spc1_core_enable_status(ncu_spc1_core_enable_status), | |
12837 | .ncu_spc2_core_enable_status(ncu_spc2_core_enable_status), | |
12838 | .ncu_spc3_core_enable_status(ncu_spc3_core_enable_status), | |
12839 | .ncu_spc4_core_enable_status(ncu_spc4_core_enable_status), | |
12840 | .ncu_spc5_core_enable_status(ncu_spc5_core_enable_status), | |
12841 | .ncu_spc6_core_enable_status(ncu_spc6_core_enable_status), | |
12842 | .ncu_spc7_core_enable_status(ncu_spc7_core_enable_status), | |
12843 | .ncu_spc0_core_running(ncu_spc0_core_running[7:0]), | |
12844 | .ncu_spc1_core_running(ncu_spc1_core_running[7:0]), | |
12845 | .ncu_spc2_core_running(ncu_spc2_core_running[7:0]), | |
12846 | .ncu_spc3_core_running(ncu_spc3_core_running[7:0]), | |
12847 | .ncu_spc4_core_running(ncu_spc4_core_running[7:0]), | |
12848 | .ncu_spc5_core_running(ncu_spc5_core_running[7:0]), | |
12849 | .ncu_spc6_core_running(ncu_spc6_core_running[7:0]), | |
12850 | .ncu_spc7_core_running(ncu_spc7_core_running[7:0]), | |
12851 | .spc0_ncu_core_running_status(spc0_ncu_core_running_status[7:0]), | |
12852 | .spc1_ncu_core_running_status(spc1_ncu_core_running_status[7:0]), | |
12853 | .spc2_ncu_core_running_status(spc2_ncu_core_running_status[7:0]), | |
12854 | .spc3_ncu_core_running_status(spc3_ncu_core_running_status[7:0]), | |
12855 | .spc4_ncu_core_running_status(spc4_ncu_core_running_status[7:0]), | |
12856 | .spc5_ncu_core_running_status(spc5_ncu_core_running_status[7:0]), | |
12857 | .spc6_ncu_core_running_status(spc6_ncu_core_running_status[7:0]), | |
12858 | .spc7_ncu_core_running_status(spc7_ncu_core_running_status[7:0]), | |
12859 | .ncu_spc_pm(ncu_spc_pm), | |
12860 | .ncu_spc_ba01(ncu_spc_ba01), | |
12861 | .ncu_spc_ba23(ncu_spc_ba23), | |
12862 | .ncu_spc_ba45(ncu_spc_ba45), | |
12863 | .ncu_spc_ba67(ncu_spc_ba67), | |
12864 | .ncu_spc_l2_idx_hash_en(ncu_spc_l2_idx_hash_en), | |
12865 | .ncu_sii_pm(ncu_sii_pm), | |
12866 | .ncu_sii_ba01(ncu_sii_ba01), | |
12867 | .ncu_sii_ba23(ncu_sii_ba23), | |
12868 | .ncu_sii_ba45(ncu_sii_ba45), | |
12869 | .ncu_sii_ba67(ncu_sii_ba67), | |
12870 | .ncu_sii_l2_idx_hash_en(ncu_sii_l2_idx_hash_en), | |
12871 | .ncu_l2t_pm(ncu_l2t_pm), | |
12872 | .ncu_l2t_ba01(ncu_l2t_ba01), | |
12873 | .ncu_l2t_ba23(ncu_l2t_ba23), | |
12874 | .ncu_l2t_ba45(ncu_l2t_ba45), | |
12875 | .ncu_l2t_ba67(ncu_l2t_ba67), | |
12876 | .ncu_mcu_pm(ncu_mcu_pm), | |
12877 | .ncu_mcu_ba01(ncu_mcu_ba01), | |
12878 | .ncu_mcu_ba23(ncu_mcu_ba23), | |
12879 | .ncu_mcu_ba45(ncu_mcu_ba45), | |
12880 | .ncu_mcu_ba67(ncu_mcu_ba67), | |
12881 | .ncu_rst_fatal_error(ncu_rst_fatal_error), | |
12882 | .ncu_tcu_bank_avail(ncu_tcu_bank_avail[7:0]), | |
12883 | .sii_ncu_dparity(sii_ncu_dparity[1:0]), | |
12884 | .sii_ncu_niuctag_ue(sii_ncu_niuctag_ue), | |
12885 | .ncu_sii_niuctag_uei(ncu_sii_niuctag_uei), | |
12886 | .sii_ncu_niuctag_ce(sii_ncu_niuctag_ce), | |
12887 | .ncu_sii_niuctag_cei(ncu_sii_niuctag_cei), | |
12888 | .sii_ncu_niua_pe(sii_ncu_niua_pe), | |
12889 | .ncu_sii_niua_pei(ncu_sii_niua_pei), | |
12890 | .sii_ncu_niud_pe(sii_ncu_niud_pe), | |
12891 | .ncu_sii_niud_pei(ncu_sii_niud_pei), | |
12892 | .sii_ncu_dmuctag_ue(sii_ncu_dmuctag_ue), | |
12893 | .ncu_sii_dmuctag_uei(ncu_sii_dmuctag_uei), | |
12894 | .sii_ncu_dmuctag_ce(sii_ncu_dmuctag_ce), | |
12895 | .ncu_sii_dmuctag_cei(ncu_sii_dmuctag_cei), | |
12896 | .sii_ncu_dmua_pe(sii_ncu_dmua_pe), | |
12897 | .ncu_sii_dmua_pei(ncu_sii_dmua_pei), | |
12898 | .sii_ncu_dmud_pe(sii_ncu_dmud_pe), | |
12899 | .ncu_sii_dmud_pei(ncu_sii_dmud_pei), | |
12900 | .sii_ncu_syn_vld(sii_ncu_syn_vld), | |
12901 | .sii_ncu_syn_data(sii_ncu_syn_data[3:0]), | |
12902 | .tcu_sck_bypass(tcu_sck_bypass), | |
12903 | .sio_ncu_ctag_ce(sio_ncu_ctag_ce), | |
12904 | .ncu_sio_ctag_cei(ncu_sio_ctag_cei), | |
12905 | .sio_ncu_ctag_ue(sio_ncu_ctag_ue), | |
12906 | .ncu_sio_ctag_uei(ncu_sio_ctag_uei), | |
12907 | .ncu_sio_d_pei(ncu_sio_d_pei), | |
12908 | .niu_ncu_ctag_ue(niu_ncu_ctag_ue), | |
12909 | .ncu_niu_ctag_uei(ncu_niu_ctag_uei), | |
12910 | .niu_ncu_ctag_ce(niu_ncu_ctag_ce), | |
12911 | .ncu_niu_ctag_cei(ncu_niu_ctag_cei), | |
12912 | .niu_ncu_d_pe(niu_ncu_d_pe), | |
12913 | .ncu_niu_d_pei(ncu_niu_d_pei), | |
12914 | .dmu_ncu_wrack_par(dmu_ncu_wrack_par), | |
12915 | .ncu_dmu_mondo_id_par(ncu_dmu_mondo_id_par), | |
12916 | .dmu_ncu_d_pe(dmu_ncu_d_pe), | |
12917 | .ncu_dmu_d_pei(ncu_dmu_d_pei), | |
12918 | .dmu_ncu_siicr_pe(dmu_ncu_siicr_pe), | |
12919 | .ncu_dmu_siicr_pei(ncu_dmu_siicr_pei), | |
12920 | .dmu_ncu_ctag_ue(dmu_ncu_ctag_ue), | |
12921 | .ncu_dmu_ctag_uei(ncu_dmu_ctag_uei), | |
12922 | .dmu_ncu_ctag_ce(dmu_ncu_ctag_ce), | |
12923 | .ncu_dmu_ctag_cei(ncu_dmu_ctag_cei), | |
12924 | .dmu_ncu_ncucr_pe(dmu_ncu_ncucr_pe), | |
12925 | .ncu_dmu_ncucr_pei(ncu_dmu_ncucr_pei), | |
12926 | .dmu_ncu_ie(dmu_ncu_ie), | |
12927 | .ncu_dmu_iei(ncu_dmu_iei), | |
12928 | .mcu0_ncu_ecc(mcu0_ncu_ecc), | |
12929 | .ncu_mcu0_ecci(ncu_mcu0_ecci), | |
12930 | .mcu0_ncu_fbr(mcu0_ncu_fbr), | |
12931 | .ncu_mcu0_fbri(ncu_mcu0_fbri), | |
12932 | .ncu_mcu0_fbui(ncu_mcu0_fbui), | |
12933 | .mcu1_ncu_ecc(mcu1_ncu_ecc), | |
12934 | .ncu_mcu1_ecci(ncu_mcu1_ecci), | |
12935 | .mcu1_ncu_fbr(mcu1_ncu_fbr), | |
12936 | .ncu_mcu1_fbri(ncu_mcu1_fbri), | |
12937 | .ncu_mcu1_fbui(ncu_mcu1_fbui), | |
12938 | .mcu2_ncu_ecc(mcu2_ncu_ecc), | |
12939 | .ncu_mcu2_ecci(ncu_mcu2_ecci), | |
12940 | .mcu2_ncu_fbr(mcu2_ncu_fbr), | |
12941 | .ncu_mcu2_fbri(ncu_mcu2_fbri), | |
12942 | .ncu_mcu2_fbui(ncu_mcu2_fbui), | |
12943 | .mcu3_ncu_ecc(mcu3_ncu_ecc), | |
12944 | .ncu_mcu3_ecci(ncu_mcu3_ecci), | |
12945 | .mcu3_ncu_fbr(mcu3_ncu_fbr), | |
12946 | .ncu_mcu3_fbri(ncu_mcu3_fbri), | |
12947 | .ncu_mcu3_fbui(ncu_mcu3_fbui), | |
12948 | .rst_wmr_protect(rst_wmr_protect), | |
12949 | .cluster_arst_l(cluster_arst_l), | |
12950 | .ccu_serdes_dtm(ccu_serdes_dtm), | |
12951 | .tcu_div_bypass(tcu_div_bypass), | |
12952 | .tcu_atpg_mode(tcu_atpg_mode), | |
12953 | .ncu_dbg1_error_event(ncu_dbg1_error_event), | |
12954 | .ncu_dbg1_stall(ncu_dbg1_stall), | |
12955 | .ncu_dbg1_vld(ncu_dbg1_vld), | |
12956 | .ncu_dbg1_data(ncu_dbg1_data[3:0]), | |
12957 | .dbg1_ncu_stall(dbg1_ncu_stall), | |
12958 | .dbg1_ncu_vld(dbg1_ncu_vld), | |
12959 | .dbg1_ncu_data(dbg1_ncu_data[3:0]) | |
12960 | ); | |
12961 | `endif // OPENSPARC_CMP | |
12962 | ||
12963 | //________________________________________________________________ | |
12964 | // leave this instance out of cmp model | |
12965 | `ifdef OPENSPARC_CMP | |
12966 | `else | |
12967 | efu efu( | |
12968 | ||
12969 | .io_vpp (VPP ), | |
12970 | .gclk ( cmp_gclk_c1_efu ), // cmp_gclk_c0_r[3] ), | |
12971 | .tcu_clk_stop ( gl_efu_io_clk_stop ), // staged clk_stop | |
12972 | .tcu_efu_clk_stop ( gl_efu_clk_stop ), // staged cmp clk_stop | |
12973 | .ccu_io_out ( gl_io_out_c1m ), // staged div phase | |
12974 | .scan_in (mio_scan_out ), | |
12975 | .tcu_scan_en (tcu_scan_en ), | |
12976 | .tcu_aclk (tcu_aclk ), | |
12977 | .tcu_bclk (tcu_bclk ), | |
12978 | .scan_out (efu_scan_out ), | |
12979 | .tcu_efu_rowaddr (tcu_efu_rowaddr[ 6 : 0 ] ), | |
12980 | .tcu_efu_coladdr (tcu_efu_coladdr[ 4 : 0 ] ), | |
12981 | .io_pgrm_en (mio_efu_prgm_en ), | |
12982 | .tcu_efu_read_en (tcu_efu_read_en ), | |
12983 | .tcu_efu_read_mode (tcu_efu_read_mode[ 2 : 0 ] ), | |
12984 | .tcu_efu_read_start (tcu_efu_read_start ), | |
12985 | .tcu_efu_fuse_bypass (tcu_efu_fuse_bypass ), | |
12986 | .tcu_efu_dest_sample (tcu_efu_dest_sample ), | |
12987 | .tcu_efu_data_in (tcu_efu_data_in ), | |
12988 | .efu_tcu_data_out (efu_tcu_data_out ), | |
12989 | .tcu_efu_updatedr (tcu_efu_updatedr ), | |
12990 | .tcu_efu_shiftdr (tcu_efu_shiftdr ), | |
12991 | .tcu_efu_capturedr (tcu_efu_capturedr ), | |
12992 | .tcu_red_reg_clr (tcu_efu_rvclr[ 6 : 0 ] ), | |
12993 | .rst_wmr_ ( gl_rst_l2_wmr_c1m ), // ( gl_l2_wmr_c1b ), - for int6.1 | |
12994 | .rst_por_ ( gl_rst_l2_por_c1m ), // ( gl_l2_por_c1t ), - for int6.1 | |
12995 | .io_cmp_clk_sync_en ( gl_io_cmp_sync_en_c1m ), | |
12996 | .cmp_io_clk_sync_en ( gl_cmp_io_sync_en_c1m ), | |
12997 | .tck (tck ), | |
12998 | .efu_niu_mac01_sfro_data (efu_niu_mac01_sfro_data ), | |
12999 | .efu_niu_mac1_sf_xfer_en (efu_niu_mac1_sf_xfer_en ), | |
13000 | .efu_niu_mac1_ro_xfer_en (efu_niu_mac1_ro_xfer_en ), | |
13001 | .efu_niu_mac0_sf_xfer_en (efu_niu_mac0_sf_xfer_en ), | |
13002 | .efu_niu_mac0_ro_xfer_en (efu_niu_mac0_ro_xfer_en ), | |
13003 | .efu_niu_ipp1_xfer_en (efu_niu_ipp1_xfer_en ), | |
13004 | .efu_niu_ipp0_xfer_en (efu_niu_ipp0_xfer_en ), | |
13005 | .efu_niu_mac1_sf_clr (efu_niu_mac1_sf_clr ), | |
13006 | .efu_niu_mac1_ro_clr (efu_niu_mac1_ro_clr ), | |
13007 | .efu_niu_mac0_sf_clr (efu_niu_mac0_sf_clr ), | |
13008 | .efu_niu_mac0_ro_clr (efu_niu_mac0_ro_clr ), | |
13009 | .efu_niu_ipp1_clr (efu_niu_ipp1_clr ), | |
13010 | .efu_niu_ipp0_clr (efu_niu_ipp0_clr ), | |
13011 | ||
13012 | .niu_efu_mac1_sf_data (niu_efu_mac1_sf_data), | |
13013 | .niu_efu_mac1_ro_data (niu_efu_mac1_ro_data), | |
13014 | .niu_efu_mac0_sf_data (niu_efu_mac0_sf_data), | |
13015 | .niu_efu_mac0_ro_data (niu_efu_mac0_ro_data), | |
13016 | .niu_efu_ipp1_data (niu_efu_ipp1_data), | |
13017 | .niu_efu_ipp0_data (niu_efu_ipp0_data), | |
13018 | .niu_efu_mac1_sf_xfer_en (niu_efu_mac1_sf_xfer_en), | |
13019 | .niu_efu_mac1_ro_xfer_en (niu_efu_mac1_ro_xfer_en), | |
13020 | .niu_efu_mac0_sf_xfer_en (niu_efu_mac0_sf_xfer_en), | |
13021 | .niu_efu_mac0_ro_xfer_en (niu_efu_mac0_ro_xfer_en), | |
13022 | .niu_efu_ipp1_xfer_en (niu_efu_ipp1_xfer_en), | |
13023 | .niu_efu_ipp0_xfer_en (niu_efu_ipp0_xfer_en), | |
13024 | .niu_efu_cfifo0_data (niu_efu_cfifo0_data), | |
13025 | .niu_efu_cfifo0_xfer_en (niu_efu_cfifo0_xfer_en), | |
13026 | .niu_efu_cfifo1_data (niu_efu_cfifo1_data), | |
13027 | .niu_efu_cfifo1_xfer_en (niu_efu_cfifo1_xfer_en), | |
13028 | .efu_niu_ram_xfer_en (efu_niu_ram_xfer_en), | |
13029 | .efu_niu_ram0_xfer_en (efu_niu_ram0_xfer_en), | |
13030 | .efu_niu_ram1_xfer_en (efu_niu_ram1_xfer_en), | |
13031 | .niu_efu_ram_xfer_en (niu_efu_ram_xfer_en), | |
13032 | .niu_efu_ram1_xfer_en (niu_efu_ram1_xfer_en), | |
13033 | .niu_efu_ram0_xfer_en (niu_efu_ram0_xfer_en), | |
13034 | .niu_efu_ram_data (niu_efu_ram_data), | |
13035 | .niu_efu_ram0_data (niu_efu_ram0_data), | |
13036 | .niu_efu_ram1_data (niu_efu_ram1_data), | |
13037 | .niu_efu_4k_xfer_en (niu_efu_4k_xfer_en), | |
13038 | .niu_efu_4k_data (niu_efu_4k_data), | |
13039 | .efu_niu_cfifo_data (efu_niu_cfifo_data ), | |
13040 | .efu_niu_cfifo0_xfer_en (efu_niu_cfifo0_xfer_en ), | |
13041 | .efu_niu_cfifo1_xfer_en (efu_niu_cfifo1_xfer_en ), | |
13042 | .efu_niu_cfifo0_clr (efu_niu_cfifo0_clr ), | |
13043 | .efu_niu_cfifo1_clr (efu_niu_cfifo1_clr ), | |
13044 | .efu_niu_ram_clr (efu_niu_ram_clr ), | |
13045 | .efu_niu_ram0_clr (efu_niu_ram0_clr ), | |
13046 | .efu_niu_ram1_clr (efu_niu_ram1_clr ), | |
13047 | .efu_mcu_fdi (efu_mcu_fdi ), | |
13048 | .mcu_efu_fdo (mcu_efu_fdo ), | |
13049 | .efu_mcu_fclk (efu_mcu_fclk ), | |
13050 | .efu_mcu_fclrz (efu_mcu_fclrz ), | |
13051 | .efu_niu_fdi (efu_niu_fdi ), | |
13052 | .niu_efu_fdo (niu_efu_fdo ), | |
13053 | .efu_niu_fclk (efu_niu_fclk ), | |
13054 | .efu_niu_fclrz (efu_niu_fclrz ), | |
13055 | .tcu_atpg_mode(tcu_atpg_mode), | |
13056 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit), | |
13057 | .cluster_arst_l(cluster_arst_l), | |
13058 | .tcu_pce_ov(tcu_pce_ov), | |
13059 | .rst_wmr_protect(rst_wmr_protect), | |
13060 | .tcu_div_bypass(tcu_div_bypass), | |
13061 | .tcu_dbr_gateoff(tcu_dbr_gateoff), | |
13062 | .efu_spc1357_fuse_data(efu_spc1357_fuse_data), | |
13063 | .efu_spc0246_fuse_data(efu_spc0246_fuse_data), | |
13064 | .efu_spc0_fuse_ixfer_en(efu_spc0_fuse_ixfer_en), | |
13065 | .efu_spc1_fuse_ixfer_en(efu_spc1_fuse_ixfer_en), | |
13066 | .efu_spc2_fuse_ixfer_en(efu_spc2_fuse_ixfer_en), | |
13067 | .efu_spc3_fuse_ixfer_en(efu_spc3_fuse_ixfer_en), | |
13068 | .efu_spc4_fuse_ixfer_en(efu_spc4_fuse_ixfer_en), | |
13069 | .efu_spc5_fuse_ixfer_en(efu_spc5_fuse_ixfer_en), | |
13070 | .efu_spc6_fuse_ixfer_en(efu_spc6_fuse_ixfer_en), | |
13071 | .efu_spc7_fuse_ixfer_en(efu_spc7_fuse_ixfer_en), | |
13072 | .efu_spc0_fuse_iclr(efu_spc0_fuse_iclr), | |
13073 | .efu_spc1_fuse_iclr(efu_spc1_fuse_iclr), | |
13074 | .efu_spc2_fuse_iclr(efu_spc2_fuse_iclr), | |
13075 | .efu_spc3_fuse_iclr(efu_spc3_fuse_iclr), | |
13076 | .efu_spc4_fuse_iclr(efu_spc4_fuse_iclr), | |
13077 | .efu_spc5_fuse_iclr(efu_spc5_fuse_iclr), | |
13078 | .efu_spc6_fuse_iclr(efu_spc6_fuse_iclr), | |
13079 | .efu_spc7_fuse_iclr(efu_spc7_fuse_iclr), | |
13080 | .efu_spc0_fuse_dxfer_en(efu_spc0_fuse_dxfer_en), | |
13081 | .efu_spc1_fuse_dxfer_en(efu_spc1_fuse_dxfer_en), | |
13082 | .efu_spc2_fuse_dxfer_en(efu_spc2_fuse_dxfer_en), | |
13083 | .efu_spc3_fuse_dxfer_en(efu_spc3_fuse_dxfer_en), | |
13084 | .efu_spc4_fuse_dxfer_en(efu_spc4_fuse_dxfer_en), | |
13085 | .efu_spc5_fuse_dxfer_en(efu_spc5_fuse_dxfer_en), | |
13086 | .efu_spc6_fuse_dxfer_en(efu_spc6_fuse_dxfer_en), | |
13087 | .efu_spc7_fuse_dxfer_en(efu_spc7_fuse_dxfer_en), | |
13088 | .efu_spc0_fuse_dclr(efu_spc0_fuse_dclr), | |
13089 | .efu_spc1_fuse_dclr(efu_spc1_fuse_dclr), | |
13090 | .efu_spc2_fuse_dclr(efu_spc2_fuse_dclr), | |
13091 | .efu_spc3_fuse_dclr(efu_spc3_fuse_dclr), | |
13092 | .efu_spc4_fuse_dclr(efu_spc4_fuse_dclr), | |
13093 | .efu_spc5_fuse_dclr(efu_spc5_fuse_dclr), | |
13094 | .efu_spc6_fuse_dclr(efu_spc6_fuse_dclr), | |
13095 | .efu_spc7_fuse_dclr(efu_spc7_fuse_dclr), | |
13096 | .spc0_efu_fuse_dxfer_en(spc0_efu_fuse_dxfer_en), | |
13097 | .spc1_efu_fuse_dxfer_en(spc1_efu_fuse_dxfer_en), | |
13098 | .spc2_efu_fuse_dxfer_en(spc2_efu_fuse_dxfer_en), | |
13099 | .spc3_efu_fuse_dxfer_en(spc3_efu_fuse_dxfer_en), | |
13100 | .spc4_efu_fuse_dxfer_en(spc4_efu_fuse_dxfer_en), | |
13101 | .spc5_efu_fuse_dxfer_en(spc5_efu_fuse_dxfer_en), | |
13102 | .spc6_efu_fuse_dxfer_en(spc6_efu_fuse_dxfer_en), | |
13103 | .spc7_efu_fuse_dxfer_en(spc7_efu_fuse_dxfer_en), | |
13104 | .spc0_efu_fuse_ixfer_en(spc0_efu_fuse_ixfer_en), | |
13105 | .spc1_efu_fuse_ixfer_en(spc1_efu_fuse_ixfer_en), | |
13106 | .spc2_efu_fuse_ixfer_en(spc2_efu_fuse_ixfer_en), | |
13107 | .spc3_efu_fuse_ixfer_en(spc3_efu_fuse_ixfer_en), | |
13108 | .spc4_efu_fuse_ixfer_en(spc4_efu_fuse_ixfer_en), | |
13109 | .spc5_efu_fuse_ixfer_en(spc5_efu_fuse_ixfer_en), | |
13110 | .spc6_efu_fuse_ixfer_en(spc6_efu_fuse_ixfer_en), | |
13111 | .spc7_efu_fuse_ixfer_en(spc7_efu_fuse_ixfer_en), | |
13112 | .spc0_efu_fuse_ddata(spc0_efu_fuse_ddata), | |
13113 | .spc1_efu_fuse_ddata(spc1_efu_fuse_ddata), | |
13114 | .spc2_efu_fuse_ddata(spc2_efu_fuse_ddata), | |
13115 | .spc3_efu_fuse_ddata(spc3_efu_fuse_ddata), | |
13116 | .spc4_efu_fuse_ddata(spc4_efu_fuse_ddata), | |
13117 | .spc5_efu_fuse_ddata(spc5_efu_fuse_ddata), | |
13118 | .spc6_efu_fuse_ddata(spc6_efu_fuse_ddata), | |
13119 | .spc7_efu_fuse_ddata(spc7_efu_fuse_ddata), | |
13120 | .spc0_efu_fuse_idata(spc0_efu_fuse_idata), | |
13121 | .spc1_efu_fuse_idata(spc1_efu_fuse_idata), | |
13122 | .spc2_efu_fuse_idata(spc2_efu_fuse_idata), | |
13123 | .spc3_efu_fuse_idata(spc3_efu_fuse_idata), | |
13124 | .spc4_efu_fuse_idata(spc4_efu_fuse_idata), | |
13125 | .spc5_efu_fuse_idata(spc5_efu_fuse_idata), | |
13126 | .spc6_efu_fuse_idata(spc6_efu_fuse_idata), | |
13127 | .spc7_efu_fuse_idata(spc7_efu_fuse_idata), | |
13128 | .efu_l2t0246_fuse_data(efu_l2t0246_fuse_data), | |
13129 | .efu_l2t1357_fuse_data(efu_l2t1357_fuse_data), | |
13130 | .efu_l2t0_fuse_xfer_en(efu_l2t0_fuse_xfer_en), | |
13131 | .efu_l2t1_fuse_xfer_en(efu_l2t1_fuse_xfer_en), | |
13132 | .efu_l2t2_fuse_xfer_en(efu_l2t2_fuse_xfer_en), | |
13133 | .efu_l2t3_fuse_xfer_en(efu_l2t3_fuse_xfer_en), | |
13134 | .efu_l2t4_fuse_xfer_en(efu_l2t4_fuse_xfer_en), | |
13135 | .efu_l2t5_fuse_xfer_en(efu_l2t5_fuse_xfer_en), | |
13136 | .efu_l2t6_fuse_xfer_en(efu_l2t6_fuse_xfer_en), | |
13137 | .efu_l2t7_fuse_xfer_en(efu_l2t7_fuse_xfer_en), | |
13138 | .efu_l2t0_fuse_clr(efu_l2t0_fuse_clr), | |
13139 | .efu_l2t1_fuse_clr(efu_l2t1_fuse_clr), | |
13140 | .efu_l2t2_fuse_clr(efu_l2t2_fuse_clr), | |
13141 | .efu_l2t3_fuse_clr(efu_l2t3_fuse_clr), | |
13142 | .efu_l2t4_fuse_clr(efu_l2t4_fuse_clr), | |
13143 | .efu_l2t5_fuse_clr(efu_l2t5_fuse_clr), | |
13144 | .efu_l2t6_fuse_clr(efu_l2t6_fuse_clr), | |
13145 | .efu_l2t7_fuse_clr(efu_l2t7_fuse_clr), | |
13146 | .l2t0_efu_fuse_xfer_en(l2t0_efu_fuse_xfer_en), | |
13147 | .l2t1_efu_fuse_xfer_en(l2t1_efu_fuse_xfer_en), | |
13148 | .l2t2_efu_fuse_xfer_en(l2t2_efu_fuse_xfer_en), | |
13149 | .l2t3_efu_fuse_xfer_en(l2t3_efu_fuse_xfer_en), | |
13150 | .l2t4_efu_fuse_xfer_en(l2t4_efu_fuse_xfer_en), | |
13151 | .l2t5_efu_fuse_xfer_en(l2t5_efu_fuse_xfer_en), | |
13152 | .l2t6_efu_fuse_xfer_en(l2t6_efu_fuse_xfer_en), | |
13153 | .l2t7_efu_fuse_xfer_en(l2t7_efu_fuse_xfer_en), | |
13154 | .l2t0_efu_fuse_data(l2t0_efu_fuse_data), | |
13155 | .l2t1_efu_fuse_data(l2t1_efu_fuse_data), | |
13156 | .l2t2_efu_fuse_data(l2t2_efu_fuse_data), | |
13157 | .l2t3_efu_fuse_data(l2t3_efu_fuse_data), | |
13158 | .l2t4_efu_fuse_data(l2t4_efu_fuse_data), | |
13159 | .l2t5_efu_fuse_data(l2t5_efu_fuse_data), | |
13160 | .l2t6_efu_fuse_data(l2t6_efu_fuse_data), | |
13161 | .l2t7_efu_fuse_data(l2t7_efu_fuse_data), | |
13162 | .efu_l2b0246_fuse_data(efu_l2b0246_fuse_data), | |
13163 | .efu_l2b1357_fuse_data(efu_l2b1357_fuse_data), | |
13164 | .efu_l2b0_fuse_xfer_en(efu_l2b0_fuse_xfer_en), | |
13165 | .efu_l2b1_fuse_xfer_en(efu_l2b1_fuse_xfer_en), | |
13166 | .efu_l2b2_fuse_xfer_en(efu_l2b2_fuse_xfer_en), | |
13167 | .efu_l2b3_fuse_xfer_en(efu_l2b3_fuse_xfer_en), | |
13168 | .efu_l2b4_fuse_xfer_en(efu_l2b4_fuse_xfer_en), | |
13169 | .efu_l2b5_fuse_xfer_en(efu_l2b5_fuse_xfer_en), | |
13170 | .efu_l2b6_fuse_xfer_en(efu_l2b6_fuse_xfer_en), | |
13171 | .efu_l2b7_fuse_xfer_en(efu_l2b7_fuse_xfer_en), | |
13172 | .efu_l2b0_fuse_clr(efu_l2b0_fuse_clr), | |
13173 | .efu_l2b1_fuse_clr(efu_l2b1_fuse_clr), | |
13174 | .efu_l2b2_fuse_clr(efu_l2b2_fuse_clr), | |
13175 | .efu_l2b3_fuse_clr(efu_l2b3_fuse_clr), | |
13176 | .efu_l2b4_fuse_clr(efu_l2b4_fuse_clr), | |
13177 | .efu_l2b5_fuse_clr(efu_l2b5_fuse_clr), | |
13178 | .efu_l2b6_fuse_clr(efu_l2b6_fuse_clr), | |
13179 | .efu_l2b7_fuse_clr(efu_l2b7_fuse_clr), | |
13180 | .l2b0_efu_fuse_xfer_en(l2b0_efu_fuse_xfer_en), | |
13181 | .l2b1_efu_fuse_xfer_en(l2b1_efu_fuse_xfer_en), | |
13182 | .l2b2_efu_fuse_xfer_en(l2b2_efu_fuse_xfer_en), | |
13183 | .l2b3_efu_fuse_xfer_en(l2b3_efu_fuse_xfer_en), | |
13184 | .l2b4_efu_fuse_xfer_en(l2b4_efu_fuse_xfer_en), | |
13185 | .l2b5_efu_fuse_xfer_en(l2b5_efu_fuse_xfer_en), | |
13186 | .l2b6_efu_fuse_xfer_en(l2b6_efu_fuse_xfer_en), | |
13187 | .l2b7_efu_fuse_xfer_en(l2b7_efu_fuse_xfer_en), | |
13188 | .l2b0_efu_fuse_data(l2b0_efu_fuse_data), | |
13189 | .l2b1_efu_fuse_data(l2b1_efu_fuse_data), | |
13190 | .l2b2_efu_fuse_data(l2b2_efu_fuse_data), | |
13191 | .l2b3_efu_fuse_data(l2b3_efu_fuse_data), | |
13192 | .l2b4_efu_fuse_data(l2b4_efu_fuse_data), | |
13193 | .l2b5_efu_fuse_data(l2b5_efu_fuse_data), | |
13194 | .l2b6_efu_fuse_data(l2b6_efu_fuse_data), | |
13195 | .l2b7_efu_fuse_data(l2b7_efu_fuse_data), | |
13196 | .efu_ncu_fuse_data(efu_ncu_fuse_data), | |
13197 | .efu_ncu_srlnum0_xfer_en(efu_ncu_srlnum0_xfer_en), | |
13198 | .efu_ncu_srlnum1_xfer_en(efu_ncu_srlnum1_xfer_en), | |
13199 | .efu_ncu_srlnum2_xfer_en(efu_ncu_srlnum2_xfer_en), | |
13200 | .efu_ncu_fusestat_xfer_en(efu_ncu_fusestat_xfer_en), | |
13201 | .efu_ncu_coreavl_xfer_en(efu_ncu_coreavl_xfer_en), | |
13202 | .efu_ncu_bankavl_xfer_en(efu_ncu_bankavl_xfer_en), | |
13203 | .efu_niu_ram_data(efu_niu_ram_data), | |
13204 | .efu_niu_4k_data(efu_niu_4k_data), | |
13205 | .efu_niu_4k_xfer_en(efu_niu_4k_xfer_en), | |
13206 | .efu_niu_4k_clr(efu_niu_4k_clr), | |
13207 | .efu_dmu_data(efu_dmu_data), | |
13208 | .efu_dmu_xfer_en(efu_dmu_xfer_en), | |
13209 | .efu_dmu_clr(efu_dmu_clr), | |
13210 | .dmu_efu_xfer_en(dmu_efu_xfer_en), | |
13211 | .dmu_efu_data(dmu_efu_data), | |
13212 | .efu_psr_fdi(efu_psr_fdi), | |
13213 | .psr_efu_fdo(psr_efu_fdo), | |
13214 | .efu_psr_fclk(efu_psr_fclk), | |
13215 | .efu_psr_fclrz(efu_psr_fclrz) | |
13216 | ); | |
13217 | `endif // OPENSPARC_CMP | |
13218 | ||
13219 | //________________________________________________________________ | |
13220 | ||
13221 | n2_pcmb_cust pcmb0 ( | |
13222 | .sel (mio_pcmb0_sel59 ), | |
13223 | .burnin (mio_pcm_burnin ), | |
13224 | .bypass (pcmb1_out), | |
13225 | .out (pcmb0_mio_ro_in) | |
13226 | ); | |
13227 | ||
13228 | //________________________________________________________________ | |
13229 | ||
13230 | n2_pcmb_cust pcmb1 ( | |
13231 | .sel (mio_pcmb1_sel60 ), | |
13232 | .burnin (mio_pcm_burnin ), | |
13233 | .bypass (pcma_out), | |
13234 | .out (pcmb1_out) | |
13235 | ); | |
13236 | ||
13237 | //________________________________________________________________ | |
13238 | ||
13239 | n2_pcma_cust pcma ( | |
13240 | .sel (mio_pcma_sel61 ), | |
13241 | .burnin (mio_pcm_burnin ), | |
13242 | .out (pcma_out) | |
13243 | ); | |
13244 | ||
13245 | ||
13246 | //________________________________________________________________ | |
13247 | ||
13248 | n2_tmpd_cust tm0 ( | |
13249 | .diode_top ( DIODE_TOP ) | |
13250 | ); | |
13251 | ||
13252 | n2_tmpd_cust tm1 ( | |
13253 | .diode_top ( DIODE_BOT ) | |
13254 | ); | |
13255 | ||
13256 | //________________________________________________________________ | |
13257 | ||
13258 | n2_rng_cust rng ( | |
13259 | .l2clk (cmp_gclk_c3_rng), // (cmp_gclk_rng), - for int6.1 | |
13260 | .rng_arst_l (rng_arst_l), | |
13261 | .ch_sel (rng_ch_sel), | |
13262 | .siclk (tcu_aclk), | |
13263 | .soclk (tcu_bclk), | |
13264 | .si (1'b0), | |
13265 | .stop (1'b0), | |
13266 | .tcu_se_scancollar_out (tcu_se_scancollar_out), | |
13267 | .so (), | |
13268 | .bypass (rng_bypass), | |
13269 | .vdd_hv15 (VDD_RNG_HV), | |
13270 | .vreg_selbg_l (mio_ccu_vreg_selbg_l), | |
13271 | .vcoctrl_sel (rng_vcoctrl_sel), | |
13272 | .anlg_sel (rng_anlg_sel), | |
13273 | .anlg_char_out (RNG_ANLG_CHAR_OUT), | |
13274 | .rng_data(rng_data) | |
13275 | ); | |
13276 | //________________________________________________________________ | |
13277 | ||
13278 | // leave this instance out of cmp model | |
13279 | `ifdef OPENSPARC_CMP | |
13280 | `else | |
13281 | ccu ccu( | |
13282 | .pll_sys_clk_p (PLL_CMP_CLK_P), | |
13283 | .pll_sys_clk_n (PLL_CMP_CLK_N), | |
13284 | .cmp_pll_clk (l2clk), | |
13285 | .dr_pll_clk (drl2clk) , | |
13286 | .gclk (cmp_gclk_c1_ccu ), | |
13287 | .scan_in (rst_scan_out ), | |
13288 | .scan_out (ccu_scan_out ), // to be connected to tcu | |
13289 | .gl_ccu_io_out (gl_io_out_c1m), | |
13290 | .pll_vdd (VDD_PLL_CMP_REG), | |
13291 | .ccu_vco_aligned(ccu_vco_aligned), | |
13292 | .gclk_aligned(gclk_aligned), | |
13293 | .ccu_ncu_stall(ccu_ncu_stall), | |
13294 | .ncu_ccu_vld(ncu_ccu_vld), | |
13295 | .ncu_ccu_data(ncu_ccu_data[3:0]), | |
13296 | .ncu_ccu_stall(ncu_ccu_stall), | |
13297 | .ccu_ncu_vld(ccu_ncu_vld), | |
13298 | .ccu_ncu_data(ccu_ncu_data[3:0]), | |
13299 | .rng_arst_l(rng_arst_l), | |
13300 | .rng_data(rng_data), | |
13301 | .rng_bypass(rng_bypass), | |
13302 | .rng_vcoctrl_sel(rng_vcoctrl_sel[1:0]), | |
13303 | .rng_ch_sel(rng_ch_sel[1:0]), | |
13304 | .rng_anlg_sel(rng_anlg_sel[1:0]), | |
13305 | .tcu_atpg_mode(tcu_atpg_mode), | |
13306 | .tcu_scan_en(tcu_scan_en), | |
13307 | .tcu_aclk(tcu_aclk), | |
13308 | .tcu_bclk(tcu_bclk), | |
13309 | .ccu_cmp_io_sync_en(ccu_cmp_io_sync_en), | |
13310 | .ccu_io_cmp_sync_en(ccu_io_cmp_sync_en), | |
13311 | .ccu_io2x_sync_en(ccu_io2x_sync_en), | |
13312 | .ccu_dr_sync_en(ccu_dr_sync_en), | |
13313 | .ccu_io2x_out(ccu_io2x_out), | |
13314 | .ccu_io_out(ccu_io_out), | |
13315 | .ccu_serdes_dtm(ccu_serdes_dtm), | |
13316 | .ccu_mio_pll_char_out(ccu_mio_pll_char_out[1:0]), | |
13317 | .ccu_mio_serdes_dtm(ccu_mio_serdes_dtm), | |
13318 | .ccu_dbg1_serdes_dtm(ccu_dbg1_serdes_dtm), | |
13319 | .mio_pll_testmode(mio_pll_testmode), | |
13320 | .mio_ccu_vreg_selbg_l(mio_ccu_vreg_selbg_l), | |
13321 | .mio_ccu_pll_clamp_fltr(mio_ccu_pll_clamp_fltr), | |
13322 | .mio_ccu_pll_div2(mio_ccu_pll_div2[5:0]), | |
13323 | .mio_ccu_pll_div4(mio_ccu_pll_div4[6:0]), | |
13324 | .mio_ccu_pll_trst_l(mio_ccu_pll_trst_l), | |
13325 | .mio_ccu_pll_char_in(mio_ccu_pll_char_in), | |
13326 | .gl_ccu_io_clk_stop(gl_ccu_io_clk_stop), | |
13327 | .gl_ccu_clk_stop(gl_ccu_clk_stop), | |
13328 | .tcu_pce_ov(tcu_pce_ov), | |
13329 | .tcu_ccu_mux_sel(tcu_ccu_mux_sel[1:0]), | |
13330 | .tcu_ccu_ext_cmp_clk(tcu_ccu_ext_cmp_clk), | |
13331 | .tcu_ccu_ext_dr_clk(tcu_ccu_ext_dr_clk), | |
13332 | .tcu_ccu_clk_stretch(tcu_ccu_clk_stretch), | |
13333 | .rst_ccu_pll_(rst_ccu_pll_), | |
13334 | .rst_ccu_(rst_ccu_), | |
13335 | .rst_wmr_protect(rst_wmr_protect), | |
13336 | .ccu_rst_change(ccu_rst_change), | |
13337 | .ccu_rst_sys_clk(ccu_rst_sys_clk), | |
13338 | .ccu_rst_sync_stable(ccu_rst_sync_stable), | |
13339 | .ccu_sys_cmp_sync_en(ccu_sys_cmp_sync_en), | |
13340 | .ccu_cmp_sys_sync_en(ccu_cmp_sys_sync_en), | |
13341 | .cluster_arst_l(cluster_arst_l) | |
13342 | ); | |
13343 | `endif // OPENSPARC_CMP | |
13344 | ||
13345 | ||
13346 | // leave this instance out of cmp model | |
13347 | `ifdef OPENSPARC_CMP | |
13348 | `else | |
13349 | tcu tcu( | |
13350 | ||
13351 | //inputs | |
13352 | .gclk ( cmp_gclk_c1_tcu ), // cmp_gclk_c2_r[4] ), | |
13353 | .ccu_io_out ( gl_io_out_c1m ), // staged div phase | |
13354 | .ccu_cmp_io2x_sync_en (gl_io2x_sync_en_c1m), | |
13355 | .ccu_cmp_dr_sync_en (gl_dr_sync_en_c1m), | |
13356 | .ccu_io_cmp_sync_en ( gl_io_cmp_sync_en_c1m ), | |
13357 | .ccu_cmp_io_sync_en ( gl_cmp_io_sync_en_c1m ), | |
13358 | .io_test_mode (mio_tcu_testmode ), | |
13359 | .io_tms (mio_tcu_tms), | |
13360 | .io_tdi (mio_tcu_tdi), | |
13361 | .io_trst_l (mio_tcu_trst_l), | |
13362 | .io_tck (mio_tcu_tck), | |
13363 | .POR_ (rst_tcu_pwron_rst_l ),//=pwron_rst_l_sys_q & | |
13364 | // mio_rst_pwron_rst_l& | |
13365 | // ccu_rst_sync_stable; | |
13366 | // Async assert, cmp-sync deassert. | |
13367 | .l2t0_tcu_mbist_done (l2t0_tcu_mbist_done_t5lff), | |
13368 | .l2t0_tcu_mbist_fail (l2t0_tcu_mbist_fail_t5lff), | |
13369 | .spc0_tcu_mbist_done (spc0_tcu_mbist_done_t5lff), | |
13370 | .spc0_tcu_mbist_fail (spc0_tcu_mbist_fail_t5lff), | |
13371 | .l2t2_tcu_mbist_done (l2t2_tcu_mbist_done_t7lff), | |
13372 | .l2t2_tcu_mbist_fail (l2t2_tcu_mbist_fail_t7lff), | |
13373 | .spc2_tcu_mbist_done (spc2_tcu_mbist_done_t7lff), | |
13374 | .spc2_tcu_mbist_fail (spc2_tcu_mbist_fail_t7lff), | |
13375 | .l2b0_tcu_mbist_done (l2b0_tcu_mbist_done_ccxlff), | |
13376 | .l2b0_tcu_mbist_fail (l2b0_tcu_mbist_fail_ccxlff), | |
13377 | .l2b1_tcu_mbist_done (l2b1_tcu_mbist_done_ccxlff), | |
13378 | .l2b1_tcu_mbist_fail (l2b1_tcu_mbist_fail_ccxlff), | |
13379 | .l2b2_tcu_mbist_done (l2b2_tcu_mbist_done_ccxlff), | |
13380 | .l2b2_tcu_mbist_fail (l2b2_tcu_mbist_fail_ccxlff), | |
13381 | .l2b3_tcu_mbist_done (l2b3_tcu_mbist_done_ccxlff), | |
13382 | .l2b3_tcu_mbist_fail (l2b3_tcu_mbist_fail_ccxlff), | |
13383 | .mcu0_tcu_mbist_done (mcu0_tcu_mbist_done_t5lff), | |
13384 | .mcu0_tcu_mbist_fail (mcu0_tcu_mbist_fail_t5lff), | |
13385 | .mcu1_tcu_mbist_done (mcu1_tcu_mbist_done_t5lff), | |
13386 | .mcu1_tcu_mbist_fail (mcu1_tcu_mbist_fail_t5lff), | |
13387 | .sii_tcu_mbist_done ({sii_tcu_mbist_done_ccxrff_1,sii_tcu_mbist_done_ccxrff_0}), | |
13388 | .sii_tcu_mbist_fail ({sii_tcu_mbist_fail_ccxrff_1,sii_tcu_mbist_fail_ccxrff_0}), | |
13389 | .ncu_tcu_mbist_done ({ncu_tcu_mbist_done[ 1 ],ncu_tcu_mbist_done_t5lff_0}), | |
13390 | .ncu_tcu_mbist_fail ({ncu_tcu_mbist_fail[ 1 ],ncu_tcu_mbist_fail_t5lff_0}), | |
13391 | .spc0_softstop_request (spc0_softstop_request_t5lff ), | |
13392 | .spc0_hardstop_request (spc0_hardstop_request_t5lff ), | |
13393 | .spc0_trigger_pulse (spc0_trigger_pulse_t5lff ), | |
13394 | .spc0_ss_complete (spc0_ss_complete_t5lff), | |
13395 | .spc2_softstop_request (spc2_softstop_request_t7lff ), | |
13396 | .spc2_hardstop_request (spc2_hardstop_request_t7lff ), | |
13397 | .spc2_trigger_pulse (spc2_trigger_pulse_t7lff ), | |
13398 | .spc2_ss_complete (spc2_ss_complete_t7lff), | |
13399 | .ncu_spc0_core_enable_status(ncu_spc0_core_enable_status), | |
13400 | .ncu_spc1_core_enable_status(ncu_spc1_core_enable_status), | |
13401 | .ncu_spc2_core_enable_status(ncu_spc2_core_enable_status), | |
13402 | .ncu_spc3_core_enable_status(ncu_spc3_core_enable_status), | |
13403 | .ncu_spc4_core_enable_status(ncu_spc4_core_enable_status), | |
13404 | .ncu_spc5_core_enable_status(ncu_spc5_core_enable_status), | |
13405 | .ncu_spc6_core_enable_status(ncu_spc6_core_enable_status), | |
13406 | .ncu_spc7_core_enable_status(ncu_spc7_core_enable_status), | |
13407 | .spc0_tcu_scan_in (spc0_tcu_scan_in[ 1 : 0 ] ), | |
13408 | .spc1_tcu_scan_in (spc1_tcu_scan_in[ 1 : 0 ] ), | |
13409 | .spc2_tcu_scan_in (spc2_tcu_scan_in[ 1 : 0 ] ), | |
13410 | .spc3_tcu_scan_in (spc3_tcu_scan_in[ 1 : 0 ] ), | |
13411 | .spc4_tcu_scan_in (spc4_tcu_scan_in[ 1 : 0 ] ), | |
13412 | .spc5_tcu_scan_in (spc5_tcu_scan_in[ 1 : 0 ] ), | |
13413 | .spc6_tcu_scan_in (spc6_tcu_scan_in[ 1 : 0 ] ), | |
13414 | .spc7_tcu_scan_in (spc7_tcu_scan_in[ 1 : 0 ] ), | |
13415 | .soca_tcu_scan_in (sii_scan_out ), | |
13416 | .socb_tcu_scan_in (mcu0_scan_out ), | |
13417 | .socc_tcu_scan_in (sio_scan_out ), | |
13418 | .socd_tcu_scan_in (dmu_scan_out ), | |
13419 | .soce_tcu_scan_in (rdp_scan_out ), | |
13420 | .socf_tcu_scan_in (rtx_scan_out ), | |
13421 | .socg_tcu_scan_in (mcu3_scan_out ), | |
13422 | .soch_tcu_scan_in (l2b7_scan_out ), | |
13423 | .soc0_tcu_scan_in (l2d1_scan_out ), | |
13424 | .soc1_tcu_scan_in (l2d3_scan_out ), | |
13425 | .soc2_tcu_scan_in (l2d5_scan_out ), | |
13426 | .soc3_tcu_scan_in (l2d7_scan_out ), | |
13427 | .soc4_tcu_scan_in (tds_scan_out ), | |
13428 | .soc5_tcu_scan_in (mac_scan_out ), | |
13429 | .soc6_tcu_scan_in (efu_scan_out ), | |
13430 | .peu_tcu_scan_in (peu_scan_out ), | |
13431 | .ccu_tcu_scan_in (ccu_scan_out ), | |
13432 | .spc0_tcu_mbist_scan_in (spc0_tcu_mbist_scan_out ), | |
13433 | .spc1_tcu_mbist_scan_in (spc1_tcu_mbist_scan_out ), | |
13434 | .spc2_tcu_mbist_scan_in (spc2_tcu_mbist_scan_out ), | |
13435 | .spc3_tcu_mbist_scan_in (spc3_tcu_mbist_scan_out ), | |
13436 | .spc4_tcu_mbist_scan_in (spc4_tcu_mbist_scan_out ), | |
13437 | .spc5_tcu_mbist_scan_in (spc5_tcu_mbist_scan_out ), | |
13438 | .spc6_tcu_mbist_scan_in (spc6_tcu_mbist_scan_out ), | |
13439 | .spc7_tcu_mbist_scan_in (spc7_tcu_mbist_scan_out ), | |
13440 | .l2t0_tcu_shscan_scan_out (l2t0_tcu_shscan_scan_out), | |
13441 | .l2t1_tcu_shscan_scan_out (l2t1_tcu_shscan_scan_out), | |
13442 | .l2t2_tcu_shscan_scan_out (l2t2_tcu_shscan_scan_out), | |
13443 | .l2t3_tcu_shscan_scan_out (l2t3_tcu_shscan_scan_out), | |
13444 | .l2t4_tcu_shscan_scan_out (l2t4_tcu_shscan_scan_out), | |
13445 | .l2t5_tcu_shscan_scan_out (l2t5_tcu_shscan_scan_out), | |
13446 | .l2t6_tcu_shscan_scan_out (l2t6_tcu_shscan_scan_out), | |
13447 | .l2t7_tcu_shscan_scan_out (l2t7_tcu_shscan_scan_out), | |
13448 | ||
13449 | .sbs_tcu_scan_out (mcu2_sbs_scan_out ), | |
13450 | .stciq_tcu (fsr4_stciq[ 0 ] ), | |
13451 | .tcu_srd_atpgd (tcu_srd_atpgd ), // temporary until fsr5 has a corresponding port | |
13452 | .srd_tcu_atpgq (srd_tcu_atpgq ), // temporary until fsr5 has a corresponding port | |
13453 | ||
13454 | //outputs | |
13455 | .tcu_asic_aclk (tcu_asic_aclk ), | |
13456 | .tcu_asic_bclk (tcu_asic_bclk ), | |
13457 | .tcu_asic_scan_en (tcu_asic_scan_en ), | |
13458 | .tcu_asic_se_scancollar_in (tcu_asic_se_scancollar_in ), | |
13459 | .tcu_asic_se_scancollar_out (tcu_asic_se_scancollar_out ), | |
13460 | .tcu_asic_array_wr_inhibit (tcu_asic_array_wr_inhibit ), | |
13461 | .dmo_coresel (dmo_coresel[ 5 : 0 ] ), | |
13462 | .tcu_efu_rvclr (tcu_efu_rvclr[ 6 : 0 ] ), | |
13463 | .tcu_soca_scan_out (tcu_ccx_scan_out[ 0 ]), | |
13464 | .tcu_socb_scan_out (tcu_ccx_scan_out[ 1 ]), | |
13465 | .tcu_socc_scan_out (tcu_socc_scan_out), | |
13466 | .tcu_socd_scan_out (tcu_socd_scan_out), | |
13467 | .tcu_soce_scan_out (tcu_soce_scan_out), | |
13468 | .tcu_socf_scan_out (tcu_socf_scan_out), | |
13469 | .tcu_socg_scan_out (tcu_socg_scan_out), | |
13470 | .tcu_soch_scan_out (tcu_soch_scan_out), | |
13471 | .tcu_spc0_scan_out (tcu_spc0_scan_out[ 1 : 0 ] ), | |
13472 | .tcu_spc1_scan_out (tcu_spc1_scan_out[ 1 : 0 ] ), | |
13473 | .tcu_spc2_scan_out (tcu_spc2_scan_out[ 1 : 0 ] ), | |
13474 | .tcu_spc3_scan_out (tcu_spc3_scan_out[ 1 : 0 ] ), | |
13475 | .tcu_spc4_scan_out (tcu_spc4_scan_out[ 1 : 0 ] ), | |
13476 | .tcu_spc5_scan_out (tcu_spc5_scan_out[ 1 : 0 ] ), | |
13477 | .tcu_spc6_scan_out (tcu_spc6_scan_out[ 1 : 0 ] ), | |
13478 | .tcu_spc7_scan_out (tcu_spc7_scan_out[ 1 : 0 ] ), | |
13479 | .tcu_spc0_mbist_scan_out (tcu_spc0_mbist_scan_in ), | |
13480 | .tcu_spc1_mbist_scan_out (tcu_spc1_mbist_scan_in ), | |
13481 | .tcu_spc2_mbist_scan_out (tcu_spc2_mbist_scan_in ), | |
13482 | .tcu_spc3_mbist_scan_out (tcu_spc3_mbist_scan_in ), | |
13483 | .tcu_spc4_mbist_scan_out (tcu_spc4_mbist_scan_in ), | |
13484 | .tcu_spc5_mbist_scan_out (tcu_spc5_mbist_scan_in ), | |
13485 | .tcu_spc6_mbist_scan_out (tcu_spc6_mbist_scan_in ), | |
13486 | .tcu_spc7_mbist_scan_out (tcu_spc7_mbist_scan_in ), | |
13487 | .tcu_soc0_scan_out (tcu_soc0_scan_out ), | |
13488 | .tcu_soc1_scan_out (tcu_soc1_scan_out ), | |
13489 | .tcu_soc2_scan_out (tcu_soc2_scan_out ), | |
13490 | .tcu_soc3_scan_out (tcu_soc3_scan_out ), | |
13491 | .tcu_soc4_scan_out (tcu_soc4_scan_out ), | |
13492 | .tcu_soc5_scan_out (tcu_soc5_scan_out ), | |
13493 | .tcu_soc6_scan_out (tcu_soc6_scan_out ), | |
13494 | .tcu_peu_scan_out (tcu_peu_scan_out ), | |
13495 | .cluster_arst_l(cluster_arst_l), | |
13496 | .tcu_ccu_clk_stop(tcu_ccu_clk_stop), | |
13497 | .tcu_ccu_io_clk_stop(tcu_ccu_io_clk_stop), | |
13498 | .jtag_revid_out(jtag_revid_out[3:0]), | |
13499 | .tcu_mio_tdo(tcu_mio_tdo), | |
13500 | .tcu_mio_tdo_en(tcu_mio_tdo_en), | |
13501 | .tcu_ncu_stall(tcu_ncu_stall), | |
13502 | .ncu_tcu_vld(ncu_tcu_vld), | |
13503 | .ncu_tcu_data(ncu_tcu_data[7:0]), | |
13504 | .tcu_ncu_vld(tcu_ncu_vld), | |
13505 | .tcu_ncu_data(tcu_ncu_data[7:0]), | |
13506 | .ncu_tcu_stall(ncu_tcu_stall), | |
13507 | .tcu_sck_bypass(tcu_sck_bypass), | |
13508 | .tcu_aclk(tcu_aclk), | |
13509 | .tcu_bclk(tcu_bclk), | |
13510 | .tcu_pce_ov(tcu_pce_ov), | |
13511 | .tcu_scan_en(tcu_scan_en), | |
13512 | .tcu_rst_scan_out(tcu_rst_scan_out), | |
13513 | .tcu_spc0_aclk(tcu_spc0_aclk), | |
13514 | .tcu_spc0_bclk(tcu_spc0_bclk), | |
13515 | .tcu_spc0_scan_en(tcu_spc0_scan_en), | |
13516 | .tcu_spc0_se_scancollar_in(tcu_spc0_se_scancollar_in), | |
13517 | .tcu_spc0_se_scancollar_out(tcu_spc0_se_scancollar_out), | |
13518 | .tcu_spc0_array_wr_inhibit(tcu_spc0_array_wr_inhibit), | |
13519 | .tcu_spc1_aclk(tcu_spc1_aclk), | |
13520 | .tcu_spc1_bclk(tcu_spc1_bclk), | |
13521 | .tcu_spc1_scan_en(tcu_spc1_scan_en), | |
13522 | .tcu_spc1_se_scancollar_in(tcu_spc1_se_scancollar_in), | |
13523 | .tcu_spc1_se_scancollar_out(tcu_spc1_se_scancollar_out), | |
13524 | .tcu_spc1_array_wr_inhibit(tcu_spc1_array_wr_inhibit), | |
13525 | .tcu_spc2_aclk(tcu_spc2_aclk), | |
13526 | .tcu_spc2_bclk(tcu_spc2_bclk), | |
13527 | .tcu_spc2_scan_en(tcu_spc2_scan_en), | |
13528 | .tcu_spc2_se_scancollar_in(tcu_spc2_se_scancollar_in), | |
13529 | .tcu_spc2_se_scancollar_out(tcu_spc2_se_scancollar_out), | |
13530 | .tcu_spc2_array_wr_inhibit(tcu_spc2_array_wr_inhibit), | |
13531 | .tcu_spc3_aclk(tcu_spc3_aclk), | |
13532 | .tcu_spc3_bclk(tcu_spc3_bclk), | |
13533 | .tcu_spc3_scan_en(tcu_spc3_scan_en), | |
13534 | .tcu_spc3_se_scancollar_in(tcu_spc3_se_scancollar_in), | |
13535 | .tcu_spc3_se_scancollar_out(tcu_spc3_se_scancollar_out), | |
13536 | .tcu_spc3_array_wr_inhibit(tcu_spc3_array_wr_inhibit), | |
13537 | .tcu_spc4_aclk(tcu_spc4_aclk), | |
13538 | .tcu_spc4_bclk(tcu_spc4_bclk), | |
13539 | .tcu_spc4_scan_en(tcu_spc4_scan_en), | |
13540 | .tcu_spc4_se_scancollar_in(tcu_spc4_se_scancollar_in), | |
13541 | .tcu_spc4_se_scancollar_out(tcu_spc4_se_scancollar_out), | |
13542 | .tcu_spc4_array_wr_inhibit(tcu_spc4_array_wr_inhibit), | |
13543 | .tcu_spc5_aclk(tcu_spc5_aclk), | |
13544 | .tcu_spc5_bclk(tcu_spc5_bclk), | |
13545 | .tcu_spc5_scan_en(tcu_spc5_scan_en), | |
13546 | .tcu_spc5_se_scancollar_in(tcu_spc5_se_scancollar_in), | |
13547 | .tcu_spc5_se_scancollar_out(tcu_spc5_se_scancollar_out), | |
13548 | .tcu_spc5_array_wr_inhibit(tcu_spc5_array_wr_inhibit), | |
13549 | .tcu_spc6_aclk(tcu_spc6_aclk), | |
13550 | .tcu_spc6_bclk(tcu_spc6_bclk), | |
13551 | .tcu_spc6_scan_en(tcu_spc6_scan_en), | |
13552 | .tcu_spc6_se_scancollar_in(tcu_spc6_se_scancollar_in), | |
13553 | .tcu_spc6_se_scancollar_out(tcu_spc6_se_scancollar_out), | |
13554 | .tcu_spc6_array_wr_inhibit(tcu_spc6_array_wr_inhibit), | |
13555 | .tcu_spc7_aclk(tcu_spc7_aclk), | |
13556 | .tcu_spc7_bclk(tcu_spc7_bclk), | |
13557 | .tcu_spc7_scan_en(tcu_spc7_scan_en), | |
13558 | .tcu_spc7_se_scancollar_in(tcu_spc7_se_scancollar_in), | |
13559 | .tcu_spc7_se_scancollar_out(tcu_spc7_se_scancollar_out), | |
13560 | .tcu_spc7_array_wr_inhibit(tcu_spc7_array_wr_inhibit), | |
13561 | .tcu_spc0_clk_stop(tcu_spc0_clk_stop), | |
13562 | .tcu_spc1_clk_stop(tcu_spc1_clk_stop), | |
13563 | .tcu_spc2_clk_stop(tcu_spc2_clk_stop), | |
13564 | .tcu_spc3_clk_stop(tcu_spc3_clk_stop), | |
13565 | .tcu_spc4_clk_stop(tcu_spc4_clk_stop), | |
13566 | .tcu_spc5_clk_stop(tcu_spc5_clk_stop), | |
13567 | .tcu_spc6_clk_stop(tcu_spc6_clk_stop), | |
13568 | .tcu_spc7_clk_stop(tcu_spc7_clk_stop), | |
13569 | .tcu_l2d0_clk_stop(tcu_l2d0_clk_stop), | |
13570 | .tcu_l2d1_clk_stop(tcu_l2d1_clk_stop), | |
13571 | .tcu_l2d2_clk_stop(tcu_l2d2_clk_stop), | |
13572 | .tcu_l2d3_clk_stop(tcu_l2d3_clk_stop), | |
13573 | .tcu_l2d4_clk_stop(tcu_l2d4_clk_stop), | |
13574 | .tcu_l2d5_clk_stop(tcu_l2d5_clk_stop), | |
13575 | .tcu_l2d6_clk_stop(tcu_l2d6_clk_stop), | |
13576 | .tcu_l2d7_clk_stop(tcu_l2d7_clk_stop), | |
13577 | .tcu_l2t0_clk_stop(tcu_l2t0_clk_stop), | |
13578 | .tcu_l2t1_clk_stop(tcu_l2t1_clk_stop), | |
13579 | .tcu_l2t2_clk_stop(tcu_l2t2_clk_stop), | |
13580 | .tcu_l2t3_clk_stop(tcu_l2t3_clk_stop), | |
13581 | .tcu_l2t4_clk_stop(tcu_l2t4_clk_stop), | |
13582 | .tcu_l2t5_clk_stop(tcu_l2t5_clk_stop), | |
13583 | .tcu_l2t6_clk_stop(tcu_l2t6_clk_stop), | |
13584 | .tcu_l2t7_clk_stop(tcu_l2t7_clk_stop), | |
13585 | .tcu_l2b0_clk_stop(tcu_l2b0_clk_stop), | |
13586 | .tcu_l2b1_clk_stop(tcu_l2b1_clk_stop), | |
13587 | .tcu_l2b2_clk_stop(tcu_l2b2_clk_stop), | |
13588 | .tcu_l2b3_clk_stop(tcu_l2b3_clk_stop), | |
13589 | .tcu_l2b4_clk_stop(tcu_l2b4_clk_stop), | |
13590 | .tcu_l2b5_clk_stop(tcu_l2b5_clk_stop), | |
13591 | .tcu_l2b6_clk_stop(tcu_l2b6_clk_stop), | |
13592 | .tcu_l2b7_clk_stop(tcu_l2b7_clk_stop), | |
13593 | .tcu_mcu0_clk_stop(tcu_mcu0_clk_stop), | |
13594 | .tcu_mcu0_dr_clk_stop(tcu_mcu0_dr_clk_stop), | |
13595 | .tcu_mcu0_io_clk_stop(tcu_mcu0_io_clk_stop), | |
13596 | .tcu_mcu0_fbd_clk_stop(tcu_mcu0_fbd_clk_stop), | |
13597 | .tcu_mcu1_clk_stop(tcu_mcu1_clk_stop), | |
13598 | .tcu_mcu1_dr_clk_stop(tcu_mcu1_dr_clk_stop), | |
13599 | .tcu_mcu1_io_clk_stop(tcu_mcu1_io_clk_stop), | |
13600 | .tcu_mcu1_fbd_clk_stop(tcu_mcu1_fbd_clk_stop), | |
13601 | .tcu_mcu2_clk_stop(tcu_mcu2_clk_stop), | |
13602 | .tcu_mcu2_dr_clk_stop(tcu_mcu2_dr_clk_stop), | |
13603 | .tcu_mcu2_io_clk_stop(tcu_mcu2_io_clk_stop), | |
13604 | .tcu_mcu2_fbd_clk_stop(tcu_mcu2_fbd_clk_stop), | |
13605 | .tcu_mcu3_clk_stop(tcu_mcu3_clk_stop), | |
13606 | .tcu_mcu3_dr_clk_stop(tcu_mcu3_dr_clk_stop), | |
13607 | .tcu_mcu3_io_clk_stop(tcu_mcu3_io_clk_stop), | |
13608 | .tcu_mcu3_fbd_clk_stop(tcu_mcu3_fbd_clk_stop), | |
13609 | .tcu_ccx_clk_stop(tcu_ccx_clk_stop), | |
13610 | .tcu_sii_clk_stop(tcu_sii_clk_stop), | |
13611 | .tcu_sii_io_clk_stop(tcu_sii_io_clk_stop), | |
13612 | .tcu_sio_clk_stop(tcu_sio_clk_stop), | |
13613 | .tcu_sio_io_clk_stop(tcu_sio_io_clk_stop), | |
13614 | .tcu_ncu_clk_stop(tcu_ncu_clk_stop), | |
13615 | .tcu_ncu_io_clk_stop(tcu_ncu_io_clk_stop), | |
13616 | .tcu_efu_clk_stop(tcu_efu_clk_stop), | |
13617 | .tcu_efu_io_clk_stop(tcu_efu_io_clk_stop), | |
13618 | .tcu_rst_clk_stop(tcu_rst_clk_stop), | |
13619 | .tcu_rst_io_clk_stop(tcu_rst_io_clk_stop), | |
13620 | .tcu_dmu_io_clk_stop(tcu_dmu_io_clk_stop), | |
13621 | .tcu_rdp_io_clk_stop(tcu_rdp_io_clk_stop), | |
13622 | .tcu_mac_io_clk_stop(tcu_mac_io_clk_stop), | |
13623 | .tcu_rtx_io_clk_stop(tcu_rtx_io_clk_stop), | |
13624 | .tcu_tds_io_clk_stop(tcu_tds_io_clk_stop), | |
13625 | .tcu_peu_pc_clk_stop(tcu_peu_pc_clk_stop), | |
13626 | .tcu_peu_io_clk_stop(tcu_peu_io_clk_stop), | |
13627 | .tcu_mcu_testmode(tcu_mcu_testmode), | |
13628 | .tcu_dectest(tcu_dectest), | |
13629 | .tcu_muxtest(tcu_muxtest), | |
13630 | .tcu_sii_data(tcu_sii_data), | |
13631 | .tcu_sii_vld(tcu_sii_vld), | |
13632 | .sio_tcu_data(sio_tcu_data), | |
13633 | .sio_tcu_vld(sio_tcu_vld), | |
13634 | .tcu_efu_rowaddr(tcu_efu_rowaddr[6:0]), | |
13635 | .tcu_efu_coladdr(tcu_efu_coladdr[4:0]), | |
13636 | .tcu_efu_read_en(tcu_efu_read_en), | |
13637 | .tcu_efu_read_mode(tcu_efu_read_mode[2:0]), | |
13638 | .tcu_efu_read_start(tcu_efu_read_start), | |
13639 | .tcu_efu_fuse_bypass(tcu_efu_fuse_bypass), | |
13640 | .tcu_efu_dest_sample(tcu_efu_dest_sample), | |
13641 | .tcu_efu_data_in(tcu_efu_data_in), | |
13642 | .efu_tcu_data_out(efu_tcu_data_out), | |
13643 | .tcu_efu_updatedr(tcu_efu_updatedr), | |
13644 | .tcu_efu_shiftdr(tcu_efu_shiftdr), | |
13645 | .tcu_efu_capturedr(tcu_efu_capturedr), | |
13646 | .tck(tck), | |
13647 | .tcu_rst_efu_done(tcu_rst_efu_done), | |
13648 | .tcu_test_protect(tcu_test_protect), | |
13649 | .tcu_dbr_gateoff(tcu_dbr_gateoff), | |
13650 | .tcu_spc_mbist_start(tcu_spc_mbist_start[7:0]), | |
13651 | .tcu_mbist_bisi_en(tcu_mbist_bisi_en), | |
13652 | .tcu_mbist_user_mode(tcu_mbist_user_mode), | |
13653 | .spc1_tcu_mbist_done(spc1_tcu_mbist_done), | |
13654 | .spc1_tcu_mbist_fail(spc1_tcu_mbist_fail), | |
13655 | .spc3_tcu_mbist_done(spc3_tcu_mbist_done), | |
13656 | .spc3_tcu_mbist_fail(spc3_tcu_mbist_fail), | |
13657 | .spc4_tcu_mbist_done(spc4_tcu_mbist_done), | |
13658 | .spc4_tcu_mbist_fail(spc4_tcu_mbist_fail), | |
13659 | .spc5_tcu_mbist_done(spc5_tcu_mbist_done), | |
13660 | .spc5_tcu_mbist_fail(spc5_tcu_mbist_fail), | |
13661 | .spc6_tcu_mbist_done(spc6_tcu_mbist_done), | |
13662 | .spc6_tcu_mbist_fail(spc6_tcu_mbist_fail), | |
13663 | .spc7_tcu_mbist_done(spc7_tcu_mbist_done), | |
13664 | .spc7_tcu_mbist_fail(spc7_tcu_mbist_fail), | |
13665 | .tcu_sii_mbist_start(tcu_sii_mbist_start[1:0]), | |
13666 | .tcu_sii_mbist_scan_in(tcu_sii_mbist_scan_in), | |
13667 | .sii_tcu_mbist_scan_out(sii_tcu_mbist_scan_out), | |
13668 | .tcu_sio_mbist_start(tcu_sio_mbist_start[1:0]), | |
13669 | .tcu_sio_mbist_scan_in(tcu_sio_mbist_scan_in), | |
13670 | .sio_tcu_mbist_done(sio_tcu_mbist_done[1:0]), | |
13671 | .sio_tcu_mbist_fail(sio_tcu_mbist_fail[1:0]), | |
13672 | .sio_tcu_mbist_scan_out(sio_tcu_mbist_scan_out), | |
13673 | .tcu_ncu_mbist_start(tcu_ncu_mbist_start[1:0]), | |
13674 | .tcu_ncu_mbist_scan_in(tcu_ncu_mbist_scan_in), | |
13675 | .ncu_tcu_mbist_scan_out(ncu_tcu_mbist_scan_out), | |
13676 | .tcu_mcu0_mbist_start(tcu_mcu0_mbist_start), | |
13677 | .tcu_mcu0_mbist_scan_in(tcu_mcu0_mbist_scan_in), | |
13678 | .mcu0_tcu_mbist_scan_out(mcu0_tcu_mbist_scan_out), | |
13679 | .tcu_mcu1_mbist_start(tcu_mcu1_mbist_start), | |
13680 | .tcu_mcu1_mbist_scan_in(tcu_mcu1_mbist_scan_in), | |
13681 | .mcu1_tcu_mbist_scan_out(mcu1_tcu_mbist_scan_out), | |
13682 | .tcu_mcu2_mbist_start(tcu_mcu2_mbist_start), | |
13683 | .tcu_mcu2_mbist_scan_in(tcu_mcu2_mbist_scan_in), | |
13684 | .mcu2_tcu_mbist_done(mcu2_tcu_mbist_done), | |
13685 | .mcu2_tcu_mbist_fail(mcu2_tcu_mbist_fail), | |
13686 | .mcu2_tcu_mbist_scan_out(mcu2_tcu_mbist_scan_out), | |
13687 | .tcu_mcu3_mbist_start(tcu_mcu3_mbist_start), | |
13688 | .tcu_mcu3_mbist_scan_in(tcu_mcu3_mbist_scan_in), | |
13689 | .mcu3_tcu_mbist_done(mcu3_tcu_mbist_done), | |
13690 | .mcu3_tcu_mbist_fail(mcu3_tcu_mbist_fail), | |
13691 | .mcu3_tcu_mbist_scan_out(mcu3_tcu_mbist_scan_out), | |
13692 | .tcu_l2b0_mbist_start(tcu_l2b0_mbist_start), | |
13693 | .tcu_l2b0_mbist_scan_in(tcu_l2b0_mbist_scan_in), | |
13694 | .l2b0_tcu_mbist_scan_out(l2b0_tcu_mbist_scan_out), | |
13695 | .tcu_l2b1_mbist_start(tcu_l2b1_mbist_start), | |
13696 | .tcu_l2b1_mbist_scan_in(tcu_l2b1_mbist_scan_in), | |
13697 | .l2b1_tcu_mbist_scan_out(l2b1_tcu_mbist_scan_out), | |
13698 | .tcu_l2b2_mbist_start(tcu_l2b2_mbist_start), | |
13699 | .tcu_l2b2_mbist_scan_in(tcu_l2b2_mbist_scan_in), | |
13700 | .l2b2_tcu_mbist_scan_out(l2b2_tcu_mbist_scan_out), | |
13701 | .tcu_l2b3_mbist_start(tcu_l2b3_mbist_start), | |
13702 | .tcu_l2b3_mbist_scan_in(tcu_l2b3_mbist_scan_in), | |
13703 | .l2b3_tcu_mbist_scan_out(l2b3_tcu_mbist_scan_out), | |
13704 | .tcu_l2b4_mbist_start(tcu_l2b4_mbist_start), | |
13705 | .tcu_l2b4_mbist_scan_in(tcu_l2b4_mbist_scan_in), | |
13706 | .l2b4_tcu_mbist_done(l2b4_tcu_mbist_done), | |
13707 | .l2b4_tcu_mbist_fail(l2b4_tcu_mbist_fail), | |
13708 | .l2b4_tcu_mbist_scan_out(l2b4_tcu_mbist_scan_out), | |
13709 | .tcu_l2b5_mbist_start(tcu_l2b5_mbist_start), | |
13710 | .tcu_l2b5_mbist_scan_in(tcu_l2b5_mbist_scan_in), | |
13711 | .l2b5_tcu_mbist_done(l2b5_tcu_mbist_done), | |
13712 | .l2b5_tcu_mbist_fail(l2b5_tcu_mbist_fail), | |
13713 | .l2b5_tcu_mbist_scan_out(l2b5_tcu_mbist_scan_out), | |
13714 | .tcu_l2b6_mbist_start(tcu_l2b6_mbist_start), | |
13715 | .tcu_l2b6_mbist_scan_in(tcu_l2b6_mbist_scan_in), | |
13716 | .l2b6_tcu_mbist_done(l2b6_tcu_mbist_done), | |
13717 | .l2b6_tcu_mbist_fail(l2b6_tcu_mbist_fail), | |
13718 | .l2b6_tcu_mbist_scan_out(l2b6_tcu_mbist_scan_out), | |
13719 | .tcu_l2b7_mbist_start(tcu_l2b7_mbist_start), | |
13720 | .tcu_l2b7_mbist_scan_in(tcu_l2b7_mbist_scan_in), | |
13721 | .l2b7_tcu_mbist_done(l2b7_tcu_mbist_done), | |
13722 | .l2b7_tcu_mbist_fail(l2b7_tcu_mbist_fail), | |
13723 | .l2b7_tcu_mbist_scan_out(l2b7_tcu_mbist_scan_out), | |
13724 | .tcu_l2t0_mbist_start(tcu_l2t0_mbist_start), | |
13725 | .tcu_l2t0_mbist_scan_in(tcu_l2t0_mbist_scan_in), | |
13726 | .l2t0_tcu_mbist_scan_out(l2t0_tcu_mbist_scan_out), | |
13727 | .tcu_l2t1_mbist_start(tcu_l2t1_mbist_start), | |
13728 | .tcu_l2t1_mbist_scan_in(tcu_l2t1_mbist_scan_in), | |
13729 | .l2t1_tcu_mbist_done(l2t1_tcu_mbist_done), | |
13730 | .l2t1_tcu_mbist_fail(l2t1_tcu_mbist_fail), | |
13731 | .l2t1_tcu_mbist_scan_out(l2t1_tcu_mbist_scan_out), | |
13732 | .tcu_l2t2_mbist_start(tcu_l2t2_mbist_start), | |
13733 | .tcu_l2t2_mbist_scan_in(tcu_l2t2_mbist_scan_in), | |
13734 | .l2t2_tcu_mbist_scan_out(l2t2_tcu_mbist_scan_out), | |
13735 | .tcu_l2t3_mbist_start(tcu_l2t3_mbist_start), | |
13736 | .tcu_l2t3_mbist_scan_in(tcu_l2t3_mbist_scan_in), | |
13737 | .l2t3_tcu_mbist_done(l2t3_tcu_mbist_done), | |
13738 | .l2t3_tcu_mbist_fail(l2t3_tcu_mbist_fail), | |
13739 | .l2t3_tcu_mbist_scan_out(l2t3_tcu_mbist_scan_out), | |
13740 | .tcu_l2t4_mbist_start(tcu_l2t4_mbist_start), | |
13741 | .tcu_l2t4_mbist_scan_in(tcu_l2t4_mbist_scan_in), | |
13742 | .l2t4_tcu_mbist_done(l2t4_tcu_mbist_done), | |
13743 | .l2t4_tcu_mbist_fail(l2t4_tcu_mbist_fail), | |
13744 | .l2t4_tcu_mbist_scan_out(l2t4_tcu_mbist_scan_out), | |
13745 | .tcu_l2t5_mbist_start(tcu_l2t5_mbist_start), | |
13746 | .tcu_l2t5_mbist_scan_in(tcu_l2t5_mbist_scan_in), | |
13747 | .l2t5_tcu_mbist_done(l2t5_tcu_mbist_done), | |
13748 | .l2t5_tcu_mbist_fail(l2t5_tcu_mbist_fail), | |
13749 | .l2t5_tcu_mbist_scan_out(l2t5_tcu_mbist_scan_out), | |
13750 | .tcu_l2t6_mbist_start(tcu_l2t6_mbist_start), | |
13751 | .tcu_l2t6_mbist_scan_in(tcu_l2t6_mbist_scan_in), | |
13752 | .l2t6_tcu_mbist_done(l2t6_tcu_mbist_done), | |
13753 | .l2t6_tcu_mbist_fail(l2t6_tcu_mbist_fail), | |
13754 | .l2t6_tcu_mbist_scan_out(l2t6_tcu_mbist_scan_out), | |
13755 | .tcu_l2t7_mbist_start(tcu_l2t7_mbist_start), | |
13756 | .tcu_l2t7_mbist_scan_in(tcu_l2t7_mbist_scan_in), | |
13757 | .l2t7_tcu_mbist_done(l2t7_tcu_mbist_done), | |
13758 | .l2t7_tcu_mbist_fail(l2t7_tcu_mbist_fail), | |
13759 | .l2t7_tcu_mbist_scan_out(l2t7_tcu_mbist_scan_out), | |
13760 | .tcu_dmu_mbist_start(tcu_dmu_mbist_start[1:0]), | |
13761 | .tcu_dmu_mbist_scan_in(tcu_dmu_mbist_scan_in), | |
13762 | .dmu_tcu_mbist_done(dmu_tcu_mbist_done[1:0]), | |
13763 | .dmu_tcu_mbist_fail(dmu_tcu_mbist_fail[1:0]), | |
13764 | .dmu_tcu_mbist_scan_out(dmu_tcu_mbist_scan_out), | |
13765 | .tcu_peu_mbist_start(tcu_peu_mbist_start), | |
13766 | .tcu_peu_mbist_scan_in(tcu_peu_mbist_scan_in), | |
13767 | .peu_tcu_mbist_done(peu_tcu_mbist_done), | |
13768 | .peu_tcu_mbist_fail(peu_tcu_mbist_fail), | |
13769 | .peu_tcu_mbist_scan_out(peu_tcu_mbist_scan_out), | |
13770 | .tcu_rdp_rdmc_mbist_start(tcu_rdp_rdmc_mbist_start), | |
13771 | .tcu_rtx_rxc_ipp0_mbist_start(tcu_rtx_rxc_ipp0_mbist_start), | |
13772 | .tcu_rtx_rxc_ipp1_mbist_start(tcu_rtx_rxc_ipp1_mbist_start), | |
13773 | .tcu_rtx_rxc_mb5_mbist_start(tcu_rtx_rxc_mb5_mbist_start), | |
13774 | .tcu_rtx_rxc_mb6_mbist_start(tcu_rtx_rxc_mb6_mbist_start), | |
13775 | .tcu_rtx_rxc_zcp0_mbist_start(tcu_rtx_rxc_zcp0_mbist_start), | |
13776 | .tcu_rtx_rxc_zcp1_mbist_start(tcu_rtx_rxc_zcp1_mbist_start), | |
13777 | .tcu_rtx_txc_txe0_mbist_start(tcu_rtx_txc_txe0_mbist_start), | |
13778 | .tcu_rtx_txc_txe1_mbist_start(tcu_rtx_txc_txe1_mbist_start), | |
13779 | .tcu_tds_smx_mbist_start(tcu_tds_smx_mbist_start), | |
13780 | .tcu_tds_tdmc_mbist_start(tcu_tds_tdmc_mbist_start), | |
13781 | .rtx_mbist_scan_in(rtx_mbist_scan_in), | |
13782 | .rdp_rdmc_mbist_scan_in(rdp_rdmc_mbist_scan_in), | |
13783 | .tds_mbist_scan_in(tds_mbist_scan_in), | |
13784 | .rtx_mbist_scan_out(rtx_mbist_scan_out), | |
13785 | .rdp_rdmc_mbist_scan_out(rdp_rdmc_mbist_scan_out), | |
13786 | .tds_mbist_scan_out(tds_mbist_scan_out), | |
13787 | .rdp_rdmc_tcu_mbist_done(rdp_rdmc_tcu_mbist_done), | |
13788 | .rtx_rxc_ipp0_tcu_mbist_done(rtx_rxc_ipp0_tcu_mbist_done), | |
13789 | .rtx_rxc_ipp1_tcu_mbist_done(rtx_rxc_ipp1_tcu_mbist_done), | |
13790 | .rtx_rxc_mb5_tcu_mbist_done(rtx_rxc_mb5_tcu_mbist_done), | |
13791 | .rtx_rxc_mb6_tcu_mbist_done(rtx_rxc_mb6_tcu_mbist_done), | |
13792 | .rtx_rxc_zcp0_tcu_mbist_done(rtx_rxc_zcp0_tcu_mbist_done), | |
13793 | .rtx_rxc_zcp1_tcu_mbist_done(rtx_rxc_zcp1_tcu_mbist_done), | |
13794 | .rtx_txc_txe0_tcu_mbist_done(rtx_txc_txe0_tcu_mbist_done), | |
13795 | .rtx_txc_txe1_tcu_mbist_done(rtx_txc_txe1_tcu_mbist_done), | |
13796 | .tds_smx_tcu_mbist_done(tds_smx_tcu_mbist_done), | |
13797 | .tds_tdmc_tcu_mbist_done(tds_tdmc_tcu_mbist_done), | |
13798 | .rdp_rdmc_tcu_mbist_fail(rdp_rdmc_tcu_mbist_fail), | |
13799 | .rtx_rxc_ipp0_tcu_mbist_fail(rtx_rxc_ipp0_tcu_mbist_fail), | |
13800 | .rtx_rxc_ipp1_tcu_mbist_fail(rtx_rxc_ipp1_tcu_mbist_fail), | |
13801 | .rtx_rxc_mb5_tcu_mbist_fail(rtx_rxc_mb5_tcu_mbist_fail), | |
13802 | .rtx_rxc_mb6_tcu_mbist_fail(rtx_rxc_mb6_tcu_mbist_fail), | |
13803 | .rtx_rxc_zcp0_tcu_mbist_fail(rtx_rxc_zcp0_tcu_mbist_fail), | |
13804 | .rtx_rxc_zcp1_tcu_mbist_fail(rtx_rxc_zcp1_tcu_mbist_fail), | |
13805 | .rtx_txc_txe0_tcu_mbist_fail(rtx_txc_txe0_tcu_mbist_fail), | |
13806 | .rtx_txc_txe1_tcu_mbist_fail(rtx_txc_txe1_tcu_mbist_fail), | |
13807 | .tds_smx_tcu_mbist_fail(tds_smx_tcu_mbist_fail), | |
13808 | .tds_tdmc_tcu_mbist_fail(tds_tdmc_tcu_mbist_fail), | |
13809 | .dmo_dcmuxctl(dmo_dcmuxctl), | |
13810 | .dmo_icmuxctl(dmo_icmuxctl), | |
13811 | .spc4_dmo_dout(spc4_dmo_dout[35:0]), | |
13812 | .spc6_dmo_dout(spc6_dmo_dout[35:0]), | |
13813 | .l2t4_dmo_dout(l2t4_dmo_dout[38:0]), | |
13814 | .l2t6_dmo_dout(l2t6_dmo_dout[38:0]), | |
13815 | .dmo_l2tsel(dmo_l2tsel[5:0]), | |
13816 | .dmo_tagmuxctl(dmo_tagmuxctl), | |
13817 | .rtx_tcu_dmo_data_out(rtx_tcu_dmo_data_out[39:0]), | |
13818 | .tds_tcu_dmo_dout(tds_tcu_dmo_dout[39:0]), | |
13819 | .rdp_tcu_dmo_dout(rdp_tcu_dmo_dout[39:0]), | |
13820 | .tcu_rtx_dmo_ctl(tcu_rtx_dmo_ctl[2:0]), | |
13821 | .spc0_tcu_shscan_scan_in(spc0_tcu_shscan_scan_in), | |
13822 | .tcu_spc0_shscan_scan_out(tcu_spc0_shscan_scan_out), | |
13823 | .spc1_tcu_shscan_scan_in(spc1_tcu_shscan_scan_in), | |
13824 | .tcu_spc1_shscan_scan_out(tcu_spc1_shscan_scan_out), | |
13825 | .spc2_tcu_shscan_scan_in(spc2_tcu_shscan_scan_in), | |
13826 | .tcu_spc2_shscan_scan_out(tcu_spc2_shscan_scan_out), | |
13827 | .spc3_tcu_shscan_scan_in(spc3_tcu_shscan_scan_in), | |
13828 | .tcu_spc3_shscan_scan_out(tcu_spc3_shscan_scan_out), | |
13829 | .spc4_tcu_shscan_scan_in(spc4_tcu_shscan_scan_in), | |
13830 | .tcu_spc4_shscan_scan_out(tcu_spc4_shscan_scan_out), | |
13831 | .spc5_tcu_shscan_scan_in(spc5_tcu_shscan_scan_in), | |
13832 | .tcu_spc5_shscan_scan_out(tcu_spc5_shscan_scan_out), | |
13833 | .spc6_tcu_shscan_scan_in(spc6_tcu_shscan_scan_in), | |
13834 | .tcu_spc6_shscan_scan_out(tcu_spc6_shscan_scan_out), | |
13835 | .spc7_tcu_shscan_scan_in(spc7_tcu_shscan_scan_in), | |
13836 | .tcu_spc7_shscan_scan_out(tcu_spc7_shscan_scan_out), | |
13837 | .tcu_spc_shscan_aclk(tcu_spc_shscan_aclk), | |
13838 | .tcu_spc_shscan_bclk(tcu_spc_shscan_bclk), | |
13839 | .tcu_spc_shscan_scan_en(tcu_spc_shscan_scan_en), | |
13840 | .tcu_spc_shscan_pce_ov(tcu_spc_shscan_pce_ov), | |
13841 | .tcu_spc0_shscan_clk_stop(tcu_spc0_shscan_clk_stop), | |
13842 | .tcu_spc1_shscan_clk_stop(tcu_spc1_shscan_clk_stop), | |
13843 | .tcu_spc2_shscan_clk_stop(tcu_spc2_shscan_clk_stop), | |
13844 | .tcu_spc3_shscan_clk_stop(tcu_spc3_shscan_clk_stop), | |
13845 | .tcu_spc4_shscan_clk_stop(tcu_spc4_shscan_clk_stop), | |
13846 | .tcu_spc5_shscan_clk_stop(tcu_spc5_shscan_clk_stop), | |
13847 | .tcu_spc6_shscan_clk_stop(tcu_spc6_shscan_clk_stop), | |
13848 | .tcu_spc7_shscan_clk_stop(tcu_spc7_shscan_clk_stop), | |
13849 | .tcu_spc_shscanid(tcu_spc_shscanid[2:0]), | |
13850 | .tcu_l2t0_shscan_scan_in(tcu_l2t0_shscan_scan_in), | |
13851 | .tcu_l2t1_shscan_scan_in(tcu_l2t1_shscan_scan_in), | |
13852 | .tcu_l2t2_shscan_scan_in(tcu_l2t2_shscan_scan_in), | |
13853 | .tcu_l2t3_shscan_scan_in(tcu_l2t3_shscan_scan_in), | |
13854 | .tcu_l2t4_shscan_scan_in(tcu_l2t4_shscan_scan_in), | |
13855 | .tcu_l2t5_shscan_scan_in(tcu_l2t5_shscan_scan_in), | |
13856 | .tcu_l2t6_shscan_scan_in(tcu_l2t6_shscan_scan_in), | |
13857 | .tcu_l2t7_shscan_scan_in(tcu_l2t7_shscan_scan_in), | |
13858 | .tcu_l2t_shscan_aclk(tcu_l2t_shscan_aclk), | |
13859 | .tcu_l2t_shscan_bclk(tcu_l2t_shscan_bclk), | |
13860 | .tcu_l2t_shscan_scan_en(tcu_l2t_shscan_scan_en), | |
13861 | .tcu_l2t_shscan_pce_ov(tcu_l2t_shscan_pce_ov), | |
13862 | .tcu_l2t0_shscan_clk_stop(tcu_l2t0_shscan_clk_stop), | |
13863 | .tcu_l2t1_shscan_clk_stop(tcu_l2t1_shscan_clk_stop), | |
13864 | .tcu_l2t2_shscan_clk_stop(tcu_l2t2_shscan_clk_stop), | |
13865 | .tcu_l2t3_shscan_clk_stop(tcu_l2t3_shscan_clk_stop), | |
13866 | .tcu_l2t4_shscan_clk_stop(tcu_l2t4_shscan_clk_stop), | |
13867 | .tcu_l2t5_shscan_clk_stop(tcu_l2t5_shscan_clk_stop), | |
13868 | .tcu_l2t6_shscan_clk_stop(tcu_l2t6_shscan_clk_stop), | |
13869 | .tcu_l2t7_shscan_clk_stop(tcu_l2t7_shscan_clk_stop), | |
13870 | .tcu_ss_mode(tcu_ss_mode[7:0]), | |
13871 | .tcu_do_mode(tcu_do_mode[7:0]), | |
13872 | .tcu_ss_request(tcu_ss_request[7:0]), | |
13873 | .spc1_ss_complete(spc1_ss_complete), | |
13874 | .spc3_ss_complete(spc3_ss_complete), | |
13875 | .spc4_ss_complete(spc4_ss_complete), | |
13876 | .spc5_ss_complete(spc5_ss_complete), | |
13877 | .spc6_ss_complete(spc6_ss_complete), | |
13878 | .spc7_ss_complete(spc7_ss_complete), | |
13879 | .spc1_softstop_request(spc1_softstop_request), | |
13880 | .spc3_softstop_request(spc3_softstop_request), | |
13881 | .spc4_softstop_request(spc4_softstop_request), | |
13882 | .spc5_softstop_request(spc5_softstop_request), | |
13883 | .spc6_softstop_request(spc6_softstop_request), | |
13884 | .spc7_softstop_request(spc7_softstop_request), | |
13885 | .spc1_hardstop_request(spc1_hardstop_request), | |
13886 | .spc3_hardstop_request(spc3_hardstop_request), | |
13887 | .spc4_hardstop_request(spc4_hardstop_request), | |
13888 | .spc5_hardstop_request(spc5_hardstop_request), | |
13889 | .spc6_hardstop_request(spc6_hardstop_request), | |
13890 | .spc7_hardstop_request(spc7_hardstop_request), | |
13891 | .spc0_ncu_core_running_status(spc0_ncu_core_running_status[7:0]), | |
13892 | .spc1_ncu_core_running_status(spc1_ncu_core_running_status[7:0]), | |
13893 | .spc2_ncu_core_running_status(spc2_ncu_core_running_status[7:0]), | |
13894 | .spc3_ncu_core_running_status(spc3_ncu_core_running_status[7:0]), | |
13895 | .spc4_ncu_core_running_status(spc4_ncu_core_running_status[7:0]), | |
13896 | .spc5_ncu_core_running_status(spc5_ncu_core_running_status[7:0]), | |
13897 | .spc6_ncu_core_running_status(spc6_ncu_core_running_status[7:0]), | |
13898 | .spc7_ncu_core_running_status(spc7_ncu_core_running_status[7:0]), | |
13899 | .spc1_trigger_pulse(spc1_trigger_pulse), | |
13900 | .spc3_trigger_pulse(spc3_trigger_pulse), | |
13901 | .spc4_trigger_pulse(spc4_trigger_pulse), | |
13902 | .spc5_trigger_pulse(spc5_trigger_pulse), | |
13903 | .spc6_trigger_pulse(spc6_trigger_pulse), | |
13904 | .spc7_trigger_pulse(spc7_trigger_pulse), | |
13905 | .rst_tcu_flush_init_req(rst_tcu_flush_init_req), | |
13906 | .rst_tcu_flush_stop_req(rst_tcu_flush_stop_req), | |
13907 | .rst_tcu_asicflush_stop_req(rst_tcu_asicflush_stop_req), | |
13908 | .tcu_rst_asicflush_stop_ack(tcu_rst_asicflush_stop_ack), | |
13909 | .tcu_rst_flush_init_ack(tcu_rst_flush_init_ack), | |
13910 | .tcu_rst_flush_stop_ack(tcu_rst_flush_stop_ack), | |
13911 | .rst_wmr_protect(rst_wmr_protect), | |
13912 | .tcu_bisx_done(tcu_bisx_done), | |
13913 | .tcu_rst_scan_mode(tcu_rst_scan_mode), | |
13914 | .rst_tcu_clk_stop(rst_tcu_clk_stop), | |
13915 | .rst_tcu_dbr_gen(rst_tcu_dbr_gen), | |
13916 | .ncu_spc0_core_available(ncu_spc0_core_available), | |
13917 | .ncu_spc1_core_available(ncu_spc1_core_available), | |
13918 | .ncu_spc2_core_available(ncu_spc2_core_available), | |
13919 | .ncu_spc3_core_available(ncu_spc3_core_available), | |
13920 | .ncu_spc4_core_available(ncu_spc4_core_available), | |
13921 | .ncu_spc5_core_available(ncu_spc5_core_available), | |
13922 | .ncu_spc6_core_available(ncu_spc6_core_available), | |
13923 | .ncu_spc7_core_available(ncu_spc7_core_available), | |
13924 | .ncu_tcu_bank_avail(ncu_tcu_bank_avail[7:0]), | |
13925 | .ncu_spc_pm(ncu_spc_pm), | |
13926 | .ncu_spc_ba01(ncu_spc_ba01), | |
13927 | .ncu_spc_ba23(ncu_spc_ba23), | |
13928 | .ncu_spc_ba45(ncu_spc_ba45), | |
13929 | .ncu_spc_ba67(ncu_spc_ba67), | |
13930 | .tcu_se_scancollar_in(tcu_se_scancollar_in), | |
13931 | .tcu_se_scancollar_out(tcu_se_scancollar_out), | |
13932 | .tcu_array_bypass(tcu_array_bypass), | |
13933 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit), | |
13934 | .tcu_mio_pins_scan_out(tcu_mio_pins_scan_out[30:0]), | |
13935 | .tcu_mio_dmo_data(tcu_mio_dmo_data[39:0]), | |
13936 | .tcu_mio_mbist_done(tcu_mio_mbist_done), | |
13937 | .tcu_mio_mbist_fail(tcu_mio_mbist_fail), | |
13938 | .tcu_mio_trigout(tcu_mio_trigout), | |
13939 | .tcu_mio_jtag_membist_mode(tcu_mio_jtag_membist_mode), | |
13940 | .tcu_mio_clk_stop(tcu_mio_clk_stop), | |
13941 | .tcu_mio_bs_scan_in(tcu_mio_bs_scan_in), | |
13942 | .tcu_mio_bs_scan_en(tcu_mio_bs_scan_en), | |
13943 | .tcu_mio_bs_clk(tcu_mio_bs_clk), | |
13944 | .tcu_mio_bs_aclk(tcu_mio_bs_aclk), | |
13945 | .tcu_mio_bs_bclk(tcu_mio_bs_bclk), | |
13946 | .tcu_mio_bs_uclk(tcu_mio_bs_uclk), | |
13947 | .tcu_mio_bs_mode_ctl(tcu_mio_bs_mode_ctl), | |
13948 | .tcu_mio_dmo_sync(tcu_mio_dmo_sync), | |
13949 | .tcu_stciclk(tcu_stciclk), | |
13950 | .tcu_stcicfg(tcu_stcicfg[1:0]), | |
13951 | .tcu_stcid(tcu_stcid), | |
13952 | .tcu_srd_atpgse(tcu_srd_atpgse), | |
13953 | .tcu_srd_atpgmode(tcu_srd_atpgmode[2:0]), | |
13954 | .tcu_sbs_enbstx(tcu_sbs_enbstx), | |
13955 | .tcu_sbs_enbsrx(tcu_sbs_enbsrx), | |
13956 | .tcu_sbs_scan_en(tcu_sbs_scan_en), | |
13957 | .tcu_sbs_clk(tcu_sbs_clk), | |
13958 | .tcu_sbs_aclk(tcu_sbs_aclk), | |
13959 | .tcu_sbs_bclk(tcu_sbs_bclk), | |
13960 | .tcu_sbs_uclk(tcu_sbs_uclk), | |
13961 | .tcu_sbs_scan_in(tcu_sbs_scan_in), | |
13962 | .tcu_sbs_acmode(tcu_sbs_acmode), | |
13963 | .tcu_sbs_actestsignal(tcu_sbs_actestsignal), | |
13964 | .tcu_sbs_enbspt(tcu_sbs_enbspt), | |
13965 | .tcu_sbs_bsinitclk(tcu_sbs_bsinitclk), | |
13966 | .tcu_peu_entestcfg(tcu_peu_entestcfg), | |
13967 | .tcu_mio_scan_out31(tcu_mio_scan_out31), | |
13968 | .mio_tcu_scan_in31(mio_tcu_scan_in31), | |
13969 | .mio_tcu_stciclk(mio_tcu_stciclk), | |
13970 | .mio_tcu_stcicfg(mio_tcu_stcicfg[1:0]), | |
13971 | .mio_tcu_stcid(mio_tcu_stcid), | |
13972 | .tcu_mio_stciq(tcu_mio_stciq), | |
13973 | .mio_tcu_io_ac_testmode(mio_tcu_io_ac_testmode), | |
13974 | .mio_tcu_io_ac_testtrig(mio_tcu_io_ac_testtrig), | |
13975 | .mio_tcu_io_aclk(mio_tcu_io_aclk), | |
13976 | .mio_tcu_io_bclk(mio_tcu_io_bclk), | |
13977 | .mio_tcu_io_scan_in(mio_tcu_io_scan_in[30:0]), | |
13978 | .mio_tcu_io_scan_en(mio_tcu_io_scan_en), | |
13979 | .mio_tcu_trigin(mio_tcu_trigin), | |
13980 | .mio_tcu_bs_scan_out(mio_tcu_bs_scan_out), | |
13981 | .mio_ext_cmp_clk(mio_ext_cmp_clk), | |
13982 | .mio_ext_dr_clk(mio_ext_dr_clk), | |
13983 | .mio_tcu_peu_clk_ext(mio_tcu_peu_clk_ext), | |
13984 | .mio_tcu_niu_clk_ext(mio_tcu_niu_clk_ext[5:0]), | |
13985 | .tcu_peu_clk_ext(tcu_peu_clk_ext), | |
13986 | .tcu_ccu_ext_cmp_clk(tcu_ccu_ext_cmp_clk), | |
13987 | .tcu_ccu_ext_dr_clk(tcu_ccu_ext_dr_clk), | |
13988 | .mac_125rx_test_clk(mac_125rx_test_clk), | |
13989 | .mac_125tx_test_clk(mac_125tx_test_clk), | |
13990 | .mac_156rx_test_clk(mac_156rx_test_clk), | |
13991 | .mac_156tx_test_clk(mac_156tx_test_clk), | |
13992 | .mac_312rx_test_clk(mac_312rx_test_clk), | |
13993 | .mac_312tx_test_clk(mac_312tx_test_clk), | |
13994 | .tcu_peu_testmode(tcu_peu_testmode), | |
13995 | .tcu_mac_testmode(tcu_mac_testmode), | |
13996 | .mio_tcu_divider_bypass(mio_tcu_divider_bypass), | |
13997 | .mio_tcu_pll_cmp_bypass(mio_tcu_pll_cmp_bypass), | |
13998 | .tcu_div_bypass(tcu_div_bypass), | |
13999 | .tcu_ccu_mux_sel(tcu_ccu_mux_sel[1:0]), | |
14000 | .tcu_ccu_clk_stretch(tcu_ccu_clk_stretch), | |
14001 | .tcu_mio_bs_highz_l(tcu_mio_bs_highz_l), | |
14002 | .dbg1_tcu_soc_hard_stop(dbg1_tcu_soc_hard_stop), | |
14003 | .dbg1_tcu_soc_asrt_trigout(dbg1_tcu_soc_asrt_trigout), | |
14004 | .tcu_db0_clk_stop(tcu_db0_clk_stop), | |
14005 | .tcu_db1_clk_stop(tcu_db1_clk_stop), | |
14006 | .tcu_spc_lbist_start(tcu_spc_lbist_start[7:0]), | |
14007 | .tcu_spc_lbist_scan_in(tcu_spc_lbist_scan_in[7:0]), | |
14008 | .tcu_spc_lbist_pgm(tcu_spc_lbist_pgm), | |
14009 | .tcu_spc0_test_mode(tcu_spc0_test_mode), | |
14010 | .tcu_spc1_test_mode(tcu_spc1_test_mode), | |
14011 | .tcu_spc2_test_mode(tcu_spc2_test_mode), | |
14012 | .tcu_spc3_test_mode(tcu_spc3_test_mode), | |
14013 | .tcu_spc4_test_mode(tcu_spc4_test_mode), | |
14014 | .tcu_spc5_test_mode(tcu_spc5_test_mode), | |
14015 | .tcu_spc6_test_mode(tcu_spc6_test_mode), | |
14016 | .tcu_spc7_test_mode(tcu_spc7_test_mode), | |
14017 | .tcu_atpg_mode(tcu_atpg_mode), | |
14018 | .spc0_tcu_lbist_done(spc0_tcu_lbist_done), | |
14019 | .spc1_tcu_lbist_done(spc1_tcu_lbist_done), | |
14020 | .spc2_tcu_lbist_done(spc2_tcu_lbist_done), | |
14021 | .spc3_tcu_lbist_done(spc3_tcu_lbist_done), | |
14022 | .spc4_tcu_lbist_done(spc4_tcu_lbist_done), | |
14023 | .spc5_tcu_lbist_done(spc5_tcu_lbist_done), | |
14024 | .spc6_tcu_lbist_done(spc6_tcu_lbist_done), | |
14025 | .spc7_tcu_lbist_done(spc7_tcu_lbist_done), | |
14026 | .spc0_tcu_lbist_scan_out(spc0_tcu_lbist_scan_out), | |
14027 | .spc1_tcu_lbist_scan_out(spc1_tcu_lbist_scan_out), | |
14028 | .spc2_tcu_lbist_scan_out(spc2_tcu_lbist_scan_out), | |
14029 | .spc3_tcu_lbist_scan_out(spc3_tcu_lbist_scan_out), | |
14030 | .spc4_tcu_lbist_scan_out(spc4_tcu_lbist_scan_out), | |
14031 | .spc5_tcu_lbist_scan_out(spc5_tcu_lbist_scan_out), | |
14032 | .spc6_tcu_lbist_scan_out(spc6_tcu_lbist_scan_out), | |
14033 | .spc7_tcu_lbist_scan_out(spc7_tcu_lbist_scan_out) | |
14034 | ||
14035 | ); | |
14036 | `endif // OPENSPARC_CMP | |
14037 | ||
14038 | ||
14039 | ||
14040 | // leave this instance out of cmp model | |
14041 | `ifdef OPENSPARC_CMP | |
14042 | `else | |
14043 | dmu dmu( | |
14044 | ||
14045 | .rst_por_ (gl_dmu_peu_por_c3b ), | |
14046 | .rst_wmr_ (gl_dmu_peu_wmr_c3b ), | |
14047 | .tcu_array_bypass (tcu_array_bypass ), | |
14048 | //.tcu_soc6io_clk_stop (tcu_dmu_io_clk_stop ), | |
14049 | .tcu_aclk ( tcu_asic_aclk ), | |
14050 | .tcu_bclk ( tcu_asic_bclk ), | |
14051 | .tcu_scan_en ( tcu_asic_scan_en ), | |
14052 | .tcu_se_scancollar_in ( tcu_asic_se_scancollar_in ), | |
14053 | .tcu_se_scancollar_out ( tcu_asic_se_scancollar_out), | |
14054 | .tcu_array_wr_inhibit ( tcu_asic_array_wr_inhibit ), | |
14055 | .scan_in (tcu_socd_scan_out ), | |
14056 | .scan_out (dmu_scan_out ), | |
14057 | .sii_dmu_wrack_par (sii_dmu_wrack_parity), | |
14058 | .gclk ( cmp_gclk_c3_dmu ), // cmp_gclk_c0_r[0] ), | |
14059 | .tcu_dmu_io_clk_stop ( gl_dmu_io_clk_stop ), // staged clk_stop | |
14060 | .ccu_io_out ( gl_io_out_c3b ), | |
14061 | .tcu_pce_ov(tcu_pce_ov), | |
14062 | .tcu_div_bypass(tcu_div_bypass), | |
14063 | .tcu_test_protect(tcu_test_protect), | |
14064 | .cluster_arst_l(cluster_arst_l), | |
14065 | .ccu_serdes_dtm(ccu_serdes_dtm), | |
14066 | .ncu_dmu_data(ncu_dmu_data[31:0]), | |
14067 | .ncu_dmu_mmu_addr_vld(ncu_dmu_mmu_addr_vld), | |
14068 | .ncu_dmu_mondo_ack(ncu_dmu_mondo_ack), | |
14069 | .ncu_dmu_mondo_id(ncu_dmu_mondo_id[5:0]), | |
14070 | .ncu_dmu_mondo_nack(ncu_dmu_mondo_nack), | |
14071 | .ncu_dmu_pio_data(ncu_dmu_pio_data[63:0]), | |
14072 | .ncu_dmu_pio_hdr_vld(ncu_dmu_pio_hdr_vld), | |
14073 | .ncu_dmu_stall(ncu_dmu_stall), | |
14074 | .ncu_dmu_vld(ncu_dmu_vld), | |
14075 | .ncu_dmu_mondo_id_par(ncu_dmu_mondo_id_par), | |
14076 | .ncu_dmu_d_pei(ncu_dmu_d_pei), | |
14077 | .ncu_dmu_siicr_pei(ncu_dmu_siicr_pei), | |
14078 | .ncu_dmu_ctag_uei(ncu_dmu_ctag_uei), | |
14079 | .ncu_dmu_ctag_cei(ncu_dmu_ctag_cei), | |
14080 | .ncu_dmu_ncucr_pei(ncu_dmu_ncucr_pei), | |
14081 | .ncu_dmu_iei(ncu_dmu_iei), | |
14082 | .p2d_ce_int(p2d_ce_int), | |
14083 | .p2d_csr_ack(p2d_csr_ack), | |
14084 | .p2d_csr_rcd(p2d_csr_rcd[95:0]), | |
14085 | .p2d_csr_req(p2d_csr_req), | |
14086 | .p2d_cto_req(p2d_cto_req), | |
14087 | .p2d_cto_tag(p2d_cto_tag[4:0]), | |
14088 | .p2d_drain(p2d_drain), | |
14089 | .p2d_ecd_rptr(p2d_ecd_rptr[7:0]), | |
14090 | .p2d_ech_rptr(p2d_ech_rptr[5:0]), | |
14091 | .p2d_erd_rptr(p2d_erd_rptr[7:0]), | |
14092 | .p2d_erh_rptr(p2d_erh_rptr[5:0]), | |
14093 | .p2d_ibc_ack(p2d_ibc_ack), | |
14094 | .p2d_idb_data(p2d_idb_data[127:0]), | |
14095 | .p2d_idb_dpar(p2d_idb_dpar[3:0]), | |
14096 | .p2d_ihb_data(p2d_ihb_data[127:0]), | |
14097 | .p2d_ihb_dpar(p2d_ihb_dpar[3:0]), | |
14098 | .d2p_ihb_rd(d2p_ihb_rd), | |
14099 | .d2p_idb_rd(d2p_idb_rd), | |
14100 | .p2d_ihb_wptr(p2d_ihb_wptr[6:0]), | |
14101 | .p2d_mps(p2d_mps[2:0]), | |
14102 | .p2d_oe_int(p2d_oe_int), | |
14103 | .p2d_spare(p2d_spare[4:0]), | |
14104 | .p2d_ue_int(p2d_ue_int), | |
14105 | .p2d_npwr_stall_en(p2d_npwr_stall_en), | |
14106 | .rst_dmu_async_por_(rst_dmu_async_por_), | |
14107 | .sii_dmu_wrack_tag(sii_dmu_wrack_tag[3:0]), | |
14108 | .sii_dmu_wrack_vld(sii_dmu_wrack_vld), | |
14109 | .sio_dmu_data(sio_dmu_data[127:0]), | |
14110 | .sio_dmu_hdr_vld(sio_dmu_hdr_vld), | |
14111 | .sio_dmu_parity(sio_dmu_parity[7:0]), | |
14112 | .tcu_mbist_bisi_en(tcu_mbist_bisi_en), | |
14113 | .tcu_mbist_user_mode(tcu_mbist_user_mode), | |
14114 | .tcu_dmu_mbist_start(tcu_dmu_mbist_start[1:0]), | |
14115 | .tcu_dmu_mbist_scan_in(tcu_dmu_mbist_scan_in), | |
14116 | .tcu_atpg_mode(tcu_atpg_mode), | |
14117 | .dmu_tcu_mbist_done(dmu_tcu_mbist_done[1:0]), | |
14118 | .dmu_tcu_mbist_fail(dmu_tcu_mbist_fail[1:0]), | |
14119 | .dmu_tcu_mbist_scan_out(dmu_tcu_mbist_scan_out), | |
14120 | .d2p_csr_ack(d2p_csr_ack), | |
14121 | .d2p_csr_rcd(d2p_csr_rcd[95:0]), | |
14122 | .d2p_csr_req(d2p_csr_req), | |
14123 | .d2p_cto_ack(d2p_cto_ack), | |
14124 | .d2p_ech_wptr(d2p_ech_wptr[5:0]), | |
14125 | .d2p_edb_addr(d2p_edb_addr[7:0]), | |
14126 | .d2p_edb_data(d2p_edb_data[127:0]), | |
14127 | .d2p_edb_dpar(d2p_edb_dpar[3:0]), | |
14128 | .d2p_edb_we(d2p_edb_we), | |
14129 | .d2p_ehb_addr(d2p_ehb_addr[5:0]), | |
14130 | .d2p_ehb_data(d2p_ehb_data[127:0]), | |
14131 | .d2p_ehb_dpar(d2p_ehb_dpar[3:0]), | |
14132 | .d2p_ehb_we(d2p_ehb_we), | |
14133 | .d2p_erh_wptr(d2p_erh_wptr[5:0]), | |
14134 | .d2p_ibc_nhc(d2p_ibc_nhc[7:0]), | |
14135 | .d2p_ibc_pdc(d2p_ibc_pdc[11:0]), | |
14136 | .d2p_ibc_phc(d2p_ibc_phc[7:0]), | |
14137 | .d2p_ibc_req(d2p_ibc_req), | |
14138 | .d2p_idb_addr(d2p_idb_addr[7:0]), | |
14139 | .d2p_ihb_addr(d2p_ihb_addr[5:0]), | |
14140 | .d2p_spare(d2p_spare[4:0]), | |
14141 | .dmu_ncu_data(dmu_ncu_data[31:0]), | |
14142 | .dmu_ncu_stall(dmu_ncu_stall), | |
14143 | .dmu_ncu_vld(dmu_ncu_vld), | |
14144 | .dmu_ncu_wrack_tag(dmu_ncu_wrack_tag[3:0]), | |
14145 | .dmu_ncu_wrack_vld(dmu_ncu_wrack_vld), | |
14146 | .dmu_ncu_wrack_par(dmu_ncu_wrack_par), | |
14147 | .dmu_ncu_d_pe(dmu_ncu_d_pe), | |
14148 | .dmu_ncu_siicr_pe(dmu_ncu_siicr_pe), | |
14149 | .dmu_ncu_ctag_ue(dmu_ncu_ctag_ue), | |
14150 | .dmu_ncu_ctag_ce(dmu_ncu_ctag_ce), | |
14151 | .dmu_ncu_ncucr_pe(dmu_ncu_ncucr_pe), | |
14152 | .dmu_ncu_ie(dmu_ncu_ie), | |
14153 | .dmu_sii_be(dmu_sii_be[15:0]), | |
14154 | .dmu_sii_data(dmu_sii_data[127:0]), | |
14155 | .dmu_sii_datareq(dmu_sii_datareq), | |
14156 | .dmu_sii_datareq16(dmu_sii_datareq16), | |
14157 | .dmu_sii_hdr_vld(dmu_sii_hdr_vld), | |
14158 | .dmu_sii_parity(dmu_sii_parity[7:0]), | |
14159 | .dmu_sii_be_parity(dmu_sii_be_parity), | |
14160 | .dmu_sii_reqbypass(dmu_sii_reqbypass), | |
14161 | .dmu_mio_debug_bus_a(dmu_mio_debug_bus_a[7:0]), | |
14162 | .dmu_mio_debug_bus_b(dmu_mio_debug_bus_b[7:0]), | |
14163 | .dmu_dbg_err_event(dmu_dbg_err_event), | |
14164 | .dbg1_dmu_stall(dbg1_dmu_stall), | |
14165 | .dbg1_dmu_resume(dbg1_dmu_resume), | |
14166 | .dmu_dbg1_stall_ack(dmu_dbg1_stall_ack), | |
14167 | .efu_dmu_data(efu_dmu_data), | |
14168 | .efu_dmu_xfer_en(efu_dmu_xfer_en), | |
14169 | .efu_dmu_clr(efu_dmu_clr), | |
14170 | .dmu_efu_data(dmu_efu_data), | |
14171 | .dmu_efu_xfer_en(dmu_efu_xfer_en), | |
14172 | .dmu_psr_rate_scale(dmu_psr_rate_scale[1:0]), | |
14173 | .dmu_psr_pll_en_sds0(dmu_psr_pll_en_sds0), | |
14174 | .dmu_psr_pll_en_sds1(dmu_psr_pll_en_sds1), | |
14175 | .dmu_psr_rx_en_b0_sds0(dmu_psr_rx_en_b0_sds0), | |
14176 | .dmu_psr_rx_en_b1_sds0(dmu_psr_rx_en_b1_sds0), | |
14177 | .dmu_psr_rx_en_b2_sds0(dmu_psr_rx_en_b2_sds0), | |
14178 | .dmu_psr_rx_en_b3_sds0(dmu_psr_rx_en_b3_sds0), | |
14179 | .dmu_psr_rx_en_b0_sds1(dmu_psr_rx_en_b0_sds1), | |
14180 | .dmu_psr_rx_en_b1_sds1(dmu_psr_rx_en_b1_sds1), | |
14181 | .dmu_psr_rx_en_b2_sds1(dmu_psr_rx_en_b2_sds1), | |
14182 | .dmu_psr_rx_en_b3_sds1(dmu_psr_rx_en_b3_sds1), | |
14183 | .dmu_psr_tx_en_b0_sds0(dmu_psr_tx_en_b0_sds0), | |
14184 | .dmu_psr_tx_en_b1_sds0(dmu_psr_tx_en_b1_sds0), | |
14185 | .dmu_psr_tx_en_b2_sds0(dmu_psr_tx_en_b2_sds0), | |
14186 | .dmu_psr_tx_en_b3_sds0(dmu_psr_tx_en_b3_sds0), | |
14187 | .dmu_psr_tx_en_b0_sds1(dmu_psr_tx_en_b0_sds1), | |
14188 | .dmu_psr_tx_en_b1_sds1(dmu_psr_tx_en_b1_sds1), | |
14189 | .dmu_psr_tx_en_b2_sds1(dmu_psr_tx_en_b2_sds1), | |
14190 | .dmu_psr_tx_en_b3_sds1(dmu_psr_tx_en_b3_sds1), | |
14191 | .d2p_req_id(d2p_req_id[15:0]) // staged div phase | |
14192 | ); | |
14193 | `endif // OPENSPARC_CMP | |
14194 | ||
14195 | ||
14196 | // leave this instance out of cmp model | |
14197 | `ifdef OPENSPARC_CMP | |
14198 | `else | |
14199 | `ifdef PEU_SYSTEMC_MODEL | |
14200 | peu peu( | |
14201 | ||
14202 | .rst_por_ (gl_dmu_peu_por_c3b ), | |
14203 | .rst_wmr_ (gl_dmu_peu_wmr_c3b ), | |
14204 | .l2t_clk ( cmp_gclk_c3_dmu ), | |
14205 | .iol2clk (dmu.l1clk), | |
14206 | .d2p_csr_ack(d2p_csr_ack), | |
14207 | .d2p_csr_rcd(d2p_csr_rcd[95:0]), | |
14208 | .d2p_csr_req(d2p_csr_req), | |
14209 | .d2p_cto_ack(d2p_cto_ack), | |
14210 | .d2p_ech_wptr(d2p_ech_wptr[5:0]), | |
14211 | .d2p_edb_addr(d2p_edb_addr[7:0]), | |
14212 | .d2p_edb_data(d2p_edb_data[127:0]), | |
14213 | .d2p_edb_dpar(d2p_edb_dpar[3:0]), | |
14214 | .d2p_edb_we(d2p_edb_we), | |
14215 | .d2p_ehb_addr(d2p_ehb_addr[5:0]), | |
14216 | .d2p_ehb_data(d2p_ehb_data[127:0]), | |
14217 | .d2p_ehb_dpar(d2p_ehb_dpar[3:0]), | |
14218 | .d2p_ehb_we(d2p_ehb_we), | |
14219 | .d2p_erh_wptr(d2p_erh_wptr[5:0]), | |
14220 | .d2p_ibc_nhc(d2p_ibc_nhc[7:0]), | |
14221 | .d2p_ibc_pdc(d2p_ibc_pdc[11:0]), | |
14222 | .d2p_ibc_phc(d2p_ibc_phc[7:0]), | |
14223 | .d2p_ibc_req(d2p_ibc_req), | |
14224 | .d2p_idb_addr(d2p_idb_addr[7:0]), | |
14225 | .d2p_idb_rd(d2p_idb_rd), | |
14226 | .d2p_ihb_addr(d2p_ihb_addr[5:0]), | |
14227 | .d2p_ihb_rd(d2p_ihb_rd), | |
14228 | // .d2p_req_id(d2p_req_id[15:0]), | |
14229 | // .d2p_spare(d2p_spare[4:0]), | |
14230 | .p2d_ce_int(p2d_ce_int), | |
14231 | .p2d_csr_ack(p2d_csr_ack), | |
14232 | .p2d_csr_rcd(p2d_csr_rcd[95:0]), | |
14233 | .p2d_csr_req(p2d_csr_req), | |
14234 | .p2d_cto_req(p2d_cto_req), | |
14235 | .p2d_cto_tag(p2d_cto_tag[4:0]), | |
14236 | .p2d_drain(p2d_drain), | |
14237 | .p2d_ecd_rptr(p2d_ecd_rptr[7:0]), | |
14238 | .p2d_ech_rptr(p2d_ech_rptr[5:0]), | |
14239 | .p2d_erd_rptr(p2d_erd_rptr[7:0]), | |
14240 | .p2d_erh_rptr(p2d_erh_rptr[5:0]), | |
14241 | .p2d_ibc_ack(p2d_ibc_ack), | |
14242 | .p2d_idb_data(p2d_idb_data[127:0]), | |
14243 | .p2d_idb_dpar(p2d_idb_dpar[3:0]), | |
14244 | .p2d_ihb_data(p2d_ihb_data[127:0]), | |
14245 | .p2d_ihb_dpar(p2d_ihb_dpar[3:0]), | |
14246 | .p2d_ihb_wptr(p2d_ihb_wptr[6:0]), | |
14247 | .p2d_mps(p2d_mps[2:0]), | |
14248 | .p2d_oe_int(p2d_oe_int), | |
14249 | // .p2d_spare(p2d_spare[4:0]), | |
14250 | .p2d_ue_int(p2d_ue_int), | |
14251 | .link_clk(PEX_REFCLK_P), | |
14252 | .link_in(PEX_RX_P), | |
14253 | .link_in_bar(PEX_RX_N), | |
14254 | .link_out(PEX_TX_P), | |
14255 | .link_out_bar(PEX_TX_N) | |
14256 | ||
14257 | ); | |
14258 | ||
14259 | assign peu_tcu_mbist_done = 1'b0; | |
14260 | ||
14261 | `else | |
14262 | /* | |
14263 | peu peu( | |
14264 | ||
14265 | .rst_por_ (gl_dmu_peu_por_c3b ), | |
14266 | .rst_wmr_ (gl_dmu_peu_wmr_c3b ), | |
14267 | .tcu_aclk ( tcu_asic_aclk ), | |
14268 | .tcu_bclk ( tcu_asic_bclk ), | |
14269 | .tcu_scan_en ( tcu_asic_scan_en ), | |
14270 | .tcu_se_scancollar_in ( tcu_asic_se_scancollar_in ), | |
14271 | .tcu_array_wr_inhibit ( tcu_asic_array_wr_inhibit ), | |
14272 | .scan_in (tcu_peu_scan_out), | |
14273 | .scan_out (peu_scan_out ), // to be connected to tcu | |
14274 | .peu_sbs_scan_in (mcu1_sbs_scan_out ), | |
14275 | .peu_sbs_scan_out (peu_mac_sbs_input ), // 0324 | |
14276 | ||
14277 | .gclk ( cmp_gclk_c3_peu ), // cmp_gclk_c0_r[0] ), | |
14278 | .tcu_peu_io_clk_stop ( gl_peu_io_clk_stop ), // staged clk_stop | |
14279 | .ccu_io_out ( gl_io_out_c3b ), // staged div phase | |
14280 | .pc_clk (psr_peu_txbclk0 ), | |
14281 | .ccu_serdes_dtm(ccu_serdes_dtm), | |
14282 | .cluster_arst_l(cluster_arst_l), | |
14283 | .rst_dmu_async_por_(rst_dmu_async_por_), | |
14284 | .tcu_pce_ov(tcu_pce_ov), | |
14285 | .tcu_peu_pc_clk_stop(tcu_peu_pc_clk_stop), | |
14286 | .tcu_atpg_mode(tcu_atpg_mode), | |
14287 | .tcu_div_bypass(tcu_div_bypass), | |
14288 | .tcu_test_protect(tcu_test_protect), | |
14289 | .tcu_peu_entestcfg(tcu_peu_entestcfg), | |
14290 | .tcu_peu_testmode(tcu_peu_testmode), | |
14291 | .tcu_peu_clk_ext(tcu_peu_clk_ext), | |
14292 | .tcu_mbist_bisi_en(tcu_mbist_bisi_en), | |
14293 | .tcu_mbist_user_mode(tcu_mbist_user_mode), | |
14294 | .tcu_peu_mbist_start(tcu_peu_mbist_start), | |
14295 | .peu_tcu_mbist_done(peu_tcu_mbist_done), | |
14296 | .peu_tcu_mbist_fail(peu_tcu_mbist_fail), | |
14297 | .tcu_peu_mbist_scan_in(tcu_peu_mbist_scan_in), | |
14298 | .peu_tcu_mbist_scan_out(peu_tcu_mbist_scan_out), | |
14299 | .tcu_sbs_scan_en(tcu_sbs_scan_en), | |
14300 | .tcu_sbs_aclk(tcu_sbs_aclk), | |
14301 | .tcu_sbs_bclk(tcu_sbs_bclk), | |
14302 | .tcu_sbs_clk(tcu_sbs_clk), | |
14303 | .tcu_sbs_uclk(tcu_sbs_uclk), | |
14304 | .tcu_sbs_enbstx(tcu_sbs_enbstx), | |
14305 | .tcu_sbs_enbsrx(tcu_sbs_enbsrx), | |
14306 | .tcu_sbs_enbspt(tcu_sbs_enbspt), | |
14307 | .tcu_sbs_acmode(tcu_sbs_acmode), | |
14308 | .tcu_sbs_actestsignal(tcu_sbs_actestsignal), | |
14309 | .peu_mio_debug_clk(peu_mio_debug_clk), | |
14310 | .peu_mio_debug_bus_a(peu_mio_debug_bus_a[7:0]), | |
14311 | .peu_mio_debug_bus_b(peu_mio_debug_bus_b[7:0]), | |
14312 | .peu_mio_pipe_txdata(peu_mio_pipe_txdata[63:0]), | |
14313 | .peu_mio_pipe_txdatak(peu_mio_pipe_txdatak[7:0]), | |
14314 | .d2p_csr_ack(d2p_csr_ack), | |
14315 | .d2p_csr_rcd(d2p_csr_rcd[95:0]), | |
14316 | .d2p_csr_req(d2p_csr_req), | |
14317 | .d2p_cto_ack(d2p_cto_ack), | |
14318 | .d2p_ech_wptr(d2p_ech_wptr[5:0]), | |
14319 | .d2p_edb_addr(d2p_edb_addr[7:0]), | |
14320 | .d2p_edb_data(d2p_edb_data[127:0]), | |
14321 | .d2p_edb_dpar(d2p_edb_dpar[3:0]), | |
14322 | .d2p_edb_we(d2p_edb_we), | |
14323 | .d2p_ehb_addr(d2p_ehb_addr[5:0]), | |
14324 | .d2p_ehb_data(d2p_ehb_data[127:0]), | |
14325 | .d2p_ehb_dpar(d2p_ehb_dpar[3:0]), | |
14326 | .d2p_ehb_we(d2p_ehb_we), | |
14327 | .d2p_erh_wptr(d2p_erh_wptr[5:0]), | |
14328 | .d2p_ibc_nhc(d2p_ibc_nhc[7:0]), | |
14329 | .d2p_ibc_pdc(d2p_ibc_pdc[11:0]), | |
14330 | .d2p_ibc_phc(d2p_ibc_phc[7:0]), | |
14331 | .d2p_ibc_req(d2p_ibc_req), | |
14332 | .d2p_idb_addr(d2p_idb_addr[7:0]), | |
14333 | .d2p_idb_rd(d2p_idb_rd), | |
14334 | .d2p_ihb_addr(d2p_ihb_addr[5:0]), | |
14335 | .d2p_ihb_rd(d2p_ihb_rd), | |
14336 | .d2p_req_id(d2p_req_id[15:0]), | |
14337 | .d2p_spare(d2p_spare[4:0]), | |
14338 | .p2d_ce_int(p2d_ce_int), | |
14339 | .p2d_csr_ack(p2d_csr_ack), | |
14340 | .p2d_csr_rcd(p2d_csr_rcd[95:0]), | |
14341 | .p2d_csr_req(p2d_csr_req), | |
14342 | .p2d_cto_req(p2d_cto_req), | |
14343 | .p2d_cto_tag(p2d_cto_tag[4:0]), | |
14344 | .p2d_drain(p2d_drain), | |
14345 | .p2d_ecd_rptr(p2d_ecd_rptr[7:0]), | |
14346 | .p2d_ech_rptr(p2d_ech_rptr[5:0]), | |
14347 | .p2d_erd_rptr(p2d_erd_rptr[7:0]), | |
14348 | .p2d_erh_rptr(p2d_erh_rptr[5:0]), | |
14349 | .p2d_ibc_ack(p2d_ibc_ack), | |
14350 | .p2d_idb_data(p2d_idb_data[127:0]), | |
14351 | .p2d_idb_dpar(p2d_idb_dpar[3:0]), | |
14352 | .p2d_ihb_data(p2d_ihb_data[127:0]), | |
14353 | .p2d_ihb_dpar(p2d_ihb_dpar[3:0]), | |
14354 | .p2d_ihb_wptr(p2d_ihb_wptr[6:0]), | |
14355 | .p2d_mps(p2d_mps[2:0]), | |
14356 | .p2d_oe_int(p2d_oe_int), | |
14357 | .p2d_spare(p2d_spare[4:0]), | |
14358 | .p2d_ue_int(p2d_ue_int), | |
14359 | .p2d_npwr_stall_en(p2d_npwr_stall_en), | |
14360 | .psr_peu_rd_b0sds0(psr_peu_rd_b0sds0[9:0]), | |
14361 | .psr_peu_rd_b1sds0(psr_peu_rd_b1sds0[9:0]), | |
14362 | .psr_peu_rd_b2sds0(psr_peu_rd_b2sds0[9:0]), | |
14363 | .psr_peu_rd_b3sds0(psr_peu_rd_b3sds0[9:0]), | |
14364 | .psr_peu_rd_b0sds1(psr_peu_rd_b0sds1[9:0]), | |
14365 | .psr_peu_rd_b1sds1(psr_peu_rd_b1sds1[9:0]), | |
14366 | .psr_peu_rd_b2sds1(psr_peu_rd_b2sds1[9:0]), | |
14367 | .psr_peu_rd_b3sds1(psr_peu_rd_b3sds1[9:0]), | |
14368 | .psr_peu_rxbclk_b0sds0(psr_peu_rxbclk_b0sds0), | |
14369 | .psr_peu_rxbclk_b1sds0(psr_peu_rxbclk_b1sds0), | |
14370 | .psr_peu_rxbclk_b2sds0(psr_peu_rxbclk_b2sds0), | |
14371 | .psr_peu_rxbclk_b3sds0(psr_peu_rxbclk_b3sds0), | |
14372 | .psr_peu_rxbclk_b0sds1(psr_peu_rxbclk_b0sds1), | |
14373 | .psr_peu_rxbclk_b1sds1(psr_peu_rxbclk_b1sds1), | |
14374 | .psr_peu_rxbclk_b2sds1(psr_peu_rxbclk_b2sds1), | |
14375 | .psr_peu_rxbclk_b3sds1(psr_peu_rxbclk_b3sds1), | |
14376 | .psr_peu_bsrxn_b0sds0(psr_peu_bsrxn_b0sds0), | |
14377 | .psr_peu_bsrxn_b1sds0(psr_peu_bsrxn_b1sds0), | |
14378 | .psr_peu_bsrxn_b2sds0(psr_peu_bsrxn_b2sds0), | |
14379 | .psr_peu_bsrxn_b3sds0(psr_peu_bsrxn_b3sds0), | |
14380 | .psr_peu_bsrxn_b0sds1(psr_peu_bsrxn_b0sds1), | |
14381 | .psr_peu_bsrxn_b1sds1(psr_peu_bsrxn_b1sds1), | |
14382 | .psr_peu_bsrxn_b2sds1(psr_peu_bsrxn_b2sds1), | |
14383 | .psr_peu_bsrxn_b3sds1(psr_peu_bsrxn_b3sds1), | |
14384 | .psr_peu_bsrxp_b0sds0(psr_peu_bsrxp_b0sds0), | |
14385 | .psr_peu_bsrxp_b1sds0(psr_peu_bsrxp_b1sds0), | |
14386 | .psr_peu_bsrxp_b2sds0(psr_peu_bsrxp_b2sds0), | |
14387 | .psr_peu_bsrxp_b3sds0(psr_peu_bsrxp_b3sds0), | |
14388 | .psr_peu_bsrxp_b0sds1(psr_peu_bsrxp_b0sds1), | |
14389 | .psr_peu_bsrxp_b1sds1(psr_peu_bsrxp_b1sds1), | |
14390 | .psr_peu_bsrxp_b2sds1(psr_peu_bsrxp_b2sds1), | |
14391 | .psr_peu_bsrxp_b3sds1(psr_peu_bsrxp_b3sds1), | |
14392 | .psr_peu_losdtct_b0sds0(psr_peu_losdtct_b0sds0), | |
14393 | .psr_peu_losdtct_b1sds0(psr_peu_losdtct_b1sds0), | |
14394 | .psr_peu_losdtct_b2sds0(psr_peu_losdtct_b2sds0), | |
14395 | .psr_peu_losdtct_b3sds0(psr_peu_losdtct_b3sds0), | |
14396 | .psr_peu_losdtct_b0sds1(psr_peu_losdtct_b0sds1), | |
14397 | .psr_peu_losdtct_b1sds1(psr_peu_losdtct_b1sds1), | |
14398 | .psr_peu_losdtct_b2sds1(psr_peu_losdtct_b2sds1), | |
14399 | .psr_peu_losdtct_b3sds1(psr_peu_losdtct_b3sds1), | |
14400 | .psr_peu_sync_b0sds0(psr_peu_sync_b0sds0), | |
14401 | .psr_peu_sync_b1sds0(psr_peu_sync_b1sds0), | |
14402 | .psr_peu_sync_b2sds0(psr_peu_sync_b2sds0), | |
14403 | .psr_peu_sync_b3sds0(psr_peu_sync_b3sds0), | |
14404 | .psr_peu_sync_b0sds1(psr_peu_sync_b0sds1), | |
14405 | .psr_peu_sync_b1sds1(psr_peu_sync_b1sds1), | |
14406 | .psr_peu_sync_b2sds1(psr_peu_sync_b2sds1), | |
14407 | .psr_peu_sync_b3sds1(psr_peu_sync_b3sds1), | |
14408 | .psr_peu_rx_tstfail_b0sds0(psr_peu_rx_tstfail_b0sds0), | |
14409 | .psr_peu_rx_tstfail_b1sds0(psr_peu_rx_tstfail_b1sds0), | |
14410 | .psr_peu_rx_tstfail_b2sds0(psr_peu_rx_tstfail_b2sds0), | |
14411 | .psr_peu_rx_tstfail_b3sds0(psr_peu_rx_tstfail_b3sds0), | |
14412 | .psr_peu_rx_tstfail_b0sds1(psr_peu_rx_tstfail_b0sds1), | |
14413 | .psr_peu_rx_tstfail_b1sds1(psr_peu_rx_tstfail_b1sds1), | |
14414 | .psr_peu_rx_tstfail_b2sds1(psr_peu_rx_tstfail_b2sds1), | |
14415 | .psr_peu_rx_tstfail_b3sds1(psr_peu_rx_tstfail_b3sds1), | |
14416 | .psr_peu_rdtcip_b0sds0(psr_peu_rdtcip_b0sds0), | |
14417 | .psr_peu_rdtcip_b1sds0(psr_peu_rdtcip_b1sds0), | |
14418 | .psr_peu_rdtcip_b2sds0(psr_peu_rdtcip_b2sds0), | |
14419 | .psr_peu_rdtcip_b3sds0(psr_peu_rdtcip_b3sds0), | |
14420 | .psr_peu_rdtcip_b0sds1(psr_peu_rdtcip_b0sds1), | |
14421 | .psr_peu_rdtcip_b1sds1(psr_peu_rdtcip_b1sds1), | |
14422 | .psr_peu_rdtcip_b2sds1(psr_peu_rdtcip_b2sds1), | |
14423 | .psr_peu_rdtcip_b3sds1(psr_peu_rdtcip_b3sds1), | |
14424 | .psr_peu_tx_tstfail_b0sds0(psr_peu_tx_tstfail_b0sds0), | |
14425 | .psr_peu_tx_tstfail_b1sds0(psr_peu_tx_tstfail_b1sds0), | |
14426 | .psr_peu_tx_tstfail_b2sds0(psr_peu_tx_tstfail_b2sds0), | |
14427 | .psr_peu_tx_tstfail_b3sds0(psr_peu_tx_tstfail_b3sds0), | |
14428 | .psr_peu_tx_tstfail_b0sds1(psr_peu_tx_tstfail_b0sds1), | |
14429 | .psr_peu_tx_tstfail_b1sds1(psr_peu_tx_tstfail_b1sds1), | |
14430 | .psr_peu_tx_tstfail_b2sds1(psr_peu_tx_tstfail_b2sds1), | |
14431 | .psr_peu_tx_tstfail_b3sds1(psr_peu_tx_tstfail_b3sds1), | |
14432 | .psr_peu_lock_sds0(psr_peu_lock_sds0), | |
14433 | .psr_peu_lock_sds1(psr_peu_lock_sds1), | |
14434 | .peu_psr_td_b0sds0(peu_psr_td_b0sds0[9:0]), | |
14435 | .peu_psr_td_b1sds0(peu_psr_td_b1sds0[9:0]), | |
14436 | .peu_psr_td_b2sds0(peu_psr_td_b2sds0[9:0]), | |
14437 | .peu_psr_td_b3sds0(peu_psr_td_b3sds0[9:0]), | |
14438 | .peu_psr_td_b0sds1(peu_psr_td_b0sds1[9:0]), | |
14439 | .peu_psr_td_b1sds1(peu_psr_td_b1sds1[9:0]), | |
14440 | .peu_psr_td_b2sds1(peu_psr_td_b2sds1[9:0]), | |
14441 | .peu_psr_td_b3sds1(peu_psr_td_b3sds1[9:0]), | |
14442 | .peu_psr_invpair_b0sds0(peu_psr_invpair_b0sds0), | |
14443 | .peu_psr_invpair_b1sds0(peu_psr_invpair_b1sds0), | |
14444 | .peu_psr_invpair_b2sds0(peu_psr_invpair_b2sds0), | |
14445 | .peu_psr_invpair_b3sds0(peu_psr_invpair_b3sds0), | |
14446 | .peu_psr_invpair_b0sds1(peu_psr_invpair_b0sds1), | |
14447 | .peu_psr_invpair_b1sds1(peu_psr_invpair_b1sds1), | |
14448 | .peu_psr_invpair_b2sds1(peu_psr_invpair_b2sds1), | |
14449 | .peu_psr_invpair_b3sds1(peu_psr_invpair_b3sds1), | |
14450 | .peu_psr_rx_lane_ctl_0(peu_psr_rx_lane_ctl_0[15:0]), | |
14451 | .peu_psr_rx_lane_ctl_1(peu_psr_rx_lane_ctl_1[15:0]), | |
14452 | .peu_psr_rx_lane_ctl_2(peu_psr_rx_lane_ctl_2[15:0]), | |
14453 | .peu_psr_rx_lane_ctl_3(peu_psr_rx_lane_ctl_3[15:0]), | |
14454 | .peu_psr_rx_lane_ctl_4(peu_psr_rx_lane_ctl_4[15:0]), | |
14455 | .peu_psr_rx_lane_ctl_5(peu_psr_rx_lane_ctl_5[15:0]), | |
14456 | .peu_psr_rx_lane_ctl_6(peu_psr_rx_lane_ctl_6[15:0]), | |
14457 | .peu_psr_rx_lane_ctl_7(peu_psr_rx_lane_ctl_7[15:0]), | |
14458 | .peu_psr_rdtct_b0sds0(peu_psr_rdtct_b0sds0[1:0]), | |
14459 | .peu_psr_rdtct_b1sds0(peu_psr_rdtct_b1sds0[1:0]), | |
14460 | .peu_psr_rdtct_b2sds0(peu_psr_rdtct_b2sds0[1:0]), | |
14461 | .peu_psr_rdtct_b3sds0(peu_psr_rdtct_b3sds0[1:0]), | |
14462 | .peu_psr_rdtct_b0sds1(peu_psr_rdtct_b0sds1[1:0]), | |
14463 | .peu_psr_rdtct_b1sds1(peu_psr_rdtct_b1sds1[1:0]), | |
14464 | .peu_psr_rdtct_b2sds1(peu_psr_rdtct_b2sds1[1:0]), | |
14465 | .peu_psr_rdtct_b3sds1(peu_psr_rdtct_b3sds1[1:0]), | |
14466 | .peu_psr_enidl_b0sds0(peu_psr_enidl_b0sds0), | |
14467 | .peu_psr_enidl_b1sds0(peu_psr_enidl_b1sds0), | |
14468 | .peu_psr_enidl_b2sds0(peu_psr_enidl_b2sds0), | |
14469 | .peu_psr_enidl_b3sds0(peu_psr_enidl_b3sds0), | |
14470 | .peu_psr_enidl_b0sds1(peu_psr_enidl_b0sds1), | |
14471 | .peu_psr_enidl_b1sds1(peu_psr_enidl_b1sds1), | |
14472 | .peu_psr_enidl_b2sds1(peu_psr_enidl_b2sds1), | |
14473 | .peu_psr_enidl_b3sds1(peu_psr_enidl_b3sds1), | |
14474 | .peu_psr_bstx_b0sds0(peu_psr_bstx_b0sds0), | |
14475 | .peu_psr_bstx_b1sds0(peu_psr_bstx_b1sds0), | |
14476 | .peu_psr_bstx_b2sds0(peu_psr_bstx_b2sds0), | |
14477 | .peu_psr_bstx_b3sds0(peu_psr_bstx_b3sds0), | |
14478 | .peu_psr_bstx_b0sds1(peu_psr_bstx_b0sds1), | |
14479 | .peu_psr_bstx_b1sds1(peu_psr_bstx_b1sds1), | |
14480 | .peu_psr_bstx_b2sds1(peu_psr_bstx_b2sds1), | |
14481 | .peu_psr_bstx_b3sds1(peu_psr_bstx_b3sds1), | |
14482 | .peu_psr_tx_lane_ctl_0(peu_psr_tx_lane_ctl_0[9:0]), | |
14483 | .peu_psr_tx_lane_ctl_1(peu_psr_tx_lane_ctl_1[9:0]), | |
14484 | .peu_psr_tx_lane_ctl_2(peu_psr_tx_lane_ctl_2[9:0]), | |
14485 | .peu_psr_tx_lane_ctl_3(peu_psr_tx_lane_ctl_3[9:0]), | |
14486 | .peu_psr_tx_lane_ctl_4(peu_psr_tx_lane_ctl_4[9:0]), | |
14487 | .peu_psr_tx_lane_ctl_5(peu_psr_tx_lane_ctl_5[9:0]), | |
14488 | .peu_psr_tx_lane_ctl_6(peu_psr_tx_lane_ctl_6[9:0]), | |
14489 | .peu_psr_tx_lane_ctl_7(peu_psr_tx_lane_ctl_7[9:0]), | |
14490 | .peu_psr_txbclkin(peu_psr_txbclkin[7:0]), | |
14491 | .peu_psr_testcfg_sds0(peu_psr_testcfg_sds0[15:0]), | |
14492 | .peu_psr_testcfg_sds1(peu_psr_testcfg_sds1[15:0]), | |
14493 | .peu_psr_pll_mpy(peu_psr_pll_mpy[3:0]), | |
14494 | .peu_psr_pll_lb(peu_psr_pll_lb[1:0]) | |
14495 | ); | |
14496 | */ | |
14497 | `endif | |
14498 | `endif // OPENSPARC_CMP | |
14499 | ||
14500 | ||
14501 | /* | |
14502 | // leave this instance out of cmp model | |
14503 | `ifdef OPENSPARC_CMP | |
14504 | `else | |
14505 | psr psr ( | |
14506 | ||
14507 | .VDDT (VDDT_PSR), | |
14508 | .VDDD (VDDD_PSR), | |
14509 | .VDDC (VDDC_PSR), | |
14510 | .VDDA (VDDA_PSR), | |
14511 | .VDDR (VDDR_PSR), | |
14512 | .VSSA (VSSA_PSR), | |
14513 | .dmu_psr_rate_scale_rx_b0sds0 (dmu_psr_rate_scale[ 1 : 0 ] ), | |
14514 | .dmu_psr_rate_scale_rx_b1sds0 (dmu_psr_rate_scale[ 1 : 0 ] ), | |
14515 | .dmu_psr_rate_scale_rx_b2sds0 (dmu_psr_rate_scale[ 1 : 0 ] ), | |
14516 | .dmu_psr_rate_scale_rx_b3sds0 (dmu_psr_rate_scale[ 1 : 0 ] ), | |
14517 | .dmu_psr_rate_scale_rx_b0sds1 (dmu_psr_rate_scale[ 1 : 0 ] ), | |
14518 | .dmu_psr_rate_scale_rx_b1sds1 (dmu_psr_rate_scale[ 1 : 0 ] ), | |
14519 | .dmu_psr_rate_scale_rx_b2sds1 (dmu_psr_rate_scale[ 1 : 0 ] ), | |
14520 | .dmu_psr_rate_scale_rx_b3sds1 (dmu_psr_rate_scale[ 1 : 0 ] ), | |
14521 | .dmu_psr_rate_scale_tx_b0sds0 (dmu_psr_rate_scale[ 1 : 0 ] ), | |
14522 | .dmu_psr_rate_scale_tx_b1sds0 (dmu_psr_rate_scale[ 1 : 0 ] ), | |
14523 | .dmu_psr_rate_scale_tx_b2sds0 (dmu_psr_rate_scale[ 1 : 0 ] ), | |
14524 | .dmu_psr_rate_scale_tx_b3sds0 (dmu_psr_rate_scale[ 1 : 0 ] ), | |
14525 | .dmu_psr_rate_scale_tx_b0sds1 (dmu_psr_rate_scale[ 1 : 0 ] ), | |
14526 | .dmu_psr_rate_scale_tx_b1sds1 (dmu_psr_rate_scale[ 1 : 0 ] ), | |
14527 | .dmu_psr_rate_scale_tx_b2sds1 (dmu_psr_rate_scale[ 1 : 0 ] ), | |
14528 | .dmu_psr_rate_scale_tx_b3sds1 (dmu_psr_rate_scale[ 1 : 0 ] ), | |
14529 | .tcu_srd_atpgse_sds0 (tcu_srd_atpgse ), | |
14530 | .tcu_srd_atpgmode_sds0 (tcu_srd_atpgmode[ 2 : 0 ] ), | |
14531 | .tcu_srd_atpgse_sds1 (tcu_srd_atpgse ), | |
14532 | .tcu_srd_atpgmode_sds1 (tcu_srd_atpgmode[ 2 : 0 ] ), | |
14533 | .peu_psr_pll_mpy_sds0 (peu_psr_pll_mpy[ 3 : 0 ] ), | |
14534 | .peu_psr_pll_lb_sds0 (peu_psr_pll_lb[ 1 : 0 ] ), | |
14535 | .peu_psr_pll_mpy_sds1 (peu_psr_pll_mpy[ 3 : 0 ] ), | |
14536 | .peu_psr_pll_lb_sds1 (peu_psr_pll_lb[ 1 : 0 ] ), | |
14537 | .bsinitclk_sds0 (tcu_sbs_bsinitclk ) , | |
14538 | .bsinitclk_sds1 (tcu_sbs_bsinitclk ) , | |
14539 | .tcu_stciclk_sds0 (tcu_stciclk ), | |
14540 | .tcu_stcicfg_sds0 (tcu_stcicfg[ 1 : 0 ] ), | |
14541 | .tcu_stciclk_sds1 (tcu_stciclk ), | |
14542 | .tcu_stcicfg_sds1 (tcu_stcicfg[ 1 : 0 ] ), | |
14543 | .psr_stcid_sds0 (fsr3_stciq[ 2 ] ), | |
14544 | .psr_stciq_sds0 (psr_stciq_sds0 ), | |
14545 | .psr_stcid_sds1 (psr_stciq_sds0 ), | |
14546 | .psr_stciq_sds1 (esr_stcid ), | |
14547 | .efu_psr_fclk_sds0 (efu_psr_fclk ), | |
14548 | .efu_psr_fclrz_sds0 (efu_psr_fclrz ), | |
14549 | .efu_psr_fclk_sds1 (efu_psr_fclk ), | |
14550 | .efu_psr_fclrz_sds1 (efu_psr_fclrz ), | |
14551 | .psr_fdi_sds0 (efu_psr_fdi ), | |
14552 | .psr_fdo_sds0 (psr_fdo_sds0 ), | |
14553 | .psr_fdi_sds1 (psr_fdo_sds0 ), | |
14554 | .psr_fdo_sds1 (psr_efu_fdo ), | |
14555 | .mio_psr_testclkr_sds0 (mio_psr_testclkr ), | |
14556 | .mio_psr_testclkt_sds0 (mio_psr_testclkt ), | |
14557 | .mio_psr_testclkr_sds1 (mio_psr_testclkr ), | |
14558 | .mio_psr_testclkt_sds1 (mio_psr_testclkt ), | |
14559 | ||
14560 | // Int 6.1: Short RXBCLKIN to RXBCLK per I/O, Clk team resolution. | |
14561 | .peu_psr_rxbclkin ({ psr_peu_rxbclk_b3sds1, psr_peu_rxbclk_b2sds1, | |
14562 | psr_peu_rxbclk_b1sds1, psr_peu_rxbclk_b0sds1, | |
14563 | psr_peu_rxbclk_b3sds0, psr_peu_rxbclk_b2sds0, | |
14564 | psr_peu_rxbclk_b1sds0, psr_peu_rxbclk_b0sds0 } ), | |
14565 | .psr_atpgd (fsr_left_atpgq ) , | |
14566 | .psr_atpgq (esr_atpgd ), | |
14567 | .PEX_RX_N(PEX_RX_N[7:0]), | |
14568 | .PEX_RX_P(PEX_RX_P[7:0]), | |
14569 | .PEX_REFCLK_N(PEX_REFCLK_N), | |
14570 | .PEX_REFCLK_P(PEX_REFCLK_P), | |
14571 | .dmu_psr_pll_en_sds0(dmu_psr_pll_en_sds0), | |
14572 | .dmu_psr_pll_en_sds1(dmu_psr_pll_en_sds1), | |
14573 | .dmu_psr_rx_en_b0_sds0(dmu_psr_rx_en_b0_sds0), | |
14574 | .dmu_psr_rx_en_b1_sds0(dmu_psr_rx_en_b1_sds0), | |
14575 | .dmu_psr_rx_en_b2_sds0(dmu_psr_rx_en_b2_sds0), | |
14576 | .dmu_psr_rx_en_b3_sds0(dmu_psr_rx_en_b3_sds0), | |
14577 | .dmu_psr_rx_en_b0_sds1(dmu_psr_rx_en_b0_sds1), | |
14578 | .dmu_psr_rx_en_b1_sds1(dmu_psr_rx_en_b1_sds1), | |
14579 | .dmu_psr_rx_en_b2_sds1(dmu_psr_rx_en_b2_sds1), | |
14580 | .dmu_psr_rx_en_b3_sds1(dmu_psr_rx_en_b3_sds1), | |
14581 | .dmu_psr_tx_en_b0_sds0(dmu_psr_tx_en_b0_sds0), | |
14582 | .dmu_psr_tx_en_b1_sds0(dmu_psr_tx_en_b1_sds0), | |
14583 | .dmu_psr_tx_en_b2_sds0(dmu_psr_tx_en_b2_sds0), | |
14584 | .dmu_psr_tx_en_b3_sds0(dmu_psr_tx_en_b3_sds0), | |
14585 | .dmu_psr_tx_en_b0_sds1(dmu_psr_tx_en_b0_sds1), | |
14586 | .dmu_psr_tx_en_b1_sds1(dmu_psr_tx_en_b1_sds1), | |
14587 | .dmu_psr_tx_en_b2_sds1(dmu_psr_tx_en_b2_sds1), | |
14588 | .dmu_psr_tx_en_b3_sds1(dmu_psr_tx_en_b3_sds1), | |
14589 | .peu_psr_td_b0sds0(peu_psr_td_b0sds0[9:0]), | |
14590 | .peu_psr_td_b1sds0(peu_psr_td_b1sds0[9:0]), | |
14591 | .peu_psr_td_b2sds0(peu_psr_td_b2sds0[9:0]), | |
14592 | .peu_psr_td_b3sds0(peu_psr_td_b3sds0[9:0]), | |
14593 | .peu_psr_td_b0sds1(peu_psr_td_b0sds1[9:0]), | |
14594 | .peu_psr_td_b1sds1(peu_psr_td_b1sds1[9:0]), | |
14595 | .peu_psr_td_b2sds1(peu_psr_td_b2sds1[9:0]), | |
14596 | .peu_psr_td_b3sds1(peu_psr_td_b3sds1[9:0]), | |
14597 | .peu_psr_invpair_b0sds0(peu_psr_invpair_b0sds0), | |
14598 | .peu_psr_invpair_b1sds0(peu_psr_invpair_b1sds0), | |
14599 | .peu_psr_invpair_b2sds0(peu_psr_invpair_b2sds0), | |
14600 | .peu_psr_invpair_b3sds0(peu_psr_invpair_b3sds0), | |
14601 | .peu_psr_invpair_b0sds1(peu_psr_invpair_b0sds1), | |
14602 | .peu_psr_invpair_b1sds1(peu_psr_invpair_b1sds1), | |
14603 | .peu_psr_invpair_b2sds1(peu_psr_invpair_b2sds1), | |
14604 | .peu_psr_invpair_b3sds1(peu_psr_invpair_b3sds1), | |
14605 | .peu_psr_rx_lane_ctl_0(peu_psr_rx_lane_ctl_0[15:0]), | |
14606 | .peu_psr_rx_lane_ctl_1(peu_psr_rx_lane_ctl_1[15:0]), | |
14607 | .peu_psr_rx_lane_ctl_2(peu_psr_rx_lane_ctl_2[15:0]), | |
14608 | .peu_psr_rx_lane_ctl_3(peu_psr_rx_lane_ctl_3[15:0]), | |
14609 | .peu_psr_rx_lane_ctl_4(peu_psr_rx_lane_ctl_4[15:0]), | |
14610 | .peu_psr_rx_lane_ctl_5(peu_psr_rx_lane_ctl_5[15:0]), | |
14611 | .peu_psr_rx_lane_ctl_6(peu_psr_rx_lane_ctl_6[15:0]), | |
14612 | .peu_psr_rx_lane_ctl_7(peu_psr_rx_lane_ctl_7[15:0]), | |
14613 | .peu_psr_rdtct_b0sds0(peu_psr_rdtct_b0sds0[1:0]), | |
14614 | .peu_psr_rdtct_b1sds0(peu_psr_rdtct_b1sds0[1:0]), | |
14615 | .peu_psr_rdtct_b2sds0(peu_psr_rdtct_b2sds0[1:0]), | |
14616 | .peu_psr_rdtct_b3sds0(peu_psr_rdtct_b3sds0[1:0]), | |
14617 | .peu_psr_rdtct_b0sds1(peu_psr_rdtct_b0sds1[1:0]), | |
14618 | .peu_psr_rdtct_b1sds1(peu_psr_rdtct_b1sds1[1:0]), | |
14619 | .peu_psr_rdtct_b2sds1(peu_psr_rdtct_b2sds1[1:0]), | |
14620 | .peu_psr_rdtct_b3sds1(peu_psr_rdtct_b3sds1[1:0]), | |
14621 | .peu_psr_enidl_b0sds0(peu_psr_enidl_b0sds0), | |
14622 | .peu_psr_enidl_b1sds0(peu_psr_enidl_b1sds0), | |
14623 | .peu_psr_enidl_b2sds0(peu_psr_enidl_b2sds0), | |
14624 | .peu_psr_enidl_b3sds0(peu_psr_enidl_b3sds0), | |
14625 | .peu_psr_enidl_b0sds1(peu_psr_enidl_b0sds1), | |
14626 | .peu_psr_enidl_b1sds1(peu_psr_enidl_b1sds1), | |
14627 | .peu_psr_enidl_b2sds1(peu_psr_enidl_b2sds1), | |
14628 | .peu_psr_enidl_b3sds1(peu_psr_enidl_b3sds1), | |
14629 | .peu_psr_bstx_b0sds0(peu_psr_bstx_b0sds0), | |
14630 | .peu_psr_bstx_b1sds0(peu_psr_bstx_b1sds0), | |
14631 | .peu_psr_bstx_b2sds0(peu_psr_bstx_b2sds0), | |
14632 | .peu_psr_bstx_b3sds0(peu_psr_bstx_b3sds0), | |
14633 | .peu_psr_bstx_b0sds1(peu_psr_bstx_b0sds1), | |
14634 | .peu_psr_bstx_b1sds1(peu_psr_bstx_b1sds1), | |
14635 | .peu_psr_bstx_b2sds1(peu_psr_bstx_b2sds1), | |
14636 | .peu_psr_bstx_b3sds1(peu_psr_bstx_b3sds1), | |
14637 | .peu_psr_tx_lane_ctl_0(peu_psr_tx_lane_ctl_0[9:0]), | |
14638 | .peu_psr_tx_lane_ctl_1(peu_psr_tx_lane_ctl_1[9:0]), | |
14639 | .peu_psr_tx_lane_ctl_2(peu_psr_tx_lane_ctl_2[9:0]), | |
14640 | .peu_psr_tx_lane_ctl_3(peu_psr_tx_lane_ctl_3[9:0]), | |
14641 | .peu_psr_tx_lane_ctl_4(peu_psr_tx_lane_ctl_4[9:0]), | |
14642 | .peu_psr_tx_lane_ctl_5(peu_psr_tx_lane_ctl_5[9:0]), | |
14643 | .peu_psr_tx_lane_ctl_6(peu_psr_tx_lane_ctl_6[9:0]), | |
14644 | .peu_psr_tx_lane_ctl_7(peu_psr_tx_lane_ctl_7[9:0]), | |
14645 | .peu_psr_txbclkin(peu_psr_txbclkin[7:0]), | |
14646 | .peu_psr_testcfg_sds0(peu_psr_testcfg_sds0[15:0]), | |
14647 | .peu_psr_testcfg_sds1(peu_psr_testcfg_sds1[15:0]), | |
14648 | .PEX_TX_N(PEX_TX_N[7:0]), | |
14649 | .PEX_TX_P(PEX_TX_P[7:0]), | |
14650 | .PEX_AMUX(PEX_AMUX[1:0]), | |
14651 | .psr_peu_rd_b0sds0(psr_peu_rd_b0sds0[9:0]), | |
14652 | .psr_peu_rd_b1sds0(psr_peu_rd_b1sds0[9:0]), | |
14653 | .psr_peu_rd_b2sds0(psr_peu_rd_b2sds0[9:0]), | |
14654 | .psr_peu_rd_b3sds0(psr_peu_rd_b3sds0[9:0]), | |
14655 | .psr_peu_rd_b0sds1(psr_peu_rd_b0sds1[9:0]), | |
14656 | .psr_peu_rd_b1sds1(psr_peu_rd_b1sds1[9:0]), | |
14657 | .psr_peu_rd_b2sds1(psr_peu_rd_b2sds1[9:0]), | |
14658 | .psr_peu_rd_b3sds1(psr_peu_rd_b3sds1[9:0]), | |
14659 | .psr_peu_rxbclk_b0sds0(psr_peu_rxbclk_b0sds0), | |
14660 | .psr_peu_rxbclk_b1sds0(psr_peu_rxbclk_b1sds0), | |
14661 | .psr_peu_rxbclk_b2sds0(psr_peu_rxbclk_b2sds0), | |
14662 | .psr_peu_rxbclk_b3sds0(psr_peu_rxbclk_b3sds0), | |
14663 | .psr_peu_rxbclk_b0sds1(psr_peu_rxbclk_b0sds1), | |
14664 | .psr_peu_rxbclk_b1sds1(psr_peu_rxbclk_b1sds1), | |
14665 | .psr_peu_rxbclk_b2sds1(psr_peu_rxbclk_b2sds1), | |
14666 | .psr_peu_rxbclk_b3sds1(psr_peu_rxbclk_b3sds1), | |
14667 | .psr_peu_bsrxn_b0sds0(psr_peu_bsrxn_b0sds0), | |
14668 | .psr_peu_bsrxn_b1sds0(psr_peu_bsrxn_b1sds0), | |
14669 | .psr_peu_bsrxn_b2sds0(psr_peu_bsrxn_b2sds0), | |
14670 | .psr_peu_bsrxn_b3sds0(psr_peu_bsrxn_b3sds0), | |
14671 | .psr_peu_bsrxn_b0sds1(psr_peu_bsrxn_b0sds1), | |
14672 | .psr_peu_bsrxn_b1sds1(psr_peu_bsrxn_b1sds1), | |
14673 | .psr_peu_bsrxn_b2sds1(psr_peu_bsrxn_b2sds1), | |
14674 | .psr_peu_bsrxn_b3sds1(psr_peu_bsrxn_b3sds1), | |
14675 | .psr_peu_bsrxp_b0sds0(psr_peu_bsrxp_b0sds0), | |
14676 | .psr_peu_bsrxp_b1sds0(psr_peu_bsrxp_b1sds0), | |
14677 | .psr_peu_bsrxp_b2sds0(psr_peu_bsrxp_b2sds0), | |
14678 | .psr_peu_bsrxp_b3sds0(psr_peu_bsrxp_b3sds0), | |
14679 | .psr_peu_bsrxp_b0sds1(psr_peu_bsrxp_b0sds1), | |
14680 | .psr_peu_bsrxp_b1sds1(psr_peu_bsrxp_b1sds1), | |
14681 | .psr_peu_bsrxp_b2sds1(psr_peu_bsrxp_b2sds1), | |
14682 | .psr_peu_bsrxp_b3sds1(psr_peu_bsrxp_b3sds1), | |
14683 | .psr_peu_losdtct_b0sds0(psr_peu_losdtct_b0sds0), | |
14684 | .psr_peu_losdtct_b1sds0(psr_peu_losdtct_b1sds0), | |
14685 | .psr_peu_losdtct_b2sds0(psr_peu_losdtct_b2sds0), | |
14686 | .psr_peu_losdtct_b3sds0(psr_peu_losdtct_b3sds0), | |
14687 | .psr_peu_losdtct_b0sds1(psr_peu_losdtct_b0sds1), | |
14688 | .psr_peu_losdtct_b1sds1(psr_peu_losdtct_b1sds1), | |
14689 | .psr_peu_losdtct_b2sds1(psr_peu_losdtct_b2sds1), | |
14690 | .psr_peu_losdtct_b3sds1(psr_peu_losdtct_b3sds1), | |
14691 | .psr_peu_sync_b0sds0(psr_peu_sync_b0sds0), | |
14692 | .psr_peu_sync_b1sds0(psr_peu_sync_b1sds0), | |
14693 | .psr_peu_sync_b2sds0(psr_peu_sync_b2sds0), | |
14694 | .psr_peu_sync_b3sds0(psr_peu_sync_b3sds0), | |
14695 | .psr_peu_sync_b0sds1(psr_peu_sync_b0sds1), | |
14696 | .psr_peu_sync_b1sds1(psr_peu_sync_b1sds1), | |
14697 | .psr_peu_sync_b2sds1(psr_peu_sync_b2sds1), | |
14698 | .psr_peu_sync_b3sds1(psr_peu_sync_b3sds1), | |
14699 | .psr_peu_rx_tstfail_b0sds0(psr_peu_rx_tstfail_b0sds0), | |
14700 | .psr_peu_rx_tstfail_b1sds0(psr_peu_rx_tstfail_b1sds0), | |
14701 | .psr_peu_rx_tstfail_b2sds0(psr_peu_rx_tstfail_b2sds0), | |
14702 | .psr_peu_rx_tstfail_b3sds0(psr_peu_rx_tstfail_b3sds0), | |
14703 | .psr_peu_rx_tstfail_b0sds1(psr_peu_rx_tstfail_b0sds1), | |
14704 | .psr_peu_rx_tstfail_b1sds1(psr_peu_rx_tstfail_b1sds1), | |
14705 | .psr_peu_rx_tstfail_b2sds1(psr_peu_rx_tstfail_b2sds1), | |
14706 | .psr_peu_rx_tstfail_b3sds1(psr_peu_rx_tstfail_b3sds1), | |
14707 | .psr_peu_rdtcip_b0sds0(psr_peu_rdtcip_b0sds0), | |
14708 | .psr_peu_rdtcip_b1sds0(psr_peu_rdtcip_b1sds0), | |
14709 | .psr_peu_rdtcip_b2sds0(psr_peu_rdtcip_b2sds0), | |
14710 | .psr_peu_rdtcip_b3sds0(psr_peu_rdtcip_b3sds0), | |
14711 | .psr_peu_rdtcip_b0sds1(psr_peu_rdtcip_b0sds1), | |
14712 | .psr_peu_rdtcip_b1sds1(psr_peu_rdtcip_b1sds1), | |
14713 | .psr_peu_rdtcip_b2sds1(psr_peu_rdtcip_b2sds1), | |
14714 | .psr_peu_rdtcip_b3sds1(psr_peu_rdtcip_b3sds1), | |
14715 | .psr_peu_tx_tstfail_b0sds0(psr_peu_tx_tstfail_b0sds0), | |
14716 | .psr_peu_tx_tstfail_b1sds0(psr_peu_tx_tstfail_b1sds0), | |
14717 | .psr_peu_tx_tstfail_b2sds0(psr_peu_tx_tstfail_b2sds0), | |
14718 | .psr_peu_tx_tstfail_b3sds0(psr_peu_tx_tstfail_b3sds0), | |
14719 | .psr_peu_tx_tstfail_b0sds1(psr_peu_tx_tstfail_b0sds1), | |
14720 | .psr_peu_tx_tstfail_b1sds1(psr_peu_tx_tstfail_b1sds1), | |
14721 | .psr_peu_tx_tstfail_b2sds1(psr_peu_tx_tstfail_b2sds1), | |
14722 | .psr_peu_tx_tstfail_b3sds1(psr_peu_tx_tstfail_b3sds1), | |
14723 | .psr_peu_lock_sds0(psr_peu_lock_sds0), | |
14724 | .psr_peu_lock_sds1(psr_peu_lock_sds1), | |
14725 | .psr_peu_txbclk0(psr_peu_txbclk0) | |
14726 | ); | |
14727 | `endif // OPENSPARC_CMP | |
14728 | ||
14729 | */ | |
14730 | ||
14731 | ||
14732 | //-------------------------------------------------------- | |
14733 | // added the following 5 IO modules | |
14734 | // // Ethernet SerDes (Called ges prior to 4-13-04.) //Replaced by real serdes | |
14735 | ||
14736 | //.testcfg_a (24'b0 ), | |
14737 | //.scancfg_a ( 2'b0 ), | |
14738 | //.scancfg_b ( 2'b0 ), | |
14739 | //.scanin_a ( 1'b0 ), | |
14740 | //.testclkr_a ( 1'b0 ), | |
14741 | //.testclkt_a ( 1'b0 ), | |
14742 | //.bstxd_a ( 4'b0 ), | |
14743 | //.cfg_a (48'b0 ), | |
14744 | //.enpll_a ( 1'b0 ), | |
14745 | //.enrx_a ( 4'b0 ), | |
14746 | //.jogcom_a ( 4'b0 ), | |
14747 | //.refclkn_a ( 1'b0 ), | |
14748 | //.refclkp_a ( 1'b0 ), | |
14749 | //.rxbclksta_a ( 4'b0 ), | |
14750 | //.rxn0_a ( 1'b0 ), | |
14751 | //.rxn1_a ( 1'b0 ), | |
14752 | //.rxn2_a ( 1'b0 ), | |
14753 | //.rxn3_a ( 1'b0 ), | |
14754 | //.rxp0_a ( 1'b0 ), | |
14755 | //.rxp1_a ( 1'b0 ), | |
14756 | //.rxp2_a ( 1'b0 ), | |
14757 | //.rxp3_a ( 1'b0 ), | |
14758 | //.rxbclkin_a ( 4'b0 ), | |
14759 | //.td0_a (10'b0 ), | |
14760 | //.td1_a (10'b0 ), | |
14761 | //.td2_a (10'b0 ), | |
14762 | //.td3_a (10'b0 ), | |
14763 | //.mdclk ( 1'b0 ), | |
14764 | //.mdo ( 1'b0 ), | |
14765 | //.mdo_0_en ( 1'b0 ), | |
14766 | //.vref ( 1'b0 ), | |
14767 | //.scanclk_a ( 1'b0 ), | |
14768 | //.txbclksta_a ( 4'b0 ), | |
14769 | //.txbclkin_a ( 4'b0 ), | |
14770 | //.testcfg_b (24'b0 ), | |
14771 | //.scanclk_b ( 1'b0 ), | |
14772 | //.scanin_b ( 1'b0 ), | |
14773 | //.testclkr_b ( 1'b0 ), | |
14774 | ||
14775 | //.scanin_b ( 1'b0 ), | |
14776 | //.testclkr_b ( 1'b0 ), | |
14777 | //.testclkt_b ( 1'b0 ), | |
14778 | //.bstxd_b ( 4'b0 ), | |
14779 | //.cfg_b (48'b0 ), | |
14780 | //.enpll_b ( 1'b0 ), | |
14781 | //.enrx_b ( 4'b0 ), | |
14782 | //.jogcom_b ( 4'b0 ), | |
14783 | //.refclkn_b ( 1'b0 ), | |
14784 | //.refclkp_b ( 1'b0 ), | |
14785 | //.rxbclksta_b ( 4'b0 ), | |
14786 | //.rxn0_b ( 1'b0 ), | |
14787 | //.rxn1_b ( 1'b0 ), | |
14788 | //.rxn2_b ( 1'b0 ), | |
14789 | //.rxn3_b ( 1'b0 ), | |
14790 | //.rxp0_b ( 1'b0 ), | |
14791 | //.rxp1_b ( 1'b0 ), | |
14792 | //.rxp2_b ( 1'b0 ), | |
14793 | //.rxp3_b ( 1'b0 ), | |
14794 | //.rxbclkin_b ( 4'b0 ), | |
14795 | //.td0_b (10'b0 ), | |
14796 | //.td1_b (10'b0 ), | |
14797 | //.td2_b (10'b0 ), | |
14798 | //.td3_b (10'b0 ), | |
14799 | //.txbclksta_b ( 4'b0 ), | |
14800 | //.txbclkin_b ( 4'b0 ) | |
14801 | ||
14802 | // ); | |
14803 | ||
14804 | // leave this instance out of cmp model | |
14805 | `ifdef OPENSPARC_CMP | |
14806 | `else | |
14807 | rst rst ( | |
14808 | .scan_in ( tcu_rst_scan_out ), | |
14809 | .scan_out ( rst_scan_out ), | |
14810 | //.mio_rst_pwron_rst_l ( mio_rst_pwron_rst_l ),// PWRON_RST_L | |
14811 | //.mio_rst_button_xir_l ( mio_rst_button_xir_l ),// BUTTON_XIR_L | |
14812 | //.mio_rst_pb_rst_l ( mio_rst_pb_rst_l ),// PB_RST_L | |
14813 | //.ccu_rst_sys_clk ( ccu_rst_sys_clk ),// Sunv name connect. | |
14814 | //.ccu_rst_change ( ccu_rst_change ),// Sunv name connect. | |
14815 | //.ccu_io_out ( ccu_io_out ),// Sunv name connect. | |
14816 | .gclk ( cmp_gclk_c1_db1 ), // ( cmp_gclk_c1_rst - for int6.1 | |
14817 | .ccu_io_cmp_sync_en ( gl_io_cmp_sync_en_c1m ), | |
14818 | .ccu_cmp_io_sync_en ( gl_cmp_io_sync_en_c1m ), | |
14819 | .tcu_rst_io_clk_stop ( gl_rst_io_clk_stop ),// staged clk_stop | |
14820 | .tcu_rst_clk_stop ( gl_rst_clk_stop ),// staged clk_stop | |
14821 | .ccu_io_out ( gl_io_out_c1m ), | |
14822 | .ccu_rst_sys_clk(ccu_rst_sys_clk), | |
14823 | .tcu_div_bypass(tcu_div_bypass), | |
14824 | .tcu_atpg_mode(tcu_atpg_mode), | |
14825 | .tcu_pce_ov(tcu_pce_ov), | |
14826 | .tcu_aclk(tcu_aclk), | |
14827 | .tcu_bclk(tcu_bclk), | |
14828 | .tcu_scan_en(tcu_scan_en), | |
14829 | .ccu_cmp_sys_sync_en(ccu_cmp_sys_sync_en), | |
14830 | .ccu_sys_cmp_sync_en(ccu_sys_cmp_sync_en), | |
14831 | .ncu_rst_vld(ncu_rst_vld), | |
14832 | .ncu_rst_data(ncu_rst_data[3:0]), | |
14833 | .rst_ncu_stall(rst_ncu_stall), | |
14834 | .rst_ncu_vld(rst_ncu_vld), | |
14835 | .rst_ncu_data(rst_ncu_data[3:0]), | |
14836 | .ncu_rst_stall(ncu_rst_stall), | |
14837 | .mio_rst_pwron_rst_l(mio_rst_pwron_rst_l), | |
14838 | .mio_rst_button_xir_l(mio_rst_button_xir_l), | |
14839 | .ncu_rst_xir_done(ncu_rst_xir_done), | |
14840 | .tcu_rst_flush_init_ack(tcu_rst_flush_init_ack), | |
14841 | .tcu_rst_flush_stop_ack(tcu_rst_flush_stop_ack), | |
14842 | .tcu_rst_asicflush_stop_ack(tcu_rst_asicflush_stop_ack), | |
14843 | .mio_rst_pb_rst_l(mio_rst_pb_rst_l), | |
14844 | .ccu_rst_change(ccu_rst_change), | |
14845 | .tcu_bisx_done(tcu_bisx_done), | |
14846 | .tcu_rst_efu_done(tcu_rst_efu_done), | |
14847 | .l2t0_rst_fatal_error(l2t0_rst_fatal_error), | |
14848 | .l2t1_rst_fatal_error(l2t1_rst_fatal_error), | |
14849 | .l2t2_rst_fatal_error(l2t2_rst_fatal_error), | |
14850 | .l2t3_rst_fatal_error(l2t3_rst_fatal_error), | |
14851 | .l2t4_rst_fatal_error(l2t4_rst_fatal_error), | |
14852 | .l2t5_rst_fatal_error(l2t5_rst_fatal_error), | |
14853 | .l2t6_rst_fatal_error(l2t6_rst_fatal_error), | |
14854 | .l2t7_rst_fatal_error(l2t7_rst_fatal_error), | |
14855 | .ncu_rst_fatal_error(ncu_rst_fatal_error), | |
14856 | .tcu_rst_scan_mode(tcu_rst_scan_mode), | |
14857 | .ccu_rst_sync_stable(ccu_rst_sync_stable), | |
14858 | .tcu_test_protect(tcu_test_protect), | |
14859 | .rst_l2_por_(rst_l2_por_), | |
14860 | .rst_l2_wmr_(rst_l2_wmr_), | |
14861 | .rst_ccu_pll_(rst_ccu_pll_), | |
14862 | .rst_ccu_(rst_ccu_), | |
14863 | .rst_wmr_protect(rst_wmr_protect), | |
14864 | .rst_tcu_clk_stop(rst_tcu_clk_stop), | |
14865 | .rst_mcu_selfrsh(rst_mcu_selfrsh), | |
14866 | .rst_tcu_flush_init_req(rst_tcu_flush_init_req), | |
14867 | .rst_tcu_flush_stop_req(rst_tcu_flush_stop_req), | |
14868 | .rst_tcu_asicflush_stop_req(rst_tcu_asicflush_stop_req), | |
14869 | .rst_niu_mac_(rst_niu_mac_), | |
14870 | .rst_niu_wmr_(rst_niu_wmr_), | |
14871 | .rst_dmu_peu_por_(rst_dmu_peu_por_), | |
14872 | .rst_dmu_peu_wmr_(rst_dmu_peu_wmr_), | |
14873 | .rst_ncu_unpark_thread(rst_ncu_unpark_thread), | |
14874 | .rst_ncu_xir_(rst_ncu_xir_), | |
14875 | .rst_mio_pex_reset_l(rst_mio_pex_reset_l), | |
14876 | .rst_mio_ssi_sync_l(rst_mio_ssi_sync_l), | |
14877 | .rst_mio_rst_state(rst_mio_rst_state[5:0]), | |
14878 | .cluster_arst_l(cluster_arst_l), | |
14879 | .rst_tcu_dbr_gen(rst_tcu_dbr_gen), | |
14880 | .rst_dmu_async_por_(rst_dmu_async_por_), | |
14881 | .rst_tcu_pwron_rst_l(rst_tcu_pwron_rst_l)// staged div phase | |
14882 | ); | |
14883 | `endif // OPENSPARC_CMP | |
14884 | //________________________________________________________________ | |
14885 | ||
14886 | ||
14887 | n2_revid_cust n2_revid_cust ( | |
14888 | .jtag_revid_in ( 4'h3 ), | |
14889 | .mask_minor ( 4'h1 ), | |
14890 | .jtag_revid_out(jtag_revid_out[3:0]), | |
14891 | .spc_revid_out(spc_revid_out[3:0])); | |
14892 | ||
14893 | //________________________________________________________________ | |
14894 | ||
14895 | n2_clk_gl_cust n2_clk_gl_cust ( | |
14896 | // PRIMARY INPUTS (FROM CCU) | |
14897 | .pll_dr_clk ( drl2clk ) , // .dr_pll_clk ( drl2clk ) , - for int6.1 | |
14898 | .pll_cmp_clk ( l2clk ) , // .cmp_pll_clk ( l2clk ) , - for int6.1 | |
14899 | // OTHERS -- AUTOMATIC CONNECTIONS | |
14900 | // PRIMARY INPUTS (FROM RST) -- AUTOMATIC CONNECTIONS | |
14901 | // PRIMARY INPUTS (FROM TCU) -- AUTOMATIC CONNECTIONS | |
14902 | // STAGED INPUTS | |
14903 | .stg1_ccx_clk_stop_in_c1b ( stg1_ccx_clk_stop_c1b ), | |
14904 | .stg1_cmp_io_sync_en_in_c1b ( stg1_cmp_io_sync_en_c1b ), | |
14905 | .stg1_cmp_io_sync_en_in_c1t ( stg1_cmp_io_sync_en_c1t ), | |
14906 | .stg1_db0_clk_stop_in_c1b ( stg1_db0_clk_stop_c1b ), | |
14907 | .stg1_dmu_io_clk_stop_in_c1b ( stg1_dmu_io_clk_stop_c1b ), | |
14908 | .stg1_dmu_peu_por_in_c1b ( stg1_dmu_peu_por_c1b ), | |
14909 | .stg1_dmu_peu_wmr_in_c1b ( stg1_dmu_peu_wmr_c1b ), | |
14910 | .stg1_dr_sync_en_in_c1t ( stg1_dr_sync_en_c1t ), | |
14911 | .stg1_io2x_out_in_c1b ( stg1_io2x_out_c1b ), | |
14912 | .stg1_io_cmp_sync_en_in_c1b ( stg1_io_cmp_sync_en_c1b ), | |
14913 | .stg1_io_cmp_sync_en_in_c1t ( stg1_io_cmp_sync_en_c1t ), | |
14914 | .stg1_io_out_in_c1b ( stg1_io_out_c1b ), | |
14915 | .stg1_io_out_in_c1t ( stg1_io_out_c1t ), | |
14916 | .stg1_l2_por_in_c1b ( stg1_rst_l2_por_c1b ),// UNDRIVEN stg1_l2_por_c1b | |
14917 | .stg1_l2_por_in_c1t ( stg1_rst_l2_por_c1t ),// UNDRIVEN stg1_l2_por_c1t | |
14918 | .stg1_l2_wmr_in_c1b ( stg1_rst_l2_wmr_c1b ),// UNDRIVEN stg1_l2_wmr_c1b | |
14919 | .stg1_l2_wmr_in_c1t ( stg1_rst_l2_wmr_c1t ),// UNDRIVEN stg1_l2_wmr_c1t | |
14920 | .stg1_l2b0_clk_stop_in_c1t ( stg1_l2b0_clk_stop_c1t ), | |
14921 | .stg1_l2b1_clk_stop_in_c1t ( stg1_l2b1_clk_stop_c1t ), | |
14922 | .stg1_l2b2_clk_stop_in_c1b ( stg1_l2b2_clk_stop_c1b ), | |
14923 | .stg1_l2b3_clk_stop_in_c1b ( stg1_l2b3_clk_stop_c1b ), | |
14924 | .stg1_l2b4_clk_stop_in_c1t ( stg1_l2b4_clk_stop_c1t ), | |
14925 | .stg1_l2b5_clk_stop_in_c1t ( stg1_l2b5_clk_stop_c1t ), | |
14926 | .stg1_l2d0_clk_stop_in_c1t ( stg1_l2d0_clk_stop_c1t ), | |
14927 | .stg1_l2d1_clk_stop_in_c1t ( stg1_l2d1_clk_stop_c1t ), | |
14928 | .stg1_l2d2_clk_stop_in_c1b ( stg1_l2d2_clk_stop_c1b ), | |
14929 | .stg1_l2d3_clk_stop_in_c1b ( stg1_l2d3_clk_stop_c1b ), | |
14930 | .stg1_l2d4_clk_stop_in_c1t ( stg1_l2d4_clk_stop_c1t ), | |
14931 | .stg1_l2d5_clk_stop_in_c1t ( stg1_l2d5_clk_stop_c1t ), | |
14932 | // .stg1_l2d6_clk_stop_in_c1b ( stg1_l2d6_clk_stop_c1b ), // ECO1.2 -mh157021 | |
14933 | .stg1_l2d7_clk_stop_in_c1b ( stg1_l2d7_clk_stop_c1b ), // ECO1.2 -mh157021 | |
14934 | .stg1_l2t0_clk_stop_in_c1t ( stg1_l2t0_clk_stop_c1t ), | |
14935 | .stg1_l2t1_clk_stop_in_c1t ( stg1_l2t1_clk_stop_c1t ), | |
14936 | .stg1_l2t2_clk_stop_in_c1b ( stg1_l2t2_clk_stop_c1b ), | |
14937 | .stg1_l2t3_clk_stop_in_c1b ( stg1_l2t3_clk_stop_c1b ), | |
14938 | .stg1_l2t5_clk_stop_in_c1t ( stg1_l2t5_clk_stop_c1t ), | |
14939 | .stg1_l2t7_clk_stop_in_c1b ( stg1_l2t7_clk_stop_c1b ), | |
14940 | .stg1_mac_io_clk_stop_in_c1b ( stg1_mac_io_clk_stop_c1b ), // UNDRIVEN stg1_mac_clk_stop_c1b | |
14941 | .stg1_mcu0_clk_stop_in_c1t ( stg1_mcu0_clk_stop_c1t ), | |
14942 | .stg1_mcu0_dr_clk_stop_in_c2b ( stg1_mcu0_dr_clk_stop_c1t ), // UNDRIVEN stg1_mcu0_dr_clk_stop_c2t | |
14943 | .stg1_mcu0_io_clk_stop_in_c1t ( stg1_mcu0_io_clk_stop_c1t ), | |
14944 | .stg1_mcu1_clk_stop_in_c1t ( stg1_mcu1_clk_stop_c1t ), | |
14945 | .stg1_mcu1_dr_clk_stop_in_c2b ( stg1_mcu1_dr_clk_stop_c1t ), // UNDRIVEN stg1_mcu1_dr_clk_stop_c2t | |
14946 | .stg1_mcu1_io_clk_stop_in_c1t ( stg1_mcu1_io_clk_stop_c1t ), | |
14947 | .stg1_mio_clk_stop_in_c1t ( stg1_mio_clk_stop_c1t ), | |
14948 | .stg1_mio_io2x_sync_en_in_c1t ( stg1_io2x_sync_en_c1t ), // UNDRIVEN stg1_mio_io2x_sync_en_c1t | |
14949 | .stg1_ncu_clk_stop_in_c1b ( stg1_ncu_clk_stop_c1b ), | |
14950 | .stg1_ncu_io_clk_stop_in_c1b ( stg1_ncu_io_clk_stop_c1b ), | |
14951 | .stg1_peu_io_clk_stop_in_c1b ( stg1_peu_io_clk_stop_c1b ), | |
14952 | .stg1_rdp_io_clk_stop_in_c1b ( stg1_rdp_io_clk_stop_c1b ), // UNDRIVEN stg1_rdp_clk_stop_c1b | |
14953 | .stg1_rst_mac_in_c1b ( stg1_rst_niu_mac_c1b ), // UNDRIVEN stg1_rst_mac_c1b | |
14954 | .stg1_rst_niu_wmr_in_c1b ( stg1_rst_niu_wmr_c1b ), | |
14955 | .stg1_tds_io_clk_stop_in_c1b (stg1_tds_io_clk_stop_c1b ), // UNDRIVEN stg1_tds_io_clk_stop_c1b | |
14956 | .stg1_rtx_io_clk_stop_in_c1b ( stg1_rtx_io_clk_stop_c1b ), // UNDRIVEN stg1_rtx_clk_stop_c1b | |
14957 | .stg1_sii_clk_stop_in_c1b ( stg1_sii_clk_stop_c1b ), | |
14958 | .stg1_sii_io_clk_stop_in_c1b ( stg1_sii_io_clk_stop_c1b ), | |
14959 | ||
14960 | .stg1_cmp_io_sync_en_in_c1bg ( stg1_cmp_io_sync_en_c1b ), // for int6.1 (set 3) | |
14961 | .stg1_cmp_io_sync_en_in_c1tg ( stg1_cmp_io_sync_en_c1t ), // for int6.1 (set 3) | |
14962 | .stg1_io_cmp_sync_en_in_c1bg ( stg1_io_cmp_sync_en_c1b ), // for int6.1 (set 3) | |
14963 | .stg1_io_cmp_sync_en_in_c1tg ( stg1_io_cmp_sync_en_c1t ), // for int6.1 (set 3) | |
14964 | .stg1_io_out_in_c1bg ( stg1_io_out_c1b ), // for int6.1 (set 3) | |
14965 | .stg1_l2_por_in_c1bg ( stg1_rst_l2_por_c1b ), // for int6.1 (set 3) | |
14966 | .stg1_l2_por_in_c1tg ( stg1_rst_l2_por_c1t ), // for int6.1 (set 3) | |
14967 | .stg1_l2_wmr_in_c1bg ( stg1_rst_l2_wmr_c1b ), // for int6.1 (set 3) | |
14968 | .stg1_l2_wmr_in_c1tg ( stg1_rst_l2_wmr_c1t ), // for int6.1 (set 3) | |
14969 | .stg1_mio_clk_stop_in_c1tg ( stg1_mio_clk_stop_c1t ), // for int6.1 (set 3) | |
14970 | .stg1_mio_io2x_sync_en_in_c1tg ( stg1_io2x_sync_en_c1t ), // for int6.1 (set 3) | |
14971 | .stg4_cmp_io_sync_en_in_c3t0 ( stg4_cmp_io_sync_en_c3t ), // for int6.1 (set 3) | |
14972 | .stg4_io_cmp_sync_en_in_c3t0 ( stg4_io_cmp_sync_en_c3t ), // for int6.1 (set 3) | |
14973 | .stg4_io_out_in_c3b0 ( stg4_io_out_c3b ), // for int6.1 (set 3) | |
14974 | .stg4_l2_por_in_c3t0 ( stg4_l2_por_c3t ), // for int6.1 (set 3) | |
14975 | .stg4_l2_wmr_in_c3t0 ( stg4_l2_wmr_c3t ), // for int6.1 (set 3) | |
14976 | ||
14977 | .stg1_spc0_clk_stop_in_c1t ( stg1_spc0_clk_stop_c1t ), | |
14978 | .stg1_spc1_clk_stop_in_c1t ( stg1_spc1_clk_stop_c1t ), | |
14979 | .stg1_spc2_clk_stop_in_c1b ( stg1_spc2_clk_stop_c1b ), | |
14980 | .stg1_spc3_clk_stop_in_c1b ( stg1_spc3_clk_stop_c1b ), | |
14981 | .stg1_spc4_clk_stop_in_c1t ( stg1_spc4_clk_stop_c1t ), | |
14982 | .stg1_spc5_clk_stop_in_c1t ( stg1_spc5_clk_stop_c1t ), | |
14983 | .stg1_spc6_clk_stop_in_c1b ( stg1_spc6_clk_stop_c1b ), // for int6.1 (set 3) | |
14984 | .stg1_spc7_clk_stop_in_c1b ( stg1_spc7_clk_stop_c1b ), | |
14985 | .stg2_ccx_clk_stop_in_c2b ( stg2_ccx_clk_stop_c1b ),// UNDRIVEN stg2_ccx_clk_stop_c2b | |
14986 | .stg2_cmp_io_sync_en_in_c2b ( stg2_cmp_io_sync_en_c1b ),// UNDRIVEN stg2_cmp_io_sync_en_c2b | |
14987 | .stg2_cmp_io_sync_en_in_c2t ( stg2_cmp_io_sync_en_c1t ),// UNDRIVEN stg2_cmp_io_sync_en_c2t | |
14988 | .stg2_db0_clk_stop_in_c2b ( stg2_db0_clk_stop_c1b ),// UNDRIVEN stg2_db0_clk_stop_c2b | |
14989 | .stg2_dmu_io_clk_stop_in_c2b ( stg2_dmu_io_clk_stop_c1b ), // UNDRIVEN stg2_dmu_io_clk_stop_c2b | |
14990 | .stg2_dmu_peu_por_in_c2b ( stg2_dmu_peu_por_c1b ), // UNDRIVEN stg2_dmu_peu_por_c2b | |
14991 | .stg2_dmu_peu_wmr_in_c2b ( stg2_dmu_peu_wmr_c1b ), // UNDRIVEN stg2_dmu_peu_wmr_c2b | |
14992 | .stg2_dr_sync_en_in_c2t ( stg2_dr_sync_en_c1t ),// stg2_dr_sync_en_c2t UNDRIVEN | |
14993 | .stg2_io_cmp_sync_en_in_c2b ( stg2_io_cmp_sync_en_c1b ),// UNDRIVEN stg2_io_cmp_sync_en_c2b | |
14994 | .stg2_io_cmp_sync_en_in_c2t ( stg2_io_cmp_sync_en_c1t ),// UNDRIVEN stg2_io_cmp_sync_en_c2t | |
14995 | .stg2_io_out_in_c2t ( stg2_io_out_c1t ),// UNDRIVEN stg2_io_out_c2t | |
14996 | .stg2_io_out_in_c2b ( stg2_io_out_c1b ),// UNDRIVEN stg2_io_out_c2b | |
14997 | .stg2_l2_por_in_c2b ( stg2_l2_por_c1b ),// UNDRIVEN stg2_l2_por_c2b | |
14998 | .stg2_l2_por_in_c2t ( stg2_l2_por_c1t ),// UNDRIVEN stg2_l2_por_c2t | |
14999 | .stg2_l2_wmr_in_c2b ( stg2_l2_wmr_c1b ),// UNDRIVEN stg2_l2_wmr_c2b | |
15000 | .stg2_l2_wmr_in_c2t ( stg2_l2_wmr_c1t ),// UNDRIVEN stg2_l2_wmr_c2t | |
15001 | .stg2_l2b0_clk_stop_in_c2t ( stg2_l2b0_clk_stop_c1t ), // UNDRIVEN stg2_l2b0_clk_stop_c2t | |
15002 | .stg2_l2b1_clk_stop_in_c2t ( stg2_l2b1_clk_stop_c1t ), // UNDRIVEN stg2_l2b1_clk_stop_c2t | |
15003 | .stg2_l2b2_clk_stop_in_c2b ( stg2_l2b2_clk_stop_c1b ),// UNDRIVEN stg2_l2b2_clk_stop_c2b | |
15004 | .stg2_l2b3_clk_stop_in_c2b ( stg2_l2b3_clk_stop_c1b ),// UNDRIVEN stg2_l2b3_clk_stop_c2b | |
15005 | .stg2_l2d0_clk_stop_in_c2t ( stg2_l2d0_clk_stop_c1t ),// UNDRIVEN stg2_l2d0_clk_stop_c2t | |
15006 | .stg2_l2d1_clk_stop_in_c2t ( stg2_l2d1_clk_stop_c1t ),// UNDRIVEN stg2_l2d1_clk_stop_c2t | |
15007 | .stg2_l2d2_clk_stop_in_c2b ( stg2_l2d2_clk_stop_c1b ),// UNDRIVEN stg2_l2d2_clk_stop_c2b | |
15008 | .stg2_l2d3_clk_stop_in_c2b ( stg2_l2d3_clk_stop_c1b ),// UNDRIVEN stg2_l2d3_clk_stop_c2b | |
15009 | .stg2_l2t0_clk_stop_in_c2t ( stg2_l2t0_clk_stop_c1t ),// UNDRIVEN stg2_l2t0_clk_stop_c2t | |
15010 | .stg2_l2t1_clk_stop_in_c2t ( stg2_l2t1_clk_stop_c1t ),// UNDRIVEN stg2_l2t1_clk_stop_c2t | |
15011 | .stg2_l2t2_clk_stop_in_c2b ( stg2_l2t2_clk_stop_c1b ),// UNDRIVEN stg2_l2t2_clk_stop_c2b | |
15012 | .stg2_l2t3_clk_stop_in_c2bz ( stg2_l2t3_clk_stop_c1b ),// UNDRIVEN stg2_l2t3_clk_stop_c2bz | |
15013 | .stg2_l2t5_clk_stop_in_c2t ( stg2_l2t5_clk_stop_c1t ),// UNDRIVEN stg2_l2t5_clk_stop_c2t | |
15014 | .stg2_l2t7_clk_stop_in_c2b ( stg2_l2t7_clk_stop_c1b ),// UNDRIVEN stg2_l2t7_clk_stop_c2b | |
15015 | .stg2_mio_io2x_sync_en_in_c2t ( stg2_mio_io2x_sync_en_c1t ), // UNDRIVEN stg2_mio_io2x_sync_en_c2t | |
15016 | .stg2_mio_clk_stop_in_c2t ( stg2_mio_clk_stop_c1t ),// UNDRIVEN stg2_mio_clk_stop_c2t | |
15017 | .stg2_ncu_clk_stop_in_c2b ( stg2_ncu_clk_stop_c1b ),// UNDRIVEN stg2_ncu_clk_stop_c2b | |
15018 | .stg2_ncu_io_clk_stop_in_c2b ( stg2_ncu_io_clk_stop_c1b ), // UNDRIVEN stg2_ncu_io_clk_stop_c2b | |
15019 | .stg2_peu_io_clk_stop_in_c2b ( stg2_peu_io_clk_stop_c1b ), // UNDRIVEN stg2_peu_io_clk_stop_c2b | |
15020 | .stg2_sii_clk_stop_in_c2b ( stg2_sii_clk_stop_c1b ), // UNDRIVEN stg2_sii_clk_stop_c2b | |
15021 | .stg2_sii_io_clk_stop_in_c2b ( stg2_sii_io_clk_stop_c1b ), // UNDRIVEN stg2_sii_io_clk_stop_c2b | |
15022 | .stg2_spc0_clk_stop_in_c2t ( stg2_spc0_clk_stop_c1t ), // UNDRIVEN stg2_spc0_clk_stop_c2t | |
15023 | .stg2_spc1_clk_stop_in_c2t ( stg2_spc1_clk_stop_c1t ), // UNDRIVEN stg2_spc1_clk_stop_c2t | |
15024 | .stg2_spc2_clk_stop_in_c2b ( stg2_spc2_clk_stop_c1b ), // UNDRIVEN stg2_spc2_clk_stop_c2b | |
15025 | .stg2_spc3_clk_stop_in_c2b ( stg2_spc3_clk_stop_c1b ), // UNDRIVEN stg2_spc3_clk_stop_c2b | |
15026 | .stg2_spc5_clk_stop_in_c2t ( stg2_spc5_clk_stop_c1t ), // UNDRIVEN stg2_spc5_clk_stop_c2t | |
15027 | .stg2_spc7_clk_stop_in_c2b ( stg2_spc7_clk_stop_c1b ), // UNDRIVEN stg2_spc7_clk_stop_c2b | |
15028 | .stg2_io2x_sync_en_in_c2t ( 1'b0 ), // ERROR: stg2_mio_io2x_sync_en_c2t | |
15029 | .stg3_ccx_clk_stop_in_c2b ( stg3_ccx_clk_stop_c2b ), | |
15030 | .stg3_cmp_io_sync_en_in_c2b ( stg3_cmp_io_sync_en_c2b ), // CHECK | |
15031 | .stg3_cmp_io_sync_en_in_c2t ( stg3_cmp_io_sync_en_c2t ), // CHECK | |
15032 | .stg3_cmp_io_sync_en_in_c3b ( stg3_cmp_io_sync_en_c2b ),// UNDRIVEN stg3_cmp_io_sync_en_c3b | |
15033 | .stg3_cmp_io_sync_en_in_c3t ( stg3_cmp_io_sync_en_c2t ),// UNDRIVEN stg3_cmp_io_sync_en_c3t | |
15034 | .stg3_db0_clk_stop_in_c3b ( stg3_db0_clk_stop_c2b ),// UNDRIVEN stg3_db0_clk_stop_c3b | |
15035 | .stg3_dmu_io_clk_stop_in_c3b ( stg3_dmu_io_clk_stop_c2b ),// UNDRIVEN stg3_dmu_io_clk_stop_c3b | |
15036 | .stg3_dmu_peu_por_in_c3b ( stg3_dmu_peu_por_c2b ), // UNDRIVEN stg3_dmu_peu_por_c3b | |
15037 | .stg3_dmu_peu_wmr_in_c3b ( stg3_dmu_peu_wmr_c2b ), // UNDRIVEN stg3_dmu_peu_wmr_c3b | |
15038 | .stg3_dr_sync_en_in_c3t ( stg3_dr_sync_en_c2t ), // stg3_dr_sync_en_c3t UNDRIVEN | |
15039 | .stg3_io2x_sync_en_in_c2t ( stg3_mio_io2x_sync_en_c2t ), // UNDRIVEN stg3_io2x_sync_en_c2t | |
15040 | .stg3_io_cmp_sync_en_in_c2b ( stg3_io_cmp_sync_en_c2b ), // CHECK | |
15041 | .stg3_io_cmp_sync_en_in_c2t ( stg3_io_cmp_sync_en_c2t ), // CHECK | |
15042 | .stg3_io_cmp_sync_en_in_c3b ( stg3_io_cmp_sync_en_c2b ), // UNDRIVEN stg3_io_cmp_sync_en_c3b | |
15043 | .stg3_io_cmp_sync_en_in_c3t ( stg3_io_cmp_sync_en_c2t ), // UNDRIVEN stg3_io_cmp_sync_en_c3t | |
15044 | .stg3_io_out_in_c3b ( stg3_io_out_c2b ), // UNDRIVEN stg3_io_out_c3b | |
15045 | .stg3_io_out_in_c3t ( stg3_io_out_c2t ), // UNDRIVEN stg3_io_out_c3t | |
15046 | .stg3_l2_por_in_c2b ( stg3_l2_por_c2b ), | |
15047 | .stg3_l2_por_in_c2t ( stg3_l2_por_c2t ), | |
15048 | .stg3_l2_por_in_c3b ( stg3_l2_por_c2b ), // UNDRIVEN stg3_l2_por_c3b | |
15049 | .stg3_l2_por_in_c3t ( stg3_l2_por_c2t ), // UNDRIVEN stg3_l2_por_c3t | |
15050 | .stg3_l2_wmr_in_c2b ( stg3_l2_wmr_c2b ), | |
15051 | .stg3_l2_wmr_in_c2t ( stg3_l2_wmr_c2t ), | |
15052 | .stg3_l2_wmr_in_c3b ( stg3_l2_wmr_c2b ), // UNDRIVEN stg3_l2_wmr_c3b | |
15053 | .stg3_l2_wmr_in_c3t ( stg3_l2_wmr_c2t ), // UNDRIVEN stg3_l2_wmr_c3t | |
15054 | .stg3_l2b0_clk_stop_in_c3t ( stg3_l2b0_clk_stop_c2t ), // UNDRIVEN stg3_l2b0_clk_stop_c3t | |
15055 | .stg3_l2b1_clk_stop_in_c3t ( stg3_l2b1_clk_stop_c2t ), // UNDRIVEN stg3_l2b1_clk_stop_c3t | |
15056 | .stg3_l2b2_clk_stop_in_c3b ( stg3_l2b2_clk_stop_c2b ), // UNDRIVEN stg3_l2b2_clk_stop_c3b | |
15057 | .stg3_l2b3_clk_stop_in_c3b ( stg3_l2b3_clk_stop_c2b ), // UNDRIVEN stg3_l2b3_clk_stop_c3b | |
15058 | .stg3_l2d0_clk_stop_in_c3t ( stg3_l2d0_clk_stop_c2t ), // UNDRIVEN stg3_l2d0_clk_stop_c3t | |
15059 | .stg3_l2d1_clk_stop_in_c3t ( stg3_l2d1_clk_stop_c2t ), // UNDRIVEN stg3_l2d1_clk_stop_c3t | |
15060 | .stg3_l2d2_clk_stop_in_c3b ( stg3_l2d2_clk_stop_c2b ), // UNDRIVEN stg3_l2d2_clk_stop_c3b | |
15061 | .stg3_l2d3_clk_stop_in_c3b ( stg3_l2d3_clk_stop_c2b ), // UNDRIVEN stg3_l2d3_clk_stop_c3b | |
15062 | .stg3_l2t0_clk_stop_in_c3t ( stg3_l2t0_clk_stop_c2t ), // UNDRIVEN stg3_l2t0_clk_stop_c3t | |
15063 | .stg3_l2t1_clk_stop_in_c2t ( stg3_l2t1_clk_stop_c2t ), // UNDRIVEN stg3_l2t1_clk_stop_c2t | |
15064 | .stg3_l2t2_clk_stop_in_c3b ( stg3_l2t2_clk_stop_c2b ), // UNDRIVEN stg3_l2t2_clk_stop_c3b | |
15065 | .stg3_l2t3_clk_stop_in_c2b ( stg3_l2t3_clk_stop_c2b ), | |
15066 | .stg3_l2t5_clk_stop_in_c2t ( stg3_l2t5_clk_stop_c2t ), | |
15067 | .stg3_l2t7_clk_stop_in_c2b ( stg3_l2t7_clk_stop_c2b ), | |
15068 | .stg3_mcu0_clk_stop_in_c3t ( stg3_mcu0_clk_stop_c2t ), // UNDRIVEN stg3_mcu0_clk_stop_c3t | |
15069 | .stg2_mcu0_dr_clk_stop_in_c4t ( stg2_mcu0_dr_clk_stop_c2b ), // UNDRIVEN stg2_mcu0_dr_clk_stop_c3t | |
15070 | .stg3_mcu0_io_clk_stop_in_c3t ( stg3_mcu0_io_clk_stop_c2t ), // UNDRIVEN stg3_mcu0_io_clk_stop_c3t | |
15071 | .stg3_mcu1_clk_stop_in_c3t ( stg3_mcu1_clk_stop_c2t ), // UNDRIVEN stg3_mcu1_clk_stop_c3t | |
15072 | .stg2_mcu1_dr_clk_stop_in_c4t ( stg2_mcu1_dr_clk_stop_c2b ), // UD stg2_mcu1_dr_clk_stop_c3t | |
15073 | .stg3_mcu1_io_clk_stop_in_c3t ( stg3_mcu1_io_clk_stop_c2t ), // UD stg3_mcu1_io_clk_stop_c3t | |
15074 | .stg3_mio_clk_stop_in_c2t ( stg3_mio_clk_stop_c2t ), | |
15075 | .stg3_mio_clk_stop_in_c3t ( stg3_mio_clk_stop_c2t ), // UNDRIVEN stg3_mio_clk_stop_c3t | |
15076 | .stg3_mio_io2x_sync_en_in_c3t ( stg3_mio_io2x_sync_en_c2t ),// UNDRIVEN stg3_mio_io2x_sync_en_c3t | |
15077 | .stg3_ncu_clk_stop_in_c3b ( stg3_ncu_clk_stop_c2b ), // UNDRIVEN stg3_ncu_clk_stop_c3b | |
15078 | .stg3_ncu_io_clk_stop_in_c3b ( stg3_ncu_io_clk_stop_c2b ),// UNDRIVEN stg3_ncu_io_clk_stop_c3b | |
15079 | .stg3_peu_io_clk_stop_in_c3b ( stg3_peu_io_clk_stop_c2b ),// UNDRIVEN stg3_peu_io_clk_stop_c3b | |
15080 | .stg3_sii_clk_stop_in_c3b ( stg3_sii_clk_stop_c2b ),// UNDRIVEN stg3_sii_clk_stop_c3b | |
15081 | .stg3_sii_io_clk_stop_in_c3b ( stg3_sii_io_clk_stop_c2b ),// UNDRIVEN stg3_sii_io_clk_stop_c3b | |
15082 | .stg3_spc0_clk_stop_in_c3t ( stg3_spc0_clk_stop_c2t ), // UNDRIVEN stg3_spc0_clk_stop_c3t | |
15083 | .stg3_spc1_clk_stop_in_c2t ( stg3_spc1_clk_stop_c2t ), // UNDRIVEN stg3_spc1_clk_stop_c2b | |
15084 | .stg3_spc2_clk_stop_in_c3b ( stg3_spc2_clk_stop_c2b ), // UNDRIVEN stg3_spc2_clk_stop_c3b | |
15085 | .stg3_spc3_clk_stop_in_c2b ( stg3_spc3_clk_stop_c2b ), | |
15086 | .stg3_spc5_clk_stop_in_c2t ( stg3_spc5_clk_stop_c2t ), // UNDRIVEN stg3_spc5_clk_stop_c2b | |
15087 | .stg3_spc7_clk_stop_in_c2b ( stg3_spc7_clk_stop_c2b ), | |
15088 | .stg4_cmp_io_sync_en_in_c3b ( stg4_cmp_io_sync_en_c3b ), | |
15089 | .stg4_cmp_io_sync_en_in_c3t ( stg4_cmp_io_sync_en_c3t ), | |
15090 | .stg4_db0_clk_stop_c3b ( stg4_db0_clk_stop_c3b ), // ERROR!! should be stg4_db0_clk_stop_in_c3b | |
15091 | .stg4_dmu_io_clk_stop_in_c3b ( stg4_dmu_io_clk_stop_c3b ), | |
15092 | .stg4_dmu_peu_por_in_c3b ( stg4_dmu_peu_por_c3b ), | |
15093 | .stg4_dmu_peu_wmr_in_c3b ( stg4_dmu_peu_wmr_c3b ), | |
15094 | .stg4_dr_sync_en_in_c3t ( stg4_dr_sync_en_c3t ), | |
15095 | .stg4_io2x_sync_en_in_c3t ( stg4_mio_io2x_sync_en_c3t ), // UNDRIVEN stg4_io2x_sync_en_c3t | |
15096 | .stg4_io_cmp_sync_en_in_c3b ( stg4_io_cmp_sync_en_c3b ), | |
15097 | .stg4_io_cmp_sync_en_in_c3t ( stg4_io_cmp_sync_en_c3t ), | |
15098 | .stg4_io_out_in_c3b ( stg4_io_out_c3b ), | |
15099 | .stg4_io_out_in_c3t ( stg4_io_out_c3t ), | |
15100 | .stg4_l2_por_in_c3b ( stg4_l2_por_c3b ), | |
15101 | .stg4_l2_por_in_c3t ( stg4_l2_por_c3t ), | |
15102 | .stg4_l2_wmr_in_c3b ( stg4_l2_wmr_c3b ), | |
15103 | .stg4_l2_wmr_in_c3t ( stg4_l2_wmr_c3t ), | |
15104 | .stg4_l2b0_clk_stop_in_c3t ( stg4_l2b0_clk_stop_c3t ), | |
15105 | .stg4_l2b1_clk_stop_in_c3t ( stg4_l2b1_clk_stop_c3t ), | |
15106 | .stg4_l2b2_clk_stop_in_c3b ( stg4_l2b2_clk_stop_c3b ), | |
15107 | .stg4_l2b3_clk_stop_in_c3b ( stg4_l2b3_clk_stop_c3b ), | |
15108 | .stg4_l2d0_clk_stop_in_c3t ( stg4_l2d0_clk_stop_c3t ), | |
15109 | .stg4_l2d1_clk_stop_in_c3t ( stg4_l2d1_clk_stop_c3t ), | |
15110 | .stg4_l2d2_clk_stop_in_c3b ( stg4_l2d2_clk_stop_c3b ), | |
15111 | .stg4_l2d3_clk_stop_in_c3b ( stg4_l2d3_clk_stop_c3b ), | |
15112 | .stg4_l2t0_clk_stop_in_c3t ( stg4_l2t0_clk_stop_c3t ), | |
15113 | .stg4_l2t2_clk_stop_in_c3b ( stg4_l2t2_clk_stop_c3b ), | |
15114 | // .stg4_mcu1_dr_clk_stop_in_c3t ( stg4_mcu1_dr_clk_stop_c3t ), | |
15115 | .stg4_mcu0_clk_stop_in_c3t ( stg4_mcu0_clk_stop_c3t ), | |
15116 | // .stg4_mcu0_dr_clk_stop_in_c3t ( stg4_mcu0_dr_clk_stop_c3t ), | |
15117 | .stg4_mcu0_io_clk_stop_in_c3t ( stg4_mcu0_io_clk_stop_c3t ), | |
15118 | .stg4_mcu1_clk_stop_in_c3t ( stg4_mcu1_clk_stop_c3t ), | |
15119 | .stg4_mcu1_io_clk_stop_in_c3t ( stg4_mcu1_io_clk_stop_c3t ), | |
15120 | .stg4_mio_clk_stop_in_c3t ( stg4_mio_clk_stop_c3t ), // UNDRIVEN stg4_mio_clk_stop_c3tz | |
15121 | .stg4_ncu_clk_stop_in_c3b ( stg4_ncu_clk_stop_c3b ), | |
15122 | .stg4_ncu_io_clk_stop_c3b ( stg4_ncu_io_clk_stop_c3b ), // ERROR!! - should be stg4_ncu_io_clk_stop_in_c3b | |
15123 | .stg4_peu_io_clk_stop_in_c3b ( stg4_peu_io_clk_stop_c3b ), | |
15124 | .stg4_sii_clk_stop_in_c3b ( stg4_sii_clk_stop_c3b ), | |
15125 | .stg4_sii_io_clk_stop_in_c3b ( stg4_sii_io_clk_stop_c3b ), | |
15126 | .stg4_spc0_clk_stop_in_c3t ( stg4_spc0_clk_stop_c3t ), | |
15127 | .stg4_spc2_clk_stop_in_c3b ( stg4_spc2_clk_stop_c3b ), | |
15128 | .stg2_mcu0_io_clk_stop_in_c2t ( stg2_mcu0_io_clk_stop_c1t ), // UD stg2_mcu0_io_clk_stop_c2t | |
15129 | // .stg2_mcu0_dr_clk_stop_in_c2t ( stg2_mcu0_dr_clk_stop_c1t ), // UD stg2_mcu0_dr_clk_stop_c2t | |
15130 | // .stg2_mcu1_dr_clk_stop_in_c2t ( stg2_mcu1_dr_clk_stop_c1t ), // UD stg2_mcu1_dr_clk_stop_c2t | |
15131 | .stg2_mcu1_io_clk_stop_in_c2t ( stg2_mcu1_io_clk_stop_c1t ), // UD stg2_mcu1_io_clk_stop_c2t | |
15132 | ||
15133 | // STAGED OUTPUTS | |
15134 | // .stg3_mcu0_dr_clk_stop_out_c2t ( stg3_mcu0_dr_clk_stop_c2t ), | |
15135 | .stg3_mcu0_io_clk_stop_out_c2t ( stg3_mcu0_io_clk_stop_c2t ), | |
15136 | // .stg3_mcu1_dr_clk_stop_out_c2t ( stg3_mcu1_dr_clk_stop_c2t ), | |
15137 | .stg3_mcu1_io_clk_stop_out_c2t ( stg3_mcu1_io_clk_stop_c2t ), | |
15138 | .stg1_ccx_clk_stop_out_c1b ( stg1_ccx_clk_stop_c1b ), | |
15139 | .stg1_cmp_io_sync_en_out_c1b ( stg1_cmp_io_sync_en_c1b ), | |
15140 | .stg1_cmp_io_sync_en_out_c1t ( stg1_cmp_io_sync_en_c1t ), | |
15141 | .stg1_db0_clk_stop_out_c1b ( stg1_db0_clk_stop_c1b ), | |
15142 | .stg1_dmu_io_clk_stop_out_c1b ( stg1_dmu_io_clk_stop_c1b ), | |
15143 | .stg1_dmu_peu_por_out_c1b ( stg1_dmu_peu_por_c1b ), | |
15144 | .stg1_dmu_peu_wmr_out_c1b ( stg1_dmu_peu_wmr_c1b ), | |
15145 | .stg1_dr_sync_en_out_c1t ( stg1_dr_sync_en_c1t ), | |
15146 | .stg1_io2x_out_out_c1b ( stg1_io2x_out_c1b ), | |
15147 | .stg1_io2x_sync_en_out_c1b ( stg1_io2x_sync_en_c1b ), | |
15148 | .stg1_io2x_sync_en_out_c1t ( stg1_io2x_sync_en_c1t ), | |
15149 | .stg1_io_cmp_sync_en_out_c1b ( stg1_io_cmp_sync_en_c1b ), | |
15150 | .stg1_io_cmp_sync_en_out_c1t ( stg1_io_cmp_sync_en_c1t ), | |
15151 | .stg1_io_out_out_c1b ( stg1_io_out_c1b ), | |
15152 | .stg1_io_out_out_c1t ( stg1_io_out_c1t ), | |
15153 | .stg1_l2b0_clk_stop_out_c1t ( stg1_l2b0_clk_stop_c1t ), | |
15154 | .stg1_l2b1_clk_stop_out_c1t ( stg1_l2b1_clk_stop_c1t ), | |
15155 | .stg1_l2b2_clk_stop_out_c1b ( stg1_l2b2_clk_stop_c1b ), | |
15156 | .stg1_l2b3_clk_stop_out_c1b ( stg1_l2b3_clk_stop_c1b ), | |
15157 | .stg1_l2b4_clk_stop_out_c1t ( stg1_l2b4_clk_stop_c1t ), | |
15158 | .stg1_l2b5_clk_stop_out_c1t ( stg1_l2b5_clk_stop_c1t ), | |
15159 | .stg1_l2d0_clk_stop_out_c1t ( stg1_l2d0_clk_stop_c1t ), | |
15160 | .stg1_l2d1_clk_stop_out_c1t ( stg1_l2d1_clk_stop_c1t ), | |
15161 | .stg1_l2d2_clk_stop_out_c1b ( stg1_l2d2_clk_stop_c1b ), | |
15162 | .stg1_l2d3_clk_stop_out_c1b ( stg1_l2d3_clk_stop_c1b ), | |
15163 | .stg1_l2d4_clk_stop_out_c1t ( stg1_l2d4_clk_stop_c1t ), | |
15164 | .stg1_l2d5_clk_stop_out_c1t ( stg1_l2d5_clk_stop_c1t ), | |
15165 | // .stg1_l2d6_clk_stop_out_c1b ( stg1_l2d6_clk_stop_c1b ), // ECO1.1 -mh157021 | |
15166 | .stg1_l2d7_clk_stop_out_c1b ( stg1_l2d7_clk_stop_c1b ), // ECO1.1 -mh157021 | |
15167 | .stg1_l2t0_clk_stop_out_c1t ( stg1_l2t0_clk_stop_c1t ), | |
15168 | .stg1_l2t1_clk_stop_out_c1t ( stg1_l2t1_clk_stop_c1t ), | |
15169 | .stg1_l2t2_clk_stop_out_c1b ( stg1_l2t2_clk_stop_c1b ), | |
15170 | .stg1_l2t3_clk_stop_out_c1b ( stg1_l2t3_clk_stop_c1b ), | |
15171 | .stg1_l2t5_clk_stop_out_c1t ( stg1_l2t5_clk_stop_c1t ), | |
15172 | .stg1_l2t7_clk_stop_out_c1b ( stg1_l2t7_clk_stop_c1b ), | |
15173 | .stg1_mac_io_clk_stop_out_c1b ( stg1_mac_io_clk_stop_c1b ), | |
15174 | .stg1_mcu0_clk_stop_out_c1t ( stg1_mcu0_clk_stop_c1t ), | |
15175 | .stg1_mcu0_dr_clk_stop_out_c1t ( stg1_mcu0_dr_clk_stop_c1t ), | |
15176 | .stg1_mcu0_io_clk_stop_out_c1t ( stg1_mcu0_io_clk_stop_c1t ), | |
15177 | .stg1_mcu1_clk_stop_out_c1t ( stg1_mcu1_clk_stop_c1t ), | |
15178 | .stg1_mcu1_dr_clk_stop_out_c1t ( stg1_mcu1_dr_clk_stop_c1t ), | |
15179 | .stg1_mcu1_io_clk_stop_out_c1t ( stg1_mcu1_io_clk_stop_c1t ), | |
15180 | .stg1_mio_clk_stop_out_c1t ( stg1_mio_clk_stop_c1t ), | |
15181 | .stg3_mio_clk_stop_out_c2t ( stg3_mio_clk_stop_c2t ), | |
15182 | .stg1_ncu_clk_stop_out_c1b ( stg1_ncu_clk_stop_c1b ), | |
15183 | .stg1_ncu_io_clk_stop_out_c1b ( stg1_ncu_io_clk_stop_c1b ), | |
15184 | .stg1_peu_io_clk_stop_out_c1b ( stg1_peu_io_clk_stop_c1b ), | |
15185 | .stg1_rdp_io_clk_stop_out_c1b ( stg1_rdp_io_clk_stop_c1b ), | |
15186 | .stg1_rst_l2_por_out_c1b ( stg1_rst_l2_por_c1b ), | |
15187 | .stg1_rst_l2_por_out_c1t ( stg1_rst_l2_por_c1t ), | |
15188 | .stg1_rst_l2_wmr_out_c1b ( stg1_rst_l2_wmr_c1b ), | |
15189 | .stg1_rst_l2_wmr_out_c1t ( stg1_rst_l2_wmr_c1t ), | |
15190 | .stg1_rst_niu_mac_out_c1b ( stg1_rst_niu_mac_c1b ), | |
15191 | .stg1_rst_niu_wmr_out_c1b ( stg1_rst_niu_wmr_c1b ), | |
15192 | .stg1_rtx_io_clk_stop_out_c1b ( stg1_rtx_io_clk_stop_c1b ), | |
15193 | .stg1_sii_clk_stop_out_c1b ( stg1_sii_clk_stop_c1b ), | |
15194 | .stg1_sii_io_clk_stop_out_c1b ( stg1_sii_io_clk_stop_c1b ), | |
15195 | .stg1_spc0_clk_stop_out_c1t ( stg1_spc0_clk_stop_c1t ), | |
15196 | .stg1_spc1_clk_stop_out_c1t ( stg1_spc1_clk_stop_c1t ), | |
15197 | .stg1_spc2_clk_stop_out_c1b ( stg1_spc2_clk_stop_c1b ), | |
15198 | .stg1_spc3_clk_stop_out_c1b ( stg1_spc3_clk_stop_c1b ), | |
15199 | .stg1_spc4_clk_stop_out_c1t ( stg1_spc4_clk_stop_c1t ), | |
15200 | .stg1_spc5_clk_stop_out_c1t ( stg1_spc5_clk_stop_c1t ), | |
15201 | .stg1_spc6_clk_stop_out_c1b ( stg1_spc6_clk_stop_c1b ), | |
15202 | .stg1_spc7_clk_stop_out_c1b ( stg1_spc7_clk_stop_c1b ), | |
15203 | .stg1_tds_io_clk_stop_out_c1b ( stg1_tds_io_clk_stop_c1b ), | |
15204 | .stg2_ccx_clk_stop_out_c1b ( stg2_ccx_clk_stop_c1b ), | |
15205 | .stg2_cmp_io_sync_en_out_c1b ( stg2_cmp_io_sync_en_c1b ), | |
15206 | .stg2_cmp_io_sync_en_out_c1t ( stg2_cmp_io_sync_en_c1t ), | |
15207 | .stg2_db0_clk_stop_out_c1b ( stg2_db0_clk_stop_c1b ), | |
15208 | .stg2_dmu_io_clk_stop_out_c1b ( stg2_dmu_io_clk_stop_c1b ), | |
15209 | .stg2_dmu_peu_por_out_c1b ( stg2_dmu_peu_por_c1b ), | |
15210 | .stg2_dmu_peu_wmr_out_c1b ( stg2_dmu_peu_wmr_c1b ), | |
15211 | .stg2_dr_sync_en_out_c1t ( stg2_dr_sync_en_c1t ), | |
15212 | .stg2_io_cmp_sync_en_out_c1b ( stg2_io_cmp_sync_en_c1b ), | |
15213 | .stg2_io_cmp_sync_en_out_c1t ( stg2_io_cmp_sync_en_c1t ), | |
15214 | .stg2_io_out_out_c1t ( stg2_io_out_c1t ), | |
15215 | .stg2_io_out_out_c1b ( stg2_io_out_c1b ), // marked | |
15216 | .stg2_l2_por_out_c1b ( stg2_l2_por_c1b ), | |
15217 | .stg2_l2_por_out_c1t ( stg2_l2_por_c1t ), | |
15218 | .stg2_l2_wmr_out_c1b ( stg2_l2_wmr_c1b ), | |
15219 | .stg2_l2_wmr_out_c1t ( stg2_l2_wmr_c1t ), | |
15220 | .stg2_l2b0_clk_stop_out_c1t ( stg2_l2b0_clk_stop_c1t ), | |
15221 | .stg2_l2b1_clk_stop_out_c1t ( stg2_l2b1_clk_stop_c1t ), | |
15222 | .stg2_l2b2_clk_stop_out_c1b ( stg2_l2b2_clk_stop_c1b ), | |
15223 | .stg2_l2b3_clk_stop_out_c1b ( stg2_l2b3_clk_stop_c1b ), | |
15224 | .stg2_l2d0_clk_stop_out_c1t ( stg2_l2d0_clk_stop_c1t ), | |
15225 | .stg2_l2d1_clk_stop_out_c1t ( stg2_l2d1_clk_stop_c1t ), | |
15226 | .stg2_l2d2_clk_stop_out_c1b ( stg2_l2d2_clk_stop_c1b ), | |
15227 | .stg2_l2d3_clk_stop_out_c1b ( stg2_l2d3_clk_stop_c1b ), | |
15228 | .stg2_l2t0_clk_stop_out_c1t ( stg2_l2t0_clk_stop_c1t ), | |
15229 | .stg2_l2t1_clk_stop_out_c1t ( stg2_l2t1_clk_stop_c1t ), | |
15230 | .stg2_l2t2_clk_stop_out_c1b ( stg2_l2t2_clk_stop_c1b ), | |
15231 | .stg2_l2t3_clk_stop_out_c1b ( stg2_l2t3_clk_stop_c1b ), | |
15232 | .stg2_l2t5_clk_stop_out_c1t ( stg2_l2t5_clk_stop_c1t ), | |
15233 | .stg2_l2t7_clk_stop_out_c1b ( stg2_l2t7_clk_stop_c1b ), | |
15234 | .stg2_mcu0_clk_stop_out_c1t ( stg2_mcu0_clk_stop_c1t ), | |
15235 | .stg2_mcu0_dr_clk_stop_out_c2b ( stg2_mcu0_dr_clk_stop_c2b ), | |
15236 | .stg2_mcu1_dr_clk_stop_out_c2b ( stg2_mcu1_dr_clk_stop_c2b ), | |
15237 | .stg2_mcu0_io_clk_stop_out_c1t ( stg2_mcu0_io_clk_stop_c1t ), | |
15238 | .stg2_mcu1_clk_stop_out_c1t ( stg2_mcu1_clk_stop_c1t ), | |
15239 | .stg2_mcu1_io_clk_stop_out_c1t ( stg2_mcu1_io_clk_stop_c1t ), | |
15240 | .stg2_mio_clk_stop_out_c1t ( stg2_mio_clk_stop_c1t ), | |
15241 | .stg2_mio_io2x_sync_en_out_c1t ( stg2_mio_io2x_sync_en_c1t ), | |
15242 | // .stg2_mio_io2x_sync_en_out_c2t (stg2_mio_io2x_sync_en_c2t ), | |
15243 | .stg2_ncu_clk_stop_out_c1b ( stg2_ncu_clk_stop_c1b ), | |
15244 | .stg2_ncu_io_clk_stop_out_c1b ( stg2_ncu_io_clk_stop_c1b ), | |
15245 | .stg2_peu_io_clk_stop_out_c1b ( stg2_peu_io_clk_stop_c1b ), | |
15246 | .stg2_sii_clk_stop_out_c1b ( stg2_sii_clk_stop_c1b ), | |
15247 | .stg2_sii_io_clk_stop_out_c1b ( stg2_sii_io_clk_stop_c1b ), | |
15248 | .stg2_spc0_clk_stop_out_c1t ( stg2_spc0_clk_stop_c1t ), | |
15249 | .stg2_spc1_clk_stop_out_c1t ( stg2_spc1_clk_stop_c1t ), | |
15250 | .stg2_spc2_clk_stop_out_c1b ( stg2_spc2_clk_stop_c1b ), | |
15251 | .stg2_spc3_clk_stop_out_c1b ( stg2_spc3_clk_stop_c1b ), | |
15252 | .stg2_spc5_clk_stop_out_c1t ( stg2_spc5_clk_stop_c1t ), | |
15253 | .stg2_spc7_clk_stop_out_c1b ( stg2_spc7_clk_stop_c1b ), | |
15254 | .stg3_ccx_clk_stop_out_c2b ( stg3_ccx_clk_stop_c2b ), | |
15255 | .stg3_cmp_io_sync_en_out_c2b ( stg3_cmp_io_sync_en_c2b ), | |
15256 | .stg3_cmp_io_sync_en_out_c2t ( stg3_cmp_io_sync_en_c2t ), | |
15257 | .stg3_db0_clk_stop_out_c2b ( stg3_db0_clk_stop_c2b ), | |
15258 | .stg3_dmu_io_clk_stop_out_c2b ( stg3_dmu_io_clk_stop_c2b ), | |
15259 | .stg3_dmu_peu_por_out_c2b ( stg3_dmu_peu_por_c2b ), | |
15260 | .stg3_dmu_peu_wmr_out_c2b ( stg3_dmu_peu_wmr_c2b ), | |
15261 | .stg3_dr_sync_en_out_c2t ( stg3_dr_sync_en_c2t ), | |
15262 | .stg3_io_cmp_sync_en_out_c2b ( stg3_io_cmp_sync_en_c2b ), | |
15263 | .stg3_io_cmp_sync_en_out_c2t ( stg3_io_cmp_sync_en_c2t ), | |
15264 | .stg3_io_out_out_c2t ( stg3_io_out_c2t ), | |
15265 | .stg3_l2_por_out_c2b ( stg3_l2_por_c2b ), | |
15266 | .stg3_l2_por_out_c2t ( stg3_l2_por_c2t ), | |
15267 | .stg3_l2_wmr_out_c2b ( stg3_l2_wmr_c2b ), | |
15268 | .stg3_l2_wmr_out_c2t ( stg3_l2_wmr_c2t ), | |
15269 | .stg3_l2b0_clk_stop_out_c2t ( stg3_l2b0_clk_stop_c2t ), | |
15270 | .stg3_l2b1_clk_stop_out_c2t ( stg3_l2b1_clk_stop_c2t ), | |
15271 | .stg3_l2b2_clk_stop_out_c2b ( stg3_l2b2_clk_stop_c2b ), | |
15272 | .stg3_l2b3_clk_stop_out_c2b ( stg3_l2b3_clk_stop_c2b ), | |
15273 | .stg3_l2d0_clk_stop_out_c2t ( stg3_l2d0_clk_stop_c2t ), | |
15274 | .stg3_l2d1_clk_stop_out_c2t ( stg3_l2d1_clk_stop_c2t ), | |
15275 | .stg3_l2d2_clk_stop_out_c2b ( stg3_l2d2_clk_stop_c2b ), | |
15276 | .stg3_l2d3_clk_stop_out_c2b ( stg3_l2d3_clk_stop_c2b ), | |
15277 | .stg3_l2t0_clk_stop_out_c2t ( stg3_l2t0_clk_stop_c2t ), | |
15278 | .stg3_l2t1_clk_stop_out_c2t ( stg3_l2t1_clk_stop_c2t ), | |
15279 | .stg3_l2t2_clk_stop_out_c2b ( stg3_l2t2_clk_stop_c2b ), | |
15280 | .stg3_l2t3_clk_stop_out_c2b ( stg3_l2t3_clk_stop_c2b ), | |
15281 | .stg3_l2t5_clk_stop_out_c2t ( stg3_l2t5_clk_stop_c2t ), | |
15282 | .stg3_l2t7_clk_stop_out_c2b ( stg3_l2t7_clk_stop_c2b ), | |
15283 | .stg3_mio_io2x_sync_en_out_c2t ( stg3_mio_io2x_sync_en_c2t ), | |
15284 | // .stg3_mcu0_dr_clk_stop_out_c2t ( stg3_mcu0_dr_clk_stop_c2t ), | |
15285 | // .stg3_mcu1_dr_clk_stop_out_c2t ( stg3_mcu1_dr_clk_stop_c2t ), | |
15286 | .stg3_ncu_clk_stop_out_c2b ( stg3_ncu_clk_stop_c2b ), | |
15287 | .stg3_ncu_io_clk_stop_out_c2b ( stg3_ncu_io_clk_stop_c2b ), | |
15288 | .stg3_io_out_out_c2b ( stg3_io_out_c2b ), // marked | |
15289 | .stg3_peu_io_clk_stop_out_c2b ( stg3_peu_io_clk_stop_c2b ), | |
15290 | .stg3_sii_clk_stop_out_c2b ( stg3_sii_clk_stop_c2b ), | |
15291 | .stg3_sii_io_clk_stop_out_c2b ( stg3_sii_io_clk_stop_c2b ), | |
15292 | .stg3_spc0_clk_stop_out_c2t ( stg3_spc0_clk_stop_c2t ), | |
15293 | .stg3_spc1_clk_stop_out_c2t ( stg3_spc1_clk_stop_c2t ), | |
15294 | .stg3_spc2_clk_stop_out_c2b ( stg3_spc2_clk_stop_c2b ), | |
15295 | .stg3_spc3_clk_stop_out_c2b ( stg3_spc3_clk_stop_c2b ), | |
15296 | .stg3_spc5_clk_stop_out_c2t ( stg3_spc5_clk_stop_c2t ), | |
15297 | .stg3_spc7_clk_stop_out_c2b ( stg3_spc7_clk_stop_c2b ), | |
15298 | .stg4_io2x_sync_en_c3t ( stg4_mio_io2x_sync_en_c3t ), // ECO1.3 .( stg4_io2x_sync_en_c3t ) -mh157021 | |
15299 | .stg4_cmp_io_sync_en_out_c3b ( stg4_cmp_io_sync_en_c3b ), | |
15300 | .stg4_cmp_io_sync_en_out_c3t ( stg4_cmp_io_sync_en_c3t ), | |
15301 | .stg4_db0_clk_stop_out_c3b ( stg4_db0_clk_stop_c3b ), | |
15302 | .stg4_dmu_io_clk_stop_out_c3b ( stg4_dmu_io_clk_stop_c3b ), | |
15303 | .stg4_dmu_peu_por_out_c3b ( stg4_dmu_peu_por_c3b ), | |
15304 | .stg4_dmu_peu_wmr_out_c3b ( stg4_dmu_peu_wmr_c3b ), | |
15305 | .stg4_dr_sync_en_out_c3t ( stg4_dr_sync_en_c3t ), | |
15306 | .stg3_io2x_sync_en_out_c2t (stg3_io2x_sync_en_c2t), // ERROR : UNUSED | |
15307 | // .stg4_io2x_sync_en_out_c2b ( stg4_io2x_sync_en_c2b ), | |
15308 | .stg4_io_cmp_sync_en_out_c3b ( stg4_io_cmp_sync_en_c3b ), | |
15309 | .stg4_io_cmp_sync_en_out_c3t ( stg4_io_cmp_sync_en_c3t ), | |
15310 | .stg4_io_out_out_c3b ( stg4_io_out_c3b ), | |
15311 | .stg4_io_out_out_c3t ( stg4_io_out_c3t ), | |
15312 | .stg4_l2_por_out_c3b ( stg4_l2_por_c3b ), | |
15313 | .stg4_l2_por_out_c3t ( stg4_l2_por_c3t ), | |
15314 | .stg4_l2_wmr_out_c3b ( stg4_l2_wmr_c3b ), | |
15315 | .stg4_l2_wmr_out_c3t ( stg4_l2_wmr_c3t ), | |
15316 | .stg4_l2b0_clk_stop_out_c3t ( stg4_l2b0_clk_stop_c3t ), | |
15317 | .stg4_l2b1_clk_stop_out_c3t ( stg4_l2b1_clk_stop_c3t ), | |
15318 | .stg4_l2b2_clk_stop_out_c3b ( stg4_l2b2_clk_stop_c3b ), | |
15319 | .stg4_l2b3_clk_stop_out_c3b ( stg4_l2b3_clk_stop_c3b ), | |
15320 | .stg4_l2d0_clk_stop_out_c3t ( stg4_l2d0_clk_stop_c3t ), | |
15321 | .stg4_l2d1_clk_stop_out_c3t ( stg4_l2d1_clk_stop_c3t ), | |
15322 | .stg4_l2d2_clk_stop_out_c3b ( stg4_l2d2_clk_stop_c3b ), | |
15323 | .stg4_l2d3_clk_stop_out_c3b ( stg4_l2d3_clk_stop_c3b ), | |
15324 | .stg4_l2t0_clk_stop_out_c3t ( stg4_l2t0_clk_stop_c3t ), | |
15325 | .stg4_l2t2_clk_stop_out_c3b ( stg4_l2t2_clk_stop_c3b ), | |
15326 | .stg4_mcu0_clk_stop_out_c3t ( stg4_mcu0_clk_stop_c3t ), | |
15327 | // .stg4_mcu0_dr_clk_stop_out_c3t ( stg4_mcu0_dr_clk_stop_c3t ), | |
15328 | .stg4_mcu0_io_clk_stop_out_c3t ( stg4_mcu0_io_clk_stop_c3t ), | |
15329 | .stg4_mcu1_clk_stop_out_c3t ( stg4_mcu1_clk_stop_c3t ), | |
15330 | // .stg4_mcu1_dr_clk_stop_out_c3t ( stg4_mcu1_dr_clk_stop_c3t ), | |
15331 | .stg4_mcu1_io_clk_stop_out_c3t ( stg4_mcu1_io_clk_stop_c3t ), | |
15332 | .stg4_mio_clk_stop_out_c3t ( stg4_mio_clk_stop_c3t ), | |
15333 | .stg4_mio_io2x_sync_en_out_c3t ( stg4_mio_io2x_sync_en_c3t ), | |
15334 | .stg4_ncu_clk_stop_out_c3b ( stg4_ncu_clk_stop_c3b ), | |
15335 | .stg4_ncu_io_clk_stop_out_c3b ( stg4_ncu_io_clk_stop_c3b ), | |
15336 | .stg4_peu_io_clk_stop_out_c3b ( stg4_peu_io_clk_stop_c3b ), | |
15337 | .stg4_sii_clk_stop_out_c3b ( stg4_sii_clk_stop_c3b ), | |
15338 | .stg4_sii_io_clk_stop_out_c3b ( stg4_sii_io_clk_stop_c3b ), | |
15339 | .stg4_spc0_clk_stop_out_c3t ( stg4_spc0_clk_stop_c3t ), | |
15340 | // .stg4_spc1_clk_stop_out_c2b ( stg4_spc1_clk_stop_c2b ), | |
15341 | .stg4_spc2_clk_stop_out_c3b ( stg4_spc2_clk_stop_c3b ), | |
15342 | // .stg4_spc5_clk_stop_out_c2b ( stg4_spc5_clk_stop_c2b ), | |
15343 | .stg2_mcu0_clk_stop_in_c2t ( stg2_mcu0_clk_stop_c1t ),// UNDRIVEN stg2_mcu0_clk_stop_in_c2t | |
15344 | .stg2_mcu1_clk_stop_in_c2t ( stg2_mcu1_clk_stop_c1t ),// UNDRIVEN stg2_mcu1_clk_stop_in_c2t | |
15345 | .stg3_mcu0_clk_stop_out_c2t ( stg3_mcu0_clk_stop_c2t ), | |
15346 | .stg3_mcu1_clk_stop_out_c2t ( stg3_mcu1_clk_stop_c2t ), | |
15347 | .cmp_gclk_c1_ccu(cmp_gclk_c1_ccu), | |
15348 | .cmp_gclk_c2_ccx_left(cmp_gclk_c2_ccx_left), | |
15349 | .cmp_gclk_c2_ccx_right(cmp_gclk_c2_ccx_right), | |
15350 | .cmp_gclk_c3_db0(cmp_gclk_c3_db0), | |
15351 | .cmp_gclk_c1_db1(cmp_gclk_c1_db1), | |
15352 | .cmp_gclk_c3_dmu(cmp_gclk_c3_dmu), | |
15353 | .cmp_gclk_c1_efu(cmp_gclk_c1_efu), | |
15354 | .cmp_gclk_c3_l2b0(cmp_gclk_c3_l2b0), | |
15355 | .cmp_gclk_c3_l2b1(cmp_gclk_c3_l2b1), | |
15356 | .cmp_gclk_c3_l2b2(cmp_gclk_c3_l2b2), | |
15357 | .cmp_gclk_c3_l2b3(cmp_gclk_c3_l2b3), | |
15358 | .cmp_gclk_c1_l2b4(cmp_gclk_c1_l2b4), | |
15359 | .cmp_gclk_c1_l2b5(cmp_gclk_c1_l2b5), | |
15360 | .cmp_gclk_c1_l2b6(cmp_gclk_c1_l2b6), | |
15361 | .cmp_gclk_c1_l2b7(cmp_gclk_c1_l2b7), | |
15362 | .cmp_gclk_c3_l2d0(cmp_gclk_c3_l2d0), | |
15363 | .cmp_gclk_c3_l2d1(cmp_gclk_c3_l2d1), | |
15364 | .cmp_gclk_c3_l2d2(cmp_gclk_c3_l2d2), | |
15365 | .cmp_gclk_c3_l2d3(cmp_gclk_c3_l2d3), | |
15366 | .cmp_gclk_c1_l2d4(cmp_gclk_c1_l2d4), | |
15367 | .cmp_gclk_c1_l2d5(cmp_gclk_c1_l2d5), | |
15368 | .cmp_gclk_c1_l2d6(cmp_gclk_c1_l2d6), | |
15369 | .cmp_gclk_c1_l2d7(cmp_gclk_c1_l2d7), | |
15370 | .cmp_gclk_c3_l2t0(cmp_gclk_c3_l2t0), | |
15371 | .cmp_gclk_c3_l2t2(cmp_gclk_c3_l2t2), | |
15372 | .cmp_gclk_c1_l2t4(cmp_gclk_c1_l2t4), | |
15373 | .cmp_gclk_c1_l2t6(cmp_gclk_c1_l2t6), | |
15374 | .cmp_gclk_c2_l2t1(cmp_gclk_c2_l2t1), | |
15375 | .cmp_gclk_c2_l2t3(cmp_gclk_c2_l2t3), | |
15376 | .cmp_gclk_c2_l2t5(cmp_gclk_c2_l2t5), | |
15377 | .cmp_gclk_c2_l2t7(cmp_gclk_c2_l2t7), | |
15378 | .cmp_gclk_c4_mcu0(cmp_gclk_c4_mcu0), | |
15379 | .cmp_gclk_c4_mcu1(cmp_gclk_c4_mcu1), | |
15380 | .cmp_gclk_c0_mcu2(cmp_gclk_c0_mcu2), | |
15381 | .cmp_gclk_c0_mcu3(cmp_gclk_c0_mcu3), | |
15382 | .dr_gclk_c4_mcu0(dr_gclk_c4_mcu0), | |
15383 | .dr_gclk_c4_mcu1(dr_gclk_c4_mcu1), | |
15384 | .dr_gclk_c0_mcu2(dr_gclk_c0_mcu2), | |
15385 | .dr_gclk_c0_mcu3(dr_gclk_c0_mcu3), | |
15386 | .cmp_gclk_c1_mio(cmp_gclk_c1_mio), | |
15387 | .cmp_gclk_c3_mio(cmp_gclk_c3_mio), | |
15388 | .cmp_gclk_c2_mio_left(cmp_gclk_c2_mio_left), | |
15389 | .cmp_gclk_c2_mio_right(cmp_gclk_c2_mio_right), | |
15390 | .cmp_gclk_c3_ncu(cmp_gclk_c3_ncu), | |
15391 | .cmp_gclk_c3_peu(cmp_gclk_c3_peu), | |
15392 | .cmp_gclk_c3_sii(cmp_gclk_c3_sii), | |
15393 | .cmp_gclk_c1_sio(cmp_gclk_c1_sio), | |
15394 | .cmp_gclk_c3_spc0(cmp_gclk_c3_spc0), | |
15395 | .cmp_gclk_c3_spc2(cmp_gclk_c3_spc2), | |
15396 | .cmp_gclk_c1_spc4(cmp_gclk_c1_spc4), | |
15397 | .cmp_gclk_c1_spc6(cmp_gclk_c1_spc6), | |
15398 | .cmp_gclk_c2_spc1(cmp_gclk_c2_spc1), | |
15399 | .cmp_gclk_c2_spc3(cmp_gclk_c2_spc3), | |
15400 | .cmp_gclk_c2_spc5(cmp_gclk_c2_spc5), | |
15401 | .cmp_gclk_c2_spc7(cmp_gclk_c2_spc7), | |
15402 | .cmp_gclk_c1_tcu(cmp_gclk_c1_tcu), | |
15403 | .cmp_gclk_c1_mac(cmp_gclk_c1_mac), | |
15404 | .cmp_gclk_c0_rdp(cmp_gclk_c0_rdp), | |
15405 | .cmp_gclk_c0_rtx(cmp_gclk_c0_rtx), | |
15406 | .cmp_gclk_c0_tds(cmp_gclk_c0_tds), | |
15407 | .cmp_gclk_c3_rng(cmp_gclk_c3_rng), | |
15408 | .dr_gclk_c4_fsr0_0(dr_gclk_c4_fsr0_0), | |
15409 | .dr_gclk_c4_fsr0_1(dr_gclk_c4_fsr0_1), | |
15410 | .dr_gclk_c4_fsr0_2(dr_gclk_c4_fsr0_2), | |
15411 | .dr_gclk_c4_fsr1_0(dr_gclk_c4_fsr1_0), | |
15412 | .dr_gclk_c4_fsr1_1(dr_gclk_c4_fsr1_1), | |
15413 | .dr_gclk_c4_fsr1_2(dr_gclk_c4_fsr1_2), | |
15414 | .dr_gclk_c4_fsr2_0(dr_gclk_c4_fsr2_0), | |
15415 | .dr_gclk_c4_fsr2_1(dr_gclk_c4_fsr2_1), | |
15416 | .dr_gclk_c4_fsr2_2(dr_gclk_c4_fsr2_2), | |
15417 | .dr_gclk_c4_fsr3_0(dr_gclk_c4_fsr3_0), | |
15418 | .dr_gclk_c4_fsr3_1(dr_gclk_c4_fsr3_1), | |
15419 | .dr_gclk_c4_fsr3_2(dr_gclk_c4_fsr3_2), | |
15420 | .dr_gclk_c0_fsr4_0(dr_gclk_c0_fsr4_0), | |
15421 | .dr_gclk_c0_fsr4_1(dr_gclk_c0_fsr4_1), | |
15422 | .dr_gclk_c0_fsr4_2(dr_gclk_c0_fsr4_2), | |
15423 | .dr_gclk_c0_fsr5_0(dr_gclk_c0_fsr5_0), | |
15424 | .dr_gclk_c0_fsr5_1(dr_gclk_c0_fsr5_1), | |
15425 | .dr_gclk_c0_fsr5_2(dr_gclk_c0_fsr5_2), | |
15426 | .dr_gclk_c0_fsr6_0(dr_gclk_c0_fsr6_0), | |
15427 | .dr_gclk_c0_fsr6_1(dr_gclk_c0_fsr6_1), | |
15428 | .dr_gclk_c0_fsr6_2(dr_gclk_c0_fsr6_2), | |
15429 | .dr_gclk_c2_fsr7_0(dr_gclk_c2_fsr7_0), | |
15430 | .dr_gclk_c2_fsr7_1(dr_gclk_c2_fsr7_1), | |
15431 | .dr_gclk_c2_fsr7_2(dr_gclk_c2_fsr7_2), | |
15432 | .ccu_cmp_io_sync_en(ccu_cmp_io_sync_en), | |
15433 | .ccu_dr_sync_en(ccu_dr_sync_en), | |
15434 | .ccu_io2x_out(ccu_io2x_out), | |
15435 | .ccu_io2x_sync_en(ccu_io2x_sync_en), | |
15436 | .ccu_io_cmp_sync_en(ccu_io_cmp_sync_en), | |
15437 | .ccu_io_out(ccu_io_out), | |
15438 | .ccu_vco_aligned(ccu_vco_aligned), | |
15439 | .gclk_aligned(gclk_aligned), | |
15440 | .gl_ccu_clk_stop(gl_ccu_clk_stop), | |
15441 | .gl_ccu_io_clk_stop(gl_ccu_io_clk_stop), | |
15442 | .gl_ccx_clk_stop(gl_ccx_clk_stop), | |
15443 | .gl_cmp_io_sync_en_c1b(gl_cmp_io_sync_en_c1b), | |
15444 | .gl_cmp_io_sync_en_c1m(gl_cmp_io_sync_en_c1m), | |
15445 | .gl_cmp_io_sync_en_c1t(gl_cmp_io_sync_en_c1t), | |
15446 | .gl_cmp_io_sync_en_c2b(gl_cmp_io_sync_en_c2b), | |
15447 | .gl_cmp_io_sync_en_c2t(gl_cmp_io_sync_en_c2t), | |
15448 | .gl_cmp_io_sync_en_c3b(gl_cmp_io_sync_en_c3b), | |
15449 | .gl_cmp_io_sync_en_c3t(gl_cmp_io_sync_en_c3t), | |
15450 | .gl_cmp_io_sync_en_c3t0(gl_cmp_io_sync_en_c3t0), | |
15451 | .gl_db0_clk_stop(gl_db0_clk_stop), | |
15452 | .gl_db1_clk_stop(gl_db1_clk_stop), | |
15453 | .gl_dmu_io_clk_stop(gl_dmu_io_clk_stop), | |
15454 | .gl_dmu_peu_por_c3b(gl_dmu_peu_por_c3b), | |
15455 | .gl_dmu_peu_wmr_c3b(gl_dmu_peu_wmr_c3b), | |
15456 | .gl_dr_sync_en_c1m(gl_dr_sync_en_c1m), | |
15457 | .gl_dr_sync_en_c3t(gl_dr_sync_en_c3t), | |
15458 | .gl_efu_clk_stop(gl_efu_clk_stop), | |
15459 | .gl_efu_io_clk_stop(gl_efu_io_clk_stop), | |
15460 | .gl_io2x_out_c1b(gl_io2x_out_c1b), | |
15461 | .gl_io2x_sync_en_c1m(gl_io2x_sync_en_c1m), | |
15462 | .gl_io2x_sync_en_c3t(gl_io2x_sync_en_c3t), | |
15463 | .gl_io2x_sync_en_c3t0(gl_io2x_sync_en_c3t0), | |
15464 | .gl_io2x_sync_en_c2t(gl_io2x_sync_en_c2t), | |
15465 | .gl_io_cmp_sync_en_c1b(gl_io_cmp_sync_en_c1b), | |
15466 | .gl_io_cmp_sync_en_c1m(gl_io_cmp_sync_en_c1m), | |
15467 | .gl_io_cmp_sync_en_c1t(gl_io_cmp_sync_en_c1t), | |
15468 | .gl_io_cmp_sync_en_c2b(gl_io_cmp_sync_en_c2b), | |
15469 | .gl_io_cmp_sync_en_c2t(gl_io_cmp_sync_en_c2t), | |
15470 | .gl_io_cmp_sync_en_c3b(gl_io_cmp_sync_en_c3b), | |
15471 | .gl_io_cmp_sync_en_c3t(gl_io_cmp_sync_en_c3t), | |
15472 | .gl_io_cmp_sync_en_c3t0(gl_io_cmp_sync_en_c3t0), | |
15473 | .gl_io_out_c1b(gl_io_out_c1b), | |
15474 | .gl_io_out_c1m(gl_io_out_c1m), | |
15475 | .gl_io_out_c3b(gl_io_out_c3b), | |
15476 | .gl_io_out_c3b0(gl_io_out_c3b0), | |
15477 | .gl_io_out_c3t(gl_io_out_c3t), | |
15478 | .gl_l2_por_c1t(gl_l2_por_c1t), | |
15479 | .gl_l2_por_c2b(gl_l2_por_c2b), | |
15480 | .gl_l2_por_c2t(gl_l2_por_c2t), | |
15481 | .gl_l2_por_c3b0(gl_l2_por_c3b0), | |
15482 | .gl_l2_por_c3t(gl_l2_por_c3t), | |
15483 | .gl_l2_por_c3t0(gl_l2_por_c3t0), | |
15484 | .gl_l2_wmr_c1b(gl_l2_wmr_c1b), | |
15485 | .gl_l2_wmr_c1t(gl_l2_wmr_c1t), | |
15486 | .gl_l2_wmr_c2b(gl_l2_wmr_c2b), | |
15487 | .gl_l2_wmr_c2t(gl_l2_wmr_c2t), | |
15488 | .gl_l2_wmr_c3b(gl_l2_wmr_c3b), | |
15489 | .gl_l2_wmr_c3t(gl_l2_wmr_c3t), | |
15490 | .gl_l2_wmr_c3t0(gl_l2_wmr_c3t0), | |
15491 | .gl_l2b0_clk_stop(gl_l2b0_clk_stop), | |
15492 | .gl_l2b1_clk_stop(gl_l2b1_clk_stop), | |
15493 | .gl_l2b2_clk_stop(gl_l2b2_clk_stop), | |
15494 | .gl_l2b3_clk_stop(gl_l2b3_clk_stop), | |
15495 | .gl_l2b4_clk_stop(gl_l2b4_clk_stop), | |
15496 | .gl_l2b5_clk_stop(gl_l2b5_clk_stop), | |
15497 | .gl_l2b6_clk_stop(gl_l2b6_clk_stop), | |
15498 | .gl_l2b7_clk_stop(gl_l2b7_clk_stop), | |
15499 | .gl_l2d0_clk_stop(gl_l2d0_clk_stop), | |
15500 | .gl_l2d1_clk_stop(gl_l2d1_clk_stop), | |
15501 | .gl_l2d2_clk_stop(gl_l2d2_clk_stop), | |
15502 | .gl_l2d3_clk_stop(gl_l2d3_clk_stop), | |
15503 | .gl_l2d4_clk_stop(gl_l2d4_clk_stop), | |
15504 | .gl_l2d5_clk_stop(gl_l2d5_clk_stop), | |
15505 | .gl_l2d6_clk_stop(gl_l2d6_clk_stop), | |
15506 | .gl_l2d7_clk_stop(gl_l2d7_clk_stop), | |
15507 | .gl_l2t0_clk_stop(gl_l2t0_clk_stop), | |
15508 | .gl_l2t1_clk_stop(gl_l2t1_clk_stop), | |
15509 | .gl_l2t2_clk_stop(gl_l2t2_clk_stop), | |
15510 | .gl_l2t3_clk_stop(gl_l2t3_clk_stop), | |
15511 | .gl_l2t4_clk_stop(gl_l2t4_clk_stop), | |
15512 | .gl_l2t5_clk_stop(gl_l2t5_clk_stop), | |
15513 | .gl_l2t6_clk_stop(gl_l2t6_clk_stop), | |
15514 | .gl_l2t7_clk_stop(gl_l2t7_clk_stop), | |
15515 | .gl_mac_io_clk_stop(gl_mac_io_clk_stop), | |
15516 | .gl_mcu0_clk_stop(gl_mcu0_clk_stop), | |
15517 | .gl_mcu0_dr_clk_stop(gl_mcu0_dr_clk_stop), | |
15518 | .gl_mcu0_io_clk_stop(gl_mcu0_io_clk_stop), | |
15519 | .gl_mcu1_clk_stop(gl_mcu1_clk_stop), | |
15520 | .gl_mcu1_dr_clk_stop(gl_mcu1_dr_clk_stop), | |
15521 | .gl_mcu1_io_clk_stop(gl_mcu1_io_clk_stop), | |
15522 | .gl_mcu2_clk_stop(gl_mcu2_clk_stop), | |
15523 | .gl_mcu2_dr_clk_stop(gl_mcu2_dr_clk_stop), | |
15524 | .gl_mcu2_io_clk_stop(gl_mcu2_io_clk_stop), | |
15525 | .gl_mcu3_clk_stop(gl_mcu3_clk_stop), | |
15526 | .gl_mcu3_dr_clk_stop(gl_mcu3_dr_clk_stop), | |
15527 | .gl_mcu3_io_clk_stop(gl_mcu3_io_clk_stop), | |
15528 | .gl_mio_clk_stop_c1t(gl_mio_clk_stop_c1t), | |
15529 | .gl_mio_clk_stop_c2t(gl_mio_clk_stop_c2t), | |
15530 | .gl_mio_clk_stop_c3t(gl_mio_clk_stop_c3t), | |
15531 | .gl_mio_io2x_sync_en_c1t(gl_mio_io2x_sync_en_c1t), | |
15532 | .gl_ncu_clk_stop(gl_ncu_clk_stop), | |
15533 | .gl_ncu_io_clk_stop(gl_ncu_io_clk_stop), | |
15534 | .gl_peu_io_clk_stop(gl_peu_io_clk_stop), | |
15535 | .gl_rdp_io_clk_stop(gl_rdp_io_clk_stop), | |
15536 | .gl_rst_clk_stop(gl_rst_clk_stop), | |
15537 | .gl_rst_io_clk_stop(gl_rst_io_clk_stop), | |
15538 | .gl_rst_l2_por_c1m(gl_rst_l2_por_c1m), | |
15539 | .gl_rst_l2_wmr_c1m(gl_rst_l2_wmr_c1m), | |
15540 | .gl_rst_mac_c1b(gl_rst_mac_c1b), | |
15541 | .gl_rst_niu_wmr_c1b(gl_rst_niu_wmr_c1b), | |
15542 | .gl_rtx_io_clk_stop(gl_rtx_io_clk_stop), | |
15543 | .gl_sii_clk_stop(gl_sii_clk_stop), | |
15544 | .gl_sii_io_clk_stop(gl_sii_io_clk_stop), | |
15545 | .gl_sio_clk_stop(gl_sio_clk_stop), | |
15546 | .gl_sio_io_clk_stop(gl_sio_io_clk_stop), | |
15547 | .gl_spc0_clk_stop(gl_spc0_clk_stop), | |
15548 | .gl_spc1_clk_stop(gl_spc1_clk_stop), | |
15549 | .gl_spc2_clk_stop(gl_spc2_clk_stop), | |
15550 | .gl_spc3_clk_stop(gl_spc3_clk_stop), | |
15551 | .gl_spc4_clk_stop(gl_spc4_clk_stop), | |
15552 | .gl_spc5_clk_stop(gl_spc5_clk_stop), | |
15553 | .gl_spc6_clk_stop(gl_spc6_clk_stop), | |
15554 | .gl_spc7_clk_stop(gl_spc7_clk_stop), | |
15555 | .gl_tds_io_clk_stop(gl_tds_io_clk_stop), | |
15556 | .rst_dmu_peu_por_(rst_dmu_peu_por_), | |
15557 | .rst_dmu_peu_wmr_(rst_dmu_peu_wmr_), | |
15558 | .rst_l2_por_(rst_l2_por_), | |
15559 | .rst_l2_wmr_(rst_l2_wmr_), | |
15560 | .rst_niu_mac_(rst_niu_mac_), | |
15561 | .gl_l2_por_c1b(gl_l2_por_c1b), | |
15562 | .rst_niu_wmr_(rst_niu_wmr_), | |
15563 | .tcu_ccu_clk_stop(tcu_ccu_clk_stop), | |
15564 | .tcu_ccu_io_clk_stop(tcu_ccu_io_clk_stop), | |
15565 | .tcu_ccx_clk_stop(tcu_ccx_clk_stop), | |
15566 | .tcu_db0_clk_stop(tcu_db0_clk_stop), | |
15567 | .tcu_db1_clk_stop(tcu_db1_clk_stop), | |
15568 | .tcu_dmu_io_clk_stop(tcu_dmu_io_clk_stop), | |
15569 | .tcu_efu_clk_stop(tcu_efu_clk_stop), | |
15570 | .tcu_efu_io_clk_stop(tcu_efu_io_clk_stop), | |
15571 | .tcu_l2b0_clk_stop(tcu_l2b0_clk_stop), | |
15572 | .tcu_l2b1_clk_stop(tcu_l2b1_clk_stop), | |
15573 | .tcu_l2b2_clk_stop(tcu_l2b2_clk_stop), | |
15574 | .tcu_l2b3_clk_stop(tcu_l2b3_clk_stop), | |
15575 | .tcu_l2b4_clk_stop(tcu_l2b4_clk_stop), | |
15576 | .tcu_l2b5_clk_stop(tcu_l2b5_clk_stop), | |
15577 | .tcu_l2b6_clk_stop(tcu_l2b6_clk_stop), | |
15578 | .tcu_l2b7_clk_stop(tcu_l2b7_clk_stop), | |
15579 | .tcu_l2d0_clk_stop(tcu_l2d0_clk_stop), | |
15580 | .tcu_l2d1_clk_stop(tcu_l2d1_clk_stop), | |
15581 | .tcu_l2d2_clk_stop(tcu_l2d2_clk_stop), | |
15582 | .tcu_l2d3_clk_stop(tcu_l2d3_clk_stop), | |
15583 | .tcu_l2d4_clk_stop(tcu_l2d4_clk_stop), | |
15584 | .tcu_l2d5_clk_stop(tcu_l2d5_clk_stop), | |
15585 | .tcu_l2d6_clk_stop(tcu_l2d6_clk_stop), | |
15586 | .tcu_l2d7_clk_stop(tcu_l2d7_clk_stop), | |
15587 | .tcu_l2t0_clk_stop(tcu_l2t0_clk_stop), | |
15588 | .tcu_l2t1_clk_stop(tcu_l2t1_clk_stop), | |
15589 | .tcu_l2t2_clk_stop(tcu_l2t2_clk_stop), | |
15590 | .tcu_l2t3_clk_stop(tcu_l2t3_clk_stop), | |
15591 | .tcu_l2t4_clk_stop(tcu_l2t4_clk_stop), | |
15592 | .tcu_l2t5_clk_stop(tcu_l2t5_clk_stop), | |
15593 | .tcu_l2t6_clk_stop(tcu_l2t6_clk_stop), | |
15594 | .tcu_l2t7_clk_stop(tcu_l2t7_clk_stop), | |
15595 | .tcu_mac_io_clk_stop(tcu_mac_io_clk_stop), | |
15596 | .tcu_mcu0_clk_stop(tcu_mcu0_clk_stop), | |
15597 | .tcu_mcu0_dr_clk_stop(tcu_mcu0_dr_clk_stop), | |
15598 | .tcu_mcu0_io_clk_stop(tcu_mcu0_io_clk_stop), | |
15599 | .tcu_mcu1_clk_stop(tcu_mcu1_clk_stop), | |
15600 | .tcu_mcu1_dr_clk_stop(tcu_mcu1_dr_clk_stop), | |
15601 | .tcu_mcu1_io_clk_stop(tcu_mcu1_io_clk_stop), | |
15602 | .tcu_mcu2_clk_stop(tcu_mcu2_clk_stop), | |
15603 | .tcu_mcu2_dr_clk_stop(tcu_mcu2_dr_clk_stop), | |
15604 | .tcu_mcu2_io_clk_stop(tcu_mcu2_io_clk_stop), | |
15605 | .tcu_mcu3_clk_stop(tcu_mcu3_clk_stop), | |
15606 | .tcu_mcu3_dr_clk_stop(tcu_mcu3_dr_clk_stop), | |
15607 | .tcu_mcu3_io_clk_stop(tcu_mcu3_io_clk_stop), | |
15608 | .tcu_mio_clk_stop(tcu_mio_clk_stop), | |
15609 | .tcu_ncu_clk_stop(tcu_ncu_clk_stop), | |
15610 | .tcu_ncu_io_clk_stop(tcu_ncu_io_clk_stop), | |
15611 | .tcu_peu_io_clk_stop(tcu_peu_io_clk_stop), | |
15612 | .tcu_rdp_io_clk_stop(tcu_rdp_io_clk_stop), | |
15613 | .tcu_rst_clk_stop(tcu_rst_clk_stop), | |
15614 | .tcu_rst_io_clk_stop(tcu_rst_io_clk_stop), | |
15615 | .tcu_rtx_io_clk_stop(tcu_rtx_io_clk_stop), | |
15616 | .tcu_sii_clk_stop(tcu_sii_clk_stop), | |
15617 | .tcu_sii_io_clk_stop(tcu_sii_io_clk_stop), | |
15618 | .tcu_sio_clk_stop(tcu_sio_clk_stop), | |
15619 | .tcu_sio_io_clk_stop(tcu_sio_io_clk_stop), | |
15620 | .tcu_spc0_clk_stop(tcu_spc0_clk_stop), | |
15621 | .tcu_spc1_clk_stop(tcu_spc1_clk_stop), | |
15622 | .tcu_spc2_clk_stop(tcu_spc2_clk_stop), | |
15623 | .tcu_spc3_clk_stop(tcu_spc3_clk_stop), | |
15624 | .tcu_spc4_clk_stop(tcu_spc4_clk_stop), | |
15625 | .tcu_spc5_clk_stop(tcu_spc5_clk_stop), | |
15626 | .tcu_spc6_clk_stop(tcu_spc6_clk_stop), | |
15627 | .tcu_spc7_clk_stop(tcu_spc7_clk_stop), | |
15628 | .tcu_tds_io_clk_stop(tcu_tds_io_clk_stop) | |
15629 | // PRIMARY OUTPUTS (CLKS) -- AUTOMATIC CONNECTIONS | |
15630 | // PRIMARY OUTPUTS -- AUTOMATIC CONNECTIONS | |
15631 | ); | |
15632 | ||
15633 | ||
15634 | ||
15635 | endmodule // cpu | |
15636 | ||
15637 |