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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_ilu_cib_csr_ilu_log_err_entry.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_ilu_cib_csr_ilu_log_err_entry | |
36 | ( | |
37 | // synopsys translate_off | |
38 | omni_ld, | |
39 | omni_data, | |
40 | omni_rw1c_alias, | |
41 | omni_rw1s_alias, | |
42 | // synopsys translate_on | |
43 | clk, | |
44 | por_l, | |
45 | w_ld, | |
46 | csrbus_wr_data, | |
47 | rw1c_alias, | |
48 | rw1s_alias, | |
49 | ilu_log_err_csrbus_read_data, | |
50 | ilu_log_err_spare3_s_hw_set, | |
51 | ilu_log_err_spare2_s_hw_set, | |
52 | ilu_log_err_spare1_s_hw_set, | |
53 | ilu_log_err_ihb_pe_s_hw_set, | |
54 | ilu_log_err_spare3_p_hw_set, | |
55 | ilu_log_err_spare2_p_hw_set, | |
56 | ilu_log_err_spare1_p_hw_set, | |
57 | ilu_log_err_ihb_pe_p_hw_set | |
58 | ); | |
59 | ||
60 | //==================================================================== | |
61 | // Polarity declarations | |
62 | //==================================================================== | |
63 | // synopsys translate_off | |
64 | input omni_ld; // Omni load | |
65 | // vlint flag_input_port_not_connected off | |
66 | input [`FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_WIDTH - 1:0] omni_data; | |
67 | // Omni write data | |
68 | // vlint flag_input_port_not_connected on | |
69 | input omni_rw1c_alias; // Omni load type: write-one-to-clear | |
70 | input omni_rw1s_alias; // Omni load type: write-one-to-set | |
71 | // synopsys translate_on | |
72 | input clk; // Clock signal | |
73 | input por_l; // Reset signal | |
74 | input w_ld; // SW load | |
75 | // vlint flag_input_port_not_connected off | |
76 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
77 | // vlint flag_input_port_not_connected on | |
78 | input rw1c_alias; // SW load type: write-one-to-clear | |
79 | input rw1s_alias; // SW load type: write-one-to-set | |
80 | output [`FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_WIDTH-1:0] ilu_log_err_csrbus_read_data; | |
81 | // SW read data | |
82 | input ilu_log_err_spare3_s_hw_set; // Hardware set signal for | |
83 | // ilu_log_err_spare3_s. When set | |
84 | // ilu_log_err will be set to one. | |
85 | input ilu_log_err_spare2_s_hw_set; // Hardware set signal for | |
86 | // ilu_log_err_spare2_s. When set | |
87 | // ilu_log_err will be set to one. | |
88 | input ilu_log_err_spare1_s_hw_set; // Hardware set signal for | |
89 | // ilu_log_err_spare1_s. When set | |
90 | // ilu_log_err will be set to one. | |
91 | input ilu_log_err_ihb_pe_s_hw_set; // Hardware set signal for | |
92 | // ilu_log_err_ihb_pe_s. When set | |
93 | // ilu_log_err will be set to one. | |
94 | input ilu_log_err_spare3_p_hw_set; // Hardware set signal for | |
95 | // ilu_log_err_spare3_p. When set | |
96 | // ilu_log_err will be set to one. | |
97 | input ilu_log_err_spare2_p_hw_set; // Hardware set signal for | |
98 | // ilu_log_err_spare2_p. When set | |
99 | // ilu_log_err will be set to one. | |
100 | input ilu_log_err_spare1_p_hw_set; // Hardware set signal for | |
101 | // ilu_log_err_spare1_p. When set | |
102 | // ilu_log_err will be set to one. | |
103 | input ilu_log_err_ihb_pe_p_hw_set; // Hardware set signal for | |
104 | // ilu_log_err_ihb_pe_p. When set | |
105 | // ilu_log_err will be set to one. | |
106 | ||
107 | //==================================================================== | |
108 | // Type declarations | |
109 | //==================================================================== | |
110 | // synopsys translate_off | |
111 | wire omni_ld; // Omni load | |
112 | // vlint flag_dangling_net_within_module off | |
113 | // vlint flag_net_has_no_load off | |
114 | wire [`FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_WIDTH - 1:0] omni_data; | |
115 | // Omni write data | |
116 | // vlint flag_dangling_net_within_module on | |
117 | // vlint flag_net_has_no_load on | |
118 | wire omni_rw1c_alias; // Omni load type: write-one-to-clear | |
119 | wire omni_rw1s_alias; // Omni load type: write-one-to-set | |
120 | // synopsys translate_on | |
121 | wire clk; // Clock signal | |
122 | wire por_l; // Reset signal | |
123 | wire w_ld; // SW load | |
124 | // vlint flag_dangling_net_within_module off | |
125 | // vlint flag_net_has_no_load off | |
126 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
127 | // vlint flag_dangling_net_within_module on | |
128 | // vlint flag_net_has_no_load on | |
129 | wire rw1c_alias; // SW load type: write-one-to-clear | |
130 | wire rw1s_alias; // SW load type: write-one-to-set | |
131 | wire [`FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_WIDTH-1:0] ilu_log_err_csrbus_read_data; | |
132 | // SW read data | |
133 | wire ilu_log_err_spare3_s_hw_set; // Hardware set signal for | |
134 | // ilu_log_err_spare3_s. When set ilu_log_err | |
135 | // will be set to one. | |
136 | wire ilu_log_err_spare2_s_hw_set; // Hardware set signal for | |
137 | // ilu_log_err_spare2_s. When set ilu_log_err | |
138 | // will be set to one. | |
139 | wire ilu_log_err_spare1_s_hw_set; // Hardware set signal for | |
140 | // ilu_log_err_spare1_s. When set ilu_log_err | |
141 | // will be set to one. | |
142 | wire ilu_log_err_ihb_pe_s_hw_set; // Hardware set signal for | |
143 | // ilu_log_err_ihb_pe_s. When set ilu_log_err | |
144 | // will be set to one. | |
145 | wire ilu_log_err_spare3_p_hw_set; // Hardware set signal for | |
146 | // ilu_log_err_spare3_p. When set ilu_log_err | |
147 | // will be set to one. | |
148 | wire ilu_log_err_spare2_p_hw_set; // Hardware set signal for | |
149 | // ilu_log_err_spare2_p. When set ilu_log_err | |
150 | // will be set to one. | |
151 | wire ilu_log_err_spare1_p_hw_set; // Hardware set signal for | |
152 | // ilu_log_err_spare1_p. When set ilu_log_err | |
153 | // will be set to one. | |
154 | wire ilu_log_err_ihb_pe_p_hw_set; // Hardware set signal for | |
155 | // ilu_log_err_ihb_pe_p. When set ilu_log_err | |
156 | // will be set to one. | |
157 | ||
158 | //==================================================================== | |
159 | // Logic | |
160 | //==================================================================== | |
161 | ||
162 | //----- Reset values | |
163 | // verilint 531 off | |
164 | wire [0:0] reset_spare3_s = 1'h0; | |
165 | wire [0:0] reset_spare2_s = 1'h0; | |
166 | wire [0:0] reset_spare1_s = 1'h0; | |
167 | wire [0:0] reset_ihb_pe_s = 1'h0; | |
168 | wire [0:0] reset_spare3_p = 1'h0; | |
169 | wire [0:0] reset_spare2_p = 1'h0; | |
170 | wire [0:0] reset_spare1_p = 1'h0; | |
171 | wire [0:0] reset_ihb_pe_p = 1'h0; | |
172 | // verilint 531 on | |
173 | ||
174 | //----- Active high reset wires | |
175 | wire por_l_active_high = ~por_l; | |
176 | ||
177 | //==================================================== | |
178 | // Instantiation of flops | |
179 | //==================================================== | |
180 | ||
181 | assign ilu_log_err_csrbus_read_data[0] = 1'b0; // bit 0 | |
182 | assign ilu_log_err_csrbus_read_data[1] = 1'b0; // bit 1 | |
183 | assign ilu_log_err_csrbus_read_data[2] = 1'b0; // bit 2 | |
184 | assign ilu_log_err_csrbus_read_data[3] = 1'b0; // bit 3 | |
185 | // bit 4 | |
186 | csr_sw csr_sw_4 | |
187 | ( | |
188 | // synopsys translate_off | |
189 | .omni_ld (omni_ld), | |
190 | .omni_data (omni_data[4]), | |
191 | .omni_rw_alias (1'b0), | |
192 | .omni_rw1c_alias (omni_rw1c_alias), | |
193 | .omni_rw1s_alias (omni_rw1s_alias), | |
194 | // synopsys translate_on | |
195 | .rst (por_l_active_high), | |
196 | .rst_val (reset_ihb_pe_p[0]), | |
197 | .csr_ld (w_ld), | |
198 | .csr_data (csrbus_wr_data[4]), | |
199 | .rw_alias (1'b0), | |
200 | .rw1c_alias (rw1c_alias), | |
201 | .rw1s_alias (rw1s_alias), | |
202 | .hw_ld (ilu_log_err_ihb_pe_p_hw_set), | |
203 | .hw_data (1'b1), | |
204 | .cp (clk), | |
205 | .q (ilu_log_err_csrbus_read_data[4]) | |
206 | ); | |
207 | ||
208 | // bit 5 | |
209 | csr_sw csr_sw_5 | |
210 | ( | |
211 | // synopsys translate_off | |
212 | .omni_ld (omni_ld), | |
213 | .omni_data (omni_data[5]), | |
214 | .omni_rw_alias (1'b0), | |
215 | .omni_rw1c_alias (omni_rw1c_alias), | |
216 | .omni_rw1s_alias (omni_rw1s_alias), | |
217 | // synopsys translate_on | |
218 | .rst (por_l_active_high), | |
219 | .rst_val (reset_spare1_p[0]), | |
220 | .csr_ld (w_ld), | |
221 | .csr_data (csrbus_wr_data[5]), | |
222 | .rw_alias (1'b0), | |
223 | .rw1c_alias (rw1c_alias), | |
224 | .rw1s_alias (rw1s_alias), | |
225 | .hw_ld (ilu_log_err_spare1_p_hw_set), | |
226 | .hw_data (1'b1), | |
227 | .cp (clk), | |
228 | .q (ilu_log_err_csrbus_read_data[5]) | |
229 | ); | |
230 | ||
231 | // bit 6 | |
232 | csr_sw csr_sw_6 | |
233 | ( | |
234 | // synopsys translate_off | |
235 | .omni_ld (omni_ld), | |
236 | .omni_data (omni_data[6]), | |
237 | .omni_rw_alias (1'b0), | |
238 | .omni_rw1c_alias (omni_rw1c_alias), | |
239 | .omni_rw1s_alias (omni_rw1s_alias), | |
240 | // synopsys translate_on | |
241 | .rst (por_l_active_high), | |
242 | .rst_val (reset_spare2_p[0]), | |
243 | .csr_ld (w_ld), | |
244 | .csr_data (csrbus_wr_data[6]), | |
245 | .rw_alias (1'b0), | |
246 | .rw1c_alias (rw1c_alias), | |
247 | .rw1s_alias (rw1s_alias), | |
248 | .hw_ld (ilu_log_err_spare2_p_hw_set), | |
249 | .hw_data (1'b1), | |
250 | .cp (clk), | |
251 | .q (ilu_log_err_csrbus_read_data[6]) | |
252 | ); | |
253 | ||
254 | // bit 7 | |
255 | csr_sw csr_sw_7 | |
256 | ( | |
257 | // synopsys translate_off | |
258 | .omni_ld (omni_ld), | |
259 | .omni_data (omni_data[7]), | |
260 | .omni_rw_alias (1'b0), | |
261 | .omni_rw1c_alias (omni_rw1c_alias), | |
262 | .omni_rw1s_alias (omni_rw1s_alias), | |
263 | // synopsys translate_on | |
264 | .rst (por_l_active_high), | |
265 | .rst_val (reset_spare3_p[0]), | |
266 | .csr_ld (w_ld), | |
267 | .csr_data (csrbus_wr_data[7]), | |
268 | .rw_alias (1'b0), | |
269 | .rw1c_alias (rw1c_alias), | |
270 | .rw1s_alias (rw1s_alias), | |
271 | .hw_ld (ilu_log_err_spare3_p_hw_set), | |
272 | .hw_data (1'b1), | |
273 | .cp (clk), | |
274 | .q (ilu_log_err_csrbus_read_data[7]) | |
275 | ); | |
276 | ||
277 | assign ilu_log_err_csrbus_read_data[8] = 1'b0; // bit 8 | |
278 | assign ilu_log_err_csrbus_read_data[9] = 1'b0; // bit 9 | |
279 | assign ilu_log_err_csrbus_read_data[10] = 1'b0; // bit 10 | |
280 | assign ilu_log_err_csrbus_read_data[11] = 1'b0; // bit 11 | |
281 | assign ilu_log_err_csrbus_read_data[12] = 1'b0; // bit 12 | |
282 | assign ilu_log_err_csrbus_read_data[13] = 1'b0; // bit 13 | |
283 | assign ilu_log_err_csrbus_read_data[14] = 1'b0; // bit 14 | |
284 | assign ilu_log_err_csrbus_read_data[15] = 1'b0; // bit 15 | |
285 | assign ilu_log_err_csrbus_read_data[16] = 1'b0; // bit 16 | |
286 | assign ilu_log_err_csrbus_read_data[17] = 1'b0; // bit 17 | |
287 | assign ilu_log_err_csrbus_read_data[18] = 1'b0; // bit 18 | |
288 | assign ilu_log_err_csrbus_read_data[19] = 1'b0; // bit 19 | |
289 | assign ilu_log_err_csrbus_read_data[20] = 1'b0; // bit 20 | |
290 | assign ilu_log_err_csrbus_read_data[21] = 1'b0; // bit 21 | |
291 | assign ilu_log_err_csrbus_read_data[22] = 1'b0; // bit 22 | |
292 | assign ilu_log_err_csrbus_read_data[23] = 1'b0; // bit 23 | |
293 | assign ilu_log_err_csrbus_read_data[24] = 1'b0; // bit 24 | |
294 | assign ilu_log_err_csrbus_read_data[25] = 1'b0; // bit 25 | |
295 | assign ilu_log_err_csrbus_read_data[26] = 1'b0; // bit 26 | |
296 | assign ilu_log_err_csrbus_read_data[27] = 1'b0; // bit 27 | |
297 | assign ilu_log_err_csrbus_read_data[28] = 1'b0; // bit 28 | |
298 | assign ilu_log_err_csrbus_read_data[29] = 1'b0; // bit 29 | |
299 | assign ilu_log_err_csrbus_read_data[30] = 1'b0; // bit 30 | |
300 | assign ilu_log_err_csrbus_read_data[31] = 1'b0; // bit 31 | |
301 | assign ilu_log_err_csrbus_read_data[32] = 1'b0; // bit 32 | |
302 | assign ilu_log_err_csrbus_read_data[33] = 1'b0; // bit 33 | |
303 | assign ilu_log_err_csrbus_read_data[34] = 1'b0; // bit 34 | |
304 | assign ilu_log_err_csrbus_read_data[35] = 1'b0; // bit 35 | |
305 | // bit 36 | |
306 | csr_sw csr_sw_36 | |
307 | ( | |
308 | // synopsys translate_off | |
309 | .omni_ld (omni_ld), | |
310 | .omni_data (omni_data[36]), | |
311 | .omni_rw_alias (1'b0), | |
312 | .omni_rw1c_alias (omni_rw1c_alias), | |
313 | .omni_rw1s_alias (omni_rw1s_alias), | |
314 | // synopsys translate_on | |
315 | .rst (por_l_active_high), | |
316 | .rst_val (reset_ihb_pe_s[0]), | |
317 | .csr_ld (w_ld), | |
318 | .csr_data (csrbus_wr_data[36]), | |
319 | .rw_alias (1'b0), | |
320 | .rw1c_alias (rw1c_alias), | |
321 | .rw1s_alias (rw1s_alias), | |
322 | .hw_ld (ilu_log_err_ihb_pe_s_hw_set), | |
323 | .hw_data (1'b1), | |
324 | .cp (clk), | |
325 | .q (ilu_log_err_csrbus_read_data[36]) | |
326 | ); | |
327 | ||
328 | // bit 37 | |
329 | csr_sw csr_sw_37 | |
330 | ( | |
331 | // synopsys translate_off | |
332 | .omni_ld (omni_ld), | |
333 | .omni_data (omni_data[37]), | |
334 | .omni_rw_alias (1'b0), | |
335 | .omni_rw1c_alias (omni_rw1c_alias), | |
336 | .omni_rw1s_alias (omni_rw1s_alias), | |
337 | // synopsys translate_on | |
338 | .rst (por_l_active_high), | |
339 | .rst_val (reset_spare1_s[0]), | |
340 | .csr_ld (w_ld), | |
341 | .csr_data (csrbus_wr_data[37]), | |
342 | .rw_alias (1'b0), | |
343 | .rw1c_alias (rw1c_alias), | |
344 | .rw1s_alias (rw1s_alias), | |
345 | .hw_ld (ilu_log_err_spare1_s_hw_set), | |
346 | .hw_data (1'b1), | |
347 | .cp (clk), | |
348 | .q (ilu_log_err_csrbus_read_data[37]) | |
349 | ); | |
350 | ||
351 | // bit 38 | |
352 | csr_sw csr_sw_38 | |
353 | ( | |
354 | // synopsys translate_off | |
355 | .omni_ld (omni_ld), | |
356 | .omni_data (omni_data[38]), | |
357 | .omni_rw_alias (1'b0), | |
358 | .omni_rw1c_alias (omni_rw1c_alias), | |
359 | .omni_rw1s_alias (omni_rw1s_alias), | |
360 | // synopsys translate_on | |
361 | .rst (por_l_active_high), | |
362 | .rst_val (reset_spare2_s[0]), | |
363 | .csr_ld (w_ld), | |
364 | .csr_data (csrbus_wr_data[38]), | |
365 | .rw_alias (1'b0), | |
366 | .rw1c_alias (rw1c_alias), | |
367 | .rw1s_alias (rw1s_alias), | |
368 | .hw_ld (ilu_log_err_spare2_s_hw_set), | |
369 | .hw_data (1'b1), | |
370 | .cp (clk), | |
371 | .q (ilu_log_err_csrbus_read_data[38]) | |
372 | ); | |
373 | ||
374 | // bit 39 | |
375 | csr_sw csr_sw_39 | |
376 | ( | |
377 | // synopsys translate_off | |
378 | .omni_ld (omni_ld), | |
379 | .omni_data (omni_data[39]), | |
380 | .omni_rw_alias (1'b0), | |
381 | .omni_rw1c_alias (omni_rw1c_alias), | |
382 | .omni_rw1s_alias (omni_rw1s_alias), | |
383 | // synopsys translate_on | |
384 | .rst (por_l_active_high), | |
385 | .rst_val (reset_spare3_s[0]), | |
386 | .csr_ld (w_ld), | |
387 | .csr_data (csrbus_wr_data[39]), | |
388 | .rw_alias (1'b0), | |
389 | .rw1c_alias (rw1c_alias), | |
390 | .rw1s_alias (rw1s_alias), | |
391 | .hw_ld (ilu_log_err_spare3_s_hw_set), | |
392 | .hw_data (1'b1), | |
393 | .cp (clk), | |
394 | .q (ilu_log_err_csrbus_read_data[39]) | |
395 | ); | |
396 | ||
397 | assign ilu_log_err_csrbus_read_data[40] = 1'b0; // bit 40 | |
398 | assign ilu_log_err_csrbus_read_data[41] = 1'b0; // bit 41 | |
399 | assign ilu_log_err_csrbus_read_data[42] = 1'b0; // bit 42 | |
400 | assign ilu_log_err_csrbus_read_data[43] = 1'b0; // bit 43 | |
401 | assign ilu_log_err_csrbus_read_data[44] = 1'b0; // bit 44 | |
402 | assign ilu_log_err_csrbus_read_data[45] = 1'b0; // bit 45 | |
403 | assign ilu_log_err_csrbus_read_data[46] = 1'b0; // bit 46 | |
404 | assign ilu_log_err_csrbus_read_data[47] = 1'b0; // bit 47 | |
405 | assign ilu_log_err_csrbus_read_data[48] = 1'b0; // bit 48 | |
406 | assign ilu_log_err_csrbus_read_data[49] = 1'b0; // bit 49 | |
407 | assign ilu_log_err_csrbus_read_data[50] = 1'b0; // bit 50 | |
408 | assign ilu_log_err_csrbus_read_data[51] = 1'b0; // bit 51 | |
409 | assign ilu_log_err_csrbus_read_data[52] = 1'b0; // bit 52 | |
410 | assign ilu_log_err_csrbus_read_data[53] = 1'b0; // bit 53 | |
411 | assign ilu_log_err_csrbus_read_data[54] = 1'b0; // bit 54 | |
412 | assign ilu_log_err_csrbus_read_data[55] = 1'b0; // bit 55 | |
413 | assign ilu_log_err_csrbus_read_data[56] = 1'b0; // bit 56 | |
414 | assign ilu_log_err_csrbus_read_data[57] = 1'b0; // bit 57 | |
415 | assign ilu_log_err_csrbus_read_data[58] = 1'b0; // bit 58 | |
416 | assign ilu_log_err_csrbus_read_data[59] = 1'b0; // bit 59 | |
417 | assign ilu_log_err_csrbus_read_data[60] = 1'b0; // bit 60 | |
418 | assign ilu_log_err_csrbus_read_data[61] = 1'b0; // bit 61 | |
419 | assign ilu_log_err_csrbus_read_data[62] = 1'b0; // bit 62 | |
420 | assign ilu_log_err_csrbus_read_data[63] = 1'b0; // bit 63 | |
421 | ||
422 | endmodule // dmu_ilu_cib_csr_ilu_log_err_entry |