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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_imu_ics_csr_imu_perf_cntrl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_imu_ics_csr_imu_perf_cntrl | |
36 | ( | |
37 | clk, | |
38 | rst_l, | |
39 | imu_perf_cntrl_w_ld, | |
40 | csrbus_wr_data, | |
41 | imu_perf_cntrl_csrbus_read_data, | |
42 | imu_perf_cntrl_sel1_hw_read, | |
43 | imu_perf_cntrl_sel0_hw_read | |
44 | ); | |
45 | ||
46 | //==================================================================== | |
47 | // Polarity declarations | |
48 | //==================================================================== | |
49 | input clk; // Clock | |
50 | input rst_l; // Reset signal | |
51 | input imu_perf_cntrl_w_ld; // SW load bus | |
52 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
53 | output [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_WIDTH-1:0] imu_perf_cntrl_csrbus_read_data; | |
54 | // SW read data | |
55 | output [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL1_INT_SLC] imu_perf_cntrl_sel1_hw_read; | |
56 | // This signal provides the current value of imu_perf_cntrl_sel1. | |
57 | output [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL0_INT_SLC] imu_perf_cntrl_sel0_hw_read; | |
58 | // This signal provides the current value of imu_perf_cntrl_sel0. | |
59 | ||
60 | //==================================================================== | |
61 | // Type declarations | |
62 | //==================================================================== | |
63 | wire clk; // Clock | |
64 | wire rst_l; // Reset signal | |
65 | wire imu_perf_cntrl_w_ld; // SW load bus | |
66 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
67 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_WIDTH-1:0] imu_perf_cntrl_csrbus_read_data; | |
68 | // SW read data | |
69 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL1_INT_SLC] imu_perf_cntrl_sel1_hw_read; | |
70 | // This signal provides the current value of imu_perf_cntrl_sel1. | |
71 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL0_INT_SLC] imu_perf_cntrl_sel0_hw_read; | |
72 | // This signal provides the current value of imu_perf_cntrl_sel0. | |
73 | ||
74 | //==================================================================== | |
75 | // Logic | |
76 | //==================================================================== | |
77 | ||
78 | // synopsys translate_off | |
79 | // verilint 123 off | |
80 | // verilint 498 off | |
81 | reg omni_ld; | |
82 | reg [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_WIDTH-1:0] omni_data; | |
83 | ||
84 | // vlint flag_unsynthesizable_initial off | |
85 | initial | |
86 | begin | |
87 | omni_ld = 1'b0; | |
88 | omni_data = `FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_WIDTH'b0; | |
89 | end// vlint flag_unsynthesizable_initial on | |
90 | ||
91 | // verilint 123 on | |
92 | // verilint 498 on | |
93 | // synopsys translate_on | |
94 | ||
95 | //----- Hardware Data Out Mux Assignments | |
96 | assign imu_perf_cntrl_sel1_hw_read= | |
97 | imu_perf_cntrl_csrbus_read_data | |
98 | [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL1_SLC]; | |
99 | assign imu_perf_cntrl_sel0_hw_read= | |
100 | imu_perf_cntrl_csrbus_read_data | |
101 | [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL0_SLC]; | |
102 | ||
103 | //==================================================================== | |
104 | // Instantiation of entries | |
105 | //==================================================================== | |
106 | ||
107 | //----- Entry 0 | |
108 | dmu_imu_ics_csr_imu_perf_cntrl_entry imu_perf_cntrl_0 | |
109 | ( | |
110 | // synopsys translate_off | |
111 | .omni_ld (omni_ld), | |
112 | .omni_data (omni_data), | |
113 | // synopsys translate_on | |
114 | .clk (clk), | |
115 | .rst_l (rst_l), | |
116 | .w_ld (imu_perf_cntrl_w_ld), | |
117 | .csrbus_wr_data (csrbus_wr_data), | |
118 | .imu_perf_cntrl_csrbus_read_data (imu_perf_cntrl_csrbus_read_data) | |
119 | ); | |
120 | ||
121 | endmodule // dmu_imu_ics_csr_imu_perf_cntrl |