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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_imu_ics_csr_msi_32_addr_reg_entry.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_imu_ics_csr_msi_32_addr_reg_entry | |
36 | ( | |
37 | // synopsys translate_off | |
38 | omni_ld, | |
39 | omni_data, | |
40 | // synopsys translate_on | |
41 | clk, | |
42 | rst_l, | |
43 | w_ld, | |
44 | csrbus_wr_data, | |
45 | msi_32_addr_reg_csrbus_read_data | |
46 | ); | |
47 | ||
48 | //==================================================================== | |
49 | // Polarity declarations | |
50 | //==================================================================== | |
51 | // synopsys translate_off | |
52 | input omni_ld; // Omni load | |
53 | // vlint flag_input_port_not_connected off | |
54 | input [`FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_WIDTH - 1:0] omni_data; | |
55 | // Omni write data | |
56 | // synopsys translate_on | |
57 | // vlint flag_input_port_not_connected on | |
58 | input clk; // Clock signal | |
59 | input rst_l; // Reset signal | |
60 | input w_ld; // SW load | |
61 | // vlint flag_input_port_not_connected off | |
62 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
63 | // vlint flag_input_port_not_connected on | |
64 | output [`FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_WIDTH-1:0] msi_32_addr_reg_csrbus_read_data; | |
65 | // SW read data | |
66 | ||
67 | //==================================================================== | |
68 | // Type declarations | |
69 | //==================================================================== | |
70 | // synopsys translate_off | |
71 | wire omni_ld; // Omni load | |
72 | // vlint flag_dangling_net_within_module off | |
73 | // vlint flag_net_has_no_load off | |
74 | wire [`FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_WIDTH - 1:0] omni_data; | |
75 | // Omni write data | |
76 | // synopsys translate_on | |
77 | // vlint flag_dangling_net_within_module on | |
78 | // vlint flag_net_has_no_load on | |
79 | wire clk; // Clock signal | |
80 | wire rst_l; // Reset signal | |
81 | wire w_ld; // SW load | |
82 | // vlint flag_dangling_net_within_module off | |
83 | // vlint flag_net_has_no_load off | |
84 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
85 | // vlint flag_dangling_net_within_module on | |
86 | // vlint flag_net_has_no_load on | |
87 | wire [`FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_WIDTH-1:0] msi_32_addr_reg_csrbus_read_data; | |
88 | // SW read data | |
89 | ||
90 | //==================================================================== | |
91 | // Logic | |
92 | //==================================================================== | |
93 | ||
94 | //----- Reset values | |
95 | // verilint 531 off | |
96 | wire [15:0] reset_addr = 16'h0; | |
97 | // verilint 531 on | |
98 | ||
99 | //----- Active high reset wires | |
100 | wire rst_l_active_high = ~rst_l; | |
101 | ||
102 | //==================================================== | |
103 | // Instantiation of flops | |
104 | //==================================================== | |
105 | ||
106 | assign msi_32_addr_reg_csrbus_read_data[0] = 1'b0; // bit 0 | |
107 | assign msi_32_addr_reg_csrbus_read_data[1] = 1'b0; // bit 1 | |
108 | assign msi_32_addr_reg_csrbus_read_data[2] = 1'b0; // bit 2 | |
109 | assign msi_32_addr_reg_csrbus_read_data[3] = 1'b0; // bit 3 | |
110 | assign msi_32_addr_reg_csrbus_read_data[4] = 1'b0; // bit 4 | |
111 | assign msi_32_addr_reg_csrbus_read_data[5] = 1'b0; // bit 5 | |
112 | assign msi_32_addr_reg_csrbus_read_data[6] = 1'b0; // bit 6 | |
113 | assign msi_32_addr_reg_csrbus_read_data[7] = 1'b0; // bit 7 | |
114 | assign msi_32_addr_reg_csrbus_read_data[8] = 1'b0; // bit 8 | |
115 | assign msi_32_addr_reg_csrbus_read_data[9] = 1'b0; // bit 9 | |
116 | assign msi_32_addr_reg_csrbus_read_data[10] = 1'b0; // bit 10 | |
117 | assign msi_32_addr_reg_csrbus_read_data[11] = 1'b0; // bit 11 | |
118 | assign msi_32_addr_reg_csrbus_read_data[12] = 1'b0; // bit 12 | |
119 | assign msi_32_addr_reg_csrbus_read_data[13] = 1'b0; // bit 13 | |
120 | assign msi_32_addr_reg_csrbus_read_data[14] = 1'b0; // bit 14 | |
121 | assign msi_32_addr_reg_csrbus_read_data[15] = 1'b0; // bit 15 | |
122 | // bit 16 | |
123 | csr_sw csr_sw_16 | |
124 | ( | |
125 | // synopsys translate_off | |
126 | .omni_ld (omni_ld), | |
127 | .omni_data (omni_data[16]), | |
128 | .omni_rw_alias (1'b1), | |
129 | .omni_rw1c_alias (1'b0), | |
130 | .omni_rw1s_alias (1'b0), | |
131 | // synopsys translate_on | |
132 | .rst (rst_l_active_high), | |
133 | .rst_val (reset_addr[0]), | |
134 | .csr_ld (w_ld), | |
135 | .csr_data (csrbus_wr_data[16]), | |
136 | .rw_alias (1'b1), | |
137 | .rw1c_alias (1'b0), | |
138 | .rw1s_alias (1'b0), | |
139 | .hw_ld (1'b0), | |
140 | .hw_data (1'b0), | |
141 | .cp (clk), | |
142 | .q (msi_32_addr_reg_csrbus_read_data[16]) | |
143 | ); | |
144 | ||
145 | // bit 17 | |
146 | csr_sw csr_sw_17 | |
147 | ( | |
148 | // synopsys translate_off | |
149 | .omni_ld (omni_ld), | |
150 | .omni_data (omni_data[17]), | |
151 | .omni_rw_alias (1'b1), | |
152 | .omni_rw1c_alias (1'b0), | |
153 | .omni_rw1s_alias (1'b0), | |
154 | // synopsys translate_on | |
155 | .rst (rst_l_active_high), | |
156 | .rst_val (reset_addr[1]), | |
157 | .csr_ld (w_ld), | |
158 | .csr_data (csrbus_wr_data[17]), | |
159 | .rw_alias (1'b1), | |
160 | .rw1c_alias (1'b0), | |
161 | .rw1s_alias (1'b0), | |
162 | .hw_ld (1'b0), | |
163 | .hw_data (1'b0), | |
164 | .cp (clk), | |
165 | .q (msi_32_addr_reg_csrbus_read_data[17]) | |
166 | ); | |
167 | ||
168 | // bit 18 | |
169 | csr_sw csr_sw_18 | |
170 | ( | |
171 | // synopsys translate_off | |
172 | .omni_ld (omni_ld), | |
173 | .omni_data (omni_data[18]), | |
174 | .omni_rw_alias (1'b1), | |
175 | .omni_rw1c_alias (1'b0), | |
176 | .omni_rw1s_alias (1'b0), | |
177 | // synopsys translate_on | |
178 | .rst (rst_l_active_high), | |
179 | .rst_val (reset_addr[2]), | |
180 | .csr_ld (w_ld), | |
181 | .csr_data (csrbus_wr_data[18]), | |
182 | .rw_alias (1'b1), | |
183 | .rw1c_alias (1'b0), | |
184 | .rw1s_alias (1'b0), | |
185 | .hw_ld (1'b0), | |
186 | .hw_data (1'b0), | |
187 | .cp (clk), | |
188 | .q (msi_32_addr_reg_csrbus_read_data[18]) | |
189 | ); | |
190 | ||
191 | // bit 19 | |
192 | csr_sw csr_sw_19 | |
193 | ( | |
194 | // synopsys translate_off | |
195 | .omni_ld (omni_ld), | |
196 | .omni_data (omni_data[19]), | |
197 | .omni_rw_alias (1'b1), | |
198 | .omni_rw1c_alias (1'b0), | |
199 | .omni_rw1s_alias (1'b0), | |
200 | // synopsys translate_on | |
201 | .rst (rst_l_active_high), | |
202 | .rst_val (reset_addr[3]), | |
203 | .csr_ld (w_ld), | |
204 | .csr_data (csrbus_wr_data[19]), | |
205 | .rw_alias (1'b1), | |
206 | .rw1c_alias (1'b0), | |
207 | .rw1s_alias (1'b0), | |
208 | .hw_ld (1'b0), | |
209 | .hw_data (1'b0), | |
210 | .cp (clk), | |
211 | .q (msi_32_addr_reg_csrbus_read_data[19]) | |
212 | ); | |
213 | ||
214 | // bit 20 | |
215 | csr_sw csr_sw_20 | |
216 | ( | |
217 | // synopsys translate_off | |
218 | .omni_ld (omni_ld), | |
219 | .omni_data (omni_data[20]), | |
220 | .omni_rw_alias (1'b1), | |
221 | .omni_rw1c_alias (1'b0), | |
222 | .omni_rw1s_alias (1'b0), | |
223 | // synopsys translate_on | |
224 | .rst (rst_l_active_high), | |
225 | .rst_val (reset_addr[4]), | |
226 | .csr_ld (w_ld), | |
227 | .csr_data (csrbus_wr_data[20]), | |
228 | .rw_alias (1'b1), | |
229 | .rw1c_alias (1'b0), | |
230 | .rw1s_alias (1'b0), | |
231 | .hw_ld (1'b0), | |
232 | .hw_data (1'b0), | |
233 | .cp (clk), | |
234 | .q (msi_32_addr_reg_csrbus_read_data[20]) | |
235 | ); | |
236 | ||
237 | // bit 21 | |
238 | csr_sw csr_sw_21 | |
239 | ( | |
240 | // synopsys translate_off | |
241 | .omni_ld (omni_ld), | |
242 | .omni_data (omni_data[21]), | |
243 | .omni_rw_alias (1'b1), | |
244 | .omni_rw1c_alias (1'b0), | |
245 | .omni_rw1s_alias (1'b0), | |
246 | // synopsys translate_on | |
247 | .rst (rst_l_active_high), | |
248 | .rst_val (reset_addr[5]), | |
249 | .csr_ld (w_ld), | |
250 | .csr_data (csrbus_wr_data[21]), | |
251 | .rw_alias (1'b1), | |
252 | .rw1c_alias (1'b0), | |
253 | .rw1s_alias (1'b0), | |
254 | .hw_ld (1'b0), | |
255 | .hw_data (1'b0), | |
256 | .cp (clk), | |
257 | .q (msi_32_addr_reg_csrbus_read_data[21]) | |
258 | ); | |
259 | ||
260 | // bit 22 | |
261 | csr_sw csr_sw_22 | |
262 | ( | |
263 | // synopsys translate_off | |
264 | .omni_ld (omni_ld), | |
265 | .omni_data (omni_data[22]), | |
266 | .omni_rw_alias (1'b1), | |
267 | .omni_rw1c_alias (1'b0), | |
268 | .omni_rw1s_alias (1'b0), | |
269 | // synopsys translate_on | |
270 | .rst (rst_l_active_high), | |
271 | .rst_val (reset_addr[6]), | |
272 | .csr_ld (w_ld), | |
273 | .csr_data (csrbus_wr_data[22]), | |
274 | .rw_alias (1'b1), | |
275 | .rw1c_alias (1'b0), | |
276 | .rw1s_alias (1'b0), | |
277 | .hw_ld (1'b0), | |
278 | .hw_data (1'b0), | |
279 | .cp (clk), | |
280 | .q (msi_32_addr_reg_csrbus_read_data[22]) | |
281 | ); | |
282 | ||
283 | // bit 23 | |
284 | csr_sw csr_sw_23 | |
285 | ( | |
286 | // synopsys translate_off | |
287 | .omni_ld (omni_ld), | |
288 | .omni_data (omni_data[23]), | |
289 | .omni_rw_alias (1'b1), | |
290 | .omni_rw1c_alias (1'b0), | |
291 | .omni_rw1s_alias (1'b0), | |
292 | // synopsys translate_on | |
293 | .rst (rst_l_active_high), | |
294 | .rst_val (reset_addr[7]), | |
295 | .csr_ld (w_ld), | |
296 | .csr_data (csrbus_wr_data[23]), | |
297 | .rw_alias (1'b1), | |
298 | .rw1c_alias (1'b0), | |
299 | .rw1s_alias (1'b0), | |
300 | .hw_ld (1'b0), | |
301 | .hw_data (1'b0), | |
302 | .cp (clk), | |
303 | .q (msi_32_addr_reg_csrbus_read_data[23]) | |
304 | ); | |
305 | ||
306 | // bit 24 | |
307 | csr_sw csr_sw_24 | |
308 | ( | |
309 | // synopsys translate_off | |
310 | .omni_ld (omni_ld), | |
311 | .omni_data (omni_data[24]), | |
312 | .omni_rw_alias (1'b1), | |
313 | .omni_rw1c_alias (1'b0), | |
314 | .omni_rw1s_alias (1'b0), | |
315 | // synopsys translate_on | |
316 | .rst (rst_l_active_high), | |
317 | .rst_val (reset_addr[8]), | |
318 | .csr_ld (w_ld), | |
319 | .csr_data (csrbus_wr_data[24]), | |
320 | .rw_alias (1'b1), | |
321 | .rw1c_alias (1'b0), | |
322 | .rw1s_alias (1'b0), | |
323 | .hw_ld (1'b0), | |
324 | .hw_data (1'b0), | |
325 | .cp (clk), | |
326 | .q (msi_32_addr_reg_csrbus_read_data[24]) | |
327 | ); | |
328 | ||
329 | // bit 25 | |
330 | csr_sw csr_sw_25 | |
331 | ( | |
332 | // synopsys translate_off | |
333 | .omni_ld (omni_ld), | |
334 | .omni_data (omni_data[25]), | |
335 | .omni_rw_alias (1'b1), | |
336 | .omni_rw1c_alias (1'b0), | |
337 | .omni_rw1s_alias (1'b0), | |
338 | // synopsys translate_on | |
339 | .rst (rst_l_active_high), | |
340 | .rst_val (reset_addr[9]), | |
341 | .csr_ld (w_ld), | |
342 | .csr_data (csrbus_wr_data[25]), | |
343 | .rw_alias (1'b1), | |
344 | .rw1c_alias (1'b0), | |
345 | .rw1s_alias (1'b0), | |
346 | .hw_ld (1'b0), | |
347 | .hw_data (1'b0), | |
348 | .cp (clk), | |
349 | .q (msi_32_addr_reg_csrbus_read_data[25]) | |
350 | ); | |
351 | ||
352 | // bit 26 | |
353 | csr_sw csr_sw_26 | |
354 | ( | |
355 | // synopsys translate_off | |
356 | .omni_ld (omni_ld), | |
357 | .omni_data (omni_data[26]), | |
358 | .omni_rw_alias (1'b1), | |
359 | .omni_rw1c_alias (1'b0), | |
360 | .omni_rw1s_alias (1'b0), | |
361 | // synopsys translate_on | |
362 | .rst (rst_l_active_high), | |
363 | .rst_val (reset_addr[10]), | |
364 | .csr_ld (w_ld), | |
365 | .csr_data (csrbus_wr_data[26]), | |
366 | .rw_alias (1'b1), | |
367 | .rw1c_alias (1'b0), | |
368 | .rw1s_alias (1'b0), | |
369 | .hw_ld (1'b0), | |
370 | .hw_data (1'b0), | |
371 | .cp (clk), | |
372 | .q (msi_32_addr_reg_csrbus_read_data[26]) | |
373 | ); | |
374 | ||
375 | // bit 27 | |
376 | csr_sw csr_sw_27 | |
377 | ( | |
378 | // synopsys translate_off | |
379 | .omni_ld (omni_ld), | |
380 | .omni_data (omni_data[27]), | |
381 | .omni_rw_alias (1'b1), | |
382 | .omni_rw1c_alias (1'b0), | |
383 | .omni_rw1s_alias (1'b0), | |
384 | // synopsys translate_on | |
385 | .rst (rst_l_active_high), | |
386 | .rst_val (reset_addr[11]), | |
387 | .csr_ld (w_ld), | |
388 | .csr_data (csrbus_wr_data[27]), | |
389 | .rw_alias (1'b1), | |
390 | .rw1c_alias (1'b0), | |
391 | .rw1s_alias (1'b0), | |
392 | .hw_ld (1'b0), | |
393 | .hw_data (1'b0), | |
394 | .cp (clk), | |
395 | .q (msi_32_addr_reg_csrbus_read_data[27]) | |
396 | ); | |
397 | ||
398 | // bit 28 | |
399 | csr_sw csr_sw_28 | |
400 | ( | |
401 | // synopsys translate_off | |
402 | .omni_ld (omni_ld), | |
403 | .omni_data (omni_data[28]), | |
404 | .omni_rw_alias (1'b1), | |
405 | .omni_rw1c_alias (1'b0), | |
406 | .omni_rw1s_alias (1'b0), | |
407 | // synopsys translate_on | |
408 | .rst (rst_l_active_high), | |
409 | .rst_val (reset_addr[12]), | |
410 | .csr_ld (w_ld), | |
411 | .csr_data (csrbus_wr_data[28]), | |
412 | .rw_alias (1'b1), | |
413 | .rw1c_alias (1'b0), | |
414 | .rw1s_alias (1'b0), | |
415 | .hw_ld (1'b0), | |
416 | .hw_data (1'b0), | |
417 | .cp (clk), | |
418 | .q (msi_32_addr_reg_csrbus_read_data[28]) | |
419 | ); | |
420 | ||
421 | // bit 29 | |
422 | csr_sw csr_sw_29 | |
423 | ( | |
424 | // synopsys translate_off | |
425 | .omni_ld (omni_ld), | |
426 | .omni_data (omni_data[29]), | |
427 | .omni_rw_alias (1'b1), | |
428 | .omni_rw1c_alias (1'b0), | |
429 | .omni_rw1s_alias (1'b0), | |
430 | // synopsys translate_on | |
431 | .rst (rst_l_active_high), | |
432 | .rst_val (reset_addr[13]), | |
433 | .csr_ld (w_ld), | |
434 | .csr_data (csrbus_wr_data[29]), | |
435 | .rw_alias (1'b1), | |
436 | .rw1c_alias (1'b0), | |
437 | .rw1s_alias (1'b0), | |
438 | .hw_ld (1'b0), | |
439 | .hw_data (1'b0), | |
440 | .cp (clk), | |
441 | .q (msi_32_addr_reg_csrbus_read_data[29]) | |
442 | ); | |
443 | ||
444 | // bit 30 | |
445 | csr_sw csr_sw_30 | |
446 | ( | |
447 | // synopsys translate_off | |
448 | .omni_ld (omni_ld), | |
449 | .omni_data (omni_data[30]), | |
450 | .omni_rw_alias (1'b1), | |
451 | .omni_rw1c_alias (1'b0), | |
452 | .omni_rw1s_alias (1'b0), | |
453 | // synopsys translate_on | |
454 | .rst (rst_l_active_high), | |
455 | .rst_val (reset_addr[14]), | |
456 | .csr_ld (w_ld), | |
457 | .csr_data (csrbus_wr_data[30]), | |
458 | .rw_alias (1'b1), | |
459 | .rw1c_alias (1'b0), | |
460 | .rw1s_alias (1'b0), | |
461 | .hw_ld (1'b0), | |
462 | .hw_data (1'b0), | |
463 | .cp (clk), | |
464 | .q (msi_32_addr_reg_csrbus_read_data[30]) | |
465 | ); | |
466 | ||
467 | // bit 31 | |
468 | csr_sw csr_sw_31 | |
469 | ( | |
470 | // synopsys translate_off | |
471 | .omni_ld (omni_ld), | |
472 | .omni_data (omni_data[31]), | |
473 | .omni_rw_alias (1'b1), | |
474 | .omni_rw1c_alias (1'b0), | |
475 | .omni_rw1s_alias (1'b0), | |
476 | // synopsys translate_on | |
477 | .rst (rst_l_active_high), | |
478 | .rst_val (reset_addr[15]), | |
479 | .csr_ld (w_ld), | |
480 | .csr_data (csrbus_wr_data[31]), | |
481 | .rw_alias (1'b1), | |
482 | .rw1c_alias (1'b0), | |
483 | .rw1s_alias (1'b0), | |
484 | .hw_ld (1'b0), | |
485 | .hw_data (1'b0), | |
486 | .cp (clk), | |
487 | .q (msi_32_addr_reg_csrbus_read_data[31]) | |
488 | ); | |
489 | ||
490 | assign msi_32_addr_reg_csrbus_read_data[32] = 1'b0; // bit 32 | |
491 | assign msi_32_addr_reg_csrbus_read_data[33] = 1'b0; // bit 33 | |
492 | assign msi_32_addr_reg_csrbus_read_data[34] = 1'b0; // bit 34 | |
493 | assign msi_32_addr_reg_csrbus_read_data[35] = 1'b0; // bit 35 | |
494 | assign msi_32_addr_reg_csrbus_read_data[36] = 1'b0; // bit 36 | |
495 | assign msi_32_addr_reg_csrbus_read_data[37] = 1'b0; // bit 37 | |
496 | assign msi_32_addr_reg_csrbus_read_data[38] = 1'b0; // bit 38 | |
497 | assign msi_32_addr_reg_csrbus_read_data[39] = 1'b0; // bit 39 | |
498 | assign msi_32_addr_reg_csrbus_read_data[40] = 1'b0; // bit 40 | |
499 | assign msi_32_addr_reg_csrbus_read_data[41] = 1'b0; // bit 41 | |
500 | assign msi_32_addr_reg_csrbus_read_data[42] = 1'b0; // bit 42 | |
501 | assign msi_32_addr_reg_csrbus_read_data[43] = 1'b0; // bit 43 | |
502 | assign msi_32_addr_reg_csrbus_read_data[44] = 1'b0; // bit 44 | |
503 | assign msi_32_addr_reg_csrbus_read_data[45] = 1'b0; // bit 45 | |
504 | assign msi_32_addr_reg_csrbus_read_data[46] = 1'b0; // bit 46 | |
505 | assign msi_32_addr_reg_csrbus_read_data[47] = 1'b0; // bit 47 | |
506 | assign msi_32_addr_reg_csrbus_read_data[48] = 1'b0; // bit 48 | |
507 | assign msi_32_addr_reg_csrbus_read_data[49] = 1'b0; // bit 49 | |
508 | assign msi_32_addr_reg_csrbus_read_data[50] = 1'b0; // bit 50 | |
509 | assign msi_32_addr_reg_csrbus_read_data[51] = 1'b0; // bit 51 | |
510 | assign msi_32_addr_reg_csrbus_read_data[52] = 1'b0; // bit 52 | |
511 | assign msi_32_addr_reg_csrbus_read_data[53] = 1'b0; // bit 53 | |
512 | assign msi_32_addr_reg_csrbus_read_data[54] = 1'b0; // bit 54 | |
513 | assign msi_32_addr_reg_csrbus_read_data[55] = 1'b0; // bit 55 | |
514 | assign msi_32_addr_reg_csrbus_read_data[56] = 1'b0; // bit 56 | |
515 | assign msi_32_addr_reg_csrbus_read_data[57] = 1'b0; // bit 57 | |
516 | assign msi_32_addr_reg_csrbus_read_data[58] = 1'b0; // bit 58 | |
517 | assign msi_32_addr_reg_csrbus_read_data[59] = 1'b0; // bit 59 | |
518 | assign msi_32_addr_reg_csrbus_read_data[60] = 1'b0; // bit 60 | |
519 | assign msi_32_addr_reg_csrbus_read_data[61] = 1'b0; // bit 61 | |
520 | assign msi_32_addr_reg_csrbus_read_data[62] = 1'b0; // bit 62 | |
521 | assign msi_32_addr_reg_csrbus_read_data[63] = 1'b0; // bit 63 | |
522 | ||
523 | endmodule // dmu_imu_ics_csr_msi_32_addr_reg_entry |