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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_imu_rds_intx_csr_int_a_int_clr_reg.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_imu_rds_intx_csr_int_a_int_clr_reg | |
36 | ( | |
37 | clk, | |
38 | rst_l, | |
39 | int_a_int_clr_reg_w_ld, | |
40 | csrbus_wr_data, | |
41 | int_a_int_clr_reg_csrbus_read_data, | |
42 | int_a_int_clr_reg_clr_hw_ld, | |
43 | int_a_int_clr_reg_clr_hw_write, | |
44 | int_a_int_clr_reg_clr_hw_read | |
45 | ); | |
46 | ||
47 | //==================================================================== | |
48 | // Polarity declarations | |
49 | //==================================================================== | |
50 | input clk; // Clock | |
51 | input rst_l; // Reset signal | |
52 | input int_a_int_clr_reg_w_ld; // SW load bus | |
53 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
54 | output [`FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_WIDTH-1:0] int_a_int_clr_reg_csrbus_read_data; | |
55 | // SW read data | |
56 | input int_a_int_clr_reg_clr_hw_ld; // Hardware load enable for | |
57 | // int_a_int_clr_reg_clr. When set, <hw | |
58 | // write signal> will be loaded into | |
59 | // int_a_int_clr_reg. | |
60 | input int_a_int_clr_reg_clr_hw_write; // data bus for hw loading of | |
61 | // int_a_int_clr_reg_clr. | |
62 | output int_a_int_clr_reg_clr_hw_read; // This signal provides the current value | |
63 | // of int_a_int_clr_reg_clr. | |
64 | ||
65 | //==================================================================== | |
66 | // Type declarations | |
67 | //==================================================================== | |
68 | wire clk; // Clock | |
69 | wire rst_l; // Reset signal | |
70 | wire int_a_int_clr_reg_w_ld; // SW load bus | |
71 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
72 | wire [`FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_WIDTH-1:0] int_a_int_clr_reg_csrbus_read_data; | |
73 | // SW read data | |
74 | wire int_a_int_clr_reg_clr_hw_ld; // Hardware load enable for | |
75 | // int_a_int_clr_reg_clr. When set, <hw write | |
76 | // signal> will be loaded into | |
77 | // int_a_int_clr_reg. | |
78 | wire int_a_int_clr_reg_clr_hw_write; // data bus for hw loading of | |
79 | // int_a_int_clr_reg_clr. | |
80 | wire int_a_int_clr_reg_clr_hw_read; // This signal provides the current value | |
81 | // of int_a_int_clr_reg_clr. | |
82 | ||
83 | //==================================================================== | |
84 | // Logic | |
85 | //==================================================================== | |
86 | ||
87 | // synopsys translate_off | |
88 | // verilint 123 off | |
89 | // verilint 498 off | |
90 | reg omni_ld; | |
91 | reg [`FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_WIDTH-1:0] omni_data; | |
92 | ||
93 | // vlint flag_unsynthesizable_initial off | |
94 | initial | |
95 | begin | |
96 | omni_ld = 1'b0; | |
97 | omni_data = `FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_WIDTH'b0; | |
98 | end// vlint flag_unsynthesizable_initial on | |
99 | ||
100 | // verilint 123 on | |
101 | // verilint 498 on | |
102 | // synopsys translate_on | |
103 | ||
104 | //----- Hardware Data Out Mux Assignments | |
105 | assign int_a_int_clr_reg_clr_hw_read= | |
106 | int_a_int_clr_reg_csrbus_read_data [0]; | |
107 | ||
108 | //==================================================================== | |
109 | // Instantiation of entries | |
110 | //==================================================================== | |
111 | ||
112 | //----- Entry 0 | |
113 | dmu_imu_rds_intx_csr_int_a_int_clr_reg_entry int_a_int_clr_reg_0 | |
114 | ( | |
115 | // synopsys translate_off | |
116 | .omni_ld (omni_ld), | |
117 | .omni_data (omni_data), | |
118 | // synopsys translate_on | |
119 | .clk (clk), | |
120 | .rst_l (rst_l), | |
121 | .w_ld (int_a_int_clr_reg_w_ld), | |
122 | .csrbus_wr_data (csrbus_wr_data), | |
123 | .int_a_int_clr_reg_csrbus_read_data (int_a_int_clr_reg_csrbus_read_data), | |
124 | .int_a_int_clr_reg_clr_hw_ld (int_a_int_clr_reg_clr_hw_ld), | |
125 | .int_a_int_clr_reg_clr_hw_write (int_a_int_clr_reg_clr_hw_write) | |
126 | ); | |
127 | ||
128 | endmodule // dmu_imu_rds_intx_csr_int_a_int_clr_reg |