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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_mmu_csr_stage_mux_only.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_mmu_csr_stage_mux_only | |
36 | ( | |
37 | clk, | |
38 | read_data_0, | |
39 | ext_done_0, | |
40 | ctl_select_pulse, | |
41 | ctl_select_pulse_out, | |
42 | tsb_select_pulse, | |
43 | tsb_select_pulse_out, | |
44 | fsh_select_pulse, | |
45 | fsh_select_pulse_out, | |
46 | inv_select, | |
47 | inv_select_out, | |
48 | log_select_pulse, | |
49 | log_select_pulse_out, | |
50 | int_en_select_pulse, | |
51 | int_en_select_pulse_out, | |
52 | en_err_select, | |
53 | en_err_select_out, | |
54 | err_select_pulse, | |
55 | err_select_pulse_out, | |
56 | flta_select_pulse, | |
57 | flta_select_pulse_out, | |
58 | flts_select_pulse, | |
59 | flts_select_pulse_out, | |
60 | prfc_select_pulse, | |
61 | prfc_select_pulse_out, | |
62 | prf0_select_pulse, | |
63 | prf0_select_pulse_out, | |
64 | prf1_select_pulse, | |
65 | prf1_select_pulse_out, | |
66 | vtb_select, | |
67 | vtb_select_out, | |
68 | ptb_select, | |
69 | ptb_select_out, | |
70 | tdb_select, | |
71 | tdb_select_out, | |
72 | dev2iotsb_select, | |
73 | dev2iotsb_select_out, | |
74 | IotsbDesc_select, | |
75 | IotsbDesc_select_out, | |
76 | err_rw1c_alias, | |
77 | err_rw1c_alias_out, | |
78 | err_rw1s_alias, | |
79 | err_rw1s_alias_out, | |
80 | daemon_csrbus_wr_in, | |
81 | daemon_csrbus_wr_out, | |
82 | daemon_csrbus_wr_data_in, | |
83 | daemon_csrbus_wr_data_out, | |
84 | ext_addr_in, | |
85 | ext_addr_out, | |
86 | read_data_0_out, | |
87 | ext_done_0_out, | |
88 | rst_l, | |
89 | rst_l_out, | |
90 | por_l, | |
91 | por_l_out | |
92 | ); | |
93 | ||
94 | //==================================================== | |
95 | // Polarity declarations | |
96 | //==================================================== | |
97 | input clk; // Clock signal | |
98 | input [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0; // Read Data | |
99 | input ext_done_0; // Ext Done | |
100 | input ctl_select_pulse; // select | |
101 | output ctl_select_pulse_out; // select | |
102 | input tsb_select_pulse; // select | |
103 | output tsb_select_pulse_out; // select | |
104 | input fsh_select_pulse; // select | |
105 | output fsh_select_pulse_out; // select | |
106 | input inv_select; // select | |
107 | output inv_select_out; // select | |
108 | input log_select_pulse; // select | |
109 | output log_select_pulse_out; // select | |
110 | input int_en_select_pulse; // select | |
111 | output int_en_select_pulse_out; // select | |
112 | input en_err_select; // select | |
113 | output en_err_select_out; // select | |
114 | input err_select_pulse; // select | |
115 | output err_select_pulse_out; // select | |
116 | input flta_select_pulse; // select | |
117 | output flta_select_pulse_out; // select | |
118 | input flts_select_pulse; // select | |
119 | output flts_select_pulse_out; // select | |
120 | input prfc_select_pulse; // select | |
121 | output prfc_select_pulse_out; // select | |
122 | input prf0_select_pulse; // select | |
123 | output prf0_select_pulse_out; // select | |
124 | input prf1_select_pulse; // select | |
125 | output prf1_select_pulse_out; // select | |
126 | input vtb_select; // select | |
127 | output vtb_select_out; // select | |
128 | input ptb_select; // select | |
129 | output ptb_select_out; // select | |
130 | input tdb_select; // select | |
131 | output tdb_select_out; // select | |
132 | input dev2iotsb_select; // select | |
133 | output dev2iotsb_select_out; // select | |
134 | input IotsbDesc_select; // select | |
135 | output IotsbDesc_select_out; // select | |
136 | input err_rw1c_alias; // SW load | |
137 | output err_rw1c_alias_out; // alias | |
138 | input err_rw1s_alias; // SW load | |
139 | output err_rw1s_alias_out; // alias | |
140 | input daemon_csrbus_wr_in; // csrbus_wr | |
141 | output daemon_csrbus_wr_out; // csrbus_wr | |
142 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in; // SW write data | |
143 | output [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // SW write | |
144 | // data | |
145 | input [8:0] ext_addr_in; // Ext addr | |
146 | output [8:0] ext_addr_out; // Ext addr | |
147 | output [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out; // Read Data | |
148 | output ext_done_0_out; // Ext Done | |
149 | input rst_l; // HW reset | |
150 | output rst_l_out; // HW reset | |
151 | input por_l; // HW reset | |
152 | output por_l_out; // HW reset | |
153 | ||
154 | //==================================================== | |
155 | // Type declarations | |
156 | //==================================================== | |
157 | wire clk; // Clock signal | |
158 | wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0; // Read Data | |
159 | wire ext_done_0; // Ext Done | |
160 | wire ctl_select_pulse; // select | |
161 | wire ctl_select_pulse_out; // select | |
162 | wire tsb_select_pulse; // select | |
163 | wire tsb_select_pulse_out; // select | |
164 | wire fsh_select_pulse; // select | |
165 | wire fsh_select_pulse_out; // select | |
166 | wire inv_select; // select | |
167 | wire inv_select_out; // select | |
168 | wire log_select_pulse; // select | |
169 | wire log_select_pulse_out; // select | |
170 | wire int_en_select_pulse; // select | |
171 | wire int_en_select_pulse_out; // select | |
172 | wire en_err_select; // select | |
173 | wire en_err_select_out; // select | |
174 | wire err_select_pulse; // select | |
175 | wire err_select_pulse_out; // select | |
176 | wire flta_select_pulse; // select | |
177 | wire flta_select_pulse_out; // select | |
178 | wire flts_select_pulse; // select | |
179 | wire flts_select_pulse_out; // select | |
180 | wire prfc_select_pulse; // select | |
181 | wire prfc_select_pulse_out; // select | |
182 | wire prf0_select_pulse; // select | |
183 | wire prf0_select_pulse_out; // select | |
184 | wire prf1_select_pulse; // select | |
185 | wire prf1_select_pulse_out; // select | |
186 | wire vtb_select; // select | |
187 | wire vtb_select_out; // select | |
188 | wire ptb_select; // select | |
189 | wire ptb_select_out; // select | |
190 | wire tdb_select; // select | |
191 | wire tdb_select_out; // select | |
192 | wire dev2iotsb_select; // select | |
193 | wire dev2iotsb_select_out; // select | |
194 | wire IotsbDesc_select; // select | |
195 | wire IotsbDesc_select_out; // select | |
196 | wire err_rw1c_alias; // SW load | |
197 | wire err_rw1c_alias_out; // alias | |
198 | wire err_rw1s_alias; // SW load | |
199 | wire err_rw1s_alias_out; // alias | |
200 | wire daemon_csrbus_wr_in; // csrbus_wr | |
201 | wire daemon_csrbus_wr_out; // csrbus_wr | |
202 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in; // SW write data | |
203 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // SW write data | |
204 | wire [8:0] ext_addr_in; // Ext addr | |
205 | wire [8:0] ext_addr_out; // Ext addr | |
206 | wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out; // Read Data | |
207 | wire ext_done_0_out; // Ext Done | |
208 | wire rst_l; // HW reset | |
209 | wire rst_l_out; // HW reset | |
210 | wire por_l; // HW reset | |
211 | wire por_l_out; // HW reset | |
212 | ||
213 | ||
214 | //==================================================== | |
215 | // Assignments only | |
216 | //==================================================== | |
217 | assign ext_done_0_out = | |
218 | ext_done_0; | |
219 | assign ctl_select_pulse_out = ctl_select_pulse; | |
220 | assign tsb_select_pulse_out = tsb_select_pulse; | |
221 | assign fsh_select_pulse_out = fsh_select_pulse; | |
222 | assign inv_select_out = inv_select; | |
223 | assign log_select_pulse_out = log_select_pulse; | |
224 | assign int_en_select_pulse_out = int_en_select_pulse; | |
225 | assign en_err_select_out = en_err_select; | |
226 | assign err_select_pulse_out = err_select_pulse; | |
227 | assign flta_select_pulse_out = flta_select_pulse; | |
228 | assign flts_select_pulse_out = flts_select_pulse; | |
229 | assign prfc_select_pulse_out = prfc_select_pulse; | |
230 | assign prf0_select_pulse_out = prf0_select_pulse; | |
231 | assign prf1_select_pulse_out = prf1_select_pulse; | |
232 | assign vtb_select_out = vtb_select; | |
233 | assign ptb_select_out = ptb_select; | |
234 | assign tdb_select_out = tdb_select; | |
235 | assign dev2iotsb_select_out = dev2iotsb_select; | |
236 | assign IotsbDesc_select_out = IotsbDesc_select; | |
237 | assign err_rw1c_alias_out = err_rw1c_alias; | |
238 | assign err_rw1s_alias_out = err_rw1s_alias; | |
239 | assign rst_l_out = rst_l; | |
240 | assign por_l_out = por_l; | |
241 | assign daemon_csrbus_wr_out = daemon_csrbus_wr_in; | |
242 | assign daemon_csrbus_wr_data_out = daemon_csrbus_wr_data_in; | |
243 | assign ext_addr_out = ext_addr_in; | |
244 | ||
245 | ||
246 | //===================================================== | |
247 | // OUTPUT: read_data_out | |
248 | //===================================================== | |
249 | dmu_mmu_csr_csrpipe_1 dmu_mmu_csr_csrpipe_1_inst_1 | |
250 | ( | |
251 | .clk (clk), | |
252 | .rst_l (rst_l), | |
253 | .reg_in (1'b0), | |
254 | .reg_out (1'b0), | |
255 | .data0 (read_data_0), | |
256 | .sel0 (1'b1), | |
257 | .out (read_data_0_out) | |
258 | ); | |
259 | ||
260 | endmodule // dmu_mmu_csr_stage_mux_only |