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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_tsb.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_tsb | |
36 | ( | |
37 | // Control Signals | |
38 | clk, | |
39 | rst_l, | |
40 | ||
41 | // RMU SRM interface | |
42 | rm2ts_i_req, | |
43 | rm2ts_i_cmd_type, | |
44 | rm2ts_i_wr_data, | |
45 | ||
46 | ts2rm_i_full, | |
47 | ts2rm_i_gnt, | |
48 | ts2rm_i_n_trn, | |
49 | ||
50 | //RMU RRM interface | |
51 | rm2ts_e_req, | |
52 | rm2ts_e_cmd_type, | |
53 | rm2ts_e_trn, | |
54 | rm2ts_e_wr_data, | |
55 | ||
56 | ts2rm_e_gnt, | |
57 | ts2rm_e_rd_data, | |
58 | ||
59 | // CSR interface | |
60 | cr2ts_csrbus_valid, | |
61 | cr2ts_csrbus_src_bus, | |
62 | cr2ts_csrbus_addr, | |
63 | cr2ts_csrbus_wr, | |
64 | cr2ts_csrbus_wr_data, | |
65 | ||
66 | ts2cr_csrbus_mapped, | |
67 | ts2cr_csrbus_read_data, | |
68 | ts2cr_csrbus_done, | |
69 | ts2cr_csrbus_acc_vio, | |
70 | j2d_instance_id, | |
71 | ||
72 | // Debug Ports | |
73 | cr2ts_dbg_sel_a, | |
74 | cr2ts_dbg_sel_b, | |
75 | ||
76 | ts2cr_dbg_a, | |
77 | ts2cr_dbg_b | |
78 | ); | |
79 | ||
80 | // synopsys sync_set_reset "rst_l" | |
81 | ||
82 | ////////////////////////////////////////////////////////////////////// | |
83 | //************************* Port Declarations ******************* | |
84 | ////////////////////////////////////////////////////////////////////// | |
85 | ||
86 | // Control signals | |
87 | input clk; | |
88 | input rst_l; | |
89 | ||
90 | // Debug Ports | |
91 | input [5:0] cr2ts_dbg_sel_a; | |
92 | input [5:0] cr2ts_dbg_sel_b; | |
93 | ||
94 | output [`FIRE_DBG_DATA_BITS] ts2cr_dbg_a; | |
95 | output [`FIRE_DBG_DATA_BITS] ts2cr_dbg_b; | |
96 | ||
97 | // RMU's SRM Interface Signals | |
98 | input rm2ts_i_req; // SRM request for access | |
99 | input [`FIRE_DLC_TSR_CMD_TYPE_WDTH-1:0] rm2ts_i_cmd_type; // type of access requested (trn req w/write) | |
100 | input [`FIRE_DLC_TSR_WR_DATA_WDTH-1:0] rm2ts_i_wr_data; // wr data to be put on scbd | |
101 | ||
102 | output ts2rm_i_full; // flow control, no request for trtag can be made | |
103 | output [`FIRE_DLC_TSR_TRN_WDTH-1:0] ts2rm_i_n_trn; // next trtag returned on trn request | |
104 | output ts2rm_i_gnt; // grant signal for request | |
105 | ||
106 | // /RMU's RRM Interface Signals | |
107 | input rm2ts_e_req; // RRM request for access | |
108 | input [`FIRE_DLC_TSR_CMD_TYPE_WDTH-1:0] rm2ts_e_cmd_type; // type of access requested (read, write, read w/clear) | |
109 | input [`FIRE_DLC_TSR_TRN_WDTH-1:0] rm2ts_e_trn; // trtag to be cleared, read from or written to | |
110 | input [`FIRE_DLC_TSR_WR_DATA_WDTH-1:0] rm2ts_e_wr_data; // wr data to be put on scbd | |
111 | ||
112 | output ts2rm_e_gnt; // grant signal for request | |
113 | output [`FIRE_DLC_TSR_RD_DATA_WDTH-1:0] ts2rm_e_rd_data; // data read from scbd (trtag is address read from) | |
114 | ||
115 | // CRU's DCC PIO Interface Signals | |
116 | input [`FIRE_CSR_SRC_BUS_ID_WIDTH-1:0] cr2ts_csrbus_src_bus; | |
117 | input cr2ts_csrbus_valid; | |
118 | input [`FIRE_CSR_ADDR_MAX_WIDTH-1:0] cr2ts_csrbus_addr; | |
119 | input cr2ts_csrbus_wr; | |
120 | input [`FIRE_CSR_DATA_WIDTH-1:0] cr2ts_csrbus_wr_data; | |
121 | input [`FIRE_J2D_INSTANCE_ID_WDTH-1:0] j2d_instance_id; | |
122 | ||
123 | output [`FIRE_CSR_DATA_WIDTH-1:0] ts2cr_csrbus_read_data; | |
124 | output ts2cr_csrbus_done; | |
125 | output ts2cr_csrbus_mapped; | |
126 | output ts2cr_csrbus_acc_vio; | |
127 | ||
128 | ////////////////////////////////////////////////////////////////////// | |
129 | //************************* Wires ******************************* | |
130 | ////////////////////////////////////////////////////////////////////// | |
131 | ||
132 | // TIC-TTG Interface | |
133 | wire tic2ttg_deq; // dequeue next trtag | |
134 | wire ttg2tic_trtag_full; // flow control from TTG to controller, no more trtags | |
135 | wire [`FIRE_DLC_TSR_TRN_WDTH-1:0] ttg2tic_n_trtag; // trtag returned to controller on deq | |
136 | ||
137 | // TEC-TTG Interface | |
138 | wire [`FIRE_DLC_TSR_TRN_WDTH-1:0] tec2ttg_trtag; // trtag retired on enq | |
139 | wire tec2ttg_enq; // enqueue trtag (clear/retire) | |
140 | ||
141 | // TIC-TDL Interface for DMA data write | |
142 | wire tic2tdl_req; // TIC req to TDL | |
143 | wire tic2tdl_dma_wr; // write enable | |
144 | wire [`FIRE_DLC_TSR_TRN_WDTH-1:0] tic2tdl_trtag; // tic-tdl wr address decode select | |
145 | wire [`FIRE_DLC_TSR_WR_DATA_WDTH-1:0] tic2tdl_wr_data; // dma data to wr to scbd | |
146 | ||
147 | // Read data select | |
148 | wire [`FIRE_DLC_TSR_TRN_WDTH-1:0] tec2tdl_trtag; // tec-tdl rd/wr address decode select | |
149 | ||
150 | // DMA Read data out to TEC | |
151 | wire [`FIRE_DLC_TSR_RD_DATA_WDTH-1:0] tdl2tec_rd_data; // dma read date from scbd | |
152 | ||
153 | // TEC-TDL Interface for DMA data write | |
154 | wire tec2tdl_req; // TEC req to TDL | |
155 | wire tec2tdl_dma_wr; // write enable | |
156 | wire [`FIRE_DLC_TSR_WR_DATA_WDTH-1:0] tec2tdl_wr_data; // dma data to wr to scbd | |
157 | ||
158 | // CSR Interface | |
159 | wire [`FIRE_DLC_TSR_TRN_WDTH-1:0] ext_addr; // External address bus for dcm dlc_tsb | |
160 | wire tsb_dma_ext_done; // acknowledges rd and wr operations for tsb_dma. | |
161 | wire tsb_dma_ext_select; // When set, register tsb_dma is selected. | |
162 | wire [`FIRE_DLC_TSR_RD_DATA_WDTH-1:0] tsb_dma_ext_rd_data; // Read data from the external bypass dma register | |
163 | ||
164 | wire tsb_sts_ext_select; | |
165 | wire tsb_sts_ext_done; | |
166 | wire tsb_sts_full_ext_read_data; | |
167 | wire [5:0] tsb_sts_num_pnd_dma_ext_read_data; | |
168 | wire tsb_sts_empty_ext_read_data; | |
169 | ||
170 | // Debug Port Interface | |
171 | ||
172 | // TSB | |
173 | wire [5:0] cr2ts_dbg_sel_a; // TSB debug select a | |
174 | wire [5:0] cr2ts_dbg_sel_b; // TSB debug select b | |
175 | ||
176 | wire [`FIRE_DBG_DATA_BITS] ts2cr_dbg_a; // TSB debug output a | |
177 | wire [`FIRE_DBG_DATA_BITS] ts2cr_dbg_b; // TSB debug output b | |
178 | ||
179 | // TTG | |
180 | wire [2:0] dbg2ttg_dbg_sel_a; // TTG debug select a | |
181 | wire [2:0] dbg2ttg_dbg_sel_b; // TTG debug select b | |
182 | ||
183 | wire [`FIRE_DBG_DATA_BITS] ttg2dbg_dbg_a; // TTG debug output a | |
184 | wire [`FIRE_DBG_DATA_BITS] ttg2dbg_dbg_b; // TTG debug output b | |
185 | ||
186 | // TDL | |
187 | wire [2:0] dbg2tdl_dbg_sel_a; // TDL debug select a | |
188 | wire [2:0] dbg2tdl_dbg_sel_b; // TDL debug select b | |
189 | ||
190 | wire [`FIRE_DBG_DATA_BITS] tdl2dbg_dbg_a; // TDL debug output a | |
191 | wire [`FIRE_DBG_DATA_BITS] tdl2dbg_dbg_b; // TDL debug output b | |
192 | ||
193 | // TIC | |
194 | wire [2:0] dbg2tic_dbg_sel_a; // TIC debug select a | |
195 | wire [2:0] dbg2tic_dbg_sel_b; // TIC debug select b | |
196 | ||
197 | wire [`FIRE_DBG_DATA_BITS] tic2dbg_dbg_a; // TIC debug output a | |
198 | wire [`FIRE_DBG_DATA_BITS] tic2dbg_dbg_b; // TIC debug output b | |
199 | ||
200 | // TEC | |
201 | wire [2:0] dbg2tec_dbg_sel_a; // TEC debug select a | |
202 | wire [2:0] dbg2tec_dbg_sel_b; // TEC debug select b | |
203 | ||
204 | wire [`FIRE_DBG_DATA_BITS] tec2dbg_dbg_a; // TEC debug output a | |
205 | wire [`FIRE_DBG_DATA_BITS] tec2dbg_dbg_b; // TEC debug output b | |
206 | ||
207 | ////////////////////////////////////////////////////////////////////// | |
208 | //*************** Zero in Checkers*********************** | |
209 | ////////////////////////////////////////////////////////////////////// | |
210 | ||
211 | // 0in req_ack -req rm2ts_i_req -ack ts2rm_i_gnt -req_until_ack -new_req_after_ack | |
212 | // 0in req_ack -req rm2ts_e_req -ack ts2rm_e_gnt -req_until_ack -new_req_after_ack | |
213 | ||
214 | // 0in known_driven -var rm2ts_i_req | |
215 | // 0in known_driven -var rm2ts_i_cmd_type -active rm2ts_i_req | |
216 | // 0in known_driven -var rm2ts_i_wr_data -active rm2ts_i_req | |
217 | // 0in known_driven -var ts2rm_i_full | |
218 | // 0in known_driven -var ts2rm_i_gnt | |
219 | // 0in known_driven -var ts2rm_i_n_trn -active ts2rm_i_gnt | |
220 | ||
221 | // 0in known_driven -var rm2ts_e_req | |
222 | // 0in known_driven -var rm2ts_e_cmd_type -active rm2ts_e_req | |
223 | // 0in known_driven -var rm2ts_e_trn -active rm2ts_e_req | |
224 | // 0in known_driven -var rm2ts_e_wr_data -active rm2ts_e_req | |
225 | // 0in known_driven -var ts2rm_e_gnt | |
226 | // 0in known_driven -var ts2rm_e_rd_data -active ts2rm_e_gnt | |
227 | ||
228 | /* 0in multi_port_memory_access | |
229 | -read (rm2ts_e_req & ((rm2ts_e_cmd_type == 4'b0001) | (rm2ts_e_cmd_type == 4'b0011)) & ts2rm_e_gnt) | |
230 | -write (rm2ts_e_req & ((rm2ts_e_cmd_type == 4'b0100) | (rm2ts_e_cmd_type == 4'b0101)) & ts2rm_e_gnt) (rm2ts_i_req & ((rm2ts_i_cmd_type == 4'b0100) | (rm2ts_i_cmd_type == 4'b0101)) & ts2rm_i_gnt) | |
231 | -read_addr rm2ts_e_trn | |
232 | -write_addr rm2ts_e_trn ts2rm_i_n_trn | |
233 | -initialized | |
234 | -single_write | |
235 | -single_read | |
236 | -read_data ts2rm_e_rd_data | |
237 | -write_data rm2ts_e_wr_data rm2ts_i_wr_data | |
238 | */ | |
239 | ||
240 | ////////////////////////////////////////////////////////////////////// | |
241 | //*************** Submodule Instantiations *********************** | |
242 | ////////////////////////////////////////////////////////////////////// | |
243 | ||
244 | //************************************************************* | |
245 | // TTG (Transaction Tag Generator) | |
246 | //************************************************************* | |
247 | ||
248 | dmu_tsb_ttg ttg | |
249 | ( | |
250 | // Control Signals | |
251 | .clk (clk), | |
252 | .rst_l (rst_l), | |
253 | ||
254 | // TIC-TTG INTERFACE | |
255 | // TIC-TTG Interface (Internal Input from TIC to TTG) | |
256 | .tag_deq (tic2ttg_deq), // dequeue next trtag | |
257 | ||
258 | // TTG-TIC Interface (Internal Output to TIC) | |
259 | .no_tag_avail (ttg2tic_trtag_full), // no transaction tags available for issue | |
260 | .tag_issue (ttg2tic_n_trtag), // next trtag to issue | |
261 | ||
262 | // TEC-TTG Interface (Internal Input from TEC to TTG) | |
263 | .tag_enq (tec2ttg_enq), // enqueue trtag (Clear / Retire) | |
264 | .tag_retire (tec2ttg_trtag), // transaction tag to retire from tec controller | |
265 | ||
266 | // CSR i/f for STATUS reg | |
267 | .tsb_sts_ext_select (tsb_sts_ext_select), | |
268 | .tsb_sts_full_ext_read_data (tsb_sts_full_ext_read_data), | |
269 | .tsb_sts_num_pnd_dma_ext_read_data (tsb_sts_num_pnd_dma_ext_read_data), | |
270 | .tsb_sts_empty_ext_read_data (tsb_sts_empty_ext_read_data), | |
271 | .tsb_sts_ext_done (tsb_sts_ext_done), | |
272 | ||
273 | // Debug Ports | |
274 | .ttg2dbg_dbg_a (ttg2dbg_dbg_a), | |
275 | .ttg2dbg_dbg_b (ttg2dbg_dbg_b), | |
276 | .dbg2ttg_dbg_sel_a (dbg2ttg_dbg_sel_a), | |
277 | .dbg2ttg_dbg_sel_b (dbg2ttg_dbg_sel_b) | |
278 | ); | |
279 | ||
280 | //************************************************************* | |
281 | // TIC (Transaction Ingress Scoreboard Controller) | |
282 | //************************************************************* | |
283 | ||
284 | // passing in CMD_TYPE_WIDTH, TAG_WIDTH, WR_DATA_WIDTH and RD_DATA_WIDTH | |
285 | dmu_common_scoreboard_controller #(4,5,48,48) tic | |
286 | ( | |
287 | // Control Signals | |
288 | .clk (clk), | |
289 | .rst_l (rst_l), | |
290 | ||
291 | // SRM INTERFACE (SRM Command Type is TRN request w/ write) | |
292 | // RMU's SRM-TIC Interface (External Input from SRM to TIC) | |
293 | .req_in (rm2ts_i_req), // request for access | |
294 | .cmd_type_in (rm2ts_i_cmd_type), // type of action requested (TRN request w/ write) | |
295 | .trn_in (5'b0), | |
296 | .wr_data_in (rm2ts_i_wr_data), // DMA data to be written to the scoreboard | |
297 | ||
298 | // TIC-RMU's SRM (External Output to SRM) | |
299 | .full_out (ts2rm_i_full), // no trtags available so no request can be made | |
300 | .n_trn_out (ts2rm_i_n_trn), // next trtag issued to SRM | |
301 | .rd_data_out (), | |
302 | .grant_out (ts2rm_i_gnt), // grant for srm's request | |
303 | ||
304 | // TDL-TIC INTERFACE | |
305 | // TDL-TIC (Internal Input from TDL to TIC) | |
306 | .rd_data_in (48'b0), | |
307 | ||
308 | // TIC-TDL (Internal Output to TDL) | |
309 | .wr1_out (tic2tdl_dma_wr), // DMA write enable to TDL | |
310 | .wr2_out (), | |
311 | .trn1_out (tic2tdl_trtag), // trtag is address to read from and write to scoreboard | |
312 | .type_out (), | |
313 | .wr_data_out (tic2tdl_wr_data), // DMA data written to TDL | |
314 | .req_out (tic2tdl_req), // TIC req to TDL | |
315 | ||
316 | // TTG INTERFACE | |
317 | // TTG-TIC (Internal Input from TTG to TIC) | |
318 | .full_in (ttg2tic_trtag_full), // full signal from ttg (no trans. tags available for issue) | |
319 | .n_trn_in (ttg2tic_n_trtag), // next trtag to issue | |
320 | ||
321 | // TIC-TTG (Internal Output to TTG) | |
322 | .deq_out (tic2ttg_deq), // dequeue next trtag for trn request | |
323 | .trn2_out (), | |
324 | .enq_out (), | |
325 | ||
326 | // debug Ports | |
327 | .dbg_a (tic2dbg_dbg_a), // TIC debug output a | |
328 | .dbg_b (tic2dbg_dbg_b), // TIC debug output b | |
329 | .dbg_sel_a (dbg2tic_dbg_sel_a), // TIC debug select a | |
330 | .dbg_sel_b (dbg2tic_dbg_sel_b) // TIC debug select b | |
331 | ||
332 | ); | |
333 | ||
334 | ||
335 | //************************************************************* | |
336 | // TEC (Transaction Egress Scoreboard Controller) | |
337 | //************************************************************* | |
338 | ||
339 | // passing in CMD_TYPE_WIDTH, TAG_WIDTH, WR_DATA_WIDTH and RD_DATA_WIDTH | |
340 | dmu_common_scoreboard_controller #(4,5,48,48) tec | |
341 | ( | |
342 | // Control Signals | |
343 | .clk (clk), | |
344 | .rst_l (rst_l), | |
345 | ||
346 | // RRM INTERFACE (RRM command type includes Read, Write and Read w/ Clear) | |
347 | // RMU's RRM-TEC Interface (External Input from RRM to TEC) | |
348 | .req_in (rm2ts_e_req), // request for access | |
349 | .cmd_type_in (rm2ts_e_cmd_type), // type of action requested (Read, Write and Read w/ Clear) | |
350 | .trn_in (rm2ts_e_trn), // trtag (for Read and Read w/ Clear) | |
351 | .wr_data_in (rm2ts_e_wr_data), // DMA data to be written to the scoreboard | |
352 | ||
353 | // TEC-RMU's RRM Interface (External Output to RRM) | |
354 | .full_out (), | |
355 | .n_trn_out (), | |
356 | .rd_data_out (ts2rm_e_rd_data), // DMA data to be read from the scoreboard | |
357 | .grant_out (ts2rm_e_gnt), // grant for rrm's request | |
358 | ||
359 | // TDL-TEC INTERFACE | |
360 | // TDL-TEC (Internal Input from TDL to TEC) | |
361 | .rd_data_in (tdl2tec_rd_data), // DMA data read from TDL | |
362 | ||
363 | // TEC-TDL (Internal Output to TDL) | |
364 | .wr1_out (tec2tdl_dma_wr), // DMA write enable to TDL | |
365 | .wr2_out (), | |
366 | .trn1_out (tec2tdl_trtag), // trtag is address to read from and write to scoreboard | |
367 | .type_out (), | |
368 | .wr_data_out (tec2tdl_wr_data), // DMA data written to TDL | |
369 | .req_out (tec2tdl_req), // TEC req to TDL | |
370 | ||
371 | // TTG INTERFACE | |
372 | // TTG-TEC (Internal Input from TTG to TEC) | |
373 | .full_in (1'b0), | |
374 | .n_trn_in (5'b0), | |
375 | ||
376 | // TEC-TTG (Internal Output to TTG) | |
377 | .deq_out (), | |
378 | .trn2_out (tec2ttg_trtag), // trtag to retire (Clear) | |
379 | .enq_out (tec2ttg_enq), // enqueue to retire trtag | |
380 | ||
381 | // debug Ports | |
382 | .dbg_a (tec2dbg_dbg_a), // TEC debug output a | |
383 | .dbg_b (tec2dbg_dbg_b), // TEC debug output b | |
384 | .dbg_sel_a (dbg2tec_dbg_sel_a), // TEC debug select a | |
385 | .dbg_sel_b (dbg2tec_dbg_sel_b) // TEC debug select b | |
386 | ||
387 | ); | |
388 | ||
389 | //************************************************************* | |
390 | // TDL (TSB DECODE LOGIC and Register Storage array for Scoreboard) | |
391 | //************************************************************* | |
392 | ||
393 | dmu_tsb_tdl tdl | |
394 | ( | |
395 | // control signals | |
396 | .clk (clk), | |
397 | .rst_l (rst_l), | |
398 | ||
399 | // TIC-TDL Interface (Internal Input from TEC to TDL) | |
400 | .tic2tdl_wr_in (tic2tdl_dma_wr), | |
401 | .tic2tdl_trtag_in (tic2tdl_trtag), | |
402 | .tic2tdl_wr_data_in (tic2tdl_wr_data), | |
403 | .tic2tdl_req_in (tic2tdl_req), | |
404 | ||
405 | // TEC-TDL Interface (Internal Input from TIC to TDL) | |
406 | .tec2tdl_wr_in (tec2tdl_dma_wr), | |
407 | .tec2tdl_trtag_in (tec2tdl_trtag), | |
408 | .tec2tdl_wr_data_in (tec2tdl_wr_data), | |
409 | .tec2tdl_req_in (tec2tdl_req), | |
410 | ||
411 | // TDL-TEC Interface (Output to TEC) | |
412 | .tdl2tec_rd_data_out (tdl2tec_rd_data), | |
413 | ||
414 | // CSR interface | |
415 | .ext_addr (ext_addr), | |
416 | .tsb_dma_ext_done (tsb_dma_ext_done), | |
417 | .tsb_dma_ext_select (tsb_dma_ext_select), | |
418 | .tsb_dma_ext_rd_data (tsb_dma_ext_rd_data), | |
419 | ||
420 | // Debug Ports | |
421 | .tdl2dbg_dbg_a (tdl2dbg_dbg_a), | |
422 | .tdl2dbg_dbg_b (tdl2dbg_dbg_b), | |
423 | .dbg2tdl_dbg_sel_a (dbg2tdl_dbg_sel_a), | |
424 | .dbg2tdl_dbg_sel_b (dbg2tdl_dbg_sel_b) | |
425 | ); | |
426 | ||
427 | ||
428 | //************************************************************* | |
429 | // TSB CSR Transaction Scoreboard CSR's | |
430 | //************************************************************* | |
431 | ||
432 | dmu_tsb_csr csr | |
433 | ( | |
434 | .clk (clk), | |
435 | .rst_l (rst_l), | |
436 | .csrbus_valid (cr2ts_csrbus_valid), | |
437 | .csrbus_done (ts2cr_csrbus_done), | |
438 | .csrbus_mapped (ts2cr_csrbus_mapped), | |
439 | .csrbus_wr_data (cr2ts_csrbus_wr_data), | |
440 | .csrbus_wr (cr2ts_csrbus_wr), | |
441 | .csrbus_read_data (ts2cr_csrbus_read_data), | |
442 | .csrbus_addr (cr2ts_csrbus_addr), | |
443 | .csrbus_src_bus (cr2ts_csrbus_src_bus), | |
444 | .csrbus_acc_vio (ts2cr_csrbus_acc_vio), | |
445 | .instance_id (j2d_instance_id), | |
446 | .ext_addr (ext_addr), | |
447 | .tsb_dma_ext_done (tsb_dma_ext_done), | |
448 | .tsb_dma_ext_select (tsb_dma_ext_select), | |
449 | .tsb_dma_entry_ext_read_data (tsb_dma_ext_rd_data), | |
450 | .tsb_sts_ext_select (tsb_sts_ext_select), | |
451 | .tsb_sts_full_ext_read_data (tsb_sts_full_ext_read_data), | |
452 | .tsb_sts_num_pnd_dma_ext_read_data (tsb_sts_num_pnd_dma_ext_read_data), | |
453 | .tsb_sts_empty_ext_read_data (tsb_sts_empty_ext_read_data), | |
454 | .tsb_sts_ext_done (tsb_sts_ext_done) | |
455 | ||
456 | ); | |
457 | ||
458 | //************************************************************* | |
459 | // TSB Debug Module | |
460 | //************************************************************* | |
461 | dmu_tsb_dbg dbg | |
462 | ( | |
463 | .clk (clk), | |
464 | .rst_l (rst_l), | |
465 | ||
466 | // TSB | |
467 | .cr2ts_dbg_sel_a (cr2ts_dbg_sel_a), // TSB debug select a | |
468 | .cr2ts_dbg_sel_b (cr2ts_dbg_sel_b), // TSB debug select b | |
469 | ||
470 | .ts2cr_dbg_a (ts2cr_dbg_a), // TSB debug output a | |
471 | .ts2cr_dbg_b (ts2cr_dbg_b), // TSB debug output b | |
472 | ||
473 | // TTG | |
474 | .dbg2ttg_dbg_sel_a (dbg2ttg_dbg_sel_a), // TTG debug select a | |
475 | .dbg2ttg_dbg_sel_b (dbg2ttg_dbg_sel_b), // TTG debug select b | |
476 | ||
477 | .ttg2dbg_dbg_a (ttg2dbg_dbg_a), // TTG debug output a | |
478 | .ttg2dbg_dbg_b (ttg2dbg_dbg_b), // TTG debug output b | |
479 | ||
480 | // PDL | |
481 | .dbg2tdl_dbg_sel_a (dbg2tdl_dbg_sel_a), // TDL debug select a | |
482 | .dbg2tdl_dbg_sel_b (dbg2tdl_dbg_sel_b), // TDL debug select b | |
483 | ||
484 | .tdl2dbg_dbg_a (tdl2dbg_dbg_a), // TDL debug output a | |
485 | .tdl2dbg_dbg_b (tdl2dbg_dbg_b), // TDL debug output b | |
486 | ||
487 | // PIC | |
488 | .dbg2tic_dbg_sel_a (dbg2tic_dbg_sel_a), // TIC debug select a | |
489 | .dbg2tic_dbg_sel_b (dbg2tic_dbg_sel_b), // TIC debug select b | |
490 | ||
491 | .tic2dbg_dbg_a (tic2dbg_dbg_a), // TIC debug output a | |
492 | .tic2dbg_dbg_b (tic2dbg_dbg_b), // TIC debug output b | |
493 | ||
494 | // PCE | |
495 | .dbg2tec_dbg_sel_a (dbg2tec_dbg_sel_a), // TEC debug select a | |
496 | .dbg2tec_dbg_sel_b (dbg2tec_dbg_sel_b), // TEC debug select b | |
497 | ||
498 | .tec2dbg_dbg_a (tec2dbg_dbg_a), // TEC debug output a | |
499 | .tec2dbg_dbg_b (tec2dbg_dbg_b) // TEC debug output b | |
500 | ); | |
501 | ||
502 | endmodule // dmu_tsb |