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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: mcu_readdp_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module mcu_readdp_dp ( | |
36 | drl2clk, | |
37 | scan_in, | |
38 | scan_out, | |
39 | tcu_pce_ov, | |
40 | tcu_aclk, | |
41 | tcu_bclk, | |
42 | tcu_scan_en, | |
43 | rddata_en, | |
44 | radr_parity, | |
45 | inj_ecc_err, | |
46 | io_mcu_ecc_in, | |
47 | io_mcu_data_in, | |
48 | fail_over_mode, | |
49 | fail_over_mask, | |
50 | fail_over_mask_l, | |
51 | fbdic_rddata_vld, | |
52 | dr_secc_err, | |
53 | dr_mecc_err, | |
54 | rddata, | |
55 | ecc_loc, | |
56 | cor_rddata, | |
57 | syndrome, | |
58 | mcu_gnd); | |
59 | wire pce_ov; | |
60 | wire stop; | |
61 | wire siclk; | |
62 | wire soclk; | |
63 | wire se; | |
64 | wire fbdic_rddata_vld_buf; | |
65 | wire [15:0] io_mcu_ecc; | |
66 | wire [127:0] io_mcu_data; | |
67 | wire [15:0] mux_rdecc_in; | |
68 | wire [127:0] mux_rddata_in; | |
69 | wire u_rddata_in_127_64_scanin; | |
70 | wire u_rddata_in_127_64_scanout; | |
71 | wire [3:0] rddata31_in; | |
72 | wire [3:0] rddata30_in; | |
73 | wire [3:0] rddata29_in; | |
74 | wire [3:0] rddata28_in; | |
75 | wire [3:0] rddata27_in; | |
76 | wire [3:0] rddata26_in; | |
77 | wire [3:0] rddata25_in; | |
78 | wire [3:0] rddata24_in; | |
79 | wire [3:0] rddata23_in; | |
80 | wire [3:0] rddata22_in; | |
81 | wire [3:0] rddata21_in; | |
82 | wire [3:0] rddata20_in; | |
83 | wire [3:0] rddata19_in; | |
84 | wire [3:0] rddata18_in; | |
85 | wire [3:0] rddata17_in; | |
86 | wire [3:0] rddata16_in; | |
87 | wire u_rddata_in_63_0_scanin; | |
88 | wire u_rddata_in_63_0_scanout; | |
89 | wire [3:0] rddata15_in; | |
90 | wire [3:0] rddata14_in; | |
91 | wire [3:0] rddata13_in; | |
92 | wire [3:0] rddata12_in; | |
93 | wire [3:0] rddata11_in; | |
94 | wire [3:0] rddata10_in; | |
95 | wire [3:0] rddata09_in; | |
96 | wire [3:0] rddata08_in; | |
97 | wire [3:0] rddata07_in; | |
98 | wire [3:0] rddata06_in; | |
99 | wire [3:0] rddata05_in; | |
100 | wire [3:0] rddata04_in; | |
101 | wire [3:0] rddata03_in; | |
102 | wire [3:0] rddata02_in; | |
103 | wire [3:0] rddata01_in; | |
104 | wire [3:0] rddata00_in; | |
105 | wire mux_rdecc_in_err_inj; | |
106 | wire u_rdecc_in_15_8_scanin; | |
107 | wire u_rdecc_in_15_8_scanout; | |
108 | wire [3:0] rd_ecc0_in; | |
109 | wire [3:0] rd_ecc1_in; | |
110 | wire u_rdecc_in_7_0_par_scanin; | |
111 | wire u_rdecc_in_7_0_par_scanout; | |
112 | wire [3:0] rd_ecc2_in; | |
113 | wire [3:0] rd_ecc3_in; | |
114 | wire rd_aparity; | |
115 | wire [3:0] diff_ecc0; | |
116 | wire [3:0] diff_ecc1; | |
117 | wire [3:0] diff_ecc2; | |
118 | wire [3:0] diff_ecc3; | |
119 | wire diffecc0_nz_3_2; | |
120 | wire diffecc0_nz_1_0; | |
121 | wire diffecc0_nz; | |
122 | wire diffecc0_zero; | |
123 | wire diffecc1_nz_3_2; | |
124 | wire diffecc1_nz_1_0; | |
125 | wire diffecc1_nz; | |
126 | wire diffecc1_zero; | |
127 | wire diffecc2_nz_3_2; | |
128 | wire diffecc2_nz_1_0; | |
129 | wire diffecc2_nz; | |
130 | wire diffecc2_zero; | |
131 | wire diffecc3_nz_3_2; | |
132 | wire diffecc3_nz_1_0; | |
133 | wire diffecc3_nz; | |
134 | wire diffecc3_zero; | |
135 | wire [3:0] rddata_cor_result30; | |
136 | wire [3:0] rddata_cor_result29; | |
137 | wire [3:0] rddata_cor_result28; | |
138 | wire [3:0] rddata_cor_result27; | |
139 | wire [3:0] rddata_cor_result26; | |
140 | wire [3:0] rddata_cor_result25; | |
141 | wire [3:0] rddata_cor_result24; | |
142 | wire [3:0] rddata_cor_result23; | |
143 | wire [3:0] rddata_cor_result22; | |
144 | wire [3:0] rddata_cor_result21; | |
145 | wire [3:0] rddata_cor_result20; | |
146 | wire [3:0] rddata_cor_result19; | |
147 | wire [3:0] rddata_cor_result18; | |
148 | wire [3:0] rddata_cor_result17; | |
149 | wire [3:0] rddata_cor_result15; | |
150 | wire [3:0] rddata_cor_result14; | |
151 | wire [3:0] rddata_cor_result13; | |
152 | wire [3:0] rddata_cor_result12; | |
153 | wire [3:0] rddata_cor_result11; | |
154 | wire [3:0] rddata_cor_result10; | |
155 | wire [3:0] rddata_cor_result09; | |
156 | wire [3:0] rddata_cor_result08; | |
157 | wire [3:0] rddata_cor_result07; | |
158 | wire [3:0] rddata_cor_result06; | |
159 | wire [3:0] rddata_cor_result05; | |
160 | wire [3:0] rddata_cor_result04; | |
161 | wire [3:0] rddata_cor_result03; | |
162 | wire [3:0] rddata_cor_result02; | |
163 | wire diffecc3_z_failmode_1; | |
164 | wire diffecc3_z_failmode; | |
165 | wire diffecc_1_2_zero; | |
166 | wire diffecc_0_2_zero; | |
167 | wire diffecc_0_1_zero; | |
168 | wire diffecc_0_1_2_zero; | |
169 | wire diffecc0_adj; | |
170 | wire diffecc1_adj; | |
171 | wire diffecc2_adj; | |
172 | wire diffecc3_nz_failmode; | |
173 | wire [3:0] diff_ecc0_adj; | |
174 | wire [3:0] diff_ecc1_adj; | |
175 | wire [3:0] diff_ecc2_adj; | |
176 | wire [3:0] diff_ecc3_adj; | |
177 | wire [3:0] secc_err; | |
178 | wire diffecc0_adj_nz_3_2; | |
179 | wire diffecc0_adj_nz_1_0; | |
180 | wire diffecc0_adj_nz; | |
181 | wire diffecc0_adj_zero; | |
182 | wire diffecc1_adj_nz_3_2; | |
183 | wire diffecc1_adj_nz_1_0; | |
184 | wire diffecc1_adj_nz; | |
185 | wire diffecc1_adj_zero; | |
186 | wire diffecc2_adj_nz_3_2; | |
187 | wire diffecc2_adj_nz_1_0; | |
188 | wire diffecc2_adj_nz; | |
189 | wire diffecc2_adj_zero; | |
190 | wire diffecc3_adj_nz_3_2; | |
191 | wire diffecc3_adj_nz_1_0; | |
192 | wire diffecc3_adj_nz; | |
193 | wire diffecc3_adj_zero; | |
194 | wire byte00_err_1; | |
195 | wire byte01_err_1; | |
196 | wire byte02_err_1; | |
197 | wire byte03_err_1; | |
198 | wire byte04_err_1; | |
199 | wire byte05_err_1; | |
200 | wire byte06_err_1; | |
201 | wire byte07_err_1; | |
202 | wire byte08_err_1; | |
203 | wire byte09_err_1; | |
204 | wire byte10_err_1; | |
205 | wire byte11_err_1; | |
206 | wire byte12_err_1; | |
207 | wire byte13_err_1; | |
208 | wire byte14_err_1; | |
209 | wire byte15_err_1; | |
210 | wire byte16_err_1; | |
211 | wire byte17_err_1; | |
212 | wire byte18_err_1; | |
213 | wire byte19_err_1; | |
214 | wire byte20_err_1; | |
215 | wire byte21_err_1; | |
216 | wire byte22_err_1; | |
217 | wire byte23_err_1; | |
218 | wire byte24_err_1; | |
219 | wire byte25_err_1; | |
220 | wire byte26_err_1; | |
221 | wire byte27_err_1; | |
222 | wire byte28_err_1; | |
223 | wire byte29_err_1; | |
224 | wire byte3031_err_1; | |
225 | wire errpos_0to14; | |
226 | wire byte00_err; | |
227 | wire byte01_err; | |
228 | wire byte02_err; | |
229 | wire byte03_err; | |
230 | wire byte04_err; | |
231 | wire byte05_err; | |
232 | wire byte06_err; | |
233 | wire byte07_err; | |
234 | wire byte08_err; | |
235 | wire byte09_err; | |
236 | wire byte10_err; | |
237 | wire byte11_err; | |
238 | wire byte12_err; | |
239 | wire byte13_err; | |
240 | wire byte14_err; | |
241 | wire errpos_15to29; | |
242 | wire byte15_err; | |
243 | wire byte16_err; | |
244 | wire byte17_err; | |
245 | wire byte18_err; | |
246 | wire byte19_err; | |
247 | wire byte20_err; | |
248 | wire byte21_err; | |
249 | wire byte22_err; | |
250 | wire byte23_err; | |
251 | wire byte24_err; | |
252 | wire byte25_err; | |
253 | wire byte26_err; | |
254 | wire byte27_err; | |
255 | wire byte28_err; | |
256 | wire byte29_err; | |
257 | wire byte30_err; | |
258 | wire byte31_err; | |
259 | wire [3:0] outbyte00_1; | |
260 | wire [3:0] outbyte01_1; | |
261 | wire [3:0] outbyte02_1; | |
262 | wire [3:0] outbyte03_1; | |
263 | wire [3:0] outbyte04_1; | |
264 | wire [3:0] outbyte05_1; | |
265 | wire [3:0] outbyte06_1; | |
266 | wire [3:0] outbyte07_1; | |
267 | wire [3:0] outbyte08_1; | |
268 | wire [3:0] outbyte09_1; | |
269 | wire [3:0] outbyte10_1; | |
270 | wire [3:0] outbyte11_1; | |
271 | wire [3:0] outbyte12_1; | |
272 | wire [3:0] outbyte13_1; | |
273 | wire [3:0] outbyte14_1; | |
274 | wire [3:0] outbyte15_1; | |
275 | wire [3:0] outbyte16_1; | |
276 | wire [3:0] outbyte17_1; | |
277 | wire [3:0] outbyte18_1; | |
278 | wire [3:0] outbyte19_1; | |
279 | wire [3:0] outbyte20_1; | |
280 | wire [3:0] outbyte21_1; | |
281 | wire [3:0] outbyte22_1; | |
282 | wire [3:0] outbyte23_1; | |
283 | wire [3:0] outbyte24_1; | |
284 | wire [3:0] outbyte25_1; | |
285 | wire [3:0] outbyte26_1; | |
286 | wire [3:0] outbyte27_1; | |
287 | wire [3:0] outbyte28_1; | |
288 | wire [3:0] outbyte29_1; | |
289 | wire [3:0] outbyte30_1; | |
290 | wire [3:0] outbyte31_1; | |
291 | wire [3:0] outbyte00; | |
292 | wire [3:0] outbyte01; | |
293 | wire [3:0] outbyte02; | |
294 | wire [3:0] outbyte03; | |
295 | wire [3:0] outbyte04; | |
296 | wire [3:0] outbyte05; | |
297 | wire [3:0] outbyte06; | |
298 | wire [3:0] outbyte07; | |
299 | wire [3:0] outbyte08; | |
300 | wire [3:0] outbyte09; | |
301 | wire [3:0] outbyte10; | |
302 | wire [3:0] outbyte11; | |
303 | wire [3:0] outbyte12; | |
304 | wire [3:0] outbyte13; | |
305 | wire [3:0] outbyte14; | |
306 | wire [3:0] outbyte15; | |
307 | wire [3:0] outbyte16; | |
308 | wire [3:0] outbyte17; | |
309 | wire [3:0] outbyte18; | |
310 | wire [3:0] outbyte19; | |
311 | wire [3:0] outbyte20; | |
312 | wire [3:0] outbyte21; | |
313 | wire [3:0] outbyte22; | |
314 | wire [3:0] outbyte23; | |
315 | wire [3:0] outbyte24; | |
316 | wire [3:0] outbyte25; | |
317 | wire [3:0] outbyte26; | |
318 | wire [3:0] outbyte27; | |
319 | wire [3:0] outbyte28; | |
320 | wire [3:0] outbyte29; | |
321 | wire [3:0] outbyte30; | |
322 | wire [3:0] outbyte31; | |
323 | wire byte00_err_mecc_1; | |
324 | wire byte08_23_err_mecc_1; | |
325 | wire byte13_28_err_mecc_1; | |
326 | wire byte12_27_err_mecc_1; | |
327 | wire byte10_25_err_mecc_1; | |
328 | wire byte06_21_err_mecc_1; | |
329 | wire byte05_20_err_mecc_1; | |
330 | wire byte14_29_err_mecc_1; | |
331 | wire byte01_16_err_mecc_1; | |
332 | wire byte11_26_err_mecc_1; | |
333 | wire byte04_19_err_mecc_1; | |
334 | wire byte09_24_err_mecc_1; | |
335 | wire byte03_18_err_mecc_1; | |
336 | wire byte02_17_err_mecc_1; | |
337 | wire byte07_22_err_mecc_1; | |
338 | wire byte15_err_mecc_1; | |
339 | wire bytexx_err_mecc_2; | |
340 | wire byteyy_err_mecc_2; | |
341 | wire byte00_err_mecc; | |
342 | wire byte01_err_mecc; | |
343 | wire byte02_err_mecc; | |
344 | wire byte03_err_mecc; | |
345 | wire byte04_err_mecc; | |
346 | wire byte05_err_mecc; | |
347 | wire byte06_err_mecc; | |
348 | wire byte07_err_mecc; | |
349 | wire byte08_err_mecc; | |
350 | wire byte09_err_mecc; | |
351 | wire byte10_err_mecc; | |
352 | wire byte11_err_mecc; | |
353 | wire byte12_err_mecc; | |
354 | wire byte13_err_mecc; | |
355 | wire byte14_err_mecc; | |
356 | wire byte15_err_mecc; | |
357 | wire byte16_err_mecc; | |
358 | wire byte17_err_mecc; | |
359 | wire byte18_err_mecc; | |
360 | wire byte19_err_mecc; | |
361 | wire byte20_err_mecc; | |
362 | wire byte21_err_mecc; | |
363 | wire byte22_err_mecc; | |
364 | wire byte23_err_mecc; | |
365 | wire byte24_err_mecc; | |
366 | wire byte25_err_mecc; | |
367 | wire byte26_err_mecc; | |
368 | wire byte27_err_mecc; | |
369 | wire byte28_err_mecc; | |
370 | wire byte29_err_mecc; | |
371 | wire [14:0] err_byte_0_14_loc; | |
372 | wire [14:0] err_byte_15_29_loc; | |
373 | wire [10:0] ecc_multi_err_1; | |
374 | wire [10:0] ecc_multi_err_2; | |
375 | wire ecc_loc_err_byte_0_14_loc_eq; | |
376 | wire ecc_loc_err_byte_15_29_loc_eq; | |
377 | wire diffecc0ecc1_adj_ne; | |
378 | wire diffecc1ecc2_adj_ne; | |
379 | wire diffecc2ecc3_adj_ne; | |
380 | wire eccloc_errbyte_0014loc_ne; | |
381 | wire eccloc_errbyte_1529loc_ne; | |
382 | wire ecc_multi_err1_4; | |
383 | wire ecc_multi_err0_4; | |
384 | wire ecc_multi_err3_5; | |
385 | wire ecc_multi_err2_5; | |
386 | wire ecc_multi_err1_5; | |
387 | wire ecc_multi_err0_5; | |
388 | wire ecc_multi_err3_6; | |
389 | wire ecc_multi_err2_6; | |
390 | wire ecc_multi_err1_6; | |
391 | wire ecc_multi_err0_6; | |
392 | wire ecc_multi_err; | |
393 | wire secc_err31; | |
394 | wire secc_err30; | |
395 | wire secc_err_hi; | |
396 | wire secc_err_lo; | |
397 | wire ecc_single_err_1; | |
398 | wire ecc_single_err_2; | |
399 | wire ecc_single_err_3; | |
400 | wire ecc_single_err_4; | |
401 | wire ecc_single_err; | |
402 | wire u_rddata_127_64_secc_err_scanin; | |
403 | wire u_rddata_127_64_secc_err_scanout; | |
404 | wire u_rddata_63_0_mecc_err_scanin; | |
405 | wire u_rddata_63_0_mecc_err_scanout; | |
406 | ||
407 | ||
408 | input drl2clk; | |
409 | input scan_in; | |
410 | output scan_out; | |
411 | input tcu_pce_ov; | |
412 | input tcu_aclk; | |
413 | input tcu_bclk; | |
414 | input tcu_scan_en; | |
415 | ||
416 | input [1:0] rddata_en; // read data nput reg enables | |
417 | input radr_parity; // read address parity to generate ECC from memory read data | |
418 | input inj_ecc_err; | |
419 | ||
420 | input [15:0] io_mcu_ecc_in; // DRAM ECC data | |
421 | input [127:0] io_mcu_data_in; // DRAM read data | |
422 | input fail_over_mode; // fail over mode | |
423 | input [34:0] fail_over_mask; // fail_over_mask_reg select | |
424 | input [34:0] fail_over_mask_l; // fail_over_mask_reg select | |
425 | ||
426 | input fbdic_rddata_vld; | |
427 | ||
428 | output dr_secc_err; // single bit error detected in drl2clk domain | |
429 | output dr_mecc_err; // multi bits error detected in drl2clk domain | |
430 | output [127:0] rddata; // memory read data for L2 | |
431 | ||
432 | output [35:0] ecc_loc; // error nibble location | |
433 | output [127:0] cor_rddata; // corrected read data to scrub data registers in the MCU write DP | |
434 | ||
435 | output [15:0] syndrome; | |
436 | ||
437 | output mcu_gnd; | |
438 | ||
439 | // Scan reassigns | |
440 | assign pce_ov = tcu_pce_ov; | |
441 | assign stop = 1'b0; | |
442 | assign siclk = tcu_aclk; | |
443 | assign soclk = tcu_bclk; | |
444 | assign se = tcu_scan_en; | |
445 | ||
446 | // | |
447 | mcu_readdp_dp_buff_macro__width_2 u_rddata_vld_buf ( | |
448 | .din ( {fbdic_rddata_vld, 1'b0} ), | |
449 | .dout( {fbdic_rddata_vld_buf, mcu_gnd} )); | |
450 | ||
451 | mcu_readdp_dp_and_macro__width_16 u_and_ecc_15_0 ( | |
452 | .din0( {16{fbdic_rddata_vld_buf}} ), | |
453 | .din1( io_mcu_ecc_in[15:0] ), | |
454 | .dout( io_mcu_ecc[15:0] )); | |
455 | ||
456 | mcu_readdp_dp_and_macro__width_64 u_and_data_127_64 ( | |
457 | .din0( {64{fbdic_rddata_vld_buf}} ), | |
458 | .din1( io_mcu_data_in[127:64] ), | |
459 | .dout( io_mcu_data[127:64] )); | |
460 | ||
461 | mcu_readdp_dp_and_macro__width_64 u_and_data_63_0 ( | |
462 | .din0( {64{fbdic_rddata_vld_buf}} ), | |
463 | .din1( io_mcu_data_in[63:0] ), | |
464 | .dout( io_mcu_data[63:0] )); | |
465 | ||
466 | // | |
467 | // Memory read data return FailOverMask muxes of 128 bits data and 16 bits ECC | |
468 | // | |
469 | ||
470 | // ecc[15:0] | |
471 | ||
472 | // ECC0 | |
473 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rdecc_in_15_12 ( | |
474 | .din0 ( io_mcu_ecc[11:8] ), | |
475 | .din1 ( io_mcu_ecc[15:12] ), | |
476 | .sel0 ( fail_over_mask[32] ), | |
477 | .sel1 ( fail_over_mask_l[32] ), | |
478 | .dout ( mux_rdecc_in[15:12] )); | |
479 | ||
480 | // ECC1 | |
481 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rdecc_in_11_8 ( | |
482 | .din0 ( io_mcu_ecc[7:4] ), | |
483 | .din1 ( io_mcu_ecc[11:8] ), | |
484 | .sel0 ( fail_over_mask[33] ), | |
485 | .sel1 ( fail_over_mask_l[33] ), | |
486 | .dout ( mux_rdecc_in[11:8] )); | |
487 | ||
488 | // ECC1 | |
489 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rdecc_in_7_4 ( | |
490 | .din0 ( io_mcu_ecc[3:0] ), | |
491 | .din1 ( io_mcu_ecc[7:4] ), | |
492 | .sel0 ( fail_over_mask[34] ), | |
493 | .sel1 ( fail_over_mask_l[34] ), | |
494 | .dout ( mux_rdecc_in[7:4] )); | |
495 | ||
496 | // ECC3 | |
497 | assign mux_rdecc_in[3:0] = io_mcu_ecc[3:0]; | |
498 | ||
499 | // data[127:0] | |
500 | ||
501 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_127_124 ( | |
502 | .din0 ( io_mcu_ecc[15:12] ), | |
503 | .din1 ( io_mcu_data[127:124] ), | |
504 | .sel0 ( fail_over_mask[31] ), | |
505 | .sel1 ( fail_over_mask_l[31] ), | |
506 | .dout ( mux_rddata_in[127:124] )); | |
507 | ||
508 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_123_120 ( | |
509 | .din0 ( io_mcu_data[127:124] ), | |
510 | .din1 ( io_mcu_data[123:120] ), | |
511 | .sel0 ( fail_over_mask[30] ), | |
512 | .sel1 ( fail_over_mask_l[30] ), | |
513 | .dout ( mux_rddata_in[123:120] )); | |
514 | ||
515 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_119_116 ( | |
516 | .din0 ( io_mcu_data[123:120] ), | |
517 | .din1 ( io_mcu_data[119:116] ), | |
518 | .sel0 ( fail_over_mask[29] ), | |
519 | .sel1 ( fail_over_mask_l[29] ), | |
520 | .dout ( mux_rddata_in[119:116] )); | |
521 | ||
522 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_115_112 ( | |
523 | .din0 ( io_mcu_data[119:116] ), | |
524 | .din1 ( io_mcu_data[115:112] ), | |
525 | .sel0 ( fail_over_mask[28] ), | |
526 | .sel1 ( fail_over_mask_l[28] ), | |
527 | .dout ( mux_rddata_in[115:112] )); | |
528 | ||
529 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_111_108 ( | |
530 | .din0 ( io_mcu_data[115:112] ), | |
531 | .din1 ( io_mcu_data[111:108] ), | |
532 | .sel0 ( fail_over_mask[27] ), | |
533 | .sel1 ( fail_over_mask_l[27] ), | |
534 | .dout ( mux_rddata_in[111:108] )); | |
535 | ||
536 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_107_104 ( | |
537 | .din0 ( io_mcu_data[111:108] ), | |
538 | .din1 ( io_mcu_data[107:104] ), | |
539 | .sel0 ( fail_over_mask[26] ), | |
540 | .sel1 ( fail_over_mask_l[26] ), | |
541 | .dout ( mux_rddata_in[107:104] )); | |
542 | ||
543 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_103_100 ( | |
544 | .din0 ( io_mcu_data[107:104] ), | |
545 | .din1 ( io_mcu_data[103:100] ), | |
546 | .sel0 ( fail_over_mask[25] ), | |
547 | .sel1 ( fail_over_mask_l[25] ), | |
548 | .dout ( mux_rddata_in[103:100] )); | |
549 | ||
550 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_99_96 ( | |
551 | .din0 ( io_mcu_data[103:100] ), | |
552 | .din1 ( io_mcu_data[99:96] ), | |
553 | .sel0 ( fail_over_mask[24] ), | |
554 | .sel1 ( fail_over_mask_l[24] ), | |
555 | .dout ( mux_rddata_in[99:96] )); | |
556 | ||
557 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_95_92 ( | |
558 | .din0 ( io_mcu_data[99:96] ), | |
559 | .din1 ( io_mcu_data[95:92] ), | |
560 | .sel0 ( fail_over_mask[23] ), | |
561 | .sel1 ( fail_over_mask_l[23] ), | |
562 | .dout ( mux_rddata_in[95:92] )); | |
563 | ||
564 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_91_88 ( | |
565 | .din0 ( io_mcu_data[95:92] ), | |
566 | .din1 ( io_mcu_data[91:88] ), | |
567 | .sel0 ( fail_over_mask[22] ), | |
568 | .sel1 ( fail_over_mask_l[22] ), | |
569 | .dout ( mux_rddata_in[91:88] )); | |
570 | ||
571 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_87_84 ( | |
572 | .din0 ( io_mcu_data[91:88] ), | |
573 | .din1 ( io_mcu_data[87:84] ), | |
574 | .sel0 ( fail_over_mask[21] ), | |
575 | .sel1 ( fail_over_mask_l[21] ), | |
576 | .dout ( mux_rddata_in[87:84] )); | |
577 | ||
578 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_83_80 ( | |
579 | .din0 ( io_mcu_data[87:84] ), | |
580 | .din1 ( io_mcu_data[83:80] ), | |
581 | .sel0 ( fail_over_mask[20] ), | |
582 | .sel1 ( fail_over_mask_l[20] ), | |
583 | .dout ( mux_rddata_in[83:80] )); | |
584 | ||
585 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_79_76 ( | |
586 | .din0 ( io_mcu_data[83:80] ), | |
587 | .din1 ( io_mcu_data[79:76] ), | |
588 | .sel0 ( fail_over_mask[19] ), | |
589 | .sel1 ( fail_over_mask_l[19] ), | |
590 | .dout ( mux_rddata_in[79:76] )); | |
591 | ||
592 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_75_72 ( | |
593 | .din0 ( io_mcu_data[79:76] ), | |
594 | .din1 ( io_mcu_data[75:72] ), | |
595 | .sel0 ( fail_over_mask[18] ), | |
596 | .sel1 ( fail_over_mask_l[18] ), | |
597 | .dout ( mux_rddata_in[75:72] )); | |
598 | ||
599 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_71_68 ( | |
600 | .din0 ( io_mcu_data[75:72] ), | |
601 | .din1 ( io_mcu_data[71:68] ), | |
602 | .sel0 ( fail_over_mask[17] ), | |
603 | .sel1 ( fail_over_mask_l[17] ), | |
604 | .dout ( mux_rddata_in[71:68] )); | |
605 | ||
606 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_67_64 ( | |
607 | .din0 ( io_mcu_data[71:68] ), | |
608 | .din1 ( io_mcu_data[67:64] ), | |
609 | .sel0 ( fail_over_mask[16] ), | |
610 | .sel1 ( fail_over_mask_l[16] ), | |
611 | .dout ( mux_rddata_in[67:64] )); | |
612 | ||
613 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_63_60 ( | |
614 | .din0 ( io_mcu_data[67:64] ), | |
615 | .din1 ( io_mcu_data[63:60] ), | |
616 | .sel0 ( fail_over_mask[15] ), | |
617 | .sel1 ( fail_over_mask_l[15] ), | |
618 | .dout ( mux_rddata_in[63:60] )); | |
619 | ||
620 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_59_56 ( | |
621 | .din0 ( io_mcu_data[63:60] ), | |
622 | .din1 ( io_mcu_data[59:56] ), | |
623 | .sel0 ( fail_over_mask[14] ), | |
624 | .sel1 ( fail_over_mask_l[14] ), | |
625 | .dout ( mux_rddata_in[59:56] )); | |
626 | ||
627 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_55_52 ( | |
628 | .din0 ( io_mcu_data[59:56] ), | |
629 | .din1 ( io_mcu_data[55:52] ), | |
630 | .sel0 ( fail_over_mask[13] ), | |
631 | .sel1 ( fail_over_mask_l[13] ), | |
632 | .dout ( mux_rddata_in[55:52] )); | |
633 | ||
634 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_51_48 ( | |
635 | .din0 ( io_mcu_data[55:52] ), | |
636 | .din1 ( io_mcu_data[51:48] ), | |
637 | .sel0 ( fail_over_mask[12] ), | |
638 | .sel1 ( fail_over_mask_l[12] ), | |
639 | .dout ( mux_rddata_in[51:48] )); | |
640 | ||
641 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_47_44 ( | |
642 | .din0 ( io_mcu_data[51:48] ), | |
643 | .din1 ( io_mcu_data[47:44] ), | |
644 | .sel0 ( fail_over_mask[11] ), | |
645 | .sel1 ( fail_over_mask_l[11] ), | |
646 | .dout ( mux_rddata_in[47:44] )); | |
647 | ||
648 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_43_40 ( | |
649 | .din0 ( io_mcu_data[47:44] ), | |
650 | .din1 ( io_mcu_data[43:40] ), | |
651 | .sel0 ( fail_over_mask[10] ), | |
652 | .sel1 ( fail_over_mask_l[10] ), | |
653 | .dout ( mux_rddata_in[43:40] )); | |
654 | ||
655 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_39_36 ( | |
656 | .din0 ( io_mcu_data[43:40] ), | |
657 | .din1 ( io_mcu_data[39:36] ), | |
658 | .sel0 ( fail_over_mask[9] ), | |
659 | .sel1 ( fail_over_mask_l[9] ), | |
660 | .dout ( mux_rddata_in[39:36] )); | |
661 | ||
662 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_35_32 ( | |
663 | .din0 ( io_mcu_data[39:36] ), | |
664 | .din1 ( io_mcu_data[35:32] ), | |
665 | .sel0 ( fail_over_mask[8] ), | |
666 | .sel1 ( fail_over_mask_l[8] ), | |
667 | .dout ( mux_rddata_in[35:32] )); | |
668 | ||
669 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_31_28 ( | |
670 | .din0 ( io_mcu_data[35:32] ), | |
671 | .din1 ( io_mcu_data[31:28] ), | |
672 | .sel0 ( fail_over_mask[7] ), | |
673 | .sel1 ( fail_over_mask_l[7] ), | |
674 | .dout ( mux_rddata_in[31:28] )); | |
675 | ||
676 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_27_24 ( | |
677 | .din0 ( io_mcu_data[31:28] ), | |
678 | .din1 ( io_mcu_data[27:24] ), | |
679 | .sel0 ( fail_over_mask[6] ), | |
680 | .sel1 ( fail_over_mask_l[6] ), | |
681 | .dout ( mux_rddata_in[27:24] )); | |
682 | ||
683 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_23_20 ( | |
684 | .din0 ( io_mcu_data[27:24] ), | |
685 | .din1 ( io_mcu_data[23:20] ), | |
686 | .sel0 ( fail_over_mask[5] ), | |
687 | .sel1 ( fail_over_mask_l[5] ), | |
688 | .dout ( mux_rddata_in[23:20] )); | |
689 | ||
690 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_19_16 ( | |
691 | .din0 ( io_mcu_data[23:20] ), | |
692 | .din1 ( io_mcu_data[19:16] ), | |
693 | .sel0 ( fail_over_mask[4] ), | |
694 | .sel1 ( fail_over_mask_l[4] ), | |
695 | .dout ( mux_rddata_in[19:16] )); | |
696 | ||
697 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_15_12 ( | |
698 | .din0 ( io_mcu_data[19:16] ), | |
699 | .din1 ( io_mcu_data[15:12] ), | |
700 | .sel0 ( fail_over_mask[3] ), | |
701 | .sel1 ( fail_over_mask_l[3] ), | |
702 | .dout ( mux_rddata_in[15:12] )); | |
703 | ||
704 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_11_8 ( | |
705 | .din0 ( io_mcu_data[15:12] ), | |
706 | .din1 ( io_mcu_data[11:8] ), | |
707 | .sel0 ( fail_over_mask[2] ), | |
708 | .sel1 ( fail_over_mask_l[2] ), | |
709 | .dout ( mux_rddata_in[11:8] )); | |
710 | ||
711 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_7_4 ( | |
712 | .din0 ( io_mcu_data[11:8] ), | |
713 | .din1 ( io_mcu_data[7:4] ), | |
714 | .sel0 ( fail_over_mask[1] ), | |
715 | .sel1 ( fail_over_mask_l[1] ), | |
716 | .dout ( mux_rddata_in[7:4] )); | |
717 | ||
718 | mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 u_mux_rddata_in_3_0 ( | |
719 | .din0 ( io_mcu_data[7:4] ), | |
720 | .din1 ( io_mcu_data[3:0] ), | |
721 | .sel0 ( fail_over_mask[0] ), | |
722 | .sel1 ( fail_over_mask_l[0] ), | |
723 | .dout ( mux_rddata_in[3:0] )); | |
724 | ||
725 | // | |
726 | // Memory read data input registers. In 1-DIMM mode, 128 bits data and 16 bits are captured in 2 | |
727 | // mcu_clk cycles. | |
728 | // | |
729 | mcu_readdp_dp_msff_macro__stack_64c__width_64 u_rddata_in_127_64 ( | |
730 | .scan_in(u_rddata_in_127_64_scanin), | |
731 | .scan_out(u_rddata_in_127_64_scanout), | |
732 | .clk ( drl2clk), | |
733 | .en ( rddata_en[0] ), | |
734 | .din ( mux_rddata_in[127:64] ), | |
735 | .dout ( { rddata31_in[3:0], rddata30_in[3:0], rddata29_in[3:0], rddata28_in[3:0], | |
736 | rddata27_in[3:0], rddata26_in[3:0], rddata25_in[3:0], rddata24_in[3:0], | |
737 | rddata23_in[3:0], rddata22_in[3:0], rddata21_in[3:0], rddata20_in[3:0], | |
738 | rddata19_in[3:0], rddata18_in[3:0], rddata17_in[3:0], rddata16_in[3:0] } ), | |
739 | .se(se), | |
740 | .siclk(siclk), | |
741 | .soclk(soclk), | |
742 | .pce_ov(pce_ov), | |
743 | .stop(stop)); | |
744 | ||
745 | mcu_readdp_dp_msff_macro__stack_64c__width_64 u_rddata_in_63_0 ( | |
746 | .scan_in(u_rddata_in_63_0_scanin), | |
747 | .scan_out(u_rddata_in_63_0_scanout), | |
748 | .clk ( drl2clk ), | |
749 | .en ( rddata_en[0] ), | |
750 | .din ( mux_rddata_in[63:0] ), | |
751 | .dout ( { rddata15_in[3:0], rddata14_in[3:0], rddata13_in[3:0], rddata12_in[3:0], | |
752 | rddata11_in[3:0], rddata10_in[3:0], rddata09_in[3:0], rddata08_in[3:0], | |
753 | rddata07_in[3:0], rddata06_in[3:0], rddata05_in[3:0], rddata04_in[3:0], | |
754 | rddata03_in[3:0], rddata02_in[3:0], rddata01_in[3:0], rddata00_in[3:0] } ), | |
755 | .se(se), | |
756 | .siclk(siclk), | |
757 | .soclk(soclk), | |
758 | .pce_ov(pce_ov), | |
759 | .stop(stop)); | |
760 | ||
761 | ||
762 | // | |
763 | // | |
764 | // | |
765 | ||
766 | mcu_readdp_dp_xor_macro__ports_2 u_xor_err_inj ( | |
767 | .din0(mux_rdecc_in[15]), | |
768 | .din1(inj_ecc_err), | |
769 | .dout(mux_rdecc_in_err_inj)); | |
770 | ||
771 | mcu_readdp_dp_msff_macro__stack_8l__width_8 u_rdecc_in_15_8 ( | |
772 | .scan_in(u_rdecc_in_15_8_scanin), | |
773 | .scan_out(u_rdecc_in_15_8_scanout), | |
774 | .clk ( drl2clk ), | |
775 | .en ( rddata_en[0] ), | |
776 | .din ( {mux_rdecc_in_err_inj, mux_rdecc_in[14:8]} ), | |
777 | .dout ( {rd_ecc0_in[3:0], rd_ecc1_in[3:0]} ), | |
778 | .se(se), | |
779 | .siclk(siclk), | |
780 | .soclk(soclk), | |
781 | .pce_ov(pce_ov), | |
782 | .stop(stop)); | |
783 | ||
784 | mcu_readdp_dp_msff_macro__stack_10l__width_9 u_rdecc_in_7_0_par ( | |
785 | .scan_in(u_rdecc_in_7_0_par_scanin), | |
786 | .scan_out(u_rdecc_in_7_0_par_scanout), | |
787 | .clk ( drl2clk ), | |
788 | .en ( rddata_en[0] ), | |
789 | .din ( {mux_rdecc_in[7:0], radr_parity} ), | |
790 | .dout ( {rd_ecc2_in[3:0], rd_ecc3_in[3:0], rd_aparity} ), | |
791 | .se(se), | |
792 | .siclk(siclk), | |
793 | .soclk(soclk), | |
794 | .pce_ov(pce_ov), | |
795 | .stop(stop)); | |
796 | ||
797 | // | |
798 | // Generate ECC for the incoming data, and compute the diffs of incoming ECC data | |
799 | // and generated ECC of the incoming data. | |
800 | // | |
801 | mcu_eccgen_dp u_r_eccgen ( | |
802 | .din ( { rddata31_in[3:0], rddata30_in[3:0], rddata29_in[3:0], rddata28_in[3:0], | |
803 | rddata27_in[3:0], rddata26_in[3:0], rddata25_in[3:0], rddata24_in[3:0], | |
804 | rddata23_in[3:0], rddata22_in[3:0], rddata21_in[3:0], rddata20_in[3:0], | |
805 | rddata19_in[3:0], rddata18_in[3:0], rddata17_in[3:0], rddata16_in[3:0], | |
806 | rddata15_in[3:0], rddata14_in[3:0], rddata13_in[3:0], rddata12_in[3:0], | |
807 | rddata11_in[3:0], rddata10_in[3:0], rddata09_in[3:0], rddata08_in[3:0], | |
808 | rddata07_in[3:0], rddata06_in[3:0], rddata05_in[3:0], rddata04_in[3:0], | |
809 | rddata03_in[3:0], rddata02_in[3:0], rddata01_in[3:0], rddata00_in[3:0] } ), | |
810 | .adr_parity ( rd_aparity ), | |
811 | .ecc0_in ( rd_ecc0_in[3:0] ), | |
812 | .ecc1_in ( rd_ecc1_in[3:0] ), | |
813 | .ecc2_in ( rd_ecc2_in[3:0] ), | |
814 | .ecc3_in ( rd_ecc3_in[3:0] ), | |
815 | .ecc ( { diff_ecc0[3:0], diff_ecc1[3:0], diff_ecc2[3:0], diff_ecc3[3:0] } )); | |
816 | ||
817 | assign syndrome[15:0] = { diff_ecc3[3:0], diff_ecc2[3:0], diff_ecc1[3:0], diff_ecc0[3:0] }; | |
818 | ||
819 | ||
820 | // | |
821 | // Generate zero, and not_equal_zero for diff_eccX. | |
822 | // | |
823 | mcu_readdp_dp_nor_macro__ports_2__stack_1l__width_1 u_diffecc0_nz_3_2 ( .din0 ( diff_ecc0[3] ), .din1 ( diff_ecc0[2] ), .dout ( diffecc0_nz_3_2 )); | |
824 | mcu_readdp_dp_nor_macro__ports_2__stack_1l__width_1 u_diffecc0_nz_1_0 ( .din0 ( diff_ecc0[1] ), .din1 ( diff_ecc0[0] ), .dout ( diffecc0_nz_1_0 )); | |
825 | mcu_readdp_dp_nand_macro__ports_2__stack_1l__width_1 u_diffecc0_nz ( .din0 ( diffecc0_nz_3_2 ), .din1 ( diffecc0_nz_1_0 ), .dout ( diffecc0_nz )); | |
826 | //and_macro U_diffecc0_zero ( stack = 1l , width = 1 , ports = 2 ) ( .din0 ( diffecc0_nz_3_2 ), .din1 ( diffecc0_nz_1_0 ), .dout ( diffecc0_zero )); | |
827 | mcu_readdp_dp_inv_macro__stack_1l__width_1 u_diffecc0_zero ( .din ( diffecc0_nz ), .dout ( diffecc0_zero )); | |
828 | ||
829 | ||
830 | mcu_readdp_dp_nor_macro__ports_2__stack_1l__width_1 u_diffecc1_nz_3_2 ( .din0 ( diff_ecc1[3] ), .din1 ( diff_ecc1[2] ), .dout ( diffecc1_nz_3_2 )); | |
831 | mcu_readdp_dp_nor_macro__ports_2__stack_1l__width_1 u_diffecc1_nz_1_0 ( .din0 ( diff_ecc1[1] ), .din1 ( diff_ecc1[0] ), .dout ( diffecc1_nz_1_0 )); | |
832 | mcu_readdp_dp_nand_macro__ports_2__stack_1l__width_1 u_diffecc1_nz ( .din0 ( diffecc1_nz_3_2 ), .din1 ( diffecc1_nz_1_0 ), .dout ( diffecc1_nz )); | |
833 | //and_macro U_diffecc1_zero ( stack = 1l , width = 1 , ports = 2 ) ( .din0 ( diffecc1_nz_3_2 ), .din1 ( diffecc1_nz_1_0 ), .dout ( diffecc1_zero )); | |
834 | mcu_readdp_dp_inv_macro__stack_1l__width_1 u_diffecc1_zero ( .din ( diffecc1_nz ), .dout ( diffecc1_zero )); | |
835 | ||
836 | mcu_readdp_dp_nor_macro__ports_2__stack_1l__width_1 u_diffecc2_nz_3_2 ( .din0 ( diff_ecc2[3] ), .din1 ( diff_ecc2[2] ), .dout ( diffecc2_nz_3_2 )); | |
837 | mcu_readdp_dp_nor_macro__ports_2__stack_1l__width_1 u_diffecc2_nz_1_0 ( .din0 ( diff_ecc2[1] ), .din1 ( diff_ecc2[0] ), .dout ( diffecc2_nz_1_0 )); | |
838 | mcu_readdp_dp_nand_macro__ports_2__stack_1l__width_1 u_diffecc2_nz ( .din0 ( diffecc2_nz_3_2 ), .din1 ( diffecc2_nz_1_0 ), .dout ( diffecc2_nz )); | |
839 | //and_macro U_diffecc2_zero ( stack = 1l , width = 1 , ports = 2 ) ( .din0 ( diffecc2_nz_3_2 ), .din1 ( diffecc2_nz_1_0 ), .dout ( diffecc2_zero )); | |
840 | mcu_readdp_dp_inv_macro__stack_1l__width_1 u_diffecc2_zero ( .din ( diffecc2_nz ), .dout ( diffecc2_zero )); | |
841 | ||
842 | mcu_readdp_dp_nor_macro__ports_2__stack_1l__width_1 u_diffecc3_nz_3_2 ( .din0 ( diff_ecc3[3] ), .din1 ( diff_ecc3[2] ), .dout ( diffecc3_nz_3_2 )); | |
843 | mcu_readdp_dp_nor_macro__ports_2__stack_1l__width_1 u_diffecc3_nz_1_0 ( .din0 ( diff_ecc3[1] ), .din1 ( diff_ecc3[0] ), .dout ( diffecc3_nz_1_0 )); | |
844 | mcu_readdp_dp_nand_macro__ports_2__stack_1l__width_1 u_diffecc3_nz ( .din0 ( diffecc3_nz_3_2 ), .din1 ( diffecc3_nz_1_0 ), .dout ( diffecc3_nz )); | |
845 | //and_macro U_diffecc3_zero ( stack = 1l , width = 1 , ports = 2 ) ( .din0 ( diffecc3_nz_3_2 ), .din1 ( diffecc3_nz_1_0 ), .dout ( diffecc3_zero )); | |
846 | mcu_readdp_dp_inv_macro__stack_1l__width_1 u_diffecc3_zero ( .din ( diffecc3_nz ), .dout ( diffecc3_zero )); | |
847 | ||
848 | // | |
849 | // Nibbles data correction. | |
850 | // | |
851 | mcu_nibcor_dp u_nibcor ( | |
852 | .diffecc2_nz ( diffecc2_nz ), | |
853 | .diff_ecc2 ( diff_ecc2[3:0] ), | |
854 | .diff_ecc1 ( diff_ecc1[3:0] ), | |
855 | .result ({ rddata_cor_result30[3:0], rddata_cor_result29[3:0], rddata_cor_result28[3:0], | |
856 | rddata_cor_result27[3:0], rddata_cor_result26[3:0], rddata_cor_result25[3:0], rddata_cor_result24[3:0], | |
857 | rddata_cor_result23[3:0], rddata_cor_result22[3:0], rddata_cor_result21[3:0], rddata_cor_result20[3:0], | |
858 | rddata_cor_result19[3:0], rddata_cor_result18[3:0], rddata_cor_result17[3:0], | |
859 | rddata_cor_result15[3:0], rddata_cor_result14[3:0], rddata_cor_result13[3:0], rddata_cor_result12[3:0], | |
860 | rddata_cor_result11[3:0], rddata_cor_result10[3:0], rddata_cor_result09[3:0], rddata_cor_result08[3:0], | |
861 | rddata_cor_result07[3:0], rddata_cor_result06[3:0], rddata_cor_result05[3:0], rddata_cor_result04[3:0], | |
862 | rddata_cor_result03[3:0], rddata_cor_result02[3:0] })); | |
863 | ||
864 | // | |
865 | // Adjust diff_ecc values in fail_mask_over mode | |
866 | // | |
867 | // assign diff_ecc0_in = (diff_ecc1 == 4'h0) & (diff_ecc2 == 4'h0) & ((diff_ecc3 == 4'h0) & ~l2if_dram_fail_over_mode | l2if_dram_fail_over_mode) ? 4'h0 : diff_ecc0; | |
868 | // assign diff_ecc1_in = (diff_ecc0 == 4'h0) & (diff_ecc2 == 4'h0) & ((diff_ecc3 == 4'h0) & ~l2if_dram_fail_over_mode | l2if_dram_fail_over_mode) ? 4'h0 : diff_ecc1; | |
869 | // assign diff_ecc2_in = (diff_ecc0 == 4'h0) & (diff_ecc1 == 4'h0) & ((diff_ecc3 == 4'h0) & ~l2if_dram_fail_over_mode | l2if_dram_fail_over_mode) ? 4'h0 : diff_ecc2; | |
870 | // assign diff_ecc3_in = (diff_ecc0 == 4'h0) & (diff_ecc1 == 4'h0) & (diff_ecc2 == 4'h0) ? 4'h0 : diff_ecc3; | |
871 | // | |
872 | // assign secc_err[0] = (diff_ecc1 == 4'h0) & (diff_ecc2 == 4'h0) & ((diff_ecc3 == 4'h0) & ~l2if_dram_fail_over_mode | l2if_dram_fail_over_mode) & (diff_ecc0 != 4'h0) ? 1'b1 : 1'b0; | |
873 | // assign secc_err[1] = (diff_ecc0 == 4'h0) & (diff_ecc2 == 4'h0) & ((diff_ecc3 == 4'h0) & ~l2if_dram_fail_over_mode | l2if_dram_fail_over_mode) & (diff_ecc1 != 4'h0) ? 1'b1 : 1'b0; | |
874 | // assign secc_err[2] = (diff_ecc0 == 4'h0) & (diff_ecc1 == 4'h0) & ((diff_ecc3 == 4'h0) & ~l2if_dram_fail_over_mode | l2if_dram_fail_over_mode) & (diff_ecc2 != 4'h0) ? 1'b1 : 1'b0; | |
875 | // assign secc_err[3] = (diff_ecc0 == 4'h0) & (diff_ecc1 == 4'h0) & (diff_ecc2 == 4'h0) & (diff_ecc3 != 4'h0) & ~l2if_dram_fail_over_mode ? 1'b1 : 1'b0; | |
876 | // | |
877 | mcu_readdp_dp_nor_macro__dnor_4x__ports_2__width_1 u_diffecc3_z_failmode_1 ( .din0 ( diffecc3_nz ), .din1 ( fail_over_mode ), .dout ( diffecc3_z_failmode_1 )); | |
878 | mcu_readdp_dp_nor_macro__dnor_16x__ports_2__width_1 u_diffecc3_z_failmode ( .din0 ( diffecc3_z_failmode_1 ), .din1 ( fail_over_mode ), .dout ( diffecc3_z_failmode )); | |
879 | ||
880 | mcu_readdp_dp_nand_macro__ports_2__stack_1l__width_1 u_diffecc_1_2_zero ( .din0 ( diffecc1_zero ), .din1 ( diffecc2_zero ), .dout ( diffecc_1_2_zero )); | |
881 | mcu_readdp_dp_nand_macro__ports_2__stack_1l__width_1 u_diffecc_0_2_zero ( .din0 ( diffecc0_zero ), .din1 ( diffecc2_zero ), .dout ( diffecc_0_2_zero )); | |
882 | mcu_readdp_dp_nand_macro__ports_2__stack_1l__width_1 u_diffecc_0_1_zero ( .din0 ( diffecc0_zero ), .din1 ( diffecc1_zero ), .dout ( diffecc_0_1_zero )); | |
883 | mcu_readdp_dp_nand_macro__ports_3__stack_1l__width_1 u_diffecc_0_1_2_zero ( .din0 ( diffecc0_zero ), .din1 ( diffecc1_zero ), .din2( diffecc2_zero ), .dout ( diffecc_0_1_2_zero )); | |
884 | ||
885 | mcu_readdp_dp_or_macro__ports_2__stack_1l__width_1 u_diffecc0_adj ( .din0 ( diffecc_1_2_zero ), .din1 ( diffecc3_z_failmode ), .dout ( diffecc0_adj )); | |
886 | mcu_readdp_dp_or_macro__ports_2__stack_1l__width_1 u_diffecc1_adj ( .din0 ( diffecc_0_2_zero ), .din1 ( diffecc3_z_failmode ), .dout ( diffecc1_adj )); | |
887 | mcu_readdp_dp_or_macro__ports_2__stack_1l__width_1 u_diffecc2_adj ( .din0 ( diffecc_0_1_zero ), .din1 ( diffecc3_z_failmode ), .dout ( diffecc2_adj )); | |
888 | ||
889 | mcu_readdp_dp_or_macro__ports_2__stack_1l__width_1 u_diffecc3_nz_failmode ( .din0 ( diffecc3_zero ), .din1 ( fail_over_mode ), .dout ( diffecc3_nz_failmode )); | |
890 | ||
891 | // | |
892 | // Adjusted diff_ecc values | |
893 | // | |
894 | mcu_readdp_dp_and_macro__dinv_32x__dnand_4x__ports_2__width_4 u_diff_ecc0_adj ( .din0 ( {4{ diffecc0_adj }} ), .din1 ( diff_ecc0[3:0] ), .dout ( diff_ecc0_adj[3:0] )); | |
895 | mcu_readdp_dp_and_macro__dinv_32x__dnand_4x__ports_2__width_4 u_diff_ecc1_adj ( .din0 ( {4{ diffecc1_adj }} ), .din1 ( diff_ecc1[3:0] ), .dout ( diff_ecc1_adj[3:0] )); | |
896 | mcu_readdp_dp_and_macro__dinv_32x__dnand_4x__ports_2__width_4 u_diff_ecc2_adj ( .din0 ( {4{ diffecc2_adj }} ), .din1 ( diff_ecc2[3:0] ), .dout ( diff_ecc2_adj[3:0] )); | |
897 | mcu_readdp_dp_and_macro__dinv_32x__dnand_4x__ports_2__width_4 u_diff_ecc3_adj ( .din0 ( {4{ diffecc_0_1_2_zero }}), .din1 ( diff_ecc3[3:0] ), .dout ( diff_ecc3_adj[3:0] )); | |
898 | ||
899 | // | |
900 | // SECC_ERR[3:0] | |
901 | // | |
902 | mcu_readdp_dp_nor_macro__ports_2__stack_1l__width_1 u_secc3_err ( .din0 ( diffecc_0_1_2_zero ), .din1 ( diffecc3_nz_failmode ), .dout ( secc_err[3] )); | |
903 | mcu_readdp_dp_nor_macro__ports_3__stack_1l__width_1 u_secc2_err ( .din0 ( diffecc_0_1_zero ), .din1 ( diffecc2_zero ), .din2 ( diffecc3_z_failmode ), .dout ( secc_err[2] )); | |
904 | mcu_readdp_dp_nor_macro__ports_3__stack_1l__width_1 u_secc1_err ( .din0 ( diffecc_0_2_zero ), .din1 ( diffecc1_zero ), .din2 ( diffecc3_z_failmode ), .dout ( secc_err[1] )); | |
905 | mcu_readdp_dp_nor_macro__ports_3__stack_1l__width_1 u_secc0_err ( .din0 ( diffecc_1_2_zero ), .din1 ( diffecc0_zero ), .din2 ( diffecc3_z_failmode ), .dout ( secc_err[0] )); | |
906 | ||
907 | // | |
908 | // diff_eccX_adj[3:0] == 4'b0 | |
909 | // diff_eccX_adj[3:0] != 4'b0 | |
910 | // | |
911 | ||
912 | mcu_readdp_dp_nor_macro__ports_2__stack_1l__width_1 u_diffecc0_adj_nz_3_2 ( .din0 ( diff_ecc0_adj[3] ), .din1 ( diff_ecc0_adj[2] ), .dout ( diffecc0_adj_nz_3_2 )); | |
913 | mcu_readdp_dp_nor_macro__ports_2__stack_1l__width_1 u_diffecc0_adj_nz_1_0 ( .din0 ( diff_ecc0_adj[1] ), .din1 ( diff_ecc0_adj[0] ), .dout ( diffecc0_adj_nz_1_0 )); | |
914 | mcu_readdp_dp_nand_macro__ports_2__stack_1l__width_1 u_diffecc0_adj_nz ( .din0 ( diffecc0_adj_nz_3_2 ), .din1 ( diffecc0_adj_nz_1_0 ), .dout ( diffecc0_adj_nz )); | |
915 | //and_macro U_diffecc0_adj_zero ( stack = 1l , width = 1 , ports = 2 ) ( .din0 ( diffecc0_adj_nz_3_2 ), .din1 ( diffecc0_adj_nz_1_0 ), .dout ( diffecc0_adj_zero )); | |
916 | mcu_readdp_dp_inv_macro__stack_1l__width_1 u_diffecc0_adj_zero ( .din ( diffecc0_adj_nz ), .dout ( diffecc0_adj_zero )); | |
917 | ||
918 | mcu_readdp_dp_nor_macro__ports_2__stack_1l__width_1 u_diffecc1_adj_nz_3_2 ( .din0 ( diff_ecc1_adj[3] ), .din1 ( diff_ecc1_adj[2] ), .dout ( diffecc1_adj_nz_3_2 )); | |
919 | mcu_readdp_dp_nor_macro__ports_2__stack_1l__width_1 u_diffecc1_adj_nz_1_0 ( .din0 ( diff_ecc1_adj[1] ), .din1 ( diff_ecc1_adj[0] ), .dout ( diffecc1_adj_nz_1_0 )); | |
920 | mcu_readdp_dp_nand_macro__ports_2__stack_1l__width_1 u_diffecc1_adj_nz ( .din0 ( diffecc1_adj_nz_3_2 ), .din1 ( diffecc1_adj_nz_1_0 ), .dout ( diffecc1_adj_nz )); | |
921 | //and_macro U_diffecc1_adj_zero ( stack = 1l , width = 1 , ports = 2 ) ( .din0 ( diffecc1_adj_nz_3_2 ), .din1 ( diffecc1_adj_nz_1_0 ), .dout ( diffecc1_adj_zero )); | |
922 | mcu_readdp_dp_inv_macro__stack_1l__width_1 u_diffecc1_adj_zero ( .din ( diffecc1_adj_nz ), .dout ( diffecc1_adj_zero )); | |
923 | ||
924 | mcu_readdp_dp_nor_macro__ports_2__stack_1l__width_1 u_diffecc2_adj_nz_3_2 ( .din0 ( diff_ecc2_adj[3] ), .din1 ( diff_ecc2_adj[2] ), .dout ( diffecc2_adj_nz_3_2 )); | |
925 | mcu_readdp_dp_nor_macro__ports_2__stack_1l__width_1 u_diffecc2_adj_nz_1_0 ( .din0 ( diff_ecc2_adj[1] ), .din1 ( diff_ecc2_adj[0] ), .dout ( diffecc2_adj_nz_1_0 )); | |
926 | mcu_readdp_dp_nand_macro__ports_2__stack_1l__width_1 u_diffecc2_adj_nz ( .din0 ( diffecc2_adj_nz_3_2 ), .din1 ( diffecc2_adj_nz_1_0 ), .dout ( diffecc2_adj_nz )); | |
927 | //and_macro U_diffecc2_adj_zero ( stack = 1l , width = 1 , ports = 2 ) ( .din0 ( diffecc2_adj_nz_3_2 ), .din1 ( diffecc2_adj_nz_1_0 ), .dout ( diffecc2_adj_zero )); | |
928 | mcu_readdp_dp_inv_macro__stack_1l__width_1 u_diffecc2_adj_zero ( .din ( diffecc2_adj_nz ), .dout ( diffecc2_adj_zero )); | |
929 | ||
930 | mcu_readdp_dp_nor_macro__ports_2__stack_1l__width_1 u_diffecc3_adj_nz_3_2 ( .din0 ( diff_ecc3_adj[3] ), .din1 ( diff_ecc3_adj[2] ), .dout ( diffecc3_adj_nz_3_2 )); | |
931 | mcu_readdp_dp_nor_macro__ports_2__stack_1l__width_1 u_diffecc3_adj_nz_1_0 ( .din0 ( diff_ecc3_adj[1] ), .din1 ( diff_ecc3_adj[0] ), .dout ( diffecc3_adj_nz_1_0 )); | |
932 | mcu_readdp_dp_nand_macro__ports_2__stack_1l__width_1 u_diffecc3_adj_nz ( .din0 ( diffecc3_adj_nz_3_2 ), .din1 ( diffecc3_adj_nz_1_0 ), .dout ( diffecc3_adj_nz )); | |
933 | //and_macro U_diffecc3_adj_zero ( stack = 1l , width = 1 , ports = 2 ) ( .din0 ( diffecc3_adj_nz_3_2 ), .din1 ( diffecc3_adj_nz_1_0 ), .dout ( diffecc3_adj_zero )); | |
934 | mcu_readdp_dp_inv_macro__stack_1l__width_1 u_diffecc3_adj_zero ( .din ( diffecc3_adj_nz ), .dout ( diffecc3_adj_zero )); | |
935 | ||
936 | // | |
937 | // Correcting nibbles 0-29 | |
938 | // | |
939 | mcu_readdp_dp_cmp_macro__width_4 u_byte00_err_1 ( .din0 ( diff_ecc0_adj[3:0] ), .din1 ( diff_ecc1_adj[3:0] ), .dout ( byte00_err_1 )); | |
940 | mcu_readdp_dp_cmp_macro__width_4 u_byte01_err_1 ( .din0 ( diff_ecc0_adj[3:0] ), .din1 ( rddata_cor_result02[3:0] ), .dout ( byte01_err_1 )); | |
941 | mcu_readdp_dp_cmp_macro__width_4 u_byte02_err_1 ( .din0 ( diff_ecc0_adj[3:0] ), .din1 ( rddata_cor_result03[3:0] ), .dout ( byte02_err_1 )); | |
942 | mcu_readdp_dp_cmp_macro__width_4 u_byte03_err_1 ( .din0 ( diff_ecc0_adj[3:0] ), .din1 ( rddata_cor_result04[3:0] ), .dout ( byte03_err_1 )); | |
943 | mcu_readdp_dp_cmp_macro__width_4 u_byte04_err_1 ( .din0 ( diff_ecc0_adj[3:0] ), .din1 ( rddata_cor_result05[3:0] ), .dout ( byte04_err_1 )); | |
944 | mcu_readdp_dp_cmp_macro__width_4 u_byte05_err_1 ( .din0 ( diff_ecc0_adj[3:0] ), .din1 ( rddata_cor_result06[3:0] ), .dout ( byte05_err_1 )); | |
945 | mcu_readdp_dp_cmp_macro__width_4 u_byte06_err_1 ( .din0 ( diff_ecc0_adj[3:0] ), .din1 ( rddata_cor_result07[3:0] ), .dout ( byte06_err_1 )); | |
946 | mcu_readdp_dp_cmp_macro__width_4 u_byte07_err_1 ( .din0 ( diff_ecc0_adj[3:0] ), .din1 ( rddata_cor_result08[3:0] ), .dout ( byte07_err_1 )); | |
947 | mcu_readdp_dp_cmp_macro__width_4 u_byte08_err_1 ( .din0 ( diff_ecc0_adj[3:0] ), .din1 ( rddata_cor_result09[3:0] ), .dout ( byte08_err_1 )); | |
948 | mcu_readdp_dp_cmp_macro__width_4 u_byte09_err_1 ( .din0 ( diff_ecc0_adj[3:0] ), .din1 ( rddata_cor_result10[3:0] ), .dout ( byte09_err_1 )); | |
949 | mcu_readdp_dp_cmp_macro__width_4 u_byte10_err_1 ( .din0 ( diff_ecc0_adj[3:0] ), .din1 ( rddata_cor_result11[3:0] ), .dout ( byte10_err_1 )); | |
950 | mcu_readdp_dp_cmp_macro__width_4 u_byte11_err_1 ( .din0 ( diff_ecc0_adj[3:0] ), .din1 ( rddata_cor_result12[3:0] ), .dout ( byte11_err_1 )); | |
951 | mcu_readdp_dp_cmp_macro__width_4 u_byte12_err_1 ( .din0 ( diff_ecc0_adj[3:0] ), .din1 ( rddata_cor_result13[3:0] ), .dout ( byte12_err_1 )); | |
952 | mcu_readdp_dp_cmp_macro__width_4 u_byte13_err_1 ( .din0 ( diff_ecc0_adj[3:0] ), .din1 ( rddata_cor_result14[3:0] ), .dout ( byte13_err_1 )); | |
953 | mcu_readdp_dp_cmp_macro__width_4 u_byte14_err_1 ( .din0 ( diff_ecc0_adj[3:0] ), .din1 ( rddata_cor_result15[3:0] ), .dout ( byte14_err_1 )); | |
954 | mcu_readdp_dp_cmp_macro__width_4 u_byte15_err_1 ( .din0 ( diff_ecc0_adj[3:0] ), .din1 ( diff_ecc2_adj[3:0] ), .dout ( byte15_err_1 )); | |
955 | mcu_readdp_dp_cmp_macro__width_4 u_byte16_err_1 ( .din0 ( diff_ecc0_adj[3:0] ), .din1 ( rddata_cor_result17[3:0] ), .dout ( byte16_err_1 )); | |
956 | mcu_readdp_dp_cmp_macro__width_4 u_byte17_err_1 ( .din0 ( diff_ecc0_adj[3:0] ), .din1 ( rddata_cor_result18[3:0] ), .dout ( byte17_err_1 )); | |
957 | mcu_readdp_dp_cmp_macro__width_4 u_byte18_err_1 ( .din0 ( diff_ecc0_adj[3:0] ), .din1 ( rddata_cor_result19[3:0] ), .dout ( byte18_err_1 )); | |
958 | mcu_readdp_dp_cmp_macro__width_4 u_byte19_err_1 ( .din0 ( diff_ecc0_adj[3:0] ), .din1 ( rddata_cor_result20[3:0] ), .dout ( byte19_err_1 )); | |
959 | mcu_readdp_dp_cmp_macro__width_4 u_byte20_err_1 ( .din0 ( diff_ecc0_adj[3:0] ), .din1 ( rddata_cor_result21[3:0] ), .dout ( byte20_err_1 )); | |
960 | mcu_readdp_dp_cmp_macro__width_4 u_byte21_err_1 ( .din0 ( diff_ecc0_adj[3:0] ), .din1 ( rddata_cor_result22[3:0] ), .dout ( byte21_err_1 )); | |
961 | mcu_readdp_dp_cmp_macro__width_4 u_byte22_err_1 ( .din0 ( diff_ecc0_adj[3:0] ), .din1 ( rddata_cor_result23[3:0] ), .dout ( byte22_err_1 )); | |
962 | mcu_readdp_dp_cmp_macro__width_4 u_byte23_err_1 ( .din0 ( diff_ecc0_adj[3:0] ), .din1 ( rddata_cor_result24[3:0] ), .dout ( byte23_err_1 )); | |
963 | mcu_readdp_dp_cmp_macro__width_4 u_byte24_err_1 ( .din0 ( diff_ecc0_adj[3:0] ), .din1 ( rddata_cor_result25[3:0] ), .dout ( byte24_err_1 )); | |
964 | mcu_readdp_dp_cmp_macro__width_4 u_byte25_err_1 ( .din0 ( diff_ecc0_adj[3:0] ), .din1 ( rddata_cor_result26[3:0] ), .dout ( byte25_err_1 )); | |
965 | mcu_readdp_dp_cmp_macro__width_4 u_byte26_err_1 ( .din0 ( diff_ecc0_adj[3:0] ), .din1 ( rddata_cor_result27[3:0] ), .dout ( byte26_err_1 )); | |
966 | mcu_readdp_dp_cmp_macro__width_4 u_byte27_err_1 ( .din0 ( diff_ecc0_adj[3:0] ), .din1 ( rddata_cor_result28[3:0] ), .dout ( byte27_err_1 )); | |
967 | mcu_readdp_dp_cmp_macro__width_4 u_byte28_err_1 ( .din0 ( diff_ecc0_adj[3:0] ), .din1 ( rddata_cor_result29[3:0] ), .dout ( byte28_err_1 )); | |
968 | mcu_readdp_dp_cmp_macro__width_4 u_byte29_err_1 ( .din0 ( diff_ecc0_adj[3:0] ), .din1 ( rddata_cor_result30[3:0] ), .dout ( byte29_err_1 )); | |
969 | mcu_readdp_dp_cmp_macro__width_4 u_byte3031_err_1 ( .din0 ( diff_ecc1_adj[3:0] ), .din1 ( diff_ecc2_adj[3:0] ), .dout ( byte3031_err_1 )); | |
970 | ||
971 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_errpos_0to14 ( .din0 ( diffecc1_adj_nz ), .din1 ( diffecc2_adj_zero ), .dout ( errpos_0to14 )); | |
972 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte00_err ( .din0 ( errpos_0to14 ), .din1 ( byte00_err_1 ), .dout ( byte00_err )); | |
973 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte01_err ( .din0 ( errpos_0to14 ), .din1 ( byte01_err_1 ), .dout ( byte01_err )); | |
974 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte02_err ( .din0 ( errpos_0to14 ), .din1 ( byte02_err_1 ), .dout ( byte02_err )); | |
975 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte03_err ( .din0 ( errpos_0to14 ), .din1 ( byte03_err_1 ), .dout ( byte03_err )); | |
976 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte04_err ( .din0 ( errpos_0to14 ), .din1 ( byte04_err_1 ), .dout ( byte04_err )); | |
977 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte05_err ( .din0 ( errpos_0to14 ), .din1 ( byte05_err_1 ), .dout ( byte05_err )); | |
978 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte06_err ( .din0 ( errpos_0to14 ), .din1 ( byte06_err_1 ), .dout ( byte06_err )); | |
979 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte07_err ( .din0 ( errpos_0to14 ), .din1 ( byte07_err_1 ), .dout ( byte07_err )); | |
980 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte08_err ( .din0 ( errpos_0to14 ), .din1 ( byte08_err_1 ), .dout ( byte08_err )); | |
981 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte09_err ( .din0 ( errpos_0to14 ), .din1 ( byte09_err_1 ), .dout ( byte09_err )); | |
982 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte10_err ( .din0 ( errpos_0to14 ), .din1 ( byte10_err_1 ), .dout ( byte10_err )); | |
983 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte11_err ( .din0 ( errpos_0to14 ), .din1 ( byte11_err_1 ), .dout ( byte11_err )); | |
984 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte12_err ( .din0 ( errpos_0to14 ), .din1 ( byte12_err_1 ), .dout ( byte12_err )); | |
985 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte13_err ( .din0 ( errpos_0to14 ), .din1 ( byte13_err_1 ), .dout ( byte13_err )); | |
986 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte14_err ( .din0 ( errpos_0to14 ), .din1 ( byte14_err_1 ), .dout ( byte14_err )); | |
987 | ||
988 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_errpos_15to29 ( .din0 ( diffecc1_adj_zero ), .din1 ( diffecc2_adj_nz ), .dout ( errpos_15to29 )); | |
989 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte15_err ( .din0 ( errpos_15to29 ), .din1 ( byte15_err_1 ), .dout ( byte15_err )); | |
990 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte16_err ( .din0 ( errpos_15to29 ), .din1 ( byte16_err_1 ), .dout ( byte16_err )); | |
991 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte17_err ( .din0 ( errpos_15to29 ), .din1 ( byte17_err_1 ), .dout ( byte17_err )); | |
992 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte18_err ( .din0 ( errpos_15to29 ), .din1 ( byte18_err_1 ), .dout ( byte18_err )); | |
993 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte19_err ( .din0 ( errpos_15to29 ), .din1 ( byte19_err_1 ), .dout ( byte19_err )); | |
994 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte20_err ( .din0 ( errpos_15to29 ), .din1 ( byte20_err_1 ), .dout ( byte20_err )); | |
995 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte21_err ( .din0 ( errpos_15to29 ), .din1 ( byte21_err_1 ), .dout ( byte21_err )); | |
996 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte22_err ( .din0 ( errpos_15to29 ), .din1 ( byte22_err_1 ), .dout ( byte22_err )); | |
997 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte23_err ( .din0 ( errpos_15to29 ), .din1 ( byte23_err_1 ), .dout ( byte23_err )); | |
998 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte24_err ( .din0 ( errpos_15to29 ), .din1 ( byte24_err_1 ), .dout ( byte24_err )); | |
999 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte25_err ( .din0 ( errpos_15to29 ), .din1 ( byte25_err_1 ), .dout ( byte25_err )); | |
1000 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte26_err ( .din0 ( errpos_15to29 ), .din1 ( byte26_err_1 ), .dout ( byte26_err )); | |
1001 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte27_err ( .din0 ( errpos_15to29 ), .din1 ( byte27_err_1 ), .dout ( byte27_err )); | |
1002 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte28_err ( .din0 ( errpos_15to29 ), .din1 ( byte28_err_1 ), .dout ( byte28_err )); | |
1003 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte29_err ( .din0 ( errpos_15to29 ), .din1 ( byte29_err_1 ), .dout ( byte29_err )); | |
1004 | ||
1005 | mcu_readdp_dp_and_macro__ports_3__stack_1l__width_1 u_byte30_err ( .din0 ( byte3031_err_1 ), .din1 ( diffecc0_adj_zero ), .din2 ( diffecc1_adj_nz ), .dout ( byte30_err )); | |
1006 | mcu_readdp_dp_and_macro__ports_3__stack_1l__width_1 u_byte31_err ( .din0 ( byte3031_err_1 ), .din1 ( byte00_err_1 ), .din2 ( diffecc0_adj_nz ), .dout ( byte31_err )); | |
1007 | ||
1008 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte00_1 ( .din0 ( {4{ byte00_err }} ), .din1 ( diff_ecc1_adj[3:0] ), .dout ( outbyte00_1[3:0] )); | |
1009 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte01_1 ( .din0 ( {4{ byte01_err }} ), .din1 ( diff_ecc1_adj[3:0] ), .dout ( outbyte01_1[3:0] )); | |
1010 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte02_1 ( .din0 ( {4{ byte02_err }} ), .din1 ( diff_ecc1_adj[3:0] ), .dout ( outbyte02_1[3:0] )); | |
1011 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte03_1 ( .din0 ( {4{ byte03_err }} ), .din1 ( diff_ecc1_adj[3:0] ), .dout ( outbyte03_1[3:0] )); | |
1012 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte04_1 ( .din0 ( {4{ byte04_err }} ), .din1 ( diff_ecc1_adj[3:0] ), .dout ( outbyte04_1[3:0] )); | |
1013 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte05_1 ( .din0 ( {4{ byte05_err }} ), .din1 ( diff_ecc1_adj[3:0] ), .dout ( outbyte05_1[3:0] )); | |
1014 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte06_1 ( .din0 ( {4{ byte06_err }} ), .din1 ( diff_ecc1_adj[3:0] ), .dout ( outbyte06_1[3:0] )); | |
1015 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte07_1 ( .din0 ( {4{ byte07_err }} ), .din1 ( diff_ecc1_adj[3:0] ), .dout ( outbyte07_1[3:0] )); | |
1016 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte08_1 ( .din0 ( {4{ byte08_err }} ), .din1 ( diff_ecc1_adj[3:0] ), .dout ( outbyte08_1[3:0] )); | |
1017 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte09_1 ( .din0 ( {4{ byte09_err }} ), .din1 ( diff_ecc1_adj[3:0] ), .dout ( outbyte09_1[3:0] )); | |
1018 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte10_1 ( .din0 ( {4{ byte10_err }} ), .din1 ( diff_ecc1_adj[3:0] ), .dout ( outbyte10_1[3:0] )); | |
1019 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte11_1 ( .din0 ( {4{ byte11_err }} ), .din1 ( diff_ecc1_adj[3:0] ), .dout ( outbyte11_1[3:0] )); | |
1020 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte12_1 ( .din0 ( {4{ byte12_err }} ), .din1 ( diff_ecc1_adj[3:0] ), .dout ( outbyte12_1[3:0] )); | |
1021 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte13_1 ( .din0 ( {4{ byte13_err }} ), .din1 ( diff_ecc1_adj[3:0] ), .dout ( outbyte13_1[3:0] )); | |
1022 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte14_1 ( .din0 ( {4{ byte14_err }} ), .din1 ( diff_ecc1_adj[3:0] ), .dout ( outbyte14_1[3:0] )); | |
1023 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte15_1 ( .din0 ( {4{ byte15_err }} ), .din1 ( diff_ecc2_adj[3:0] ), .dout ( outbyte15_1[3:0] )); | |
1024 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte16_1 ( .din0 ( {4{ byte16_err }} ), .din1 ( diff_ecc2_adj[3:0] ), .dout ( outbyte16_1[3:0] )); | |
1025 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte17_1 ( .din0 ( {4{ byte17_err }} ), .din1 ( diff_ecc2_adj[3:0] ), .dout ( outbyte17_1[3:0] )); | |
1026 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte18_1 ( .din0 ( {4{ byte18_err }} ), .din1 ( diff_ecc2_adj[3:0] ), .dout ( outbyte18_1[3:0] )); | |
1027 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte19_1 ( .din0 ( {4{ byte19_err }} ), .din1 ( diff_ecc2_adj[3:0] ), .dout ( outbyte19_1[3:0] )); | |
1028 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte20_1 ( .din0 ( {4{ byte20_err }} ), .din1 ( diff_ecc2_adj[3:0] ), .dout ( outbyte20_1[3:0] )); | |
1029 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte21_1 ( .din0 ( {4{ byte21_err }} ), .din1 ( diff_ecc2_adj[3:0] ), .dout ( outbyte21_1[3:0] )); | |
1030 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte22_1 ( .din0 ( {4{ byte22_err }} ), .din1 ( diff_ecc2_adj[3:0] ), .dout ( outbyte22_1[3:0] )); | |
1031 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte23_1 ( .din0 ( {4{ byte23_err }} ), .din1 ( diff_ecc2_adj[3:0] ), .dout ( outbyte23_1[3:0] )); | |
1032 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte24_1 ( .din0 ( {4{ byte24_err }} ), .din1 ( diff_ecc2_adj[3:0] ), .dout ( outbyte24_1[3:0] )); | |
1033 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte25_1 ( .din0 ( {4{ byte25_err }} ), .din1 ( diff_ecc2_adj[3:0] ), .dout ( outbyte25_1[3:0] )); | |
1034 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte26_1 ( .din0 ( {4{ byte26_err }} ), .din1 ( diff_ecc2_adj[3:0] ), .dout ( outbyte26_1[3:0] )); | |
1035 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte27_1 ( .din0 ( {4{ byte27_err }} ), .din1 ( diff_ecc2_adj[3:0] ), .dout ( outbyte27_1[3:0] )); | |
1036 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte28_1 ( .din0 ( {4{ byte28_err }} ), .din1 ( diff_ecc2_adj[3:0] ), .dout ( outbyte28_1[3:0] )); | |
1037 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte29_1 ( .din0 ( {4{ byte29_err }} ), .din1 ( diff_ecc2_adj[3:0] ), .dout ( outbyte29_1[3:0] )); | |
1038 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte30_1 ( .din0 ( {4{ byte30_err }} ), .din1 ( diff_ecc2_adj[3:0] ), .dout ( outbyte30_1[3:0] )); | |
1039 | mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 u_outbyte31_1 ( .din0 ( {4{ byte31_err }} ), .din1 ( diff_ecc2_adj[3:0] ), .dout ( outbyte31_1[3:0] )); | |
1040 | ||
1041 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte00 ( .din0 ( outbyte00_1[3:0] ), .din1 ( rddata00_in[3:0] ), .dout ( outbyte00[3:0] )); | |
1042 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte01 ( .din0 ( outbyte01_1[3:0] ), .din1 ( rddata01_in[3:0] ), .dout ( outbyte01[3:0] )); | |
1043 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte02 ( .din0 ( outbyte02_1[3:0] ), .din1 ( rddata02_in[3:0] ), .dout ( outbyte02[3:0] )); | |
1044 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte03 ( .din0 ( outbyte03_1[3:0] ), .din1 ( rddata03_in[3:0] ), .dout ( outbyte03[3:0] )); | |
1045 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte04 ( .din0 ( outbyte04_1[3:0] ), .din1 ( rddata04_in[3:0] ), .dout ( outbyte04[3:0] )); | |
1046 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte05 ( .din0 ( outbyte05_1[3:0] ), .din1 ( rddata05_in[3:0] ), .dout ( outbyte05[3:0] )); | |
1047 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte06 ( .din0 ( outbyte06_1[3:0] ), .din1 ( rddata06_in[3:0] ), .dout ( outbyte06[3:0] )); | |
1048 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte07 ( .din0 ( outbyte07_1[3:0] ), .din1 ( rddata07_in[3:0] ), .dout ( outbyte07[3:0] )); | |
1049 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte08 ( .din0 ( outbyte08_1[3:0] ), .din1 ( rddata08_in[3:0] ), .dout ( outbyte08[3:0] )); | |
1050 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte09 ( .din0 ( outbyte09_1[3:0] ), .din1 ( rddata09_in[3:0] ), .dout ( outbyte09[3:0] )); | |
1051 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte10 ( .din0 ( outbyte10_1[3:0] ), .din1 ( rddata10_in[3:0] ), .dout ( outbyte10[3:0] )); | |
1052 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte11 ( .din0 ( outbyte11_1[3:0] ), .din1 ( rddata11_in[3:0] ), .dout ( outbyte11[3:0] )); | |
1053 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte12 ( .din0 ( outbyte12_1[3:0] ), .din1 ( rddata12_in[3:0] ), .dout ( outbyte12[3:0] )); | |
1054 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte13 ( .din0 ( outbyte13_1[3:0] ), .din1 ( rddata13_in[3:0] ), .dout ( outbyte13[3:0] )); | |
1055 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte14 ( .din0 ( outbyte14_1[3:0] ), .din1 ( rddata14_in[3:0] ), .dout ( outbyte14[3:0] )); | |
1056 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte15 ( .din0 ( outbyte15_1[3:0] ), .din1 ( rddata15_in[3:0] ), .dout ( outbyte15[3:0] )); | |
1057 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte16 ( .din0 ( outbyte16_1[3:0] ), .din1 ( rddata16_in[3:0] ), .dout ( outbyte16[3:0] )); | |
1058 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte17 ( .din0 ( outbyte17_1[3:0] ), .din1 ( rddata17_in[3:0] ), .dout ( outbyte17[3:0] )); | |
1059 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte18 ( .din0 ( outbyte18_1[3:0] ), .din1 ( rddata18_in[3:0] ), .dout ( outbyte18[3:0] )); | |
1060 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte19 ( .din0 ( outbyte19_1[3:0] ), .din1 ( rddata19_in[3:0] ), .dout ( outbyte19[3:0] )); | |
1061 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte20 ( .din0 ( outbyte20_1[3:0] ), .din1 ( rddata20_in[3:0] ), .dout ( outbyte20[3:0] )); | |
1062 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte21 ( .din0 ( outbyte21_1[3:0] ), .din1 ( rddata21_in[3:0] ), .dout ( outbyte21[3:0] )); | |
1063 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte22 ( .din0 ( outbyte22_1[3:0] ), .din1 ( rddata22_in[3:0] ), .dout ( outbyte22[3:0] )); | |
1064 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte23 ( .din0 ( outbyte23_1[3:0] ), .din1 ( rddata23_in[3:0] ), .dout ( outbyte23[3:0] )); | |
1065 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte24 ( .din0 ( outbyte24_1[3:0] ), .din1 ( rddata24_in[3:0] ), .dout ( outbyte24[3:0] )); | |
1066 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte25 ( .din0 ( outbyte25_1[3:0] ), .din1 ( rddata25_in[3:0] ), .dout ( outbyte25[3:0] )); | |
1067 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte26 ( .din0 ( outbyte26_1[3:0] ), .din1 ( rddata26_in[3:0] ), .dout ( outbyte26[3:0] )); | |
1068 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte27 ( .din0 ( outbyte27_1[3:0] ), .din1 ( rddata27_in[3:0] ), .dout ( outbyte27[3:0] )); | |
1069 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte28 ( .din0 ( outbyte28_1[3:0] ), .din1 ( rddata28_in[3:0] ), .dout ( outbyte28[3:0] )); | |
1070 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte29 ( .din0 ( outbyte29_1[3:0] ), .din1 ( rddata29_in[3:0] ), .dout ( outbyte29[3:0] )); | |
1071 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte30 ( .din0 ( outbyte30_1[3:0] ), .din1 ( rddata30_in[3:0] ), .dout ( outbyte30[3:0] )); | |
1072 | mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 u_outbyte31 ( .din0 ( outbyte31_1[3:0] ), .din1 ( rddata31_in[3:0] ), .dout ( outbyte31[3:0] )); | |
1073 | ||
1074 | // MECC detection | |
1075 | ||
1076 | mcu_readdp_dp_cmp_macro__width_4 u_byte00_err_mecc_1 ( .din0 ( diff_ecc3_adj[3:0] ), .din1 ( diff_ecc1_adj[3:0] ), .dout ( byte00_err_mecc_1 )); | |
1077 | mcu_readdp_dp_cmp_macro__width_4 u_byte08_23_err_mecc_1 ( .din0 ( diff_ecc3_adj[3:0] ), .din1 ( rddata_cor_result02[3:0] ), .dout ( byte08_23_err_mecc_1 )); | |
1078 | mcu_readdp_dp_cmp_macro__width_4 u_byte13_28_err_mecc_1 ( .din0 ( diff_ecc3_adj[3:0] ), .din1 ( rddata_cor_result03[3:0] ), .dout ( byte13_28_err_mecc_1 )); | |
1079 | mcu_readdp_dp_cmp_macro__width_4 u_byte12_27_err_mecc_1 ( .din0 ( diff_ecc3_adj[3:0] ), .din1 ( rddata_cor_result04[3:0] ), .dout ( byte12_27_err_mecc_1 )); | |
1080 | mcu_readdp_dp_cmp_macro__width_4 u_byte10_25_err_mecc_1 ( .din0 ( diff_ecc3_adj[3:0] ), .din1 ( rddata_cor_result05[3:0] ), .dout ( byte10_25_err_mecc_1 )); | |
1081 | mcu_readdp_dp_cmp_macro__width_4 u_byte06_21_err_mecc_1 ( .din0 ( diff_ecc3_adj[3:0] ), .din1 ( rddata_cor_result06[3:0] ), .dout ( byte06_21_err_mecc_1 )); | |
1082 | mcu_readdp_dp_cmp_macro__width_4 u_byte05_20_err_mecc_1 ( .din0 ( diff_ecc3_adj[3:0] ), .din1 ( rddata_cor_result07[3:0] ), .dout ( byte05_20_err_mecc_1 )); | |
1083 | mcu_readdp_dp_cmp_macro__width_4 u_byte14_29_err_mecc_1 ( .din0 ( diff_ecc3_adj[3:0] ), .din1 ( rddata_cor_result08[3:0] ), .dout ( byte14_29_err_mecc_1 )); | |
1084 | mcu_readdp_dp_cmp_macro__width_4 u_byte01_16_err_mecc_1 ( .din0 ( diff_ecc3_adj[3:0] ), .din1 ( rddata_cor_result09[3:0] ), .dout ( byte01_16_err_mecc_1 )); | |
1085 | mcu_readdp_dp_cmp_macro__width_4 u_byte11_26_err_mecc_1 ( .din0 ( diff_ecc3_adj[3:0] ), .din1 ( rddata_cor_result10[3:0] ), .dout ( byte11_26_err_mecc_1 )); | |
1086 | mcu_readdp_dp_cmp_macro__width_4 u_byte04_19_err_mecc_1 ( .din0 ( diff_ecc3_adj[3:0] ), .din1 ( rddata_cor_result11[3:0] ), .dout ( byte04_19_err_mecc_1 )); | |
1087 | mcu_readdp_dp_cmp_macro__width_4 u_byte09_24_err_mecc_1 ( .din0 ( diff_ecc3_adj[3:0] ), .din1 ( rddata_cor_result12[3:0] ), .dout ( byte09_24_err_mecc_1 )); | |
1088 | mcu_readdp_dp_cmp_macro__width_4 u_byte03_18_err_mecc_1 ( .din0 ( diff_ecc3_adj[3:0] ), .din1 ( rddata_cor_result13[3:0] ), .dout ( byte03_18_err_mecc_1 )); | |
1089 | mcu_readdp_dp_cmp_macro__width_4 u_byte02_17_err_mecc_1 ( .din0 ( diff_ecc3_adj[3:0] ), .din1 ( rddata_cor_result14[3:0] ), .dout ( byte02_17_err_mecc_1 )); | |
1090 | mcu_readdp_dp_cmp_macro__width_4 u_byte07_22_err_mecc_1 ( .din0 ( diff_ecc3_adj[3:0] ), .din1 ( rddata_cor_result15[3:0] ), .dout ( byte07_22_err_mecc_1 )); | |
1091 | mcu_readdp_dp_cmp_macro__width_4 u_byte15_err_mecc_1 ( .din0 ( diff_ecc3_adj[3:0] ), .din1 ( diff_ecc2_adj[3:0] ), .dout ( byte15_err_mecc_1 )); | |
1092 | ||
1093 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_bytexx_err_mecc_2 ( .din0 ( diffecc1_adj_nz ), .din1 ( diffecc2_adj_zero ), .dout ( bytexx_err_mecc_2 )); | |
1094 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byteyy_err_mecc_2 ( .din0 ( diffecc1_adj_zero ), .din1 ( diffecc2_adj_nz ), .dout ( byteyy_err_mecc_2 )); | |
1095 | ||
1096 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte00_err_mecc ( .din0 ( bytexx_err_mecc_2 ), .din1 ( byte00_err_mecc_1 ), .dout ( byte00_err_mecc )); | |
1097 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte01_err_mecc ( .din0 ( bytexx_err_mecc_2 ), .din1 ( byte01_16_err_mecc_1 ), .dout ( byte01_err_mecc )); | |
1098 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte02_err_mecc ( .din0 ( bytexx_err_mecc_2 ), .din1 ( byte02_17_err_mecc_1 ), .dout ( byte02_err_mecc )); | |
1099 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte03_err_mecc ( .din0 ( bytexx_err_mecc_2 ), .din1 ( byte03_18_err_mecc_1 ), .dout ( byte03_err_mecc )); | |
1100 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte04_err_mecc ( .din0 ( bytexx_err_mecc_2 ), .din1 ( byte04_19_err_mecc_1 ), .dout ( byte04_err_mecc )); | |
1101 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte05_err_mecc ( .din0 ( bytexx_err_mecc_2 ), .din1 ( byte05_20_err_mecc_1 ), .dout ( byte05_err_mecc )); | |
1102 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte06_err_mecc ( .din0 ( bytexx_err_mecc_2 ), .din1 ( byte06_21_err_mecc_1 ), .dout ( byte06_err_mecc )); | |
1103 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte07_err_mecc ( .din0 ( bytexx_err_mecc_2 ), .din1 ( byte07_22_err_mecc_1 ), .dout ( byte07_err_mecc )); | |
1104 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte08_err_mecc ( .din0 ( bytexx_err_mecc_2 ), .din1 ( byte08_23_err_mecc_1 ), .dout ( byte08_err_mecc )); | |
1105 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte09_err_mecc ( .din0 ( bytexx_err_mecc_2 ), .din1 ( byte09_24_err_mecc_1 ), .dout ( byte09_err_mecc )); | |
1106 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte10_err_mecc ( .din0 ( bytexx_err_mecc_2 ), .din1 ( byte10_25_err_mecc_1 ), .dout ( byte10_err_mecc )); | |
1107 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte11_err_mecc ( .din0 ( bytexx_err_mecc_2 ), .din1 ( byte11_26_err_mecc_1 ), .dout ( byte11_err_mecc )); | |
1108 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte12_err_mecc ( .din0 ( bytexx_err_mecc_2 ), .din1 ( byte12_27_err_mecc_1 ), .dout ( byte12_err_mecc )); | |
1109 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte13_err_mecc ( .din0 ( bytexx_err_mecc_2 ), .din1 ( byte13_28_err_mecc_1 ), .dout ( byte13_err_mecc )); | |
1110 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte14_err_mecc ( .din0 ( bytexx_err_mecc_2 ), .din1 ( byte14_29_err_mecc_1 ), .dout ( byte14_err_mecc )); | |
1111 | ||
1112 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte15_err_mecc ( .din0 ( byteyy_err_mecc_2 ), .din1 ( byte15_err_mecc_1 ), .dout ( byte15_err_mecc )); | |
1113 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte16_err_mecc ( .din0 ( byteyy_err_mecc_2 ), .din1 ( byte01_16_err_mecc_1 ), .dout ( byte16_err_mecc )); | |
1114 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte17_err_mecc ( .din0 ( byteyy_err_mecc_2 ), .din1 ( byte02_17_err_mecc_1 ), .dout ( byte17_err_mecc )); | |
1115 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte18_err_mecc ( .din0 ( byteyy_err_mecc_2 ), .din1 ( byte03_18_err_mecc_1 ), .dout ( byte18_err_mecc )); | |
1116 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte19_err_mecc ( .din0 ( byteyy_err_mecc_2 ), .din1 ( byte04_19_err_mecc_1 ), .dout ( byte19_err_mecc )); | |
1117 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte20_err_mecc ( .din0 ( byteyy_err_mecc_2 ), .din1 ( byte05_20_err_mecc_1 ), .dout ( byte20_err_mecc )); | |
1118 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte21_err_mecc ( .din0 ( byteyy_err_mecc_2 ), .din1 ( byte06_21_err_mecc_1 ), .dout ( byte21_err_mecc )); | |
1119 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte22_err_mecc ( .din0 ( byteyy_err_mecc_2 ), .din1 ( byte07_22_err_mecc_1 ), .dout ( byte22_err_mecc )); | |
1120 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte23_err_mecc ( .din0 ( byteyy_err_mecc_2 ), .din1 ( byte08_23_err_mecc_1 ), .dout ( byte23_err_mecc )); | |
1121 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte24_err_mecc ( .din0 ( byteyy_err_mecc_2 ), .din1 ( byte09_24_err_mecc_1 ), .dout ( byte24_err_mecc )); | |
1122 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte25_err_mecc ( .din0 ( byteyy_err_mecc_2 ), .din1 ( byte10_25_err_mecc_1 ), .dout ( byte25_err_mecc )); | |
1123 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte26_err_mecc ( .din0 ( byteyy_err_mecc_2 ), .din1 ( byte11_26_err_mecc_1 ), .dout ( byte26_err_mecc )); | |
1124 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte27_err_mecc ( .din0 ( byteyy_err_mecc_2 ), .din1 ( byte12_27_err_mecc_1 ), .dout ( byte27_err_mecc )); | |
1125 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte28_err_mecc ( .din0 ( byteyy_err_mecc_2 ), .din1 ( byte13_28_err_mecc_1 ), .dout ( byte28_err_mecc )); | |
1126 | mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 u_byte29_err_mecc ( .din0 ( byteyy_err_mecc_2 ), .din1 ( byte14_29_err_mecc_1 ), .dout ( byte29_err_mecc )); | |
1127 | ||
1128 | assign ecc_loc[35:0] = { secc_err[3:0], | |
1129 | byte31_err, byte30_err, byte29_err, byte28_err, byte27_err, byte26_err, byte25_err, byte24_err, | |
1130 | byte23_err, byte22_err, byte21_err, byte20_err, byte19_err, byte18_err, byte17_err, byte16_err, | |
1131 | byte15_err, byte14_err, byte13_err, byte12_err, byte11_err, byte10_err, byte09_err, byte08_err, | |
1132 | byte07_err, byte06_err, byte05_err, byte04_err, byte03_err, byte02_err, byte01_err, byte00_err }; | |
1133 | ||
1134 | assign err_byte_0_14_loc[14:0] = { byte14_err_mecc, byte13_err_mecc, byte12_err_mecc, byte11_err_mecc, byte10_err_mecc, | |
1135 | byte09_err_mecc, byte08_err_mecc, byte07_err_mecc, byte06_err_mecc, byte05_err_mecc, | |
1136 | byte04_err_mecc, byte03_err_mecc, byte02_err_mecc, byte01_err_mecc, byte00_err_mecc }; | |
1137 | ||
1138 | assign err_byte_15_29_loc[14:0] = { byte29_err_mecc, byte28_err_mecc, byte27_err_mecc, byte26_err_mecc, byte25_err_mecc, | |
1139 | byte24_err_mecc, byte23_err_mecc, byte22_err_mecc, byte21_err_mecc, byte20_err_mecc, | |
1140 | byte19_err_mecc, byte18_err_mecc, byte17_err_mecc, byte16_err_mecc, byte15_err_mecc }; | |
1141 | ||
1142 | ||
1143 | // | |
1144 | // N1 dram_ecc_cor line_409 | |
1145 | // | |
1146 | // assign ecc_multi_err = ~l2if_dram_fail_over_mode & ( | |
1147 | // ((diff_ecc0_d1 == 4'h0) & (diff_ecc1_d1 == 4'h0) & (diff_ecc2_d1 != 4'h0) & (diff_ecc3_d1 != 4'h0)) | | |
1148 | // ((diff_ecc0_d1 != 4'h0) & (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (diff_ecc3_d1 == 4'h0)) | | |
1149 | // ((diff_ecc0_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (diff_ecc2_d1 != 4'h0) & (diff_ecc3_d1 == 4'h0)) | | |
1150 | // ((diff_ecc0_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (diff_ecc2_d1 == 4'h0) & (diff_ecc3_d1 != 4'h0)) | | |
1151 | // ((diff_ecc0_d1 == 4'h0) & (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (diff_ecc3_d1 != 4'h0)) | | |
1152 | // ((diff_ecc0_d1 == 4'h0) & (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 != 4'h0) & (diff_ecc3_d1 == 4'h0)) | | |
1153 | // ((diff_ecc0_d1 != 4'h0) & (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 != 4'h0) & (diff_ecc3_d1 != 4'h0)) | | |
1154 | // ((diff_ecc0_d1 != 4'h0) & (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (diff_ecc3_d1 != 4'h0) & (ecc_loc[14:0] != err_byte_0_14_loc[14:0]) ) | | |
1155 | // ((diff_ecc0_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (diff_ecc2_d1 != 4'h0) & (diff_ecc3_d1 != 4'h0) & (ecc_loc[29:15] != err_byte_15_29_loc[14:0]) ) | | |
1156 | // ((diff_ecc0_d1 != 4'h0) & (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 != 4'h0) & (diff_ecc3_d1 == 4'h0) & ((diff_ecc0_d1 != diff_ecc1_d1) | (diff_ecc1_d1 != diff_ecc2_d1)) ) | | |
1157 | // ((diff_ecc0_d1 == 4'h0) & (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 != 4'h0) & (diff_ecc3_d1 != 4'h0) & ((diff_ecc1_d1 != diff_ecc2_d1) | (diff_ecc2_d1 != diff_ecc3_d1)) )); | |
1158 | // | |
1159 | // | |
1160 | ||
1161 | mcu_readdp_dp_nand_macro__ports_4__width_1 u_ecc_multi_err10_1 ( .din0 ( diffecc0_adj_zero ), .din1 ( diffecc1_adj_zero ), .din2 ( diffecc2_adj_nz ), .din3 ( diffecc3_adj_nz ), .dout ( ecc_multi_err_1[10] )); | |
1162 | mcu_readdp_dp_nand_macro__ports_4__width_1 u_ecc_multi_err9_1 ( .din0 ( diffecc0_adj_nz ), .din1 ( diffecc1_adj_nz ), .din2 ( diffecc2_adj_zero ), .din3 ( diffecc3_adj_zero ), .dout ( ecc_multi_err_1[9] )); | |
1163 | mcu_readdp_dp_nand_macro__ports_4__width_1 u_ecc_multi_err8_1 ( .din0 ( diffecc0_adj_nz ), .din1 ( diffecc1_adj_zero ), .din2 ( diffecc2_adj_nz ), .din3 ( diffecc3_adj_zero ), .dout ( ecc_multi_err_1[8] )); | |
1164 | mcu_readdp_dp_nand_macro__ports_4__width_1 u_ecc_multi_err7_1 ( .din0 ( diffecc0_adj_nz ), .din1 ( diffecc1_adj_zero ), .din2 ( diffecc2_adj_zero ), .din3 ( diffecc3_adj_nz ), .dout ( ecc_multi_err_1[7] )); | |
1165 | mcu_readdp_dp_nand_macro__ports_4__width_1 u_ecc_multi_err6_1 ( .din0 ( diffecc0_adj_zero ), .din1 ( diffecc1_adj_nz ), .din2 ( diffecc2_adj_zero ), .din3 ( diffecc3_adj_nz ), .dout ( ecc_multi_err_1[6] )); | |
1166 | mcu_readdp_dp_nand_macro__ports_4__width_1 u_ecc_multi_err5_1 ( .din0 ( diffecc0_adj_zero ), .din1 ( diffecc1_adj_nz ), .din2 ( diffecc2_adj_nz ), .din3 ( diffecc3_adj_zero ), .dout ( ecc_multi_err_1[5] )); | |
1167 | mcu_readdp_dp_nand_macro__ports_4__width_1 u_ecc_multi_err4_1 ( .din0 ( diffecc0_adj_nz ), .din1 ( diffecc1_adj_nz ), .din2 ( diffecc2_adj_nz ), .din3 ( diffecc3_adj_nz ), .dout ( ecc_multi_err_1[4] )); | |
1168 | mcu_readdp_dp_nand_macro__ports_4__width_1 u_ecc_multi_err3_1 ( .din0 ( diffecc0_adj_nz ), .din1 ( diffecc1_adj_nz ), .din2 ( diffecc2_adj_zero ), .din3 ( diffecc3_adj_nz ), .dout ( ecc_multi_err_1[3] )); | |
1169 | mcu_readdp_dp_nand_macro__ports_4__width_1 u_ecc_multi_err2_1 ( .din0 ( diffecc0_adj_nz ), .din1 ( diffecc1_adj_zero ), .din2 ( diffecc2_adj_nz ), .din3 ( diffecc3_adj_nz ), .dout ( ecc_multi_err_1[2] )); | |
1170 | mcu_readdp_dp_nand_macro__ports_4__width_1 u_ecc_multi_err1_1 ( .din0 ( diffecc0_adj_nz ), .din1 ( diffecc1_adj_nz ), .din2 ( diffecc2_adj_nz ), .din3 ( diffecc3_adj_zero ), .dout ( ecc_multi_err_1[1] )); | |
1171 | mcu_readdp_dp_nand_macro__ports_4__width_1 u_ecc_multi_err0_1 ( .din0 ( diffecc0_adj_zero ), .din1 ( diffecc1_adj_nz ), .din2 ( diffecc2_adj_nz ), .din3 ( diffecc3_adj_nz ), .dout ( ecc_multi_err_1[0] )); | |
1172 | ||
1173 | mcu_readdp_dp_nor_macro__ports_2__width_1 u_ecc_multi_err10_2 ( .din0 ( ecc_multi_err_1[10] ), .din1 ( fail_over_mode ), .dout ( ecc_multi_err_2[10] )); | |
1174 | mcu_readdp_dp_nor_macro__ports_2__width_1 u_ecc_multi_err9_2 ( .din0 ( ecc_multi_err_1[9] ), .din1 ( fail_over_mode ), .dout ( ecc_multi_err_2[9] )); | |
1175 | mcu_readdp_dp_nor_macro__ports_2__width_1 u_ecc_multi_err8_2 ( .din0 ( ecc_multi_err_1[8] ), .din1 ( fail_over_mode ), .dout ( ecc_multi_err_2[8] )); | |
1176 | mcu_readdp_dp_nor_macro__ports_2__width_1 u_ecc_multi_err7_2 ( .din0 ( ecc_multi_err_1[7] ), .din1 ( fail_over_mode ), .dout ( ecc_multi_err_2[7] )); | |
1177 | mcu_readdp_dp_nor_macro__ports_2__width_1 u_ecc_multi_err6_2 ( .din0 ( ecc_multi_err_1[6] ), .din1 ( fail_over_mode ), .dout ( ecc_multi_err_2[6] )); | |
1178 | mcu_readdp_dp_nor_macro__ports_2__width_1 u_ecc_multi_err5_2 ( .din0 ( ecc_multi_err_1[5] ), .din1 ( fail_over_mode ), .dout ( ecc_multi_err_2[5] )); | |
1179 | mcu_readdp_dp_nor_macro__ports_2__width_1 u_ecc_multi_err4_2 ( .din0 ( ecc_multi_err_1[4] ), .din1 ( fail_over_mode ), .dout ( ecc_multi_err_2[4] )); | |
1180 | mcu_readdp_dp_nor_macro__ports_2__width_1 u_ecc_multi_err3_2 ( .din0 ( ecc_multi_err_1[3] ), .din1 ( fail_over_mode ), .dout ( ecc_multi_err_2[3] )); | |
1181 | mcu_readdp_dp_nor_macro__ports_2__width_1 u_ecc_multi_err2_2 ( .din0 ( ecc_multi_err_1[2] ), .din1 ( fail_over_mode ), .dout ( ecc_multi_err_2[2] )); | |
1182 | mcu_readdp_dp_nor_macro__ports_2__width_1 u_ecc_multi_err1_2 ( .din0 ( ecc_multi_err_1[1] ), .din1 ( fail_over_mode ), .dout ( ecc_multi_err_2[1] )); | |
1183 | mcu_readdp_dp_nor_macro__ports_2__width_1 u_ecc_multi_err0_2 ( .din0 ( ecc_multi_err_1[0] ), .din1 ( fail_over_mode ), .dout ( ecc_multi_err_2[0] )); | |
1184 | ||
1185 | mcu_readdp_dp_cmp_macro__width_16 u_ecc_multi_err1_cmp ( .din0 ( { 1'b0, ecc_loc[14:0] } ), .din1 ( { 1'b0, err_byte_0_14_loc[14:0] } ), .dout ( ecc_loc_err_byte_0_14_loc_eq )); | |
1186 | mcu_readdp_dp_cmp_macro__width_16 u_ecc_multi_err0_cmp ( .din0 ( { 1'b0, ecc_loc[29:15] } ), .din1 ( { 1'b0, err_byte_15_29_loc[14:0] } ), .dout ( ecc_loc_err_byte_15_29_loc_eq )); | |
1187 | ||
1188 | mcu_readdp_dp_inv_macro__width_1 u_ecc_multi_err4_3 ( .din ( byte00_err_1 ), .dout ( diffecc0ecc1_adj_ne )); | |
1189 | mcu_readdp_dp_inv_macro__width_1 u_ecc_multi_err3_3 ( .din ( byte3031_err_1 ), .dout ( diffecc1ecc2_adj_ne )); | |
1190 | mcu_readdp_dp_inv_macro__width_1 u_ecc_multi_err2_3 ( .din ( byte15_err_mecc_1 ), .dout ( diffecc2ecc3_adj_ne )); | |
1191 | mcu_readdp_dp_inv_macro__width_1 u_ecc_multi_err1_3 ( .din ( ecc_loc_err_byte_0_14_loc_eq ), .dout ( eccloc_errbyte_0014loc_ne )); | |
1192 | mcu_readdp_dp_inv_macro__width_1 u_ecc_multi_err0_3 ( .din ( ecc_loc_err_byte_15_29_loc_eq ), .dout ( eccloc_errbyte_1529loc_ne )); | |
1193 | ||
1194 | mcu_readdp_dp_or_macro__ports_2__width_1 u_ecc_multi_err1_4 ( .din0 ( diffecc0ecc1_adj_ne ), .din1 ( diffecc1ecc2_adj_ne ), .dout ( ecc_multi_err1_4 )); | |
1195 | mcu_readdp_dp_or_macro__ports_2__width_1 u_ecc_multi_err0_4 ( .din0 ( diffecc1ecc2_adj_ne ), .din1 ( diffecc2ecc3_adj_ne ), .dout ( ecc_multi_err0_4 )); | |
1196 | ||
1197 | mcu_readdp_dp_and_macro__dinv_4x__dnand_2x__ports_2__width_1 u_ecc_multi_err3_5 ( .din0 ( ecc_multi_err_2[3]), .din1 ( eccloc_errbyte_0014loc_ne ), .dout ( ecc_multi_err3_5 )); | |
1198 | mcu_readdp_dp_and_macro__dinv_4x__dnand_2x__ports_2__width_1 u_ecc_multi_err2_5 ( .din0 ( ecc_multi_err_2[2]), .din1 ( eccloc_errbyte_1529loc_ne ), .dout ( ecc_multi_err2_5 )); | |
1199 | mcu_readdp_dp_and_macro__dinv_4x__dnand_2x__ports_2__width_1 u_ecc_multi_err1_5 ( .din0 ( ecc_multi_err_2[1]), .din1 ( ecc_multi_err1_4 ), .dout ( ecc_multi_err1_5 )); | |
1200 | mcu_readdp_dp_and_macro__dinv_4x__dnand_2x__ports_2__width_1 u_ecc_multi_err0_5 ( .din0 ( ecc_multi_err_2[0]), .din1 ( ecc_multi_err0_4 ), .dout ( ecc_multi_err0_5 )); | |
1201 | ||
1202 | mcu_readdp_dp_nor_macro__dnor_4x__ports_3__width_1 u_ecc_multi_err3_6 ( .din0 ( ecc_multi_err_2[10] ), .din1 ( ecc_multi_err_2[9] ), .din2 ( ecc_multi_err_2[8] ), .dout ( ecc_multi_err3_6 )); | |
1203 | mcu_readdp_dp_nor_macro__dnor_4x__ports_3__width_1 u_ecc_multi_err2_6 ( .din0 ( ecc_multi_err_2[7] ), .din1 ( ecc_multi_err_2[6] ), .din2 ( ecc_multi_err_2[5] ), .dout ( ecc_multi_err2_6 )); | |
1204 | mcu_readdp_dp_nor_macro__dnor_4x__ports_3__width_1 u_ecc_multi_err1_6 ( .din0 ( ecc_multi_err_2[4] ), .din1 ( ecc_multi_err3_5 ), .din2 ( ecc_multi_err2_5 ), .dout ( ecc_multi_err1_6 )); | |
1205 | mcu_readdp_dp_nor_macro__dnor_4x__ports_2__width_1 u_ecc_multi_err0_6 ( .din0 ( ecc_multi_err1_5 ), .din1 ( ecc_multi_err0_5 ), .dout ( ecc_multi_err0_6 )); | |
1206 | ||
1207 | mcu_readdp_dp_nand_macro__ports_4__width_1 u_ecc_multi_err ( .din0 ( ecc_multi_err3_6 ), .din1 (ecc_multi_err2_6), .din2 ( ecc_multi_err1_6 ), .din3 ( ecc_multi_err0_6 ), .dout ( ecc_multi_err )); | |
1208 | ||
1209 | // // Generate single ecc error signal. | |
1210 | // wire secc_err31 = (diff_ecc0_d1 != 4'h0) & ( (diff_ecc2_d1 == diff_ecc1_d1) & (diff_ecc2_d1 == diff_ecc0_d1) ); | |
1211 | // wire secc_err30 = (diff_ecc1_d1 != 4'h0) & ( (diff_ecc1_d1 == diff_ecc2_d1) & (diff_ecc0_d1 == 4'h0) ); | |
1212 | // wire secc_err_lo = (diff_ecc1_d1 != 4'h0) & (diff_ecc0_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0); | |
1213 | // wire secc_err_hi = (diff_ecc2_d1 != 4'h0) & (diff_ecc0_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0); | |
1214 | // assign ecc_single_err = ~ecc_multi_err & ((secc_err31 | secc_err30 | secc_err_hi | secc_err_lo) | (|secc_err_d1)); | |
1215 | ||
1216 | ||
1217 | mcu_readdp_dp_and_macro__ports_3__width_1 u_secc_err31 ( .din0 ( byte3031_err_1 ), .din1 ( byte15_err_1 ), .din2 ( diffecc0_adj_nz ), .dout ( secc_err31 )); | |
1218 | mcu_readdp_dp_and_macro__ports_3__width_1 u_secc_err30 ( .din0 ( byte3031_err_1 ), .din1 ( diffecc1_adj_nz ), .din2 ( diffecc0_adj_zero ), .dout ( secc_err30 )); | |
1219 | mcu_readdp_dp_and_macro__ports_3__width_1 u_secc_err_hi ( .din0 ( diffecc2_adj_nz ), .din1 ( diffecc1_adj_zero ), .din2 ( diffecc0_adj_nz ), .dout ( secc_err_hi )); | |
1220 | mcu_readdp_dp_and_macro__ports_3__width_1 u_secc_err_lo ( .din0 ( diffecc2_adj_zero ), .din1 ( diffecc1_adj_nz ), .din2 ( diffecc0_adj_nz ), .dout ( secc_err_lo )); | |
1221 | ||
1222 | mcu_readdp_dp_nor_macro__ports_3__width_1 u_ecc_single_err_1 ( .din0 ( secc_err31 ), .din1 ( secc_err30 ), .din2 ( secc_err_hi ), .dout ( ecc_single_err_1 )); | |
1223 | mcu_readdp_dp_nor_macro__ports_3__width_1 u_ecc_single_err_2 ( .din0 ( secc_err_lo ), .din1 ( secc_err[3] ), .din2 ( secc_err[2] ), .dout ( ecc_single_err_2 )); | |
1224 | mcu_readdp_dp_nor_macro__ports_2__width_1 u_ecc_single_err_3 ( .din0 ( secc_err[1] ), .din1 ( secc_err[0] ), .dout ( ecc_single_err_3 )); | |
1225 | mcu_readdp_dp_and_macro__ports_3__width_1 u_ecc_single_err_4 ( .din0 ( ecc_single_err_1 ), .din1 ( ecc_single_err_2 ), .din2 ( ecc_single_err_3 ), .dout ( ecc_single_err_4 )); | |
1226 | mcu_readdp_dp_nor_macro__ports_2__width_1 u_ecc_single_err ( .din0 ( ecc_single_err_4 ), .din1 ( ecc_multi_err ), .dout ( ecc_single_err )); | |
1227 | ||
1228 | ||
1229 | // | |
1230 | // Corrected data | |
1231 | // | |
1232 | mcu_readdp_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__stack_64c__width_64 u_cordata_127_64 ( | |
1233 | .din0 ( { rddata31_in[3:0], rddata30_in[3:0], rddata29_in[3:0], rddata28_in[3:0], | |
1234 | rddata27_in[3:0], rddata26_in[3:0], rddata25_in[3:0], rddata24_in[3:0], | |
1235 | rddata23_in[3:0], rddata22_in[3:0], rddata21_in[3:0], rddata20_in[3:0], | |
1236 | rddata19_in[3:0], rddata18_in[3:0], rddata17_in[3:0], rddata16_in[3:0] }), | |
1237 | .din1 ( { outbyte31[3:0], outbyte30[3:0], outbyte29[3:0], outbyte28[3:0], | |
1238 | outbyte27[3:0], outbyte26[3:0], outbyte25[3:0], outbyte24[3:0], | |
1239 | outbyte23[3:0], outbyte22[3:0], outbyte21[3:0], outbyte20[3:0], | |
1240 | outbyte19[3:0], outbyte18[3:0], outbyte17[3:0], outbyte16[3:0] }), | |
1241 | .sel0 ( ecc_multi_err ), | |
1242 | .dout ( cor_rddata[127:64] )); | |
1243 | ||
1244 | mcu_readdp_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__stack_64c__width_64 u_cordata_63_0 ( | |
1245 | .din0 ( { rddata15_in[3:0], rddata14_in[3:0], rddata13_in[3:0], rddata12_in[3:0], | |
1246 | rddata11_in[3:0], rddata10_in[3:0], rddata09_in[3:0], rddata08_in[3:0], | |
1247 | rddata07_in[3:0], rddata06_in[3:0], rddata05_in[3:0], rddata04_in[3:0], | |
1248 | rddata03_in[3:0], rddata02_in[3:0], rddata01_in[3:0], rddata00_in[3:0] }), | |
1249 | .din1 ( { outbyte15[3:0], outbyte14[3:0], outbyte13[3:0], outbyte12[3:0], | |
1250 | outbyte11[3:0], outbyte10[3:0], outbyte09[3:0], outbyte08[3:0], | |
1251 | outbyte07[3:0], outbyte06[3:0], outbyte05[3:0], outbyte04[3:0], | |
1252 | outbyte03[3:0], outbyte02[3:0], outbyte01[3:0], outbyte00[3:0] }), | |
1253 | .sel0 ( ecc_multi_err ), | |
1254 | .dout ( cor_rddata[63:0] )); | |
1255 | ||
1256 | mcu_readdp_dp_msff_macro__stack_66c__width_65 u_rddata_127_64_secc_err ( | |
1257 | .scan_in(u_rddata_127_64_secc_err_scanin), | |
1258 | .scan_out(u_rddata_127_64_secc_err_scanout), | |
1259 | .clk ( drl2clk ), | |
1260 | .en ( rddata_en[1] ), | |
1261 | .din ( {cor_rddata[127:64], ecc_single_err } ), | |
1262 | .dout ( {rddata[127:64], dr_secc_err } ), | |
1263 | .se(se), | |
1264 | .siclk(siclk), | |
1265 | .soclk(soclk), | |
1266 | .pce_ov(pce_ov), | |
1267 | .stop(stop)); | |
1268 | ||
1269 | mcu_readdp_dp_msff_macro__stack_66c__width_65 u_rddata_63_0_mecc_err ( | |
1270 | .scan_in(u_rddata_63_0_mecc_err_scanin), | |
1271 | .scan_out(u_rddata_63_0_mecc_err_scanout), | |
1272 | .clk ( drl2clk ), | |
1273 | .en ( rddata_en[1] ), | |
1274 | .din ( { cor_rddata[63:0], ecc_multi_err } ), | |
1275 | .dout ( { rddata[63:0], dr_mecc_err } ), | |
1276 | .se(se), | |
1277 | .siclk(siclk), | |
1278 | .soclk(soclk), | |
1279 | .pce_ov(pce_ov), | |
1280 | .stop(stop)); | |
1281 | ||
1282 | // fixscan start: | |
1283 | assign u_rddata_in_127_64_scanin = scan_in ; | |
1284 | assign u_rddata_in_63_0_scanin = u_rddata_in_127_64_scanout; | |
1285 | assign u_rdecc_in_15_8_scanin = u_rddata_in_63_0_scanout ; | |
1286 | assign u_rdecc_in_7_0_par_scanin = u_rdecc_in_15_8_scanout ; | |
1287 | assign u_rddata_127_64_secc_err_scanin = u_rdecc_in_7_0_par_scanout; | |
1288 | assign u_rddata_63_0_mecc_err_scanin = u_rddata_127_64_secc_err_scanout; | |
1289 | assign scan_out = u_rddata_63_0_mecc_err_scanout; | |
1290 | // fixscan end: | |
1291 | endmodule // mcu_readdp_dp; | |
1292 | ||
1293 | ||
1294 | ||
1295 | // | |
1296 | // buff macro | |
1297 | // | |
1298 | // | |
1299 | ||
1300 | ||
1301 | ||
1302 | ||
1303 | ||
1304 | module mcu_readdp_dp_buff_macro__width_2 ( | |
1305 | din, | |
1306 | dout); | |
1307 | input [1:0] din; | |
1308 | output [1:0] dout; | |
1309 | ||
1310 | ||
1311 | ||
1312 | ||
1313 | ||
1314 | ||
1315 | buff #(2) d0_0 ( | |
1316 | .in(din[1:0]), | |
1317 | .out(dout[1:0]) | |
1318 | ); | |
1319 | ||
1320 | ||
1321 | ||
1322 | ||
1323 | ||
1324 | ||
1325 | ||
1326 | ||
1327 | endmodule | |
1328 | ||
1329 | ||
1330 | ||
1331 | ||
1332 | ||
1333 | // | |
1334 | // and macro for ports = 2,3,4 | |
1335 | // | |
1336 | // | |
1337 | ||
1338 | ||
1339 | ||
1340 | ||
1341 | ||
1342 | module mcu_readdp_dp_and_macro__width_16 ( | |
1343 | din0, | |
1344 | din1, | |
1345 | dout); | |
1346 | input [15:0] din0; | |
1347 | input [15:0] din1; | |
1348 | output [15:0] dout; | |
1349 | ||
1350 | ||
1351 | ||
1352 | ||
1353 | ||
1354 | ||
1355 | and2 #(16) d0_0 ( | |
1356 | .in0(din0[15:0]), | |
1357 | .in1(din1[15:0]), | |
1358 | .out(dout[15:0]) | |
1359 | ); | |
1360 | ||
1361 | ||
1362 | ||
1363 | ||
1364 | ||
1365 | ||
1366 | ||
1367 | ||
1368 | ||
1369 | endmodule | |
1370 | ||
1371 | ||
1372 | ||
1373 | ||
1374 | ||
1375 | // | |
1376 | // and macro for ports = 2,3,4 | |
1377 | // | |
1378 | // | |
1379 | ||
1380 | ||
1381 | ||
1382 | ||
1383 | ||
1384 | module mcu_readdp_dp_and_macro__width_64 ( | |
1385 | din0, | |
1386 | din1, | |
1387 | dout); | |
1388 | input [63:0] din0; | |
1389 | input [63:0] din1; | |
1390 | output [63:0] dout; | |
1391 | ||
1392 | ||
1393 | ||
1394 | ||
1395 | ||
1396 | ||
1397 | and2 #(64) d0_0 ( | |
1398 | .in0(din0[63:0]), | |
1399 | .in1(din1[63:0]), | |
1400 | .out(dout[63:0]) | |
1401 | ); | |
1402 | ||
1403 | ||
1404 | ||
1405 | ||
1406 | ||
1407 | ||
1408 | ||
1409 | ||
1410 | ||
1411 | endmodule | |
1412 | ||
1413 | ||
1414 | ||
1415 | ||
1416 | ||
1417 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1418 | // also for pass-gate with decoder | |
1419 | ||
1420 | ||
1421 | ||
1422 | ||
1423 | ||
1424 | // any PARAMS parms go into naming of macro | |
1425 | ||
1426 | module mcu_readdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_4l__width_4 ( | |
1427 | din0, | |
1428 | sel0, | |
1429 | din1, | |
1430 | sel1, | |
1431 | dout); | |
1432 | input [3:0] din0; | |
1433 | input sel0; | |
1434 | input [3:0] din1; | |
1435 | input sel1; | |
1436 | output [3:0] dout; | |
1437 | ||
1438 | ||
1439 | ||
1440 | ||
1441 | ||
1442 | mux2s #(4) d0_0 ( | |
1443 | .sel0(sel0), | |
1444 | .sel1(sel1), | |
1445 | .in0(din0[3:0]), | |
1446 | .in1(din1[3:0]), | |
1447 | .dout(dout[3:0]) | |
1448 | ); | |
1449 | ||
1450 | ||
1451 | ||
1452 | ||
1453 | ||
1454 | ||
1455 | ||
1456 | ||
1457 | ||
1458 | ||
1459 | ||
1460 | ||
1461 | ||
1462 | endmodule | |
1463 | ||
1464 | ||
1465 | ||
1466 | ||
1467 | ||
1468 | ||
1469 | // any PARAMS parms go into naming of macro | |
1470 | ||
1471 | module mcu_readdp_dp_msff_macro__stack_64c__width_64 ( | |
1472 | din, | |
1473 | clk, | |
1474 | en, | |
1475 | se, | |
1476 | scan_in, | |
1477 | siclk, | |
1478 | soclk, | |
1479 | pce_ov, | |
1480 | stop, | |
1481 | dout, | |
1482 | scan_out); | |
1483 | wire l1clk; | |
1484 | wire siclk_out; | |
1485 | wire soclk_out; | |
1486 | wire [62:0] so; | |
1487 | ||
1488 | input [63:0] din; | |
1489 | ||
1490 | ||
1491 | input clk; | |
1492 | input en; | |
1493 | input se; | |
1494 | input scan_in; | |
1495 | input siclk; | |
1496 | input soclk; | |
1497 | input pce_ov; | |
1498 | input stop; | |
1499 | ||
1500 | ||
1501 | ||
1502 | output [63:0] dout; | |
1503 | ||
1504 | ||
1505 | output scan_out; | |
1506 | ||
1507 | ||
1508 | ||
1509 | ||
1510 | cl_dp1_l1hdr_8x c0_0 ( | |
1511 | .l2clk(clk), | |
1512 | .pce(en), | |
1513 | .aclk(siclk), | |
1514 | .bclk(soclk), | |
1515 | .l1clk(l1clk), | |
1516 | .se(se), | |
1517 | .pce_ov(pce_ov), | |
1518 | .stop(stop), | |
1519 | .siclk_out(siclk_out), | |
1520 | .soclk_out(soclk_out) | |
1521 | ); | |
1522 | dff #(64) d0_0 ( | |
1523 | .l1clk(l1clk), | |
1524 | .siclk(siclk_out), | |
1525 | .soclk(soclk_out), | |
1526 | .d(din[63:0]), | |
1527 | .si({scan_in,so[62:0]}), | |
1528 | .so({so[62:0],scan_out}), | |
1529 | .q(dout[63:0]) | |
1530 | ); | |
1531 | ||
1532 | ||
1533 | ||
1534 | ||
1535 | ||
1536 | ||
1537 | ||
1538 | ||
1539 | ||
1540 | ||
1541 | ||
1542 | ||
1543 | ||
1544 | ||
1545 | ||
1546 | ||
1547 | ||
1548 | ||
1549 | ||
1550 | ||
1551 | endmodule | |
1552 | ||
1553 | ||
1554 | ||
1555 | ||
1556 | ||
1557 | ||
1558 | ||
1559 | ||
1560 | ||
1561 | // | |
1562 | // xor macro for ports = 2,3 | |
1563 | // | |
1564 | // | |
1565 | ||
1566 | ||
1567 | ||
1568 | ||
1569 | ||
1570 | module mcu_readdp_dp_xor_macro__ports_2 ( | |
1571 | din0, | |
1572 | din1, | |
1573 | dout); | |
1574 | input [0:0] din0; | |
1575 | input [0:0] din1; | |
1576 | output [0:0] dout; | |
1577 | ||
1578 | ||
1579 | ||
1580 | ||
1581 | ||
1582 | xor2 #(1) d0_0 ( | |
1583 | .in0(din0[0:0]), | |
1584 | .in1(din1[0:0]), | |
1585 | .out(dout[0:0]) | |
1586 | ); | |
1587 | ||
1588 | ||
1589 | ||
1590 | ||
1591 | ||
1592 | ||
1593 | ||
1594 | ||
1595 | endmodule | |
1596 | ||
1597 | ||
1598 | ||
1599 | ||
1600 | ||
1601 | ||
1602 | ||
1603 | ||
1604 | ||
1605 | // any PARAMS parms go into naming of macro | |
1606 | ||
1607 | module mcu_readdp_dp_msff_macro__stack_8l__width_8 ( | |
1608 | din, | |
1609 | clk, | |
1610 | en, | |
1611 | se, | |
1612 | scan_in, | |
1613 | siclk, | |
1614 | soclk, | |
1615 | pce_ov, | |
1616 | stop, | |
1617 | dout, | |
1618 | scan_out); | |
1619 | wire l1clk; | |
1620 | wire siclk_out; | |
1621 | wire soclk_out; | |
1622 | wire [6:0] so; | |
1623 | ||
1624 | input [7:0] din; | |
1625 | ||
1626 | ||
1627 | input clk; | |
1628 | input en; | |
1629 | input se; | |
1630 | input scan_in; | |
1631 | input siclk; | |
1632 | input soclk; | |
1633 | input pce_ov; | |
1634 | input stop; | |
1635 | ||
1636 | ||
1637 | ||
1638 | output [7:0] dout; | |
1639 | ||
1640 | ||
1641 | output scan_out; | |
1642 | ||
1643 | ||
1644 | ||
1645 | ||
1646 | cl_dp1_l1hdr_8x c0_0 ( | |
1647 | .l2clk(clk), | |
1648 | .pce(en), | |
1649 | .aclk(siclk), | |
1650 | .bclk(soclk), | |
1651 | .l1clk(l1clk), | |
1652 | .se(se), | |
1653 | .pce_ov(pce_ov), | |
1654 | .stop(stop), | |
1655 | .siclk_out(siclk_out), | |
1656 | .soclk_out(soclk_out) | |
1657 | ); | |
1658 | dff #(8) d0_0 ( | |
1659 | .l1clk(l1clk), | |
1660 | .siclk(siclk_out), | |
1661 | .soclk(soclk_out), | |
1662 | .d(din[7:0]), | |
1663 | .si({scan_in,so[6:0]}), | |
1664 | .so({so[6:0],scan_out}), | |
1665 | .q(dout[7:0]) | |
1666 | ); | |
1667 | ||
1668 | ||
1669 | ||
1670 | ||
1671 | ||
1672 | ||
1673 | ||
1674 | ||
1675 | ||
1676 | ||
1677 | ||
1678 | ||
1679 | ||
1680 | ||
1681 | ||
1682 | ||
1683 | ||
1684 | ||
1685 | ||
1686 | ||
1687 | endmodule | |
1688 | ||
1689 | ||
1690 | ||
1691 | ||
1692 | ||
1693 | ||
1694 | ||
1695 | ||
1696 | ||
1697 | ||
1698 | ||
1699 | ||
1700 | ||
1701 | // any PARAMS parms go into naming of macro | |
1702 | ||
1703 | module mcu_readdp_dp_msff_macro__stack_10l__width_9 ( | |
1704 | din, | |
1705 | clk, | |
1706 | en, | |
1707 | se, | |
1708 | scan_in, | |
1709 | siclk, | |
1710 | soclk, | |
1711 | pce_ov, | |
1712 | stop, | |
1713 | dout, | |
1714 | scan_out); | |
1715 | wire l1clk; | |
1716 | wire siclk_out; | |
1717 | wire soclk_out; | |
1718 | wire [7:0] so; | |
1719 | ||
1720 | input [8:0] din; | |
1721 | ||
1722 | ||
1723 | input clk; | |
1724 | input en; | |
1725 | input se; | |
1726 | input scan_in; | |
1727 | input siclk; | |
1728 | input soclk; | |
1729 | input pce_ov; | |
1730 | input stop; | |
1731 | ||
1732 | ||
1733 | ||
1734 | output [8:0] dout; | |
1735 | ||
1736 | ||
1737 | output scan_out; | |
1738 | ||
1739 | ||
1740 | ||
1741 | ||
1742 | cl_dp1_l1hdr_8x c0_0 ( | |
1743 | .l2clk(clk), | |
1744 | .pce(en), | |
1745 | .aclk(siclk), | |
1746 | .bclk(soclk), | |
1747 | .l1clk(l1clk), | |
1748 | .se(se), | |
1749 | .pce_ov(pce_ov), | |
1750 | .stop(stop), | |
1751 | .siclk_out(siclk_out), | |
1752 | .soclk_out(soclk_out) | |
1753 | ); | |
1754 | dff #(9) d0_0 ( | |
1755 | .l1clk(l1clk), | |
1756 | .siclk(siclk_out), | |
1757 | .soclk(soclk_out), | |
1758 | .d(din[8:0]), | |
1759 | .si({scan_in,so[7:0]}), | |
1760 | .so({so[7:0],scan_out}), | |
1761 | .q(dout[8:0]) | |
1762 | ); | |
1763 | ||
1764 | ||
1765 | ||
1766 | ||
1767 | ||
1768 | ||
1769 | ||
1770 | ||
1771 | endmodule | |
1772 | ||
1773 | ||
1774 | ||
1775 | ||
1776 | // | |
1777 | // buff macro | |
1778 | // | |
1779 | // | |
1780 | ||
1781 | ||
1782 | ||
1783 | ||
1784 | ||
1785 | module mcu_readdp_dp_buff_macro__stack_64c__width_64 ( | |
1786 | din, | |
1787 | dout); | |
1788 | input [63:0] din; | |
1789 | output [63:0] dout; | |
1790 | ||
1791 | ||
1792 | ||
1793 | ||
1794 | ||
1795 | ||
1796 | buff #(64) d0_0 ( | |
1797 | .in(din[63:0]), | |
1798 | .out(dout[63:0]) | |
1799 | ); | |
1800 | ||
1801 | ||
1802 | ||
1803 | ||
1804 | ||
1805 | ||
1806 | ||
1807 | ||
1808 | endmodule | |
1809 | ||
1810 | ||
1811 | ||
1812 | ||
1813 | ||
1814 | // | |
1815 | // buff macro | |
1816 | // | |
1817 | // | |
1818 | ||
1819 | ||
1820 | ||
1821 | ||
1822 | ||
1823 | module mcu_readdp_dp_buff_macro__stack_2l__width_2 ( | |
1824 | din, | |
1825 | dout); | |
1826 | input [1:0] din; | |
1827 | output [1:0] dout; | |
1828 | ||
1829 | ||
1830 | ||
1831 | ||
1832 | ||
1833 | ||
1834 | buff #(2) d0_0 ( | |
1835 | .in(din[1:0]), | |
1836 | .out(dout[1:0]) | |
1837 | ); | |
1838 | ||
1839 | ||
1840 | ||
1841 | ||
1842 | ||
1843 | ||
1844 | ||
1845 | ||
1846 | endmodule | |
1847 | ||
1848 | ||
1849 | ||
1850 | ||
1851 | ||
1852 | // | |
1853 | // xor macro for ports = 2,3 | |
1854 | // | |
1855 | // | |
1856 | ||
1857 | ||
1858 | ||
1859 | ||
1860 | ||
1861 | module mcu_readdp_dp_xor_macro__dxor_8x__ports_3__width_1 ( | |
1862 | din0, | |
1863 | din1, | |
1864 | din2, | |
1865 | dout); | |
1866 | input [0:0] din0; | |
1867 | input [0:0] din1; | |
1868 | input [0:0] din2; | |
1869 | output [0:0] dout; | |
1870 | ||
1871 | ||
1872 | ||
1873 | ||
1874 | ||
1875 | xor3 #(1) d0_0 ( | |
1876 | .in0(din0[0:0]), | |
1877 | .in1(din1[0:0]), | |
1878 | .in2(din2[0:0]), | |
1879 | .out(dout[0:0]) | |
1880 | ); | |
1881 | ||
1882 | ||
1883 | ||
1884 | ||
1885 | ||
1886 | ||
1887 | ||
1888 | ||
1889 | endmodule | |
1890 | ||
1891 | ||
1892 | ||
1893 | ||
1894 | ||
1895 | // | |
1896 | // buff macro | |
1897 | // | |
1898 | // | |
1899 | ||
1900 | ||
1901 | ||
1902 | ||
1903 | ||
1904 | module mcu_readdp_dp_buff_macro__stack_16l__width_16 ( | |
1905 | din, | |
1906 | dout); | |
1907 | input [15:0] din; | |
1908 | output [15:0] dout; | |
1909 | ||
1910 | ||
1911 | ||
1912 | ||
1913 | ||
1914 | ||
1915 | buff #(16) d0_0 ( | |
1916 | .in(din[15:0]), | |
1917 | .out(dout[15:0]) | |
1918 | ); | |
1919 | ||
1920 | ||
1921 | ||
1922 | ||
1923 | ||
1924 | ||
1925 | ||
1926 | ||
1927 | endmodule | |
1928 | ||
1929 | ||
1930 | ||
1931 | ||
1932 | ||
1933 | // | |
1934 | // nor macro for ports = 2,3 | |
1935 | // | |
1936 | // | |
1937 | ||
1938 | ||
1939 | ||
1940 | ||
1941 | ||
1942 | module mcu_readdp_dp_nor_macro__ports_2__stack_1l__width_1 ( | |
1943 | din0, | |
1944 | din1, | |
1945 | dout); | |
1946 | input [0:0] din0; | |
1947 | input [0:0] din1; | |
1948 | output [0:0] dout; | |
1949 | ||
1950 | ||
1951 | ||
1952 | ||
1953 | ||
1954 | ||
1955 | nor2 #(1) d0_0 ( | |
1956 | .in0(din0[0:0]), | |
1957 | .in1(din1[0:0]), | |
1958 | .out(dout[0:0]) | |
1959 | ); | |
1960 | ||
1961 | ||
1962 | ||
1963 | ||
1964 | ||
1965 | ||
1966 | ||
1967 | endmodule | |
1968 | ||
1969 | ||
1970 | ||
1971 | ||
1972 | ||
1973 | // | |
1974 | // nand macro for ports = 2,3,4 | |
1975 | // | |
1976 | // | |
1977 | ||
1978 | ||
1979 | ||
1980 | ||
1981 | ||
1982 | module mcu_readdp_dp_nand_macro__ports_2__stack_1l__width_1 ( | |
1983 | din0, | |
1984 | din1, | |
1985 | dout); | |
1986 | input [0:0] din0; | |
1987 | input [0:0] din1; | |
1988 | output [0:0] dout; | |
1989 | ||
1990 | ||
1991 | ||
1992 | ||
1993 | ||
1994 | ||
1995 | nand2 #(1) d0_0 ( | |
1996 | .in0(din0[0:0]), | |
1997 | .in1(din1[0:0]), | |
1998 | .out(dout[0:0]) | |
1999 | ); | |
2000 | ||
2001 | ||
2002 | ||
2003 | ||
2004 | ||
2005 | ||
2006 | ||
2007 | ||
2008 | ||
2009 | endmodule | |
2010 | ||
2011 | ||
2012 | ||
2013 | ||
2014 | ||
2015 | // | |
2016 | // invert macro | |
2017 | // | |
2018 | // | |
2019 | ||
2020 | ||
2021 | ||
2022 | ||
2023 | ||
2024 | module mcu_readdp_dp_inv_macro__stack_1l__width_1 ( | |
2025 | din, | |
2026 | dout); | |
2027 | input [0:0] din; | |
2028 | output [0:0] dout; | |
2029 | ||
2030 | ||
2031 | ||
2032 | ||
2033 | ||
2034 | ||
2035 | inv #(1) d0_0 ( | |
2036 | .in(din[0:0]), | |
2037 | .out(dout[0:0]) | |
2038 | ); | |
2039 | ||
2040 | ||
2041 | ||
2042 | ||
2043 | ||
2044 | ||
2045 | ||
2046 | ||
2047 | ||
2048 | endmodule | |
2049 | ||
2050 | ||
2051 | ||
2052 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
2053 | // also for pass-gate with decoder | |
2054 | ||
2055 | ||
2056 | ||
2057 | ||
2058 | ||
2059 | // any PARAMS parms go into naming of macro | |
2060 | ||
2061 | module mcu_readdp_dp_mux_macro__mux_pgpe__ports_2__stack_4c__width_4 ( | |
2062 | din0, | |
2063 | din1, | |
2064 | sel0, | |
2065 | dout); | |
2066 | wire psel0_unused; | |
2067 | wire psel1; | |
2068 | ||
2069 | input [3:0] din0; | |
2070 | input [3:0] din1; | |
2071 | input sel0; | |
2072 | output [3:0] dout; | |
2073 | ||
2074 | ||
2075 | ||
2076 | ||
2077 | ||
2078 | cl_dp1_penc2_8x c0_0 ( | |
2079 | .sel0(sel0), | |
2080 | .psel0(psel0_unused), | |
2081 | .psel1(psel1) | |
2082 | ); | |
2083 | ||
2084 | mux2e #(4) d0_0 ( | |
2085 | .sel(psel1), | |
2086 | .in0(din0[3:0]), | |
2087 | .in1(din1[3:0]), | |
2088 | .dout(dout[3:0]) | |
2089 | ); | |
2090 | ||
2091 | ||
2092 | ||
2093 | ||
2094 | ||
2095 | ||
2096 | ||
2097 | ||
2098 | ||
2099 | ||
2100 | ||
2101 | ||
2102 | ||
2103 | endmodule | |
2104 | ||
2105 | ||
2106 | // | |
2107 | // xor macro for ports = 2,3 | |
2108 | // | |
2109 | // | |
2110 | ||
2111 | ||
2112 | ||
2113 | ||
2114 | ||
2115 | module mcu_readdp_dp_xor_macro__ports_3__stack_1l__width_1 ( | |
2116 | din0, | |
2117 | din1, | |
2118 | din2, | |
2119 | dout); | |
2120 | input [0:0] din0; | |
2121 | input [0:0] din1; | |
2122 | input [0:0] din2; | |
2123 | output [0:0] dout; | |
2124 | ||
2125 | ||
2126 | ||
2127 | ||
2128 | ||
2129 | xor3 #(1) d0_0 ( | |
2130 | .in0(din0[0:0]), | |
2131 | .in1(din1[0:0]), | |
2132 | .in2(din2[0:0]), | |
2133 | .out(dout[0:0]) | |
2134 | ); | |
2135 | ||
2136 | ||
2137 | ||
2138 | ||
2139 | ||
2140 | ||
2141 | ||
2142 | ||
2143 | endmodule | |
2144 | ||
2145 | ||
2146 | ||
2147 | ||
2148 | ||
2149 | // | |
2150 | // xor macro for ports = 2,3 | |
2151 | // | |
2152 | // | |
2153 | ||
2154 | ||
2155 | ||
2156 | ||
2157 | ||
2158 | module mcu_readdp_dp_xor_macro__ports_2__stack_1l__width_1 ( | |
2159 | din0, | |
2160 | din1, | |
2161 | dout); | |
2162 | input [0:0] din0; | |
2163 | input [0:0] din1; | |
2164 | output [0:0] dout; | |
2165 | ||
2166 | ||
2167 | ||
2168 | ||
2169 | ||
2170 | xor2 #(1) d0_0 ( | |
2171 | .in0(din0[0:0]), | |
2172 | .in1(din1[0:0]), | |
2173 | .out(dout[0:0]) | |
2174 | ); | |
2175 | ||
2176 | ||
2177 | ||
2178 | ||
2179 | ||
2180 | ||
2181 | ||
2182 | ||
2183 | endmodule | |
2184 | ||
2185 | ||
2186 | ||
2187 | ||
2188 | ||
2189 | // | |
2190 | // buff macro | |
2191 | // | |
2192 | // | |
2193 | ||
2194 | ||
2195 | ||
2196 | ||
2197 | ||
2198 | module mcu_readdp_dp_buff_macro__stack_1l__width_1 ( | |
2199 | din, | |
2200 | dout); | |
2201 | input [0:0] din; | |
2202 | output [0:0] dout; | |
2203 | ||
2204 | ||
2205 | ||
2206 | ||
2207 | ||
2208 | ||
2209 | buff #(1) d0_0 ( | |
2210 | .in(din[0:0]), | |
2211 | .out(dout[0:0]) | |
2212 | ); | |
2213 | ||
2214 | ||
2215 | ||
2216 | ||
2217 | ||
2218 | ||
2219 | ||
2220 | ||
2221 | endmodule | |
2222 | ||
2223 | ||
2224 | ||
2225 | ||
2226 | ||
2227 | // | |
2228 | // buff macro | |
2229 | // | |
2230 | // | |
2231 | ||
2232 | ||
2233 | ||
2234 | ||
2235 | ||
2236 | module mcu_readdp_dp_buff_macro__stack_56l__width_56 ( | |
2237 | din, | |
2238 | dout); | |
2239 | input [55:0] din; | |
2240 | output [55:0] dout; | |
2241 | ||
2242 | ||
2243 | ||
2244 | ||
2245 | ||
2246 | ||
2247 | buff #(56) d0_0 ( | |
2248 | .in(din[55:0]), | |
2249 | .out(dout[55:0]) | |
2250 | ); | |
2251 | ||
2252 | ||
2253 | ||
2254 | ||
2255 | ||
2256 | ||
2257 | ||
2258 | ||
2259 | endmodule | |
2260 | ||
2261 | ||
2262 | ||
2263 | ||
2264 | ||
2265 | // | |
2266 | // nor macro for ports = 2,3 | |
2267 | // | |
2268 | // | |
2269 | ||
2270 | ||
2271 | ||
2272 | ||
2273 | ||
2274 | module mcu_readdp_dp_nor_macro__dnor_4x__ports_2__width_1 ( | |
2275 | din0, | |
2276 | din1, | |
2277 | dout); | |
2278 | input [0:0] din0; | |
2279 | input [0:0] din1; | |
2280 | output [0:0] dout; | |
2281 | ||
2282 | ||
2283 | ||
2284 | ||
2285 | ||
2286 | ||
2287 | nor2 #(1) d0_0 ( | |
2288 | .in0(din0[0:0]), | |
2289 | .in1(din1[0:0]), | |
2290 | .out(dout[0:0]) | |
2291 | ); | |
2292 | ||
2293 | ||
2294 | ||
2295 | ||
2296 | ||
2297 | ||
2298 | ||
2299 | endmodule | |
2300 | ||
2301 | ||
2302 | ||
2303 | ||
2304 | ||
2305 | // | |
2306 | // nor macro for ports = 2,3 | |
2307 | // | |
2308 | // | |
2309 | ||
2310 | ||
2311 | ||
2312 | ||
2313 | ||
2314 | module mcu_readdp_dp_nor_macro__dnor_16x__ports_2__width_1 ( | |
2315 | din0, | |
2316 | din1, | |
2317 | dout); | |
2318 | input [0:0] din0; | |
2319 | input [0:0] din1; | |
2320 | output [0:0] dout; | |
2321 | ||
2322 | ||
2323 | ||
2324 | ||
2325 | ||
2326 | ||
2327 | nor2 #(1) d0_0 ( | |
2328 | .in0(din0[0:0]), | |
2329 | .in1(din1[0:0]), | |
2330 | .out(dout[0:0]) | |
2331 | ); | |
2332 | ||
2333 | ||
2334 | ||
2335 | ||
2336 | ||
2337 | ||
2338 | ||
2339 | endmodule | |
2340 | ||
2341 | ||
2342 | ||
2343 | ||
2344 | ||
2345 | // | |
2346 | // nand macro for ports = 2,3,4 | |
2347 | // | |
2348 | // | |
2349 | ||
2350 | ||
2351 | ||
2352 | ||
2353 | ||
2354 | module mcu_readdp_dp_nand_macro__ports_3__stack_1l__width_1 ( | |
2355 | din0, | |
2356 | din1, | |
2357 | din2, | |
2358 | dout); | |
2359 | input [0:0] din0; | |
2360 | input [0:0] din1; | |
2361 | input [0:0] din2; | |
2362 | output [0:0] dout; | |
2363 | ||
2364 | ||
2365 | ||
2366 | ||
2367 | ||
2368 | ||
2369 | nand3 #(1) d0_0 ( | |
2370 | .in0(din0[0:0]), | |
2371 | .in1(din1[0:0]), | |
2372 | .in2(din2[0:0]), | |
2373 | .out(dout[0:0]) | |
2374 | ); | |
2375 | ||
2376 | ||
2377 | ||
2378 | ||
2379 | ||
2380 | ||
2381 | ||
2382 | ||
2383 | ||
2384 | endmodule | |
2385 | ||
2386 | ||
2387 | ||
2388 | ||
2389 | ||
2390 | // | |
2391 | // or macro for ports = 2,3 | |
2392 | // | |
2393 | // | |
2394 | ||
2395 | ||
2396 | ||
2397 | ||
2398 | ||
2399 | module mcu_readdp_dp_or_macro__ports_2__stack_1l__width_1 ( | |
2400 | din0, | |
2401 | din1, | |
2402 | dout); | |
2403 | input [0:0] din0; | |
2404 | input [0:0] din1; | |
2405 | output [0:0] dout; | |
2406 | ||
2407 | ||
2408 | ||
2409 | ||
2410 | ||
2411 | ||
2412 | or2 #(1) d0_0 ( | |
2413 | .in0(din0[0:0]), | |
2414 | .in1(din1[0:0]), | |
2415 | .out(dout[0:0]) | |
2416 | ); | |
2417 | ||
2418 | ||
2419 | ||
2420 | ||
2421 | ||
2422 | ||
2423 | ||
2424 | ||
2425 | ||
2426 | endmodule | |
2427 | ||
2428 | ||
2429 | ||
2430 | ||
2431 | ||
2432 | // | |
2433 | // and macro for ports = 2,3,4 | |
2434 | // | |
2435 | // | |
2436 | ||
2437 | ||
2438 | ||
2439 | ||
2440 | ||
2441 | module mcu_readdp_dp_and_macro__dinv_32x__dnand_4x__ports_2__width_4 ( | |
2442 | din0, | |
2443 | din1, | |
2444 | dout); | |
2445 | input [3:0] din0; | |
2446 | input [3:0] din1; | |
2447 | output [3:0] dout; | |
2448 | ||
2449 | ||
2450 | ||
2451 | ||
2452 | ||
2453 | ||
2454 | and2 #(4) d0_0 ( | |
2455 | .in0(din0[3:0]), | |
2456 | .in1(din1[3:0]), | |
2457 | .out(dout[3:0]) | |
2458 | ); | |
2459 | ||
2460 | ||
2461 | ||
2462 | ||
2463 | ||
2464 | ||
2465 | ||
2466 | ||
2467 | ||
2468 | endmodule | |
2469 | ||
2470 | ||
2471 | ||
2472 | ||
2473 | ||
2474 | // | |
2475 | // nor macro for ports = 2,3 | |
2476 | // | |
2477 | // | |
2478 | ||
2479 | ||
2480 | ||
2481 | ||
2482 | ||
2483 | module mcu_readdp_dp_nor_macro__ports_3__stack_1l__width_1 ( | |
2484 | din0, | |
2485 | din1, | |
2486 | din2, | |
2487 | dout); | |
2488 | input [0:0] din0; | |
2489 | input [0:0] din1; | |
2490 | input [0:0] din2; | |
2491 | output [0:0] dout; | |
2492 | ||
2493 | ||
2494 | ||
2495 | ||
2496 | ||
2497 | ||
2498 | nor3 #(1) d0_0 ( | |
2499 | .in0(din0[0:0]), | |
2500 | .in1(din1[0:0]), | |
2501 | .in2(din2[0:0]), | |
2502 | .out(dout[0:0]) | |
2503 | ); | |
2504 | ||
2505 | ||
2506 | ||
2507 | ||
2508 | ||
2509 | ||
2510 | ||
2511 | endmodule | |
2512 | ||
2513 | ||
2514 | ||
2515 | ||
2516 | ||
2517 | // | |
2518 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) | |
2519 | // | |
2520 | // | |
2521 | ||
2522 | ||
2523 | ||
2524 | ||
2525 | ||
2526 | module mcu_readdp_dp_cmp_macro__width_4 ( | |
2527 | din0, | |
2528 | din1, | |
2529 | dout); | |
2530 | input [3:0] din0; | |
2531 | input [3:0] din1; | |
2532 | output dout; | |
2533 | ||
2534 | ||
2535 | ||
2536 | ||
2537 | ||
2538 | ||
2539 | cmp #(4) m0_0 ( | |
2540 | .in0(din0[3:0]), | |
2541 | .in1(din1[3:0]), | |
2542 | .out(dout) | |
2543 | ); | |
2544 | ||
2545 | ||
2546 | ||
2547 | ||
2548 | ||
2549 | ||
2550 | ||
2551 | ||
2552 | ||
2553 | ||
2554 | endmodule | |
2555 | ||
2556 | ||
2557 | ||
2558 | ||
2559 | ||
2560 | // | |
2561 | // and macro for ports = 2,3,4 | |
2562 | // | |
2563 | // | |
2564 | ||
2565 | ||
2566 | ||
2567 | ||
2568 | ||
2569 | module mcu_readdp_dp_and_macro__ports_2__stack_1l__width_1 ( | |
2570 | din0, | |
2571 | din1, | |
2572 | dout); | |
2573 | input [0:0] din0; | |
2574 | input [0:0] din1; | |
2575 | output [0:0] dout; | |
2576 | ||
2577 | ||
2578 | ||
2579 | ||
2580 | ||
2581 | ||
2582 | and2 #(1) d0_0 ( | |
2583 | .in0(din0[0:0]), | |
2584 | .in1(din1[0:0]), | |
2585 | .out(dout[0:0]) | |
2586 | ); | |
2587 | ||
2588 | ||
2589 | ||
2590 | ||
2591 | ||
2592 | ||
2593 | ||
2594 | ||
2595 | ||
2596 | endmodule | |
2597 | ||
2598 | ||
2599 | ||
2600 | ||
2601 | ||
2602 | // | |
2603 | // and macro for ports = 2,3,4 | |
2604 | // | |
2605 | // | |
2606 | ||
2607 | ||
2608 | ||
2609 | ||
2610 | ||
2611 | module mcu_readdp_dp_and_macro__ports_3__stack_1l__width_1 ( | |
2612 | din0, | |
2613 | din1, | |
2614 | din2, | |
2615 | dout); | |
2616 | input [0:0] din0; | |
2617 | input [0:0] din1; | |
2618 | input [0:0] din2; | |
2619 | output [0:0] dout; | |
2620 | ||
2621 | ||
2622 | ||
2623 | ||
2624 | ||
2625 | ||
2626 | and3 #(1) d0_0 ( | |
2627 | .in0(din0[0:0]), | |
2628 | .in1(din1[0:0]), | |
2629 | .in2(din2[0:0]), | |
2630 | .out(dout[0:0]) | |
2631 | ); | |
2632 | ||
2633 | ||
2634 | ||
2635 | ||
2636 | ||
2637 | ||
2638 | ||
2639 | ||
2640 | ||
2641 | endmodule | |
2642 | ||
2643 | ||
2644 | ||
2645 | ||
2646 | ||
2647 | // | |
2648 | // and macro for ports = 2,3,4 | |
2649 | // | |
2650 | // | |
2651 | ||
2652 | ||
2653 | ||
2654 | ||
2655 | ||
2656 | module mcu_readdp_dp_and_macro__ports_2__stack_4l__width_4 ( | |
2657 | din0, | |
2658 | din1, | |
2659 | dout); | |
2660 | input [3:0] din0; | |
2661 | input [3:0] din1; | |
2662 | output [3:0] dout; | |
2663 | ||
2664 | ||
2665 | ||
2666 | ||
2667 | ||
2668 | ||
2669 | and2 #(4) d0_0 ( | |
2670 | .in0(din0[3:0]), | |
2671 | .in1(din1[3:0]), | |
2672 | .out(dout[3:0]) | |
2673 | ); | |
2674 | ||
2675 | ||
2676 | ||
2677 | ||
2678 | ||
2679 | ||
2680 | ||
2681 | ||
2682 | ||
2683 | endmodule | |
2684 | ||
2685 | ||
2686 | ||
2687 | ||
2688 | ||
2689 | // | |
2690 | // xor macro for ports = 2,3 | |
2691 | // | |
2692 | // | |
2693 | ||
2694 | ||
2695 | ||
2696 | ||
2697 | ||
2698 | module mcu_readdp_dp_xor_macro__ports_2__stack_4l__width_4 ( | |
2699 | din0, | |
2700 | din1, | |
2701 | dout); | |
2702 | input [3:0] din0; | |
2703 | input [3:0] din1; | |
2704 | output [3:0] dout; | |
2705 | ||
2706 | ||
2707 | ||
2708 | ||
2709 | ||
2710 | xor2 #(4) d0_0 ( | |
2711 | .in0(din0[3:0]), | |
2712 | .in1(din1[3:0]), | |
2713 | .out(dout[3:0]) | |
2714 | ); | |
2715 | ||
2716 | ||
2717 | ||
2718 | ||
2719 | ||
2720 | ||
2721 | ||
2722 | ||
2723 | endmodule | |
2724 | ||
2725 | ||
2726 | ||
2727 | ||
2728 | ||
2729 | // | |
2730 | // nand macro for ports = 2,3,4 | |
2731 | // | |
2732 | // | |
2733 | ||
2734 | ||
2735 | ||
2736 | ||
2737 | ||
2738 | module mcu_readdp_dp_nand_macro__ports_4__width_1 ( | |
2739 | din0, | |
2740 | din1, | |
2741 | din2, | |
2742 | din3, | |
2743 | dout); | |
2744 | input [0:0] din0; | |
2745 | input [0:0] din1; | |
2746 | input [0:0] din2; | |
2747 | input [0:0] din3; | |
2748 | output [0:0] dout; | |
2749 | ||
2750 | ||
2751 | ||
2752 | ||
2753 | ||
2754 | ||
2755 | nand4 #(1) d0_0 ( | |
2756 | .in0(din0[0:0]), | |
2757 | .in1(din1[0:0]), | |
2758 | .in2(din2[0:0]), | |
2759 | .in3(din3[0:0]), | |
2760 | .out(dout[0:0]) | |
2761 | ); | |
2762 | ||
2763 | ||
2764 | ||
2765 | ||
2766 | ||
2767 | ||
2768 | ||
2769 | ||
2770 | ||
2771 | endmodule | |
2772 | ||
2773 | ||
2774 | ||
2775 | ||
2776 | ||
2777 | // | |
2778 | // nor macro for ports = 2,3 | |
2779 | // | |
2780 | // | |
2781 | ||
2782 | ||
2783 | ||
2784 | ||
2785 | ||
2786 | module mcu_readdp_dp_nor_macro__ports_2__width_1 ( | |
2787 | din0, | |
2788 | din1, | |
2789 | dout); | |
2790 | input [0:0] din0; | |
2791 | input [0:0] din1; | |
2792 | output [0:0] dout; | |
2793 | ||
2794 | ||
2795 | ||
2796 | ||
2797 | ||
2798 | ||
2799 | nor2 #(1) d0_0 ( | |
2800 | .in0(din0[0:0]), | |
2801 | .in1(din1[0:0]), | |
2802 | .out(dout[0:0]) | |
2803 | ); | |
2804 | ||
2805 | ||
2806 | ||
2807 | ||
2808 | ||
2809 | ||
2810 | ||
2811 | endmodule | |
2812 | ||
2813 | ||
2814 | ||
2815 | ||
2816 | ||
2817 | // | |
2818 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) | |
2819 | // | |
2820 | // | |
2821 | ||
2822 | ||
2823 | ||
2824 | ||
2825 | ||
2826 | module mcu_readdp_dp_cmp_macro__width_16 ( | |
2827 | din0, | |
2828 | din1, | |
2829 | dout); | |
2830 | input [15:0] din0; | |
2831 | input [15:0] din1; | |
2832 | output dout; | |
2833 | ||
2834 | ||
2835 | ||
2836 | ||
2837 | ||
2838 | ||
2839 | cmp #(16) m0_0 ( | |
2840 | .in0(din0[15:0]), | |
2841 | .in1(din1[15:0]), | |
2842 | .out(dout) | |
2843 | ); | |
2844 | ||
2845 | ||
2846 | ||
2847 | ||
2848 | ||
2849 | ||
2850 | ||
2851 | ||
2852 | ||
2853 | ||
2854 | endmodule | |
2855 | ||
2856 | ||
2857 | ||
2858 | ||
2859 | ||
2860 | // | |
2861 | // invert macro | |
2862 | // | |
2863 | // | |
2864 | ||
2865 | ||
2866 | ||
2867 | ||
2868 | ||
2869 | module mcu_readdp_dp_inv_macro__width_1 ( | |
2870 | din, | |
2871 | dout); | |
2872 | input [0:0] din; | |
2873 | output [0:0] dout; | |
2874 | ||
2875 | ||
2876 | ||
2877 | ||
2878 | ||
2879 | ||
2880 | inv #(1) d0_0 ( | |
2881 | .in(din[0:0]), | |
2882 | .out(dout[0:0]) | |
2883 | ); | |
2884 | ||
2885 | ||
2886 | ||
2887 | ||
2888 | ||
2889 | ||
2890 | ||
2891 | ||
2892 | ||
2893 | endmodule | |
2894 | ||
2895 | ||
2896 | ||
2897 | ||
2898 | ||
2899 | // | |
2900 | // or macro for ports = 2,3 | |
2901 | // | |
2902 | // | |
2903 | ||
2904 | ||
2905 | ||
2906 | ||
2907 | ||
2908 | module mcu_readdp_dp_or_macro__ports_2__width_1 ( | |
2909 | din0, | |
2910 | din1, | |
2911 | dout); | |
2912 | input [0:0] din0; | |
2913 | input [0:0] din1; | |
2914 | output [0:0] dout; | |
2915 | ||
2916 | ||
2917 | ||
2918 | ||
2919 | ||
2920 | ||
2921 | or2 #(1) d0_0 ( | |
2922 | .in0(din0[0:0]), | |
2923 | .in1(din1[0:0]), | |
2924 | .out(dout[0:0]) | |
2925 | ); | |
2926 | ||
2927 | ||
2928 | ||
2929 | ||
2930 | ||
2931 | ||
2932 | ||
2933 | ||
2934 | ||
2935 | endmodule | |
2936 | ||
2937 | ||
2938 | ||
2939 | ||
2940 | ||
2941 | // | |
2942 | // and macro for ports = 2,3,4 | |
2943 | // | |
2944 | // | |
2945 | ||
2946 | ||
2947 | ||
2948 | ||
2949 | ||
2950 | module mcu_readdp_dp_and_macro__dinv_4x__dnand_2x__ports_2__width_1 ( | |
2951 | din0, | |
2952 | din1, | |
2953 | dout); | |
2954 | input [0:0] din0; | |
2955 | input [0:0] din1; | |
2956 | output [0:0] dout; | |
2957 | ||
2958 | ||
2959 | ||
2960 | ||
2961 | ||
2962 | ||
2963 | and2 #(1) d0_0 ( | |
2964 | .in0(din0[0:0]), | |
2965 | .in1(din1[0:0]), | |
2966 | .out(dout[0:0]) | |
2967 | ); | |
2968 | ||
2969 | ||
2970 | ||
2971 | ||
2972 | ||
2973 | ||
2974 | ||
2975 | ||
2976 | ||
2977 | endmodule | |
2978 | ||
2979 | ||
2980 | ||
2981 | ||
2982 | ||
2983 | // | |
2984 | // nor macro for ports = 2,3 | |
2985 | // | |
2986 | // | |
2987 | ||
2988 | ||
2989 | ||
2990 | ||
2991 | ||
2992 | module mcu_readdp_dp_nor_macro__dnor_4x__ports_3__width_1 ( | |
2993 | din0, | |
2994 | din1, | |
2995 | din2, | |
2996 | dout); | |
2997 | input [0:0] din0; | |
2998 | input [0:0] din1; | |
2999 | input [0:0] din2; | |
3000 | output [0:0] dout; | |
3001 | ||
3002 | ||
3003 | ||
3004 | ||
3005 | ||
3006 | ||
3007 | nor3 #(1) d0_0 ( | |
3008 | .in0(din0[0:0]), | |
3009 | .in1(din1[0:0]), | |
3010 | .in2(din2[0:0]), | |
3011 | .out(dout[0:0]) | |
3012 | ); | |
3013 | ||
3014 | ||
3015 | ||
3016 | ||
3017 | ||
3018 | ||
3019 | ||
3020 | endmodule | |
3021 | ||
3022 | ||
3023 | ||
3024 | ||
3025 | ||
3026 | // | |
3027 | // and macro for ports = 2,3,4 | |
3028 | // | |
3029 | // | |
3030 | ||
3031 | ||
3032 | ||
3033 | ||
3034 | ||
3035 | module mcu_readdp_dp_and_macro__ports_3__width_1 ( | |
3036 | din0, | |
3037 | din1, | |
3038 | din2, | |
3039 | dout); | |
3040 | input [0:0] din0; | |
3041 | input [0:0] din1; | |
3042 | input [0:0] din2; | |
3043 | output [0:0] dout; | |
3044 | ||
3045 | ||
3046 | ||
3047 | ||
3048 | ||
3049 | ||
3050 | and3 #(1) d0_0 ( | |
3051 | .in0(din0[0:0]), | |
3052 | .in1(din1[0:0]), | |
3053 | .in2(din2[0:0]), | |
3054 | .out(dout[0:0]) | |
3055 | ); | |
3056 | ||
3057 | ||
3058 | ||
3059 | ||
3060 | ||
3061 | ||
3062 | ||
3063 | ||
3064 | ||
3065 | endmodule | |
3066 | ||
3067 | ||
3068 | ||
3069 | ||
3070 | ||
3071 | // | |
3072 | // nor macro for ports = 2,3 | |
3073 | // | |
3074 | // | |
3075 | ||
3076 | ||
3077 | ||
3078 | ||
3079 | ||
3080 | module mcu_readdp_dp_nor_macro__ports_3__width_1 ( | |
3081 | din0, | |
3082 | din1, | |
3083 | din2, | |
3084 | dout); | |
3085 | input [0:0] din0; | |
3086 | input [0:0] din1; | |
3087 | input [0:0] din2; | |
3088 | output [0:0] dout; | |
3089 | ||
3090 | ||
3091 | ||
3092 | ||
3093 | ||
3094 | ||
3095 | nor3 #(1) d0_0 ( | |
3096 | .in0(din0[0:0]), | |
3097 | .in1(din1[0:0]), | |
3098 | .in2(din2[0:0]), | |
3099 | .out(dout[0:0]) | |
3100 | ); | |
3101 | ||
3102 | ||
3103 | ||
3104 | ||
3105 | ||
3106 | ||
3107 | ||
3108 | endmodule | |
3109 | ||
3110 | ||
3111 | ||
3112 | ||
3113 | ||
3114 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
3115 | // also for pass-gate with decoder | |
3116 | ||
3117 | ||
3118 | ||
3119 | ||
3120 | ||
3121 | // any PARAMS parms go into naming of macro | |
3122 | ||
3123 | module mcu_readdp_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__stack_64c__width_64 ( | |
3124 | din0, | |
3125 | din1, | |
3126 | sel0, | |
3127 | dout); | |
3128 | wire psel0_unused; | |
3129 | wire psel1; | |
3130 | ||
3131 | input [63:0] din0; | |
3132 | input [63:0] din1; | |
3133 | input sel0; | |
3134 | output [63:0] dout; | |
3135 | ||
3136 | ||
3137 | ||
3138 | ||
3139 | ||
3140 | cl_dp1_penc2_8x c0_0 ( | |
3141 | .sel0(sel0), | |
3142 | .psel0(psel0_unused), | |
3143 | .psel1(psel1) | |
3144 | ); | |
3145 | ||
3146 | mux2e #(64) d0_0 ( | |
3147 | .sel(psel1), | |
3148 | .in0(din0[63:0]), | |
3149 | .in1(din1[63:0]), | |
3150 | .dout(dout[63:0]) | |
3151 | ); | |
3152 | ||
3153 | ||
3154 | ||
3155 | ||
3156 | ||
3157 | ||
3158 | ||
3159 | ||
3160 | ||
3161 | ||
3162 | ||
3163 | ||
3164 | ||
3165 | endmodule | |
3166 | ||
3167 | ||
3168 | ||
3169 | ||
3170 | ||
3171 | ||
3172 | // any PARAMS parms go into naming of macro | |
3173 | ||
3174 | module mcu_readdp_dp_msff_macro__stack_66c__width_65 ( | |
3175 | din, | |
3176 | clk, | |
3177 | en, | |
3178 | se, | |
3179 | scan_in, | |
3180 | siclk, | |
3181 | soclk, | |
3182 | pce_ov, | |
3183 | stop, | |
3184 | dout, | |
3185 | scan_out); | |
3186 | wire l1clk; | |
3187 | wire siclk_out; | |
3188 | wire soclk_out; | |
3189 | wire [63:0] so; | |
3190 | ||
3191 | input [64:0] din; | |
3192 | ||
3193 | ||
3194 | input clk; | |
3195 | input en; | |
3196 | input se; | |
3197 | input scan_in; | |
3198 | input siclk; | |
3199 | input soclk; | |
3200 | input pce_ov; | |
3201 | input stop; | |
3202 | ||
3203 | ||
3204 | ||
3205 | output [64:0] dout; | |
3206 | ||
3207 | ||
3208 | output scan_out; | |
3209 | ||
3210 | ||
3211 | ||
3212 | ||
3213 | cl_dp1_l1hdr_8x c0_0 ( | |
3214 | .l2clk(clk), | |
3215 | .pce(en), | |
3216 | .aclk(siclk), | |
3217 | .bclk(soclk), | |
3218 | .l1clk(l1clk), | |
3219 | .se(se), | |
3220 | .pce_ov(pce_ov), | |
3221 | .stop(stop), | |
3222 | .siclk_out(siclk_out), | |
3223 | .soclk_out(soclk_out) | |
3224 | ); | |
3225 | dff #(65) d0_0 ( | |
3226 | .l1clk(l1clk), | |
3227 | .siclk(siclk_out), | |
3228 | .soclk(soclk_out), | |
3229 | .d(din[64:0]), | |
3230 | .si({scan_in,so[63:0]}), | |
3231 | .so({so[63:0],scan_out}), | |
3232 | .q(dout[64:0]) | |
3233 | ); | |
3234 | ||
3235 | ||
3236 | ||
3237 | ||
3238 | ||
3239 | ||
3240 | ||
3241 | ||
3242 | ||
3243 | ||
3244 | ||
3245 | ||
3246 | ||
3247 | ||
3248 | ||
3249 | ||
3250 | ||
3251 | ||
3252 | ||
3253 | ||
3254 | endmodule | |
3255 | ||
3256 | ||
3257 | ||
3258 | ||
3259 | ||
3260 | ||
3261 | ||
3262 |