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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: fflp_cam_srch_sm.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | /**********************************************************************/ | |
36 | /*project name: N2 */ | |
37 | /*module name: fflp_cam_srch_sm */ | |
38 | /*description: */ | |
39 | /* Controls CAM accesses for both CPU commands and */ | |
40 | /* forward search */ | |
41 | /* */ | |
42 | /*parent module in: fflp_cam_srch */ | |
43 | /*child modules in: none */ | |
44 | /*interface modules: */ | |
45 | /*author name: Jeanne Cai */ | |
46 | /*date created: 03-10-04 */ | |
47 | /* */ | |
48 | /* Copyright (c) 2004, Sun Microsystems, Inc. */ | |
49 | /* Sun Proprietary and Confidential */ | |
50 | /* */ | |
51 | /*modifications: */ | |
52 | /* */ | |
53 | /* */ | |
54 | `include "fflp.h" | |
55 | module fflp_cam_srch_sm | |
56 | ( | |
57 | cclk, | |
58 | reset, | |
59 | cam_srch_latency, | |
60 | do_srch_cycle, | |
61 | do_cpu_cycle, | |
62 | cpu_cmd, | |
63 | ||
64 | cam_compare_sm, | |
65 | cam_pio_wr_sm, | |
66 | cam_pio_sel_sm, | |
67 | data_inp_sel, | |
68 | data_inp_en, | |
69 | srch_wait_done, | |
70 | cpu_cmd_done_sm, | |
71 | kick_off_ram_srch_sm | |
72 | ); | |
73 | ||
74 | input cclk; | |
75 | input reset; | |
76 | input[3:0] cam_srch_latency; | |
77 | input do_srch_cycle; | |
78 | input do_cpu_cycle; | |
79 | input[2:0] cpu_cmd; | |
80 | ||
81 | output cam_compare_sm; | |
82 | output cam_pio_wr_sm; | |
83 | output cam_pio_sel_sm; | |
84 | output[1:0] data_inp_sel; | |
85 | output data_inp_en; | |
86 | output srch_wait_done; | |
87 | output cpu_cmd_done_sm; | |
88 | output kick_off_ram_srch_sm; | |
89 | ||
90 | reg cam_compare_sm; | |
91 | reg cam_pio_wr_sm; | |
92 | reg cam_pio_sel_sm; | |
93 | reg[1:0] data_inp_sel; | |
94 | reg data_inp_en; | |
95 | reg cpu_cmd_done_sm; | |
96 | reg kick_off_ram_srch_sm; | |
97 | reg inc_wait_cnt; | |
98 | reg[2:0] next_state; | |
99 | ||
100 | wire[3:0] srch_wait_cnt_in; | |
101 | wire[3:0] srch_wait_cnt; | |
102 | wire[2:0] state; | |
103 | wire srch_wait_done; | |
104 | ||
105 | assign srch_wait_done = (srch_wait_cnt == cam_srch_latency); | |
106 | ||
107 | //state machine states | |
108 | parameter | |
109 | READY = 3'b000, | |
110 | SRCH_CYC_2 = 3'b001, | |
111 | SRCH_CYC_3 = 3'b010, | |
112 | CMD_WR_CYC_2 = 3'b011, | |
113 | CMD_WR_CYC_3 = 3'b100, | |
114 | CMD_WR_CYC_4 = 3'b101, | |
115 | CMD_COMP_CYC_2 = 3'b110, | |
116 | CMD_COMP_CYC_3 = 3'b111; | |
117 | ||
118 | always @ ( | |
119 | state or | |
120 | cpu_cmd or | |
121 | do_srch_cycle or | |
122 | do_cpu_cycle or | |
123 | srch_wait_done | |
124 | ) | |
125 | ||
126 | begin | |
127 | ||
128 | cam_compare_sm = 1'b0; | |
129 | cam_pio_wr_sm = 1'b0; | |
130 | cam_pio_sel_sm = 1'b0; | |
131 | data_inp_sel = 2'b0; | |
132 | data_inp_en = 1'b0; | |
133 | cpu_cmd_done_sm = 1'b0; | |
134 | inc_wait_cnt = 1'b0; | |
135 | kick_off_ram_srch_sm = 1'b0; | |
136 | next_state = READY; | |
137 | ||
138 | case (state) //synopsys parallel_case full_case | |
139 | // 0in < case -full -parallel -message "0in ERROR: case check in fflp_cam_srch_sm:state" | |
140 | ||
141 | READY: | |
142 | begin | |
143 | if (do_srch_cycle) | |
144 | begin | |
145 | cam_compare_sm = 1'b1; | |
146 | cam_pio_wr_sm = 1'b0; | |
147 | cam_pio_sel_sm = 1'b0; | |
148 | data_inp_sel = 2'b00; | |
149 | data_inp_en = 1'b1; | |
150 | cpu_cmd_done_sm = 1'b0; | |
151 | inc_wait_cnt = 1'b1; | |
152 | next_state = SRCH_CYC_2; | |
153 | end | |
154 | else if (do_cpu_cycle) | |
155 | begin | |
156 | case (cpu_cmd) //synopsys parallel_case full_case | |
157 | ||
158 | `NOP_CMD1, `NOP_CMD2, `NOP_CMD3: | |
159 | begin | |
160 | cam_compare_sm = 1'b0; | |
161 | cam_pio_wr_sm = 1'b0; | |
162 | cam_pio_sel_sm = 1'b0; | |
163 | data_inp_sel = 2'b00; | |
164 | data_inp_en = 1'b0; | |
165 | cpu_cmd_done_sm = 1'b1; | |
166 | inc_wait_cnt = 1'b0; | |
167 | next_state = READY; | |
168 | end | |
169 | ||
170 | `WR_CAM_KEY: | |
171 | begin | |
172 | cam_compare_sm = 1'b0; | |
173 | cam_pio_wr_sm = 1'b1; | |
174 | cam_pio_sel_sm = 1'b0; | |
175 | data_inp_sel = 2'b10; | |
176 | data_inp_en = 1'b1; | |
177 | cpu_cmd_done_sm = 1'b0; | |
178 | inc_wait_cnt = 1'b0; | |
179 | next_state = CMD_WR_CYC_2; | |
180 | end | |
181 | ||
182 | `COMP_SINGLE_KEY: | |
183 | begin | |
184 | cam_compare_sm = 1'b1; | |
185 | cam_pio_wr_sm = 1'b0; | |
186 | cam_pio_sel_sm = 1'b0; | |
187 | data_inp_sel = 2'b10; | |
188 | data_inp_en = 1'b1; | |
189 | cpu_cmd_done_sm = 1'b0; | |
190 | inc_wait_cnt = 1'b1; | |
191 | next_state = CMD_COMP_CYC_2; | |
192 | end | |
193 | ||
194 | default: | |
195 | next_state = state; | |
196 | ||
197 | endcase //cpu_cmd | |
198 | end | |
199 | else | |
200 | next_state = state; | |
201 | end //end READY | |
202 | ||
203 | SRCH_CYC_2: | |
204 | begin | |
205 | cam_compare_sm = 1'b1; | |
206 | cam_pio_wr_sm = 1'b0; | |
207 | cam_pio_sel_sm = 1'b0; | |
208 | data_inp_sel = 2'b00; | |
209 | data_inp_en = 1'b0; | |
210 | cpu_cmd_done_sm = 1'b0; | |
211 | inc_wait_cnt = 1'b1; | |
212 | next_state = SRCH_CYC_3; | |
213 | end | |
214 | ||
215 | SRCH_CYC_3: | |
216 | begin | |
217 | cam_compare_sm = 1'b0; | |
218 | cam_pio_wr_sm = 1'b0; | |
219 | cam_pio_sel_sm = 1'b0; | |
220 | data_inp_sel = 2'b00; | |
221 | data_inp_en = 1'b0; | |
222 | cpu_cmd_done_sm = 1'b0; | |
223 | if (srch_wait_done) | |
224 | begin | |
225 | inc_wait_cnt = 1'b0; | |
226 | kick_off_ram_srch_sm = 1'b1; | |
227 | next_state = READY; | |
228 | end | |
229 | else | |
230 | begin | |
231 | inc_wait_cnt = 1'b1; | |
232 | kick_off_ram_srch_sm = 1'b0; | |
233 | next_state = state; | |
234 | end | |
235 | end | |
236 | ||
237 | CMD_WR_CYC_2: | |
238 | begin | |
239 | cam_compare_sm = 1'b0; | |
240 | cam_pio_wr_sm = 1'b1; | |
241 | cam_pio_sel_sm = 1'b0; | |
242 | data_inp_sel = 2'b10; | |
243 | data_inp_en = 1'b0; | |
244 | cpu_cmd_done_sm = 1'b0; | |
245 | inc_wait_cnt = 1'b0; | |
246 | next_state = CMD_WR_CYC_3; | |
247 | end | |
248 | ||
249 | CMD_WR_CYC_3: | |
250 | begin | |
251 | cam_compare_sm = 1'b0; | |
252 | cam_pio_wr_sm = 1'b1; | |
253 | cam_pio_sel_sm = 1'b1; | |
254 | data_inp_sel = 2'b11; | |
255 | data_inp_en = 1'b1; | |
256 | cpu_cmd_done_sm = 1'b0; | |
257 | inc_wait_cnt = 1'b0; | |
258 | next_state = CMD_WR_CYC_4; | |
259 | end | |
260 | ||
261 | CMD_WR_CYC_4: | |
262 | begin | |
263 | cam_compare_sm = 1'b0; | |
264 | cam_pio_wr_sm = 1'b1; | |
265 | cam_pio_sel_sm = 1'b1; | |
266 | data_inp_sel = 2'b11; | |
267 | data_inp_en = 1'b0; | |
268 | cpu_cmd_done_sm = 1'b1; | |
269 | inc_wait_cnt = 1'b0; | |
270 | next_state = READY; | |
271 | end | |
272 | ||
273 | CMD_COMP_CYC_2: | |
274 | begin | |
275 | cam_compare_sm = 1'b1; | |
276 | cam_pio_wr_sm = 1'b0; | |
277 | cam_pio_sel_sm = 1'b0; | |
278 | data_inp_sel = 2'b10; | |
279 | data_inp_en = 1'b0; | |
280 | cpu_cmd_done_sm = 1'b0; | |
281 | inc_wait_cnt = 1'b1; | |
282 | next_state = CMD_COMP_CYC_3; | |
283 | end | |
284 | ||
285 | CMD_COMP_CYC_3: | |
286 | begin | |
287 | cam_compare_sm = 1'b0; | |
288 | cam_pio_wr_sm = 1'b0; | |
289 | cam_pio_sel_sm = 1'b0; | |
290 | data_inp_sel = 2'b00; | |
291 | data_inp_en = 1'b0; | |
292 | if (srch_wait_done) | |
293 | begin | |
294 | inc_wait_cnt = 1'b0; | |
295 | cpu_cmd_done_sm = 1'b1; | |
296 | next_state = READY; | |
297 | end | |
298 | else | |
299 | begin | |
300 | inc_wait_cnt = 1'b1; | |
301 | cpu_cmd_done_sm = 1'b0; | |
302 | next_state = state; | |
303 | end | |
304 | end | |
305 | ||
306 | default: | |
307 | next_state = READY; | |
308 | ||
309 | endcase | |
310 | end | |
311 | ||
312 | ||
313 | dffr #(3) state_reg (cclk, reset, next_state, state); | |
314 | dffr #(4) srch_wait_cnt_reg (cclk, reset, srch_wait_cnt_in, srch_wait_cnt); | |
315 | ||
316 | assign srch_wait_cnt_in = {4{inc_wait_cnt}} & (srch_wait_cnt + 4'd1); | |
317 | ||
318 | ||
319 | endmodule | |
320 | ||
321 |