Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: niu_pio_ldgim_decoder.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | /*%W% %G%*/ | |
36 | ||
37 | /***************************************************************** | |
38 | * | |
39 | * File Name : niu_pio_ldgim_decoder.v | |
40 | * Author Name : John Lo | |
41 | * Description : It contains logical device group interrupt | |
42 | * management register read/write decoder, | |
43 | * | |
44 | * Parent Module: niu_pio_ldgim_decoder.v | |
45 | * Child Module: | |
46 | * Interface Mod: many. | |
47 | * Date Created : 3/30/04 | |
48 | * | |
49 | * Copyright (c) 2020, Sun Microsystems, Inc. | |
50 | * Sun Proprietary and Confidential | |
51 | * | |
52 | * Modification : | |
53 | * | |
54 | ****************************************************************/ | |
55 | ||
56 | module niu_pio_ldgim_decoder (/*AUTOARG*/ | |
57 | // Outputs | |
58 | ldgim_ack, ldgim_rdata, ldgim_err, ld_ldgim0, ld_ldgim1, | |
59 | ld_ldgim2, ld_ldgim3, ld_ldgim4, ld_ldgim5, ld_ldgim6, ld_ldgim7, | |
60 | ld_ldgim8, ld_ldgim9, ld_ldgim10, ld_ldgim11, ld_ldgim12, | |
61 | ld_ldgim13, ld_ldgim14, ld_ldgim15, ld_ldgim16, ld_ldgim17, | |
62 | ld_ldgim18, ld_ldgim19, ld_ldgim20, ld_ldgim21, ld_ldgim22, | |
63 | ld_ldgim23, ld_ldgim24, ld_ldgim25, ld_ldgim26, ld_ldgim27, | |
64 | ld_ldgim28, ld_ldgim29, ld_ldgim30, ld_ldgim31, ld_ldgim32, | |
65 | ld_ldgim33, ld_ldgim34, ld_ldgim35, ld_ldgim36, ld_ldgim37, | |
66 | ld_ldgim38, ld_ldgim39, ld_ldgim40, ld_ldgim41, ld_ldgim42, | |
67 | ld_ldgim43, ld_ldgim44, ld_ldgim45, ld_ldgim46, ld_ldgim47, | |
68 | ld_ldgim48, ld_ldgim49, ld_ldgim50, ld_ldgim51, ld_ldgim52, | |
69 | ld_ldgim53, ld_ldgim54, ld_ldgim55, ld_ldgim56, ld_ldgim57, | |
70 | ld_ldgim58, ld_ldgim59, ld_ldgim60, ld_ldgim61, ld_ldgim62, | |
71 | ld_ldgim63, intr_reg_sel, | |
72 | // Inputs | |
73 | clk, reset, ldgim_sel_reg, addr, rd, arm0, arm1, arm2, | |
74 | arm3, arm4, arm5, arm6, arm7, arm8, arm9, arm10, arm11, arm12, | |
75 | arm13, arm14, arm15, arm16, arm17, arm18, arm19, arm20, arm21, | |
76 | arm22, arm23, arm24, arm25, arm26, arm27, arm28, arm29, arm30, | |
77 | arm31, arm32, arm33, arm34, arm35, arm36, arm37, arm38, arm39, | |
78 | arm40, arm41, arm42, arm43, arm44, arm45, arm46, arm47, arm48, | |
79 | arm49, arm50, arm51, arm52, arm53, arm54, arm55, arm56, arm57, | |
80 | arm58, arm59, arm60, arm61, arm62, arm63, timer0, timer1, timer2, | |
81 | timer3, timer4, timer5, timer6, timer7, timer8, timer9, timer10, | |
82 | timer11, timer12, timer13, timer14, timer15, timer16, timer17, | |
83 | timer18, timer19, timer20, timer21, timer22, timer23, timer24, | |
84 | timer25, timer26, timer27, timer28, timer29, timer30, timer31, | |
85 | timer32, timer33, timer34, timer35, timer36, timer37, timer38, | |
86 | timer39, timer40, timer41, timer42, timer43, timer44, timer45, | |
87 | timer46, timer47, timer48, timer49, timer50, timer51, timer52, | |
88 | timer53, timer54, timer55, timer56, timer57, timer58, timer59, | |
89 | timer60, timer61, timer62, timer63 | |
90 | ); | |
91 | input clk; | |
92 | input reset; | |
93 | input ldgim_sel_reg; | |
94 | // pio broadcast signals | |
95 | input [18:0] addr; | |
96 | input rd; | |
97 | input arm0 ; | |
98 | input arm1 ; | |
99 | input arm2 ; | |
100 | input arm3 ; | |
101 | input arm4 ; | |
102 | input arm5 ; | |
103 | input arm6 ; | |
104 | input arm7 ; | |
105 | input arm8 ; | |
106 | input arm9 ; | |
107 | input arm10; | |
108 | input arm11; | |
109 | input arm12; | |
110 | input arm13; | |
111 | input arm14; | |
112 | input arm15; | |
113 | input arm16; | |
114 | input arm17; | |
115 | input arm18; | |
116 | input arm19; | |
117 | input arm20; | |
118 | input arm21; | |
119 | input arm22; | |
120 | input arm23; | |
121 | input arm24; | |
122 | input arm25; | |
123 | input arm26; | |
124 | input arm27; | |
125 | input arm28; | |
126 | input arm29; | |
127 | input arm30; | |
128 | input arm31; | |
129 | input arm32; | |
130 | input arm33; | |
131 | input arm34; | |
132 | input arm35; | |
133 | input arm36; | |
134 | input arm37; | |
135 | input arm38; | |
136 | input arm39; | |
137 | input arm40; | |
138 | input arm41; | |
139 | input arm42; | |
140 | input arm43; | |
141 | input arm44; | |
142 | input arm45; | |
143 | input arm46; | |
144 | input arm47; | |
145 | input arm48; | |
146 | input arm49; | |
147 | input arm50; | |
148 | input arm51; | |
149 | input arm52; | |
150 | input arm53; | |
151 | input arm54; | |
152 | input arm55; | |
153 | input arm56; | |
154 | input arm57; | |
155 | input arm58; | |
156 | input arm59; | |
157 | input arm60; | |
158 | input arm61; | |
159 | input arm62; | |
160 | input arm63; | |
161 | ||
162 | ||
163 | input [5:0] timer0 ; | |
164 | input [5:0] timer1 ; | |
165 | input [5:0] timer2 ; | |
166 | input [5:0] timer3 ; | |
167 | input [5:0] timer4 ; | |
168 | input [5:0] timer5 ; | |
169 | input [5:0] timer6 ; | |
170 | input [5:0] timer7 ; | |
171 | input [5:0] timer8 ; | |
172 | input [5:0] timer9 ; | |
173 | input [5:0] timer10; | |
174 | input [5:0] timer11; | |
175 | input [5:0] timer12; | |
176 | input [5:0] timer13; | |
177 | input [5:0] timer14; | |
178 | input [5:0] timer15; | |
179 | input [5:0] timer16; | |
180 | input [5:0] timer17; | |
181 | input [5:0] timer18; | |
182 | input [5:0] timer19; | |
183 | input [5:0] timer20; | |
184 | input [5:0] timer21; | |
185 | input [5:0] timer22; | |
186 | input [5:0] timer23; | |
187 | input [5:0] timer24; | |
188 | input [5:0] timer25; | |
189 | input [5:0] timer26; | |
190 | input [5:0] timer27; | |
191 | input [5:0] timer28; | |
192 | input [5:0] timer29; | |
193 | input [5:0] timer30; | |
194 | input [5:0] timer31; | |
195 | input [5:0] timer32; | |
196 | input [5:0] timer33; | |
197 | input [5:0] timer34; | |
198 | input [5:0] timer35; | |
199 | input [5:0] timer36; | |
200 | input [5:0] timer37; | |
201 | input [5:0] timer38; | |
202 | input [5:0] timer39; | |
203 | input [5:0] timer40; | |
204 | input [5:0] timer41; | |
205 | input [5:0] timer42; | |
206 | input [5:0] timer43; | |
207 | input [5:0] timer44; | |
208 | input [5:0] timer45; | |
209 | input [5:0] timer46; | |
210 | input [5:0] timer47; | |
211 | input [5:0] timer48; | |
212 | input [5:0] timer49; | |
213 | input [5:0] timer50; | |
214 | input [5:0] timer51; | |
215 | input [5:0] timer52; | |
216 | input [5:0] timer53; | |
217 | input [5:0] timer54; | |
218 | input [5:0] timer55; | |
219 | input [5:0] timer56; | |
220 | input [5:0] timer57; | |
221 | input [5:0] timer58; | |
222 | input [5:0] timer59; | |
223 | input [5:0] timer60; | |
224 | input [5:0] timer61; | |
225 | input [5:0] timer62; | |
226 | input [5:0] timer63; | |
227 | ||
228 | ||
229 | output ldgim_ack; | |
230 | output [63:0] ldgim_rdata; | |
231 | output ldgim_err; | |
232 | // | |
233 | output ld_ldgim0 ; | |
234 | output ld_ldgim1 ; | |
235 | output ld_ldgim2 ; | |
236 | output ld_ldgim3 ; | |
237 | output ld_ldgim4 ; | |
238 | output ld_ldgim5 ; | |
239 | output ld_ldgim6 ; | |
240 | output ld_ldgim7 ; | |
241 | output ld_ldgim8 ; | |
242 | output ld_ldgim9 ; | |
243 | output ld_ldgim10; | |
244 | output ld_ldgim11; | |
245 | output ld_ldgim12; | |
246 | output ld_ldgim13; | |
247 | output ld_ldgim14; | |
248 | output ld_ldgim15; | |
249 | output ld_ldgim16; | |
250 | output ld_ldgim17; | |
251 | output ld_ldgim18; | |
252 | output ld_ldgim19; | |
253 | output ld_ldgim20; | |
254 | output ld_ldgim21; | |
255 | output ld_ldgim22; | |
256 | output ld_ldgim23; | |
257 | output ld_ldgim24; | |
258 | output ld_ldgim25; | |
259 | output ld_ldgim26; | |
260 | output ld_ldgim27; | |
261 | output ld_ldgim28; | |
262 | output ld_ldgim29; | |
263 | output ld_ldgim30; | |
264 | output ld_ldgim31; | |
265 | output ld_ldgim32; | |
266 | output ld_ldgim33; | |
267 | output ld_ldgim34; | |
268 | output ld_ldgim35; | |
269 | output ld_ldgim36; | |
270 | output ld_ldgim37; | |
271 | output ld_ldgim38; | |
272 | output ld_ldgim39; | |
273 | output ld_ldgim40; | |
274 | output ld_ldgim41; | |
275 | output ld_ldgim42; | |
276 | output ld_ldgim43; | |
277 | output ld_ldgim44; | |
278 | output ld_ldgim45; | |
279 | output ld_ldgim46; | |
280 | output ld_ldgim47; | |
281 | output ld_ldgim48; | |
282 | output ld_ldgim49; | |
283 | output ld_ldgim50; | |
284 | output ld_ldgim51; | |
285 | output ld_ldgim52; | |
286 | output ld_ldgim53; | |
287 | output ld_ldgim54; | |
288 | output ld_ldgim55; | |
289 | output ld_ldgim56; | |
290 | output ld_ldgim57; | |
291 | output ld_ldgim58; | |
292 | output ld_ldgim59; | |
293 | output ld_ldgim60; | |
294 | output ld_ldgim61; | |
295 | output ld_ldgim62; | |
296 | output ld_ldgim63; | |
297 | output intr_reg_sel; | |
298 | ||
299 | // common reg declaration | |
300 | reg [63:0] rd_data; | |
301 | reg non_qualified_addr_err; | |
302 | // common wrie declaration | |
303 | wire [63:0] ldgim_rdata; | |
304 | wire rd_en; | |
305 | wire wr_en; | |
306 | wire rasr; | |
307 | // output reg declaration | |
308 | reg ld_ldgim0 ; | |
309 | reg ld_ldgim1 ; | |
310 | reg ld_ldgim2 ; | |
311 | reg ld_ldgim3 ; | |
312 | reg ld_ldgim4 ; | |
313 | reg ld_ldgim5 ; | |
314 | reg ld_ldgim6 ; | |
315 | reg ld_ldgim7 ; | |
316 | reg ld_ldgim8 ; | |
317 | reg ld_ldgim9 ; | |
318 | reg ld_ldgim10; | |
319 | reg ld_ldgim11; | |
320 | reg ld_ldgim12; | |
321 | reg ld_ldgim13; | |
322 | reg ld_ldgim14; | |
323 | reg ld_ldgim15; | |
324 | reg ld_ldgim16; | |
325 | reg ld_ldgim17; | |
326 | reg ld_ldgim18; | |
327 | reg ld_ldgim19; | |
328 | reg ld_ldgim20; | |
329 | reg ld_ldgim21; | |
330 | reg ld_ldgim22; | |
331 | reg ld_ldgim23; | |
332 | reg ld_ldgim24; | |
333 | reg ld_ldgim25; | |
334 | reg ld_ldgim26; | |
335 | reg ld_ldgim27; | |
336 | reg ld_ldgim28; | |
337 | reg ld_ldgim29; | |
338 | reg ld_ldgim30; | |
339 | reg ld_ldgim31; | |
340 | reg ld_ldgim32; | |
341 | reg ld_ldgim33; | |
342 | reg ld_ldgim34; | |
343 | reg ld_ldgim35; | |
344 | reg ld_ldgim36; | |
345 | reg ld_ldgim37; | |
346 | reg ld_ldgim38; | |
347 | reg ld_ldgim39; | |
348 | reg ld_ldgim40; | |
349 | reg ld_ldgim41; | |
350 | reg ld_ldgim42; | |
351 | reg ld_ldgim43; | |
352 | reg ld_ldgim44; | |
353 | reg ld_ldgim45; | |
354 | reg ld_ldgim46; | |
355 | reg ld_ldgim47; | |
356 | reg ld_ldgim48; | |
357 | reg ld_ldgim49; | |
358 | reg ld_ldgim50; | |
359 | reg ld_ldgim51; | |
360 | reg ld_ldgim52; | |
361 | reg ld_ldgim53; | |
362 | reg ld_ldgim54; | |
363 | reg ld_ldgim55; | |
364 | reg ld_ldgim56; | |
365 | reg ld_ldgim57; | |
366 | reg ld_ldgim58; | |
367 | reg ld_ldgim59; | |
368 | reg ld_ldgim60; | |
369 | reg ld_ldgim61; | |
370 | reg ld_ldgim62; | |
371 | reg ld_ldgim63; | |
372 | reg intr_reg_sel; | |
373 | ||
374 | `ifdef NEPTUNE | |
375 | /* ---------------------------------------------------------- */ | |
376 | reg ldgim_sel_reg_int; | |
377 | reg rd_int; | |
378 | reg [18:0] addr_int; | |
379 | ||
380 | always @(posedge clk) | |
381 | if (reset) | |
382 | begin | |
383 | ldgim_sel_reg_int <= 1'b0; | |
384 | rd_int <= 1'b0; | |
385 | addr_int <= 19'b0; | |
386 | end | |
387 | else | |
388 | begin | |
389 | ldgim_sel_reg_int <= ldgim_sel_reg ; | |
390 | rd_int <= rd ; | |
391 | addr_int <= addr; | |
392 | end | |
393 | ||
394 | `else | |
395 | /* ---------------------------------------------------------- */ | |
396 | ||
397 | wire ldgim_sel_reg_int; | |
398 | wire rd_int; | |
399 | wire [18:0] addr_int; | |
400 | ||
401 | assign ldgim_sel_reg_int = ldgim_sel_reg ; | |
402 | assign rd_int = rd ; | |
403 | assign addr_int = addr ; | |
404 | /* ----------------------------------------------------------- */ | |
405 | `endif | |
406 | ||
407 | ||
408 | niu_rw_ctl ldgim_rw_ctl( | |
409 | // Outputs | |
410 | .wr_en (wr_en), | |
411 | .rd_en (rd_en), | |
412 | .ack (ldgim_ack), | |
413 | .rdata (ldgim_rdata[63:0]), | |
414 | .err (ldgim_err), | |
415 | .rasr (rasr), | |
416 | // Inputs | |
417 | .clk (clk), | |
418 | .sel (ldgim_sel_reg_int), | |
419 | .rd (rd_int), | |
420 | .rd_data (rd_data[63:0]), | |
421 | .non_qualified_addr_err(non_qualified_addr_err)); | |
422 | ||
423 | ||
424 | always @ (/*AUTOSENSE*/addr_int or arm0 or arm1 or arm10 or arm11 or arm12 | |
425 | or arm13 or arm14 or arm15 or arm16 or arm17 or arm18 | |
426 | or arm19 or arm2 or arm20 or arm21 or arm22 or arm23 | |
427 | or arm24 or arm25 or arm26 or arm27 or arm28 or arm29 | |
428 | or arm3 or arm30 or arm31 or arm32 or arm33 or arm34 | |
429 | or arm35 or arm36 or arm37 or arm38 or arm39 or arm4 | |
430 | or arm40 or arm41 or arm42 or arm43 or arm44 or arm45 | |
431 | or arm46 or arm47 or arm48 or arm49 or arm5 or arm50 | |
432 | or arm51 or arm52 or arm53 or arm54 or arm55 or arm56 | |
433 | or arm57 or arm58 or arm59 or arm6 or arm60 or arm61 | |
434 | or arm62 or arm63 or arm7 or arm8 or arm9 or timer0 | |
435 | or timer1 or timer10 or timer11 or timer12 or timer13 | |
436 | or timer14 or timer15 or timer16 or timer17 or timer18 | |
437 | or timer19 or timer2 or timer20 or timer21 or timer22 | |
438 | or timer23 or timer24 or timer25 or timer26 or timer27 | |
439 | or timer28 or timer29 or timer3 or timer30 or timer31 | |
440 | or timer32 or timer33 or timer34 or timer35 or timer36 | |
441 | or timer37 or timer38 or timer39 or timer4 or timer40 | |
442 | or timer41 or timer42 or timer43 or timer44 or timer45 | |
443 | or timer46 or timer47 or timer48 or timer49 or timer5 | |
444 | or timer50 or timer51 or timer52 or timer53 or timer54 | |
445 | or timer55 or timer56 or timer57 or timer58 or timer59 | |
446 | or timer6 or timer60 or timer61 or timer62 or timer63 | |
447 | or timer7 or timer8 or timer9 or wr_en) | |
448 | begin | |
449 | non_qualified_addr_err = 0; | |
450 | rd_data = 64'hdead_beef_dead_beef; | |
451 | ||
452 | ld_ldgim0 = 0; | |
453 | ld_ldgim1 = 0; | |
454 | ld_ldgim2 = 0; | |
455 | ld_ldgim3 = 0; | |
456 | ld_ldgim4 = 0; | |
457 | ld_ldgim5 = 0; | |
458 | ld_ldgim6 = 0; | |
459 | ld_ldgim7 = 0; | |
460 | ld_ldgim8 = 0; | |
461 | ld_ldgim9 = 0; | |
462 | ld_ldgim10 = 0; | |
463 | ld_ldgim11 = 0; | |
464 | ld_ldgim12 = 0; | |
465 | ld_ldgim13 = 0; | |
466 | ld_ldgim14 = 0; | |
467 | ld_ldgim15 = 0; | |
468 | ld_ldgim16 = 0; | |
469 | ld_ldgim17 = 0; | |
470 | ld_ldgim18 = 0; | |
471 | ld_ldgim19 = 0; | |
472 | ld_ldgim20 = 0; | |
473 | ld_ldgim21 = 0; | |
474 | ld_ldgim22 = 0; | |
475 | ld_ldgim23 = 0; | |
476 | ld_ldgim24 = 0; | |
477 | ld_ldgim25 = 0; | |
478 | ld_ldgim26 = 0; | |
479 | ld_ldgim27 = 0; | |
480 | ld_ldgim28 = 0; | |
481 | ld_ldgim29 = 0; | |
482 | ld_ldgim30 = 0; | |
483 | ld_ldgim31 = 0; | |
484 | ld_ldgim32 = 0; | |
485 | ld_ldgim33 = 0; | |
486 | ld_ldgim34 = 0; | |
487 | ld_ldgim35 = 0; | |
488 | ld_ldgim36 = 0; | |
489 | ld_ldgim37 = 0; | |
490 | ld_ldgim38 = 0; | |
491 | ld_ldgim39 = 0; | |
492 | ld_ldgim40 = 0; | |
493 | ld_ldgim41 = 0; | |
494 | ld_ldgim42 = 0; | |
495 | ld_ldgim43 = 0; | |
496 | ld_ldgim44 = 0; | |
497 | ld_ldgim45 = 0; | |
498 | ld_ldgim46 = 0; | |
499 | ld_ldgim47 = 0; | |
500 | ld_ldgim48 = 0; | |
501 | ld_ldgim49 = 0; | |
502 | ld_ldgim50 = 0; | |
503 | ld_ldgim51 = 0; | |
504 | ld_ldgim52 = 0; | |
505 | ld_ldgim53 = 0; | |
506 | ld_ldgim54 = 0; | |
507 | ld_ldgim55 = 0; | |
508 | ld_ldgim56 = 0; | |
509 | ld_ldgim57 = 0; | |
510 | ld_ldgim58 = 0; | |
511 | ld_ldgim59 = 0; | |
512 | ld_ldgim60 = 0; | |
513 | ld_ldgim61 = 0; | |
514 | ld_ldgim62 = 0; | |
515 | ld_ldgim63 = 0; | |
516 | intr_reg_sel = 0; | |
517 | ||
518 | case({addr_int[18:3],3'b0}) //synopsys parallel_case full_case | |
519 | ||
520 | // DMA binding registers | |
521 | 19'h0_0018: begin | |
522 | ld_ldgim0 = wr_en; | |
523 | intr_reg_sel = 1'b1; | |
524 | rd_data = {32'b0,arm0,25'b0,timer0}; | |
525 | end | |
526 | 19'h0_2018: begin | |
527 | ld_ldgim1 = wr_en; | |
528 | intr_reg_sel = 1'b1; | |
529 | rd_data = {32'b0,arm1,25'b0,timer1}; | |
530 | end | |
531 | 19'h0_4018: begin | |
532 | ld_ldgim2 = wr_en; | |
533 | intr_reg_sel = 1'b1; | |
534 | rd_data = {32'b0,arm2,25'b0,timer2}; | |
535 | end | |
536 | 19'h0_6018: begin | |
537 | ld_ldgim3 = wr_en; | |
538 | intr_reg_sel = 1'b1; | |
539 | rd_data = {32'b0,arm3,25'b0,timer3}; | |
540 | end | |
541 | 19'h0_8018: begin | |
542 | ld_ldgim4 = wr_en; | |
543 | intr_reg_sel = 1'b1; | |
544 | rd_data = {32'b0,arm4,25'b0,timer4}; | |
545 | end | |
546 | 19'h0_a018: begin | |
547 | ld_ldgim5 = wr_en; | |
548 | intr_reg_sel = 1'b1; | |
549 | rd_data = {32'b0,arm5,25'b0,timer5}; | |
550 | end | |
551 | 19'h0_c018: begin | |
552 | ld_ldgim6 = wr_en; | |
553 | intr_reg_sel = 1'b1; | |
554 | rd_data = {32'b0,arm6,25'b0,timer6}; | |
555 | end | |
556 | 19'h0_e018: begin | |
557 | ld_ldgim7 = wr_en; | |
558 | intr_reg_sel = 1'b1; | |
559 | rd_data = {32'b0,arm7,25'b0,timer7}; | |
560 | end | |
561 | 19'h1_0018: begin | |
562 | ld_ldgim8 = wr_en; | |
563 | intr_reg_sel = 1'b1; | |
564 | rd_data = {32'b0,arm8,25'b0,timer8}; | |
565 | end | |
566 | 19'h1_2018: begin | |
567 | ld_ldgim9 = wr_en; | |
568 | intr_reg_sel = 1'b1; | |
569 | rd_data = {32'b0,arm9,25'b0,timer9}; | |
570 | end | |
571 | 19'h1_4018: begin | |
572 | ld_ldgim10 = wr_en; | |
573 | intr_reg_sel = 1'b1; | |
574 | rd_data = {32'b0,arm10,25'b0,timer10}; | |
575 | end | |
576 | 19'h1_6018: begin | |
577 | ld_ldgim11 = wr_en; | |
578 | intr_reg_sel = 1'b1; | |
579 | rd_data = {32'b0,arm11,25'b0,timer11}; | |
580 | end | |
581 | 19'h1_8018: begin | |
582 | ld_ldgim12 = wr_en; | |
583 | intr_reg_sel = 1'b1; | |
584 | rd_data = {32'b0,arm12,25'b0,timer12}; | |
585 | end | |
586 | 19'h1_a018: begin | |
587 | ld_ldgim13 = wr_en; | |
588 | intr_reg_sel = 1'b1; | |
589 | rd_data = {32'b0,arm13,25'b0,timer13}; | |
590 | end | |
591 | 19'h1_c018: begin | |
592 | ld_ldgim14 = wr_en; | |
593 | intr_reg_sel = 1'b1; | |
594 | rd_data = {32'b0,arm14,25'b0,timer14}; | |
595 | end | |
596 | 19'h1_e018: begin | |
597 | ld_ldgim15 = wr_en; | |
598 | intr_reg_sel = 1'b1; | |
599 | rd_data = {32'b0,arm15,25'b0,timer15}; | |
600 | end | |
601 | 19'h2_0018: begin | |
602 | ld_ldgim16 = wr_en; | |
603 | intr_reg_sel = 1'b1; | |
604 | rd_data = {32'b0,arm16,25'b0,timer16}; | |
605 | end | |
606 | 19'h2_2018: begin | |
607 | ld_ldgim17 = wr_en; | |
608 | intr_reg_sel = 1'b1; | |
609 | rd_data = {32'b0,arm17,25'b0,timer17}; | |
610 | end | |
611 | 19'h2_4018: begin | |
612 | ld_ldgim18 = wr_en; | |
613 | intr_reg_sel = 1'b1; | |
614 | rd_data = {32'b0,arm18,25'b0,timer18}; | |
615 | end | |
616 | 19'h2_6018: begin | |
617 | ld_ldgim19 = wr_en; | |
618 | intr_reg_sel = 1'b1; | |
619 | rd_data = {32'b0,arm19,25'b0,timer19}; | |
620 | end | |
621 | 19'h2_8018: begin | |
622 | ld_ldgim20 = wr_en; | |
623 | intr_reg_sel = 1'b1; | |
624 | rd_data = {32'b0,arm20,25'b0,timer20}; | |
625 | end | |
626 | 19'h2_a018: begin | |
627 | ld_ldgim21 = wr_en; | |
628 | intr_reg_sel = 1'b1; | |
629 | rd_data = {32'b0,arm21,25'b0,timer21}; | |
630 | end | |
631 | 19'h2_c018: begin | |
632 | ld_ldgim22 = wr_en; | |
633 | intr_reg_sel = 1'b1; | |
634 | rd_data = {32'b0,arm22,25'b0,timer22}; | |
635 | end | |
636 | 19'h2_e018: begin | |
637 | ld_ldgim23 = wr_en; | |
638 | intr_reg_sel = 1'b1; | |
639 | rd_data = {32'b0,arm23,25'b0,timer23}; | |
640 | end | |
641 | 19'h3_0018: begin | |
642 | ld_ldgim24 = wr_en; | |
643 | intr_reg_sel = 1'b1; | |
644 | rd_data = {32'b0,arm24,25'b0,timer24}; | |
645 | end | |
646 | 19'h3_2018: begin | |
647 | ld_ldgim25 = wr_en; | |
648 | intr_reg_sel = 1'b1; | |
649 | rd_data = {32'b0,arm25,25'b0,timer25}; | |
650 | end | |
651 | 19'h3_4018: begin | |
652 | ld_ldgim26 = wr_en; | |
653 | intr_reg_sel = 1'b1; | |
654 | rd_data = {32'b0,arm26,25'b0,timer26}; | |
655 | end | |
656 | 19'h3_6018: begin | |
657 | ld_ldgim27 = wr_en; | |
658 | intr_reg_sel = 1'b1; | |
659 | rd_data = {32'b0,arm27,25'b0,timer27}; | |
660 | end | |
661 | 19'h3_8018: begin | |
662 | ld_ldgim28 = wr_en; | |
663 | intr_reg_sel = 1'b1; | |
664 | rd_data = {32'b0,arm28,25'b0,timer28}; | |
665 | end | |
666 | 19'h3_a018: begin | |
667 | ld_ldgim29 = wr_en; | |
668 | intr_reg_sel = 1'b1; | |
669 | rd_data = {32'b0,arm29,25'b0,timer29}; | |
670 | end | |
671 | 19'h3_c018: begin | |
672 | ld_ldgim30 = wr_en; | |
673 | intr_reg_sel = 1'b1; | |
674 | rd_data = {32'b0,arm30,25'b0,timer30}; | |
675 | end | |
676 | 19'h3_e018: begin | |
677 | ld_ldgim31 = wr_en; | |
678 | intr_reg_sel = 1'b1; | |
679 | rd_data = {32'b0,arm31,25'b0,timer31}; | |
680 | end | |
681 | 19'h4_0018: begin | |
682 | ld_ldgim32 = wr_en; | |
683 | intr_reg_sel = 1'b1; | |
684 | rd_data = {32'b0,arm32,25'b0,timer32}; | |
685 | end | |
686 | 19'h4_2018: begin | |
687 | ld_ldgim33 = wr_en; | |
688 | intr_reg_sel = 1'b1; | |
689 | rd_data = {32'b0,arm33,25'b0,timer33}; | |
690 | end | |
691 | 19'h4_4018: begin | |
692 | ld_ldgim34 = wr_en; | |
693 | intr_reg_sel = 1'b1; | |
694 | rd_data = {32'b0,arm34,25'b0,timer34}; | |
695 | end | |
696 | 19'h4_6018: begin | |
697 | ld_ldgim35 = wr_en; | |
698 | intr_reg_sel = 1'b1; | |
699 | rd_data = {32'b0,arm35,25'b0,timer35}; | |
700 | end | |
701 | 19'h4_8018: begin | |
702 | ld_ldgim36 = wr_en; | |
703 | intr_reg_sel = 1'b1; | |
704 | rd_data = {32'b0,arm36,25'b0,timer36}; | |
705 | end | |
706 | 19'h4_a018: begin | |
707 | ld_ldgim37 = wr_en; | |
708 | intr_reg_sel = 1'b1; | |
709 | rd_data = {32'b0,arm37,25'b0,timer37}; | |
710 | end | |
711 | 19'h4_c018: begin | |
712 | ld_ldgim38 = wr_en; | |
713 | intr_reg_sel = 1'b1; | |
714 | rd_data = {32'b0,arm38,25'b0,timer38}; | |
715 | end | |
716 | 19'h4_e018: begin | |
717 | ld_ldgim39 = wr_en; | |
718 | intr_reg_sel = 1'b1; | |
719 | rd_data = {32'b0,arm39,25'b0,timer39}; | |
720 | end | |
721 | 19'h5_0018: begin | |
722 | ld_ldgim40 = wr_en; | |
723 | intr_reg_sel = 1'b1; | |
724 | rd_data = {32'b0,arm40,25'b0,timer40}; | |
725 | end | |
726 | 19'h5_2018: begin | |
727 | ld_ldgim41 = wr_en; | |
728 | intr_reg_sel = 1'b1; | |
729 | rd_data = {32'b0,arm41,25'b0,timer41}; | |
730 | end | |
731 | 19'h5_4018: begin | |
732 | ld_ldgim42 = wr_en; | |
733 | intr_reg_sel = 1'b1; | |
734 | rd_data = {32'b0,arm42,25'b0,timer42}; | |
735 | end | |
736 | 19'h5_6018: begin | |
737 | ld_ldgim43 = wr_en; | |
738 | intr_reg_sel = 1'b1; | |
739 | rd_data = {32'b0,arm43,25'b0,timer43}; | |
740 | end | |
741 | 19'h5_8018: begin | |
742 | ld_ldgim44 = wr_en; | |
743 | intr_reg_sel = 1'b1; | |
744 | rd_data = {32'b0,arm44,25'b0,timer44}; | |
745 | end | |
746 | 19'h5_a018: begin | |
747 | ld_ldgim45 = wr_en; | |
748 | intr_reg_sel = 1'b1; | |
749 | rd_data = {32'b0,arm45,25'b0,timer45}; | |
750 | end | |
751 | 19'h5_c018: begin | |
752 | ld_ldgim46 = wr_en; | |
753 | intr_reg_sel = 1'b1; | |
754 | rd_data = {32'b0,arm46,25'b0,timer46}; | |
755 | end | |
756 | 19'h5_e018: begin | |
757 | ld_ldgim47 = wr_en; | |
758 | intr_reg_sel = 1'b1; | |
759 | rd_data = {32'b0,arm47,25'b0,timer47}; | |
760 | end | |
761 | 19'h6_0018: begin | |
762 | ld_ldgim48 = wr_en; | |
763 | intr_reg_sel = 1'b1; | |
764 | rd_data = {32'b0,arm48,25'b0,timer48}; | |
765 | end | |
766 | 19'h6_2018: begin | |
767 | ld_ldgim49 = wr_en; | |
768 | intr_reg_sel = 1'b1; | |
769 | rd_data = {32'b0,arm49,25'b0,timer49}; | |
770 | end | |
771 | 19'h6_4018: begin | |
772 | ld_ldgim50 = wr_en; | |
773 | intr_reg_sel = 1'b1; | |
774 | rd_data = {32'b0,arm50,25'b0,timer50}; | |
775 | end | |
776 | 19'h6_6018: begin | |
777 | ld_ldgim51 = wr_en; | |
778 | intr_reg_sel = 1'b1; | |
779 | rd_data = {32'b0,arm51,25'b0,timer51}; | |
780 | end | |
781 | 19'h6_8018: begin | |
782 | ld_ldgim52 = wr_en; | |
783 | intr_reg_sel = 1'b1; | |
784 | rd_data = {32'b0,arm52,25'b0,timer52}; | |
785 | end | |
786 | 19'h6_a018: begin | |
787 | ld_ldgim53 = wr_en; | |
788 | intr_reg_sel = 1'b1; | |
789 | rd_data = {32'b0,arm53,25'b0,timer53}; | |
790 | end | |
791 | 19'h6_c018: begin | |
792 | ld_ldgim54 = wr_en; | |
793 | intr_reg_sel = 1'b1; | |
794 | rd_data = {32'b0,arm54,25'b0,timer54}; | |
795 | end | |
796 | 19'h6_e018: begin | |
797 | ld_ldgim55 = wr_en; | |
798 | intr_reg_sel = 1'b1; | |
799 | rd_data = {32'b0,arm55,25'b0,timer55}; | |
800 | end | |
801 | 19'h7_0018: begin | |
802 | ld_ldgim56 = wr_en; | |
803 | intr_reg_sel = 1'b1; | |
804 | rd_data = {32'b0,arm56,25'b0,timer56}; | |
805 | end | |
806 | 19'h7_2018: begin | |
807 | ld_ldgim57 = wr_en; | |
808 | intr_reg_sel = 1'b1; | |
809 | rd_data = {32'b0,arm57,25'b0,timer57}; | |
810 | end | |
811 | 19'h7_4018: begin | |
812 | ld_ldgim58 = wr_en; | |
813 | intr_reg_sel = 1'b1; | |
814 | rd_data = {32'b0,arm58,25'b0,timer58}; | |
815 | end | |
816 | 19'h7_6018: begin | |
817 | ld_ldgim59 = wr_en; | |
818 | intr_reg_sel = 1'b1; | |
819 | rd_data = {32'b0,arm59,25'b0,timer59}; | |
820 | end | |
821 | 19'h7_8018: begin | |
822 | ld_ldgim60 = wr_en; | |
823 | intr_reg_sel = 1'b1; | |
824 | rd_data = {32'b0,arm60,25'b0,timer60}; | |
825 | end | |
826 | 19'h7_a018: begin | |
827 | ld_ldgim61 = wr_en; | |
828 | intr_reg_sel = 1'b1; | |
829 | rd_data = {32'b0,arm61,25'b0,timer61}; | |
830 | end | |
831 | 19'h7_c018: begin | |
832 | ld_ldgim62 = wr_en; | |
833 | intr_reg_sel = 1'b1; | |
834 | rd_data = {32'b0,arm62,25'b0,timer62}; | |
835 | end | |
836 | 19'h7_e018: begin | |
837 | ld_ldgim63 = wr_en; | |
838 | intr_reg_sel = 1'b1; | |
839 | rd_data = {32'b0,arm63,25'b0,timer63}; | |
840 | end | |
841 | ||
842 | default: begin | |
843 | rd_data = 64'hdead_beef_dead_beef; | |
844 | intr_reg_sel = 1'b0; | |
845 | non_qualified_addr_err = 0; | |
846 | end // case: default | |
847 | endcase // case({addr[18:3],3'b0}) | |
848 | end // always @ (... | |
849 | ||
850 | endmodule // niu_pio_ldgim_decoder | |
851 |