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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: niu_rdmc_fetch_desp_sm.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module niu_rdmc_fetch_desp_sm ( | |
36 | clk, | |
37 | reset, | |
38 | dma_chnl_grp_id, | |
39 | dma_reset, | |
40 | dma_fatal_err, | |
41 | fetch_desp_trig, | |
42 | fetch_desp_num, | |
43 | desp_init_valid, | |
44 | fetch_desp_gnt, | |
45 | rdmc_resp_rdy_valid, | |
46 | rdmc_req_err, | |
47 | rdmc_resp_cmd, | |
48 | rdmc_resp_cmd_status, | |
49 | rdmc_resp_data_status, | |
50 | rdmc_resp_dma_num, | |
51 | rdmc_resp_data_valid, | |
52 | rdmc_resp_byteenable, | |
53 | rdmc_resp_comp, | |
54 | rdmc_resp_trans_comp, | |
55 | resp_data_in_process, | |
56 | ||
57 | fetch_desp_req, | |
58 | rdmc_resp_accept_sm, //use rdmc_resp_accept if timing | |
59 | fetch_desp_resp_vld, | |
60 | fetch_desp_req_sm, | |
61 | fetch_desp_pre_done, | |
62 | fetch_desp_done, | |
63 | resp_bus_err, | |
64 | resp_bus_err_type, | |
65 | rbr_idle_cycle | |
66 | ||
67 | ); | |
68 | ||
69 | ||
70 | input clk; | |
71 | input reset; | |
72 | input[4:0] dma_chnl_grp_id; | |
73 | input dma_reset; | |
74 | input dma_fatal_err; | |
75 | input fetch_desp_trig; | |
76 | input[4:0] fetch_desp_num; | |
77 | input desp_init_valid; | |
78 | input fetch_desp_gnt; | |
79 | input rdmc_resp_rdy_valid; | |
80 | input rdmc_req_err; | |
81 | input[4:0] rdmc_resp_cmd; | |
82 | input[3:0] rdmc_resp_cmd_status; | |
83 | input[3:0] rdmc_resp_data_status; | |
84 | input[4:0] rdmc_resp_dma_num; | |
85 | input rdmc_resp_data_valid; | |
86 | input[15:0] rdmc_resp_byteenable; | |
87 | input rdmc_resp_comp; | |
88 | input rdmc_resp_trans_comp; | |
89 | input resp_data_in_process; | |
90 | ||
91 | output fetch_desp_req; | |
92 | output rdmc_resp_accept_sm; | |
93 | output fetch_desp_resp_vld; | |
94 | output fetch_desp_req_sm; | |
95 | output fetch_desp_pre_done; | |
96 | output fetch_desp_done; | |
97 | output resp_bus_err; | |
98 | output[3:0] resp_bus_err_type; | |
99 | output rbr_idle_cycle; | |
100 | ||
101 | reg rbr_idle_cycle; | |
102 | reg fetch_desp_req_sm; | |
103 | reg rdmc_resp_accept_sm; | |
104 | reg fetch_desp_resp_valid_sm; | |
105 | reg resp_cmd_err; | |
106 | reg fetch_desp_pre_done; | |
107 | reg fetch_desp_done; | |
108 | reg[2:0] next_state; | |
109 | reg[2:0] state; | |
110 | reg fetch_desp_req; | |
111 | //reg rdmc_resp_accept; | |
112 | reg fetch_desp_resp_vld; | |
113 | ||
114 | reg[2:0] valid_addr_cnt; | |
115 | reg[4:0] resp_data_cnt; | |
116 | reg valid_bit_err; | |
117 | reg valid_bit_err_r; | |
118 | reg resp_data_err; | |
119 | ||
120 | wire vaild_bit0; | |
121 | wire vaild_bit1; | |
122 | wire vaild_bit2; | |
123 | wire vaild_bit3; | |
124 | wire[3:0] vaild_bit_array; | |
125 | ||
126 | wire valid_bit_err0; | |
127 | wire valid_bit_err1; | |
128 | wire valid_bit_err2; | |
129 | wire valid_bit_err3; | |
130 | wire valid_bit_err_tmp; | |
131 | wire resp_data_cnt_err; | |
132 | wire resp_bus_err; | |
133 | wire[3:0] resp_bus_err_type; | |
134 | ||
135 | wire resp_id_match = (dma_chnl_grp_id == rdmc_resp_dma_num); | |
136 | ||
137 | wire rdmc_resp_cmd_err = (rdmc_resp_cmd_status == 4'b1111) | !(rdmc_resp_cmd[4:0] == 5'b00101); | |
138 | ||
139 | parameter | |
140 | ||
141 | IDLE = 3'b000, | |
142 | DESP_REQ = 3'b001, | |
143 | DESP_RESP1 = 3'b010, | |
144 | DESP_RESP_DATA1 = 3'b011, | |
145 | DESP_RESP2 = 3'b100, | |
146 | DESP_RESP_DATA2 = 3'b101, | |
147 | DESP_RESP_DONE = 3'b110, | |
148 | RESP_ERR = 3'b111; | |
149 | ||
150 | ||
151 | always @ (state or | |
152 | desp_init_valid or fetch_desp_trig or | |
153 | fetch_desp_gnt or rdmc_resp_rdy_valid or | |
154 | rdmc_resp_comp or rdmc_resp_trans_comp or | |
155 | resp_data_in_process or resp_id_match or | |
156 | dma_fatal_err or rdmc_req_err or rdmc_resp_cmd_err) | |
157 | begin | |
158 | rbr_idle_cycle = 1'b0; | |
159 | fetch_desp_req_sm = 1'b0; | |
160 | rdmc_resp_accept_sm = 1'b0; | |
161 | fetch_desp_resp_valid_sm= 1'b0; | |
162 | resp_cmd_err = 1'b0; | |
163 | fetch_desp_pre_done = 1'b0; | |
164 | fetch_desp_done = 1'b0; | |
165 | next_state = 3'b0; | |
166 | ||
167 | ||
168 | case (state) //synopsys parallel_case full_case | |
169 | ||
170 | IDLE: | |
171 | begin | |
172 | rbr_idle_cycle = 1'b1; | |
173 | if (desp_init_valid & !dma_fatal_err) | |
174 | begin | |
175 | if (fetch_desp_trig) | |
176 | begin | |
177 | fetch_desp_req_sm = 1'b1; | |
178 | next_state = DESP_REQ; | |
179 | end | |
180 | else | |
181 | next_state = state; | |
182 | end | |
183 | else | |
184 | next_state = state; | |
185 | end | |
186 | ||
187 | DESP_REQ: | |
188 | begin | |
189 | if (fetch_desp_gnt) | |
190 | next_state = DESP_RESP1; | |
191 | else | |
192 | next_state = state; | |
193 | end | |
194 | ||
195 | DESP_RESP1: | |
196 | begin | |
197 | if (resp_data_in_process) | |
198 | begin | |
199 | rdmc_resp_accept_sm = 1'b0; | |
200 | fetch_desp_resp_valid_sm = 1'b0; | |
201 | next_state = state; | |
202 | end | |
203 | else if (rdmc_req_err) | |
204 | begin | |
205 | rdmc_resp_accept_sm = 1'b0; | |
206 | fetch_desp_resp_valid_sm = 1'b0; | |
207 | next_state = RESP_ERR; | |
208 | end | |
209 | else if (rdmc_resp_rdy_valid & resp_id_match & rdmc_resp_cmd_err) | |
210 | begin | |
211 | rdmc_resp_accept_sm = 1'b1; | |
212 | fetch_desp_resp_valid_sm = 1'b0; | |
213 | next_state = RESP_ERR; | |
214 | end | |
215 | else if (rdmc_resp_rdy_valid & resp_id_match) | |
216 | begin | |
217 | rdmc_resp_accept_sm = 1'b1; | |
218 | fetch_desp_resp_valid_sm = 1'b1; | |
219 | next_state = DESP_RESP_DATA1; | |
220 | end | |
221 | else | |
222 | next_state = state; | |
223 | end | |
224 | ||
225 | DESP_RESP_DATA1: | |
226 | begin | |
227 | if (rdmc_resp_comp & rdmc_resp_trans_comp) | |
228 | begin | |
229 | fetch_desp_pre_done = 1'b1; | |
230 | next_state = DESP_RESP_DONE; | |
231 | end | |
232 | else if (rdmc_resp_comp) | |
233 | next_state = DESP_RESP2; | |
234 | else | |
235 | next_state = state; | |
236 | end | |
237 | ||
238 | DESP_RESP2: | |
239 | begin | |
240 | if (resp_data_in_process) | |
241 | begin | |
242 | rdmc_resp_accept_sm = 1'b0; | |
243 | fetch_desp_resp_valid_sm = 1'b0; | |
244 | next_state = state; | |
245 | end | |
246 | else if (rdmc_resp_rdy_valid & resp_id_match & rdmc_resp_cmd_err) | |
247 | begin | |
248 | rdmc_resp_accept_sm = 1'b1; | |
249 | fetch_desp_resp_valid_sm = 1'b0; | |
250 | next_state = RESP_ERR; | |
251 | end | |
252 | else if (rdmc_resp_rdy_valid & resp_id_match) | |
253 | begin | |
254 | rdmc_resp_accept_sm = 1'b1; | |
255 | fetch_desp_resp_valid_sm = 1'b1; | |
256 | next_state = DESP_RESP_DATA2; | |
257 | end | |
258 | else | |
259 | next_state = state; | |
260 | end | |
261 | ||
262 | DESP_RESP_DATA2: | |
263 | begin | |
264 | if (rdmc_resp_comp & rdmc_resp_trans_comp) | |
265 | begin | |
266 | fetch_desp_pre_done = 1'b1; | |
267 | next_state = DESP_RESP_DONE; | |
268 | end | |
269 | else if (rdmc_resp_comp) | |
270 | next_state = RESP_ERR; | |
271 | else | |
272 | next_state = state; | |
273 | end | |
274 | ||
275 | DESP_RESP_DONE: | |
276 | begin | |
277 | fetch_desp_done = 1'b1; | |
278 | next_state = IDLE; | |
279 | end | |
280 | ||
281 | RESP_ERR: | |
282 | begin | |
283 | fetch_desp_done = 1'b1; | |
284 | resp_cmd_err = 1'b1; | |
285 | next_state = IDLE; | |
286 | end | |
287 | ||
288 | default: | |
289 | next_state = IDLE; | |
290 | endcase | |
291 | end | |
292 | ||
293 | ||
294 | always @ (posedge clk) | |
295 | if (reset) | |
296 | state <= 3'b0; | |
297 | else if (dma_reset) | |
298 | state <= 3'b0; | |
299 | else | |
300 | state <= next_state; | |
301 | ||
302 | always @ (posedge clk) | |
303 | if (reset) | |
304 | fetch_desp_req <= 1'b0; | |
305 | else if (dma_reset) | |
306 | fetch_desp_req <= 1'b0; | |
307 | else if (fetch_desp_req_sm) | |
308 | fetch_desp_req <= 1'b1; | |
309 | else if (fetch_desp_gnt) | |
310 | fetch_desp_req <= 1'b0; | |
311 | else | |
312 | fetch_desp_req <= fetch_desp_req; | |
313 | ||
314 | /* | |
315 | always @ (posedge clk) | |
316 | if (reset) | |
317 | rdmc_resp_accept <= 1'b0; | |
318 | else | |
319 | rdmc_resp_accept <= rdmc_resp_accept_sm; | |
320 | */ | |
321 | ||
322 | always @ (posedge clk) | |
323 | if (reset) | |
324 | fetch_desp_resp_vld <= 1'b0; | |
325 | else if (dma_reset) | |
326 | fetch_desp_resp_vld <= 1'b0; | |
327 | else if (fetch_desp_resp_valid_sm) | |
328 | fetch_desp_resp_vld <= 1'b1; | |
329 | else if (rdmc_resp_comp) | |
330 | fetch_desp_resp_vld <= 1'b0; | |
331 | else | |
332 | fetch_desp_resp_vld <= fetch_desp_resp_vld; | |
333 | ||
334 | ||
335 | assign vaild_bit0 = &rdmc_resp_byteenable[3:0]; | |
336 | assign vaild_bit1 = &rdmc_resp_byteenable[7:4]; | |
337 | assign vaild_bit2 = &rdmc_resp_byteenable[11:8]; | |
338 | assign vaild_bit3 = &rdmc_resp_byteenable[15:12]; | |
339 | assign vaild_bit_array = {vaild_bit3, vaild_bit2, vaild_bit1, vaild_bit0}; | |
340 | ||
341 | assign valid_bit_err0 = |rdmc_resp_byteenable[3:0] & !vaild_bit0; | |
342 | assign valid_bit_err1 = |rdmc_resp_byteenable[7:4] & !vaild_bit1; | |
343 | assign valid_bit_err2 = |rdmc_resp_byteenable[11:8] & !vaild_bit2; | |
344 | assign valid_bit_err3 = |rdmc_resp_byteenable[15:12] & !vaild_bit3; | |
345 | ||
346 | assign valid_bit_err_tmp = valid_bit_err0 | valid_bit_err1 | | |
347 | valid_bit_err2 | valid_bit_err3 | valid_bit_err; | |
348 | ||
349 | assign resp_data_cnt_err = !(resp_data_cnt == fetch_desp_num); | |
350 | ||
351 | always @ (vaild_bit_array) | |
352 | begin | |
353 | ||
354 | case (vaild_bit_array) //synopsys parallel_case full_case | |
355 | ||
356 | 4'b0001, 4'b0010, 4'b0100, 4'b1000: | |
357 | begin | |
358 | valid_addr_cnt = 3'b001; | |
359 | valid_bit_err = 1'b0; | |
360 | end | |
361 | 4'b0011, 4'b0110, 4'b1100: | |
362 | begin | |
363 | valid_addr_cnt = 3'b010; | |
364 | valid_bit_err = 1'b0; | |
365 | end | |
366 | 4'b0111, 4'b1110: | |
367 | begin | |
368 | valid_addr_cnt = 3'b011; | |
369 | valid_bit_err = 1'b0; | |
370 | end | |
371 | 4'b1111: | |
372 | begin | |
373 | valid_addr_cnt = 3'b100; | |
374 | valid_bit_err = 1'b0; | |
375 | end | |
376 | default: | |
377 | begin | |
378 | valid_addr_cnt = 3'b000; | |
379 | valid_bit_err = 1'b1; | |
380 | end | |
381 | endcase | |
382 | end | |
383 | ||
384 | ||
385 | always @ (posedge clk) | |
386 | if (reset) | |
387 | resp_data_cnt <= 5'b0; | |
388 | else if (dma_reset) | |
389 | resp_data_cnt <= 5'b0; | |
390 | else if (fetch_desp_gnt) | |
391 | resp_data_cnt <= 5'b0; | |
392 | else if (fetch_desp_resp_vld & rdmc_resp_data_valid) | |
393 | resp_data_cnt <= resp_data_cnt + {2'b0, valid_addr_cnt}; | |
394 | else | |
395 | resp_data_cnt <= resp_data_cnt; | |
396 | ||
397 | always @ (posedge clk) | |
398 | if (reset) | |
399 | valid_bit_err_r <= 1'b0; | |
400 | else if (dma_reset) | |
401 | valid_bit_err_r <= 1'b0; | |
402 | else if (fetch_desp_gnt) | |
403 | valid_bit_err_r <= 1'b0; | |
404 | else if (fetch_desp_resp_vld & rdmc_resp_data_valid) | |
405 | valid_bit_err_r <= valid_bit_err_tmp | valid_bit_err_r; | |
406 | else | |
407 | valid_bit_err_r <= valid_bit_err_r; | |
408 | ||
409 | always @ (posedge clk) | |
410 | if (reset) | |
411 | resp_data_err <= 1'b0; | |
412 | else if (dma_reset) | |
413 | resp_data_err <= 1'b0; | |
414 | else if (fetch_desp_gnt) | |
415 | resp_data_err <= 1'b0; | |
416 | else if (fetch_desp_resp_vld & rdmc_resp_data_valid & (rdmc_resp_data_status != 4'b0)) | |
417 | resp_data_err <= 1'b1; | |
418 | else | |
419 | resp_data_err <= resp_data_err; | |
420 | ||
421 | assign resp_bus_err = (resp_cmd_err | resp_data_cnt_err | valid_bit_err_r | resp_data_err) & fetch_desp_done; | |
422 | assign resp_bus_err_type = {resp_cmd_err, resp_data_cnt_err, valid_bit_err_r, resp_data_err}; | |
423 | ||
424 | endmodule | |
425 | ||
426 | ||
427 | ||
428 | ||
429 | ||
430 | ||
431 |