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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: xmac_2pcs_clk_mux.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | /*%W% %G%*/ | |
36 | ||
37 | /************************************************************************* | |
38 | * | |
39 | * File Name : xmac_2pcs_clk_mux.v | |
40 | * Author Name : John Lo | |
41 | * Description : xmac_2pcs_clk_mux.v is a modification version of | |
42 | * xmac_clk_mux.v file. It is specific for 250 MHz | |
43 | * core clock and 312.5Mhz clock input. | |
44 | * | |
45 | * xmac_2pcs_clk_mux works closely with esr_ctl4, sphy_dpath4. | |
46 | * The phy_clock_4ports is clock path. | |
47 | * The sphy_dpath4 is data path. | |
48 | * The control path is esr_ctl4. | |
49 | * When doing changes/modifications make sure | |
50 | * phy_clock_4ports , sphy_dpath4 and esr_ctl4 are in sync. | |
51 | * | |
52 | * Parent Module: phy_clock_2ports/phy_clock_4ports | |
53 | * Child Module: | |
54 | * Interface Mod: many. | |
55 | * Date Created : 8/24/01 | |
56 | * | |
57 | * Copyright (c) 2003, Sun Microsystems, Inc. | |
58 | * Sun Proprietary and Confidential | |
59 | * | |
60 | * Modification : 1. 3/23/04 -loj: changed eser_phy to esr_mac. | |
61 | * 2. 3/23/04 -loj: changed iser_phy to psr_mac. | |
62 | * 3. 4/21/04 -loj: changed esr_mac_tclk to | |
63 | * ref_clk_312mhz for 10G optical and | |
64 | * Bth esr_tclk_125mhz0 and esr_tclk_125mhz1 are | |
65 | * for 1G optical. | |
66 | * 4. 11/29/04 -loj: Added dft mux to ref_clk_312mhz. | |
67 | * | |
68 | * | |
69 | * Synthesis Notes: Make sure those asyn reset flops are used. | |
70 | * | |
71 | *************************************************************************/ | |
72 | ||
73 | `include "xmac.h" | |
74 | ||
75 | module xmac_2pcs_clk_mux( | |
76 | `ifdef NEPTUNE | |
77 | `else | |
78 | FUNC_MODE, | |
79 | mac_312tx_test_clk, | |
80 | mac_312rx_test_clk, | |
81 | mac_156tx_test_clk, | |
82 | mac_156rx_test_clk, | |
83 | mac_125tx_test_clk, | |
84 | mac_125rx_test_clk, | |
85 | `endif | |
86 | reset, | |
87 | clk, | |
88 | loopback, | |
89 | sel_por_clk_src, | |
90 | mii_mode, | |
91 | xgmii_mode, | |
92 | pcs_bypass, // select external pcs | |
93 | xpcs_loopback, // !ref_clk_312mhz as xpcs_loopback clock | |
94 | gmii_mode, | |
95 | ref_clk_250mhz, | |
96 | sel_clk_25mhz, | |
97 | tx_heart_beat_timer, // from tx_mii_gmii.v | |
98 | rx_heart_beat_timer, // from rx_mii_gmii.v | |
99 | // 802.3 input rx clocks | |
100 | gmii_rx_clk, // shared between mii and gmii receive clk | |
101 | // xpcs clock | |
102 | esr_tclk_312mhz, | |
103 | esr_mac_rclk0, | |
104 | esr_mac_rclk1, | |
105 | esr_mac_rclk2, | |
106 | esr_mac_rclk3, | |
107 | // pcs clock | |
108 | atca_GE, | |
109 | esr_tclk_125mhz0, | |
110 | esr_tclk_125mhz1, | |
111 | esr_rclk_125mhz0, | |
112 | esr_rclk_125mhz1, | |
113 | // outputs to clock tree | |
114 | tx_nbclk_muxd, | |
115 | tx_clk_muxd, | |
116 | tx_clk_312mhz_muxd, | |
117 | rx_nbclk_muxd, | |
118 | rx_clk_muxd, | |
119 | rbc0_a_muxd, | |
120 | rbc0_b_muxd, | |
121 | rbc0_c_muxd, | |
122 | rbc0_d_muxd, | |
123 | debug_tclk_156mhz, | |
124 | debug_rclk_156mhz | |
125 | ); | |
126 | `ifdef NEPTUNE | |
127 | `else | |
128 | input FUNC_MODE; | |
129 | input mac_312tx_test_clk; | |
130 | input [3:0] mac_312rx_test_clk; | |
131 | input mac_156tx_test_clk; | |
132 | input mac_156rx_test_clk; | |
133 | input mac_125tx_test_clk; | |
134 | input mac_125rx_test_clk; | |
135 | `endif | |
136 | input reset; | |
137 | input clk; | |
138 | input loopback; | |
139 | input sel_por_clk_src; | |
140 | input mii_mode; | |
141 | input xgmii_mode; | |
142 | input pcs_bypass; // select external pcs | |
143 | input xpcs_loopback; // !tx_pclk as xpcs_loopback clock | |
144 | // vlint flag_dangling_net_within_module off | |
145 | // vlint flag_input_port_not_connected off | |
146 | // vlint flag_net_has_no_load off | |
147 | input gmii_mode; | |
148 | input ref_clk_250mhz; | |
149 | input sel_clk_25mhz; | |
150 | input [3:0] tx_heart_beat_timer;// from tx_mii_gmii.v | |
151 | input [3:0] rx_heart_beat_timer;// from rx_mii_gmii.v | |
152 | // vlint flag_dangling_net_within_module on | |
153 | // vlint flag_input_port_not_connected on | |
154 | // vlint flag_net_has_no_load on | |
155 | // 802.3 rx clocks | |
156 | input gmii_rx_clk; // shared between mii and gmii receive clk | |
157 | // xpcs clock | |
158 | input esr_tclk_312mhz; // For 10G optical | |
159 | input esr_mac_rclk0; // for 10G optical | |
160 | input esr_mac_rclk1; // for 10G optical | |
161 | input esr_mac_rclk2; // for 10G optical | |
162 | input esr_mac_rclk3; // for 10G optical | |
163 | // pcs clock | |
164 | input atca_GE; | |
165 | input esr_tclk_125mhz0; // For 1G optical | |
166 | input esr_tclk_125mhz1; // For 1G optical | |
167 | input esr_rclk_125mhz0; // For 1G optical | |
168 | input esr_rclk_125mhz1; // For 1G optical | |
169 | // outputs to clock tree | |
170 | output tx_nbclk_muxd; // 125/25/2.5mhz | |
171 | output tx_clk_muxd; // 156mhz | |
172 | output tx_clk_312mhz_muxd;// 312mhz | |
173 | output rx_nbclk_muxd; // 125/25/2.5mhz | |
174 | output rx_clk_muxd; // 156mhz | |
175 | output rbc0_a_muxd; // 312mhz | |
176 | output rbc0_b_muxd; // 312mhz | |
177 | output rbc0_c_muxd; // 312mhz | |
178 | output rbc0_d_muxd; // 312mhz | |
179 | // debug clocks | |
180 | output debug_tclk_156mhz; | |
181 | output debug_rclk_156mhz; | |
182 | ||
183 | wire inv_tx_heart_beat_timer3 = ~tx_heart_beat_timer[3]; | |
184 | wire inv_tx_heart_beat_timer2 = ~tx_heart_beat_timer[2]; | |
185 | wire cu_tclk; // 125/25/2.5 mhz | |
186 | wire tx_mg_clk; | |
187 | wire mgmii_rx_clk; | |
188 | wire rx_mg_clk; | |
189 | wire rx_xg_clk; | |
190 | wire xmac_loopback_clk; | |
191 | wire xpcs_loopback_clk; | |
192 | wire tx_nbclk_muxd; // to clock tree | |
193 | wire tx_clk_muxd; // to clock tree | |
194 | wire rx_nbclk_muxd; // to clock tree | |
195 | wire rx_clk_muxd; // to clock tree | |
196 | wire rbc0_a_muxd; | |
197 | wire rbc0_b_muxd; | |
198 | wire rbc0_c_muxd; | |
199 | wire rbc0_d_muxd; | |
200 | wire p1_tx_nbclk_muxd; // to clock tree | |
201 | wire p1_tx_clk_muxd; // to clock tree | |
202 | wire p1_rx_nbclk_muxd; // to clock tree | |
203 | wire p1_rx_clk_muxd; // to clock tree | |
204 | wire p1_rbc0_a_muxd; | |
205 | wire p1_rbc0_b_muxd; | |
206 | wire p1_rbc0_c_muxd; | |
207 | wire p1_rbc0_d_muxd; | |
208 | wire tclk_156mhz; | |
209 | wire rclk_156mhz; | |
210 | wire opti_tclk; | |
211 | wire opti_t125; | |
212 | wire tclk; | |
213 | wire clk4; | |
214 | wire rbcx2_ext; | |
215 | wire tclk156mhz_div2_clkin; | |
216 | wire rclk156mhz_div2_clkin; | |
217 | ||
218 | // vlint flag_dangling_net_within_module off | |
219 | // vlint flag_net_has_no_load off | |
220 | wire toggle; | |
221 | wire cnt3; | |
222 | wire cnt4; | |
223 | wire cnt49; | |
224 | // vlint flag_dangling_net_within_module on | |
225 | // vlint flag_net_has_no_load on | |
226 | ||
227 | `ifdef USE_NON_INVERTING_CLOCK | |
228 | // divider clock polarity | |
229 | assign tclk156mhz_div2_clkin = esr_tclk_312mhz; | |
230 | assign rclk156mhz_div2_clkin = p1_rbc0_a_muxd; | |
231 | // loopback clock polarity | |
232 | assign xmac_loopback_clk = p1_tx_nbclk_muxd; | |
233 | assign xpcs_loopback_clk = esr_tclk_312mhz; | |
234 | `else | |
235 | // divider clock polarity | |
236 | inv_buffer tclk156mhz_div2_clkin_inv_buffer(.z (tclk156mhz_div2_clkin),.a(esr_tclk_312mhz)); | |
237 | inv_buffer rclk156mhz_div2_clkin_inv_buffer(.z (rclk156mhz_div2_clkin),.a(p1_rbc0_a_muxd)); | |
238 | // loopback clock polarity | |
239 | inv_buffer xmac_loopback_clk_inv_buffer (.z (xmac_loopback_clk), .a(p1_tx_nbclk_muxd)); | |
240 | inv_buffer xpcs_loopback_clk_inv_buffer (.z (xpcs_loopback_clk), .a(esr_tclk_312mhz)); | |
241 | `endif | |
242 | ||
243 | /* ************************************* | |
244 | * local clock generation logic | |
245 | * *************************************/ | |
246 | ||
247 | DIV4_CLK clk4_DIV4_CLK( | |
248 | .reset(reset), | |
249 | .clk(clk), | |
250 | .clk4(clk4) | |
251 | ); | |
252 | ||
253 | ||
254 | DIV2_CLK tclk_156mhz_DIV2_CLK( | |
255 | .reset(reset), | |
256 | .clk(tclk156mhz_div2_clkin), | |
257 | .clk2(tclk_156mhz) | |
258 | ); | |
259 | ||
260 | DIV2_CLK rclk_156mhz_DIV2_CLK( | |
261 | .reset(reset), | |
262 | .clk(rclk156mhz_div2_clkin), | |
263 | .clk2(rclk_156mhz) | |
264 | ); | |
265 | ||
266 | // debug clock monitor | |
267 | DIV2_CLK debug_tclk_156mhz_DIV2_CLK( | |
268 | .reset(reset), | |
269 | .clk(tclk156mhz_div2_clkin), | |
270 | .clk2(debug_tclk_156mhz) | |
271 | ); | |
272 | ||
273 | DIV2_CLK debug_rclk_156mhz_DIV2_CLK( | |
274 | .reset(reset), | |
275 | .clk(rclk156mhz_div2_clkin), | |
276 | .clk2(debug_rclk_156mhz) | |
277 | ); | |
278 | ||
279 | /* ************************************* | |
280 | * tx_mac's clk mux | |
281 | * *************************************/ | |
282 | func_mux1 p1_tx_nbclk_muxd_func_mux1_u0( // pre LV mux | |
283 | .dout (p1_tx_nbclk_muxd), | |
284 | .select(sel_por_clk_src), | |
285 | .din1 (clk4), // sys_clk/4 | |
286 | .din0 (tclk)); | |
287 | ||
288 | func_mux1 tclk_func_mux1_u1( | |
289 | .dout (tclk), // 156/125(optical)/125(copper)/25/2.5 Mhz | |
290 | .select(pcs_bypass), | |
291 | .din1 (cu_tclk), // cupper phy; 125(copper)/25/2.5mhz | |
292 | .din0 (opti_tclk)); // optical phy; 156/125(optical)mhz | |
293 | ||
294 | func_mux1 opti_tclk_func_mux1_u2( | |
295 | .dout (opti_tclk), | |
296 | .select(xgmii_mode), | |
297 | .din1 (tclk_156mhz), // 10G -> 156mhz | |
298 | .din0 (opti_t125)); // 1G -> 125mhz | |
299 | ||
300 | func_mux1 opti_t125_func_mux1_u3( | |
301 | .dout (opti_t125), | |
302 | .select(atca_GE), | |
303 | .din1 (esr_tclk_125mhz1), // sel 1 | |
304 | .din0 (esr_tclk_125mhz0)); // sel 0 | |
305 | ||
306 | func_mux1 p1_tx_clk_muxd_func_mux1_u4( // pre LV mux | |
307 | .dout (p1_tx_clk_muxd), | |
308 | .select(xgmii_mode), | |
309 | .din1 (p1_tx_nbclk_muxd), // 10G -> 156mhz | |
310 | .din0 (tx_mg_clk)); // 1G -> 125mhz | |
311 | ||
312 | func_mux1 tx_mg_clk_func_mux1_u5(.dout (tx_mg_clk), | |
313 | .select(mii_mode), | |
314 | .din1 (inv_tx_heart_beat_timer3), | |
315 | .din0 (inv_tx_heart_beat_timer2)); | |
316 | ||
317 | /* ************************************* | |
318 | * rx_mac's clk mux | |
319 | * *************************************/ | |
320 | func_mux1 p1_rx_nbclk_muxd_func_mux1_u6( | |
321 | .dout (p1_rx_nbclk_muxd), | |
322 | .select(loopback), | |
323 | .din1(xmac_loopback_clk), | |
324 | .din0(mgmii_rx_clk)); | |
325 | ||
326 | func_mux1 mgmii_rx_clk_func_mux1_u7(.dout(mgmii_rx_clk), | |
327 | .select(pcs_bypass), | |
328 | .din1(gmii_rx_clk), // rx copper 1G | |
329 | .din0(rbcx2_ext)); // rx opti 1G | |
330 | ||
331 | func_mux1 rbcx2_ext_func_mux1_u8(.dout(rbcx2_ext), | |
332 | .select(atca_GE), | |
333 | .din1(esr_rclk_125mhz1), | |
334 | .din0(esr_rclk_125mhz0)); | |
335 | ||
336 | func_mux1 p1_rx_clk_muxd_func_mux1_u9( | |
337 | .dout (p1_rx_clk_muxd), | |
338 | .select(xgmii_mode), | |
339 | .din1(rx_xg_clk), | |
340 | .din0(rx_mg_clk)); | |
341 | ||
342 | func_mux1 rx_xg_clk_func_mux1_u10(.dout(rx_xg_clk), | |
343 | .select(loopback), | |
344 | .din1(xmac_loopback_clk), | |
345 | .din0(rclk_156mhz)); | |
346 | ||
347 | ||
348 | func_mux1 rx_mg_clk_func_mux1_u11(.dout(rx_mg_clk), | |
349 | .select(mii_mode), | |
350 | .din1(rx_heart_beat_timer[3]), | |
351 | .din0(rx_heart_beat_timer[2])); | |
352 | ||
353 | /* ************************************* | |
354 | * xpcs's clk mux | |
355 | * *************************************/ | |
356 | func_mux1 p1_rbc0_a_muxd_func_mux1_u16( // pre LV mux | |
357 | .dout(p1_rbc0_a_muxd), | |
358 | .select(xpcs_loopback), | |
359 | .din1(xpcs_loopback_clk), | |
360 | .din0(esr_mac_rclk0)); | |
361 | ||
362 | func_mux1 p1_rbc0_b_muxd_func_mux1_u17( // pre LV mux | |
363 | .dout(p1_rbc0_b_muxd), | |
364 | .select(xpcs_loopback), | |
365 | .din1(xpcs_loopback_clk), | |
366 | .din0(esr_mac_rclk1)); | |
367 | ||
368 | func_mux1 p1_rbc0_c_muxd_func_mux1_u18( // pre LV mux | |
369 | .dout(p1_rbc0_c_muxd), | |
370 | .select(xpcs_loopback), | |
371 | .din1(xpcs_loopback_clk), | |
372 | .din0(esr_mac_rclk2)); | |
373 | ||
374 | func_mux1 p1_rbc0_d_muxd_func_mux1_u19( // pre LV mux | |
375 | .dout(p1_rbc0_d_muxd), | |
376 | .select(xpcs_loopback), | |
377 | .din1(xpcs_loopback_clk), | |
378 | .din0(esr_mac_rclk3)); | |
379 | ||
380 | ||
381 | `ifdef NEPTUNE | |
382 | rgmii_clk_gen rgmii_clk_gen( | |
383 | .ref_clk_250mhz(ref_clk_250mhz), | |
384 | .reset(reset), | |
385 | .gmii_mode(gmii_mode), | |
386 | .sel_clk_25mhz(sel_clk_25mhz), | |
387 | // output | |
388 | .cu_tclk(cu_tclk), | |
389 | // for observation | |
390 | .toggle(toggle), | |
391 | .cnt3(cnt3), | |
392 | .cnt4(cnt4), | |
393 | .cnt49(cnt49) | |
394 | ); | |
395 | ||
396 | /* ************************************* | |
397 | * eliminate LV muxes | |
398 | * *************************************/ | |
399 | // tx side | |
400 | assign tx_nbclk_muxd = p1_tx_nbclk_muxd; | |
401 | assign tx_clk_muxd = p1_tx_clk_muxd; | |
402 | assign tx_clk_312mhz_muxd = esr_tclk_312mhz; | |
403 | assign rx_nbclk_muxd = p1_rx_nbclk_muxd; | |
404 | // rx side | |
405 | assign rx_clk_muxd = p1_rx_clk_muxd; | |
406 | assign rbc0_a_muxd = p1_rbc0_a_muxd; | |
407 | assign rbc0_b_muxd = p1_rbc0_b_muxd; | |
408 | assign rbc0_c_muxd = p1_rbc0_c_muxd; | |
409 | assign rbc0_d_muxd = p1_rbc0_d_muxd; | |
410 | ||
411 | `else // N2 -> does not have rgmii interface | |
412 | assign cu_tclk = 1'b0; | |
413 | assign toggle = 1'b0; | |
414 | assign cnt3 = 1'b0; | |
415 | assign cnt4 = 1'b0; | |
416 | assign cnt49 = 1'b0; | |
417 | ||
418 | /* ************************************* | |
419 | * LV muxes | |
420 | * *************************************/ | |
421 | // tx side | |
422 | lv_mux1 tx_nbclk_muxd_lv_mux1_u20( | |
423 | .dout(tx_nbclk_muxd), | |
424 | .select(FUNC_MODE), | |
425 | .din1(p1_tx_nbclk_muxd), | |
426 | .din0(mac_125tx_test_clk)); | |
427 | ||
428 | lv_mux1 tx_clk_muxd_lv_mux1_u21( | |
429 | .dout(tx_clk_muxd), | |
430 | .select(FUNC_MODE), | |
431 | .din1(p1_tx_clk_muxd), | |
432 | .din0(mac_156tx_test_clk)); | |
433 | ||
434 | lv_mux1 tx_clk_312mhz_muxd_lv_mux1_u22( | |
435 | .dout(tx_clk_312mhz_muxd), | |
436 | .select(FUNC_MODE), | |
437 | .din1(esr_tclk_312mhz), // esr_mac_tclk | |
438 | .din0(mac_312tx_test_clk)); | |
439 | ||
440 | // rx side | |
441 | lv_mux1 rx_nbclk_muxd_lv_mux1_u30( | |
442 | .dout(rx_nbclk_muxd), | |
443 | .select(FUNC_MODE), | |
444 | .din1(p1_rx_nbclk_muxd), | |
445 | .din0(mac_125rx_test_clk)); | |
446 | ||
447 | lv_mux1 rx_clk_muxd_lv_mux1_u31( | |
448 | .dout(rx_clk_muxd), | |
449 | .select(FUNC_MODE), | |
450 | .din1(p1_rx_clk_muxd), | |
451 | .din0(mac_156rx_test_clk)); | |
452 | ||
453 | lv_mux1 rbc0_a_muxd_lv_mux1_u32( | |
454 | .dout(rbc0_a_muxd), | |
455 | .select(FUNC_MODE), | |
456 | .din1(p1_rbc0_a_muxd), | |
457 | .din0(mac_312rx_test_clk[0])); | |
458 | ||
459 | lv_mux1 rbc0_b_muxd_lv_mux1_u33( | |
460 | .dout(rbc0_b_muxd), | |
461 | .select(FUNC_MODE), | |
462 | .din1(p1_rbc0_b_muxd), | |
463 | .din0(mac_312rx_test_clk[1])); | |
464 | ||
465 | lv_mux1 rbc0_c_muxd_lv_mux1_u34( | |
466 | .dout(rbc0_c_muxd), | |
467 | .select(FUNC_MODE), | |
468 | .din1(p1_rbc0_c_muxd), | |
469 | .din0(mac_312rx_test_clk[2])); | |
470 | ||
471 | lv_mux1 rbc0_d_muxd_lv_mux1_u35( | |
472 | .dout(rbc0_d_muxd), | |
473 | .select(FUNC_MODE), | |
474 | .din1(p1_rbc0_d_muxd), | |
475 | .din0(mac_312rx_test_clk[3])); | |
476 | ||
477 | ||
478 | `endif | |
479 | ||
480 | endmodule // xmac_2pcs_clk_mux | |
481 |