Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: pcie_dcm_daemon.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module pcie_dcm_daemon | |
36 | ( | |
37 | daemon_csrbus_valid, | |
38 | daemon_csrbus_mapped, | |
39 | daemon_csrbus_wr_data, | |
40 | daemon_csrbus_done, | |
41 | daemon_csrbus_addr, | |
42 | daemon_csrbus_wr, | |
43 | daemon_transaction_in_progress, | |
44 | // synopsys translate_off | |
45 | rst_l, | |
46 | clk, | |
47 | csrbus_read_data, | |
48 | // synopsys translate_on | |
49 | csrbus_valid, | |
50 | csrbus_mapped, | |
51 | csrbus_wr_data, | |
52 | csrbus_done, | |
53 | csrbus_addr, | |
54 | csrbus_wr | |
55 | ); | |
56 | ||
57 | parameter ADDR_WIDTH = 27; | |
58 | parameter DATA_WIDTH = 64; | |
59 | ||
60 | // synopsys translate_off | |
61 | parameter DAEMON_STATE_IDLE = 3'd0; | |
62 | parameter DAEMON_STATE_RD = 3'd4; // bit 2 is mux select | |
63 | parameter DAEMON_STATE_WR = 3'd5; | |
64 | parameter DAEMON_STATE_WAIT_RD = 3'd6; | |
65 | parameter DAEMON_STATE_WAIT_WR = 3'd7; | |
66 | // synopsys translate_on | |
67 | ||
68 | output daemon_csrbus_valid; | |
69 | output [DATA_WIDTH-1:0] daemon_csrbus_wr_data; | |
70 | output [ADDR_WIDTH-1:0] daemon_csrbus_addr; | |
71 | output daemon_csrbus_wr; | |
72 | output daemon_transaction_in_progress; | |
73 | ||
74 | output csrbus_mapped; | |
75 | output csrbus_done; | |
76 | ||
77 | input daemon_csrbus_mapped; | |
78 | input daemon_csrbus_done; | |
79 | ||
80 | // synopsys translate_off | |
81 | input rst_l; | |
82 | input clk; | |
83 | input [DATA_WIDTH-1:0] csrbus_read_data; // needed to return back to daemon task | |
84 | // synopsys translate_on | |
85 | ||
86 | input csrbus_valid; | |
87 | input [DATA_WIDTH-1:0] csrbus_wr_data; | |
88 | input [ADDR_WIDTH-1:0] csrbus_addr; | |
89 | input csrbus_wr; | |
90 | ||
91 | ||
92 | reg daemon_csrbus_valid; | |
93 | reg [ADDR_WIDTH-1:0] daemon_csrbus_addr; | |
94 | reg [DATA_WIDTH-1:0] daemon_csrbus_wr_data; | |
95 | reg daemon_csrbus_wr; | |
96 | ||
97 | wire daemon_transaction_in_progress; | |
98 | reg csrbus_done; | |
99 | reg csrbus_mapped; | |
100 | ||
101 | // synopsys translate_off | |
102 | ||
103 | // inputs/outputs from task | |
104 | reg daemon_wr; | |
105 | reg daemon_rd; | |
106 | reg [ADDR_WIDTH-1:0] daemon_addr; | |
107 | reg [DATA_WIDTH-1:0] daemon_wr_data; | |
108 | ||
109 | // vlint flag_dangling_net_within_module off | |
110 | // vlint flag_net_has_no_load off | |
111 | wire [DATA_WIDTH-1:0] daemon_rd_data; | |
112 | // vlint flag_net_has_no_load on | |
113 | // vlint flag_dangling_net_within_module on | |
114 | ||
115 | // registered versions | |
116 | reg daemon_wr_reg; | |
117 | reg daemon_rd_reg; | |
118 | reg [ADDR_WIDTH-1:0] daemon_addr_reg; | |
119 | reg [DATA_WIDTH-1:0] daemon_wr_data_reg; | |
120 | reg daemon_csrbus_done_reg; | |
121 | ||
122 | // done signals back to verif | |
123 | ||
124 | // vlint flag_dangling_net_within_module off | |
125 | // vlint flag_net_has_no_load off | |
126 | // vlint flag_variable_assign_never_reference off | |
127 | reg daemon_rd_done; | |
128 | reg daemon_wr_done; | |
129 | // vlint flag_variable_assign_never_reference on | |
130 | // vlint flag_net_has_no_load on | |
131 | // vlint flag_dangling_net_within_module on | |
132 | ||
133 | // internal wires | |
134 | wire daemon_starting_transaction; | |
135 | wire daemon_ok_to_start_transaction; | |
136 | wire daemon_rd_done_a1; | |
137 | wire daemon_wr_done_a1; | |
138 | reg [2:0] daemon_state; | |
139 | ||
140 | reg csrbus_valid_d; | |
141 | ||
142 | // vlint flag_dangling_net_within_module off | |
143 | // vlint flag_net_has_no_load off | |
144 | // vlint flag_variable_assign_never_reference off | |
145 | reg [DATA_WIDTH-1:0] csrbus_read_data_reg; | |
146 | // vlint flag_variable_assign_never_reference on | |
147 | // vlint flag_net_has_no_load on | |
148 | // vlint flag_dangling_net_within_module on | |
149 | ||
150 | // vlint flag_unsynthesizable_initial off | |
151 | initial | |
152 | begin | |
153 | daemon_state = DAEMON_STATE_IDLE; | |
154 | // N2- AT: daemon_rd = 1'b0; | |
155 | // N2- AT: daemon_wr = 1'b0; | |
156 | daemon_wr_data = {DATA_WIDTH{1'b0}}; | |
157 | daemon_addr = {ADDR_WIDTH{1'b0}}; | |
158 | end // initial begin | |
159 | // vlint flag_unsynthesizable_initial on | |
160 | ||
161 | always @(posedge clk) | |
162 | begin | |
163 | if (~rst_l) begin | |
164 | daemon_rd_reg <= 1'b0; | |
165 | daemon_wr_reg <= 1'b0; | |
166 | daemon_wr_data_reg <= {DATA_WIDTH{1'b0}}; | |
167 | daemon_addr_reg <= {ADDR_WIDTH{1'b0}}; | |
168 | daemon_rd_done <= 1'b0; | |
169 | daemon_wr_done <= 1'b0; | |
170 | daemon_csrbus_done_reg <= 1'b0; | |
171 | daemon_wr <= 1'b0; | |
172 | daemon_rd <= 1'b0; | |
173 | end | |
174 | else begin | |
175 | daemon_rd_reg <= daemon_rd; | |
176 | daemon_wr_reg <= daemon_wr; | |
177 | daemon_wr_data_reg <= daemon_wr_data; | |
178 | daemon_addr_reg <= daemon_addr; | |
179 | daemon_rd_done <= daemon_rd_done_a1; | |
180 | daemon_wr_done <= daemon_wr_done_a1; | |
181 | daemon_csrbus_done_reg <= daemon_csrbus_done; | |
182 | end | |
183 | end // always @ (posedge clk) | |
184 | ||
185 | always @(posedge clk) | |
186 | begin | |
187 | if (~rst_l ) begin | |
188 | csrbus_valid_d <= 1'b0; | |
189 | csrbus_read_data_reg <= {DATA_WIDTH{1'b0}}; | |
190 | end | |
191 | else begin | |
192 | csrbus_valid_d <= csrbus_valid; | |
193 | csrbus_read_data_reg <= csrbus_read_data; | |
194 | end | |
195 | end | |
196 | ||
197 | always @(posedge clk) | |
198 | begin | |
199 | if (~rst_l) | |
200 | daemon_state <= DAEMON_STATE_IDLE; | |
201 | else begin | |
202 | case (daemon_state) | |
203 | ||
204 | DAEMON_STATE_IDLE: | |
205 | begin | |
206 | if (daemon_rd_reg & daemon_ok_to_start_transaction) // do daemon read | |
207 | begin | |
208 | if (daemon_csrbus_done_reg) | |
209 | daemon_state <= DAEMON_STATE_WAIT_RD; // zero cycles | |
210 | else | |
211 | daemon_state <= DAEMON_STATE_RD; // takes more than zero cycles | |
212 | end // if (daemon_rd) | |
213 | ||
214 | else if (daemon_wr_reg & daemon_ok_to_start_transaction) | |
215 | begin | |
216 | if (daemon_csrbus_done_reg) | |
217 | daemon_state <= DAEMON_STATE_WAIT_WR; // less than one cycle | |
218 | else | |
219 | daemon_state <= DAEMON_STATE_WR; // slow | |
220 | end // if (daemon_wr_reg) | |
221 | ||
222 | else | |
223 | begin | |
224 | daemon_state <= DAEMON_STATE_IDLE; // nothing to do | |
225 | end // else: !if(daemon_wr_reg) | |
226 | ||
227 | end // case: DAEMON_STATE_IDLE | |
228 | ||
229 | DAEMON_STATE_WR: // holds a write until finished | |
230 | begin | |
231 | if (daemon_csrbus_done_reg) // done or timeout | |
232 | begin | |
233 | daemon_state <= DAEMON_STATE_WAIT_WR; | |
234 | end | |
235 | ||
236 | else if (~daemon_wr_reg) // timeout | |
237 | begin | |
238 | daemon_state <= DAEMON_STATE_WAIT_WR; | |
239 | end | |
240 | ||
241 | else | |
242 | begin | |
243 | daemon_state <= DAEMON_STATE_WR; // wait | |
244 | end // else: !if(~daemon_wr_reg) | |
245 | ||
246 | end | |
247 | ||
248 | DAEMON_STATE_RD: | |
249 | begin | |
250 | if (daemon_csrbus_done_reg) // done | |
251 | begin | |
252 | daemon_state <= DAEMON_STATE_WAIT_RD; | |
253 | end | |
254 | ||
255 | else if (~daemon_rd_reg) | |
256 | begin | |
257 | daemon_state <= DAEMON_STATE_WAIT_RD; | |
258 | end | |
259 | ||
260 | else | |
261 | begin | |
262 | daemon_state <= DAEMON_STATE_RD; // wait | |
263 | end | |
264 | ||
265 | end // case: DAEMON_STATE_RD | |
266 | ||
267 | DAEMON_STATE_WAIT_RD: | |
268 | begin | |
269 | if (daemon_wr_reg & daemon_ok_to_start_transaction) | |
270 | begin | |
271 | daemon_state <= DAEMON_STATE_WR; // more than one cycle | |
272 | end | |
273 | ||
274 | else if (daemon_rd_reg & daemon_ok_to_start_transaction) | |
275 | begin | |
276 | daemon_state <= DAEMON_STATE_RD; // read | |
277 | end | |
278 | ||
279 | else | |
280 | begin | |
281 | daemon_state <= DAEMON_STATE_IDLE; // nothing to do, go back to idle | |
282 | end | |
283 | ||
284 | end // case: DAEMON_STATE_WAIT_RD | |
285 | ||
286 | DAEMON_STATE_WAIT_WR: | |
287 | begin | |
288 | if (daemon_rd_reg & daemon_ok_to_start_transaction) // new rd? | |
289 | begin | |
290 | daemon_state <= DAEMON_STATE_RD; | |
291 | end | |
292 | ||
293 | else if (daemon_wr_reg & daemon_ok_to_start_transaction) // new write? | |
294 | begin | |
295 | daemon_state <= DAEMON_STATE_WR; | |
296 | end | |
297 | ||
298 | else | |
299 | begin | |
300 | daemon_state <= DAEMON_STATE_IDLE; // nothing to do, go back to idle | |
301 | end | |
302 | ||
303 | end // case: DAEMON_STATE_WAIT_WR | |
304 | ||
305 | default: | |
306 | begin | |
307 | daemon_state <= daemon_state; | |
308 | end | |
309 | ||
310 | endcase // case(daemon_state) | |
311 | end | |
312 | end // always @ (posedge clk) | |
313 | ||
314 | assign daemon_rd_done_a1 = | |
315 | ( | |
316 | (daemon_state == DAEMON_STATE_IDLE) & | |
317 | daemon_csrbus_done & | |
318 | daemon_rd_reg & | |
319 | daemon_ok_to_start_transaction | |
320 | ) | |
321 | | | |
322 | ( | |
323 | (daemon_state == DAEMON_STATE_RD) & | |
324 | daemon_csrbus_done | |
325 | ); | |
326 | ||
327 | assign daemon_wr_done_a1 = | |
328 | ( | |
329 | (daemon_state == DAEMON_STATE_IDLE) & | |
330 | daemon_csrbus_done & | |
331 | daemon_wr_reg & | |
332 | ~daemon_rd_reg & | |
333 | daemon_ok_to_start_transaction | |
334 | ) | |
335 | | | |
336 | ( | |
337 | (daemon_state == DAEMON_STATE_WR) & | |
338 | daemon_csrbus_done | |
339 | ); | |
340 | ||
341 | ||
342 | ||
343 | assign daemon_rd_data = csrbus_read_data_reg; | |
344 | ||
345 | assign daemon_ok_to_start_transaction = ~csrbus_valid_d; | |
346 | ||
347 | wire good_starting_state = (daemon_state == DAEMON_STATE_IDLE); | |
348 | ||
349 | assign daemon_starting_transaction = good_starting_state & | |
350 | (daemon_rd_reg | daemon_wr_reg) & | |
351 | daemon_ok_to_start_transaction; | |
352 | ||
353 | // synopsys translate_on | |
354 | ||
355 | // phaser split_component_by_output | |
356 | always @(csrbus_valid or csrbus_wr or csrbus_wr_data or csrbus_addr or | |
357 | daemon_csrbus_done or daemon_csrbus_mapped | |
358 | // synopsys translate_off | |
359 | or | |
360 | daemon_state or | |
361 | daemon_addr_reg or | |
362 | daemon_wr_reg or | |
363 | daemon_wr_data_reg or | |
364 | daemon_rd_reg or | |
365 | daemon_transaction_in_progress | |
366 | // synopsys translate_on | |
367 | ) | |
368 | begin | |
369 | // synopsys translate_off | |
370 | if (daemon_transaction_in_progress) | |
371 | begin | |
372 | daemon_csrbus_addr = daemon_addr_reg; | |
373 | daemon_csrbus_wr = (daemon_state == DAEMON_STATE_WR) | | |
374 | ( | |
375 | (daemon_state == DAEMON_STATE_IDLE) & | |
376 | daemon_wr_reg & | |
377 | ~ daemon_rd_reg | |
378 | ); | |
379 | ||
380 | daemon_csrbus_wr_data = daemon_wr_data_reg; | |
381 | daemon_csrbus_valid = ( | |
382 | (daemon_state == DAEMON_STATE_IDLE) & | |
383 | (daemon_rd_reg | daemon_wr_reg) | |
384 | ) | | |
385 | (daemon_state == DAEMON_STATE_WR) | | |
386 | (daemon_state == DAEMON_STATE_RD); | |
387 | csrbus_done = 1'b0; | |
388 | csrbus_mapped = 1'b0; | |
389 | end // if (daemon_state != DAEMON_STATE_IDLE) | |
390 | ||
391 | else // normal operation | |
392 | // synopsys translate_on | |
393 | begin | |
394 | daemon_csrbus_wr = csrbus_wr; | |
395 | daemon_csrbus_wr_data = csrbus_wr_data; | |
396 | daemon_csrbus_addr = csrbus_addr; | |
397 | daemon_csrbus_valid = csrbus_valid; | |
398 | csrbus_done = daemon_csrbus_done; | |
399 | csrbus_mapped = daemon_csrbus_mapped; | |
400 | end // else: !if(daemon_state != DAEMON_STATE_IDLE) | |
401 | end // always @ (csrbus_wr... | |
402 | ||
403 | assign daemon_transaction_in_progress = | |
404 | // synopsys translate_off | |
405 | ((daemon_state != DAEMON_STATE_IDLE) | daemon_starting_transaction ) ? 1'b1 : | |
406 | // synopsys translate_on | |
407 | 1'b0; | |
408 | ||
409 | endmodule |