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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dec_dcd_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dec_dcd_ctl ( | |
36 | dec_inst_d, | |
37 | ded_perr_d, | |
38 | ded_ferr_d, | |
39 | dcd_lsu_sign_ext_d, | |
40 | dcd_sethi_d, | |
41 | dcd_priv_d, | |
42 | dcd_fsrc_rs1_d, | |
43 | dcd_fsrc_rs2_d, | |
44 | dcd_fpdest_single_d, | |
45 | dcd_fp_rs1_single_d, | |
46 | dcd_fp_rs2_single_d, | |
47 | dcd_fsrsync_d, | |
48 | dcd_callclass_d, | |
49 | dcd_specbr_d, | |
50 | dcd_specfp_d, | |
51 | dcd_tcc_d, | |
52 | dcd_done_d, | |
53 | dcd_retry_d, | |
54 | dcd_load_d, | |
55 | dcd_store_d, | |
56 | dcd_lsdouble_d, | |
57 | dcd_prefetch_d, | |
58 | dcd_flush_d, | |
59 | dcd_memstbar_d, | |
60 | dcd_sr_d, | |
61 | dcd_pr_d, | |
62 | dcd_hpr_d, | |
63 | dcd_casa_d, | |
64 | dcd_ldstub_d, | |
65 | dcd_alt_d, | |
66 | dcd_alti_d, | |
67 | dcd_swap_d, | |
68 | dcd_lsize_d, | |
69 | dcd_killfgu_d, | |
70 | dcd_exu_src_d, | |
71 | dcd_save_restore_d, | |
72 | dcd_sir_d, | |
73 | dcd_stdfa_d, | |
74 | dcd_fpdisable_d, | |
75 | dcd_wrtick_d); | |
76 | wire priv_u; | |
77 | wire [31:0] i; | |
78 | wire casa_u; | |
79 | wire lsdouble_u; | |
80 | wire fsrc_rs1_u; | |
81 | wire fsrc_rs2_u; | |
82 | wire fpdest_single_u; | |
83 | wire fp_rs1_single_u; | |
84 | wire fp_rs2_single_u; | |
85 | wire fsrsync_u; | |
86 | wire callclass_u; | |
87 | wire specbr_u; | |
88 | wire specfp_u; | |
89 | wire tcc_u; | |
90 | wire done_u; | |
91 | wire retry_u; | |
92 | wire load_u; | |
93 | wire store_u; | |
94 | wire prefetch_u; | |
95 | wire flush_u; | |
96 | wire memstbar_u; | |
97 | wire sr_u; | |
98 | wire pr_u; | |
99 | wire hpr_u; | |
100 | wire ldstub_u; | |
101 | wire alt_u; | |
102 | wire alti_u; | |
103 | wire swap_u; | |
104 | wire [1:0] lsize_u; | |
105 | wire killfgu_u; | |
106 | wire exu_src_u; | |
107 | wire save_restore_u; | |
108 | wire sir_u; | |
109 | wire stdfa_u; | |
110 | wire fpdisable_u; | |
111 | wire wrtick_u; | |
112 | wire kill_decode_d; | |
113 | wire illegal_d; | |
114 | ||
115 | ||
116 | input [31:0] dec_inst_d; // inst to decode | |
117 | ||
118 | input ded_perr_d; // parity error | |
119 | ||
120 | input ded_ferr_d; // ifetch error | |
121 | ||
122 | output dcd_lsu_sign_ext_d; // is a signed load | |
123 | ||
124 | output dcd_sethi_d; // inst is a special sethi inst | |
125 | ||
126 | ||
127 | output dcd_priv_d; // autogenerated outputs | |
128 | output dcd_fsrc_rs1_d; | |
129 | output dcd_fsrc_rs2_d; | |
130 | output dcd_fpdest_single_d; | |
131 | output dcd_fp_rs1_single_d; | |
132 | output dcd_fp_rs2_single_d; | |
133 | output dcd_fsrsync_d; | |
134 | output dcd_callclass_d; | |
135 | output dcd_specbr_d; | |
136 | output dcd_specfp_d; | |
137 | output dcd_tcc_d; | |
138 | output dcd_done_d; | |
139 | output dcd_retry_d; | |
140 | output dcd_load_d; | |
141 | output dcd_store_d; | |
142 | output dcd_lsdouble_d; | |
143 | output dcd_prefetch_d; | |
144 | output dcd_flush_d; | |
145 | output dcd_memstbar_d; | |
146 | output dcd_sr_d; | |
147 | output dcd_pr_d; | |
148 | output dcd_hpr_d; | |
149 | output dcd_casa_d; | |
150 | output dcd_ldstub_d; | |
151 | output dcd_alt_d; | |
152 | output dcd_alti_d; | |
153 | output dcd_swap_d; | |
154 | output [1:0] dcd_lsize_d; | |
155 | output dcd_killfgu_d; | |
156 | output dcd_exu_src_d; | |
157 | output dcd_save_restore_d; | |
158 | output dcd_sir_d; | |
159 | output dcd_stdfa_d; | |
160 | output dcd_fpdisable_d; | |
161 | output dcd_wrtick_d; | |
162 | ||
163 | dec_dcd_ctl_spare_ctl_macro__flops_0__num_2 spares ( | |
164 | ); | |
165 | ||
166 | ||
167 | // --- autogenerated by n2decode view=dec Wed Aug 10 15:04:27 CDT 2005 | |
168 | ||
169 | assign priv_u = (i[31]&i[24]&i[23]&!i[22]&!i[21]&!i[20]&i[19]) | (i[31]&i[24] | |
170 | &!i[23]&i[22]&!i[21]&!i[19]&i[18]&i[16]) | (i[31]&i[24]&!i[23]&i[22] | |
171 | &!i[21]&!i[19]&i[17]&!i[15]&i[14]) | (i[31]&!i[30]&i[28]&!i[26]&i[25] | |
172 | &i[24]&i[23]&!i[22]&!i[21]&!i[19]) | (i[31]&!i[30]&i[29]&i[27]&i[24] | |
173 | &i[23]&!i[22]&!i[21]&!i[19]) | (i[31]&!i[30]&i[29]&!i[28]&!i[25] | |
174 | &i[24]&i[23]&!i[22]&!i[21]&!i[19]) | (!i[30]&i[24]&i[23]&i[22]&i[21] | |
175 | &i[20]) | (i[31]&i[24]&!i[23]&i[22]&!i[21]&!i[19]&i[18]&!i[17]&!i[14]) | ( | |
176 | i[31]&i[24]&!i[23]&i[22]&!i[21]&i[20]&!i[19]) | (i[31]&i[24]&i[23] | |
177 | &!i[22]&!i[21]&i[20]&!i[19]); | |
178 | ||
179 | assign casa_u = (i[31]&i[30]&i[24]&i[22]&!i[19]); | |
180 | ||
181 | assign lsdouble_u = (i[31]&i[30]&!i[22]&i[20]&i[19]); | |
182 | ||
183 | assign fsrc_rs1_u = (i[31]&!i[30]&!i[13]&!i[11]&i[10]&i[9]&!i[7]&!i[6]) | ( | |
184 | i[31]&!i[30]&!i[13]&!i[12]&i[9]&!i[8]&i[5]) | (i[31]&!i[30]&i[20] | |
185 | &!i[13]&i[10]&!i[9]&i[8]) | (i[31]&!i[30]&i[20]&!i[13]&i[11]&!i[9] | |
186 | &i[8]&!i[5]) | (i[31]&!i[30]&!i[19]&!i[13]&i[11]&i[10]&i[7]&!i[6]) | ( | |
187 | i[31]&!i[30]&i[20]&!i[13]&i[11]&!i[7]&i[6]) | (i[31]&!i[30]&i[20] | |
188 | &!i[19]&!i[13]&!i[11]&i[10]&!i[5]) | (i[31]&!i[30]&!i[22]&!i[20] | |
189 | &!i[19]&!i[13]&!i[12]&i[11]) | (i[31]&!i[30]&!i[13]&!i[12]&i[11]&i[9] | |
190 | &!i[8]); | |
191 | ||
192 | assign fsrc_rs2_u = (i[31]&!i[30]&!i[13]&i[11]&!i[8]&i[6]) | (i[31]&!i[30]&!i[13] | |
193 | &i[11]&i[9]&!i[7]) | (i[31]&!i[30]&!i[13]&i[11]&i[8]&!i[6]) | (i[31] | |
194 | &!i[30]&!i[19]&!i[13]&!i[11]&i[10]) | (i[31]&!i[30]&!i[13]&i[11]&!i[9] | |
195 | &i[7]) | (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]&!i[20]) | (i[31] | |
196 | &!i[30]&!i[22]&!i[13]&i[11]&!i[10]); | |
197 | ||
198 | assign fpdest_single_u = (i[31]&!i[30]&!i[19]&!i[13]&i[12]&i[7]) | (i[31]&!i[30] | |
199 | &!i[13]&i[9]&i[8]&i[6]&i[5]) | (i[31]&!i[30]&!i[13]&i[9]&i[8]&i[7] | |
200 | &i[5]) | (i[31]&!i[30]&!i[20]&!i[13]&!i[11]&i[10]&i[5]) | (i[31] | |
201 | &!i[30]&!i[22]&!i[19]&!i[13]&i[12]&i[11]&!i[8]) | (i[31]&!i[30]&!i[19] | |
202 | &!i[13]&i[11]&!i[8]&i[5]) | (i[31]&i[24]&i[23]&!i[22]&!i[20]&i[19] | |
203 | &!i[9]&i[5]) | (i[31]&!i[30]&!i[20]&!i[19]&!i[13]&!i[12]&!i[10]&i[5]) | ( | |
204 | i[31]&!i[30]&i[20]&!i[13]&i[11]&i[10]&i[5]) | (i[31]&i[30]&i[24] | |
205 | &!i[22]&!i[19]); | |
206 | ||
207 | assign fp_rs1_single_u = (i[31]&!i[30]&!i[13]&!i[11]&i[9]&!i[8]&!i[7]&i[5]) | ( | |
208 | i[31]&!i[30]&!i[13]&!i[11]&i[10]&i[9]&!i[7]&!i[6]) | (i[31]&!i[30] | |
209 | &i[20]&!i[13]&i[11]&i[9]&!i[8]&i[5]) | (i[31]&!i[30]&i[20]&!i[13] | |
210 | &i[10]&!i[9]&i[8]&i[5]) | (i[31]&!i[30]&!i[20]&!i[19]&!i[13]&!i[12] | |
211 | &i[11]&i[5]) | (i[31]&!i[30]&!i[19]&!i[13]&i[11]&i[10]&i[7]&!i[6] | |
212 | &i[5]) | (i[31]&!i[30]&!i[13]&i[11]&!i[7]&i[6]&i[5]) | (i[31]&!i[30] | |
213 | &!i[13]&!i[12]&i[9]&!i[8]&!i[6]&i[5]) | (i[31]&i[30]&i[24]&!i[21] | |
214 | &!i[19]); | |
215 | ||
216 | assign fp_rs2_single_u = (i[31]&!i[30]&!i[22]&!i[13]&i[12]&i[11]&!i[6]) | ( | |
217 | i[31]&!i[30]&!i[13]&i[9]&!i[8]&!i[7]&i[6]&i[5]) | (i[31]&!i[30]&!i[13] | |
218 | &!i[11]&i[10]&!i[8]&i[7]&!i[6]&i[5]) | (i[31]&!i[30]&!i[13]&!i[11] | |
219 | &i[10]&i[9]&i[8]&!i[7]&!i[6]) | (i[31]&!i[30]&!i[13]&i[11]&!i[9]&i[7] | |
220 | &i[5]) | (i[31]&!i[30]&!i[13]&i[11]&!i[8]&i[6]&i[5]) | (i[31]&!i[30] | |
221 | &!i[13]&i[11]&i[8]&!i[6]&i[5]) | (i[31]&!i[30]&!i[13]&i[11]&i[9]&!i[7] | |
222 | &i[5]) | (i[31]&!i[30]&!i[13]&i[11]&!i[10]&i[5]) | (i[31]&i[24]&i[23] | |
223 | &!i[22]&i[21]&!i[20]&i[5]) | (i[31]&i[30]&i[24]&!i[22]&!i[19]) | ( | |
224 | i[31]&i[30]&!i[25]&i[24]&!i[22]&i[21]&!i[20]); | |
225 | ||
226 | assign fsrsync_u = (i[31]&!i[30]&!i[13]&!i[11]&i[9]&i[8]&i[7]&!i[5]) | (i[31] | |
227 | &i[30]&i[24]&!i[22]&!i[20]&i[19]); | |
228 | ||
229 | assign callclass_u = (i[24]&i[23]&i[22]&!i[21]&!i[20]) | (!i[31]&i[30]); | |
230 | ||
231 | assign specbr_u = (!i[31]&!i[30]&i[22]) | (!i[31]&!i[30]&i[23]); | |
232 | ||
233 | assign specfp_u = (i[31]&!i[30]&!i[13]&i[12]&i[5]) | (i[31]&!i[30]&!i[13]&i[10] | |
234 | &i[9]) | (i[31]&!i[30]&!i[22]&!i[13]&i[11]) | (i[31]&!i[30]&i[24] | |
235 | &i[23]&!i[22]&i[21]&!i[20]); | |
236 | ||
237 | assign tcc_u = (!i[30]&i[24]&i[23]&i[22]&!i[21]&i[20]&!i[19]); | |
238 | ||
239 | assign done_u = (!i[30]&!i[25]&i[24]&i[23]&i[22]&i[21]&i[20]); | |
240 | ||
241 | assign retry_u = (!i[30]&i[25]&i[24]&i[23]&i[22]&i[21]&i[20]); | |
242 | ||
243 | assign load_u = (i[31]&i[24]&!i[23]&i[22]&i[20]&!i[19]&i[16]) | (i[31]&i[24] | |
244 | &!i[23]&i[22]&!i[21]&!i[17]&i[16]) | (i[31]&i[24]&!i[23]&i[22]&!i[21] | |
245 | &!i[20]&i[19]) | (i[31]&i[24]&!i[23]&i[22]&!i[21]&!i[19]&!i[16]) | ( | |
246 | i[31]&i[30]&i[24]&i[22]) | (i[31]&i[30]&i[22]&i[19]) | (i[31]&i[30] | |
247 | &!i[21]); | |
248 | ||
249 | assign store_u = (i[31]&!i[30]&!i[26]&i[24]&i[23]&!i[22]&!i[21]&!i[19]) | ( | |
250 | i[31]&i[30]&i[21]&!i[19]) | (i[31]&!i[30]&!i[28]&i[24]&i[23]&!i[22] | |
251 | &!i[21]&!i[19]) | (i[31]&!i[30]&i[24]&i[23]&!i[22]&!i[21]&i[20]) | ( | |
252 | i[31]&i[30]&!i[22]&i[21]) | (i[31]&i[30]&!i[24]&i[21]); | |
253 | ||
254 | assign prefetch_u = (i[31]&i[30]&i[24]&i[22]&i[19]); | |
255 | ||
256 | assign flush_u = (!i[30]&i[24]&i[23]&i[22]&i[20]&i[19]); | |
257 | ||
258 | assign memstbar_u = (i[31]&i[24]&!i[23]&i[22]&!i[21]&i[1]) | (i[31]&i[24]&!i[23] | |
259 | &i[22]&!i[21]&i[5]) | (i[31]&i[24]&!i[23]&i[22]&!i[21]&i[6]); | |
260 | ||
261 | assign sr_u = (i[31]&i[24]&!i[23]&i[22]&!i[21]&!i[20]&!i[19]&!i[17]) | (i[31] | |
262 | &i[24]&!i[23]&i[22]&!i[21]&!i[20]&!i[19]&!i[16]) | (i[31]&!i[30] | |
263 | &!i[28]&i[24]&i[23]&!i[22]&!i[21]&!i[20]&!i[19]) | (i[31]&!i[30] | |
264 | &!i[27]&i[24]&i[23]&!i[22]&!i[21]&!i[20]&!i[19]); | |
265 | ||
266 | assign pr_u = (i[31]&i[24]&!i[23]&i[22]&!i[21]&i[20]&!i[19]) | (i[31]&i[24] | |
267 | &i[23]&!i[22]&!i[21]&i[20]&!i[19]); | |
268 | ||
269 | assign hpr_u = (i[31]&i[24]&!i[23]&i[22]&!i[21]&!i[20]&i[19]) | (i[31]&!i[30] | |
270 | &i[24]&i[23]&!i[22]&i[20]&i[19]); | |
271 | ||
272 | assign ldstub_u = (i[31]&i[30]&!i[24]&i[22]&i[21]&!i[20]); | |
273 | ||
274 | assign alt_u = (i[31]&i[30]&i[23]&!i[13]); | |
275 | ||
276 | assign alti_u = (i[31]&i[30]&i[23]&i[13]); | |
277 | ||
278 | assign swap_u = (i[31]&i[30]&i[22]&i[21]&i[20]&i[19]); | |
279 | ||
280 | assign lsize_u[1] = (i[22]&i[21]&!i[19]) | (i[24]) | (i[20]&i[19]) | (!i[20] | |
281 | &!i[19]); | |
282 | ||
283 | assign lsize_u[0] = (i[20]&!i[19]) | (!i[30]) | (i[25]&i[24]&i[19]) | (!i[22] | |
284 | &i[20]) | (!i[21]&i[20]); | |
285 | ||
286 | assign killfgu_u = (i[31]&!i[30]&!i[13]&!i[10]&i[9]&i[8]); | |
287 | ||
288 | assign exu_src_u = (i[31]&i[24]&!i[23]&i[22]&i[21]&i[20]&!i[19]) | (i[31]&!i[30] | |
289 | &i[24]&!i[23]&!i[22]&i[21]&!i[20]&!i[19]) | (!i[30]&i[24]&i[23]&i[22] | |
290 | &i[21]&!i[20]) | (i[31]&!i[30]&i[22]&i[21]&!i[20]&i[19]) | (i[31] | |
291 | &!i[30]&!i[24]&i[22]&i[20]) | (i[31]&!i[30]&!i[24]&i[22]&i[19]); | |
292 | ||
293 | assign save_restore_u = (!i[30]&i[24]&i[23]&i[22]&i[21]&!i[20]); | |
294 | ||
295 | assign sir_u = (i[31]&!i[30]&i[28]&i[26]&i[24]&i[23]&!i[22]&!i[21]&!i[20]); | |
296 | ||
297 | assign stdfa_u = (i[31]&i[24]&i[23]&i[21]&i[20]&i[19]&!i[13]); | |
298 | ||
299 | assign fpdisable_u = (i[31]&!i[30]&!i[13]&i[12]&i[5]) | (!i[30]&i[24]&!i[23] | |
300 | &i[22]&!i[21]&!i[20]&!i[19]&i[18]&!i[16]&i[15]) | (!i[30]&i[29]&!i[27] | |
301 | &i[26]&i[24]&i[23]&!i[22]&!i[20]) | (i[31]&!i[30]&!i[13]&i[9]&i[8]) | ( | |
302 | i[31]&i[24]&!i[22]&!i[13]&i[11]) | (i[31]&i[24]&!i[22]&!i[13]&i[10]) | ( | |
303 | !i[30]&i[24]&!i[23]&i[22]&i[21]&!i[20]&!i[19]&!i[18]) | (!i[30]&i[24] | |
304 | &i[23]&!i[22]&i[21]&!i[20]) | (i[31]&i[30]&i[24]&!i[22]) | (!i[31] | |
305 | &!i[30]&i[24]&i[22]) | (!i[31]&!i[30]&i[24]&i[23]); | |
306 | ||
307 | assign wrtick_u = (i[31]&!i[30]&i[28]&!i[25]&i[24]&i[23]&!i[22]&!i[21]&!i[20]) | ( | |
308 | i[31]&!i[30]&!i[29]&i[27]&!i[26]&i[24]&i[23]&!i[22]&!i[21]&!i[20] | |
309 | &!i[19]); | |
310 | ||
311 | // end autogeneration | |
312 | ||
313 | ||
314 | // force decode to zeroes when the instruction is invalid | |
315 | assign kill_decode_d = illegal_d | ded_perr_d | ded_ferr_d; | |
316 | ||
317 | assign dcd_priv_d = priv_u & ~kill_decode_d; | |
318 | assign dcd_fsrc_rs1_d = fsrc_rs1_u & ~kill_decode_d; | |
319 | assign dcd_fsrc_rs2_d = fsrc_rs2_u & ~kill_decode_d; | |
320 | assign dcd_fpdest_single_d = fpdest_single_u & ~kill_decode_d; | |
321 | assign dcd_fp_rs1_single_d = fp_rs1_single_u & ~kill_decode_d; | |
322 | assign dcd_fp_rs2_single_d = fp_rs2_single_u & ~kill_decode_d; | |
323 | assign dcd_fsrsync_d = fsrsync_u & ~kill_decode_d; | |
324 | assign dcd_callclass_d = callclass_u & ~kill_decode_d; | |
325 | assign dcd_specbr_d = specbr_u & ~kill_decode_d; | |
326 | assign dcd_specfp_d = specfp_u & ~kill_decode_d; | |
327 | assign dcd_tcc_d = tcc_u & ~kill_decode_d; | |
328 | assign dcd_done_d = done_u & ~kill_decode_d; | |
329 | assign dcd_retry_d = retry_u & ~kill_decode_d; | |
330 | assign dcd_load_d = load_u & ~kill_decode_d; | |
331 | assign dcd_store_d = store_u & ~kill_decode_d; | |
332 | assign dcd_lsdouble_d = lsdouble_u & ~kill_decode_d; | |
333 | assign dcd_prefetch_d = prefetch_u & ~kill_decode_d; | |
334 | assign dcd_flush_d = flush_u & ~kill_decode_d; | |
335 | assign dcd_memstbar_d = memstbar_u & ~kill_decode_d; | |
336 | assign dcd_sr_d = sr_u & ~kill_decode_d; | |
337 | assign dcd_pr_d = pr_u & ~kill_decode_d; | |
338 | assign dcd_hpr_d = hpr_u & ~kill_decode_d; | |
339 | assign dcd_casa_d = casa_u & ~kill_decode_d; | |
340 | assign dcd_ldstub_d = ldstub_u & ~kill_decode_d; | |
341 | assign dcd_alt_d = alt_u & ~kill_decode_d; | |
342 | assign dcd_alti_d = alti_u & ~kill_decode_d; | |
343 | assign dcd_swap_d = swap_u & ~kill_decode_d; | |
344 | assign dcd_lsize_d[1:0] = lsize_u[1:0] & {2{~kill_decode_d}}; | |
345 | assign dcd_killfgu_d = killfgu_u & ~kill_decode_d; | |
346 | assign dcd_exu_src_d = exu_src_u & ~kill_decode_d; | |
347 | assign dcd_save_restore_d = save_restore_u & ~kill_decode_d; | |
348 | assign dcd_sir_d = sir_u & ~kill_decode_d; | |
349 | assign dcd_stdfa_d = stdfa_u & ~kill_decode_d; | |
350 | assign dcd_fpdisable_d = fpdisable_u & ~kill_decode_d; | |
351 | assign dcd_wrtick_d = wrtick_u & ~kill_decode_d; | |
352 | ||
353 | ||
354 | assign dcd_sethi_d = ~i[31] & ~i[30] & i[24] & ~i[23] & ~i[22] & i[21:0]==22'h0003f0; | |
355 | ||
356 | assign i[31:0] = dec_inst_d[31:0]; | |
357 | ||
358 | // all illegals are mapped to this before they are written into the icache | |
359 | assign illegal_d = ~i[31] & ~i[30] & ~i[24] & ~i[23] & ~i[22]; | |
360 | ||
361 | assign dcd_lsu_sign_ext_d = i[22] & ~i[21]; // op3[3:2]==10 | |
362 | ||
363 | supply0 vss; | |
364 | supply1 vdd; | |
365 | ||
366 | endmodule | |
367 | ||
368 | ||
369 | // Description: Spare gate macro for control blocks | |
370 | // | |
371 | // Param num controls the number of times the macro is added | |
372 | // flops=0 can be used to use only combination spare logic | |
373 | ||
374 | ||
375 | module dec_dcd_ctl_spare_ctl_macro__flops_0__num_2; | |
376 | wire spare0_buf_32x_unused; | |
377 | wire spare0_nand3_8x_unused; | |
378 | wire spare0_inv_8x_unused; | |
379 | wire spare0_aoi22_4x_unused; | |
380 | wire spare0_buf_8x_unused; | |
381 | wire spare0_oai22_4x_unused; | |
382 | wire spare0_inv_16x_unused; | |
383 | wire spare0_nand2_16x_unused; | |
384 | wire spare0_nor3_4x_unused; | |
385 | wire spare0_nand2_8x_unused; | |
386 | wire spare0_buf_16x_unused; | |
387 | wire spare0_nor2_16x_unused; | |
388 | wire spare0_inv_32x_unused; | |
389 | wire spare1_buf_32x_unused; | |
390 | wire spare1_nand3_8x_unused; | |
391 | wire spare1_inv_8x_unused; | |
392 | wire spare1_aoi22_4x_unused; | |
393 | wire spare1_buf_8x_unused; | |
394 | wire spare1_oai22_4x_unused; | |
395 | wire spare1_inv_16x_unused; | |
396 | wire spare1_nand2_16x_unused; | |
397 | wire spare1_nor3_4x_unused; | |
398 | wire spare1_nand2_8x_unused; | |
399 | wire spare1_buf_16x_unused; | |
400 | wire spare1_nor2_16x_unused; | |
401 | wire spare1_inv_32x_unused; | |
402 | ||
403 | ||
404 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
405 | .out(spare0_buf_32x_unused)); | |
406 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
407 | .in1(1'b1), | |
408 | .in2(1'b1), | |
409 | .out(spare0_nand3_8x_unused)); | |
410 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
411 | .out(spare0_inv_8x_unused)); | |
412 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
413 | .in01(1'b1), | |
414 | .in10(1'b1), | |
415 | .in11(1'b1), | |
416 | .out(spare0_aoi22_4x_unused)); | |
417 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
418 | .out(spare0_buf_8x_unused)); | |
419 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
420 | .in01(1'b1), | |
421 | .in10(1'b1), | |
422 | .in11(1'b1), | |
423 | .out(spare0_oai22_4x_unused)); | |
424 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
425 | .out(spare0_inv_16x_unused)); | |
426 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
427 | .in1(1'b1), | |
428 | .out(spare0_nand2_16x_unused)); | |
429 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
430 | .in1(1'b0), | |
431 | .in2(1'b0), | |
432 | .out(spare0_nor3_4x_unused)); | |
433 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
434 | .in1(1'b1), | |
435 | .out(spare0_nand2_8x_unused)); | |
436 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
437 | .out(spare0_buf_16x_unused)); | |
438 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
439 | .in1(1'b0), | |
440 | .out(spare0_nor2_16x_unused)); | |
441 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
442 | .out(spare0_inv_32x_unused)); | |
443 | ||
444 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
445 | .out(spare1_buf_32x_unused)); | |
446 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
447 | .in1(1'b1), | |
448 | .in2(1'b1), | |
449 | .out(spare1_nand3_8x_unused)); | |
450 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
451 | .out(spare1_inv_8x_unused)); | |
452 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
453 | .in01(1'b1), | |
454 | .in10(1'b1), | |
455 | .in11(1'b1), | |
456 | .out(spare1_aoi22_4x_unused)); | |
457 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
458 | .out(spare1_buf_8x_unused)); | |
459 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
460 | .in01(1'b1), | |
461 | .in10(1'b1), | |
462 | .in11(1'b1), | |
463 | .out(spare1_oai22_4x_unused)); | |
464 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
465 | .out(spare1_inv_16x_unused)); | |
466 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
467 | .in1(1'b1), | |
468 | .out(spare1_nand2_16x_unused)); | |
469 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
470 | .in1(1'b0), | |
471 | .in2(1'b0), | |
472 | .out(spare1_nor3_4x_unused)); | |
473 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
474 | .in1(1'b1), | |
475 | .out(spare1_nand2_8x_unused)); | |
476 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
477 | .out(spare1_buf_16x_unused)); | |
478 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
479 | .in1(1'b0), | |
480 | .out(spare1_nor2_16x_unused)); | |
481 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
482 | .out(spare1_inv_32x_unused)); | |
483 | ||
484 | ||
485 | ||
486 | endmodule | |
487 |