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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: tlu_ecd_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module tlu_ecd_dp ( | |
36 | data_in, | |
37 | ecc_in, | |
38 | cerer_ce, | |
39 | cerer_ue, | |
40 | syndrome, | |
41 | cecc_err, | |
42 | uecc_err, | |
43 | uecc_err_); | |
44 | wire [67:0] d; | |
45 | wire [7:0] e; | |
46 | wire [37:0] check0_bus; | |
47 | wire check0_4; | |
48 | wire check0_3; | |
49 | wire check0_2; | |
50 | wire check0_1; | |
51 | wire check0_0; | |
52 | wire c0; | |
53 | wire [37:0] check1_bus; | |
54 | wire check1_4; | |
55 | wire check1_3; | |
56 | wire check1_2; | |
57 | wire check1_1; | |
58 | wire check1_0; | |
59 | wire c1; | |
60 | wire [35:0] check2_bus; | |
61 | wire check2_4; | |
62 | wire check2_3; | |
63 | wire check2_2; | |
64 | wire check2_1; | |
65 | wire check2_0; | |
66 | wire c2; | |
67 | wire [35:0] check3_bus; | |
68 | wire check3_4; | |
69 | wire check3_3; | |
70 | wire check3_2; | |
71 | wire check3_1; | |
72 | wire check3_0; | |
73 | wire c3; | |
74 | wire [31:0] check4_bus; | |
75 | wire c4; | |
76 | wire [31:0] check5_bus; | |
77 | wire c5; | |
78 | wire [11:0] check6_bus; | |
79 | wire c6; | |
80 | wire [74:0] check7_bus; | |
81 | wire check7_4; | |
82 | wire check7_3; | |
83 | wire check7_2; | |
84 | wire check7_1; | |
85 | wire check7_0; | |
86 | wire c7; | |
87 | wire [7:7] e_; | |
88 | wire c7_; | |
89 | wire parity_incorrect; | |
90 | wire parity_correct; | |
91 | wire ecc_err_0; | |
92 | wire ecc_err_1; | |
93 | wire ecc_err_2; | |
94 | wire ecc_err; | |
95 | ||
96 | ||
97 | ||
98 | input [67:0] data_in; // Used for generation and checking | |
99 | input [7:0] ecc_in; // Used for checking only | |
100 | input cerer_ce; | |
101 | input cerer_ue; | |
102 | ||
103 | output [7:0] syndrome; // Used for generation and checking | |
104 | output cecc_err; // Used for checking only; unused for gen | |
105 | output uecc_err; // Used for checking only; unused for gen | |
106 | output uecc_err_; // Used for checking only; unused for gen | |
107 | ||
108 | ||
109 | ||
110 | ////////////////////////////////////////////////////////////////////////////// | |
111 | ||
112 | // Position Binary | |
113 | // 1 0000001 C0 | |
114 | // 2 0000010 C1 | |
115 | // 3 0000011 D0 | |
116 | // | |
117 | // 4 0000100 C2 | |
118 | // 5 0000101 D1 | |
119 | // 6 0000110 D2 | |
120 | // 7 0000111 D3 | |
121 | // | |
122 | // 8 0001000 C3 | |
123 | // 9 0001001 D4 | |
124 | // 10 0001010 D5 | |
125 | // 11 0001011 D6 | |
126 | // 12 0001100 D7 | |
127 | // ... ... | |
128 | // 15 0001111 D10 | |
129 | // | |
130 | // 16 0010000 C4 | |
131 | // 17 0010001 D11 | |
132 | // ... ... | |
133 | // 20 0010100 D14 | |
134 | // ... ... | |
135 | // 24 0011000 D18 | |
136 | // ... ... | |
137 | // 28 0011100 D22 | |
138 | // ... ... | |
139 | // 31 0011111 D25 | |
140 | // | |
141 | // 32 0100000 C5 | |
142 | // 33 0100001 D26 | |
143 | // ... ... | |
144 | // 36 0100100 D29 | |
145 | // ... ... | |
146 | // 40 0101000 D33 | |
147 | // ... ... | |
148 | // 44 0101100 D37 | |
149 | // ... ... | |
150 | // 48 0110000 D41 | |
151 | // ... ... | |
152 | // 52 0110100 D45 | |
153 | // ... ... | |
154 | // 56 0111000 D49 | |
155 | // ... ... | |
156 | // 60 0111100 D53 | |
157 | // ... ... | |
158 | // 63 0111111 D56 | |
159 | // | |
160 | // 64 1000000 C6 | |
161 | // 65 1000001 D57 | |
162 | // ... ... | |
163 | // 68 1000100 D60 | |
164 | // ... ... | |
165 | // 72 1001000 D64 | |
166 | // 73 1001001 D65 | |
167 | // 74 1001010 D66 | |
168 | // 75 1001011 D67 | |
169 | // | |
170 | // 76 1001100 C7 | |
171 | ||
172 | assign d[67:0] = | |
173 | data_in[67:0]; | |
174 | assign e[7:0] = | |
175 | ecc_in[7:0]; | |
176 | ||
177 | ||
178 | ||
179 | // All odd positions (LSB of position set) | |
180 | assign check0_bus[37:0] = | |
181 | {d[67], d[65], d[63], d[61], d[59], d[57], | |
182 | d[56], d[54], d[52], d[50], d[48], d[46], d[44], d[42], | |
183 | d[40], d[38], d[36], d[34], d[32], d[30], d[28], d[26], | |
184 | d[25], d[23], d[21], d[19], d[17], d[15], d[13], d[11], | |
185 | d[10], d[8], d[6], d[4], | |
186 | d[3], d[1], | |
187 | d[0], | |
188 | e[0]}; | |
189 | ||
190 | tlu_ecd_dp_prty_macro__width_8 check0_4_pty ( | |
191 | .din (check0_bus [37:30] ), | |
192 | .dout (check0_4 ) | |
193 | ); | |
194 | ||
195 | tlu_ecd_dp_prty_macro__width_8 check0_3_pty ( | |
196 | .din (check0_bus [29:22] ), | |
197 | .dout (check0_3 ) | |
198 | ); | |
199 | ||
200 | tlu_ecd_dp_prty_macro__width_8 check0_2_pty ( | |
201 | .din (check0_bus [21:14] ), | |
202 | .dout (check0_2 ) | |
203 | ); | |
204 | ||
205 | tlu_ecd_dp_prty_macro__width_8 check0_1_pty ( | |
206 | .din (check0_bus [13:6] ), | |
207 | .dout (check0_1 ) | |
208 | ); | |
209 | ||
210 | tlu_ecd_dp_prty_macro__width_8 check0_0_pty ( | |
211 | .din ({check0_bus [5:0], | |
212 | {2 {1'b0}} }), | |
213 | .dout (check0_0 ) | |
214 | ); | |
215 | ||
216 | tlu_ecd_dp_prty_macro__width_8 check0_pty ( | |
217 | .din ({check0_4 , | |
218 | check0_3 , | |
219 | check0_2 , | |
220 | check0_1 , | |
221 | check0_0 , | |
222 | {3 {1'b0}} }), | |
223 | .dout (c0 ) | |
224 | ); | |
225 | ||
226 | ||
227 | ||
228 | // All positions with secondmost LSB set | |
229 | assign check1_bus[37:0] = | |
230 | {d[67:66], d[63:62], d[59:58], | |
231 | d[56:55], d[52:51], d[48:47], d[44:43], | |
232 | d[40:39], d[36:35], d[32:31], d[28:27], | |
233 | d[25:24], d[21:20], d[17:16], d[13:12], | |
234 | d[10:9], d[6:5], | |
235 | d[3:2], | |
236 | d[0], | |
237 | e[1]}; | |
238 | ||
239 | tlu_ecd_dp_prty_macro__width_8 check1_4_pty ( | |
240 | .din (check1_bus [37:30] ), | |
241 | .dout (check1_4 ) | |
242 | ); | |
243 | ||
244 | tlu_ecd_dp_prty_macro__width_8 check1_3_pty ( | |
245 | .din (check1_bus [29:22] ), | |
246 | .dout (check1_3 ) | |
247 | ); | |
248 | ||
249 | tlu_ecd_dp_prty_macro__width_8 check1_2_pty ( | |
250 | .din (check1_bus [21:14] ), | |
251 | .dout (check1_2 ) | |
252 | ); | |
253 | ||
254 | tlu_ecd_dp_prty_macro__width_8 check1_1_pty ( | |
255 | .din (check1_bus [13:6] ), | |
256 | .dout (check1_1 ) | |
257 | ); | |
258 | ||
259 | tlu_ecd_dp_prty_macro__width_8 check1_0_pty ( | |
260 | .din ({check1_bus [5:0], | |
261 | {2 {1'b0}} }), | |
262 | .dout (check1_0 ) | |
263 | ); | |
264 | ||
265 | tlu_ecd_dp_prty_macro__width_8 check1_pty ( | |
266 | .din ({check1_0 , | |
267 | check1_1 , | |
268 | check1_2 , | |
269 | check1_3 , | |
270 | check1_4 , | |
271 | {3 {1'b0}} }), | |
272 | .dout (c1 ) | |
273 | ); | |
274 | ||
275 | ||
276 | ||
277 | // All positions with thirdmost LSB set | |
278 | assign check2_bus[35:0] = | |
279 | {d[63:60], | |
280 | d[56:53], d[48:45], d[40:37], d[32:29], | |
281 | d[25:22], d[17:14], | |
282 | d[10:7], | |
283 | d[3:1], | |
284 | e[2]}; | |
285 | ||
286 | tlu_ecd_dp_prty_macro__width_8 check2_4_pty ( | |
287 | .din ({1'b0, | |
288 | check2_bus [35:29]}), | |
289 | .dout (check2_4 ) | |
290 | ); | |
291 | ||
292 | tlu_ecd_dp_prty_macro__width_8 check2_3_pty ( | |
293 | .din (check2_bus [28:21] ), | |
294 | .dout (check2_3 ) | |
295 | ); | |
296 | ||
297 | tlu_ecd_dp_prty_macro__width_8 check2_2_pty ( | |
298 | .din (check2_bus [20:13] ), | |
299 | .dout (check2_2 ) | |
300 | ); | |
301 | ||
302 | tlu_ecd_dp_prty_macro__width_8 check2_1_pty ( | |
303 | .din (check2_bus [12:5] ), | |
304 | .dout (check2_1 ) | |
305 | ); | |
306 | ||
307 | tlu_ecd_dp_prty_macro__width_8 check2_0_pty ( | |
308 | .din ({check2_bus [4:0], | |
309 | {3 {1'b0}} }), | |
310 | .dout (check2_0 ) | |
311 | ); | |
312 | ||
313 | tlu_ecd_dp_prty_macro__width_8 check2_pty ( | |
314 | .din ({check2_0 , | |
315 | check2_1 , | |
316 | check2_2 , | |
317 | check2_3 , | |
318 | check2_4 , | |
319 | {3 {1'b0}} }), | |
320 | .dout (c2 ) | |
321 | ); | |
322 | ||
323 | ||
324 | ||
325 | // All positions with fourthmost LSB set | |
326 | assign check3_bus[35:0] = | |
327 | {d[67:64], | |
328 | d[56:49], d[40:33], | |
329 | d[25:18], | |
330 | d[10:4], | |
331 | e[3]}; | |
332 | ||
333 | tlu_ecd_dp_prty_macro__width_8 check3_4_pty ( | |
334 | .din ({{1 {1'b0}} , | |
335 | check3_bus [35:29]}), | |
336 | .dout (check3_4 ) | |
337 | ); | |
338 | ||
339 | tlu_ecd_dp_prty_macro__width_8 check3_3_pty ( | |
340 | .din (check3_bus [28:21] ), | |
341 | .dout (check3_3 ) | |
342 | ); | |
343 | ||
344 | tlu_ecd_dp_prty_macro__width_8 check3_2_pty ( | |
345 | .din (check3_bus [20:13] ), | |
346 | .dout (check3_2 ) | |
347 | ); | |
348 | ||
349 | tlu_ecd_dp_prty_macro__width_8 check3_1_pty ( | |
350 | .din (check3_bus [12:5] ), | |
351 | .dout (check3_1 ) | |
352 | ); | |
353 | ||
354 | tlu_ecd_dp_prty_macro__width_8 check3_0_pty ( | |
355 | .din ({check3_bus [4:0], | |
356 | {3 {1'b0}} }), | |
357 | .dout (check3_0 ) | |
358 | ); | |
359 | ||
360 | tlu_ecd_dp_prty_macro__width_8 check3_pty ( | |
361 | .din ({check3_0 , | |
362 | check3_1 , | |
363 | check3_2 , | |
364 | check3_3 , | |
365 | check3_4 , | |
366 | {3 {1'b0}} }), | |
367 | .dout (c3 ) | |
368 | ); | |
369 | ||
370 | ||
371 | // All positions with fifthmost LSB set | |
372 | assign check4_bus[31:0] = | |
373 | {d[56:41], | |
374 | d[25:11], | |
375 | e[4]}; | |
376 | ||
377 | tlu_ecd_dp_prty_macro__width_32 check4_pty ( | |
378 | .din (check4_bus [31:0] ), | |
379 | .dout (c4 ) | |
380 | ); | |
381 | ||
382 | ||
383 | ||
384 | // All positions with sixthmost LSB set | |
385 | assign check5_bus[31:0] = | |
386 | {d[56:26], | |
387 | e[5]}; | |
388 | ||
389 | tlu_ecd_dp_prty_macro__width_32 check5_pty ( | |
390 | .din (check5_bus [31:0] ), | |
391 | .dout (c5 ) | |
392 | ); | |
393 | ||
394 | ||
395 | ||
396 | // All positions with seventhmost LSB set | |
397 | assign check6_bus[11:0] = | |
398 | {d[67:57], | |
399 | e[6]}; | |
400 | ||
401 | tlu_ecd_dp_prty_macro__width_16 check6_pty ( | |
402 | .din ({{4 {1'b0}} , | |
403 | check6_bus [11:0]}), | |
404 | .dout (c6 ) | |
405 | ); | |
406 | ||
407 | ||
408 | ||
409 | // Parity of the whole word (including ECC bits) | |
410 | // Then xnor with e[07] to check the parity | |
411 | // (or in this case, xor with e[07] to get miscompare) | |
412 | assign check7_bus[74:0] = | |
413 | {d[67:0], e[6:0]}; | |
414 | ||
415 | tlu_ecd_dp_prty_macro__width_16 check7_4_pty ( | |
416 | .din ({{5 {1'b0}} , | |
417 | check7_bus [74:64]}), | |
418 | .dout (check7_4 ) | |
419 | ); | |
420 | ||
421 | tlu_ecd_dp_prty_macro__width_16 check7_3_pty ( | |
422 | .din (check7_bus [63:48] ), | |
423 | .dout (check7_3 ) | |
424 | ); | |
425 | ||
426 | tlu_ecd_dp_prty_macro__width_16 check7_2_pty ( | |
427 | .din (check7_bus [47:32] ), | |
428 | .dout (check7_2 ) | |
429 | ); | |
430 | ||
431 | tlu_ecd_dp_prty_macro__width_16 check7_1_pty ( | |
432 | .din (check7_bus [31:16] ), | |
433 | .dout (check7_1 ) | |
434 | ); | |
435 | ||
436 | tlu_ecd_dp_prty_macro__width_16 check7_0_pty ( | |
437 | .din (check7_bus [15:0] ), | |
438 | .dout (check7_0 ) | |
439 | ); | |
440 | ||
441 | tlu_ecd_dp_prty_macro__width_8 check7_inv_pty ( | |
442 | .din ({{2 {1'b0}} , | |
443 | e [7 ], | |
444 | check7_0 , | |
445 | check7_1 , | |
446 | check7_2 , | |
447 | check7_3 , | |
448 | check7_4 }), | |
449 | .dout (c7 ) | |
450 | ); | |
451 | ||
452 | tlu_ecd_dp_inv_macro__width_1 e7_inv ( | |
453 | .din (e [7 ] ), | |
454 | .dout (e_ [7 ] ) | |
455 | ); | |
456 | ||
457 | tlu_ecd_dp_prty_macro__width_8 check7_pty ( | |
458 | .din ({{2 {1'b0}} , | |
459 | e_ [7 ], | |
460 | check7_0 , | |
461 | check7_1 , | |
462 | check7_2 , | |
463 | check7_3 , | |
464 | check7_4 }), | |
465 | .dout (c7_ ) | |
466 | ); | |
467 | ||
468 | assign parity_incorrect = | |
469 | c7; | |
470 | ||
471 | assign parity_correct = | |
472 | c7_; | |
473 | ||
474 | ||
475 | assign syndrome[7:0] = | |
476 | {c7, c6, c5, c4, c3, c2, c1, c0}; | |
477 | ||
478 | ||
479 | ||
480 | // If the syndrome is zero and overall parity is correct, then no errors | |
481 | ||
482 | // If overall parity is incorrect, then correctable | |
483 | //assign cecc_err = | |
484 | // c7; | |
485 | // If overall parity is correct and the syndrome is nonzero, then uncorrectable | |
486 | //assign uecc_err = | |
487 | // (| ecc_out[06:00]) & ~c7; | |
488 | // Also need to factor in CERER bits | |
489 | ||
490 | tlu_ecd_dp_nor_macro__ports_3__width_1 ecc_err_2_nor ( | |
491 | .din0 (syndrome [6] ), | |
492 | .din1 (syndrome [5] ), | |
493 | .din2 (syndrome [4] ), | |
494 | .dout (ecc_err_0 ) | |
495 | ); | |
496 | ||
497 | tlu_ecd_dp_nor_macro__ports_2__width_1 ecc_err_1_nor ( | |
498 | .din0 (syndrome [3] ), | |
499 | .din1 (syndrome [2] ), | |
500 | .dout (ecc_err_1 ) | |
501 | ); | |
502 | ||
503 | tlu_ecd_dp_nor_macro__ports_2__width_1 ecc_err_0_nor ( | |
504 | .din0 (syndrome [1] ), | |
505 | .din1 (syndrome [0] ), | |
506 | .dout (ecc_err_2 ) | |
507 | ); | |
508 | ||
509 | tlu_ecd_dp_nand_macro__ports_3__width_1 ecc_err_nand ( | |
510 | .din0 (ecc_err_0 ), | |
511 | .din1 (ecc_err_1 ), | |
512 | .din2 (ecc_err_2 ), | |
513 | .dout (ecc_err ) | |
514 | ); | |
515 | ||
516 | tlu_ecd_dp_and_macro__ports_2__width_1 cecc_err_and ( | |
517 | .din0 (parity_incorrect ), | |
518 | .din1 (cerer_ce ), | |
519 | .dout (cecc_err ) | |
520 | ); | |
521 | ||
522 | tlu_ecd_dp_and_macro__ports_3__width_1 uecc_err_and ( | |
523 | .din0 (ecc_err ), | |
524 | .din1 (parity_correct ), | |
525 | .din2 (cerer_ue ), | |
526 | .dout (uecc_err ) | |
527 | ); | |
528 | ||
529 | tlu_ecd_dp_nand_macro__ports_3__width_1 uecc_err_nand ( | |
530 | .din0 (ecc_err ), | |
531 | .din1 (parity_correct ), | |
532 | .din2 (cerer_ue ), | |
533 | .dout (uecc_err_ ) | |
534 | ); | |
535 | ||
536 | ||
537 | supply0 vss; // <- port for ground | |
538 | supply1 vdd; // <- port for power | |
539 | ||
540 | endmodule | |
541 | ||
542 | ||
543 | ||
544 | // | |
545 | // parity macro (even parity) | |
546 | // | |
547 | // | |
548 | ||
549 | ||
550 | ||
551 | ||
552 | ||
553 | module tlu_ecd_dp_prty_macro__width_8 ( | |
554 | din, | |
555 | dout); | |
556 | input [7:0] din; | |
557 | output dout; | |
558 | ||
559 | ||
560 | ||
561 | ||
562 | ||
563 | ||
564 | ||
565 | prty #(8) m0_0 ( | |
566 | .in(din[7:0]), | |
567 | .out(dout) | |
568 | ); | |
569 | ||
570 | ||
571 | ||
572 | ||
573 | ||
574 | ||
575 | ||
576 | ||
577 | ||
578 | ||
579 | endmodule | |
580 | ||
581 | ||
582 | ||
583 | ||
584 | ||
585 | // | |
586 | // parity macro (even parity) | |
587 | // | |
588 | // | |
589 | ||
590 | ||
591 | ||
592 | ||
593 | ||
594 | module tlu_ecd_dp_prty_macro__width_32 ( | |
595 | din, | |
596 | dout); | |
597 | input [31:0] din; | |
598 | output dout; | |
599 | ||
600 | ||
601 | ||
602 | ||
603 | ||
604 | ||
605 | ||
606 | prty #(32) m0_0 ( | |
607 | .in(din[31:0]), | |
608 | .out(dout) | |
609 | ); | |
610 | ||
611 | ||
612 | ||
613 | ||
614 | ||
615 | ||
616 | ||
617 | ||
618 | ||
619 | ||
620 | endmodule | |
621 | ||
622 | ||
623 | ||
624 | ||
625 | ||
626 | // | |
627 | // parity macro (even parity) | |
628 | // | |
629 | // | |
630 | ||
631 | ||
632 | ||
633 | ||
634 | ||
635 | module tlu_ecd_dp_prty_macro__width_16 ( | |
636 | din, | |
637 | dout); | |
638 | input [15:0] din; | |
639 | output dout; | |
640 | ||
641 | ||
642 | ||
643 | ||
644 | ||
645 | ||
646 | ||
647 | prty #(16) m0_0 ( | |
648 | .in(din[15:0]), | |
649 | .out(dout) | |
650 | ); | |
651 | ||
652 | ||
653 | ||
654 | ||
655 | ||
656 | ||
657 | ||
658 | ||
659 | ||
660 | ||
661 | endmodule | |
662 | ||
663 | ||
664 | ||
665 | ||
666 | ||
667 | // | |
668 | // invert macro | |
669 | // | |
670 | // | |
671 | ||
672 | ||
673 | ||
674 | ||
675 | ||
676 | module tlu_ecd_dp_inv_macro__width_1 ( | |
677 | din, | |
678 | dout); | |
679 | input [0:0] din; | |
680 | output [0:0] dout; | |
681 | ||
682 | ||
683 | ||
684 | ||
685 | ||
686 | ||
687 | inv #(1) d0_0 ( | |
688 | .in(din[0:0]), | |
689 | .out(dout[0:0]) | |
690 | ); | |
691 | ||
692 | ||
693 | ||
694 | ||
695 | ||
696 | ||
697 | ||
698 | ||
699 | ||
700 | endmodule | |
701 | ||
702 | ||
703 | ||
704 | ||
705 | ||
706 | // | |
707 | // nor macro for ports = 2,3 | |
708 | // | |
709 | // | |
710 | ||
711 | ||
712 | ||
713 | ||
714 | ||
715 | module tlu_ecd_dp_nor_macro__ports_3__width_1 ( | |
716 | din0, | |
717 | din1, | |
718 | din2, | |
719 | dout); | |
720 | input [0:0] din0; | |
721 | input [0:0] din1; | |
722 | input [0:0] din2; | |
723 | output [0:0] dout; | |
724 | ||
725 | ||
726 | ||
727 | ||
728 | ||
729 | ||
730 | nor3 #(1) d0_0 ( | |
731 | .in0(din0[0:0]), | |
732 | .in1(din1[0:0]), | |
733 | .in2(din2[0:0]), | |
734 | .out(dout[0:0]) | |
735 | ); | |
736 | ||
737 | ||
738 | ||
739 | ||
740 | ||
741 | ||
742 | ||
743 | endmodule | |
744 | ||
745 | ||
746 | ||
747 | ||
748 | ||
749 | // | |
750 | // nor macro for ports = 2,3 | |
751 | // | |
752 | // | |
753 | ||
754 | ||
755 | ||
756 | ||
757 | ||
758 | module tlu_ecd_dp_nor_macro__ports_2__width_1 ( | |
759 | din0, | |
760 | din1, | |
761 | dout); | |
762 | input [0:0] din0; | |
763 | input [0:0] din1; | |
764 | output [0:0] dout; | |
765 | ||
766 | ||
767 | ||
768 | ||
769 | ||
770 | ||
771 | nor2 #(1) d0_0 ( | |
772 | .in0(din0[0:0]), | |
773 | .in1(din1[0:0]), | |
774 | .out(dout[0:0]) | |
775 | ); | |
776 | ||
777 | ||
778 | ||
779 | ||
780 | ||
781 | ||
782 | ||
783 | endmodule | |
784 | ||
785 | ||
786 | ||
787 | ||
788 | ||
789 | // | |
790 | // nand macro for ports = 2,3,4 | |
791 | // | |
792 | // | |
793 | ||
794 | ||
795 | ||
796 | ||
797 | ||
798 | module tlu_ecd_dp_nand_macro__ports_3__width_1 ( | |
799 | din0, | |
800 | din1, | |
801 | din2, | |
802 | dout); | |
803 | input [0:0] din0; | |
804 | input [0:0] din1; | |
805 | input [0:0] din2; | |
806 | output [0:0] dout; | |
807 | ||
808 | ||
809 | ||
810 | ||
811 | ||
812 | ||
813 | nand3 #(1) d0_0 ( | |
814 | .in0(din0[0:0]), | |
815 | .in1(din1[0:0]), | |
816 | .in2(din2[0:0]), | |
817 | .out(dout[0:0]) | |
818 | ); | |
819 | ||
820 | ||
821 | ||
822 | ||
823 | ||
824 | ||
825 | ||
826 | ||
827 | ||
828 | endmodule | |
829 | ||
830 | ||
831 | ||
832 | ||
833 | ||
834 | // | |
835 | // and macro for ports = 2,3,4 | |
836 | // | |
837 | // | |
838 | ||
839 | ||
840 | ||
841 | ||
842 | ||
843 | module tlu_ecd_dp_and_macro__ports_2__width_1 ( | |
844 | din0, | |
845 | din1, | |
846 | dout); | |
847 | input [0:0] din0; | |
848 | input [0:0] din1; | |
849 | output [0:0] dout; | |
850 | ||
851 | ||
852 | ||
853 | ||
854 | ||
855 | ||
856 | and2 #(1) d0_0 ( | |
857 | .in0(din0[0:0]), | |
858 | .in1(din1[0:0]), | |
859 | .out(dout[0:0]) | |
860 | ); | |
861 | ||
862 | ||
863 | ||
864 | ||
865 | ||
866 | ||
867 | ||
868 | ||
869 | ||
870 | endmodule | |
871 | ||
872 | ||
873 | ||
874 | ||
875 | ||
876 | // | |
877 | // and macro for ports = 2,3,4 | |
878 | // | |
879 | // | |
880 | ||
881 | ||
882 | ||
883 | ||
884 | ||
885 | module tlu_ecd_dp_and_macro__ports_3__width_1 ( | |
886 | din0, | |
887 | din1, | |
888 | din2, | |
889 | dout); | |
890 | input [0:0] din0; | |
891 | input [0:0] din1; | |
892 | input [0:0] din2; | |
893 | output [0:0] dout; | |
894 | ||
895 | ||
896 | ||
897 | ||
898 | ||
899 | ||
900 | and3 #(1) d0_0 ( | |
901 | .in0(din0[0:0]), | |
902 | .in1(din1[0:0]), | |
903 | .in2(din2[0:0]), | |
904 | .out(dout[0:0]) | |
905 | ); | |
906 | ||
907 | ||
908 | ||
909 | ||
910 | ||
911 | ||
912 | ||
913 | ||
914 | ||
915 | endmodule | |
916 | ||
917 | ||
918 | ||
919 |