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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: n2_arf_dp_16x128_cust.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | ||
36 | //////////////////////////////////////////////////////////////////////////////// | |
37 | // $Id: n2_arf_dp_16x128_cust.sv,v 1.13 2005/06/17 18:57:37 co132877 Exp $ | |
38 | // | |
39 | // Copyright (C) 2003 by Sun Microsystems, Inc. | |
40 | // | |
41 | // All rights reserved. No part of this design may be reproduced, | |
42 | // stored in a retrieval system, or transmitted, in any form or by | |
43 | // any means, electronic, mechanical, photocopying, recording, or | |
44 | // otherwise, without prior written permission of Sun Microsystems, | |
45 | // Inc. | |
46 | // | |
47 | // Sun Proprietary/Confidential | |
48 | // | |
49 | // Description: SPU AES Key Register File | |
50 | // - 16 entry, 128-bit with a two bit interleave | |
51 | // - 1 Read | |
52 | // - 1 Write | |
53 | // + no write bypassing necessary (internal or external) | |
54 | // + 64-bit writeable with 64-bit write data | |
55 | // - Logically holds up to 60 32-bit keys | |
56 | // | |
57 | // | |
58 | // The 128-bits are interleaved in such a way so the output | |
59 | // will match the 64-bit datapath below. | |
60 | // | |
61 | // Datapath -> 63 62 1 0 | |
62 | // Array -> [127],[63] [126],[62] ... [65],[1] [64],[0] | |
63 | // | |
64 | // | |
65 | // Primary Contact: christopher.olson@sun.com | |
66 | //////////////////////////////////////////////////////////////////////////////// | |
67 | ||
68 | ||
69 | module n2_arf_dp_16x128_cust ( | |
70 | l2clk, | |
71 | scan_in, | |
72 | pce, | |
73 | tcu_pce_ov, | |
74 | tcu_array_wr_inhibit, | |
75 | tcu_se_scancollar_in, | |
76 | tcu_scan_en, | |
77 | tcu_aclk, | |
78 | tcu_bclk, | |
79 | clken, | |
80 | rd_addr, | |
81 | rd_enable, | |
82 | wr_addr, | |
83 | wr_data, | |
84 | wr_enable, | |
85 | arf_rd_data, | |
86 | scan_out); | |
87 | wire siclk; | |
88 | wire soclk; | |
89 | wire l1clk; | |
90 | wire [31:0] i_wr_data_ff0_scanin; | |
91 | wire [31:0] i_wr_data_ff0_scanout; | |
92 | wire [63:0] wr_data_ff; | |
93 | wire [3:0] i_wr_addr_ff_scanin; | |
94 | wire [3:0] i_wr_addr_ff_scanout; | |
95 | wire [3:0] wr_addr_ff; | |
96 | wire [1:0] i_wr_en_ff_scanin; | |
97 | wire [1:0] i_wr_en_ff_scanout; | |
98 | wire [1:0] wr_enable_ff; | |
99 | wire [4:0] i_rd_ff_scanin; | |
100 | wire [4:0] i_rd_ff_scanout; | |
101 | wire l1clk_free; | |
102 | wire [3:0] rd_addr_ff; | |
103 | wire rd_enable_ff; | |
104 | wire [4:0] rd_lat_l_unused; | |
105 | wire [4:0] rd_dout_l_unused; | |
106 | wire [4:0] rd_dout_unused; | |
107 | wire [31:0] i_wr_data_ff1_scanin; | |
108 | wire [31:0] i_wr_data_ff1_scanout; | |
109 | ||
110 | ||
111 | input l2clk; | |
112 | input scan_in; | |
113 | input pce; | |
114 | input tcu_pce_ov; | |
115 | ||
116 | input tcu_array_wr_inhibit; | |
117 | input tcu_se_scancollar_in; | |
118 | input tcu_scan_en; | |
119 | input tcu_aclk; | |
120 | input tcu_bclk; | |
121 | input clken; | |
122 | input [3:0] rd_addr; | |
123 | input rd_enable; | |
124 | input [3:0] wr_addr; | |
125 | input [63:0] wr_data; | |
126 | input [1:0] wr_enable; | |
127 | ||
128 | output [127:0] arf_rd_data; | |
129 | ||
130 | output scan_out; | |
131 | ||
132 | ||
133 | ||
134 | assign siclk = tcu_aclk; | |
135 | assign soclk = tcu_bclk; | |
136 | ||
137 | ||
138 | n2_arf_dp_16x128_cust_l1clkhdr_ctl_macro clkgen ( | |
139 | .l2clk (l2clk ), | |
140 | .l1en (clken ), | |
141 | .pce_ov (tcu_pce_ov ), | |
142 | .stop (1'b0 ), | |
143 | .se (tcu_se_scancollar_in ), | |
144 | .l1clk (l1clk )); | |
145 | ||
146 | ||
147 | ||
148 | n2_arf_dp_16x128_cust_msff_ctl_macro__fs_1__scanreverse_1__width_32 i_wr_data_ff0 ( | |
149 | .scan_in(i_wr_data_ff0_scanin[31:0]), | |
150 | .scan_out(i_wr_data_ff0_scanout[31:0]), | |
151 | .l1clk( l1clk ), | |
152 | .din ( wr_data[31:0] ), | |
153 | .dout ( wr_data_ff[31:0] ), | |
154 | .siclk(siclk), | |
155 | .soclk(soclk)); | |
156 | ||
157 | ||
158 | n2_arf_dp_16x128_cust_msff_ctl_macro__fs_1__scanreverse_1__width_4 i_wr_addr_ff ( | |
159 | .scan_in(i_wr_addr_ff_scanin[3:0]), | |
160 | .scan_out(i_wr_addr_ff_scanout[3:0]), | |
161 | .l1clk( l1clk ), | |
162 | .din ( wr_addr[3:0] ), | |
163 | .dout ( wr_addr_ff[3:0] ), | |
164 | .siclk(siclk), | |
165 | .soclk(soclk)); | |
166 | ||
167 | ||
168 | n2_arf_dp_16x128_cust_msff_ctl_macro__fs_1__scanreverse_1__width_2 i_wr_en_ff ( | |
169 | .scan_in(i_wr_en_ff_scanin[1:0]), | |
170 | .scan_out(i_wr_en_ff_scanout[1:0]), | |
171 | .l1clk( l1clk ), | |
172 | .din ( wr_enable[1:0] ), | |
173 | .dout ( wr_enable_ff[1:0] ), | |
174 | .siclk(siclk), | |
175 | .soclk(soclk)); | |
176 | ||
177 | ||
178 | n2_arf_dp_16x128_cust_sram_msff_mo_macro__fs_1__scanreverse_1__width_5 i_rd_ff ( | |
179 | .scan_in(i_rd_ff_scanin[4:0]), | |
180 | .scan_out(i_rd_ff_scanout[4:0]), | |
181 | .l1clk ( l1clk ), | |
182 | .and_clk ( l1clk_free ), | |
183 | .d ({rd_addr[3:0] , rd_enable} ), | |
184 | .mq ({rd_addr_ff[3:0] , rd_enable_ff} ), | |
185 | .mq_l ( rd_lat_l_unused[4:0] ), | |
186 | .q_l ( rd_dout_l_unused[4:0] ), | |
187 | .q ( rd_dout_unused[4:0] ), | |
188 | .siclk(siclk), | |
189 | .soclk(soclk)); | |
190 | ||
191 | ||
192 | n2_arf_dp_16x128_cust_msff_ctl_macro__fs_1__scanreverse_1__width_32 i_wr_data_ff1 ( | |
193 | .scan_in(i_wr_data_ff1_scanin[31:0]), | |
194 | .scan_out(i_wr_data_ff1_scanout[31:0]), | |
195 | .l1clk( l1clk ), | |
196 | .din ( wr_data[63:32] ), | |
197 | .dout ( wr_data_ff[63:32] ), | |
198 | .siclk(siclk), | |
199 | .soclk(soclk)); | |
200 | ||
201 | ||
202 | ||
203 | ||
204 | // L2 clock "free-running" clock | |
205 | n2_arf_dp_16x128_cust_l1clkhdr_ctl_macro clkgen_free ( | |
206 | .l2clk (l2clk ), | |
207 | .l1en (pce ), | |
208 | .pce_ov (tcu_pce_ov ), | |
209 | .stop (1'b0 ), | |
210 | .se (tcu_scan_en ), | |
211 | .l1clk (l1clk_free )); | |
212 | ||
213 | ||
214 | lib_16x64b_1r1w_array arf_array0 ( | |
215 | .clk ( l1clk_free ), | |
216 | .rd_addr ( rd_addr_ff[3:0] ), | |
217 | .rd_en ( rd_enable_ff ), | |
218 | .wr_addr ( wr_addr_ff[3:0] ), | |
219 | .wr_en ( wr_enable_ff[0] ), | |
220 | .din ( wr_data_ff[63:0] ), | |
221 | .dout ( arf_rd_data[63:0] ), | |
222 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit)); | |
223 | ||
224 | ||
225 | ||
226 | lib_16x64b_1r1w_array arf_array1 ( | |
227 | .clk ( l1clk_free ), | |
228 | .rd_addr ( rd_addr_ff[3:0] ), | |
229 | .rd_en ( rd_enable_ff ), | |
230 | .wr_addr ( wr_addr_ff[3:0] ), | |
231 | .wr_en ( wr_enable_ff[1] ), | |
232 | .din ( wr_data_ff[63:0] ), | |
233 | .dout ( arf_rd_data[127:64] ), | |
234 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit)); | |
235 | ||
236 | ||
237 | ||
238 | ||
239 | ||
240 | supply0 vss; | |
241 | supply1 vdd; | |
242 | ||
243 | ||
244 | ||
245 | ||
246 | ||
247 | // scanorder start | |
248 | // i_wr_data_ff0_scanin[0:31] | |
249 | // i_wr_addr_ff_scanin[0:3] | |
250 | // i_wr_en_ff_scanin[0:1] | |
251 | // i_rd_ff_scanin[0:4] | |
252 | // i_wr_data_ff1_scanin[0:31] | |
253 | // scanorder end | |
254 | // fixscan start | |
255 | assign i_wr_data_ff0_scanin[0]=scan_in; | |
256 | assign i_wr_data_ff0_scanin[1]=i_wr_data_ff0_scanout[0]; | |
257 | assign i_wr_data_ff0_scanin[2]=i_wr_data_ff0_scanout[1]; | |
258 | assign i_wr_data_ff0_scanin[3]=i_wr_data_ff0_scanout[2]; | |
259 | assign i_wr_data_ff0_scanin[4]=i_wr_data_ff0_scanout[3]; | |
260 | assign i_wr_data_ff0_scanin[5]=i_wr_data_ff0_scanout[4]; | |
261 | assign i_wr_data_ff0_scanin[6]=i_wr_data_ff0_scanout[5]; | |
262 | assign i_wr_data_ff0_scanin[7]=i_wr_data_ff0_scanout[6]; | |
263 | assign i_wr_data_ff0_scanin[8]=i_wr_data_ff0_scanout[7]; | |
264 | assign i_wr_data_ff0_scanin[9]=i_wr_data_ff0_scanout[8]; | |
265 | assign i_wr_data_ff0_scanin[10]=i_wr_data_ff0_scanout[9]; | |
266 | assign i_wr_data_ff0_scanin[11]=i_wr_data_ff0_scanout[10]; | |
267 | assign i_wr_data_ff0_scanin[12]=i_wr_data_ff0_scanout[11]; | |
268 | assign i_wr_data_ff0_scanin[13]=i_wr_data_ff0_scanout[12]; | |
269 | assign i_wr_data_ff0_scanin[14]=i_wr_data_ff0_scanout[13]; | |
270 | assign i_wr_data_ff0_scanin[15]=i_wr_data_ff0_scanout[14]; | |
271 | assign i_wr_data_ff0_scanin[16]=i_wr_data_ff0_scanout[15]; | |
272 | assign i_wr_data_ff0_scanin[17]=i_wr_data_ff0_scanout[16]; | |
273 | assign i_wr_data_ff0_scanin[18]=i_wr_data_ff0_scanout[17]; | |
274 | assign i_wr_data_ff0_scanin[19]=i_wr_data_ff0_scanout[18]; | |
275 | assign i_wr_data_ff0_scanin[20]=i_wr_data_ff0_scanout[19]; | |
276 | assign i_wr_data_ff0_scanin[21]=i_wr_data_ff0_scanout[20]; | |
277 | assign i_wr_data_ff0_scanin[22]=i_wr_data_ff0_scanout[21]; | |
278 | assign i_wr_data_ff0_scanin[23]=i_wr_data_ff0_scanout[22]; | |
279 | assign i_wr_data_ff0_scanin[24]=i_wr_data_ff0_scanout[23]; | |
280 | assign i_wr_data_ff0_scanin[25]=i_wr_data_ff0_scanout[24]; | |
281 | assign i_wr_data_ff0_scanin[26]=i_wr_data_ff0_scanout[25]; | |
282 | assign i_wr_data_ff0_scanin[27]=i_wr_data_ff0_scanout[26]; | |
283 | assign i_wr_data_ff0_scanin[28]=i_wr_data_ff0_scanout[27]; | |
284 | assign i_wr_data_ff0_scanin[29]=i_wr_data_ff0_scanout[28]; | |
285 | assign i_wr_data_ff0_scanin[30]=i_wr_data_ff0_scanout[29]; | |
286 | assign i_wr_data_ff0_scanin[31]=i_wr_data_ff0_scanout[30]; | |
287 | assign i_wr_addr_ff_scanin[0]=i_wr_data_ff0_scanout[31]; | |
288 | assign i_wr_addr_ff_scanin[1]=i_wr_addr_ff_scanout[0]; | |
289 | assign i_wr_addr_ff_scanin[2]=i_wr_addr_ff_scanout[1]; | |
290 | assign i_wr_addr_ff_scanin[3]=i_wr_addr_ff_scanout[2]; | |
291 | assign i_wr_en_ff_scanin[0]=i_wr_addr_ff_scanout[3]; | |
292 | assign i_wr_en_ff_scanin[1]=i_wr_en_ff_scanout[0]; | |
293 | assign i_rd_ff_scanin[0]=i_wr_en_ff_scanout[1]; | |
294 | assign i_rd_ff_scanin[1]=i_rd_ff_scanout[0]; | |
295 | assign i_rd_ff_scanin[2]=i_rd_ff_scanout[1]; | |
296 | assign i_rd_ff_scanin[3]=i_rd_ff_scanout[2]; | |
297 | assign i_rd_ff_scanin[4]=i_rd_ff_scanout[3]; | |
298 | assign i_wr_data_ff1_scanin[0]=i_rd_ff_scanout[4]; | |
299 | assign i_wr_data_ff1_scanin[1]=i_wr_data_ff1_scanout[0]; | |
300 | assign i_wr_data_ff1_scanin[2]=i_wr_data_ff1_scanout[1]; | |
301 | assign i_wr_data_ff1_scanin[3]=i_wr_data_ff1_scanout[2]; | |
302 | assign i_wr_data_ff1_scanin[4]=i_wr_data_ff1_scanout[3]; | |
303 | assign i_wr_data_ff1_scanin[5]=i_wr_data_ff1_scanout[4]; | |
304 | assign i_wr_data_ff1_scanin[6]=i_wr_data_ff1_scanout[5]; | |
305 | assign i_wr_data_ff1_scanin[7]=i_wr_data_ff1_scanout[6]; | |
306 | assign i_wr_data_ff1_scanin[8]=i_wr_data_ff1_scanout[7]; | |
307 | assign i_wr_data_ff1_scanin[9]=i_wr_data_ff1_scanout[8]; | |
308 | assign i_wr_data_ff1_scanin[10]=i_wr_data_ff1_scanout[9]; | |
309 | assign i_wr_data_ff1_scanin[11]=i_wr_data_ff1_scanout[10]; | |
310 | assign i_wr_data_ff1_scanin[12]=i_wr_data_ff1_scanout[11]; | |
311 | assign i_wr_data_ff1_scanin[13]=i_wr_data_ff1_scanout[12]; | |
312 | assign i_wr_data_ff1_scanin[14]=i_wr_data_ff1_scanout[13]; | |
313 | assign i_wr_data_ff1_scanin[15]=i_wr_data_ff1_scanout[14]; | |
314 | assign i_wr_data_ff1_scanin[16]=i_wr_data_ff1_scanout[15]; | |
315 | assign i_wr_data_ff1_scanin[17]=i_wr_data_ff1_scanout[16]; | |
316 | assign i_wr_data_ff1_scanin[18]=i_wr_data_ff1_scanout[17]; | |
317 | assign i_wr_data_ff1_scanin[19]=i_wr_data_ff1_scanout[18]; | |
318 | assign i_wr_data_ff1_scanin[20]=i_wr_data_ff1_scanout[19]; | |
319 | assign i_wr_data_ff1_scanin[21]=i_wr_data_ff1_scanout[20]; | |
320 | assign i_wr_data_ff1_scanin[22]=i_wr_data_ff1_scanout[21]; | |
321 | assign i_wr_data_ff1_scanin[23]=i_wr_data_ff1_scanout[22]; | |
322 | assign i_wr_data_ff1_scanin[24]=i_wr_data_ff1_scanout[23]; | |
323 | assign i_wr_data_ff1_scanin[25]=i_wr_data_ff1_scanout[24]; | |
324 | assign i_wr_data_ff1_scanin[26]=i_wr_data_ff1_scanout[25]; | |
325 | assign i_wr_data_ff1_scanin[27]=i_wr_data_ff1_scanout[26]; | |
326 | assign i_wr_data_ff1_scanin[28]=i_wr_data_ff1_scanout[27]; | |
327 | assign i_wr_data_ff1_scanin[29]=i_wr_data_ff1_scanout[28]; | |
328 | assign i_wr_data_ff1_scanin[30]=i_wr_data_ff1_scanout[29]; | |
329 | assign i_wr_data_ff1_scanin[31]=i_wr_data_ff1_scanout[30]; | |
330 | assign scan_out=i_wr_data_ff1_scanout[31]; | |
331 | // fixscan end | |
332 | endmodule | |
333 | ||
334 | ||
335 | ||
336 | ||
337 | ||
338 | ||
339 | // any PARAMS parms go into naming of macro | |
340 | ||
341 | module n2_arf_dp_16x128_cust_l1clkhdr_ctl_macro ( | |
342 | l2clk, | |
343 | l1en, | |
344 | pce_ov, | |
345 | stop, | |
346 | se, | |
347 | l1clk); | |
348 | ||
349 | ||
350 | input l2clk; | |
351 | input l1en; | |
352 | input pce_ov; | |
353 | input stop; | |
354 | input se; | |
355 | output l1clk; | |
356 | ||
357 | ||
358 | ||
359 | ||
360 | ||
361 | cl_sc1_l1hdr_8x c_0 ( | |
362 | ||
363 | ||
364 | .l2clk(l2clk), | |
365 | .pce(l1en), | |
366 | .l1clk(l1clk), | |
367 | .se(se), | |
368 | .pce_ov(pce_ov), | |
369 | .stop(stop) | |
370 | ); | |
371 | ||
372 | ||
373 | ||
374 | endmodule | |
375 | ||
376 | ||
377 | ||
378 | ||
379 | ||
380 | ||
381 | ||
382 | ||
383 | ||
384 | ||
385 | ||
386 | ||
387 | ||
388 | // any PARAMS parms go into naming of macro | |
389 | ||
390 | module n2_arf_dp_16x128_cust_msff_ctl_macro__fs_1__scanreverse_1__width_32 ( | |
391 | din, | |
392 | l1clk, | |
393 | scan_in, | |
394 | siclk, | |
395 | soclk, | |
396 | dout, | |
397 | scan_out); | |
398 | wire [31:0] fdin; | |
399 | ||
400 | input [31:0] din; | |
401 | input l1clk; | |
402 | input [31:0] scan_in; | |
403 | ||
404 | ||
405 | input siclk; | |
406 | input soclk; | |
407 | ||
408 | output [31:0] dout; | |
409 | output [31:0] scan_out; | |
410 | assign fdin[31:0] = din[31:0]; | |
411 | ||
412 | ||
413 | ||
414 | ||
415 | ||
416 | ||
417 | dff #(32) d0_0 ( | |
418 | .l1clk(l1clk), | |
419 | .siclk(siclk), | |
420 | .soclk(soclk), | |
421 | .d(fdin[31:0]), | |
422 | .si(scan_in[31:0]), | |
423 | .so(scan_out[31:0]), | |
424 | .q(dout[31:0]) | |
425 | ); | |
426 | ||
427 | ||
428 | ||
429 | ||
430 | ||
431 | ||
432 | ||
433 | ||
434 | ||
435 | ||
436 | ||
437 | ||
438 | endmodule | |
439 | ||
440 | ||
441 | ||
442 | ||
443 | ||
444 | ||
445 | ||
446 | ||
447 | ||
448 | ||
449 | ||
450 | ||
451 | ||
452 | // any PARAMS parms go into naming of macro | |
453 | ||
454 | module n2_arf_dp_16x128_cust_msff_ctl_macro__fs_1__scanreverse_1__width_4 ( | |
455 | din, | |
456 | l1clk, | |
457 | scan_in, | |
458 | siclk, | |
459 | soclk, | |
460 | dout, | |
461 | scan_out); | |
462 | wire [3:0] fdin; | |
463 | ||
464 | input [3:0] din; | |
465 | input l1clk; | |
466 | input [3:0] scan_in; | |
467 | ||
468 | ||
469 | input siclk; | |
470 | input soclk; | |
471 | ||
472 | output [3:0] dout; | |
473 | output [3:0] scan_out; | |
474 | assign fdin[3:0] = din[3:0]; | |
475 | ||
476 | ||
477 | ||
478 | ||
479 | ||
480 | ||
481 | dff #(4) d0_0 ( | |
482 | .l1clk(l1clk), | |
483 | .siclk(siclk), | |
484 | .soclk(soclk), | |
485 | .d(fdin[3:0]), | |
486 | .si(scan_in[3:0]), | |
487 | .so(scan_out[3:0]), | |
488 | .q(dout[3:0]) | |
489 | ); | |
490 | ||
491 | ||
492 | ||
493 | ||
494 | ||
495 | ||
496 | ||
497 | ||
498 | ||
499 | ||
500 | ||
501 | ||
502 | endmodule | |
503 | ||
504 | ||
505 | ||
506 | ||
507 | ||
508 | ||
509 | ||
510 | ||
511 | ||
512 | ||
513 | ||
514 | ||
515 | ||
516 | // any PARAMS parms go into naming of macro | |
517 | ||
518 | module n2_arf_dp_16x128_cust_msff_ctl_macro__fs_1__scanreverse_1__width_2 ( | |
519 | din, | |
520 | l1clk, | |
521 | scan_in, | |
522 | siclk, | |
523 | soclk, | |
524 | dout, | |
525 | scan_out); | |
526 | wire [1:0] fdin; | |
527 | ||
528 | input [1:0] din; | |
529 | input l1clk; | |
530 | input [1:0] scan_in; | |
531 | ||
532 | ||
533 | input siclk; | |
534 | input soclk; | |
535 | ||
536 | output [1:0] dout; | |
537 | output [1:0] scan_out; | |
538 | assign fdin[1:0] = din[1:0]; | |
539 | ||
540 | ||
541 | ||
542 | ||
543 | ||
544 | ||
545 | dff #(2) d0_0 ( | |
546 | .l1clk(l1clk), | |
547 | .siclk(siclk), | |
548 | .soclk(soclk), | |
549 | .d(fdin[1:0]), | |
550 | .si(scan_in[1:0]), | |
551 | .so(scan_out[1:0]), | |
552 | .q(dout[1:0]) | |
553 | ); | |
554 | ||
555 | ||
556 | ||
557 | ||
558 | ||
559 | ||
560 | ||
561 | ||
562 | ||
563 | ||
564 | ||
565 | ||
566 | endmodule | |
567 | ||
568 | ||
569 | ||
570 | ||
571 | ||
572 | ||
573 | ||
574 | ||
575 | ||
576 | // | |
577 | // macro for cl_mc1_sram_msff_mo_{16,8,4}x flops | |
578 | // | |
579 | // | |
580 | ||
581 | ||
582 | ||
583 | ||
584 | ||
585 | module n2_arf_dp_16x128_cust_sram_msff_mo_macro__fs_1__scanreverse_1__width_5 ( | |
586 | d, | |
587 | scan_in, | |
588 | l1clk, | |
589 | and_clk, | |
590 | siclk, | |
591 | soclk, | |
592 | mq, | |
593 | mq_l, | |
594 | scan_out, | |
595 | q, | |
596 | q_l); | |
597 | input [4:0] d; | |
598 | input [4:0] scan_in; | |
599 | input l1clk; | |
600 | input and_clk; | |
601 | input siclk; | |
602 | input soclk; | |
603 | output [4:0] mq; | |
604 | output [4:0] mq_l; | |
605 | output [4:0] scan_out; | |
606 | output [4:0] q; | |
607 | output [4:0] q_l; | |
608 | ||
609 | ||
610 | ||
611 | ||
612 | ||
613 | ||
614 | new_dlata #(5) d0_0 ( | |
615 | .d(d[4:0]), | |
616 | .si(scan_in[4:0]), | |
617 | .so(scan_out[4:0]), | |
618 | .l1clk(l1clk), | |
619 | .and_clk(and_clk), | |
620 | .siclk(siclk), | |
621 | .soclk(soclk), | |
622 | .q(q[4:0]), | |
623 | .q_l(q_l[4:0]), | |
624 | .mq(mq[4:0]), | |
625 | .mq_l(mq_l[4:0]) | |
626 | ); | |
627 | ||
628 | ||
629 | ||
630 | ||
631 | ||
632 | ||
633 | ||
634 | ||
635 | ||
636 | ||
637 | //place::generic_place($width,$stack,$left); | |
638 | ||
639 | endmodule | |
640 | ||
641 | ||
642 | ||
643 | ||
644 | ||
645 | //////////////////////////////////////////////////////////////////////////////// | |
646 | // $Id: lib_16x64b_1r1w_array.sv,v 1.5 2005/06/27 15:27:09 co132877 Exp $ | |
647 | // | |
648 | // Copyright (C) 2003 by Sun Microsystems, Inc. | |
649 | // | |
650 | // All rights reserved. No part of this design may be reproduced, | |
651 | // stored in a retrieval system, or transmitted, in any form or by | |
652 | // any means, electronic, mechanical, photocopying, recording, or | |
653 | // otherwise, without prior written permission of Sun Microsystems, | |
654 | // Inc. | |
655 | // | |
656 | // Sun Proprietary/Confidential | |
657 | // | |
658 | // Description: 16 x 64 dual port array | |
659 | // read produces X's on read/write collision | |
660 | // | |
661 | // To produce a debussy dump of memory contents, | |
662 | // add -vcs_run_args=+DUMPMEM_16x64 to sims command line | |
663 | // | |
664 | // Primary Contact: Chris Olson | |
665 | //////////////////////////////////////////////////////////////////////////////// | |
666 | ||
667 | module lib_16x64b_1r1w_array ( | |
668 | clk, | |
669 | tcu_array_wr_inhibit, | |
670 | rd_addr, | |
671 | rd_en, | |
672 | wr_en, | |
673 | wr_addr, | |
674 | din, | |
675 | dout); | |
676 | wire rd_enable; | |
677 | wire wr_enable; | |
678 | wire rd_eq_wr; | |
679 | ||
680 | ||
681 | input clk; | |
682 | input tcu_array_wr_inhibit; | |
683 | input [3:0] rd_addr; | |
684 | input rd_en; | |
685 | input wr_en; | |
686 | input [3:0] wr_addr; | |
687 | ||
688 | input [63:0] din; | |
689 | output [63:0] dout; | |
690 | ||
691 | ||
692 | reg [63:0] mem[15:0]; | |
693 | reg [63:0] local_dout; | |
694 | ||
695 | `ifndef NOINITMEM | |
696 | integer i; | |
697 | initial begin | |
698 | for (i=0; i<16; i=i+1) begin | |
699 | mem[i] = {64{1'b0}}; | |
700 | end | |
701 | local_dout = {64{1'b0}}; | |
702 | end | |
703 | `endif | |
704 | ||
705 | ||
706 | assign rd_enable = rd_en & ~tcu_array_wr_inhibit; | |
707 | assign wr_enable = wr_en & ~tcu_array_wr_inhibit; | |
708 | assign rd_eq_wr = wr_en & (rd_addr[3:0] == wr_addr[3:0]); | |
709 | ||
710 | ////////////////////// | |
711 | // Read/write array | |
712 | ////////////////////// | |
713 | ||
714 | always @ (clk or rd_enable or rd_addr or rd_eq_wr) begin | |
715 | if (clk) begin | |
716 | ||
717 | if (rd_enable) | |
718 | begin | |
719 | if(rd_eq_wr) local_dout[63:0] <= {64{1'bx}}; // Read = Write conflict | |
720 | else local_dout[63:0] <= mem[rd_addr]; // Normal Read | |
721 | end | |
722 | else local_dout[63:0] <= {64{1'b0}}; // Precharge | |
723 | ||
724 | end // CLK | |
725 | end // ALWAYS | |
726 | ||
727 | ||
728 | ||
729 | always @ (negedge clk) begin | |
730 | ||
731 | if (wr_enable) begin | |
732 | mem[wr_addr] <= din; | |
733 | ||
734 | ||
735 | ||
736 | end | |
737 | ||
738 | end // NEGEDGE ALWAYS | |
739 | ||
740 | ||
741 | assign dout[63:0] = local_dout[63:0]; | |
742 | ||
743 | supply0 vss; | |
744 | supply1 vdd; | |
745 | endmodule | |
746 |