Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: n2_ict_sp_1920b_cust.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module n2_ict_sp_1920b_cust ( | |
36 | l2clk, | |
37 | scan_in, | |
38 | tcu_pce_ov, | |
39 | tcu_scan_en, | |
40 | tcu_aclk, | |
41 | tcu_bclk, | |
42 | tcu_se_scancollar_in, | |
43 | tcu_array_wr_inhibit, | |
44 | agd_ic_index_bf, | |
45 | agc_fill_wrway_bf, | |
46 | ftp_tg_rd_req_bf, | |
47 | ftp_tg_wr_req_bf, | |
48 | ftp_tg_clk_en, | |
49 | agd_ict_wrtag_bf, | |
50 | ict_itlb_way_0_tag_f, | |
51 | ict_itlb_way_1_tag_f, | |
52 | ict_itlb_way_2_tag_f, | |
53 | ict_itlb_way_3_tag_f, | |
54 | ict_itlb_way_4_tag_f, | |
55 | ict_itlb_way_5_tag_f, | |
56 | ict_itlb_way_6_tag_f, | |
57 | ict_itlb_way_7_tag_f, | |
58 | scan_out) ; | |
59 | wire l1clk_din; | |
60 | wire l1clk_in; | |
61 | wire l1clk_array; | |
62 | wire pce_ov; | |
63 | wire stop; | |
64 | wire siclk; | |
65 | wire soclk; | |
66 | wire wr_inhibit; | |
67 | wire [2:0] wrway_b; | |
68 | wire [7:0] wrway_dec_b; | |
69 | wire wr_inhibit_; | |
70 | wire wrreq_b; | |
71 | wire [7:0] wr_en_way_b; | |
72 | wire [7:0] wr_en_way_f; | |
73 | wire [7:0] wr_en_unused; | |
74 | wire wrway_reg_scanin; | |
75 | wire wrway_reg_scanout; | |
76 | wire [2:0] wrway_b_unused; | |
77 | wire index_reg_i_5_scanin; | |
78 | wire index_reg_i_5_scanout; | |
79 | wire [10:5] index_f; | |
80 | wire [10:5] index_f_l_unused; | |
81 | wire index_reg_i_6_scanin; | |
82 | wire index_reg_i_6_scanout; | |
83 | wire index_reg_i_7_scanin; | |
84 | wire index_reg_i_7_scanout; | |
85 | wire index_reg_i_8_scanin; | |
86 | wire index_reg_i_8_scanout; | |
87 | wire index_reg_i_9_scanin; | |
88 | wire index_reg_i_9_scanout; | |
89 | wire index_reg_i_10_scanin; | |
90 | wire index_reg_i_10_scanout; | |
91 | wire rdreq_reg_scanin; | |
92 | wire rdreq_reg_scanout; | |
93 | wire rdreq_a; | |
94 | wire rdreq_f; | |
95 | wire rdreq_f_unused; | |
96 | wire wrreq_reg_scanin; | |
97 | wire wrreq_reg_scanout; | |
98 | wire wrreq_a; | |
99 | wire rdreq_reg_dup_scanin; | |
100 | wire rdreq_reg_dup_scanout; | |
101 | wire rdreq_b; | |
102 | wire rdreq_f_l_dup_unused; | |
103 | wire wrreq_reg_dup_scanin; | |
104 | wire wrreq_reg_dup_scanout; | |
105 | wire wrreq_b_; | |
106 | wire rd_en_b; | |
107 | wire [29:0] wrtag_reg_in; | |
108 | wire wrtag_reg_scanin; | |
109 | wire wrtag_reg_scanout; | |
110 | wire [29:0] wrtag_reg_out; | |
111 | wire [29:0] ic_wrtag_f_l; | |
112 | wire [29:0] ic_wrtag_f; | |
113 | ||
114 | ||
115 | input l2clk; | |
116 | input scan_in; | |
117 | input tcu_pce_ov; | |
118 | input tcu_scan_en; | |
119 | input tcu_aclk; | |
120 | input tcu_bclk; | |
121 | input tcu_se_scancollar_in; | |
122 | input tcu_array_wr_inhibit; | |
123 | ||
124 | input [10:5] agd_ic_index_bf; | |
125 | input [2:0] agc_fill_wrway_bf; // way to write to, this is | |
126 | // sent by the l2c over the cpx | |
127 | input ftp_tg_rd_req_bf; | |
128 | input ftp_tg_wr_req_bf; | |
129 | input ftp_tg_clk_en; | |
130 | ||
131 | ||
132 | ||
133 | input [29:0] agd_ict_wrtag_bf; // tag + 1b parity | |
134 | ||
135 | output [29:0] ict_itlb_way_0_tag_f; // Tag compare is done in TLB block | |
136 | output [29:0] ict_itlb_way_1_tag_f; // Tag compare is done in TLB block | |
137 | output [29:0] ict_itlb_way_2_tag_f; // Tag compare is done in TLB block | |
138 | output [29:0] ict_itlb_way_3_tag_f; // Tag compare is done in TLB block | |
139 | output [29:0] ict_itlb_way_4_tag_f; // Tag compare is done in TLB block | |
140 | output [29:0] ict_itlb_way_5_tag_f; // Tag compare is done in TLB block | |
141 | output [29:0] ict_itlb_way_6_tag_f; // Tag compare is done in TLB block | |
142 | output [29:0] ict_itlb_way_7_tag_f; // Tag compare is done in TLB block | |
143 | output scan_out; | |
144 | ||
145 | `ifndef FPGA | |
146 | // synopsys translate_off | |
147 | `endif | |
148 | ||
149 | //================================================ | |
150 | // Clock headers | |
151 | //================================================ | |
152 | // This clock gates the wrtag input flops. | |
153 | n2_ict_sp_1920b_cust_l1clkhdr_ctl_macro l1ch_din ( | |
154 | .l2clk (l2clk), | |
155 | .l1en (ftp_tg_clk_en), | |
156 | .se (tcu_se_scancollar_in), | |
157 | .l1clk (l1clk_din), | |
158 | .pce_ov(pce_ov), | |
159 | .stop(stop) | |
160 | ); | |
161 | ||
162 | ||
163 | ||
164 | n2_ict_sp_1920b_cust_l1clkhdr_ctl_macro l1ch_in ( | |
165 | .l2clk (l2clk), | |
166 | .l1en (1'b1), | |
167 | .se (tcu_se_scancollar_in), | |
168 | .l1clk (l1clk_in), | |
169 | .pce_ov(pce_ov), | |
170 | .stop(stop) | |
171 | ); | |
172 | ||
173 | // This clock gates the array and internal logic. | |
174 | n2_ict_sp_1920b_cust_l1clkhdr_ctl_macro l1ch_free ( | |
175 | .l2clk (l2clk), | |
176 | .l1en (ftp_tg_clk_en), | |
177 | .se (tcu_scan_en), | |
178 | .l1clk (l1clk_array), | |
179 | .pce_ov(pce_ov), | |
180 | .stop(stop) | |
181 | ); | |
182 | ||
183 | ||
184 | ||
185 | ||
186 | ||
187 | assign pce_ov = tcu_pce_ov; | |
188 | assign stop = 1'b0; | |
189 | assign siclk = tcu_aclk ; | |
190 | assign soclk = tcu_bclk; | |
191 | assign wr_inhibit = tcu_array_wr_inhibit; | |
192 | ||
193 | ||
194 | /////////////////////// | |
195 | // Code starts here | |
196 | /////////////////////// | |
197 | // assign wr_en_way_0_f = wrreq_f & (wrway_f[2:0] == 3'b000) ; | |
198 | // assign wr_en_way_1_f = wrreq_f & (wrway_f[2:0] == 3'b001) ; | |
199 | // assign wr_en_way_2_f = wrreq_f & (wrway_f[2:0] == 3'b010) ; | |
200 | // assign wr_en_way_3_f = wrreq_f & (wrway_f[2:0] == 3'b011) ; | |
201 | // assign wr_en_way_4_f = wrreq_f & (wrway_f[2:0] == 3'b100) ; | |
202 | // assign wr_en_way_5_f = wrreq_f & (wrway_f[2:0] == 3'b101) ; | |
203 | // assign wr_en_way_6_f = wrreq_f & (wrway_f[2:0] == 3'b110) ; | |
204 | // assign wr_en_way_7_f = wrreq_f & (wrway_f[2:0] == 3'b111) ; | |
205 | ||
206 | ////////////////////////////////////////////////////////// | |
207 | // 4:8 decode // | |
208 | ////////////////////////////////////////////////////////// | |
209 | n2_ict_sp_1920b_cust_mux_macro__mux_aodec__ports_8__width_8 wr_way_decode ( | |
210 | .din0 (8'b00000001), | |
211 | .din1 (8'b00000010), | |
212 | .din2 (8'b00000100), | |
213 | .din3 (8'b00001000), | |
214 | .din4 (8'b00010000), | |
215 | .din5 (8'b00100000), | |
216 | .din6 (8'b01000000), | |
217 | .din7 (8'b10000000), | |
218 | .sel (wrway_b[2:0]), | |
219 | .dout (wrway_dec_b[7:0]) | |
220 | ); | |
221 | ||
222 | n2_ict_sp_1920b_cust_inv_macro__width_1 wr_inhibit_gate ( | |
223 | .din(wr_inhibit), | |
224 | .dout(wr_inhibit_) | |
225 | ); | |
226 | ||
227 | n2_ict_sp_1920b_cust_and_macro__ports_3__width_8 wr_en_gate ( | |
228 | .din0(wrway_dec_b[7:0]), | |
229 | .din1({8{wrreq_b}}), | |
230 | .din2({8{wr_inhibit_}}), | |
231 | .dout(wr_en_way_b[7:0]) | |
232 | ); | |
233 | ||
234 | ||
235 | assign wr_en_way_f[7:0] = wr_en_way_b[7:0] ; | |
236 | assign wr_en_unused[7:0] = wr_en_way_f[7:0] ; | |
237 | ||
238 | /////////////////////////////////////////////////////////////// | |
239 | // Scan chain connections // | |
240 | /////////////////////////////////////////////////////////////// | |
241 | /////////////////////////////////////////////////////////////// | |
242 | // Flop the inputs // | |
243 | /////////////////////////////////////////////////////////////// | |
244 | n2_ict_sp_1920b_cust_tisram_msff_macro__width_3 wrway_reg ( | |
245 | .scan_in(wrway_reg_scanin), | |
246 | .scan_out(wrway_reg_scanout), | |
247 | .l1clk ( l1clk_in ), | |
248 | .d ( agc_fill_wrway_bf[2:0] ), | |
249 | .latout( wrway_b[2:0] ), | |
250 | .latout_l( wrway_b_unused[2:0] ), | |
251 | .siclk(siclk), | |
252 | .soclk(soclk)); | |
253 | ||
254 | n2_ict_sp_1920b_cust_tisram_msff_macro__width_1 index_reg_i_5 ( | |
255 | .scan_in(index_reg_i_5_scanin), | |
256 | .scan_out(index_reg_i_5_scanout), | |
257 | .l1clk ( l1clk_in ), | |
258 | .d ( agd_ic_index_bf[5] ), | |
259 | .latout( index_f[5] ), | |
260 | .latout_l( index_f_l_unused[5] ), | |
261 | .siclk(siclk), | |
262 | .soclk(soclk)); | |
263 | ||
264 | ||
265 | n2_ict_sp_1920b_cust_tisram_msff_macro__width_1 index_reg_i_6 ( | |
266 | .scan_in(index_reg_i_6_scanin), | |
267 | .scan_out(index_reg_i_6_scanout), | |
268 | .l1clk ( l1clk_in ), | |
269 | .d ( agd_ic_index_bf[6] ), | |
270 | .latout( index_f[6] ), | |
271 | .latout_l( index_f_l_unused[6] ), | |
272 | .siclk(siclk), | |
273 | .soclk(soclk)); | |
274 | ||
275 | ||
276 | n2_ict_sp_1920b_cust_tisram_msff_macro__width_1 index_reg_i_7 ( | |
277 | .scan_in(index_reg_i_7_scanin), | |
278 | .scan_out(index_reg_i_7_scanout), | |
279 | .l1clk ( l1clk_in ), | |
280 | .d ( agd_ic_index_bf[7] ), | |
281 | .latout( index_f[7] ), | |
282 | .latout_l( index_f_l_unused[7] ), | |
283 | .siclk(siclk), | |
284 | .soclk(soclk)); | |
285 | ||
286 | ||
287 | n2_ict_sp_1920b_cust_tisram_msff_macro__width_1 index_reg_i_8 ( | |
288 | .scan_in(index_reg_i_8_scanin), | |
289 | .scan_out(index_reg_i_8_scanout), | |
290 | .l1clk ( l1clk_in ), | |
291 | .d ( agd_ic_index_bf[8] ), | |
292 | .latout( index_f[8] ), | |
293 | .latout_l( index_f_l_unused[8] ), | |
294 | .siclk(siclk), | |
295 | .soclk(soclk)); | |
296 | ||
297 | ||
298 | n2_ict_sp_1920b_cust_tisram_msff_macro__width_1 index_reg_i_9 ( | |
299 | .scan_in(index_reg_i_9_scanin), | |
300 | .scan_out(index_reg_i_9_scanout), | |
301 | .l1clk ( l1clk_in ), | |
302 | .d ( agd_ic_index_bf[9] ), | |
303 | .latout( index_f[9] ), | |
304 | .latout_l( index_f_l_unused[9] ), | |
305 | .siclk(siclk), | |
306 | .soclk(soclk)); | |
307 | ||
308 | ||
309 | n2_ict_sp_1920b_cust_tisram_msff_macro__width_1 index_reg_i_10 ( | |
310 | .scan_in(index_reg_i_10_scanin), | |
311 | .scan_out(index_reg_i_10_scanout), | |
312 | .l1clk ( l1clk_in ), | |
313 | .d ( agd_ic_index_bf[10] ), | |
314 | .latout( index_f[10] ), | |
315 | .latout_l( index_f_l_unused[10] ), | |
316 | .siclk(siclk), | |
317 | .soclk(soclk)); | |
318 | ||
319 | ||
320 | ||
321 | n2_ict_sp_1920b_cust_msff_ctl_macro__width_1 rdreq_reg ( | |
322 | .scan_in(rdreq_reg_scanin), | |
323 | .scan_out(rdreq_reg_scanout), | |
324 | .l1clk ( l1clk_in ), | |
325 | .din ( ftp_tg_rd_req_bf ), | |
326 | .dout( rdreq_a ), | |
327 | .siclk(siclk), | |
328 | .soclk(soclk)) ; | |
329 | ||
330 | assign rdreq_f = rdreq_a ; | |
331 | assign rdreq_f_unused = rdreq_f ; | |
332 | ||
333 | n2_ict_sp_1920b_cust_msff_ctl_macro__width_1 wrreq_reg ( | |
334 | .scan_in(wrreq_reg_scanin), | |
335 | .scan_out(wrreq_reg_scanout), | |
336 | .l1clk ( l1clk_in ), | |
337 | .din ( ftp_tg_wr_req_bf ), | |
338 | .dout( wrreq_a ), | |
339 | .siclk(siclk), | |
340 | .soclk(soclk)) ; | |
341 | ||
342 | n2_ict_sp_1920b_cust_tisram_msff_macro__width_1 rdreq_reg_dup ( | |
343 | .scan_in(rdreq_reg_dup_scanin), | |
344 | .scan_out(rdreq_reg_dup_scanout), | |
345 | .l1clk ( l1clk_in ), | |
346 | .d ( ftp_tg_rd_req_bf ), | |
347 | .latout( rdreq_b ), | |
348 | .latout_l( rdreq_f_l_dup_unused ), | |
349 | .siclk(siclk), | |
350 | .soclk(soclk)); | |
351 | ||
352 | ||
353 | n2_ict_sp_1920b_cust_tisram_msff_macro__width_1 wrreq_reg_dup ( | |
354 | .scan_in(wrreq_reg_dup_scanin), | |
355 | .scan_out(wrreq_reg_dup_scanout), | |
356 | .l1clk ( l1clk_in ), | |
357 | .d ( ftp_tg_wr_req_bf ), | |
358 | .latout( wrreq_b ), | |
359 | .latout_l( wrreq_b_ ), | |
360 | .siclk(siclk), | |
361 | .soclk(soclk)); | |
362 | ||
363 | ||
364 | n2_ict_sp_1920b_cust_and_macro__ports_3__width_1 read_and ( | |
365 | .din0 (rdreq_b), | |
366 | .din1 (wrreq_b_), | |
367 | .din2 (wr_inhibit_), | |
368 | .dout (rd_en_b) | |
369 | ); | |
370 | ||
371 | ||
372 | // write data regsiter | |
373 | ||
374 | assign wrtag_reg_in[29:0] = {agd_ict_wrtag_bf[0], | |
375 | agd_ict_wrtag_bf[1], | |
376 | agd_ict_wrtag_bf[2], | |
377 | agd_ict_wrtag_bf[3], | |
378 | agd_ict_wrtag_bf[4], | |
379 | agd_ict_wrtag_bf[5], | |
380 | agd_ict_wrtag_bf[6], | |
381 | agd_ict_wrtag_bf[7], | |
382 | agd_ict_wrtag_bf[8], | |
383 | agd_ict_wrtag_bf[9], | |
384 | agd_ict_wrtag_bf[10], | |
385 | agd_ict_wrtag_bf[11], | |
386 | agd_ict_wrtag_bf[12], | |
387 | agd_ict_wrtag_bf[13], | |
388 | agd_ict_wrtag_bf[14], | |
389 | agd_ict_wrtag_bf[15], | |
390 | agd_ict_wrtag_bf[16], | |
391 | agd_ict_wrtag_bf[17], | |
392 | agd_ict_wrtag_bf[18], | |
393 | agd_ict_wrtag_bf[19], | |
394 | agd_ict_wrtag_bf[20], | |
395 | agd_ict_wrtag_bf[21], | |
396 | agd_ict_wrtag_bf[22], | |
397 | agd_ict_wrtag_bf[23], | |
398 | agd_ict_wrtag_bf[24], | |
399 | agd_ict_wrtag_bf[25], | |
400 | agd_ict_wrtag_bf[26], | |
401 | agd_ict_wrtag_bf[27], | |
402 | agd_ict_wrtag_bf[28], | |
403 | agd_ict_wrtag_bf[29]} ; | |
404 | ||
405 | n2_ict_sp_1920b_cust_msffi_ctl_macro__width_30 wrtag_reg ( | |
406 | .scan_in(wrtag_reg_scanin), | |
407 | .scan_out(wrtag_reg_scanout), | |
408 | .l1clk(l1clk_din), | |
409 | .din(wrtag_reg_in[29:0]), | |
410 | .q_l (wrtag_reg_out[29:0] ), | |
411 | .siclk(siclk), | |
412 | .soclk(soclk)); | |
413 | ||
414 | assign ic_wrtag_f_l[29:0] = {wrtag_reg_out[0], | |
415 | wrtag_reg_out[1], | |
416 | wrtag_reg_out[2], | |
417 | wrtag_reg_out[3], | |
418 | wrtag_reg_out[4], | |
419 | wrtag_reg_out[5], | |
420 | wrtag_reg_out[6], | |
421 | wrtag_reg_out[7], | |
422 | wrtag_reg_out[8], | |
423 | wrtag_reg_out[9], | |
424 | wrtag_reg_out[10], | |
425 | wrtag_reg_out[11], | |
426 | wrtag_reg_out[12], | |
427 | wrtag_reg_out[13], | |
428 | wrtag_reg_out[14], | |
429 | wrtag_reg_out[15], | |
430 | wrtag_reg_out[16], | |
431 | wrtag_reg_out[17], | |
432 | wrtag_reg_out[18], | |
433 | wrtag_reg_out[19], | |
434 | wrtag_reg_out[20], | |
435 | wrtag_reg_out[21], | |
436 | wrtag_reg_out[22], | |
437 | wrtag_reg_out[23], | |
438 | wrtag_reg_out[24], | |
439 | wrtag_reg_out[25], | |
440 | wrtag_reg_out[26], | |
441 | wrtag_reg_out[27], | |
442 | wrtag_reg_out[28], | |
443 | wrtag_reg_out[29]} ; | |
444 | ||
445 | n2_ict_sp_1920b_cust_inv_macro__width_30 data_inv ( | |
446 | .din(ic_wrtag_f_l[29:0]), | |
447 | .dout(ic_wrtag_f[29:0]) ) ; | |
448 | ||
449 | ///////////////////////////////////////////////////////////////// | |
450 | // Instantiate each TAG way ARRAY. // | |
451 | ///////////////////////////////////////////////////////////////// | |
452 | // WAY 0 /////// | |
453 | ////////////////////////////// | |
454 | n2_ict_sp_1920b_array tag_way_0 (.addr(index_f[10:5]), // comes on negedge | |
455 | .rd_en_b(rd_en_b), // comes on negedge | |
456 | .wr_en_w_b(wr_en_way_b[0]), // comes on negedge | |
457 | .rd_en_a(rdreq_a), // comes on posedge | |
458 | .wrreq_a(wrreq_a), // comes on posedge | |
459 | .din(ic_wrtag_f[29:0]), | |
460 | .dout(ict_itlb_way_0_tag_f[29:0]), | |
461 | .clk(l1clk_array), | |
462 | .wr_inhibit(wr_inhibit) | |
463 | ); | |
464 | ||
465 | ||
466 | ////////////////////////////// | |
467 | // WAY 1 /////// | |
468 | ////////////////////////////// | |
469 | n2_ict_sp_1920b_array tag_way_1 (.addr(index_f[10:5]), | |
470 | .rd_en_b(rd_en_b), // comes on negedge | |
471 | .wr_en_w_b(wr_en_way_b[1]), // comes on negedge | |
472 | .rd_en_a(rdreq_a), // comes on posedge | |
473 | .wrreq_a(wrreq_a), // comes on posedge | |
474 | .wr_inhibit(wr_inhibit), | |
475 | .din(ic_wrtag_f[29:0]), | |
476 | .dout(ict_itlb_way_1_tag_f[29:0]), | |
477 | .clk(l1clk_array) | |
478 | ); | |
479 | ////////////////////////////// | |
480 | // WAY 2 /////// | |
481 | ////////////////////////////// | |
482 | n2_ict_sp_1920b_array tag_way_2 (.addr(index_f[10:5]), | |
483 | .rd_en_b(rd_en_b), // comes on negedge | |
484 | .wr_en_w_b(wr_en_way_b[2]), // comes on negedge | |
485 | .rd_en_a(rdreq_a), // comes on posedge | |
486 | .wrreq_a(wrreq_a), // comes on posedge | |
487 | .wr_inhibit(wr_inhibit), | |
488 | .din(ic_wrtag_f[29:0]), | |
489 | .dout(ict_itlb_way_2_tag_f[29:0]), | |
490 | .clk(l1clk_array) | |
491 | ); | |
492 | ////////////////////////////// | |
493 | // WAY 3 /////// | |
494 | ////////////////////////////// | |
495 | n2_ict_sp_1920b_array tag_way_3 (.addr(index_f[10:5]), | |
496 | .rd_en_b(rd_en_b), // comes on negedge | |
497 | .wr_en_w_b(wr_en_way_b[3]), // comes on negedge | |
498 | .rd_en_a(rdreq_a), // comes on posedge | |
499 | .wrreq_a(wrreq_a), // comes on posedge | |
500 | .wr_inhibit(wr_inhibit), | |
501 | .din(ic_wrtag_f[29:0]), | |
502 | .dout(ict_itlb_way_3_tag_f[29:0]), | |
503 | .clk(l1clk_array) | |
504 | ); | |
505 | ////////////////////////////// | |
506 | // WAY 4 /////// | |
507 | ////////////////////////////// | |
508 | n2_ict_sp_1920b_array tag_way_4 (.addr(index_f[10:5]), | |
509 | .rd_en_b(rd_en_b), // comes on negedge | |
510 | .wr_en_w_b(wr_en_way_b[4]), // comes on negedge | |
511 | .rd_en_a(rdreq_a), // comes on posedge | |
512 | .wrreq_a(wrreq_a), // comes on posedge | |
513 | .wr_inhibit(wr_inhibit), | |
514 | .din(ic_wrtag_f[29:0]), | |
515 | .dout(ict_itlb_way_4_tag_f[29:0]), | |
516 | .clk(l1clk_array) | |
517 | ); | |
518 | ////////////////////////////// | |
519 | // WAY 5 /////// | |
520 | ////////////////////////////// | |
521 | n2_ict_sp_1920b_array tag_way_5 (.addr(index_f[10:5]), | |
522 | .rd_en_b(rd_en_b), // comes on negedge | |
523 | .wr_en_w_b(wr_en_way_b[5]), // comes on negedge | |
524 | .rd_en_a(rdreq_a), // comes on posedge | |
525 | .wrreq_a(wrreq_a), // comes on posedge | |
526 | .wr_inhibit(wr_inhibit), | |
527 | .din(ic_wrtag_f[29:0]), | |
528 | .dout(ict_itlb_way_5_tag_f[29:0]), | |
529 | .clk(l1clk_array) | |
530 | ); | |
531 | ////////////////////////////// | |
532 | // WAY 6 /////// | |
533 | ////////////////////////////// | |
534 | n2_ict_sp_1920b_array tag_way_6 (.addr(index_f[10:5]), | |
535 | .rd_en_b(rd_en_b), // comes on negedge | |
536 | .wr_en_w_b(wr_en_way_b[6]), // comes on negedge | |
537 | .rd_en_a(rdreq_a), // comes on posedge | |
538 | .wrreq_a(wrreq_a), // comes on posedge | |
539 | .wr_inhibit(wr_inhibit), | |
540 | .din(ic_wrtag_f[29:0]), | |
541 | .dout(ict_itlb_way_6_tag_f[29:0]), | |
542 | .clk(l1clk_array) | |
543 | ); | |
544 | ////////////////////////////// | |
545 | // WAY 7 /////// | |
546 | ////////////////////////////// | |
547 | n2_ict_sp_1920b_array tag_way_7 (.addr(index_f[10:5]), | |
548 | .rd_en_b(rd_en_b), // comes on negedge | |
549 | .wr_en_w_b(wr_en_way_b[7]), // comes on negedge | |
550 | .rd_en_a(rdreq_a), // comes on posedge | |
551 | .wrreq_a(wrreq_a), // comes on posedge | |
552 | .wr_inhibit(wr_inhibit), | |
553 | .din(ic_wrtag_f[29:0]), | |
554 | .dout(ict_itlb_way_7_tag_f[29:0]), | |
555 | .clk(l1clk_array) | |
556 | ); | |
557 | supply0 vss; | |
558 | supply1 vdd; | |
559 | ||
560 | // scan_in -> | |
561 | // agc_fill_wrway_bf<2> - 43th | |
562 | // agc_fill_wrway_bf<1> - 42th | |
563 | // agc_fill_wrway_bf<0> - 41th | |
564 | // agd_ic_index_bf<5> - 40th | |
565 | // agd_ic_index_bf<6> - 39th | |
566 | // agd_ic_index_bf<7> - 38th | |
567 | // agd_ic_index_bf<8> - 37th | |
568 | // agd_ic_index_bf<9> - 36th | |
569 | // agd_ic_index_bf<10> - 35th | |
570 | // ftp_tg_rd_req_bf - 34th | |
571 | // ftp_tg_wr_req_bf - 33th | |
572 | // ftp_tg_rd_req_bf - 32th | |
573 | // ftp_tg_wr_req_bf - 31th | |
574 | // agd_ict_wrtag_bf<0> - 30th | |
575 | // agd_ict_wrtag_bf<1> - 29th | |
576 | // ..... .. - .. | |
577 | // agd_ict_wrtag_bf<27> - 3rd | |
578 | // agd_ict_wrtag_bf<28> - 2nd | |
579 | // agd_ict_wrtag_bf<29> - 1st | |
580 | // scan_out | |
581 | ||
582 | ||
583 | ||
584 | ||
585 | ||
586 | // fixscan start: | |
587 | assign wrway_reg_scanin = scan_in ; | |
588 | assign index_reg_i_5_scanin = wrway_reg_scanout ; | |
589 | assign index_reg_i_6_scanin = index_reg_i_5_scanout ; | |
590 | assign index_reg_i_7_scanin = index_reg_i_6_scanout ; | |
591 | assign index_reg_i_8_scanin = index_reg_i_7_scanout ; | |
592 | assign index_reg_i_9_scanin = index_reg_i_8_scanout ; | |
593 | assign index_reg_i_10_scanin = index_reg_i_9_scanout ; | |
594 | assign rdreq_reg_scanin = index_reg_i_10_scanout ; | |
595 | assign wrreq_reg_scanin = rdreq_reg_scanout ; | |
596 | assign rdreq_reg_dup_scanin = wrreq_reg_scanout ; | |
597 | assign wrreq_reg_dup_scanin = rdreq_reg_dup_scanout ; | |
598 | assign wrtag_reg_scanin = wrreq_reg_dup_scanout ; | |
599 | assign scan_out = wrtag_reg_scanout ; | |
600 | // fixscan end: | |
601 | ||
602 | `ifndef FPGA | |
603 | // synopsys translate_on | |
604 | `endif | |
605 | ||
606 | endmodule // sparc_ifu_ict | |
607 | ||
608 | ||
609 | ||
610 | ||
611 | ||
612 | ||
613 | ||
614 | ||
615 | ||
616 | ||
617 | ||
618 | ||
619 | // any PARAMS parms go into naming of macro | |
620 | ||
621 | module n2_ict_sp_1920b_cust_l1clkhdr_ctl_macro ( | |
622 | l2clk, | |
623 | l1en, | |
624 | pce_ov, | |
625 | stop, | |
626 | se, | |
627 | l1clk); | |
628 | ||
629 | ||
630 | input l2clk; | |
631 | input l1en; | |
632 | input pce_ov; | |
633 | input stop; | |
634 | input se; | |
635 | output l1clk; | |
636 | ||
637 | ||
638 | ||
639 | ||
640 | ||
641 | cl_sc1_l1hdr_8x c_0 ( | |
642 | ||
643 | ||
644 | .l2clk(l2clk), | |
645 | .pce(l1en), | |
646 | .l1clk(l1clk), | |
647 | .se(se), | |
648 | .pce_ov(pce_ov), | |
649 | .stop(stop) | |
650 | ); | |
651 | ||
652 | ||
653 | ||
654 | endmodule | |
655 | ||
656 | ||
657 | ||
658 | ||
659 | ||
660 | ||
661 | ||
662 | ||
663 | ||
664 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
665 | // also for pass-gate with decoder | |
666 | ||
667 | ||
668 | ||
669 | ||
670 | ||
671 | // any PARAMS parms go into naming of macro | |
672 | ||
673 | module n2_ict_sp_1920b_cust_mux_macro__mux_aodec__ports_8__width_8 ( | |
674 | din0, | |
675 | din1, | |
676 | din2, | |
677 | din3, | |
678 | din4, | |
679 | din5, | |
680 | din6, | |
681 | din7, | |
682 | sel, | |
683 | dout); | |
684 | wire psel0; | |
685 | wire psel1; | |
686 | wire psel2; | |
687 | wire psel3; | |
688 | wire psel4; | |
689 | wire psel5; | |
690 | wire psel6; | |
691 | wire psel7; | |
692 | ||
693 | input [7:0] din0; | |
694 | input [7:0] din1; | |
695 | input [7:0] din2; | |
696 | input [7:0] din3; | |
697 | input [7:0] din4; | |
698 | input [7:0] din5; | |
699 | input [7:0] din6; | |
700 | input [7:0] din7; | |
701 | input [2:0] sel; | |
702 | output [7:0] dout; | |
703 | ||
704 | ||
705 | ||
706 | ||
707 | ||
708 | cl_dp1_pdec8_8x c0_0 ( | |
709 | .test(1'b1), | |
710 | .sel0(sel[0]), | |
711 | .sel1(sel[1]), | |
712 | .sel2(sel[2]), | |
713 | .psel0(psel0), | |
714 | .psel1(psel1), | |
715 | .psel2(psel2), | |
716 | .psel3(psel3), | |
717 | .psel4(psel4), | |
718 | .psel5(psel5), | |
719 | .psel6(psel6), | |
720 | .psel7(psel7) | |
721 | ); | |
722 | ||
723 | mux8s #(8) d0_0 ( | |
724 | .sel0(psel0), | |
725 | .sel1(psel1), | |
726 | .sel2(psel2), | |
727 | .sel3(psel3), | |
728 | .sel4(psel4), | |
729 | .sel5(psel5), | |
730 | .sel6(psel6), | |
731 | .sel7(psel7), | |
732 | .in0(din0[7:0]), | |
733 | .in1(din1[7:0]), | |
734 | .in2(din2[7:0]), | |
735 | .in3(din3[7:0]), | |
736 | .in4(din4[7:0]), | |
737 | .in5(din5[7:0]), | |
738 | .in6(din6[7:0]), | |
739 | .in7(din7[7:0]), | |
740 | .dout(dout[7:0]) | |
741 | ); | |
742 | ||
743 | ||
744 | ||
745 | ||
746 | ||
747 | ||
748 | ||
749 | ||
750 | ||
751 | ||
752 | ||
753 | ||
754 | ||
755 | endmodule | |
756 | ||
757 | ||
758 | // | |
759 | // invert macro | |
760 | // | |
761 | // | |
762 | ||
763 | ||
764 | ||
765 | ||
766 | ||
767 | module n2_ict_sp_1920b_cust_inv_macro__width_1 ( | |
768 | din, | |
769 | dout); | |
770 | input [0:0] din; | |
771 | output [0:0] dout; | |
772 | ||
773 | ||
774 | ||
775 | ||
776 | ||
777 | ||
778 | inv #(1) d0_0 ( | |
779 | .in(din[0:0]), | |
780 | .out(dout[0:0]) | |
781 | ); | |
782 | ||
783 | ||
784 | ||
785 | ||
786 | ||
787 | ||
788 | ||
789 | ||
790 | ||
791 | endmodule | |
792 | ||
793 | ||
794 | ||
795 | ||
796 | ||
797 | // | |
798 | // and macro for ports = 2,3,4 | |
799 | // | |
800 | // | |
801 | ||
802 | ||
803 | ||
804 | ||
805 | ||
806 | module n2_ict_sp_1920b_cust_and_macro__ports_3__width_8 ( | |
807 | din0, | |
808 | din1, | |
809 | din2, | |
810 | dout); | |
811 | input [7:0] din0; | |
812 | input [7:0] din1; | |
813 | input [7:0] din2; | |
814 | output [7:0] dout; | |
815 | ||
816 | ||
817 | ||
818 | ||
819 | ||
820 | ||
821 | and3 #(8) d0_0 ( | |
822 | .in0(din0[7:0]), | |
823 | .in1(din1[7:0]), | |
824 | .in2(din2[7:0]), | |
825 | .out(dout[7:0]) | |
826 | ); | |
827 | ||
828 | ||
829 | ||
830 | ||
831 | ||
832 | ||
833 | ||
834 | ||
835 | ||
836 | endmodule | |
837 | ||
838 | ||
839 | ||
840 | ||
841 | ||
842 | // | |
843 | // macro for cl_mc1_tisram_msff_{16,8}x flops | |
844 | // | |
845 | // | |
846 | ||
847 | ||
848 | ||
849 | ||
850 | ||
851 | module n2_ict_sp_1920b_cust_tisram_msff_macro__width_3 ( | |
852 | d, | |
853 | scan_in, | |
854 | l1clk, | |
855 | siclk, | |
856 | soclk, | |
857 | scan_out, | |
858 | latout, | |
859 | latout_l); | |
860 | wire [1:0] so; | |
861 | ||
862 | input [2:0] d; | |
863 | input scan_in; | |
864 | input l1clk; | |
865 | input siclk; | |
866 | input soclk; | |
867 | output scan_out; | |
868 | output [2:0] latout; | |
869 | output [2:0] latout_l; | |
870 | ||
871 | ||
872 | ||
873 | ||
874 | ||
875 | ||
876 | tisram_msff #(3) d0_0 ( | |
877 | .d(d[2:0]), | |
878 | .si({scan_in,so[1:0]}), | |
879 | .so({so[1:0],scan_out}), | |
880 | .l1clk(l1clk), | |
881 | .siclk(siclk), | |
882 | .soclk(soclk), | |
883 | .latout(latout[2:0]), | |
884 | .latout_l(latout_l[2:0]) | |
885 | ); | |
886 | ||
887 | ||
888 | ||
889 | ||
890 | ||
891 | ||
892 | ||
893 | ||
894 | ||
895 | ||
896 | ||
897 | ||
898 | //place::generic_place($width,$stack,$left); | |
899 | ||
900 | endmodule | |
901 | ||
902 | ||
903 | ||
904 | ||
905 | ||
906 | // | |
907 | // macro for cl_mc1_tisram_msff_{16,8}x flops | |
908 | // | |
909 | // | |
910 | ||
911 | ||
912 | ||
913 | ||
914 | ||
915 | module n2_ict_sp_1920b_cust_tisram_msff_macro__width_1 ( | |
916 | d, | |
917 | scan_in, | |
918 | l1clk, | |
919 | siclk, | |
920 | soclk, | |
921 | scan_out, | |
922 | latout, | |
923 | latout_l); | |
924 | input [0:0] d; | |
925 | input scan_in; | |
926 | input l1clk; | |
927 | input siclk; | |
928 | input soclk; | |
929 | output scan_out; | |
930 | output [0:0] latout; | |
931 | output [0:0] latout_l; | |
932 | ||
933 | ||
934 | ||
935 | ||
936 | ||
937 | ||
938 | tisram_msff #(1) d0_0 ( | |
939 | .d(d[0:0]), | |
940 | .si(scan_in), | |
941 | .so(scan_out), | |
942 | .l1clk(l1clk), | |
943 | .siclk(siclk), | |
944 | .soclk(soclk), | |
945 | .latout(latout[0:0]), | |
946 | .latout_l(latout_l[0:0]) | |
947 | ); | |
948 | ||
949 | ||
950 | ||
951 | ||
952 | ||
953 | ||
954 | ||
955 | ||
956 | ||
957 | ||
958 | ||
959 | ||
960 | //place::generic_place($width,$stack,$left); | |
961 | ||
962 | endmodule | |
963 | ||
964 | ||
965 | ||
966 | ||
967 | ||
968 | ||
969 | ||
970 | ||
971 | ||
972 | // any PARAMS parms go into naming of macro | |
973 | ||
974 | module n2_ict_sp_1920b_cust_msff_ctl_macro__width_1 ( | |
975 | din, | |
976 | l1clk, | |
977 | scan_in, | |
978 | siclk, | |
979 | soclk, | |
980 | dout, | |
981 | scan_out); | |
982 | wire [0:0] fdin; | |
983 | ||
984 | input [0:0] din; | |
985 | input l1clk; | |
986 | input scan_in; | |
987 | ||
988 | ||
989 | input siclk; | |
990 | input soclk; | |
991 | ||
992 | output [0:0] dout; | |
993 | output scan_out; | |
994 | assign fdin[0:0] = din[0:0]; | |
995 | ||
996 | ||
997 | ||
998 | ||
999 | ||
1000 | ||
1001 | dff #(1) d0_0 ( | |
1002 | .l1clk(l1clk), | |
1003 | .siclk(siclk), | |
1004 | .soclk(soclk), | |
1005 | .d(fdin[0:0]), | |
1006 | .si(scan_in), | |
1007 | .so(scan_out), | |
1008 | .q(dout[0:0]) | |
1009 | ); | |
1010 | ||
1011 | ||
1012 | ||
1013 | ||
1014 | ||
1015 | ||
1016 | ||
1017 | ||
1018 | ||
1019 | ||
1020 | ||
1021 | ||
1022 | endmodule | |
1023 | ||
1024 | ||
1025 | ||
1026 | ||
1027 | ||
1028 | ||
1029 | ||
1030 | ||
1031 | ||
1032 | // | |
1033 | // and macro for ports = 2,3,4 | |
1034 | // | |
1035 | // | |
1036 | ||
1037 | ||
1038 | ||
1039 | ||
1040 | ||
1041 | module n2_ict_sp_1920b_cust_and_macro__ports_3__width_1 ( | |
1042 | din0, | |
1043 | din1, | |
1044 | din2, | |
1045 | dout); | |
1046 | input [0:0] din0; | |
1047 | input [0:0] din1; | |
1048 | input [0:0] din2; | |
1049 | output [0:0] dout; | |
1050 | ||
1051 | ||
1052 | ||
1053 | ||
1054 | ||
1055 | ||
1056 | and3 #(1) d0_0 ( | |
1057 | .in0(din0[0:0]), | |
1058 | .in1(din1[0:0]), | |
1059 | .in2(din2[0:0]), | |
1060 | .out(dout[0:0]) | |
1061 | ); | |
1062 | ||
1063 | ||
1064 | ||
1065 | ||
1066 | ||
1067 | ||
1068 | ||
1069 | ||
1070 | ||
1071 | endmodule | |
1072 | ||
1073 | ||
1074 | ||
1075 | ||
1076 | ||
1077 | ||
1078 | ||
1079 | ||
1080 | ||
1081 | // any PARAMS parms go into naming of macro | |
1082 | ||
1083 | module n2_ict_sp_1920b_cust_msffi_ctl_macro__width_30 ( | |
1084 | din, | |
1085 | l1clk, | |
1086 | scan_in, | |
1087 | siclk, | |
1088 | soclk, | |
1089 | q_l, | |
1090 | scan_out); | |
1091 | wire [28:0] so; | |
1092 | ||
1093 | input [29:0] din; | |
1094 | input l1clk; | |
1095 | input scan_in; | |
1096 | ||
1097 | ||
1098 | input siclk; | |
1099 | input soclk; | |
1100 | ||
1101 | output [29:0] q_l; | |
1102 | output scan_out; | |
1103 | ||
1104 | ||
1105 | ||
1106 | ||
1107 | ||
1108 | ||
1109 | msffi #(30) d0_0 ( | |
1110 | .l1clk(l1clk), | |
1111 | .siclk(siclk), | |
1112 | .soclk(soclk), | |
1113 | .d(din[29:0]), | |
1114 | .si({scan_in,so[28:0]}), | |
1115 | .so({so[28:0],scan_out}), | |
1116 | .q_l(q_l[29:0]) | |
1117 | ); | |
1118 | ||
1119 | ||
1120 | ||
1121 | ||
1122 | ||
1123 | ||
1124 | ||
1125 | ||
1126 | ||
1127 | ||
1128 | ||
1129 | ||
1130 | endmodule | |
1131 | ||
1132 | ||
1133 | ||
1134 | ||
1135 | ||
1136 | ||
1137 | ||
1138 | ||
1139 | ||
1140 | // | |
1141 | // invert macro | |
1142 | // | |
1143 | // | |
1144 | ||
1145 | ||
1146 | ||
1147 | ||
1148 | ||
1149 | module n2_ict_sp_1920b_cust_inv_macro__width_30 ( | |
1150 | din, | |
1151 | dout); | |
1152 | input [29:0] din; | |
1153 | output [29:0] dout; | |
1154 | ||
1155 | ||
1156 | ||
1157 | ||
1158 | ||
1159 | ||
1160 | inv #(30) d0_0 ( | |
1161 | .in(din[29:0]), | |
1162 | .out(dout[29:0]) | |
1163 | ); | |
1164 | ||
1165 | ||
1166 | ||
1167 | ||
1168 | ||
1169 | ||
1170 | ||
1171 | ||
1172 | ||
1173 | endmodule | |
1174 | ||
1175 | ||
1176 | ||
1177 | ||
1178 | ||
1179 | ||
1180 | module n2_ict_sp_1920b_array ( | |
1181 | clk, | |
1182 | rd_en_b, | |
1183 | wr_en_w_b, | |
1184 | rd_en_a, | |
1185 | wrreq_a, | |
1186 | addr, | |
1187 | wr_inhibit, | |
1188 | din, | |
1189 | dout); | |
1190 | wire rd_en_b_unused; | |
1191 | ||
1192 | ||
1193 | `define WIDTH 30 | |
1194 | `define ENTRIES 64 | |
1195 | `define ADDRBITS 6 | |
1196 | ||
1197 | ||
1198 | input clk; | |
1199 | input rd_en_b; // comes on negedge | |
1200 | input wr_en_w_b; // comes on negedge (way specific) | |
1201 | input rd_en_a; // comes on posedge | |
1202 | input wrreq_a; // comes on posedge (not way specific) | |
1203 | input [`ADDRBITS-1:0] addr; // comes on negedge | |
1204 | input wr_inhibit; // async | |
1205 | ||
1206 | input [`WIDTH-1:0] din; // comes on posedge | |
1207 | output [`WIDTH-1:0] dout; | |
1208 | ||
1209 | ||
1210 | ||
1211 | ||
1212 | ||
1213 | ||
1214 | ||
1215 | ||
1216 | reg [`WIDTH-1:0] mem[`ENTRIES-1:0]; | |
1217 | reg [`WIDTH-1:0] local_dout; | |
1218 | ||
1219 | assign rd_en_b_unused = rd_en_b; | |
1220 | ||
1221 | `ifndef NOINITMEM | |
1222 | // Emulate reset | |
1223 | integer i; | |
1224 | initial begin | |
1225 | for (i=0; i<`ENTRIES; i=i+1) begin | |
1226 | mem[i] = {`WIDTH{1'b0}}; | |
1227 | end | |
1228 | local_dout = {`WIDTH{1'b0}}; | |
1229 | end | |
1230 | `endif | |
1231 | ||
1232 | ////////////////////// | |
1233 | // Read/write array | |
1234 | ////////////////////// | |
1235 | ||
1236 | always @(negedge clk) begin | |
1237 | if (wr_en_w_b) begin | |
1238 | mem[addr] <= din; | |
1239 | ||
1240 | ||
1241 | ||
1242 | end | |
1243 | end | |
1244 | ||
1245 | // always @(clk or rd_en_a or wr_en_a or addr) begin | |
1246 | // if (clk) begin | |
1247 | // if (rd_en_a) begin | |
1248 | // if (wr_en_a) | |
1249 | // local_dout[`WIDTH-1:0] = `WIDTH'hx; | |
1250 | // else | |
1251 | // local_dout[`WIDTH-1:0] = mem[addr] ; | |
1252 | // end | |
1253 | // else | |
1254 | // local_dout[`WIDTH-1:0] = `WIDTH'h0; | |
1255 | // end | |
1256 | ||
1257 | always @(posedge clk) begin | |
1258 | if (rd_en_b) | |
1259 | local_dout[`WIDTH-1:0] <= mem[addr]; | |
1260 | else | |
1261 | local_dout[`WIDTH-1:0] <= `WIDTH'h0; | |
1262 | end | |
1263 | ||
1264 | assign dout[`WIDTH-1:0] = local_dout[`WIDTH-1:0] & {`WIDTH{rd_en_a & ~wrreq_a & ~wr_inhibit}}; | |
1265 | ||
1266 | supply0 vss; | |
1267 | supply1 vdd; | |
1268 | ||
1269 | ||
1270 | endmodule | |
1271 |