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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_err_dram_DAC_st_trap.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap | |
39 | ||
40 | ||
41 | #define MAIN_PAGE_NUCLEUS_ALSO | |
42 | #define MAIN_PAGE_HV_ALSO | |
43 | ||
44 | #define DRAM_ERR_INJ_REG 0x8400000290 | |
45 | #define DRAM_ERR_STAT_REG 0x8400000280 | |
46 | #define L2_ERR_STAT_REG 0xAB00000000 | |
47 | #define L2_ERR_ADDR_REG 0xAC00000000 | |
48 | ||
49 | #define TT_SW_Error 0x40 | |
50 | ||
51 | ||
52 | #define ERROR_ADDR 0x20200000 | |
53 | #define TEST_DATA0 0x1000100081c3e008 | |
54 | #define TEST_DATA1 0x2000200081c3e008 | |
55 | #define TEST_DATA2 0x3000300081c3e008 | |
56 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 | |
57 | #define DRAM_ES_W1C_VALUE 0xfe00000000000000 | |
58 | ||
59 | #include "hboot.s" | |
60 | #include "asi_s.h" | |
61 | #include "err_defines.h" | |
62 | ||
63 | ||
64 | .text | |
65 | .global main | |
66 | !.global My_Recoverable_Sw_error_trap | |
67 | .global My_Corrected_ECC_error_trap | |
68 | ||
69 | ||
70 | ||
71 | ||
72 | main: | |
73 | ta T_CHANGE_HPRIV | |
74 | disable_l1: | |
75 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
76 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) | |
77 | andn %l0, 0x3, %l0 | |
78 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
79 | ||
80 | ||
81 | clear_dram_esr_0: | |
82 | ! Clear DRAM Error status register (Bit[63:57] write-1-clear) | |
83 | setx DRAM_ES_W1C_VALUE, %l0, %g4 | |
84 | setx DRAM_ERR_STAT_REG, %l3, %g5 | |
85 | stx %g4, [%g5] | |
86 | ||
87 | set_DRAM_error_inject_ch0: | |
88 | mov 0x2, %l1 ! ECC Mask (1-bit error) | |
89 | mov 0x1, %l2 | |
90 | sllx %l2, DRAM_EI_SSHOT, %l3 | |
91 | Or %l1, %l3, %l1 ! Set single shot ; | |
92 | mov 0x1, %l2 | |
93 | sllx %l2, DRAM_EI_ENB, %l3 | |
94 | or %l1, %l3, %l1 ! Enable error injection for the next write | |
95 | setx DRAM_ERR_INJ_REG, %l3, %g6 | |
96 | stx %l1, [%g6] | |
97 | membar 0x40 | |
98 | ||
99 | enable_err_reporting: | |
100 | setx L2EE_PA0, %l0, %l1 | |
101 | ldx [%l1], %l2 | |
102 | mov 0x3, %l0 | |
103 | or %l2, %l0, %l2 | |
104 | stx %l2, [%l1] | |
105 | ||
106 | ! Write 1 to clear L2 Error status registers | |
107 | clear_l2_ESR: | |
108 | setx L2ES_PA0, %l3, %l4 | |
109 | stx %g4, [%l4] | |
110 | nop | |
111 | ||
112 | store_to_L2: | |
113 | setx TEST_DATA1, %l0, %g5 | |
114 | ||
115 | ||
116 | set_L2_Directly_Mapped_Mode: | |
117 | setx L2CS_PA0, %l6, %g1 | |
118 | mov 0x2, %l0 | |
119 | stx %l0, [%g1] | |
120 | ||
121 | ||
122 | store_to_L2_way0: | |
123 | setx 0x2200aa00, %l0, %g2 ! bits [21:18] select way | |
124 | stx %g5, [%g2] | |
125 | stx %g5, [%g2+8] | |
126 | membar #Sync | |
127 | ||
128 | ! Storing to same L2 way0 but different tag,this will write to mcu | |
129 | write_mcu_channel_0: | |
130 | setx 0x2100aa00, %l0, %g3 ! bits [21:18] select way | |
131 | stx %g5, [%g3] | |
132 | stx %g5, [%g3+8] | |
133 | membar #Sync | |
134 | ||
135 | ||
136 | read_error_address_ch0: | |
137 | stx %g5, [%g2] | |
138 | ! ldx [%g2], %l1 | |
139 | membar #Sync | |
140 | ! ldx [%g3], %l2 | |
141 | ! membar #Sync | |
142 | ||
143 | ||
144 | check_DRAM_ESR_0: | |
145 | setx DRAM_ERR_STAT_REG, %l3, %g5 | |
146 | ldx [%g5], %l6 | |
147 | ||
148 | compute_dram_ESR: | |
149 | mov 0x1, %l1 | |
150 | sllx %l1, DRAM_ES_DAC, %l0 | |
151 | set 0x0002, %l3 ! 16-bit Syndrome - for SECC, it's the mask nibble-reversed | |
152 | or %l0, %l3, %l0 ! %l0 has expected value | |
153 | ||
154 | verify_dram_ESR: | |
155 | cmp %l0, %l6 | |
156 | bne %xcc, test_fail | |
157 | nop | |
158 | ||
159 | check_L2_ESR_0: | |
160 | setx L2_ERR_STAT_REG, %l3, %g5 | |
161 | ldx [%g5], %l6 | |
162 | ||
163 | compute_L2_ESR: | |
164 | setx 0xfffffffff0000000, %l3, %l0 | |
165 | andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits | |
166 | mov 0x1, %l1 | |
167 | sllx %l1, L2ES_DAC, %l0 | |
168 | mov 0x1, %l1 | |
169 | sllx %l1, L2ES_VEC, %l2 | |
170 | or %l0, %l2, %l3 | |
171 | ||
172 | verify_L2_ESR: | |
173 | cmp %l5, %l3 | |
174 | bne %xcc, test_fail | |
175 | nop | |
176 | ||
177 | ||
178 | setx L2EA_PA0, %l2, %l3 | |
179 | check_l2_EAR: | |
180 | ldx [%l3], %l4 | |
181 | ! Error address is the physical address of the cache line | |
182 | setx 0x2200aa00, %l0, %l1 ! bits [21:18] select way | |
183 | setx 0xffffffffc0, %l0,%o2 | |
184 | and %l4, %o2, %l4 | |
185 | cmp %l4, %l1 | |
186 | bne %xcc, test_fail | |
187 | nop | |
188 | ||
189 | ||
190 | check_hw_err_trap: | |
191 | ! Check if a Hardware Corrected Error Trap happened | |
192 | set EXECUTED, %l0 | |
193 | cmp %o0, %l0 | |
194 | bne test_fail | |
195 | nop | |
196 | mov TT_Corrected_ECC, %l0 | |
197 | ! mov TT_SW_Error, %l0 | |
198 | cmp %o1, %l0 | |
199 | bne test_fail | |
200 | nop | |
201 | ||
202 | ||
203 | ba test_pass | |
204 | nop | |
205 | ||
206 | My_Corrected_ECC_error_trap: | |
207 | ||
208 | !My_Recoverable_Sw_error_trap: | |
209 | ! Signal trap taken | |
210 | setx EXECUTED, %l0, %o0 | |
211 | ! save trap type value | |
212 | rdpr %tt, %o1 | |
213 | retry | |
214 | nop | |
215 | ||
216 | /******************************************************* | |
217 | * Exit code | |
218 | *******************************************************/ | |
219 | ||
220 | test_pass: | |
221 | ta T_GOOD_TRAP | |
222 | ||
223 | ||
224 | test_fail: | |
225 | ta T_BAD_TRAP | |
226 | ||
227 | ||
228 |