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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: Bug103049.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define MAIN_PAGE_HV_ALSO | |
39 | #define RESET_STAT_CHECK | |
40 | #define RESET_CHECK_REG | |
41 | ||
42 | #define H_HT0_DAE_invalid_asi_0x14 | |
43 | #define SUN_H_HT0_DAE_invalid_asi_0x14 \ | |
44 | inc %l0;\ | |
45 | done; nop | |
46 | ||
47 | #include "hboot.s" | |
48 | #include "rst_defines.h" | |
49 | ||
50 | /* | |
51 | Test case code start | |
52 | */ | |
53 | .text | |
54 | .global main | |
55 | main: | |
56 | ||
57 | ta T_CHANGE_HPRIV | |
58 | nop | |
59 | ||
60 | ||
61 | ! ASI_OVERLAP_MODE - access not implemented. See bug 103105 | |
62 | ! trying to access it should cause an exception | |
63 | ||
64 | mov 0, %l0 ! interrupt count | |
65 | mov 0x10, %g1 | |
66 | ldxa [%g1]ASI_LSU_CONTROL, %g1 | |
67 | ||
68 | cmp %l0, 0 | |
69 | be test_failed ! should have taken an interrupt | |
70 | nop | |
71 | ||
72 | ! ASI_WMR_VEC_MASK (asi 0x45) | |
73 | ||
74 | mov 0x18, %g1 | |
75 | ldxa [%g1]ASI_LSU_CONTROL, %g1 | |
76 | ||
77 | ! ASI_CMP_CORE (asi 0x41) | |
78 | ||
79 | mov ASI_CMP_CORE_AVAIL, %g1 | |
80 | ldxa [%g1]ASI_CMP_CORE, %g1 | |
81 | ||
82 | mov ASI_CMP_CORE_ENABLED, %g1 | |
83 | ldxa [%g1]ASI_CMP_CORE, %g1 | |
84 | ||
85 | mov ASI_CMP_CORE_ENABLE, %g1 | |
86 | ldxa [%g1]ASI_CMP_CORE, %g1 | |
87 | ||
88 | mov ASI_CMP_XIR_STEERING, %g1 | |
89 | ldxa [%g1]ASI_CMP_CORE, %g1 | |
90 | ||
91 | mov ASI_CMP_TICK_ENABLE, %g1 | |
92 | ldxa [%g1]ASI_CMP_CORE, %g1 | |
93 | ||
94 | mov ASI_CMP_CORE_RUNNING_RW, %g1 | |
95 | ldxa [%g1]ASI_CMP_CORE, %g1 | |
96 | ||
97 | mov ASI_CMP_CORE_RUNNING_STATUS, %g1 | |
98 | ldxa [%g1]ASI_CMP_CORE, %g1 | |
99 | ||
100 | mov 0, %l0 ! interrupt count | |
101 | mov ASI_CMP_CORE_RUNNING_W1S, %g1 | |
102 | ldxa [%g1]ASI_CMP_CORE, %g1 | |
103 | ||
104 | cmp %l0, 0 | |
105 | be test_failed ! should have taken an interrupt | |
106 | nop | |
107 | ||
108 | mov 0, %l0 ! interrupt count | |
109 | mov ASI_CMP_CORE_RUNNING_W1C, %g1 | |
110 | ldxa [%g1]ASI_CMP_CORE, %g1 | |
111 | ||
112 | cmp %l0, 0 | |
113 | be test_failed ! should have taken an interrupt | |
114 | nop | |
115 | ||
116 | do_SUBSYSTEM_RESET: | |
117 | setx 0x8900000800, %g1, %g5 ! RST base addr + 0x800 | |
118 | mov RST_SSYS_RESET__DMU_PEU, %g7 ! subsystem reset reg data | |
119 | stx %g7, [%g5+0x38] ! Subsystem Reset | |
120 | ||
121 | mov 255, %l0 ! loop timeout count | |
122 | ||
123 | Wait4SsysReset: | |
124 | ldx [%g5+0x38], %l7 ! check if reset bit has cleared | |
125 | brz %l7, read_other_rst_regs | |
126 | nop | |
127 | dec %l0 | |
128 | brnz %l0, Wait4SsysReset | |
129 | nop | |
130 | ba test_failed ! Subsystem reset should have completed | |
131 | nop | |
132 | ||
133 | read_other_rst_regs: | |
134 | ldx [%g5+0x08], %l0 | |
135 | ldx [%g5+0x10], %l1 | |
136 | ldx [%g5+0x18], %l2 | |
137 | ldx [%g5+0x20], %l3 | |
138 | ldx [%g5+0x38], %l4 | |
139 | ! ldx [%g5+0x70], %l5 | |
140 | ! ldx [%g5+0x80], %l6 | |
141 | ! ldx [%g5+0x90], %l7 | |
142 | nop | |
143 | ||
144 | test_passed: | |
145 | EXIT_GOOD | |
146 | ||
147 | test_failed: | |
148 | EXIT_BAD | |
149 |