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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: PCIePIOTimeout.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define ENABLE_PCIE_LINK_TRAINING | |
39 | #define MAIN_PAGE_HV_ALSO | |
40 | ||
41 | #define H_HT0_Data_access_error_0x32 | |
42 | #define SUN_H_HT0_Data_access_error_0x32 \ | |
43 | inc %l4; \ | |
44 | done; | |
45 | ||
46 | #include "hboot.s" | |
47 | ||
48 | #define CFG0_RD_ADDR N2_PCIE_BASE_ADDR | |
49 | #define CFG1_RD_ADDR mpeval(CFG0_RD_ADDR + CFG1_ACCESS_PA) | |
50 | ||
51 | /************************************************************************ | |
52 | Test case code start | |
53 | ************************************************************************/ | |
54 | .text | |
55 | .global main | |
56 | main: | |
57 | ta T_CHANGE_HPRIV | |
58 | nop | |
59 | ||
60 | mov 0, %l4 ! zero the interrupt count | |
61 | ||
62 | /****************************************************************************** | |
63 | Set the Completion Timeout Select (CTO_SEL) to its minimum (2^10 symbol times) | |
64 | ******************************************************************************/ | |
65 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g2, %g3 | |
66 | set 0x00070000, %g4 ! set bits[18: 16] to 3'b111 | |
67 | ldx [%g3], %g5 | |
68 | or %g5, %g4, %g5 | |
69 | stx %g5, [%g3] | |
70 | ||
71 | ||
72 | ! select a CFG1 address in PCI address range and transmit the command to NCU | |
73 | setx CFG1_RD_ADDR, %g1, %g2 | |
74 | ||
75 | ! Load a couple of words to show that PIOs are working | |
76 | lduw [%g2 + 0*4], %o4 | |
77 | lduw [%g2 + 1*4], %o5 | |
78 | ||
79 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR, %g1, %g3 | |
80 | ldx [%g3], %g4 ! status | |
81 | stx %g4, [%g3] ! clear it | |
82 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1C_ALIAS_ADDR, %g1, %g5 | |
83 | ldx [%g5], %g4 ! status | |
84 | stx %g4, [%g5] ! clear it | |
85 | ||
86 | /****************************************************************************** | |
87 | On the next PIO, get a timeout error (no completion) | |
88 | ******************************************************************************/ | |
89 | ! $EV trig_pc_d(1, @VA(.MAIN.PIO_Timeout)) -> EnablePCIeIgCmd ("PIO_TIMEOUT",0,0,0,1) | |
90 | PIO_Timeout: nop; nop; nop; nop; nop; nop; nop; nop; | |
91 | lduw [%g2 + 5*8], %o4 ! this one should timeout | |
92 | ||
93 | lduw [%g2 + 6*8], %o5 ! this one should be good | |
94 | lduw [%g2 + 7*8], %o6 ! this one should be good | |
95 | ||
96 | ldx [%g3], %g4 ! OE status => should get the CTO bit set | |
97 | setx 0x0000000000200000, %g1, %l1 | |
98 | xor %l1, %g4, %l1 | |
99 | brnz %l1, test_failed | |
100 | stx %g4, [%g3] ! clear it | |
101 | ||
102 | ldx [%g3 + 0x10], %l0 ! OE Receive Hdr1 | |
103 | ldx [%g3 + 0x18], %l1 ! OE Receive Hdr2 | |
104 | ||
105 | ldx [%g5], %g6 ! UE status => should get the CTO bit set | |
106 | setx 0x0000000000004000, %g1, %l1 | |
107 | xor %l1, %g6, %l1 | |
108 | brnz %l1, test_failed | |
109 | stx %g6, [%g5] ! clear it | |
110 | ||
111 | ldx [%g5 + 0x10], %l0 ! UE Receive Hdr1 | |
112 | ldx [%g5 + 0x18], %l1 ! UE Receive Hdr2 | |
113 | ||
114 | ! test whether enough exceptions were taken | |
115 | sub %l4, 1, %l4 | |
116 | brnz %l4, test_failed | |
117 | nop | |
118 | ||
119 | ||
120 | test_passed: | |
121 | EXIT_GOOD | |
122 | ||
123 | test_failed: | |
124 | EXIT_BAD | |
125 | ||
126 | ||
127 | SECTION .DATA2 DATA_VA=CFG1_RD_ADDR | |
128 | attr_data { | |
129 | Name = .DATA2, | |
130 | hypervisor, | |
131 | compressimage | |
132 | } | |
133 | ||
134 | .data | |
135 | .word 0x11121314 | |
136 | .word 0x21222324 | |
137 | .word 0x31323334 | |
138 | .word 0x41424344 | |
139 | .word 0xdeadbeef | |
140 | .word 0x61626364 | |
141 | .word 0x71727374 | |
142 | .word 0x81828384 | |
143 | ||
144 | ||
145 | /************************************************************************/ |