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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: ncu_mcu0_sample.vrhpal | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | sample ncu_mcu0_intf_size_sample (ncu_mcu0_size) | |
36 | { | |
37 | state SIZE0 ( 3'b011 ); | |
38 | } | |
39 | sample ncu_mcu0_intf_type_sample (ncu_mcu0_type) | |
40 | { | |
41 | state READ_REQ ( 4'b0100 ); | |
42 | state WRITE_REQ ( 4'b0101 ); | |
43 | } | |
44 | sample ncu_mcu0_intf_type_trans (ncu_mcu0_type) | |
45 | { | |
46 | state READ_REQ ( 4'b0100 ); | |
47 | state WRITE_REQ ( 4'b0101 ); | |
48 | ||
49 | trans TYPE_TRAN00 ("READ_REQ" -> "READ_REQ"); | |
50 | trans TYPE_TRAN01 ("READ_REQ" -> "WRITE_REQ"); | |
51 | ||
52 | trans TYPE_TRAN10 ("WRITE_REQ" -> "READ_REQ"); | |
53 | trans TYPE_TRAN11 ("WRITE_REQ" -> "WRITE_REQ"); | |
54 | ||
55 | } | |
56 | ||
57 | ||
58 | sample ncu_mcu0_intf_bufid_sample (ncu_mcu0_bufid) | |
59 | { | |
60 | m_state BUFFID (0:1); | |
61 | } | |
62 | ||
63 | ||
64 | ||
65 | sample ncu_mcu0_intf_cpuid_sample (ncu_mcu0_cpuid) | |
66 | { | |
67 | m_state CPUID ( 0:63 ) ; | |
68 | } | |
69 | ||
70 | sample ncu_mcu0_intf_b2b_sample (ncu_mcu0_b2b) | |
71 | { | |
72 | m_state B2B ( 2:5 ) ; | |
73 | } | |
74 | ||
75 | sample ncu_mcu0_intf_stall_b2b_sample (mcu0_ncu_stall_b2b) | |
76 | { | |
77 | m_state STALL ( 1:30) ; | |
78 | } | |
79 | sample ncu_mcu0_intf_pkt_gap (ncu_mcu0_pkt_gap) | |
80 | { | |
81 | m_state PKT_GAP ( 1:10) ; | |
82 | } | |
83 | ||
84 | cross ncu_mcu0_intf_id_type_cross(ncu_mcu0_intf_cpuid_sample, ncu_mcu0_intf_type_sample); | |
85 |