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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: FcMcuMonPort.if.vrh | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | #ifndef INC_FC_MCUMON_IF_VRH | |
36 | #define INC_FC_MCUMON_IF_VRH | |
37 | ||
38 | ||
39 | #include <vera_defines.vrh> | |
40 | #define INPUT_SKEW #-0 | |
41 | ||
42 | interface dram_write_Mcu0_if { | |
43 | ||
44 | input clk CLOCK verilog_node "tb_top.cpu.mcu0.drl2clk"; | |
45 | input ncu_sii_l2_idx_hash_en PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.sii.ncu_sii_l2_idx_hash_en"; | |
46 | input drif_dram_rank_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.drif_dram_rank_a"; | |
47 | input [2:0] drif_dram_dimm_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.drif_dram_dimm_a"; | |
48 | input [2:0] drif_dram_bank_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.drif_dram_bank_a"; | |
49 | input [15:0] drif_dram_addr_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.drif_dram_addr_a"; | |
50 | #ifdef MCU_GATE | |
51 | input [2:0] drif_dram_cmd_a PSAMPLE INPUT_SKEW verilog_node "{ `CPU.mcu0.drif__n32596, `CPU.mcu0.\drif_dram_cmd_a[1] , `CPU.mcu0.\drif_dram_cmd_a[0] }"; | |
52 | #else | |
53 | input [2:0] drif_dram_cmd_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.drif_dram_cmd_a"; | |
54 | #endif // MCU_GATE | |
55 | ||
56 | input drif_dram_rank_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.drif_dram_rank_b"; | |
57 | input [2:0] drif_dram_dimm_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.drif_dram_dimm_b"; | |
58 | input [2:0] drif_dram_bank_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.drif_dram_bank_b"; | |
59 | input [15:0] drif_dram_addr_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.drif_dram_addr_b"; | |
60 | input [2:0] drif_dram_cmd_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.drif_dram_cmd_b"; | |
61 | ||
62 | input drif_dram_rank_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.drif_dram_rank_c"; | |
63 | input [2:0] drif_dram_dimm_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.drif_dram_dimm_c"; | |
64 | input [2:0] drif_dram_bank_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.drif_dram_bank_c"; | |
65 | input [15:0] drif_dram_addr_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.drif_dram_addr_c"; | |
66 | input [2:0] drif_dram_cmd_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.drif_dram_cmd_c"; | |
67 | ||
68 | input ncu_mcu_ba01 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.ncu_mcu_ba01"; | |
69 | input ncu_mcu_ba23 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.ncu_mcu_ba23"; | |
70 | input ncu_mcu_ba45 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.ncu_mcu_ba45"; | |
71 | input ncu_mcu_ba67 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.ncu_mcu_ba67"; | |
72 | } | |
73 | ||
74 | interface dram_write_Mcu1_if { | |
75 | ||
76 | input clk CLOCK verilog_node "tb_top.cpu.mcu1.drl2clk"; | |
77 | input drif_dram_rank_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.drif_dram_rank_a"; | |
78 | input [2:0] drif_dram_dimm_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.drif_dram_dimm_a"; | |
79 | input [2:0] drif_dram_bank_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.drif_dram_bank_a"; | |
80 | input [15:0] drif_dram_addr_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.drif_dram_addr_a"; | |
81 | #ifdef MCU_GATE | |
82 | input [2:0] drif_dram_cmd_a PSAMPLE INPUT_SKEW verilog_node "{ `CPU.mcu1.drif__n32596, `CPU.mcu1.\drif_dram_cmd_a[1] , `CPU.mcu1.\drif_dram_cmd_a[0] }"; | |
83 | #else | |
84 | input [2:0] drif_dram_cmd_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.drif_dram_cmd_a"; | |
85 | #endif // MCU_GATE | |
86 | ||
87 | input drif_dram_rank_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.drif_dram_rank_b"; | |
88 | input [2:0] drif_dram_dimm_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.drif_dram_dimm_b"; | |
89 | input [2:0] drif_dram_bank_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.drif_dram_bank_b"; | |
90 | input [15:0] drif_dram_addr_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.drif_dram_addr_b"; | |
91 | input [2:0] drif_dram_cmd_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.drif_dram_cmd_b"; | |
92 | ||
93 | input drif_dram_rank_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.drif_dram_rank_c"; | |
94 | input [2:0] drif_dram_dimm_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.drif_dram_dimm_c"; | |
95 | input [2:0] drif_dram_bank_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.drif_dram_bank_c"; | |
96 | input [15:0] drif_dram_addr_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.drif_dram_addr_c"; | |
97 | input [2:0] drif_dram_cmd_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.drif_dram_cmd_c"; | |
98 | ||
99 | input ncu_mcu_ba01 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.ncu_mcu_ba01"; | |
100 | input ncu_mcu_ba23 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.ncu_mcu_ba23"; | |
101 | input ncu_mcu_ba45 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.ncu_mcu_ba45"; | |
102 | input ncu_mcu_ba67 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.ncu_mcu_ba67"; | |
103 | } | |
104 | ||
105 | interface dram_write_Mcu2_if { | |
106 | ||
107 | input clk CLOCK verilog_node "tb_top.cpu.mcu2.drl2clk"; | |
108 | input drif_dram_rank_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.drif_dram_rank_a"; | |
109 | input [2:0] drif_dram_dimm_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.drif_dram_dimm_a"; | |
110 | input [2:0] drif_dram_bank_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.drif_dram_bank_a"; | |
111 | input [15:0] drif_dram_addr_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.drif_dram_addr_a"; | |
112 | #ifdef MCU_GATE | |
113 | input [2:0] drif_dram_cmd_a PSAMPLE INPUT_SKEW verilog_node "{ `CPU.mcu2.drif__n32596, `CPU.mcu2.\drif_dram_cmd_a[1] , `CPU.mcu2.\drif_dram_cmd_a[0] }"; | |
114 | #else | |
115 | input [2:0] drif_dram_cmd_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.drif_dram_cmd_a"; | |
116 | #endif // MCU_GATE | |
117 | ||
118 | input drif_dram_rank_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.drif_dram_rank_b"; | |
119 | input [2:0] drif_dram_dimm_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.drif_dram_dimm_b"; | |
120 | input [2:0] drif_dram_bank_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.drif_dram_bank_b"; | |
121 | input [15:0] drif_dram_addr_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.drif_dram_addr_b"; | |
122 | input [2:0] drif_dram_cmd_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.drif_dram_cmd_b"; | |
123 | ||
124 | input drif_dram_rank_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.drif_dram_rank_c"; | |
125 | input [2:0] drif_dram_dimm_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.drif_dram_dimm_c"; | |
126 | input [2:0] drif_dram_bank_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.drif_dram_bank_c"; | |
127 | input [15:0] drif_dram_addr_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.drif_dram_addr_c"; | |
128 | input [2:0] drif_dram_cmd_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.drif_dram_cmd_c"; | |
129 | ||
130 | input ncu_mcu_ba01 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.ncu_mcu_ba01"; | |
131 | input ncu_mcu_ba23 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.ncu_mcu_ba23"; | |
132 | input ncu_mcu_ba45 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.ncu_mcu_ba45"; | |
133 | input ncu_mcu_ba67 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.ncu_mcu_ba67"; | |
134 | } | |
135 | ||
136 | interface dram_write_Mcu3_if { | |
137 | ||
138 | input clk CLOCK verilog_node "tb_top.cpu.mcu3.drl2clk"; | |
139 | input drif_dram_rank_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.drif_dram_rank_a"; | |
140 | input [2:0] drif_dram_dimm_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.drif_dram_dimm_a"; | |
141 | input [2:0] drif_dram_bank_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.drif_dram_bank_a"; | |
142 | input [15:0] drif_dram_addr_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.drif_dram_addr_a"; | |
143 | #ifdef MCU_GATE | |
144 | input [2:0] drif_dram_cmd_a PSAMPLE INPUT_SKEW verilog_node "{ `CPU.mcu3.drif__n32596, `CPU.mcu3.\drif_dram_cmd_a[1] , `CPU.mcu3.\drif_dram_cmd_a[0] }"; | |
145 | #else | |
146 | input [2:0] drif_dram_cmd_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.drif_dram_cmd_a"; | |
147 | #endif // MCU_GATE | |
148 | ||
149 | input drif_dram_rank_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.drif_dram_rank_b"; | |
150 | input [2:0] drif_dram_dimm_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.drif_dram_dimm_b"; | |
151 | input [2:0] drif_dram_bank_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.drif_dram_bank_b"; | |
152 | input [15:0] drif_dram_addr_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.drif_dram_addr_b"; | |
153 | input [2:0] drif_dram_cmd_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.drif_dram_cmd_b"; | |
154 | ||
155 | input drif_dram_rank_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.drif_dram_rank_c"; | |
156 | input [2:0] drif_dram_dimm_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.drif_dram_dimm_c"; | |
157 | input [2:0] drif_dram_bank_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.drif_dram_bank_c"; | |
158 | input [15:0] drif_dram_addr_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.drif_dram_addr_c"; | |
159 | input [2:0] drif_dram_cmd_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.drif_dram_cmd_c"; | |
160 | ||
161 | input ncu_mcu_ba01 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.ncu_mcu_ba01"; | |
162 | input ncu_mcu_ba23 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.ncu_mcu_ba23"; | |
163 | input ncu_mcu_ba45 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.ncu_mcu_ba45"; | |
164 | input ncu_mcu_ba67 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.ncu_mcu_ba67"; | |
165 | } | |
166 | ||
167 | port dram_write_MCU | |
168 | { | |
169 | drl2clk; | |
170 | index_hashing; | |
171 | drif_dram_rank_a; | |
172 | drif_dram_dimm_a; | |
173 | drif_dram_bank_a; | |
174 | drif_dram_addr_a; | |
175 | drif_dram_cmd_a; | |
176 | ||
177 | drif_dram_rank_b; | |
178 | drif_dram_dimm_b; | |
179 | drif_dram_bank_b; | |
180 | drif_dram_addr_b; | |
181 | drif_dram_cmd_b; | |
182 | ||
183 | drif_dram_rank_c; | |
184 | drif_dram_dimm_c; | |
185 | drif_dram_bank_c; | |
186 | drif_dram_addr_c; | |
187 | drif_dram_cmd_c; | |
188 | ||
189 | ncu_mcu_ba01; | |
190 | ncu_mcu_ba23; | |
191 | ncu_mcu_ba45; | |
192 | ncu_mcu_ba67; | |
193 | ||
194 | } | |
195 | ||
196 | bind dram_write_MCU DramWriteMCU0 | |
197 | { | |
198 | drl2clk dram_write_Mcu0_if.clk; | |
199 | index_hashing dram_write_Mcu0_if.ncu_sii_l2_idx_hash_en; | |
200 | drif_dram_rank_a dram_write_Mcu0_if.drif_dram_rank_a; | |
201 | drif_dram_dimm_a dram_write_Mcu0_if.drif_dram_dimm_a; | |
202 | drif_dram_bank_a dram_write_Mcu0_if.drif_dram_bank_a; | |
203 | drif_dram_addr_a dram_write_Mcu0_if.drif_dram_addr_a; | |
204 | drif_dram_cmd_a dram_write_Mcu0_if.drif_dram_cmd_a; | |
205 | ||
206 | drif_dram_rank_b dram_write_Mcu0_if.drif_dram_rank_b; | |
207 | drif_dram_dimm_b dram_write_Mcu0_if.drif_dram_dimm_b; | |
208 | drif_dram_bank_b dram_write_Mcu0_if.drif_dram_bank_b; | |
209 | drif_dram_addr_b dram_write_Mcu0_if.drif_dram_addr_b; | |
210 | drif_dram_cmd_b dram_write_Mcu0_if.drif_dram_cmd_b; | |
211 | ||
212 | drif_dram_rank_c dram_write_Mcu0_if.drif_dram_rank_c; | |
213 | drif_dram_dimm_c dram_write_Mcu0_if.drif_dram_dimm_c; | |
214 | drif_dram_bank_c dram_write_Mcu0_if.drif_dram_bank_c; | |
215 | drif_dram_addr_c dram_write_Mcu0_if.drif_dram_addr_c; | |
216 | drif_dram_cmd_c dram_write_Mcu0_if.drif_dram_cmd_c; | |
217 | ||
218 | ncu_mcu_ba01 dram_write_Mcu0_if.ncu_mcu_ba01; | |
219 | ncu_mcu_ba23 dram_write_Mcu0_if.ncu_mcu_ba23; | |
220 | ncu_mcu_ba45 dram_write_Mcu0_if.ncu_mcu_ba45; | |
221 | ncu_mcu_ba67 dram_write_Mcu0_if.ncu_mcu_ba67; | |
222 | } | |
223 | ||
224 | bind dram_write_MCU DramWriteMCU1 | |
225 | { | |
226 | drl2clk dram_write_Mcu1_if.clk; | |
227 | index_hashing dram_write_Mcu0_if.ncu_sii_l2_idx_hash_en; | |
228 | drif_dram_rank_a dram_write_Mcu1_if.drif_dram_rank_a; | |
229 | drif_dram_dimm_a dram_write_Mcu1_if.drif_dram_dimm_a; | |
230 | drif_dram_bank_a dram_write_Mcu1_if.drif_dram_bank_a; | |
231 | drif_dram_addr_a dram_write_Mcu1_if.drif_dram_addr_a; | |
232 | drif_dram_cmd_a dram_write_Mcu1_if.drif_dram_cmd_a; | |
233 | ||
234 | drif_dram_rank_b dram_write_Mcu1_if.drif_dram_rank_b; | |
235 | drif_dram_dimm_b dram_write_Mcu1_if.drif_dram_dimm_b; | |
236 | drif_dram_bank_b dram_write_Mcu1_if.drif_dram_bank_b; | |
237 | drif_dram_addr_b dram_write_Mcu1_if.drif_dram_addr_b; | |
238 | drif_dram_cmd_b dram_write_Mcu1_if.drif_dram_cmd_b; | |
239 | ||
240 | drif_dram_rank_c dram_write_Mcu1_if.drif_dram_rank_c; | |
241 | drif_dram_dimm_c dram_write_Mcu1_if.drif_dram_dimm_c; | |
242 | drif_dram_bank_c dram_write_Mcu1_if.drif_dram_bank_c; | |
243 | drif_dram_addr_c dram_write_Mcu1_if.drif_dram_addr_c; | |
244 | drif_dram_cmd_c dram_write_Mcu1_if.drif_dram_cmd_c; | |
245 | ||
246 | ncu_mcu_ba01 dram_write_Mcu1_if.ncu_mcu_ba01; | |
247 | ncu_mcu_ba23 dram_write_Mcu1_if.ncu_mcu_ba23; | |
248 | ncu_mcu_ba45 dram_write_Mcu1_if.ncu_mcu_ba45; | |
249 | ncu_mcu_ba67 dram_write_Mcu1_if.ncu_mcu_ba67; | |
250 | } | |
251 | ||
252 | bind dram_write_MCU DramWriteMCU2 | |
253 | { | |
254 | drl2clk dram_write_Mcu2_if.clk; | |
255 | index_hashing dram_write_Mcu0_if.ncu_sii_l2_idx_hash_en; | |
256 | drif_dram_rank_a dram_write_Mcu2_if.drif_dram_rank_a; | |
257 | drif_dram_dimm_a dram_write_Mcu2_if.drif_dram_dimm_a; | |
258 | drif_dram_bank_a dram_write_Mcu2_if.drif_dram_bank_a; | |
259 | drif_dram_addr_a dram_write_Mcu2_if.drif_dram_addr_a; | |
260 | drif_dram_cmd_a dram_write_Mcu2_if.drif_dram_cmd_a; | |
261 | ||
262 | drif_dram_rank_b dram_write_Mcu2_if.drif_dram_rank_b; | |
263 | drif_dram_dimm_b dram_write_Mcu2_if.drif_dram_dimm_b; | |
264 | drif_dram_bank_b dram_write_Mcu2_if.drif_dram_bank_b; | |
265 | drif_dram_addr_b dram_write_Mcu2_if.drif_dram_addr_b; | |
266 | drif_dram_cmd_b dram_write_Mcu2_if.drif_dram_cmd_b; | |
267 | ||
268 | drif_dram_rank_c dram_write_Mcu2_if.drif_dram_rank_c; | |
269 | drif_dram_dimm_c dram_write_Mcu2_if.drif_dram_dimm_c; | |
270 | drif_dram_bank_c dram_write_Mcu2_if.drif_dram_bank_c; | |
271 | drif_dram_addr_c dram_write_Mcu2_if.drif_dram_addr_c; | |
272 | drif_dram_cmd_c dram_write_Mcu2_if.drif_dram_cmd_c; | |
273 | ||
274 | ncu_mcu_ba01 dram_write_Mcu2_if.ncu_mcu_ba01; | |
275 | ncu_mcu_ba23 dram_write_Mcu2_if.ncu_mcu_ba23; | |
276 | ncu_mcu_ba45 dram_write_Mcu2_if.ncu_mcu_ba45; | |
277 | ncu_mcu_ba67 dram_write_Mcu2_if.ncu_mcu_ba67; | |
278 | } | |
279 | ||
280 | bind dram_write_MCU DramWriteMCU3 | |
281 | { | |
282 | drl2clk dram_write_Mcu3_if.clk; | |
283 | index_hashing dram_write_Mcu0_if.ncu_sii_l2_idx_hash_en; | |
284 | drif_dram_rank_a dram_write_Mcu3_if.drif_dram_rank_a; | |
285 | drif_dram_dimm_a dram_write_Mcu3_if.drif_dram_dimm_a; | |
286 | drif_dram_bank_a dram_write_Mcu3_if.drif_dram_bank_a; | |
287 | drif_dram_addr_a dram_write_Mcu3_if.drif_dram_addr_a; | |
288 | drif_dram_cmd_a dram_write_Mcu3_if.drif_dram_cmd_a; | |
289 | ||
290 | drif_dram_rank_b dram_write_Mcu3_if.drif_dram_rank_b; | |
291 | drif_dram_dimm_b dram_write_Mcu3_if.drif_dram_dimm_b; | |
292 | drif_dram_bank_b dram_write_Mcu3_if.drif_dram_bank_b; | |
293 | drif_dram_addr_b dram_write_Mcu3_if.drif_dram_addr_b; | |
294 | drif_dram_cmd_b dram_write_Mcu3_if.drif_dram_cmd_b; | |
295 | ||
296 | drif_dram_rank_c dram_write_Mcu3_if.drif_dram_rank_c; | |
297 | drif_dram_dimm_c dram_write_Mcu3_if.drif_dram_dimm_c; | |
298 | drif_dram_bank_c dram_write_Mcu3_if.drif_dram_bank_c; | |
299 | drif_dram_addr_c dram_write_Mcu3_if.drif_dram_addr_c; | |
300 | drif_dram_cmd_c dram_write_Mcu3_if.drif_dram_cmd_c; | |
301 | ||
302 | ncu_mcu_ba01 dram_write_Mcu3_if.ncu_mcu_ba01; | |
303 | ncu_mcu_ba23 dram_write_Mcu3_if.ncu_mcu_ba23; | |
304 | ncu_mcu_ba45 dram_write_Mcu3_if.ncu_mcu_ba45; | |
305 | ncu_mcu_ba67 dram_write_Mcu3_if.ncu_mcu_ba67; | |
306 | } | |
307 | ||
308 | #endif |