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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: ncu_xir_chkr.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module ncu_xir_chkr (); | |
36 | ||
37 | /* 0in assert_follower | |
38 | -leader ( $0in_falling_edge (`RST.rst_fsm_ctl.mio_rst_button_xir_sys_)) | |
39 | -follower ( $0in_falling_edge (`RST.rst_fsm_ctl.rst_ncu_xir_sys_)) | |
40 | -clock `RST.rst_fsm_ctl.ref_clk | |
41 | -module rst | |
42 | */ | |
43 | /* 0in assert_follower | |
44 | -leader ($0in_falling_edge (`CPU.rst_ncu_xir_)) | |
45 | -follower ($0in_rising_edge (`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.xir_trigger )) | |
46 | -clock `NCU.iol2clk | |
47 | -module ncu | |
48 | */ | |
49 | reg rst_ncu_xir_active; | |
50 | reg rst_ncu_xir_active_d1; | |
51 | reg rst_ncu_xir_active_d2; | |
52 | reg rst_ncu_xir_active_pusle_d1; | |
53 | reg rst_ncu_xir_done_pulse_d1; | |
54 | reg valid_d1; | |
55 | ||
56 | reg [63:0] xir_steering_save; | |
57 | reg [2:0] expected_cpuid; | |
58 | reg [2:0] expected_thrid; | |
59 | reg [6:0] expected_valid; | |
60 | reg [6:0] num_valid; | |
61 | reg [6:0] i; | |
62 | reg [6:0] j; | |
63 | ||
64 | ||
65 | wire valid_in = `CPU.ncu_cpx_data_ca[145] & (`CPU.ncu_cpx_data_ca[144:141] == 4'b0111) & (`CPU.ncu_cpx_data_ca[15:14] == 2'b01) & (`CPU.ncu_cpx_data_ca[5:0] == 6'b000011); | |
66 | wire rst_ncu_xir_active_pusle = rst_ncu_xir_active & ~rst_ncu_xir_active_d1; | |
67 | wire rst_ncu_xir_done_pulse = ~rst_ncu_xir_active & rst_ncu_xir_active_d1; | |
68 | wire valid_pulse = valid_in & ~valid_d1; | |
69 | wire valid_gone_pulse = ~valid_in & valid_d1; | |
70 | wire thrd_on = |xir_steering_save[63:0]; | |
71 | wire rst_ncu_xir_done_por_ = rst_ncu_xir_done_pulse & ~`CPU.TESTMODE & ~`TCU.tcu_scan_en; | |
72 | ||
73 | initial begin | |
74 | rst_ncu_xir_active = 1'b0; | |
75 | rst_ncu_xir_active_d1 = 1'b0; | |
76 | rst_ncu_xir_active_pusle_d1 = 1'b0; | |
77 | rst_ncu_xir_done_pulse_d1 = 1'b0; | |
78 | xir_steering_save[63:0] = 64'b0; | |
79 | valid_d1 = 1'b0; | |
80 | expected_cpuid = 3'b0; | |
81 | expected_thrid = 3'b0; | |
82 | expected_valid = 7'b0; | |
83 | num_valid = 7'b0; | |
84 | j = 7'b0; | |
85 | i = 7'b0; | |
86 | end | |
87 | ||
88 | // 0in never -var (( `CPU.ncu_cpx_data_ca[136:134] != expected_thrid[2:0] ) | (`CPU.ncu_cpx_data_ca[13:11] != expected_cpuid[2:0]) | (`CPU.ncu_cpx_data_ca[10:8] != expected_thrid[2:0])) -active (valid_in & ~`CPU.TESTMODE & ~`TCU.tcu_scan_en) -clock `NCU.l2clk -message "TIMEOUT: the cpu and thread id's do not match the expected data" | |
89 | ||
90 | //-0in never -var ( i != 6'b0 ) -active (rst_ncu_xir_done_pulse & `CPU.efu.rst_por_) | |
91 | ||
92 | // 0in never -var ( (num_valid[6:0] != expected_valid[6:0]) ) -active ($0in_rising_edge(rst_ncu_xir_done_por_)) -clock `NCU.iol2clk -message "TIMEOUT: # of valid does not match expected #" | |
93 | ||
94 | always @ (negedge `CPU.rst_ncu_xir_ ) begin | |
95 | i = 7'b0; | |
96 | j = 7'b0; | |
97 | end | |
98 | ||
99 | always @(posedge valid_pulse ) | |
100 | begin | |
101 | while (!i[6] & thrd_on & !xir_steering_save[i]) | |
102 | i = i + 7'b1; | |
103 | {expected_cpuid, expected_thrid} = i[5:0]; | |
104 | i = i + 7'b1; | |
105 | num_valid[6:0] = num_valid[6:0] + 7'b1; | |
106 | end | |
107 | ||
108 | always @(posedge `CPU.ncu.iol2clk) | |
109 | begin | |
110 | rst_ncu_xir_active <= ~`CPU.rst_ncu_xir_; | |
111 | rst_ncu_xir_active_d1 <= rst_ncu_xir_active; | |
112 | rst_ncu_xir_active_pusle_d1 <= rst_ncu_xir_active_pusle; | |
113 | ||
114 | rst_ncu_xir_done_pulse_d1 <= rst_ncu_xir_done_pulse; | |
115 | ||
116 | if (rst_ncu_xir_active_pusle) | |
117 | xir_steering_save <= `CPU.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.xir_steering[63:0]; | |
118 | ||
119 | if (rst_ncu_xir_done_pulse_d1) | |
120 | begin | |
121 | i <= 7'b0; | |
122 | j <= 7'b0; | |
123 | expected_valid[6:0] <= 7'b0; | |
124 | num_valid[6:0] <= 7'b0; | |
125 | end | |
126 | end | |
127 | ||
128 | always @ (negedge rst_ncu_xir_active_pusle_d1) | |
129 | for (j = 7'b0 ; j < 7'b100_0000 ; j = j + 1) | |
130 | expected_valid[6:0] = expected_valid[6:0] + xir_steering_save[j]; | |
131 | ||
132 | always @ (posedge `CPU.ncu.l2clk) | |
133 | valid_d1 <= valid_in; | |
134 | ||
135 | endmodule |