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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: fbdimm.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `ifdef STINGRAY | |
36 | `timescale 1ns/1ps | |
37 | `endif | |
38 | ||
39 | `ifdef AXIS_DDR2_MODEL | |
40 | module fbdimm ( ps , ps_bar, sn , sn_bar, pn, pn_bar, ss , ss_bar , // channel interface | |
41 | sclk,dq,err_en,dram_clk,dram_2x_clk, link_clk,ref_2x_clk,clk_int,clk_int_2x); | |
42 | wire reset_n; | |
43 | `else | |
44 | module fbdimm ( ps , ps_bar, sn , sn_bar, pn, pn_bar, ss , ss_bar , // channel interface | |
45 | sclk,reset_n,err_en, dram_clk,dram_2x_clk, link_clk,ref_2x_clk,clk_int,clk_int_2x); | |
46 | input reset_n; | |
47 | `endif | |
48 | ||
49 | // Parameters | |
50 | parameter NB_LINK = 14; | |
51 | parameter SB_LINK = 10; | |
52 | parameter DS = 0; | |
53 | ||
54 | // Inputs/Outputs | |
55 | output [NB_LINK-1:0] pn,pn_bar; // primary northbound | |
56 | input [NB_LINK-1:0] sn,sn_bar; // secondary northbound | |
57 | output [SB_LINK-1:0] ss,ss_bar; // secondary southbound | |
58 | input [SB_LINK-1:0] ps,ps_bar; // primary southbound | |
59 | input sclk; | |
60 | input err_en; | |
61 | input dram_clk,dram_2x_clk, link_clk,ref_2x_clk,clk_int,clk_int_2x; | |
62 | `ifdef AXIS_DDR2_MODEL | |
63 | inout [71:0] dq; | |
64 | `else | |
65 | wire [71:0] dq,dq0,dq1; | |
66 | `endif | |
67 | ||
68 | //internal registers | |
69 | reg reset_r; | |
70 | wire reset=reset_r; | |
71 | wire clear_dcalcsr31; | |
72 | wire [3:0] ch_state; | |
73 | wire [23:0] command_in; | |
74 | wire command_rdy; | |
75 | wire [1:0] command_type; | |
76 | wire [71:0] data_in,data_out; | |
77 | wire get_wbuffer_data,put_rbuffer_data; | |
78 | wire [31:0] dcalcsr,dcaladdr,drc; | |
79 | wire dram_clk,dram_2x_clk,link_clk,ref_2x_clk,clk_int,clk_int_2x; | |
80 | wire [18:0] cke_rank0,cke_rank1,bcs,bras,bcas,bwe,dqs,bdqs,dm_rdqs,brdqs,odt,areset,term; | |
81 | wire [2:0] ba; | |
82 | wire [15:0] addr; | |
83 | wire frm_start; | |
84 | wire dram_cmd_vld_delayed,cke_reg_delayed; | |
85 | wire rs; | |
86 | wire ddrio_nbencode_rd; | |
87 | wire sb_crc_error; | |
88 | ||
89 | `ifdef STINGRAY | |
90 | // Top module AMB logic | |
91 | amb_top #(NB_LINK,SB_LINK,DS) amb( .ps ( ps ), | |
92 | .ps_bar ( ps_bar), | |
93 | .sn ( sn ), | |
94 | .sn_bar ( sn_bar), | |
95 | .pn ( pn ), | |
96 | .pn_bar ( pn_bar), | |
97 | .ss ( ss ), | |
98 | .ss_bar ( ss_bar), | |
99 | .link_clk ( link_clk), | |
100 | .link_clk_bar (~link_clk), | |
101 | .sclk ( sclk), | |
102 | .reset (~reset_n), | |
103 | .ch_state ( ch_state), | |
104 | .frm_boundary ( frm_boundary), | |
105 | .command_in ( command_in), | |
106 | .command_rdy ( command_rdy), | |
107 | .command_type ( command_type), | |
108 | .data_in ( data_in), | |
109 | .data_out ( data_out), | |
110 | .get_wbuffer_data ( get_wbuffer_data), | |
111 | .put_rbuffer_data ( put_rbuffer_data), | |
112 | .dcalcsr ( dcalcsr), | |
113 | .dcaladdr ( dcaladdr), | |
114 | .clear_dcalcsr31 ( clear_dcalcsr31 ), | |
115 | .drc ( drc), | |
116 | .dram_clk ( dram_clk), | |
117 | .dram_2x_clk ( dram_2x_clk), | |
118 | .frm_start ( frm_start), | |
119 | .ref_2x_clk ( ref_2x_clk), | |
120 | .clk_int ( clk_int), | |
121 | .ddrio_nbencode_rd ( ddrio_nbencode_rd ), | |
122 | .dram_cmd_vld_delayed ( dram_cmd_vld_delayed), | |
123 | .sb_crc_error ( sb_crc_error), | |
124 | .cke_reg_delayed ( cke_reg_delayed) | |
125 | `else | |
126 | // Top module AMB logic | |
127 | amb_top #(NB_LINK,SB_LINK,DS) amb( .ps ( ps ), | |
128 | .ps_bar ( ps_bar), | |
129 | .sn ( sn ), | |
130 | .sn_bar ( sn_bar), | |
131 | .pn ( pn ), | |
132 | .pn_bar ( pn_bar), | |
133 | .ss ( ss ), | |
134 | .ss_bar ( ss_bar), | |
135 | .link_clk ( link_clk), | |
136 | .link_clk_bar (~link_clk), | |
137 | .sclk ( sclk), | |
138 | .reset ( reset), | |
139 | .frm_boundary ( frm_boundary), | |
140 | .ch_state ( ch_state), | |
141 | .command_in ( command_in), | |
142 | .command_type ( command_type), | |
143 | .command_rdy ( command_rdy), | |
144 | .data_in ( data_in), | |
145 | .data_out ( data_out), | |
146 | .get_wbuffer_data ( get_wbuffer_data), | |
147 | .put_rbuffer_data ( put_rbuffer_data), | |
148 | .dcalcsr ( dcalcsr), | |
149 | .dcaladdr ( dcaladdr), | |
150 | .clear_dcalcsr31 ( clear_dcalcsr31 ), | |
151 | .ddrio_nbencode_rd ( ddrio_nbencode_rd ), | |
152 | .drc ( drc), | |
153 | .frm_start ( frm_start), | |
154 | .dram_clk ( dram_clk), | |
155 | .ref_2x_clk ( ref_2x_clk), | |
156 | .dram_cmd_vld_delayed ( dram_cmd_vld_delayed), | |
157 | .clk_int ( clk_int), | |
158 | .sb_crc_error ( sb_crc_error), | |
159 | .cke_reg_delayed ( cke_reg_delayed), | |
160 | .dram_2x_clk ( dram_2x_clk) | |
161 | `endif | |
162 | ||
163 | ); | |
164 | ||
165 | `ifdef FBDIMM_EXTERNAL_CLK_GEN | |
166 | `else | |
167 | fbdimm_clk_gen fbdimm_clk_gen (.sclk ( sclk), | |
168 | .frm_start ( frm_start), | |
169 | .dram_clk ( dram_clk), | |
170 | .reset_n ( reset_n), | |
171 | .frm_boundary_sb ( frm_boundary), | |
172 | .link_clk ( link_clk), | |
173 | .dram_2x_clk ( dram_2x_clk), | |
174 | .clk_int ( clk_int), | |
175 | .clk_int_2x ( clk_int_2x), | |
176 | .ref_2x_clk ( ref_2x_clk)); | |
177 | ||
178 | `endif | |
179 | ||
180 | wire drams_on; | |
181 | ||
182 | `ifdef STINGRAY | |
183 | ddr_io #(DS) dram_io ( | |
184 | `ifdef AXIS_FBDIMM_NO_FSR | |
185 | `else | |
186 | .link_clk (link_clk), | |
187 | `endif | |
188 | .dram_clk ( dram_clk), | |
189 | .dram_2x_clk ( dram_2x_clk), | |
190 | .command_in ( command_in), | |
191 | .command_type ( command_type), | |
192 | .ddrio_nbencode_rd ( ddrio_nbencode_rd ), | |
193 | .command_rdy ( command_rdy ), | |
194 | .data_in ( data_in), | |
195 | .data_out ( data_out), | |
196 | .get_wbuffer_data ( get_wbuffer_data), | |
197 | .put_rbuffer_data ( put_rbuffer_data), | |
198 | .dcalcsr ( dcalcsr), | |
199 | .frm_boundary ( frm_boundary), | |
200 | .dcaladdr ( dcaladdr), | |
201 | .ch_state ( ch_state), | |
202 | .drc ( drc), | |
203 | .reset (~reset_n), | |
204 | .init ( amb.init), | |
205 | .cke_rank0 ( cke_rank0), | |
206 | .cke_rank1 ( cke_rank1), | |
207 | .bcs ( bcs), | |
208 | .bras ( bras), | |
209 | .bcas ( bcas), | |
210 | .bwe ( bwe), | |
211 | .ba ( ba), | |
212 | .addr ( addr), | |
213 | .clear_dcalcsr31 ( clear_dcalcsr31), | |
214 | .dq ( dq), | |
215 | .dqs ( dqs), | |
216 | .bdqs ( bdqs), | |
217 | .dm_rdqs ( dm_rdqs), | |
218 | .brdqs ( brdqs), | |
219 | .dqs_in ( dqs[1]), | |
220 | .odt ( odt), | |
221 | .areset ( areset), | |
222 | .term ( term), | |
223 | .drams_on_out ( drams_on), | |
224 | .sb_crc_error ( sb_crc_error), | |
225 | .clk_int ( clk_int), | |
226 | .rs ( rs) | |
227 | `else | |
228 | ddr_io #(DS) dram_io ( | |
229 | `ifdef AXIS_FBDIMM_NO_FSR | |
230 | `else | |
231 | .link_clk ( link_clk), | |
232 | `endif | |
233 | .dram_clk ( dram_clk), | |
234 | .dram_2x_clk ( dram_2x_clk), | |
235 | .command_in ( command_in), | |
236 | .command_type ( command_type ), | |
237 | .command_rdy ( command_rdy ), | |
238 | .data_in ( data_in), | |
239 | .data_out ( data_out), | |
240 | .get_wbuffer_data ( get_wbuffer_data), | |
241 | .put_rbuffer_data ( put_rbuffer_data), | |
242 | .ch_state ( ch_state), | |
243 | .dcalcsr ( dcalcsr), | |
244 | .dcaladdr ( dcaladdr), | |
245 | .frm_boundary ( frm_boundary), | |
246 | .clear_dcalcsr31 ( clear_dcalcsr31), | |
247 | .ddrio_nbencode_rd ( ddrio_nbencode_rd ), | |
248 | .drc ( drc), | |
249 | .reset ( reset), | |
250 | .init ( amb.init), | |
251 | .cke_rank0 ( cke_rank0), | |
252 | .cke_rank1 ( cke_rank1), | |
253 | .bcs ( bcs), | |
254 | .bras ( bras), | |
255 | .bcas ( bcas), | |
256 | .bwe ( bwe), | |
257 | .ba ( ba), | |
258 | .addr ( addr), | |
259 | .dq ( dq), | |
260 | .dqs ( dqs), | |
261 | .bdqs ( bdqs), | |
262 | .dm_rdqs ( dm_rdqs), | |
263 | .brdqs ( brdqs), | |
264 | .dqs_in ( dqs[1]), | |
265 | .odt ( odt), | |
266 | .drams_on_out ( drams_on), | |
267 | .areset ( areset), | |
268 | .term ( term), | |
269 | .sb_crc_error ( sb_crc_error), | |
270 | .clk_int ( clk_int), | |
271 | .rs (rs) | |
272 | `endif | |
273 | ||
274 | ); | |
275 | ||
276 | ||
277 | ||
278 | // DRAM CODE | |
279 | ||
280 | // Dram devices for X4 configuration | |
281 | //`ifdef X4 | |
282 | ||
283 | `ifdef ZEROIN_DDR2_DRAM_MONITOR_X | |
284 | ||
285 | zi_cw_ddr2_sdram_2_0_monitor #( 1, /* Constraints mode */ | |
286 | 0, /* CONTROLLER SIDE */ | |
287 | 15, /* ROW_ADDRESS_WIDTH */ | |
288 | 4, /* DATA_BUS_WITDH */ | |
289 | 1, /* DLL_TRACKING_ENABLE */ | |
290 | 6, /* TRAS */ | |
291 | 2, /* TRCD */ | |
292 | 1, /* TRP */ | |
293 | 2, /* TRRD */ | |
294 | 2, /* TCCD */ | |
295 | 4, /* TRTW */ | |
296 | 1, /* TWTR */ | |
297 | 2, /* TWR */ | |
298 | 9, /* TRFC */ | |
299 | 10, /* TXSNR */ | |
300 | 200, /* TXSRD */ | |
301 | 2, /* TMRD */ | |
302 | 12, /* AUTOPRECHARGE_ENABLE_ADDRESS_BIT */ | |
303 | 1, /* READ_BEFORE_WRITE_CHECK_ENABLE */ | |
304 | 2, /* TXP */ | |
305 | 2, /* TXARD */ | |
306 | 3, /* BANK_ADDRESS_WITDH */ | |
307 | 1, /* ENABLE_PRECHARGE_TO_IDLE_BANK */ | |
308 | 0 /* BYPASS_INIT */ ) | |
309 | ZeroIn_DDR2_MON ( .ck (dram_clk), | |
310 | .ck_n (~dram_clk), | |
311 | .reset (~reset_n), | |
312 | .areset (~reset_n), | |
313 | .cke (cke_rank0[1]), | |
314 | .cs_n (bcs[1]), | |
315 | .ras_n (bras[1]), | |
316 | .cas_n (bcas[1]), | |
317 | .we_n (bwe[1]), | |
318 | .ba (ba), | |
319 | .a (addr), | |
320 | .dq (dq[7:0]), | |
321 | .dqs (dqs), | |
322 | .ldqs (), | |
323 | .ldm (), | |
324 | .udqs (), | |
325 | .udm (), | |
326 | .mode_register_in ()); | |
327 | ||
328 | `endif | |
329 | ||
330 | `ifdef AXIS_DDR2_MODEL | |
331 | `else | |
332 | ||
333 | `ifdef DRAM_SAT | |
334 | wire[7:0] cs_sel; | |
335 | reg [7:0] cs_sel_reg; | |
336 | assign cs_sel = cs_sel_reg; | |
337 | ||
338 | initial begin | |
339 | if ( $test$plusargs("fbdimm0_disable") && ( DS == 0 ) ) | |
340 | cs_sel_reg = 8'b11111110; | |
341 | if ( $test$plusargs("fbdimm1_disable") && ( DS == 1 ) ) | |
342 | cs_sel_reg = 8'b11111101; | |
343 | if ( $test$plusargs("fbdimm2_disable") && ( DS == 2 ) ) | |
344 | cs_sel_reg = 8'b11111011; | |
345 | if ( $test$plusargs("fbdimm3_disable") && ( DS == 3 ) ) | |
346 | cs_sel_reg = 8'b11110111; | |
347 | if ( $test$plusargs("fbdimm4_disable") && ( DS == 4 ) ) | |
348 | cs_sel_reg = 8'b11101111; | |
349 | if ( $test$plusargs("fbdimm5_disable") && ( DS == 5 ) ) | |
350 | cs_sel_reg = 8'b11011111; | |
351 | if ( $test$plusargs("fbdimm6_disable") && ( DS == 6 ) ) | |
352 | cs_sel_reg = 8'b10111111; | |
353 | if ( $test$plusargs("fbdimm7_disable") && ( DS == 7 ) ) | |
354 | cs_sel_reg = 8'b01111111; | |
355 | else | |
356 | cs_sel_reg = 8'b00000000; | |
357 | ||
358 | end | |
359 | ||
360 | `ifdef X8 | |
361 | fbdimm_DIMMx8 fbdimm_DIMMx8 | |
362 | `else | |
363 | fbdimm_DIMMx4 fbdimm_DIMMx4 | |
364 | `endif | |
365 | (.CK (dram_clk), | |
366 | .bCK (~dram_clk), | |
367 | .CKE ( cke_rank0[18:1]), | |
368 | .bCS (bcs[18:1] | (!drams_on ? bcs[18:1] : {18{rs}}) ), | |
369 | .bRAS (bras[18:1]), | |
370 | .bCAS (bcas[18:1]), | |
371 | .bWE (bwe[18:1]), | |
372 | .BA (ba), | |
373 | .DQ (dq[63:0]), | |
374 | .CB (dq[71:64]), | |
375 | .DQS (dqs[8:0]), | |
376 | .bDQS (bdqs[8:0]), | |
377 | .DM_RDQS (dqs[17:9]), | |
378 | .bRDQS (bdqs[8:0]), | |
379 | .Addr (addr), | |
380 | .ODT (odt[18:1]), | |
381 | .term (term[18:1]), | |
382 | .CS_SEL (cs_sel[7:0])); | |
383 | ||
384 | ||
385 | `ifdef DDR2_MONITOR_ON | |
386 | ||
387 | reg dram_areset; | |
388 | wire dram_mon_areset = dram_areset; | |
389 | ||
390 | initial dram_areset=1; | |
391 | ||
392 | always@(posedge dram_clk) | |
393 | dram_areset <= reset; | |
394 | ||
395 | ddr2_monitor #( 2, /* tMRD */ | |
396 | 15, /* tRFC */ | |
397 | 200, /* tXSRD */ | |
398 | 10, /* tXSNR */ | |
399 | 9, /* tRAS */ | |
400 | 3, /* tCAS */ | |
401 | 3, /* tRCD */ | |
402 | 2, /* tCCD */ | |
403 | 12, /* tRC */ | |
404 | 2, /* tRRD */ | |
405 | 2, /* tWTR */ | |
406 | 4, /* tRTW */ | |
407 | 3, /* tWR */ | |
408 | 2, /* tXP */ | |
409 | 2, /* tXARD */ | |
410 | 3, /* tRP */ | |
411 | 9, /* tFAW */ | |
412 | 16, /* ROW_WIDTH */ | |
413 | 64, /* DATA WIDTH */ | |
414 | 1, /* DATA_MASK_WIDTH */ | |
415 | 1, /* DLL_TRACK_EN */ | |
416 | 1, /* BURST_TYPE_SEQ */ | |
417 | 4, /* BURST_LENGTH */ | |
418 | 0, /* ADDITIVE LATENCY */ | |
419 | 2 /* DATA_STROBE_NUM */ ) | |
420 | custom_ddr2_monitor( | |
421 | .addr (addr), | |
422 | .ba (ba), | |
423 | .cas_bar ( bcas[1]), | |
424 | .cke (cke_rank0[1]), | |
425 | .ck (dram_clk), | |
426 | .ck_bar (~dram_clk), | |
427 | .ras_bar (bras[1]), | |
428 | .we_bar (bwe[1]), | |
429 | .dqs (dqs[8:0]), | |
430 | .dq (dq[63:0]), | |
431 | .odt (odt[1]), | |
432 | .areset (dram_mon_areset), | |
433 | .cs_bar (cs_sel | {8{rs}} ), | |
434 | .dqs_bar (bdqs) | |
435 | ); | |
436 | `endif | |
437 | ||
438 | `ifdef DRAM_SAT // to be removed later | |
439 | ||
440 | amb_dram_err_inject amb_dram_err_inj (.clk (dram_clk), | |
441 | .int_clk (~dram_clk), | |
442 | .DRAM_RST_L (reset), | |
443 | .DRAM_CS_L (cs_sel[7:0]), | |
444 | .DRAM_BA (ba), | |
445 | .DRAM_RAS_L (bras[1]), | |
446 | .DRAM_CAS_L (bcas[1]), | |
447 | .DRAM_WE_L (bwe[1]), | |
448 | .DRAM_DQ (dq[63:0]), | |
449 | .DRAM_DQS (dqs[8:0]), | |
450 | .CHNL_ERR_ENABLE (err_en), | |
451 | .DRAM_CB (dq[71:64]), | |
452 | .AMB_L0_STATE (~amb.init)); | |
453 | ||
454 | ||
455 | `endif | |
456 | ||
457 | `ifdef STACK_DIMM | |
458 | ||
459 | `ifdef X8 | |
460 | fbdimm_DIMMx8 fbdimm_DIMMx8_rank2 | |
461 | `else | |
462 | fbdimm_DIMMx4 fbdimm_DIMMx4_rank2 | |
463 | `endif | |
464 | (.CK (dram_clk), | |
465 | .bCK (~dram_clk), | |
466 | .CKE (cke_rank1[18:1]), | |
467 | .bCS (bcs[18:1] | (!drams_on ? bcs[18:1] : {18{~rs}}) ), | |
468 | .bRAS (bras[18:1]), | |
469 | .bCAS (bcas[18:1]), | |
470 | .bWE (bwe[18:1]), | |
471 | .BA (ba), | |
472 | .DQ (dq[63:0]), | |
473 | .CB (dq[71:64]), | |
474 | .DQS (dqs[8:0]), | |
475 | .bDQS (bdqs[8:0]), | |
476 | .DM_RDQS (dqs[17:9]), | |
477 | .bRDQS (bdqs[8:0]), | |
478 | .Addr (addr), | |
479 | .ODT (odt[18:1]), | |
480 | .term (term[18:1]), | |
481 | .CS_SEL (cs_sel[7:0])); | |
482 | ||
483 | `endif // STACK DIMM | |
484 | ||
485 | ||
486 | //`endif // X4 | |
487 | `endif // DRAM_SAT | |
488 | `endif // AXIS_DDR2_MODEL | |
489 | ||
490 | ||
491 | ||
492 | `ifdef STINGRAY | |
493 | fbdimm_tasks fbdimm_tasks(); | |
494 | `endif | |
495 | ||
496 | ||
497 | ||
498 | ||
499 | `ifdef AXIS_FBDIMM_HW | |
500 | `else | |
501 | `ifdef STINGRAY | |
502 | `else | |
503 | // Initialization and reset sequence | |
504 | initial begin | |
505 | reset_r = 1'b1; | |
506 | #100; | |
507 | reset_r = 1'b0; | |
508 | end | |
509 | `endif //ST | |
510 | `endif // !AXIS_FBDIMM_HW | |
511 | ||
512 | endmodule | |
513 |