| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: ccu_cmp_dr_sync.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | `timescale 1 ns / 1ps |
| 36 | |
| 37 | module ccu_cmp_dr_sync ( |
| 38 | align, |
| 39 | align_shift, |
| 40 | ccu_serdes_dtm, |
| 41 | clk, |
| 42 | ratio, |
| 43 | pulse, |
| 44 | rst_n |
| 45 | ); |
| 46 | |
| 47 | |
| 48 | input ccu_serdes_dtm; |
| 49 | input align; |
| 50 | input [1:0] align_shift; |
| 51 | input clk; |
| 52 | input rst_n; |
| 53 | input [4:0] ratio; |
| 54 | output pulse; |
| 55 | |
| 56 | wire ccu_serdes_dtm; |
| 57 | wire align; |
| 58 | wire [1:0] align_shift; |
| 59 | wire clk; |
| 60 | wire rst_n; |
| 61 | wire [4:0] ratio; |
| 62 | wire [4:0] func_ratio; |
| 63 | wire [4:0] dtm_ratio; |
| 64 | wire pulse; |
| 65 | |
| 66 | reg [4:0] cnt; |
| 67 | reg [3:0] agg_k; // aggregate for k=0,1,2,3 |
| 68 | reg [3:0] dtm_agg_k; // aggregate for k=0,1,2,3 for DTM |
| 69 | |
| 70 | reg pulse_minus1; |
| 71 | reg pulse_nom; |
| 72 | reg pulse_plus1; |
| 73 | |
| 74 | |
| 75 | // only one set of ratios is active |
| 76 | assign func_ratio = ccu_serdes_dtm ? 5'b0 : ratio; |
| 77 | assign dtm_ratio = ccu_serdes_dtm ? ratio : 5'b0 ; |
| 78 | |
| 79 | // this causes the aggregates of that set to be quiescent |
| 80 | |
| 81 | |
| 82 | assign pulse = (align_shift == 2'b10) ? pulse_minus1 : |
| 83 | (align_shift == 2'b01) ? pulse_plus1 : pulse_nom ; |
| 84 | |
| 85 | |
| 86 | always @ (posedge clk) begin |
| 87 | if (!rst_n) begin |
| 88 | pulse_minus1 <= 1'b0; |
| 89 | pulse_nom <= 1'b0; |
| 90 | pulse_plus1 <= 1'b0; |
| 91 | end else begin |
| 92 | pulse_minus1 <= (| (agg_k | dtm_agg_k)) ; // pulse is OR of any pulse @k |
| 93 | pulse_nom <= pulse_minus1; // code ensures only one set of |
| 94 | pulse_plus1 <= pulse_nom; // pulses is active at any time |
| 95 | end |
| 96 | end |
| 97 | |
| 98 | |
| 99 | // pulse counter starting from align |
| 100 | always @ (posedge clk) begin |
| 101 | if (!rst_n) |
| 102 | cnt <= 5'h00; |
| 103 | else begin |
| 104 | if (align == 1'b1) |
| 105 | cnt <= 5'h00; |
| 106 | else |
| 107 | cnt <= cnt + 1'b1; |
| 108 | end |
| 109 | end |
| 110 | |
| 111 | // PULSE POSITIONS @ CCU BOUNDARY |
| 112 | // ============================== |
| 113 | // |
| 114 | // FUNCTIONAL MODE |
| 115 | // |
| 116 | // cmp:dr Binary K -> slow clk cycles |
| 117 | // ratio Div4 0 1 2 3 |
| 118 | // ----------------------------------------- |
| 119 | // 2.00 0100_0 7 1 3 5 |
| 120 | // 2.25 0100_1 0 2 5 7 |
| 121 | // 2.50 0101_0 1 4 6 9 |
| 122 | // 2.75 0101_1 2 5 8 0 |
| 123 | // 3.00 0110_0 3 6 9 0 |
| 124 | // 3.25 0110_1 5 8 11 1 |
| 125 | // 3.50 0111_0 6 9 13 2 |
| 126 | // 3.75 0111_1 7 11 14 3 |
| 127 | // 4.00 1000_0 8 12 0 4 |
| 128 | // 4.25 1000_1 9 13 1 5 |
| 129 | // 4.50 1001_0 10 15 1 6 |
| 130 | // 4.75 1001_1 11 16 2 7 |
| 131 | // 5.00 1010_0 12 17 2 7 |
| 132 | // 5.25 1010_1 14 19 3 8 |
| 133 | // |
| 134 | // DTM |
| 135 | // |
| 136 | // cmp:dr Binary K -> slow clk cycles |
| 137 | // ratio Div2 0 1 2 3 |
| 138 | // ----------------------------------------- |
| 139 | // 8.00 0111 2 2 2 2 |
| 140 | // 11.00 1010 6 6 6 6 |
| 141 | // 15.00 1110 12 12 12 12 |
| 142 | |
| 143 | |
| 144 | // pulse gen from counter (combo logic) |
| 145 | // Functional mode |
| 146 | always @ (cnt or func_ratio) begin |
| 147 | case (func_ratio) |
| 148 | 5'b01000: // 010 00 => 2.00 |
| 149 | case (cnt) |
| 150 | 5'd07: agg_k = 4'b0001; |
| 151 | 5'd01: agg_k = 4'b0010; |
| 152 | 5'd03: agg_k = 4'b0100; |
| 153 | 5'd05: agg_k = 4'b1000; |
| 154 | default: agg_k = 4'h0; |
| 155 | endcase |
| 156 | 5'b01001: // 010 01 => 2.25 |
| 157 | case (cnt) |
| 158 | 5'd00: agg_k = 4'b0001; |
| 159 | 5'd02: agg_k = 4'b0010; |
| 160 | 5'd05: agg_k = 4'b0100; |
| 161 | 5'd07: agg_k = 4'b1000; |
| 162 | default: agg_k = 4'h0; |
| 163 | endcase |
| 164 | 5'b01010: // 010 10 => 2.50 |
| 165 | case (cnt) |
| 166 | 5'd01: agg_k = 4'b0001; |
| 167 | 5'd04: agg_k = 4'b0010; |
| 168 | 5'd06: agg_k = 4'b0100; |
| 169 | 5'd09: agg_k = 4'b1000; |
| 170 | default: agg_k = 4'h0; |
| 171 | endcase |
| 172 | 5'b01011: // 010 11 => 2.75 |
| 173 | case (cnt) |
| 174 | 5'd02: agg_k = 4'b0001; |
| 175 | 5'd05: agg_k = 4'b0010; |
| 176 | 5'd08: agg_k = 4'b0100; |
| 177 | 5'd00: agg_k = 4'b1000; |
| 178 | default: agg_k = 4'h0; |
| 179 | endcase |
| 180 | 5'b01100: // 011 00 => 3.00 |
| 181 | case (cnt) |
| 182 | 5'd03: agg_k = 4'b0001; |
| 183 | 5'd06: agg_k = 4'b0010; |
| 184 | 5'd09: agg_k = 4'b0100; |
| 185 | 5'd00: agg_k = 4'b1000; |
| 186 | default: agg_k = 4'h0; |
| 187 | endcase |
| 188 | 5'b01101: // 011 01 => 3.25 |
| 189 | case (cnt) |
| 190 | 5'd05: agg_k = 4'b0001; |
| 191 | 5'd08: agg_k = 4'b0010; |
| 192 | 5'd11: agg_k = 4'b0100; |
| 193 | 5'd01: agg_k = 4'b1000; |
| 194 | default: agg_k = 4'h0; |
| 195 | endcase |
| 196 | 5'b01110: // 011 10 => 3.50 |
| 197 | case (cnt) |
| 198 | 5'd06: agg_k = 4'b0001; |
| 199 | 5'd09: agg_k = 4'b0010; |
| 200 | 5'd13: agg_k = 4'b0100; |
| 201 | 5'd02: agg_k = 4'b1000; |
| 202 | default: agg_k = 4'h0; |
| 203 | endcase |
| 204 | 5'b01111: // 011 11 => 3.75 |
| 205 | case (cnt) |
| 206 | 5'd07: agg_k = 4'b0001; |
| 207 | 5'd11: agg_k = 4'b0010; |
| 208 | 5'd14: agg_k = 4'b0100; |
| 209 | 5'd03: agg_k = 4'b1000; |
| 210 | default: agg_k = 4'h0; |
| 211 | endcase |
| 212 | 5'b10000: // 100 00 => 4.00 |
| 213 | case (cnt) |
| 214 | 5'd08: agg_k = 4'b0001; |
| 215 | 5'd12: agg_k = 4'b0010; |
| 216 | 5'd00: agg_k = 4'b0100; |
| 217 | 5'd04: agg_k = 4'b1000; |
| 218 | default: agg_k = 4'h0; |
| 219 | endcase |
| 220 | 5'b10001: // 100 01 => 4.25 |
| 221 | case (cnt) |
| 222 | 5'd09: agg_k = 4'b0001; |
| 223 | 5'd13: agg_k = 4'b0010; |
| 224 | 5'd01: agg_k = 4'b0100; |
| 225 | 5'd05: agg_k = 4'b1000; |
| 226 | default: agg_k = 4'h0; |
| 227 | endcase |
| 228 | 5'b10010: // 100 10 => 4.50 |
| 229 | case (cnt) |
| 230 | 5'd10: agg_k = 4'b0001; |
| 231 | 5'd15: agg_k = 4'b0010; |
| 232 | 5'd01: agg_k = 4'b0100; |
| 233 | 5'd06: agg_k = 4'b1000; |
| 234 | default: agg_k = 4'h0; |
| 235 | endcase |
| 236 | 5'b10011: // 100 11 => 4.75 |
| 237 | case (cnt) |
| 238 | 5'd11: agg_k = 4'b0001; |
| 239 | 5'd16: agg_k = 4'b0010; |
| 240 | 5'd02: agg_k = 4'b0100; |
| 241 | 5'd07: agg_k = 4'b1000; |
| 242 | default: agg_k = 4'h0; |
| 243 | endcase |
| 244 | 5'b10100: // 101 00 => 5.00 |
| 245 | case (cnt) |
| 246 | 5'd12: agg_k = 4'b0001; |
| 247 | 5'd17: agg_k = 4'b0010; |
| 248 | 5'd02: agg_k = 4'b0100; |
| 249 | 5'd07: agg_k = 4'b1000; |
| 250 | default: agg_k = 4'h0; |
| 251 | endcase |
| 252 | 5'b10101: // 101 01 => 5.25 |
| 253 | case (cnt) |
| 254 | 5'd14: agg_k = 4'b0001; |
| 255 | 5'd19: agg_k = 4'b0010; |
| 256 | 5'd03: agg_k = 4'b0100; |
| 257 | 5'd08: agg_k = 4'b1000; |
| 258 | default: agg_k = 4'h0; |
| 259 | endcase |
| 260 | default: agg_k = 4'h0; // no pulses |
| 261 | endcase |
| 262 | end |
| 263 | |
| 264 | |
| 265 | |
| 266 | // pulse gen from counter (combo logic) |
| 267 | // DTM |
| 268 | always @ (cnt or dtm_ratio) begin |
| 269 | case (dtm_ratio) |
| 270 | 5'b00111: // 0_0111 => 8 |
| 271 | case (cnt) |
| 272 | 5'd02: dtm_agg_k = 4'b0001; // same cnt applies to k=1,2,3 |
| 273 | default: dtm_agg_k = 4'h0; |
| 274 | endcase |
| 275 | 5'b01010: // 0_1010 => 11 |
| 276 | case (cnt) |
| 277 | 5'd06: dtm_agg_k = 4'b0001; // same cnt applies to k=1,2,3 |
| 278 | default: dtm_agg_k = 4'h0; |
| 279 | endcase |
| 280 | 5'b01110: // 0_1110 => 15 |
| 281 | case (cnt) |
| 282 | 5'd12: dtm_agg_k = 4'b0001; // same cnt applies to k=1,2,3 |
| 283 | default: dtm_agg_k = 4'h0; |
| 284 | endcase |
| 285 | default: dtm_agg_k = 4'h0; // no pulses |
| 286 | |
| 287 | endcase |
| 288 | end |
| 289 | |
| 290 | |
| 291 | endmodule |
| 292 | |