| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: ccu_hm_top.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module ccu_hm_top ( |
| 36 | ref_clk, |
| 37 | cmp_pll_clk_l, |
| 38 | shift_amt, |
| 39 | dr_shift_amt, |
| 40 | rst_n, |
| 41 | rst_out_n, |
| 42 | div_msb, |
| 43 | pulse_out |
| 44 | ); |
| 45 | |
| 46 | input ref_clk; |
| 47 | input cmp_pll_clk_l; |
| 48 | input [4:0] shift_amt; |
| 49 | input [4:0] dr_shift_amt; |
| 50 | input rst_n; |
| 51 | output rst_out_n; |
| 52 | input div_msb; |
| 53 | output pulse_out; |
| 54 | |
| 55 | wire ref_clk; |
| 56 | wire cmp_pll_clk_l; |
| 57 | wire [4:0] shift_amt; |
| 58 | wire [4:0] dr_shift_amt; |
| 59 | wire rst_n; |
| 60 | wire rst_out_n; |
| 61 | wire div_msb; |
| 62 | wire pulse_out; |
| 63 | |
| 64 | |
| 65 | wire pll_l1clk; |
| 66 | wire pll_buf_clk; |
| 67 | wire pll_div4_msb; |
| 68 | wire aligned; |
| 69 | wire aligned_tmp; |
| 70 | wire dft_rst_a_l; |
| 71 | |
| 72 | assign pll_div4_msb = div_msb; |
| 73 | assign pulse_out = aligned; |
| 74 | assign rst_out_n = dft_rst_a_l; |
| 75 | |
| 76 | wire rst = ~rst_n; |
| 77 | |
| 78 | // *********************************************** |
| 79 | // ref-clk/cmp clk align detection |
| 80 | // *********************************************** |
| 81 | ccu_hm_align_det align_det ( |
| 82 | .ref_clk (ref_clk), |
| 83 | .fast_clk (pll_l1clk), |
| 84 | .rst_n (rst_n), |
| 85 | .aligned (aligned_shft) |
| 86 | ); |
| 87 | |
| 88 | // *********************************************** |
| 89 | // shift align pulse+3 cycle to rising edges |
| 90 | // *********************************************** |
| 91 | ccu_hm_pulse_shift align_pulse_shift ( |
| 92 | .rst_n (rst_n), |
| 93 | .clk (pll_l1clk), |
| 94 | .shift (shift_amt), |
| 95 | .pulse_in (aligned_shft), |
| 96 | .pulse_out (aligned_tmp) |
| 97 | ); |
| 98 | |
| 99 | my_msff_arst_4x output_stg_eco2 ( // eco 2.2 |
| 100 | .l1clk (pll_l1clk), |
| 101 | .d(aligned_tmp), |
| 102 | .q(aligned), |
| 103 | .siclk(1'b0), |
| 104 | .soclk(1'b0), |
| 105 | .si(1'b0), |
| 106 | .reset (rst), |
| 107 | .so() |
| 108 | ); |
| 109 | |
| 110 | // *********************************************** |
| 111 | // generate reset to pll for d4 output (dr_clk) |
| 112 | // *********************************************** |
| 113 | ccu_hm_dr_reset_gen dr_reset_gen ( |
| 114 | .rst_out_n (dft_rst_a_l), |
| 115 | .clk (pll_l1clk), |
| 116 | .shift_amt (dr_shift_amt), |
| 117 | .aligned (aligned), |
| 118 | .div_msb (pll_div4_msb), |
| 119 | .rst_n (rst_n) |
| 120 | ); |
| 121 | |
| 122 | // *********************************************************** |
| 123 | // Inversion & L1 header - pll l1clk |
| 124 | // *********************************************************** |
| 125 | // |
| 126 | cl_a1_inv_32x pll_clk_inv ( .in (cmp_pll_clk_l), .out (pll_l1clk) ); |
| 127 | |
| 128 | endmodule // ccu_hm_top |