| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_cb0.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_cb0 ( |
| 36 | dmu_cb0_run, |
| 37 | dmu_cb0_addr, |
| 38 | dmu_cb0_wdata_key, |
| 39 | dmu_cb0_mmu_vtb_wr_en, |
| 40 | dmu_cb0_mmu_vtb_rd_en, |
| 41 | dmu_cb0_mmu_vtb_lkup_en, |
| 42 | dmu_cb0_mmu_ptb_wr_en, |
| 43 | dmu_cb0_mmu_ptb_rd_en, |
| 44 | dmu_cb0_mmu_ptb_lkup_en, |
| 45 | dmu_cb0_hld, |
| 46 | dmu_cb0_done, |
| 47 | dmu_cb0_fail, |
| 48 | scan_out, |
| 49 | l1clk, |
| 50 | scan_in, |
| 51 | tcu_aclk, |
| 52 | tcu_bclk, |
| 53 | rst_, |
| 54 | tcu_dmu_cb0_start, |
| 55 | dmu_cb0_bisi_mode, |
| 56 | dmu_cb0_user_mode, |
| 57 | mmu_vtb_read_data, |
| 58 | mmu_ptb_read_data, |
| 59 | mmu_vtb_hit, |
| 60 | mmu_ptb_hit); |
| 61 | wire siclk; |
| 62 | wire soclk; |
| 63 | wire reset; |
| 64 | wire config_reg_scanin; |
| 65 | wire config_reg_scanout; |
| 66 | wire [7:0] config_in; |
| 67 | wire [7:0] config_out; |
| 68 | wire start_transition; |
| 69 | wire reset_engine; |
| 70 | wire mbist_user_loop_mode; |
| 71 | wire mbist_done; |
| 72 | wire run; |
| 73 | wire bisi; |
| 74 | wire user_mode; |
| 75 | wire user_data_mode; |
| 76 | wire user_addr_mode; |
| 77 | wire user_loop_mode; |
| 78 | wire ten_n_mode; |
| 79 | wire mbist_user_data_mode; |
| 80 | wire mbist_user_addr_mode; |
| 81 | wire mbist_ten_n_mode; |
| 82 | wire user_data_reg_scanin; |
| 83 | wire user_data_reg_scanout; |
| 84 | wire [7:0] user_data_in; |
| 85 | wire [7:0] user_data_out; |
| 86 | wire user_start_addr_reg_scanin; |
| 87 | wire user_start_addr_reg_scanout; |
| 88 | wire [5:0] user_start_addr_in; |
| 89 | wire [5:0] user_start_addr; |
| 90 | wire user_stop_addr_reg_scanin; |
| 91 | wire user_stop_addr_reg_scanout; |
| 92 | wire [5:0] user_stop_addr_in; |
| 93 | wire [5:0] user_stop_addr; |
| 94 | wire user_incr_addr_reg_scanin; |
| 95 | wire user_incr_addr_reg_scanout; |
| 96 | wire [5:0] user_incr_addr_in; |
| 97 | wire [5:0] user_incr_addr; |
| 98 | wire user_array_sel_reg_scanin; |
| 99 | wire user_array_sel_reg_scanout; |
| 100 | wire user_array_sel_in; |
| 101 | wire user_array_sel; |
| 102 | wire user_cam_mode_reg_scanin; |
| 103 | wire user_cam_mode_reg_scanout; |
| 104 | wire user_cam_mode_in; |
| 105 | wire user_cam_mode; |
| 106 | wire user_cam_select_reg_scanin; |
| 107 | wire user_cam_select_reg_scanout; |
| 108 | wire user_cam_sel_in; |
| 109 | wire user_cam_sel; |
| 110 | wire user_cam_test_select_reg_scanin; |
| 111 | wire user_cam_test_select_reg_scanout; |
| 112 | wire [2:0] user_cam_test_sel_in; |
| 113 | wire [2:0] user_cam_test_sel; |
| 114 | wire user_bisi_wr_reg_scanin; |
| 115 | wire user_bisi_wr_reg_scanout; |
| 116 | wire user_bisi_wr_mode_in; |
| 117 | wire user_bisi_wr_mode; |
| 118 | wire user_bisi_rd_reg_scanin; |
| 119 | wire user_bisi_rd_reg_scanout; |
| 120 | wire user_bisi_rd_mode_in; |
| 121 | wire user_bisi_rd_mode; |
| 122 | wire mbist_user_bisi_wr_mode; |
| 123 | wire mbist_user_bisi_wr_rd_mode; |
| 124 | wire start_transition_reg_scanin; |
| 125 | wire start_transition_reg_scanout; |
| 126 | wire start_transition_piped; |
| 127 | wire run_reg_scanin; |
| 128 | wire run_reg_scanout; |
| 129 | wire run1_reg_scanin; |
| 130 | wire run1_reg_scanout; |
| 131 | wire run1_in; |
| 132 | wire run1_out; |
| 133 | wire run2_reg_scanin; |
| 134 | wire run2_reg_scanout; |
| 135 | wire run2_in; |
| 136 | wire run2_out; |
| 137 | wire run_piped3; |
| 138 | wire msb; |
| 139 | wire addr_reg_scanin; |
| 140 | wire addr_reg_scanout; |
| 141 | wire [5:0] int_address; |
| 142 | wire cambist; |
| 143 | wire [5:0] cam_addr; |
| 144 | wire [5:0] mbist_address; |
| 145 | wire key_reg_scanin; |
| 146 | wire key_reg_scanout; |
| 147 | wire [32:0] mbist_wdata_key; |
| 148 | wire array_write; |
| 149 | wire array_read; |
| 150 | wire [7:0] mbist_wdata; |
| 151 | wire ctest0; |
| 152 | wire ctest2; |
| 153 | wire ctest4; |
| 154 | wire cseq0; |
| 155 | wire ctest1; |
| 156 | wire ctest3; |
| 157 | wire cseq1; |
| 158 | wire crw0; |
| 159 | wire crw1; |
| 160 | wire crw2; |
| 161 | wire crw3; |
| 162 | wire crw4; |
| 163 | wire wr_rd_en_reg_scanin; |
| 164 | wire wr_rd_en_reg_scanout; |
| 165 | wire vtb_wr_en; |
| 166 | wire vtb_rd_en; |
| 167 | wire vtb_lkup_en; |
| 168 | wire ptb_wr_en; |
| 169 | wire ptb_rd_en; |
| 170 | wire ptb_lkup_en; |
| 171 | wire hld_reg_scanin; |
| 172 | wire hld_reg_scanout; |
| 173 | wire mbist_hld; |
| 174 | wire done_reg_scanin; |
| 175 | wire done_reg_scanout; |
| 176 | wire mbist_fail_reg_scanin; |
| 177 | wire mbist_fail_reg_scanout; |
| 178 | wire fail; |
| 179 | wire [32:0] res_read_data; |
| 180 | wire vtb_sel_piped2; |
| 181 | wire read_data_pipe_reg_scanin; |
| 182 | wire read_data_pipe_reg_scanout; |
| 183 | wire [32:0] res_read_data_piped; |
| 184 | wire [63:0] res_hit_data; |
| 185 | wire cam_vtb_sel_piped2; |
| 186 | wire hit_data_pipe_reg_scanin; |
| 187 | wire hit_data_pipe_reg_scanout; |
| 188 | wire [63:0] res_hit_data_piped; |
| 189 | wire control_reg_scanin; |
| 190 | wire control_reg_scanout; |
| 191 | wire [18:0] control_in; |
| 192 | wire [18:0] control_out; |
| 193 | wire bisi_wr_rd; |
| 194 | wire array_sel; |
| 195 | wire [1:0] data_control; |
| 196 | wire address_mix; |
| 197 | wire [3:0] march_element; |
| 198 | wire [5:0] array_address; |
| 199 | wire upaddress_march; |
| 200 | wire [2:0] read_write_control; |
| 201 | wire five_cycle_march; |
| 202 | wire one_cycle_march; |
| 203 | wire increment_addr; |
| 204 | wire [5:0] start_addr; |
| 205 | wire [5:0] next_array_address; |
| 206 | wire next_upaddr_march; |
| 207 | wire next_downaddr_march; |
| 208 | wire [5:0] stop_addr; |
| 209 | wire [6:0] overflow_addr; |
| 210 | wire [5:0] incr_addr; |
| 211 | wire overflow; |
| 212 | wire [6:0] compare_addr; |
| 213 | wire [5:0] add; |
| 214 | wire [5:0] adj_address; |
| 215 | wire increment_march_elem; |
| 216 | wire next_array_sel; |
| 217 | wire [1:0] next_data_control; |
| 218 | wire next_address_mix; |
| 219 | wire [3:0] next_march_element; |
| 220 | wire true_data; |
| 221 | wire [7:0] data_pattern; |
| 222 | wire done_counter_reg_scanin; |
| 223 | wire done_counter_reg_scanout; |
| 224 | wire [2:0] done_counter_in; |
| 225 | wire [2:0] done_counter_out; |
| 226 | wire final_msb; |
| 227 | wire cam_msb; |
| 228 | wire vtb_sel; |
| 229 | wire ptb_sel; |
| 230 | wire cam_vtb_sel; |
| 231 | wire cam_wr_en; |
| 232 | wire cam_ptb_sel; |
| 233 | wire cam_array_sel; |
| 234 | wire cam_lkup_en; |
| 235 | wire cam_cntl_reg_scanin; |
| 236 | wire cam_cntl_reg_scanout; |
| 237 | wire [14:0] cam_in; |
| 238 | wire [14:0] cam_out; |
| 239 | wire [2:0] ctest; |
| 240 | wire cseq; |
| 241 | wire [2:0] crw; |
| 242 | wire [14:0] qual_cam; |
| 243 | wire next_cam_array_sel; |
| 244 | wire [2:0] next_ctest; |
| 245 | wire [5:0] next_cam_addr; |
| 246 | wire [2:0] next_crw; |
| 247 | wire addr_pipe_reg1_scanin; |
| 248 | wire addr_pipe_reg1_scanout; |
| 249 | wire [5:0] addr_pipe_reg1_in; |
| 250 | wire [5:0] addr_pipe_out1; |
| 251 | wire addr_pipe_reg2_scanin; |
| 252 | wire addr_pipe_reg2_scanout; |
| 253 | wire [5:0] addr_pipe_reg2_in; |
| 254 | wire [5:0] addr_pipe_out2; |
| 255 | wire [5:0] dmu_cb0_piped_addr; |
| 256 | wire data_pipe_reg1_scanin; |
| 257 | wire data_pipe_reg1_scanout; |
| 258 | wire [7:0] date_pipe_reg1_in; |
| 259 | wire [7:0] data_pipe_out1; |
| 260 | wire data_pipe_reg2_scanin; |
| 261 | wire data_pipe_reg2_scanout; |
| 262 | wire [7:0] date_pipe_reg2_in; |
| 263 | wire [7:0] data_pipe_out2; |
| 264 | wire [7:0] dmu_cb0_piped_data; |
| 265 | wire vtb_sel_pipe_reg1_scanin; |
| 266 | wire vtb_sel_pipe_reg1_scanout; |
| 267 | wire vtb_sel_pipe_reg1_in; |
| 268 | wire vtb_sel_piped; |
| 269 | wire vtb_sel_pipe_reg2_scanin; |
| 270 | wire vtb_sel_pipe_reg2_scanout; |
| 271 | wire vtb_sel_pipe_reg2_in; |
| 272 | wire vtb_ren_pipe_reg1_scanin; |
| 273 | wire vtb_ren_pipe_reg1_scanout; |
| 274 | wire vtb_ren_pipe_reg1_in; |
| 275 | wire vtb_rd_en_piped; |
| 276 | wire vtb_ren_pipe_reg2_scanin; |
| 277 | wire vtb_ren_pipe_reg2_scanout; |
| 278 | wire vtb_ren_pipe_reg2_in; |
| 279 | wire vtb_rd_en_piped2; |
| 280 | wire ptb_ren_pipe_reg1_scanin; |
| 281 | wire ptb_ren_pipe_reg1_scanout; |
| 282 | wire ptb_ren_pipe_reg1_in; |
| 283 | wire ptb_rd_en_piped; |
| 284 | wire ptb_ren_pipe_reg2_scanin; |
| 285 | wire ptb_ren_pipe_reg2_scanout; |
| 286 | wire ptb_ren_pipe_reg2_in; |
| 287 | wire ptb_rd_en_piped2; |
| 288 | wire cam_vtb_sel_pipe_reg1_scanin; |
| 289 | wire cam_vtb_sel_pipe_reg1_scanout; |
| 290 | wire cam_vtb_sel_pipe_reg1_in; |
| 291 | wire cam_vtb_sel_piped; |
| 292 | wire cam_vtb_sel_pipe_reg2_scanin; |
| 293 | wire cam_vtb_sel_pipe_reg2_scanout; |
| 294 | wire cam_vtb_sel_pipe_reg2_in; |
| 295 | wire vtb_lkup_en_pipe_reg1_scanin; |
| 296 | wire vtb_lkup_en_pipe_reg1_scanout; |
| 297 | wire vtb_lkup_en_pipe_reg1_in; |
| 298 | wire vtb_lkup_en_piped; |
| 299 | wire vtb_lkup_en_pipe_reg2_scanin; |
| 300 | wire vtb_lkup_en_pipe_reg2_scanout; |
| 301 | wire vtb_lkup_en_pipe_reg2_in; |
| 302 | wire vtb_lkup_en_piped2; |
| 303 | wire ptb_lkup_en_pipe_reg1_scanin; |
| 304 | wire ptb_lkup_en_pipe_reg1_scanout; |
| 305 | wire ptb_lkup_en_pipe_reg1_in; |
| 306 | wire ptb_lkup_en_piped; |
| 307 | wire ptb_lkup_en_pipe_reg2_scanin; |
| 308 | wire ptb_lkup_en_pipe_reg2_scanout; |
| 309 | wire ptb_lkup_en_pipe_reg2_in; |
| 310 | wire ptb_lkup_en_piped2; |
| 311 | wire ctest_pipe_reg1_scanin; |
| 312 | wire ctest_pipe_reg1_scanout; |
| 313 | wire [2:0] ctest_pipe_reg1_in; |
| 314 | wire [2:0] ctest_pipe_out1; |
| 315 | wire ctest_pipe_reg2_scanin; |
| 316 | wire ctest_pipe_reg2_scanout; |
| 317 | wire [2:0] ctest_pipe_reg2_in; |
| 318 | wire [2:0] ctest_pipe_out2; |
| 319 | wire ctest_pipe_reg3_scanin; |
| 320 | wire ctest_pipe_reg3_scanout; |
| 321 | wire [2:0] ctest_pipe_reg3_in; |
| 322 | wire [2:0] ctest_pipe_out3; |
| 323 | wire [2:0] ctest_piped3; |
| 324 | wire crw_pipe_reg1_scanin; |
| 325 | wire crw_pipe_reg1_scanout; |
| 326 | wire [2:0] crw_pipe_reg1_in; |
| 327 | wire [2:0] crw_pipe_out1; |
| 328 | wire crw_pipe_reg2_scanin; |
| 329 | wire crw_pipe_reg2_scanout; |
| 330 | wire [2:0] crw_pipe_reg2_in; |
| 331 | wire [2:0] crw_pipe_out2; |
| 332 | wire crw_pipe_reg3_scanin; |
| 333 | wire crw_pipe_reg3_scanout; |
| 334 | wire [2:0] crw_pipe_reg3_in; |
| 335 | wire [2:0] crw_pipe_out3; |
| 336 | wire [2:0] crw_piped3; |
| 337 | wire fail_reg_scanin; |
| 338 | wire fail_reg_scanout; |
| 339 | wire [1:0] fail_reg_in; |
| 340 | wire [1:0] fail_reg_out; |
| 341 | wire qual_ptb_fail; |
| 342 | wire qual_vtb_fail; |
| 343 | wire fail_detect; |
| 344 | wire [1:0] cam_fail_reg_out; |
| 345 | wire qual_cam_vtb_fail; |
| 346 | wire qual_cam_ptb_fail; |
| 347 | wire cam_fail_reg_scanin; |
| 348 | wire cam_fail_reg_scanout; |
| 349 | wire [1:0] cam_fail_reg_in; |
| 350 | wire cam_fail_detect; |
| 351 | |
| 352 | |
| 353 | |
| 354 | output dmu_cb0_run; |
| 355 | |
| 356 | output [5:0] dmu_cb0_addr; |
| 357 | output [32:0] dmu_cb0_wdata_key; |
| 358 | |
| 359 | output dmu_cb0_mmu_vtb_wr_en; |
| 360 | output dmu_cb0_mmu_vtb_rd_en; |
| 361 | output dmu_cb0_mmu_vtb_lkup_en; |
| 362 | |
| 363 | output dmu_cb0_mmu_ptb_wr_en; |
| 364 | output dmu_cb0_mmu_ptb_rd_en; |
| 365 | output dmu_cb0_mmu_ptb_lkup_en; |
| 366 | |
| 367 | output dmu_cb0_hld; // New addition. |
| 368 | |
| 369 | output dmu_cb0_done; |
| 370 | output dmu_cb0_fail; |
| 371 | |
| 372 | output scan_out; |
| 373 | |
| 374 | // input l2clk; |
| 375 | input l1clk; |
| 376 | // input tcu_scan_en; |
| 377 | input scan_in; |
| 378 | input tcu_aclk; |
| 379 | input tcu_bclk; |
| 380 | // input tcu_pce_ov; |
| 381 | // input tcu_clk_stop; |
| 382 | input rst_; |
| 383 | |
| 384 | input tcu_dmu_cb0_start; |
| 385 | input dmu_cb0_bisi_mode; |
| 386 | input dmu_cb0_user_mode; |
| 387 | |
| 388 | input [32:0] mmu_vtb_read_data; |
| 389 | input [32:0] mmu_ptb_read_data; |
| 390 | |
| 391 | input [63:0] mmu_vtb_hit; |
| 392 | input [63:0] mmu_ptb_hit; |
| 393 | |
| 394 | |
| 395 | /////////////////////////////////////// |
| 396 | // Scan chain connections |
| 397 | /////////////////////////////////////// |
| 398 | // scan renames |
| 399 | // assign se = tcu_scan_en; |
| 400 | assign siclk = tcu_aclk; |
| 401 | assign soclk = tcu_bclk; |
| 402 | // assign pce_ov = tcu_pce_ov; |
| 403 | // assign stop = tcu_clk_stop; |
| 404 | // end scan |
| 405 | |
| 406 | // l1clkhdr_ctl_macro clkgen (library=a1) ( |
| 407 | // .l2clk (l2clk ), |
| 408 | // .l1en (1'b1 ), |
| 409 | // .l1clk (l1clk) |
| 410 | // ); |
| 411 | |
| 412 | assign reset = rst_; |
| 413 | |
| 414 | |
| 415 | // ///////////////////////////////////////////////////////////////////////////// |
| 416 | // |
| 417 | // MBIST Config Register |
| 418 | // |
| 419 | // ///////////////////////////////////////////////////////////////////////////// |
| 420 | // |
| 421 | // A low to high transition on mbist_start will reset and start the engine. |
| 422 | // mbist_start must remain active high for the duration of MBIST. |
| 423 | // If mbist_start deasserts the engine will stop but not reset. |
| 424 | // Once MBIST has completed mbist_done will assert and the fail status |
| 425 | // signals will be valid. |
| 426 | // To run MBIST again the mbist_start signal must transition low then high. |
| 427 | // |
| 428 | // Loop on Address will disable the address mix function. |
| 429 | // |
| 430 | // ///////////////////////////////////////////////////////////////////////////// |
| 431 | |
| 432 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_8 config_reg ( |
| 433 | .scan_in(config_reg_scanin), |
| 434 | .scan_out(config_reg_scanout), |
| 435 | .din ( config_in[7:0] ), |
| 436 | .dout ( config_out[7:0] ), |
| 437 | .reset(reset), |
| 438 | .l1clk(l1clk), |
| 439 | .siclk(siclk), |
| 440 | .soclk(soclk)); |
| 441 | |
| 442 | |
| 443 | |
| 444 | assign config_in[0] = tcu_dmu_cb0_start; |
| 445 | assign config_in[1] = config_out[0]; |
| 446 | assign start_transition = config_out[0] & ~config_out[1]; |
| 447 | assign reset_engine = start_transition | (mbist_user_loop_mode & mbist_done); |
| 448 | // assign run = config_out[1] & (mbist_user_loop_mode | ~mbist_done); |
| 449 | assign run = config_out[0] & config_out[1]; // 9/19/05 run to follow start only! |
| 450 | |
| 451 | assign config_in[2] = start_transition ? dmu_cb0_bisi_mode: config_out[2]; |
| 452 | assign bisi = config_out[2]; |
| 453 | |
| 454 | assign config_in[3] = start_transition ? dmu_cb0_user_mode: config_out[3]; |
| 455 | assign user_mode = config_out[3]; |
| 456 | |
| 457 | assign config_in[4] = config_out[4]; |
| 458 | assign user_data_mode = config_out[4]; |
| 459 | |
| 460 | assign config_in[5] = config_out[5]; |
| 461 | assign user_addr_mode = config_out[5]; |
| 462 | |
| 463 | assign config_in[6] = config_out[6]; |
| 464 | assign user_loop_mode = config_out[6]; |
| 465 | |
| 466 | assign config_in[7] = config_out[7]; |
| 467 | assign ten_n_mode = config_out[7]; |
| 468 | |
| 469 | |
| 470 | assign mbist_user_data_mode = user_mode & user_data_mode; |
| 471 | assign mbist_user_addr_mode = user_mode & user_addr_mode; |
| 472 | assign mbist_user_loop_mode = user_mode & user_loop_mode; |
| 473 | assign mbist_ten_n_mode = user_mode & ten_n_mode; |
| 474 | |
| 475 | |
| 476 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_8 user_data_reg ( |
| 477 | .scan_in(user_data_reg_scanin), |
| 478 | .scan_out(user_data_reg_scanout), |
| 479 | .din ( user_data_in[7:0] ), |
| 480 | .dout ( user_data_out[7:0] ), |
| 481 | .reset(reset), |
| 482 | .l1clk(l1clk), |
| 483 | .siclk(siclk), |
| 484 | .soclk(soclk)); |
| 485 | |
| 486 | |
| 487 | assign user_data_in[7:0] = user_data_out[7:0]; |
| 488 | |
| 489 | |
| 490 | // Defining User start, stop, and increment addresses. |
| 491 | |
| 492 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_6 user_start_addr_reg ( |
| 493 | .scan_in(user_start_addr_reg_scanin), |
| 494 | .scan_out(user_start_addr_reg_scanout), |
| 495 | .din ( user_start_addr_in[5:0] ), |
| 496 | .dout ( user_start_addr[5:0] ), |
| 497 | .reset(reset), |
| 498 | .l1clk(l1clk), |
| 499 | .siclk(siclk), |
| 500 | .soclk(soclk)); |
| 501 | |
| 502 | assign user_start_addr_in[5:0] = user_start_addr[5:0]; |
| 503 | |
| 504 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_6 user_stop_addr_reg ( |
| 505 | .scan_in(user_stop_addr_reg_scanin), |
| 506 | .scan_out(user_stop_addr_reg_scanout), |
| 507 | .din ( user_stop_addr_in[5:0] ), |
| 508 | .dout ( user_stop_addr[5:0] ), |
| 509 | .reset(reset), |
| 510 | .l1clk(l1clk), |
| 511 | .siclk(siclk), |
| 512 | .soclk(soclk)); |
| 513 | |
| 514 | assign user_stop_addr_in[5:0] = user_stop_addr[5:0]; |
| 515 | |
| 516 | |
| 517 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_6 user_incr_addr_reg ( |
| 518 | .scan_in(user_incr_addr_reg_scanin), |
| 519 | .scan_out(user_incr_addr_reg_scanout), |
| 520 | .din ( user_incr_addr_in[5:0] ), |
| 521 | .dout ( user_incr_addr[5:0] ), |
| 522 | .reset(reset), |
| 523 | .l1clk(l1clk), |
| 524 | .siclk(siclk), |
| 525 | .soclk(soclk)); |
| 526 | |
| 527 | assign user_incr_addr_in[5:0] = user_incr_addr[5:0]; |
| 528 | |
| 529 | // Defining User array_sel. |
| 530 | |
| 531 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_1 user_array_sel_reg ( |
| 532 | .scan_in(user_array_sel_reg_scanin), |
| 533 | .scan_out(user_array_sel_reg_scanout), |
| 534 | .din ( user_array_sel_in ), |
| 535 | .dout ( user_array_sel ), |
| 536 | .reset(reset), |
| 537 | .l1clk(l1clk), |
| 538 | .siclk(siclk), |
| 539 | .soclk(soclk)); |
| 540 | |
| 541 | assign user_array_sel_in = user_array_sel; |
| 542 | |
| 543 | |
| 544 | // user_cam_mode Register |
| 545 | // During user_mode, if user_cam_mode=0, then memBIST (R/W test); |
| 546 | // if user_cam_mode=1, then camBIST. |
| 547 | |
| 548 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_1 user_cam_mode_reg ( |
| 549 | .scan_in(user_cam_mode_reg_scanin), |
| 550 | .scan_out(user_cam_mode_reg_scanout), |
| 551 | .din ( user_cam_mode_in ), |
| 552 | .dout ( user_cam_mode ), |
| 553 | .reset(reset), |
| 554 | .l1clk(l1clk), |
| 555 | .siclk(siclk), |
| 556 | .soclk(soclk)); |
| 557 | |
| 558 | assign user_cam_mode_in = user_cam_mode; |
| 559 | |
| 560 | // cambist: user CAM select |
| 561 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_1 user_cam_select_reg ( |
| 562 | .scan_in(user_cam_select_reg_scanin), |
| 563 | .scan_out(user_cam_select_reg_scanout), |
| 564 | .din ( user_cam_sel_in ), |
| 565 | .dout ( user_cam_sel ), |
| 566 | .reset(reset), |
| 567 | .l1clk(l1clk), |
| 568 | .siclk(siclk), |
| 569 | .soclk(soclk)); |
| 570 | |
| 571 | assign user_cam_sel_in = user_cam_sel; |
| 572 | |
| 573 | // cambist: user CAM test select |
| 574 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_3 user_cam_test_select_reg ( |
| 575 | .scan_in(user_cam_test_select_reg_scanin), |
| 576 | .scan_out(user_cam_test_select_reg_scanout), |
| 577 | .din ( user_cam_test_sel_in[2:0] ), |
| 578 | .dout ( user_cam_test_sel[2:0] ), |
| 579 | .reset(reset), |
| 580 | .l1clk(l1clk), |
| 581 | .siclk(siclk), |
| 582 | .soclk(soclk)); |
| 583 | |
| 584 | assign user_cam_test_sel_in[2:0] = user_cam_test_sel[2:0]; |
| 585 | |
| 586 | // Defining user_bisi write and read registers |
| 587 | |
| 588 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_1 user_bisi_wr_reg ( |
| 589 | .scan_in(user_bisi_wr_reg_scanin), |
| 590 | .scan_out(user_bisi_wr_reg_scanout), |
| 591 | .din ( user_bisi_wr_mode_in ), |
| 592 | .dout ( user_bisi_wr_mode ), |
| 593 | .reset(reset), |
| 594 | .l1clk(l1clk), |
| 595 | .siclk(siclk), |
| 596 | .soclk(soclk)); |
| 597 | |
| 598 | assign user_bisi_wr_mode_in = user_bisi_wr_mode; |
| 599 | |
| 600 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_1 user_bisi_rd_reg ( |
| 601 | .scan_in(user_bisi_rd_reg_scanin), |
| 602 | .scan_out(user_bisi_rd_reg_scanout), |
| 603 | .din ( user_bisi_rd_mode_in ), |
| 604 | .dout ( user_bisi_rd_mode ), |
| 605 | .reset(reset), |
| 606 | .l1clk(l1clk), |
| 607 | .siclk(siclk), |
| 608 | .soclk(soclk)); |
| 609 | |
| 610 | assign user_bisi_rd_mode_in = user_bisi_rd_mode; |
| 611 | |
| 612 | assign mbist_user_bisi_wr_mode = user_mode & bisi & user_bisi_wr_mode & ~user_bisi_rd_mode; |
| 613 | // assign mbist_user_bisi_rd_mode = user_mode & bisi & user_bisi_rd_mode & ~user_bisi_wr_mode; |
| 614 | |
| 615 | assign mbist_user_bisi_wr_rd_mode = user_mode & bisi & |
| 616 | ((user_bisi_wr_mode & user_bisi_rd_mode) | |
| 617 | (~user_bisi_wr_mode & ~user_bisi_rd_mode)); |
| 618 | |
| 619 | //////////////////////////////////////////////////////////////////////////////// |
| 620 | // Piping start_transition |
| 621 | //////////////////////////////////////////////////////////////////////////////// |
| 622 | |
| 623 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_1 start_transition_reg ( |
| 624 | .scan_in(start_transition_reg_scanin), |
| 625 | .scan_out(start_transition_reg_scanout), |
| 626 | .din ( start_transition ), |
| 627 | .dout ( start_transition_piped ), |
| 628 | .reset(reset), |
| 629 | .l1clk(l1clk), |
| 630 | .siclk(siclk), |
| 631 | .soclk(soclk)); |
| 632 | |
| 633 | //////////////////////////////////////////////////////////////////////////////// |
| 634 | // Staging run for 3 cycles |
| 635 | //////////////////////////////////////////////////////////////////////////////// |
| 636 | |
| 637 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_1 run_reg ( |
| 638 | .scan_in(run_reg_scanin), |
| 639 | .scan_out(run_reg_scanout), |
| 640 | .din ( run ), |
| 641 | .dout ( dmu_cb0_run ), |
| 642 | .reset(reset), |
| 643 | .l1clk(l1clk), |
| 644 | .siclk(siclk), |
| 645 | .soclk(soclk)); |
| 646 | |
| 647 | //Adding 2 extra pipeline stages to run to delay the start of mbist for 3 cycles. |
| 648 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_1 run1_reg ( |
| 649 | .scan_in(run1_reg_scanin), |
| 650 | .scan_out(run1_reg_scanout), |
| 651 | .din ( run1_in ), |
| 652 | .dout ( run1_out ), |
| 653 | .reset(reset), |
| 654 | .l1clk(l1clk), |
| 655 | .siclk(siclk), |
| 656 | .soclk(soclk)); |
| 657 | |
| 658 | assign run1_in = reset_engine ? 1'b0: dmu_cb0_run; |
| 659 | |
| 660 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_1 run2_reg ( |
| 661 | .scan_in(run2_reg_scanin), |
| 662 | .scan_out(run2_reg_scanout), |
| 663 | .din ( run2_in ), |
| 664 | .dout ( run2_out ), |
| 665 | .reset(reset), |
| 666 | .l1clk(l1clk), |
| 667 | .siclk(siclk), |
| 668 | .soclk(soclk)); |
| 669 | |
| 670 | assign run2_in = reset_engine ? 1'b0: run1_out; |
| 671 | // assign run_piped3 = run2_out & run; |
| 672 | assign run_piped3 = config_out[0] & run2_out & ~msb; |
| 673 | |
| 674 | |
| 675 | //////////////////////////////////////////////////////////////////////////////// |
| 676 | // Creating flop boundaries for the outputs of the mbist |
| 677 | //////////////////////////////////////////////////////////////////////////////// |
| 678 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_6 addr_reg ( |
| 679 | .scan_in(addr_reg_scanin), |
| 680 | .scan_out(addr_reg_scanout), |
| 681 | .din ( int_address[5:0] ), |
| 682 | .dout ( dmu_cb0_addr[5:0] ), |
| 683 | .reset(reset), |
| 684 | .l1clk(l1clk), |
| 685 | .siclk(siclk), |
| 686 | .soclk(soclk)); |
| 687 | |
| 688 | assign int_address[5:0] = cambist ? cam_addr[5:0] : mbist_address[5:0]; |
| 689 | |
| 690 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_33 key_reg ( |
| 691 | .scan_in(key_reg_scanin), |
| 692 | .scan_out(key_reg_scanout), |
| 693 | .din ( mbist_wdata_key[32:0] ), |
| 694 | .dout ( dmu_cb0_wdata_key[32:0] ), |
| 695 | .reset(reset), |
| 696 | .l1clk(l1clk), |
| 697 | .siclk(siclk), |
| 698 | .soclk(soclk)); |
| 699 | |
| 700 | |
| 701 | assign mbist_wdata_key[32:0] = array_write | array_read ? { mbist_wdata[0], {4{mbist_wdata[7:0]}} } : |
| 702 | (ctest0 | ctest2 | ctest4) & cseq0 ? 33'b0 : |
| 703 | (ctest1 | ctest3) & cseq0 ? {33{1'b1}} : |
| 704 | cseq1 & ( ((ctest0 | ctest2) & (crw0 | crw1)) | (ctest1 & crw2) ) ? {33{1'b1}} : |
| 705 | cseq1 & ( (ctest0 & crw2) | (ctest1 & (crw0 | crw1)) | (ctest2 & (crw2 | crw3 | crw4)) ) ? 33'b0 : |
| 706 | ctest3 & (cam_addr[5:0] == 6'b0) ? 33'h1FFFFFFFE : // Start walking0 |
| 707 | ctest4 & (cam_addr[5:0] == 6'b0) ? 33'h01 : // Start walking1 |
| 708 | (ctest3 | ctest4) & cseq1 ? {dmu_cb0_wdata_key[31:0], dmu_cb0_wdata_key[32]} : |
| 709 | 33'b0; |
| 710 | |
| 711 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_6 wr_rd_en_reg ( |
| 712 | .scan_in(wr_rd_en_reg_scanin), |
| 713 | .scan_out(wr_rd_en_reg_scanout), |
| 714 | .din ( {vtb_wr_en, vtb_rd_en, vtb_lkup_en, ptb_wr_en, ptb_rd_en, ptb_lkup_en} ), |
| 715 | .dout ( {dmu_cb0_mmu_vtb_wr_en, dmu_cb0_mmu_vtb_rd_en, dmu_cb0_mmu_vtb_lkup_en, dmu_cb0_mmu_ptb_wr_en, dmu_cb0_mmu_ptb_rd_en, dmu_cb0_mmu_ptb_lkup_en } ), |
| 716 | .reset(reset), |
| 717 | .l1clk(l1clk), |
| 718 | .siclk(siclk), |
| 719 | .soclk(soclk)); |
| 720 | |
| 721 | |
| 722 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_1 hld_reg ( |
| 723 | .scan_in(hld_reg_scanin), |
| 724 | .scan_out(hld_reg_scanout), |
| 725 | .din ( mbist_hld ), |
| 726 | .dout ( dmu_cb0_hld ), |
| 727 | .reset(reset), |
| 728 | .l1clk(l1clk), |
| 729 | .siclk(siclk), |
| 730 | .soclk(soclk)); |
| 731 | |
| 732 | |
| 733 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_1 done_reg ( |
| 734 | .scan_in(done_reg_scanin), |
| 735 | .scan_out(done_reg_scanout), |
| 736 | .din ( mbist_done ), |
| 737 | .dout ( dmu_cb0_done ), |
| 738 | .reset(reset), |
| 739 | .l1clk(l1clk), |
| 740 | .siclk(siclk), |
| 741 | .soclk(soclk)); |
| 742 | |
| 743 | |
| 744 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_1 mbist_fail_reg ( |
| 745 | .scan_in(mbist_fail_reg_scanin), |
| 746 | .scan_out(mbist_fail_reg_scanout), |
| 747 | .din ( fail ), |
| 748 | .dout ( dmu_cb0_fail ), |
| 749 | .reset(reset), |
| 750 | .l1clk(l1clk), |
| 751 | .siclk(siclk), |
| 752 | .soclk(soclk)); |
| 753 | |
| 754 | |
| 755 | //////////////////////////////////////////////////////////////////////////////// |
| 756 | // Creating resultant read_data by muxing the memories outputs |
| 757 | //////////////////////////////////////////////////////////////////////////////// |
| 758 | |
| 759 | //Piped off internal vtb_sel, therefore, piped twice. |
| 760 | assign res_read_data[32:0] = vtb_sel_piped2 ? mmu_vtb_read_data[32:0] : |
| 761 | mmu_ptb_read_data[32:0]; |
| 762 | |
| 763 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_33 read_data_pipe_reg ( |
| 764 | .scan_in(read_data_pipe_reg_scanin), |
| 765 | .scan_out(read_data_pipe_reg_scanout), |
| 766 | .din ( res_read_data[32:0] ), |
| 767 | .dout ( res_read_data_piped[32:0] ), |
| 768 | .reset(reset), |
| 769 | .l1clk(l1clk), |
| 770 | .siclk(siclk), |
| 771 | .soclk(soclk)); |
| 772 | |
| 773 | //////////////////////////////////////////////////////////////////////////////// |
| 774 | // Creating resultant hit_data by muxing the memories hit outputs |
| 775 | //////////////////////////////////////////////////////////////////////////////// |
| 776 | |
| 777 | //Piped off internal cam_vtb_sel, therefore, piped twice. |
| 778 | assign res_hit_data[63:0] = cam_vtb_sel_piped2 ? mmu_vtb_hit[63:0] : mmu_ptb_hit[63:0]; |
| 779 | |
| 780 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_64 hit_data_pipe_reg ( |
| 781 | .scan_in(hit_data_pipe_reg_scanin), |
| 782 | .scan_out(hit_data_pipe_reg_scanout), |
| 783 | .din ( res_hit_data[63:0] ), |
| 784 | .dout ( res_hit_data_piped[63:0] ), |
| 785 | .reset(reset), |
| 786 | .l1clk(l1clk), |
| 787 | .siclk(siclk), |
| 788 | .soclk(soclk)); |
| 789 | |
| 790 | |
| 791 | // ///////////////////////////////////////////////////////////////////////////// |
| 792 | // |
| 793 | // MBIST Control Register |
| 794 | // |
| 795 | // ///////////////////////////////////////////////////////////////////////////// |
| 796 | |
| 797 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_19 control_reg ( |
| 798 | .scan_in(control_reg_scanin), |
| 799 | .scan_out(control_reg_scanout), |
| 800 | .din ( control_in[18:0] ), |
| 801 | .dout ( control_out[18:0] ), |
| 802 | .reset(reset), |
| 803 | .l1clk(l1clk), |
| 804 | .siclk(siclk), |
| 805 | .soclk(soclk)); |
| 806 | |
| 807 | assign msb = ~bisi & user_mode & user_cam_mode ? 1'b1 : control_out[18]; |
| 808 | assign bisi_wr_rd = (bisi & ~user_mode) | mbist_user_bisi_wr_rd_mode ? control_out[17] : 1'b1; |
| 809 | assign array_sel = user_mode ? user_array_sel : control_out[16]; |
| 810 | assign data_control[1:0] = control_out[15:14]; |
| 811 | assign address_mix = (bisi | mbist_user_addr_mode) ? 1'b0: control_out[13]; |
| 812 | assign march_element[3:0] = control_out[12:9]; |
| 813 | assign array_address[5:0] = upaddress_march ? control_out[8:3] : ~control_out[8:3]; |
| 814 | assign read_write_control[2:0] = ~five_cycle_march ? {2'b11, control_out[0]} : |
| 815 | control_out[2:0]; |
| 816 | |
| 817 | |
| 818 | assign control_in[2:0] = reset_engine ? 3'b0: |
| 819 | ~run_piped3 ? control_out[2:0]: |
| 820 | (five_cycle_march && (read_write_control[2:0] == 3'b100)) ? 3'b000: |
| 821 | (one_cycle_march && (read_write_control[2:0] == 3'b110)) ? 3'b000: |
| 822 | control_out[2:0] + 3'b001; |
| 823 | |
| 824 | assign increment_addr = (five_cycle_march && (read_write_control[2:0] == 3'b100)) || |
| 825 | (one_cycle_march && (read_write_control[2:0] == 3'b110)) || |
| 826 | (read_write_control[2:0] == 3'b111); |
| 827 | |
| 828 | // start_transition_piped was added to have the correct start_addr at the start |
| 829 | // of mbist during user_addr_mode |
| 830 | assign control_in[8:3] = start_transition_piped || reset_engine ? start_addr[5:0]: |
| 831 | ~run_piped3 || ~increment_addr ? control_out[8:3]: |
| 832 | next_array_address[5:0]; |
| 833 | |
| 834 | assign next_array_address[5:0] = next_upaddr_march ? start_addr[5:0]: |
| 835 | next_downaddr_march ? ~stop_addr[5:0]: |
| 836 | (overflow_addr[5:0]); // array_addr + incr_addr |
| 837 | |
| 838 | assign start_addr[5:0] = mbist_user_addr_mode ? user_start_addr[5:0] : 6'b000000; |
| 839 | assign stop_addr[5:0] = mbist_user_addr_mode ? user_stop_addr[5:0] : 6'b111111; |
| 840 | assign incr_addr[5:0] = mbist_user_addr_mode ? user_incr_addr[5:0] : 6'b000001; |
| 841 | |
| 842 | assign overflow_addr[6:0] = {1'b0,control_out[8:3]} + {1'b0,incr_addr[5:0]}; |
| 843 | assign overflow = compare_addr[6:0] < overflow_addr[6:0]; |
| 844 | |
| 845 | assign compare_addr[6:0] = upaddress_march ? {1'b0, stop_addr[5:0]} : |
| 846 | {1'b0, ~start_addr[5:0]}; |
| 847 | |
| 848 | assign next_upaddr_march = ( (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h1) || |
| 849 | (march_element[3:0] == 4'h6) || (march_element[3:0] == 4'h5) || |
| 850 | (march_element[3:0] == 4'h8) ) && overflow; |
| 851 | |
| 852 | assign next_downaddr_march = ( (march_element[3:0] == 4'h2) || (march_element[3:0] == 4'h7) || |
| 853 | (march_element[3:0] == 4'h3) || (march_element[3:0] == 4'h4) ) && |
| 854 | overflow; |
| 855 | |
| 856 | |
| 857 | |
| 858 | assign add[5:0] = five_cycle_march && ( (read_write_control[2:0] == 3'h1) || |
| 859 | (read_write_control[2:0] == 3'h3)) ? |
| 860 | adj_address[5:0]: array_address[5:0]; |
| 861 | |
| 862 | // All addresses are row addresses. There are two banks however. 0:31 in one |
| 863 | // bank and 32:63 in the other. |
| 864 | assign adj_address[5:0] = { array_address[5:3], ~array_address[2], array_address[1:0] }; |
| 865 | |
| 866 | assign mbist_address[5:0] = address_mix ? {add[1:0],add[5:2]}: |
| 867 | add[5:0]; |
| 868 | |
| 869 | // Definition of the rest of the control register |
| 870 | assign increment_march_elem = increment_addr && overflow; |
| 871 | |
| 872 | assign control_in[18:9] = reset_engine ? 10'b0: |
| 873 | ~run_piped3 ? control_out[18:9]: |
| 874 | {msb, bisi_wr_rd, next_array_sel, next_data_control[1:0], next_address_mix, next_march_element[3:0]} |
| 875 | + {9'b0, increment_march_elem}; |
| 876 | |
| 877 | assign next_array_sel = user_mode ? 1'b1: control_out[16]; |
| 878 | assign next_data_control[1:0] = (bisi || (mbist_user_data_mode && (data_control[1:0] == 2'b00))) ? 2'b11: |
| 879 | data_control[1:0]; |
| 880 | |
| 881 | assign next_address_mix = bisi | mbist_user_addr_mode ? 1'b1 : address_mix; |
| 882 | |
| 883 | // Modified next_march_element to remove a possible long path. |
| 884 | // Incorporated ten_n_mode! |
| 885 | assign next_march_element[3:0] = ( bisi || |
| 886 | (mbist_ten_n_mode && (march_element[3:0] == 4'b0101)) || |
| 887 | ((march_element[3:0] == 4'b1000) && (read_write_control[2:0] == 3'b100)) ) |
| 888 | && overflow ? 4'b1111: march_element[3:0]; |
| 889 | |
| 890 | // assign next_march_element[3:0] = (bisi || ((march_element[3:0] == 4'b1000) && (read_write_control[2:0] == 3'b100)) ) |
| 891 | // && overflow ? 4'b1111: march_element[3:0]; |
| 892 | |
| 893 | |
| 894 | assign array_write = ~run_piped3 ? 1'b0: |
| 895 | five_cycle_march ? (read_write_control[2:0] == 3'h0) || |
| 896 | (read_write_control[2:0] == 3'h1) || |
| 897 | (read_write_control[2:0] == 3'h4): |
| 898 | (~five_cycle_march & ~one_cycle_march) ? read_write_control[0]: |
| 899 | ( ((march_element[3:0] == 4'h0) & (~bisi || ~bisi_wr_rd || mbist_user_bisi_wr_mode)) || (march_element[3:0] == 4'h7)); |
| 900 | |
| 901 | assign array_read = ~array_write && run_piped3; // && ~initialize; |
| 902 | // assign mbist_done = msb; |
| 903 | |
| 904 | assign mbist_wdata[7:0] = true_data ? data_pattern[7:0]: ~data_pattern[7:0]; |
| 905 | |
| 906 | |
| 907 | assign five_cycle_march = (march_element[3:0] == 4'h6) || (march_element[3:0] == 4'h8); |
| 908 | assign one_cycle_march = (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h5) || |
| 909 | (march_element[3:0] == 4'h7); |
| 910 | |
| 911 | assign upaddress_march = (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h1) || |
| 912 | (march_element[3:0] == 4'h2) || (march_element[3:0] == 4'h6) || |
| 913 | (march_element[3:0] == 4'h7); |
| 914 | |
| 915 | // assign true_data = read_write_control[1] ^ ~march_element[0]; |
| 916 | |
| 917 | assign true_data = (five_cycle_march && (march_element[3:0] == 4'h6)) ? |
| 918 | ((read_write_control[2:0] == 3'h0) || (read_write_control[2:0] == 3'h2)): |
| 919 | (five_cycle_march && (march_element[3:0] == 4'h8)) ? |
| 920 | ((read_write_control[2:0] == 3'h1) || |
| 921 | (read_write_control[2:0] == 3'h3) || (read_write_control[2:0] == 3'h4)): |
| 922 | one_cycle_march ? (march_element[3:0] == 4'h7): |
| 923 | ~(read_write_control[0] ^ march_element[0]); |
| 924 | |
| 925 | |
| 926 | assign data_pattern[7:0] = (bisi & mbist_user_data_mode) ? ~user_data_out[7:0]: |
| 927 | mbist_user_data_mode ? user_data_out[7:0]: |
| 928 | bisi ? 8'hFF: // true_data function will invert to 8'h00 |
| 929 | (data_control[1:0] == 2'h0) ? 8'hAA: |
| 930 | (data_control[1:0] == 2'h1) ? 8'h99: |
| 931 | (data_control[1:0] == 2'h2) ? 8'hCC: |
| 932 | 8'h00; |
| 933 | |
| 934 | |
| 935 | ///////////////////////////////////////////////////////////////////////// |
| 936 | // Creating the mbist_done signal |
| 937 | ///////////////////////////////////////////////////////////////////////// |
| 938 | // Delaying mbist_done 8 clock signals after msb going high, to provide |
| 939 | // a generic solution for done going high after the last fail has come back! |
| 940 | |
| 941 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_3 done_counter_reg ( |
| 942 | .scan_in(done_counter_reg_scanin), |
| 943 | .scan_out(done_counter_reg_scanout), |
| 944 | .din ( done_counter_in[2:0] ), |
| 945 | .dout ( done_counter_out[2:0] ), |
| 946 | .reset(reset), |
| 947 | .l1clk(l1clk), |
| 948 | .siclk(siclk), |
| 949 | .soclk(soclk)); |
| 950 | |
| 951 | // config_out[1] is AND'ed to force mbist_done low 2 cycles after mbist_start |
| 952 | // goes low. |
| 953 | |
| 954 | assign mbist_done = (&done_counter_out[2:0] == 1'b1) & config_out[1]; |
| 955 | assign done_counter_in[2:0] = reset_engine ? 3'b000: |
| 956 | final_msb & ~mbist_done & config_out[1] ? done_counter_out[2:0] + 3'b001: |
| 957 | done_counter_out[2:0]; |
| 958 | |
| 959 | assign final_msb = bisi ? msb : cam_msb; |
| 960 | |
| 961 | ///////////////////////////////////////////////////////////////////////// |
| 962 | // Creating the select lines and enable signals. |
| 963 | ///////////////////////////////////////////////////////////////////////// |
| 964 | |
| 965 | assign vtb_sel = ~array_sel; |
| 966 | assign ptb_sel = array_sel; |
| 967 | |
| 968 | assign vtb_rd_en = vtb_sel && array_read; |
| 969 | assign vtb_wr_en = (vtb_sel && array_write) || (cam_vtb_sel && cam_wr_en); |
| 970 | |
| 971 | assign ptb_rd_en = ptb_sel && array_read; |
| 972 | assign ptb_wr_en = (ptb_sel && array_write) || (cam_ptb_sel && cam_wr_en); |
| 973 | |
| 974 | assign cam_vtb_sel = ~cam_array_sel; |
| 975 | assign cam_ptb_sel = cam_array_sel; |
| 976 | |
| 977 | assign vtb_lkup_en = cam_vtb_sel && cam_lkup_en; |
| 978 | assign ptb_lkup_en = cam_ptb_sel && cam_lkup_en; |
| 979 | |
| 980 | |
| 981 | // ///////////////////////////////////////////////////////////////////////////// |
| 982 | // CAM BIST: |
| 983 | // ///////////////////////////////////////////////////////////////////////////// |
| 984 | |
| 985 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_15 cam_cntl_reg ( |
| 986 | .scan_in(cam_cntl_reg_scanin), |
| 987 | .scan_out(cam_cntl_reg_scanout), |
| 988 | .din ( cam_in[14:0] ), |
| 989 | .dout ( cam_out[14:0] ), |
| 990 | .reset(reset), |
| 991 | .l1clk(l1clk), |
| 992 | .siclk(siclk), |
| 993 | .soclk(soclk)); |
| 994 | |
| 995 | assign cam_msb = user_mode & ~user_cam_mode & msb ? 1'b1 : cam_out[14]; |
| 996 | |
| 997 | assign cam_array_sel = user_mode ? user_cam_sel: |
| 998 | cam_out[13]; |
| 999 | |
| 1000 | assign ctest[2:0] = user_mode ? user_cam_test_sel[2:0] : |
| 1001 | cam_out[12:10]; |
| 1002 | |
| 1003 | assign cseq = cam_out[9]; |
| 1004 | |
| 1005 | assign cam_addr[5:0] = cam_out[8:3]; |
| 1006 | |
| 1007 | assign crw[2:0] = cseq0 | (ctest3 | ctest4) ? 3'b111: |
| 1008 | cam_out[2:0]; // read write control |
| 1009 | |
| 1010 | assign ctest0 = ~( ctest[2] | ctest[1] | ctest[0]); // ^(W0); ^(W1 C1 W0) |
| 1011 | assign ctest1 = ~( ctest[2] | ctest[1] | ~ctest[0]); // ^(W1); ^(W0 C0 W1) |
| 1012 | assign ctest2 = ~( ctest[2] | ~ctest[1] | ctest[0]); // ^(W0); ^(W1 C1 C0,hld C0 W0) for VTB only! |
| 1013 | assign ctest3 = ~( ctest[2] | ~ctest[1] | ~ctest[0]); // ^(W1); >C(wk0) |
| 1014 | assign ctest4 = ~( ~ctest[2] | ctest[1] | ctest[0]); // ^(W0); >C(wk1) |
| 1015 | |
| 1016 | assign cseq0 = ~cseq; |
| 1017 | assign cseq1 = cseq; |
| 1018 | |
| 1019 | assign crw0 = ~( crw[2] | crw[1] | crw[0]); |
| 1020 | assign crw1 = ~( crw[2] | crw[1] | ~crw[0]); |
| 1021 | assign crw2 = ~( crw[2] | ~crw[1] | crw[0]); |
| 1022 | assign crw3 = ~( crw[2] | ~crw[1] | ~crw[0]); |
| 1023 | assign crw4 = ~(~crw[2] | crw[1] | crw[0]); |
| 1024 | |
| 1025 | |
| 1026 | assign cam_wr_en = cambist & ( cseq0 | |
| 1027 | (cseq1 & ((ctest0 | ctest1) & (crw0 | crw2)) | |
| 1028 | ( ctest2 & (crw0 | crw4)) ) ); |
| 1029 | |
| 1030 | assign cam_lkup_en = cambist & cseq1 & |
| 1031 | ( ((ctest0 | ctest1) & crw1 ) | |
| 1032 | ( ctest2 & (crw1 | crw2 | crw3)) | |
| 1033 | ( ctest3 | ctest4) ); |
| 1034 | |
| 1035 | assign mbist_hld = cambist & ctest2 & cseq1 & crw2; |
| 1036 | |
| 1037 | assign qual_cam[14:0] = {cam_msb, |
| 1038 | next_cam_array_sel, |
| 1039 | next_ctest[2:0], |
| 1040 | cseq, |
| 1041 | next_cam_addr[5:0], |
| 1042 | next_crw[2:0]}; |
| 1043 | |
| 1044 | assign cam_in[14:0] = reset_engine ? 15'b0: // set zero |
| 1045 | cambist ? qual_cam[14:0] + 15'h1: // increment |
| 1046 | qual_cam[14:0]; // save value |
| 1047 | |
| 1048 | assign next_cam_array_sel = user_mode ? 1'b1 : cam_out[13]; |
| 1049 | |
| 1050 | assign next_ctest[2:0] = user_mode ? 3'b111 : |
| 1051 | ctest4 & cseq1 & (cam_addr[5:0] == 6'b100000) ? 3'b111 : |
| 1052 | cam_array_sel & ctest1 & cseq1 & crw2 & (cam_addr[5:0] == 6'b111111) ? 3'b010 : cam_out[12:10]; |
| 1053 | |
| 1054 | assign next_cam_addr[5:0] = (ctest3 | ctest4) & cseq1 & |
| 1055 | (cam_addr[5:0] == 6'b100000) ? 6'b111111 : cam_addr[5:0]; |
| 1056 | |
| 1057 | assign next_crw[2:0] = (ctest0 | ctest1) & cseq1 & crw2 ? 3'b111 : |
| 1058 | ctest2 & cseq1 & crw4 ? 3'b111 : crw[2:0]; |
| 1059 | |
| 1060 | // Defining cambist mode of operation! |
| 1061 | |
| 1062 | assign cambist = ~bisi & run2_out & msb & ~cam_msb; |
| 1063 | |
| 1064 | // ///////////////////////////////////////////////////////////////////////////// |
| 1065 | // Pipeline for wdata, Read_en and lkup_en |
| 1066 | // ///////////////////////////////////////////////////////////////////////////// |
| 1067 | |
| 1068 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_6 addr_pipe_reg1 ( |
| 1069 | .scan_in(addr_pipe_reg1_scanin), |
| 1070 | .scan_out(addr_pipe_reg1_scanout), |
| 1071 | .din ( addr_pipe_reg1_in[5:0] ), |
| 1072 | .dout ( addr_pipe_out1[5:0] ), |
| 1073 | .reset(reset), |
| 1074 | .l1clk(l1clk), |
| 1075 | .siclk(siclk), |
| 1076 | .soclk(soclk)); |
| 1077 | |
| 1078 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_6 addr_pipe_reg2 ( |
| 1079 | .scan_in(addr_pipe_reg2_scanin), |
| 1080 | .scan_out(addr_pipe_reg2_scanout), |
| 1081 | .din ( addr_pipe_reg2_in[5:0] ), |
| 1082 | .dout ( addr_pipe_out2[5:0] ), |
| 1083 | .reset(reset), |
| 1084 | .l1clk(l1clk), |
| 1085 | .siclk(siclk), |
| 1086 | .soclk(soclk)); |
| 1087 | |
| 1088 | assign addr_pipe_reg1_in[5:0] = reset_engine ? 6'h00: dmu_cb0_addr[5:0]; |
| 1089 | assign addr_pipe_reg2_in[5:0] = reset_engine ? 6'h00: addr_pipe_out1[5:0]; |
| 1090 | |
| 1091 | assign dmu_cb0_piped_addr[5:0] = addr_pipe_out2[5:0]; |
| 1092 | |
| 1093 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_8 data_pipe_reg1 ( |
| 1094 | .scan_in(data_pipe_reg1_scanin), |
| 1095 | .scan_out(data_pipe_reg1_scanout), |
| 1096 | .din ( date_pipe_reg1_in[7:0] ), |
| 1097 | .dout ( data_pipe_out1[7:0] ), |
| 1098 | .reset(reset), |
| 1099 | .l1clk(l1clk), |
| 1100 | .siclk(siclk), |
| 1101 | .soclk(soclk)); |
| 1102 | |
| 1103 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_8 data_pipe_reg2 ( |
| 1104 | .scan_in(data_pipe_reg2_scanin), |
| 1105 | .scan_out(data_pipe_reg2_scanout), |
| 1106 | .din ( date_pipe_reg2_in[7:0] ), |
| 1107 | .dout ( data_pipe_out2[7:0] ), |
| 1108 | .reset(reset), |
| 1109 | .l1clk(l1clk), |
| 1110 | .siclk(siclk), |
| 1111 | .soclk(soclk)); |
| 1112 | |
| 1113 | assign date_pipe_reg1_in[7:0] = reset_engine ? 8'h00: dmu_cb0_wdata_key[7:0]; |
| 1114 | assign date_pipe_reg2_in[7:0] = reset_engine ? 8'h00: data_pipe_out1[7:0]; |
| 1115 | // assign date_pipe_reg3_in[7:0] = reset_engine ? 8'h00: data_pipe_out2[7:0]; |
| 1116 | |
| 1117 | assign dmu_cb0_piped_data[7:0] = data_pipe_out2[7:0]; |
| 1118 | |
| 1119 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_1 vtb_sel_pipe_reg1 ( |
| 1120 | .scan_in(vtb_sel_pipe_reg1_scanin), |
| 1121 | .scan_out(vtb_sel_pipe_reg1_scanout), |
| 1122 | .din ( vtb_sel_pipe_reg1_in ), |
| 1123 | .dout ( vtb_sel_piped ), |
| 1124 | .reset(reset), |
| 1125 | .l1clk(l1clk), |
| 1126 | .siclk(siclk), |
| 1127 | .soclk(soclk)); |
| 1128 | |
| 1129 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_1 vtb_sel_pipe_reg2 ( |
| 1130 | .scan_in(vtb_sel_pipe_reg2_scanin), |
| 1131 | .scan_out(vtb_sel_pipe_reg2_scanout), |
| 1132 | .din ( vtb_sel_pipe_reg2_in ), |
| 1133 | .dout ( vtb_sel_piped2 ), |
| 1134 | .reset(reset), |
| 1135 | .l1clk(l1clk), |
| 1136 | .siclk(siclk), |
| 1137 | .soclk(soclk)); |
| 1138 | |
| 1139 | assign vtb_sel_pipe_reg1_in = reset_engine ? 1'b0: vtb_sel; |
| 1140 | assign vtb_sel_pipe_reg2_in = reset_engine ? 1'b0: vtb_sel_piped; |
| 1141 | |
| 1142 | |
| 1143 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_1 vtb_ren_pipe_reg1 ( |
| 1144 | .scan_in(vtb_ren_pipe_reg1_scanin), |
| 1145 | .scan_out(vtb_ren_pipe_reg1_scanout), |
| 1146 | .din ( vtb_ren_pipe_reg1_in ), |
| 1147 | .dout ( vtb_rd_en_piped ), |
| 1148 | .reset(reset), |
| 1149 | .l1clk(l1clk), |
| 1150 | .siclk(siclk), |
| 1151 | .soclk(soclk)); |
| 1152 | |
| 1153 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_1 vtb_ren_pipe_reg2 ( |
| 1154 | .scan_in(vtb_ren_pipe_reg2_scanin), |
| 1155 | .scan_out(vtb_ren_pipe_reg2_scanout), |
| 1156 | .din ( vtb_ren_pipe_reg2_in ), |
| 1157 | .dout ( vtb_rd_en_piped2 ), |
| 1158 | .reset(reset), |
| 1159 | .l1clk(l1clk), |
| 1160 | .siclk(siclk), |
| 1161 | .soclk(soclk)); |
| 1162 | |
| 1163 | assign vtb_ren_pipe_reg1_in = reset_engine ? 1'b0: dmu_cb0_mmu_vtb_rd_en; |
| 1164 | assign vtb_ren_pipe_reg2_in = reset_engine ? 1'b0: vtb_rd_en_piped; |
| 1165 | |
| 1166 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_1 ptb_ren_pipe_reg1 ( |
| 1167 | .scan_in(ptb_ren_pipe_reg1_scanin), |
| 1168 | .scan_out(ptb_ren_pipe_reg1_scanout), |
| 1169 | .din ( ptb_ren_pipe_reg1_in ), |
| 1170 | .dout ( ptb_rd_en_piped ), |
| 1171 | .reset(reset), |
| 1172 | .l1clk(l1clk), |
| 1173 | .siclk(siclk), |
| 1174 | .soclk(soclk)); |
| 1175 | |
| 1176 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_1 ptb_ren_pipe_reg2 ( |
| 1177 | .scan_in(ptb_ren_pipe_reg2_scanin), |
| 1178 | .scan_out(ptb_ren_pipe_reg2_scanout), |
| 1179 | .din ( ptb_ren_pipe_reg2_in ), |
| 1180 | .dout ( ptb_rd_en_piped2 ), |
| 1181 | .reset(reset), |
| 1182 | .l1clk(l1clk), |
| 1183 | .siclk(siclk), |
| 1184 | .soclk(soclk)); |
| 1185 | |
| 1186 | assign ptb_ren_pipe_reg1_in = reset_engine ? 1'b0: dmu_cb0_mmu_ptb_rd_en; |
| 1187 | assign ptb_ren_pipe_reg2_in = reset_engine ? 1'b0: ptb_rd_en_piped; |
| 1188 | |
| 1189 | //lkup_en |
| 1190 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_1 cam_vtb_sel_pipe_reg1 ( |
| 1191 | .scan_in(cam_vtb_sel_pipe_reg1_scanin), |
| 1192 | .scan_out(cam_vtb_sel_pipe_reg1_scanout), |
| 1193 | .din ( cam_vtb_sel_pipe_reg1_in ), |
| 1194 | .dout ( cam_vtb_sel_piped ), |
| 1195 | .reset(reset), |
| 1196 | .l1clk(l1clk), |
| 1197 | .siclk(siclk), |
| 1198 | .soclk(soclk)); |
| 1199 | |
| 1200 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_1 cam_vtb_sel_pipe_reg2 ( |
| 1201 | .scan_in(cam_vtb_sel_pipe_reg2_scanin), |
| 1202 | .scan_out(cam_vtb_sel_pipe_reg2_scanout), |
| 1203 | .din ( cam_vtb_sel_pipe_reg2_in ), |
| 1204 | .dout ( cam_vtb_sel_piped2 ), |
| 1205 | .reset(reset), |
| 1206 | .l1clk(l1clk), |
| 1207 | .siclk(siclk), |
| 1208 | .soclk(soclk)); |
| 1209 | |
| 1210 | assign cam_vtb_sel_pipe_reg1_in = reset_engine ? 1'b0: cam_vtb_sel; |
| 1211 | assign cam_vtb_sel_pipe_reg2_in = reset_engine ? 1'b0: cam_vtb_sel_piped; |
| 1212 | |
| 1213 | |
| 1214 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_1 vtb_lkup_en_pipe_reg1 ( |
| 1215 | .scan_in(vtb_lkup_en_pipe_reg1_scanin), |
| 1216 | .scan_out(vtb_lkup_en_pipe_reg1_scanout), |
| 1217 | .din ( vtb_lkup_en_pipe_reg1_in ), |
| 1218 | .dout ( vtb_lkup_en_piped ), |
| 1219 | .reset(reset), |
| 1220 | .l1clk(l1clk), |
| 1221 | .siclk(siclk), |
| 1222 | .soclk(soclk)); |
| 1223 | |
| 1224 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_1 vtb_lkup_en_pipe_reg2 ( |
| 1225 | .scan_in(vtb_lkup_en_pipe_reg2_scanin), |
| 1226 | .scan_out(vtb_lkup_en_pipe_reg2_scanout), |
| 1227 | .din ( vtb_lkup_en_pipe_reg2_in ), |
| 1228 | .dout ( vtb_lkup_en_piped2 ), |
| 1229 | .reset(reset), |
| 1230 | .l1clk(l1clk), |
| 1231 | .siclk(siclk), |
| 1232 | .soclk(soclk)); |
| 1233 | |
| 1234 | assign vtb_lkup_en_pipe_reg1_in = reset_engine ? 1'b0: dmu_cb0_mmu_vtb_lkup_en; |
| 1235 | assign vtb_lkup_en_pipe_reg2_in = reset_engine ? 1'b0: vtb_lkup_en_piped; |
| 1236 | |
| 1237 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_1 ptb_lkup_en_pipe_reg1 ( |
| 1238 | .scan_in(ptb_lkup_en_pipe_reg1_scanin), |
| 1239 | .scan_out(ptb_lkup_en_pipe_reg1_scanout), |
| 1240 | .din ( ptb_lkup_en_pipe_reg1_in ), |
| 1241 | .dout ( ptb_lkup_en_piped ), |
| 1242 | .reset(reset), |
| 1243 | .l1clk(l1clk), |
| 1244 | .siclk(siclk), |
| 1245 | .soclk(soclk)); |
| 1246 | |
| 1247 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_1 ptb_lkup_en_pipe_reg2 ( |
| 1248 | .scan_in(ptb_lkup_en_pipe_reg2_scanin), |
| 1249 | .scan_out(ptb_lkup_en_pipe_reg2_scanout), |
| 1250 | .din ( ptb_lkup_en_pipe_reg2_in ), |
| 1251 | .dout ( ptb_lkup_en_piped2 ), |
| 1252 | .reset(reset), |
| 1253 | .l1clk(l1clk), |
| 1254 | .siclk(siclk), |
| 1255 | .soclk(soclk)); |
| 1256 | |
| 1257 | assign ptb_lkup_en_pipe_reg1_in = reset_engine ? 1'b0: dmu_cb0_mmu_ptb_lkup_en; |
| 1258 | assign ptb_lkup_en_pipe_reg2_in = reset_engine ? 1'b0: ptb_lkup_en_piped; |
| 1259 | |
| 1260 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_3 ctest_pipe_reg1 ( |
| 1261 | .scan_in(ctest_pipe_reg1_scanin), |
| 1262 | .scan_out(ctest_pipe_reg1_scanout), |
| 1263 | .din ( ctest_pipe_reg1_in[2:0] ), |
| 1264 | .dout ( ctest_pipe_out1[2:0] ), |
| 1265 | .reset(reset), |
| 1266 | .l1clk(l1clk), |
| 1267 | .siclk(siclk), |
| 1268 | .soclk(soclk)); |
| 1269 | |
| 1270 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_3 ctest_pipe_reg2 ( |
| 1271 | .scan_in(ctest_pipe_reg2_scanin), |
| 1272 | .scan_out(ctest_pipe_reg2_scanout), |
| 1273 | .din ( ctest_pipe_reg2_in[2:0] ), |
| 1274 | .dout ( ctest_pipe_out2[2:0] ), |
| 1275 | .reset(reset), |
| 1276 | .l1clk(l1clk), |
| 1277 | .siclk(siclk), |
| 1278 | .soclk(soclk)); |
| 1279 | |
| 1280 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_3 ctest_pipe_reg3 ( |
| 1281 | .scan_in(ctest_pipe_reg3_scanin), |
| 1282 | .scan_out(ctest_pipe_reg3_scanout), |
| 1283 | .din ( ctest_pipe_reg3_in[2:0] ), |
| 1284 | .dout ( ctest_pipe_out3[2:0] ), |
| 1285 | .reset(reset), |
| 1286 | .l1clk(l1clk), |
| 1287 | .siclk(siclk), |
| 1288 | .soclk(soclk)); |
| 1289 | |
| 1290 | assign ctest_pipe_reg1_in[2:0] = reset_engine ? 3'b000: ctest[2:0]; |
| 1291 | assign ctest_pipe_reg2_in[2:0] = reset_engine ? 3'b000: ctest_pipe_out1[2:0]; |
| 1292 | assign ctest_pipe_reg3_in[2:0] = reset_engine ? 3'b000: ctest_pipe_out2[2:0]; |
| 1293 | |
| 1294 | assign ctest_piped3[2:0] = ctest_pipe_out3[2:0]; |
| 1295 | |
| 1296 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_3 crw_pipe_reg1 ( |
| 1297 | .scan_in(crw_pipe_reg1_scanin), |
| 1298 | .scan_out(crw_pipe_reg1_scanout), |
| 1299 | .din ( crw_pipe_reg1_in[2:0] ), |
| 1300 | .dout ( crw_pipe_out1[2:0] ), |
| 1301 | .reset(reset), |
| 1302 | .l1clk(l1clk), |
| 1303 | .siclk(siclk), |
| 1304 | .soclk(soclk)); |
| 1305 | |
| 1306 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_3 crw_pipe_reg2 ( |
| 1307 | .scan_in(crw_pipe_reg2_scanin), |
| 1308 | .scan_out(crw_pipe_reg2_scanout), |
| 1309 | .din ( crw_pipe_reg2_in[2:0] ), |
| 1310 | .dout ( crw_pipe_out2[2:0] ), |
| 1311 | .reset(reset), |
| 1312 | .l1clk(l1clk), |
| 1313 | .siclk(siclk), |
| 1314 | .soclk(soclk)); |
| 1315 | |
| 1316 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_3 crw_pipe_reg3 ( |
| 1317 | .scan_in(crw_pipe_reg3_scanin), |
| 1318 | .scan_out(crw_pipe_reg3_scanout), |
| 1319 | .din ( crw_pipe_reg3_in[2:0] ), |
| 1320 | .dout ( crw_pipe_out3[2:0] ), |
| 1321 | .reset(reset), |
| 1322 | .l1clk(l1clk), |
| 1323 | .siclk(siclk), |
| 1324 | .soclk(soclk)); |
| 1325 | |
| 1326 | assign crw_pipe_reg1_in[2:0] = reset_engine ? 3'b00: crw[2:0]; |
| 1327 | assign crw_pipe_reg2_in[2:0] = reset_engine ? 3'b00: crw_pipe_out1[2:0]; |
| 1328 | assign crw_pipe_reg3_in[2:0] = reset_engine ? 3'b00: crw_pipe_out2[2:0]; |
| 1329 | |
| 1330 | assign crw_piped3[2:0] = crw_pipe_out3[2:0]; |
| 1331 | |
| 1332 | // ///////////////////////////////////////////////////////////////////////////// |
| 1333 | // Shared Fail Detection |
| 1334 | // ///////////////////////////////////////////////////////////////////////////// |
| 1335 | // 05/10/05: Updated to meet these new features: |
| 1336 | // 1.When mbist_done signal is asserted when it completes all the |
| 1337 | // tests, it also need to assert static membist fail signal if |
| 1338 | // there were any failures during the tests. |
| 1339 | // 2.The mbist_fail signal won't be sticky bit from membist |
| 1340 | // engine. The TCU will make it sticky fail bit as needed. |
| 1341 | |
| 1342 | |
| 1343 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_2 fail_reg ( |
| 1344 | .scan_in(fail_reg_scanin), |
| 1345 | .scan_out(fail_reg_scanout), |
| 1346 | .din ( fail_reg_in[1:0] ), |
| 1347 | .dout ( fail_reg_out[1:0] ), |
| 1348 | .reset(reset), |
| 1349 | .l1clk(l1clk), |
| 1350 | .siclk(siclk), |
| 1351 | .soclk(soclk)); |
| 1352 | |
| 1353 | |
| 1354 | assign fail_reg_in[1:0] = reset_engine ? 2'b0: {qual_ptb_fail,qual_vtb_fail} | fail_reg_out[1:0]; |
| 1355 | |
| 1356 | assign qual_vtb_fail = fail_detect && vtb_rd_en_piped2; |
| 1357 | assign qual_ptb_fail = fail_detect && ptb_rd_en_piped2; |
| 1358 | |
| 1359 | assign fail = mbist_done ? (|fail_reg_out[1:0]) || (|cam_fail_reg_out[1:0]): |
| 1360 | qual_vtb_fail | qual_ptb_fail | qual_cam_vtb_fail | qual_cam_ptb_fail; |
| 1361 | |
| 1362 | |
| 1363 | // assign fail_detect = vtb_rd_en_piped2 ? |
| 1364 | // ({4{dmu_cb0_piped_data[7:0]} } != res_read_data_piped[31:0]): |
| 1365 | // ({ dmu_cb0_piped_data[0], {4{dmu_cb0_piped_data[7:0]}} } != res_read_data_piped[32:0]); |
| 1366 | |
| 1367 | assign fail_detect = ({ dmu_cb0_piped_data[0], {4{dmu_cb0_piped_data[7:0]}} } != res_read_data_piped[32:0]); |
| 1368 | |
| 1369 | // CAM Fail |
| 1370 | |
| 1371 | dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_2 cam_fail_reg ( |
| 1372 | .scan_in(cam_fail_reg_scanin), |
| 1373 | .scan_out(cam_fail_reg_scanout), |
| 1374 | .din ( cam_fail_reg_in[1:0] ), |
| 1375 | .dout ( cam_fail_reg_out[1:0] ), |
| 1376 | .reset(reset), |
| 1377 | .l1clk(l1clk), |
| 1378 | .siclk(siclk), |
| 1379 | .soclk(soclk)); |
| 1380 | |
| 1381 | |
| 1382 | assign cam_fail_reg_in[1:0] = reset_engine ? 2'b0: {qual_cam_ptb_fail,qual_cam_vtb_fail} | |
| 1383 | cam_fail_reg_out[1:0]; |
| 1384 | |
| 1385 | assign qual_cam_vtb_fail = cam_fail_detect && vtb_lkup_en_piped2; |
| 1386 | assign qual_cam_ptb_fail = cam_fail_detect && ptb_lkup_en_piped2; |
| 1387 | |
| 1388 | |
| 1389 | // integer i; |
| 1390 | reg [63:0] expct_res_hit_data_piped; |
| 1391 | |
| 1392 | // always@(dmu_cb0_piped_addr) |
| 1393 | // begin |
| 1394 | // for(i=0;i<64;i=i+1) |
| 1395 | // begin |
| 1396 | // if(i==(dmu_cb0_piped_addr[5:0])) |
| 1397 | // expct_res_hit_data_piped[i] = 1'b1; |
| 1398 | // else |
| 1399 | // expct_res_hit_data_piped[i] = 1'b0; |
| 1400 | // end |
| 1401 | //end |
| 1402 | |
| 1403 | always@ (dmu_cb0_piped_addr[5:0]) begin |
| 1404 | case (dmu_cb0_piped_addr[5:0]) //synopsys parallel_case full_case |
| 1405 | |
| 1406 | 6'h00 : expct_res_hit_data_piped = {63'b0, 1'b1}; |
| 1407 | 6'h01 : expct_res_hit_data_piped = {62'b0, 1'b1, 1'b0}; |
| 1408 | 6'h02 : expct_res_hit_data_piped = {61'b0, 1'b1, 2'b0}; |
| 1409 | 6'h03 : expct_res_hit_data_piped = {60'b0, 1'b1, 3'b0}; |
| 1410 | 6'h04 : expct_res_hit_data_piped = {59'b0, 1'b1, 4'b0}; |
| 1411 | 6'h05 : expct_res_hit_data_piped = {58'b0, 1'b1, 5'b0}; |
| 1412 | 6'h06 : expct_res_hit_data_piped = {57'b0, 1'b1, 6'b0}; |
| 1413 | 6'h07 : expct_res_hit_data_piped = {56'b0, 1'b1, 7'b0}; |
| 1414 | 6'h08 : expct_res_hit_data_piped = {55'b0, 1'b1, 8'b0}; |
| 1415 | 6'h09 : expct_res_hit_data_piped = {54'b0, 1'b1, 9'b0}; |
| 1416 | 6'h0A : expct_res_hit_data_piped = {53'b0, 1'b1, 10'b0}; |
| 1417 | 6'h0B : expct_res_hit_data_piped = {52'b0, 1'b1, 11'b0}; |
| 1418 | 6'h0C : expct_res_hit_data_piped = {51'b0, 1'b1, 12'b0}; |
| 1419 | 6'h0D : expct_res_hit_data_piped = {50'b0, 1'b1, 13'b0}; |
| 1420 | 6'h0E : expct_res_hit_data_piped = {49'b0, 1'b1, 14'b0}; |
| 1421 | 6'h0F : expct_res_hit_data_piped = {48'b0, 1'b1, 15'b0}; |
| 1422 | |
| 1423 | 6'h10 : expct_res_hit_data_piped = {47'b0, 1'b1, 16'b0}; |
| 1424 | 6'h11 : expct_res_hit_data_piped = {46'b0, 1'b1, 17'b0}; |
| 1425 | 6'h12 : expct_res_hit_data_piped = {45'b0, 1'b1, 18'b0}; |
| 1426 | 6'h13 : expct_res_hit_data_piped = {44'b0, 1'b1, 19'b0}; |
| 1427 | 6'h14 : expct_res_hit_data_piped = {43'b0, 1'b1, 20'b0}; |
| 1428 | 6'h15 : expct_res_hit_data_piped = {42'b0, 1'b1, 21'b0}; |
| 1429 | 6'h16 : expct_res_hit_data_piped = {41'b0, 1'b1, 22'b0}; |
| 1430 | 6'h17 : expct_res_hit_data_piped = {40'b0, 1'b1, 23'b0}; |
| 1431 | 6'h18 : expct_res_hit_data_piped = {39'b0, 1'b1, 24'b0}; |
| 1432 | 6'h19 : expct_res_hit_data_piped = {38'b0, 1'b1, 25'b0}; |
| 1433 | 6'h1A : expct_res_hit_data_piped = {37'b0, 1'b1, 26'b0}; |
| 1434 | 6'h1B : expct_res_hit_data_piped = {36'b0, 1'b1, 27'b0}; |
| 1435 | 6'h1C : expct_res_hit_data_piped = {35'b0, 1'b1, 28'b0}; |
| 1436 | 6'h1D : expct_res_hit_data_piped = {34'b0, 1'b1, 29'b0}; |
| 1437 | 6'h1E : expct_res_hit_data_piped = {33'b0, 1'b1, 30'b0}; |
| 1438 | 6'h1F : expct_res_hit_data_piped = {32'b0, 1'b1, 31'b0}; |
| 1439 | |
| 1440 | 6'h20 : expct_res_hit_data_piped = {31'b0, 1'b1, 32'b0}; |
| 1441 | 6'h21 : expct_res_hit_data_piped = {30'b0, 1'b1, 33'b0}; |
| 1442 | 6'h22 : expct_res_hit_data_piped = {29'b0, 1'b1, 34'b0}; |
| 1443 | 6'h23 : expct_res_hit_data_piped = {28'b0, 1'b1, 35'b0}; |
| 1444 | 6'h24 : expct_res_hit_data_piped = {27'b0, 1'b1, 36'b0}; |
| 1445 | 6'h25 : expct_res_hit_data_piped = {26'b0, 1'b1, 37'b0}; |
| 1446 | 6'h26 : expct_res_hit_data_piped = {25'b0, 1'b1, 38'b0}; |
| 1447 | 6'h27 : expct_res_hit_data_piped = {24'b0, 1'b1, 39'b0}; |
| 1448 | 6'h28 : expct_res_hit_data_piped = {23'b0, 1'b1, 40'b0}; |
| 1449 | 6'h29 : expct_res_hit_data_piped = {22'b0, 1'b1, 41'b0}; |
| 1450 | 6'h2A : expct_res_hit_data_piped = {21'b0, 1'b1, 42'b0}; |
| 1451 | 6'h2B : expct_res_hit_data_piped = {20'b0, 1'b1, 43'b0}; |
| 1452 | 6'h2C : expct_res_hit_data_piped = {19'b0, 1'b1, 44'b0}; |
| 1453 | 6'h2D : expct_res_hit_data_piped = {18'b0, 1'b1, 45'b0}; |
| 1454 | 6'h2E : expct_res_hit_data_piped = {17'b0, 1'b1, 46'b0}; |
| 1455 | 6'h2F : expct_res_hit_data_piped = {16'b0, 1'b1, 47'b0}; |
| 1456 | |
| 1457 | 6'h30 : expct_res_hit_data_piped = {15'b0, 1'b1, 48'b0}; |
| 1458 | 6'h31 : expct_res_hit_data_piped = {14'b0, 1'b1, 49'b0}; |
| 1459 | 6'h32 : expct_res_hit_data_piped = {13'b0, 1'b1, 50'b0}; |
| 1460 | 6'h33 : expct_res_hit_data_piped = {12'b0, 1'b1, 51'b0}; |
| 1461 | 6'h34 : expct_res_hit_data_piped = {11'b0, 1'b1, 52'b0}; |
| 1462 | 6'h35 : expct_res_hit_data_piped = {10'b0, 1'b1, 53'b0}; |
| 1463 | 6'h36 : expct_res_hit_data_piped = {9'b0, 1'b1, 54'b0}; |
| 1464 | 6'h37 : expct_res_hit_data_piped = {8'b0, 1'b1, 55'b0}; |
| 1465 | 6'h38 : expct_res_hit_data_piped = {7'b0, 1'b1, 56'b0}; |
| 1466 | 6'h39 : expct_res_hit_data_piped = {6'b0, 1'b1, 57'b0}; |
| 1467 | 6'h3A : expct_res_hit_data_piped = {5'b0, 1'b1, 58'b0}; |
| 1468 | 6'h3B : expct_res_hit_data_piped = {4'b0, 1'b1, 59'b0}; |
| 1469 | 6'h3C : expct_res_hit_data_piped = {3'b0, 1'b1, 60'b0}; |
| 1470 | 6'h3D : expct_res_hit_data_piped = {2'b0, 1'b1, 61'b0}; |
| 1471 | 6'h3E : expct_res_hit_data_piped = {1'b0, 1'b1, 62'b0}; |
| 1472 | default : expct_res_hit_data_piped = {1'b1, 63'b0}; |
| 1473 | |
| 1474 | endcase |
| 1475 | end |
| 1476 | |
| 1477 | assign cam_fail_detect = (( ctest_piped3[2:0] == 3'b000 ) | ( ctest_piped3[2:0] == 3'b001 )) ? |
| 1478 | //(( res_hit_data_piped[dmu_cb0_piped_addr] != 1'b1 ) & ( res_hit_data_piped[~dmu_cb0_piped_addr] != 1'b0 )) : |
| 1479 | (expct_res_hit_data_piped[63:0] != res_hit_data_piped[63:0]) : |
| 1480 | ( ctest_piped3[2:0] == 3'b010 ) & (( crw_piped3[2:0] == 3'b001 ) | ( crw_piped3[2:0] == 3'b010 )) ? |
| 1481 | (expct_res_hit_data_piped[63:0] != res_hit_data_piped[63:0]) : |
| 1482 | ( ctest_piped3[2:0] == 3'b010 ) & ( crw_piped3[2:0] == 3'b011 ) ? |
| 1483 | (~expct_res_hit_data_piped[63:0] != res_hit_data_piped[63:0]) : |
| 1484 | ( res_hit_data_piped[63:0] != 64'b0); |
| 1485 | |
| 1486 | |
| 1487 | // fixscan start: |
| 1488 | assign config_reg_scanin = scan_in ; |
| 1489 | assign user_data_reg_scanin = config_reg_scanout ; |
| 1490 | assign user_start_addr_reg_scanin = user_data_reg_scanout ; |
| 1491 | assign user_stop_addr_reg_scanin = user_start_addr_reg_scanout; |
| 1492 | assign user_incr_addr_reg_scanin = user_stop_addr_reg_scanout; |
| 1493 | assign user_array_sel_reg_scanin = user_incr_addr_reg_scanout; |
| 1494 | assign user_cam_mode_reg_scanin = user_array_sel_reg_scanout; |
| 1495 | assign user_cam_select_reg_scanin = user_cam_mode_reg_scanout; |
| 1496 | assign user_cam_test_select_reg_scanin = user_cam_select_reg_scanout; |
| 1497 | assign user_bisi_wr_reg_scanin = user_cam_test_select_reg_scanout; |
| 1498 | assign user_bisi_rd_reg_scanin = user_bisi_wr_reg_scanout ; |
| 1499 | assign start_transition_reg_scanin = user_bisi_rd_reg_scanout ; |
| 1500 | assign run_reg_scanin = start_transition_reg_scanout; |
| 1501 | assign run1_reg_scanin = run_reg_scanout ; |
| 1502 | assign run2_reg_scanin = run1_reg_scanout ; |
| 1503 | assign addr_reg_scanin = run2_reg_scanout ; |
| 1504 | assign key_reg_scanin = addr_reg_scanout ; |
| 1505 | assign wr_rd_en_reg_scanin = key_reg_scanout ; |
| 1506 | assign hld_reg_scanin = wr_rd_en_reg_scanout ; |
| 1507 | assign done_reg_scanin = hld_reg_scanout ; |
| 1508 | assign mbist_fail_reg_scanin = done_reg_scanout ; |
| 1509 | assign read_data_pipe_reg_scanin = mbist_fail_reg_scanout ; |
| 1510 | assign hit_data_pipe_reg_scanin = read_data_pipe_reg_scanout; |
| 1511 | assign control_reg_scanin = hit_data_pipe_reg_scanout; |
| 1512 | assign done_counter_reg_scanin = control_reg_scanout ; |
| 1513 | assign cam_cntl_reg_scanin = done_counter_reg_scanout ; |
| 1514 | assign addr_pipe_reg1_scanin = cam_cntl_reg_scanout ; |
| 1515 | assign addr_pipe_reg2_scanin = addr_pipe_reg1_scanout ; |
| 1516 | assign data_pipe_reg1_scanin = addr_pipe_reg2_scanout ; |
| 1517 | assign data_pipe_reg2_scanin = data_pipe_reg1_scanout ; |
| 1518 | assign vtb_sel_pipe_reg1_scanin = data_pipe_reg2_scanout ; |
| 1519 | assign vtb_sel_pipe_reg2_scanin = vtb_sel_pipe_reg1_scanout; |
| 1520 | assign vtb_ren_pipe_reg1_scanin = vtb_sel_pipe_reg2_scanout; |
| 1521 | assign vtb_ren_pipe_reg2_scanin = vtb_ren_pipe_reg1_scanout; |
| 1522 | assign ptb_ren_pipe_reg1_scanin = vtb_ren_pipe_reg2_scanout; |
| 1523 | assign ptb_ren_pipe_reg2_scanin = ptb_ren_pipe_reg1_scanout; |
| 1524 | assign cam_vtb_sel_pipe_reg1_scanin = ptb_ren_pipe_reg2_scanout; |
| 1525 | assign cam_vtb_sel_pipe_reg2_scanin = cam_vtb_sel_pipe_reg1_scanout; |
| 1526 | assign vtb_lkup_en_pipe_reg1_scanin = cam_vtb_sel_pipe_reg2_scanout; |
| 1527 | assign vtb_lkup_en_pipe_reg2_scanin = vtb_lkup_en_pipe_reg1_scanout; |
| 1528 | assign ptb_lkup_en_pipe_reg1_scanin = vtb_lkup_en_pipe_reg2_scanout; |
| 1529 | assign ptb_lkup_en_pipe_reg2_scanin = ptb_lkup_en_pipe_reg1_scanout; |
| 1530 | assign ctest_pipe_reg1_scanin = ptb_lkup_en_pipe_reg2_scanout; |
| 1531 | assign ctest_pipe_reg2_scanin = ctest_pipe_reg1_scanout ; |
| 1532 | assign ctest_pipe_reg3_scanin = ctest_pipe_reg2_scanout ; |
| 1533 | assign crw_pipe_reg1_scanin = ctest_pipe_reg3_scanout ; |
| 1534 | assign crw_pipe_reg2_scanin = crw_pipe_reg1_scanout ; |
| 1535 | assign crw_pipe_reg3_scanin = crw_pipe_reg2_scanout ; |
| 1536 | assign fail_reg_scanin = crw_pipe_reg3_scanout ; |
| 1537 | assign cam_fail_reg_scanin = fail_reg_scanout ; |
| 1538 | assign scan_out = cam_fail_reg_scanout ; |
| 1539 | // fixscan end: |
| 1540 | endmodule |
| 1541 | |
| 1542 | |
| 1543 | |
| 1544 | |
| 1545 | |
| 1546 | |
| 1547 | // any PARAMS parms go into naming of macro |
| 1548 | |
| 1549 | module dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_8 ( |
| 1550 | din, |
| 1551 | reset, |
| 1552 | l1clk, |
| 1553 | scan_in, |
| 1554 | siclk, |
| 1555 | soclk, |
| 1556 | dout, |
| 1557 | scan_out); |
| 1558 | wire [7:0] fdin; |
| 1559 | wire [7:1] sout; |
| 1560 | |
| 1561 | input [7:0] din; |
| 1562 | input reset; |
| 1563 | input l1clk; |
| 1564 | input scan_in; |
| 1565 | |
| 1566 | |
| 1567 | input siclk; |
| 1568 | input soclk; |
| 1569 | |
| 1570 | output [7:0] dout; |
| 1571 | output scan_out; |
| 1572 | assign fdin[7:0] = din[7:0] & {8 {reset}}; |
| 1573 | |
| 1574 | |
| 1575 | |
| 1576 | |
| 1577 | |
| 1578 | |
| 1579 | |
| 1580 | |
| 1581 | |
| 1582 | |
| 1583 | |
| 1584 | |
| 1585 | |
| 1586 | |
| 1587 | |
| 1588 | |
| 1589 | |
| 1590 | cl_a1_msff_syrst_4x d0_0 ( |
| 1591 | .l1clk(l1clk), |
| 1592 | .siclk(siclk), |
| 1593 | .soclk(soclk), |
| 1594 | .d(fdin[0]), |
| 1595 | .si(sout[1]), |
| 1596 | .so(scan_out), |
| 1597 | .reset(reset), |
| 1598 | .q(dout[0]) |
| 1599 | ); |
| 1600 | cl_a1_msff_syrst_4x d0_1 ( |
| 1601 | .l1clk(l1clk), |
| 1602 | .siclk(siclk), |
| 1603 | .soclk(soclk), |
| 1604 | .d(fdin[1]), |
| 1605 | .si(sout[2]), |
| 1606 | .so(sout[1]), |
| 1607 | .reset(reset), |
| 1608 | .q(dout[1]) |
| 1609 | ); |
| 1610 | cl_a1_msff_syrst_4x d0_2 ( |
| 1611 | .l1clk(l1clk), |
| 1612 | .siclk(siclk), |
| 1613 | .soclk(soclk), |
| 1614 | .d(fdin[2]), |
| 1615 | .si(sout[3]), |
| 1616 | .so(sout[2]), |
| 1617 | .reset(reset), |
| 1618 | .q(dout[2]) |
| 1619 | ); |
| 1620 | cl_a1_msff_syrst_4x d0_3 ( |
| 1621 | .l1clk(l1clk), |
| 1622 | .siclk(siclk), |
| 1623 | .soclk(soclk), |
| 1624 | .d(fdin[3]), |
| 1625 | .si(sout[4]), |
| 1626 | .so(sout[3]), |
| 1627 | .reset(reset), |
| 1628 | .q(dout[3]) |
| 1629 | ); |
| 1630 | cl_a1_msff_syrst_4x d0_4 ( |
| 1631 | .l1clk(l1clk), |
| 1632 | .siclk(siclk), |
| 1633 | .soclk(soclk), |
| 1634 | .d(fdin[4]), |
| 1635 | .si(sout[5]), |
| 1636 | .so(sout[4]), |
| 1637 | .reset(reset), |
| 1638 | .q(dout[4]) |
| 1639 | ); |
| 1640 | cl_a1_msff_syrst_4x d0_5 ( |
| 1641 | .l1clk(l1clk), |
| 1642 | .siclk(siclk), |
| 1643 | .soclk(soclk), |
| 1644 | .d(fdin[5]), |
| 1645 | .si(sout[6]), |
| 1646 | .so(sout[5]), |
| 1647 | .reset(reset), |
| 1648 | .q(dout[5]) |
| 1649 | ); |
| 1650 | cl_a1_msff_syrst_4x d0_6 ( |
| 1651 | .l1clk(l1clk), |
| 1652 | .siclk(siclk), |
| 1653 | .soclk(soclk), |
| 1654 | .d(fdin[6]), |
| 1655 | .si(sout[7]), |
| 1656 | .so(sout[6]), |
| 1657 | .reset(reset), |
| 1658 | .q(dout[6]) |
| 1659 | ); |
| 1660 | cl_a1_msff_syrst_4x d0_7 ( |
| 1661 | .l1clk(l1clk), |
| 1662 | .siclk(siclk), |
| 1663 | .soclk(soclk), |
| 1664 | .d(fdin[7]), |
| 1665 | .si(scan_in), |
| 1666 | .so(sout[7]), |
| 1667 | .reset(reset), |
| 1668 | .q(dout[7]) |
| 1669 | ); |
| 1670 | |
| 1671 | |
| 1672 | |
| 1673 | |
| 1674 | endmodule |
| 1675 | |
| 1676 | |
| 1677 | |
| 1678 | |
| 1679 | |
| 1680 | |
| 1681 | |
| 1682 | |
| 1683 | |
| 1684 | |
| 1685 | |
| 1686 | |
| 1687 | |
| 1688 | // any PARAMS parms go into naming of macro |
| 1689 | |
| 1690 | module dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_6 ( |
| 1691 | din, |
| 1692 | reset, |
| 1693 | l1clk, |
| 1694 | scan_in, |
| 1695 | siclk, |
| 1696 | soclk, |
| 1697 | dout, |
| 1698 | scan_out); |
| 1699 | wire [5:0] fdin; |
| 1700 | wire [5:1] sout; |
| 1701 | |
| 1702 | input [5:0] din; |
| 1703 | input reset; |
| 1704 | input l1clk; |
| 1705 | input scan_in; |
| 1706 | |
| 1707 | |
| 1708 | input siclk; |
| 1709 | input soclk; |
| 1710 | |
| 1711 | output [5:0] dout; |
| 1712 | output scan_out; |
| 1713 | assign fdin[5:0] = din[5:0] & {6 {reset}}; |
| 1714 | |
| 1715 | |
| 1716 | |
| 1717 | |
| 1718 | |
| 1719 | |
| 1720 | |
| 1721 | |
| 1722 | |
| 1723 | |
| 1724 | |
| 1725 | |
| 1726 | |
| 1727 | |
| 1728 | |
| 1729 | |
| 1730 | |
| 1731 | cl_a1_msff_syrst_4x d0_0 ( |
| 1732 | .l1clk(l1clk), |
| 1733 | .siclk(siclk), |
| 1734 | .soclk(soclk), |
| 1735 | .d(fdin[0]), |
| 1736 | .si(sout[1]), |
| 1737 | .so(scan_out), |
| 1738 | .reset(reset), |
| 1739 | .q(dout[0]) |
| 1740 | ); |
| 1741 | cl_a1_msff_syrst_4x d0_1 ( |
| 1742 | .l1clk(l1clk), |
| 1743 | .siclk(siclk), |
| 1744 | .soclk(soclk), |
| 1745 | .d(fdin[1]), |
| 1746 | .si(sout[2]), |
| 1747 | .so(sout[1]), |
| 1748 | .reset(reset), |
| 1749 | .q(dout[1]) |
| 1750 | ); |
| 1751 | cl_a1_msff_syrst_4x d0_2 ( |
| 1752 | .l1clk(l1clk), |
| 1753 | .siclk(siclk), |
| 1754 | .soclk(soclk), |
| 1755 | .d(fdin[2]), |
| 1756 | .si(sout[3]), |
| 1757 | .so(sout[2]), |
| 1758 | .reset(reset), |
| 1759 | .q(dout[2]) |
| 1760 | ); |
| 1761 | cl_a1_msff_syrst_4x d0_3 ( |
| 1762 | .l1clk(l1clk), |
| 1763 | .siclk(siclk), |
| 1764 | .soclk(soclk), |
| 1765 | .d(fdin[3]), |
| 1766 | .si(sout[4]), |
| 1767 | .so(sout[3]), |
| 1768 | .reset(reset), |
| 1769 | .q(dout[3]) |
| 1770 | ); |
| 1771 | cl_a1_msff_syrst_4x d0_4 ( |
| 1772 | .l1clk(l1clk), |
| 1773 | .siclk(siclk), |
| 1774 | .soclk(soclk), |
| 1775 | .d(fdin[4]), |
| 1776 | .si(sout[5]), |
| 1777 | .so(sout[4]), |
| 1778 | .reset(reset), |
| 1779 | .q(dout[4]) |
| 1780 | ); |
| 1781 | cl_a1_msff_syrst_4x d0_5 ( |
| 1782 | .l1clk(l1clk), |
| 1783 | .siclk(siclk), |
| 1784 | .soclk(soclk), |
| 1785 | .d(fdin[5]), |
| 1786 | .si(scan_in), |
| 1787 | .so(sout[5]), |
| 1788 | .reset(reset), |
| 1789 | .q(dout[5]) |
| 1790 | ); |
| 1791 | |
| 1792 | |
| 1793 | |
| 1794 | |
| 1795 | endmodule |
| 1796 | |
| 1797 | |
| 1798 | |
| 1799 | |
| 1800 | |
| 1801 | |
| 1802 | |
| 1803 | |
| 1804 | |
| 1805 | |
| 1806 | |
| 1807 | |
| 1808 | |
| 1809 | // any PARAMS parms go into naming of macro |
| 1810 | |
| 1811 | module dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_1 ( |
| 1812 | din, |
| 1813 | reset, |
| 1814 | l1clk, |
| 1815 | scan_in, |
| 1816 | siclk, |
| 1817 | soclk, |
| 1818 | dout, |
| 1819 | scan_out); |
| 1820 | wire [0:0] fdin; |
| 1821 | |
| 1822 | input [0:0] din; |
| 1823 | input reset; |
| 1824 | input l1clk; |
| 1825 | input scan_in; |
| 1826 | |
| 1827 | |
| 1828 | input siclk; |
| 1829 | input soclk; |
| 1830 | |
| 1831 | output [0:0] dout; |
| 1832 | output scan_out; |
| 1833 | assign fdin[0:0] = din[0:0] & {1 {reset}}; |
| 1834 | |
| 1835 | |
| 1836 | |
| 1837 | |
| 1838 | |
| 1839 | |
| 1840 | |
| 1841 | |
| 1842 | |
| 1843 | |
| 1844 | |
| 1845 | |
| 1846 | |
| 1847 | |
| 1848 | |
| 1849 | |
| 1850 | |
| 1851 | cl_a1_msff_syrst_4x d0_0 ( |
| 1852 | .l1clk(l1clk), |
| 1853 | .siclk(siclk), |
| 1854 | .soclk(soclk), |
| 1855 | .d(fdin[0]), |
| 1856 | .si(scan_in), |
| 1857 | .so(scan_out), |
| 1858 | .reset(reset), |
| 1859 | .q(dout[0]) |
| 1860 | ); |
| 1861 | |
| 1862 | |
| 1863 | |
| 1864 | |
| 1865 | endmodule |
| 1866 | |
| 1867 | |
| 1868 | |
| 1869 | |
| 1870 | |
| 1871 | |
| 1872 | |
| 1873 | |
| 1874 | |
| 1875 | |
| 1876 | |
| 1877 | |
| 1878 | |
| 1879 | // any PARAMS parms go into naming of macro |
| 1880 | |
| 1881 | module dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_3 ( |
| 1882 | din, |
| 1883 | reset, |
| 1884 | l1clk, |
| 1885 | scan_in, |
| 1886 | siclk, |
| 1887 | soclk, |
| 1888 | dout, |
| 1889 | scan_out); |
| 1890 | wire [2:0] fdin; |
| 1891 | wire [2:1] sout; |
| 1892 | |
| 1893 | input [2:0] din; |
| 1894 | input reset; |
| 1895 | input l1clk; |
| 1896 | input scan_in; |
| 1897 | |
| 1898 | |
| 1899 | input siclk; |
| 1900 | input soclk; |
| 1901 | |
| 1902 | output [2:0] dout; |
| 1903 | output scan_out; |
| 1904 | assign fdin[2:0] = din[2:0] & {3 {reset}}; |
| 1905 | |
| 1906 | |
| 1907 | |
| 1908 | |
| 1909 | |
| 1910 | |
| 1911 | |
| 1912 | |
| 1913 | |
| 1914 | |
| 1915 | |
| 1916 | |
| 1917 | |
| 1918 | |
| 1919 | |
| 1920 | |
| 1921 | |
| 1922 | cl_a1_msff_syrst_4x d0_0 ( |
| 1923 | .l1clk(l1clk), |
| 1924 | .siclk(siclk), |
| 1925 | .soclk(soclk), |
| 1926 | .d(fdin[0]), |
| 1927 | .si(sout[1]), |
| 1928 | .so(scan_out), |
| 1929 | .reset(reset), |
| 1930 | .q(dout[0]) |
| 1931 | ); |
| 1932 | cl_a1_msff_syrst_4x d0_1 ( |
| 1933 | .l1clk(l1clk), |
| 1934 | .siclk(siclk), |
| 1935 | .soclk(soclk), |
| 1936 | .d(fdin[1]), |
| 1937 | .si(sout[2]), |
| 1938 | .so(sout[1]), |
| 1939 | .reset(reset), |
| 1940 | .q(dout[1]) |
| 1941 | ); |
| 1942 | cl_a1_msff_syrst_4x d0_2 ( |
| 1943 | .l1clk(l1clk), |
| 1944 | .siclk(siclk), |
| 1945 | .soclk(soclk), |
| 1946 | .d(fdin[2]), |
| 1947 | .si(scan_in), |
| 1948 | .so(sout[2]), |
| 1949 | .reset(reset), |
| 1950 | .q(dout[2]) |
| 1951 | ); |
| 1952 | |
| 1953 | |
| 1954 | |
| 1955 | |
| 1956 | endmodule |
| 1957 | |
| 1958 | |
| 1959 | |
| 1960 | |
| 1961 | |
| 1962 | |
| 1963 | |
| 1964 | |
| 1965 | |
| 1966 | |
| 1967 | |
| 1968 | |
| 1969 | |
| 1970 | // any PARAMS parms go into naming of macro |
| 1971 | |
| 1972 | module dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_33 ( |
| 1973 | din, |
| 1974 | reset, |
| 1975 | l1clk, |
| 1976 | scan_in, |
| 1977 | siclk, |
| 1978 | soclk, |
| 1979 | dout, |
| 1980 | scan_out); |
| 1981 | wire [32:0] fdin; |
| 1982 | wire [32:1] sout; |
| 1983 | |
| 1984 | input [32:0] din; |
| 1985 | input reset; |
| 1986 | input l1clk; |
| 1987 | input scan_in; |
| 1988 | |
| 1989 | |
| 1990 | input siclk; |
| 1991 | input soclk; |
| 1992 | |
| 1993 | output [32:0] dout; |
| 1994 | output scan_out; |
| 1995 | assign fdin[32:0] = din[32:0] & {33 {reset}}; |
| 1996 | |
| 1997 | |
| 1998 | |
| 1999 | |
| 2000 | |
| 2001 | |
| 2002 | |
| 2003 | |
| 2004 | |
| 2005 | |
| 2006 | |
| 2007 | |
| 2008 | |
| 2009 | |
| 2010 | |
| 2011 | |
| 2012 | |
| 2013 | cl_a1_msff_syrst_4x d0_0 ( |
| 2014 | .l1clk(l1clk), |
| 2015 | .siclk(siclk), |
| 2016 | .soclk(soclk), |
| 2017 | .d(fdin[0]), |
| 2018 | .si(sout[1]), |
| 2019 | .so(scan_out), |
| 2020 | .reset(reset), |
| 2021 | .q(dout[0]) |
| 2022 | ); |
| 2023 | cl_a1_msff_syrst_4x d0_1 ( |
| 2024 | .l1clk(l1clk), |
| 2025 | .siclk(siclk), |
| 2026 | .soclk(soclk), |
| 2027 | .d(fdin[1]), |
| 2028 | .si(sout[2]), |
| 2029 | .so(sout[1]), |
| 2030 | .reset(reset), |
| 2031 | .q(dout[1]) |
| 2032 | ); |
| 2033 | cl_a1_msff_syrst_4x d0_2 ( |
| 2034 | .l1clk(l1clk), |
| 2035 | .siclk(siclk), |
| 2036 | .soclk(soclk), |
| 2037 | .d(fdin[2]), |
| 2038 | .si(sout[3]), |
| 2039 | .so(sout[2]), |
| 2040 | .reset(reset), |
| 2041 | .q(dout[2]) |
| 2042 | ); |
| 2043 | cl_a1_msff_syrst_4x d0_3 ( |
| 2044 | .l1clk(l1clk), |
| 2045 | .siclk(siclk), |
| 2046 | .soclk(soclk), |
| 2047 | .d(fdin[3]), |
| 2048 | .si(sout[4]), |
| 2049 | .so(sout[3]), |
| 2050 | .reset(reset), |
| 2051 | .q(dout[3]) |
| 2052 | ); |
| 2053 | cl_a1_msff_syrst_4x d0_4 ( |
| 2054 | .l1clk(l1clk), |
| 2055 | .siclk(siclk), |
| 2056 | .soclk(soclk), |
| 2057 | .d(fdin[4]), |
| 2058 | .si(sout[5]), |
| 2059 | .so(sout[4]), |
| 2060 | .reset(reset), |
| 2061 | .q(dout[4]) |
| 2062 | ); |
| 2063 | cl_a1_msff_syrst_4x d0_5 ( |
| 2064 | .l1clk(l1clk), |
| 2065 | .siclk(siclk), |
| 2066 | .soclk(soclk), |
| 2067 | .d(fdin[5]), |
| 2068 | .si(sout[6]), |
| 2069 | .so(sout[5]), |
| 2070 | .reset(reset), |
| 2071 | .q(dout[5]) |
| 2072 | ); |
| 2073 | cl_a1_msff_syrst_4x d0_6 ( |
| 2074 | .l1clk(l1clk), |
| 2075 | .siclk(siclk), |
| 2076 | .soclk(soclk), |
| 2077 | .d(fdin[6]), |
| 2078 | .si(sout[7]), |
| 2079 | .so(sout[6]), |
| 2080 | .reset(reset), |
| 2081 | .q(dout[6]) |
| 2082 | ); |
| 2083 | cl_a1_msff_syrst_4x d0_7 ( |
| 2084 | .l1clk(l1clk), |
| 2085 | .siclk(siclk), |
| 2086 | .soclk(soclk), |
| 2087 | .d(fdin[7]), |
| 2088 | .si(sout[8]), |
| 2089 | .so(sout[7]), |
| 2090 | .reset(reset), |
| 2091 | .q(dout[7]) |
| 2092 | ); |
| 2093 | cl_a1_msff_syrst_4x d0_8 ( |
| 2094 | .l1clk(l1clk), |
| 2095 | .siclk(siclk), |
| 2096 | .soclk(soclk), |
| 2097 | .d(fdin[8]), |
| 2098 | .si(sout[9]), |
| 2099 | .so(sout[8]), |
| 2100 | .reset(reset), |
| 2101 | .q(dout[8]) |
| 2102 | ); |
| 2103 | cl_a1_msff_syrst_4x d0_9 ( |
| 2104 | .l1clk(l1clk), |
| 2105 | .siclk(siclk), |
| 2106 | .soclk(soclk), |
| 2107 | .d(fdin[9]), |
| 2108 | .si(sout[10]), |
| 2109 | .so(sout[9]), |
| 2110 | .reset(reset), |
| 2111 | .q(dout[9]) |
| 2112 | ); |
| 2113 | cl_a1_msff_syrst_4x d0_10 ( |
| 2114 | .l1clk(l1clk), |
| 2115 | .siclk(siclk), |
| 2116 | .soclk(soclk), |
| 2117 | .d(fdin[10]), |
| 2118 | .si(sout[11]), |
| 2119 | .so(sout[10]), |
| 2120 | .reset(reset), |
| 2121 | .q(dout[10]) |
| 2122 | ); |
| 2123 | cl_a1_msff_syrst_4x d0_11 ( |
| 2124 | .l1clk(l1clk), |
| 2125 | .siclk(siclk), |
| 2126 | .soclk(soclk), |
| 2127 | .d(fdin[11]), |
| 2128 | .si(sout[12]), |
| 2129 | .so(sout[11]), |
| 2130 | .reset(reset), |
| 2131 | .q(dout[11]) |
| 2132 | ); |
| 2133 | cl_a1_msff_syrst_4x d0_12 ( |
| 2134 | .l1clk(l1clk), |
| 2135 | .siclk(siclk), |
| 2136 | .soclk(soclk), |
| 2137 | .d(fdin[12]), |
| 2138 | .si(sout[13]), |
| 2139 | .so(sout[12]), |
| 2140 | .reset(reset), |
| 2141 | .q(dout[12]) |
| 2142 | ); |
| 2143 | cl_a1_msff_syrst_4x d0_13 ( |
| 2144 | .l1clk(l1clk), |
| 2145 | .siclk(siclk), |
| 2146 | .soclk(soclk), |
| 2147 | .d(fdin[13]), |
| 2148 | .si(sout[14]), |
| 2149 | .so(sout[13]), |
| 2150 | .reset(reset), |
| 2151 | .q(dout[13]) |
| 2152 | ); |
| 2153 | cl_a1_msff_syrst_4x d0_14 ( |
| 2154 | .l1clk(l1clk), |
| 2155 | .siclk(siclk), |
| 2156 | .soclk(soclk), |
| 2157 | .d(fdin[14]), |
| 2158 | .si(sout[15]), |
| 2159 | .so(sout[14]), |
| 2160 | .reset(reset), |
| 2161 | .q(dout[14]) |
| 2162 | ); |
| 2163 | cl_a1_msff_syrst_4x d0_15 ( |
| 2164 | .l1clk(l1clk), |
| 2165 | .siclk(siclk), |
| 2166 | .soclk(soclk), |
| 2167 | .d(fdin[15]), |
| 2168 | .si(sout[16]), |
| 2169 | .so(sout[15]), |
| 2170 | .reset(reset), |
| 2171 | .q(dout[15]) |
| 2172 | ); |
| 2173 | cl_a1_msff_syrst_4x d0_16 ( |
| 2174 | .l1clk(l1clk), |
| 2175 | .siclk(siclk), |
| 2176 | .soclk(soclk), |
| 2177 | .d(fdin[16]), |
| 2178 | .si(sout[17]), |
| 2179 | .so(sout[16]), |
| 2180 | .reset(reset), |
| 2181 | .q(dout[16]) |
| 2182 | ); |
| 2183 | cl_a1_msff_syrst_4x d0_17 ( |
| 2184 | .l1clk(l1clk), |
| 2185 | .siclk(siclk), |
| 2186 | .soclk(soclk), |
| 2187 | .d(fdin[17]), |
| 2188 | .si(sout[18]), |
| 2189 | .so(sout[17]), |
| 2190 | .reset(reset), |
| 2191 | .q(dout[17]) |
| 2192 | ); |
| 2193 | cl_a1_msff_syrst_4x d0_18 ( |
| 2194 | .l1clk(l1clk), |
| 2195 | .siclk(siclk), |
| 2196 | .soclk(soclk), |
| 2197 | .d(fdin[18]), |
| 2198 | .si(sout[19]), |
| 2199 | .so(sout[18]), |
| 2200 | .reset(reset), |
| 2201 | .q(dout[18]) |
| 2202 | ); |
| 2203 | cl_a1_msff_syrst_4x d0_19 ( |
| 2204 | .l1clk(l1clk), |
| 2205 | .siclk(siclk), |
| 2206 | .soclk(soclk), |
| 2207 | .d(fdin[19]), |
| 2208 | .si(sout[20]), |
| 2209 | .so(sout[19]), |
| 2210 | .reset(reset), |
| 2211 | .q(dout[19]) |
| 2212 | ); |
| 2213 | cl_a1_msff_syrst_4x d0_20 ( |
| 2214 | .l1clk(l1clk), |
| 2215 | .siclk(siclk), |
| 2216 | .soclk(soclk), |
| 2217 | .d(fdin[20]), |
| 2218 | .si(sout[21]), |
| 2219 | .so(sout[20]), |
| 2220 | .reset(reset), |
| 2221 | .q(dout[20]) |
| 2222 | ); |
| 2223 | cl_a1_msff_syrst_4x d0_21 ( |
| 2224 | .l1clk(l1clk), |
| 2225 | .siclk(siclk), |
| 2226 | .soclk(soclk), |
| 2227 | .d(fdin[21]), |
| 2228 | .si(sout[22]), |
| 2229 | .so(sout[21]), |
| 2230 | .reset(reset), |
| 2231 | .q(dout[21]) |
| 2232 | ); |
| 2233 | cl_a1_msff_syrst_4x d0_22 ( |
| 2234 | .l1clk(l1clk), |
| 2235 | .siclk(siclk), |
| 2236 | .soclk(soclk), |
| 2237 | .d(fdin[22]), |
| 2238 | .si(sout[23]), |
| 2239 | .so(sout[22]), |
| 2240 | .reset(reset), |
| 2241 | .q(dout[22]) |
| 2242 | ); |
| 2243 | cl_a1_msff_syrst_4x d0_23 ( |
| 2244 | .l1clk(l1clk), |
| 2245 | .siclk(siclk), |
| 2246 | .soclk(soclk), |
| 2247 | .d(fdin[23]), |
| 2248 | .si(sout[24]), |
| 2249 | .so(sout[23]), |
| 2250 | .reset(reset), |
| 2251 | .q(dout[23]) |
| 2252 | ); |
| 2253 | cl_a1_msff_syrst_4x d0_24 ( |
| 2254 | .l1clk(l1clk), |
| 2255 | .siclk(siclk), |
| 2256 | .soclk(soclk), |
| 2257 | .d(fdin[24]), |
| 2258 | .si(sout[25]), |
| 2259 | .so(sout[24]), |
| 2260 | .reset(reset), |
| 2261 | .q(dout[24]) |
| 2262 | ); |
| 2263 | cl_a1_msff_syrst_4x d0_25 ( |
| 2264 | .l1clk(l1clk), |
| 2265 | .siclk(siclk), |
| 2266 | .soclk(soclk), |
| 2267 | .d(fdin[25]), |
| 2268 | .si(sout[26]), |
| 2269 | .so(sout[25]), |
| 2270 | .reset(reset), |
| 2271 | .q(dout[25]) |
| 2272 | ); |
| 2273 | cl_a1_msff_syrst_4x d0_26 ( |
| 2274 | .l1clk(l1clk), |
| 2275 | .siclk(siclk), |
| 2276 | .soclk(soclk), |
| 2277 | .d(fdin[26]), |
| 2278 | .si(sout[27]), |
| 2279 | .so(sout[26]), |
| 2280 | .reset(reset), |
| 2281 | .q(dout[26]) |
| 2282 | ); |
| 2283 | cl_a1_msff_syrst_4x d0_27 ( |
| 2284 | .l1clk(l1clk), |
| 2285 | .siclk(siclk), |
| 2286 | .soclk(soclk), |
| 2287 | .d(fdin[27]), |
| 2288 | .si(sout[28]), |
| 2289 | .so(sout[27]), |
| 2290 | .reset(reset), |
| 2291 | .q(dout[27]) |
| 2292 | ); |
| 2293 | cl_a1_msff_syrst_4x d0_28 ( |
| 2294 | .l1clk(l1clk), |
| 2295 | .siclk(siclk), |
| 2296 | .soclk(soclk), |
| 2297 | .d(fdin[28]), |
| 2298 | .si(sout[29]), |
| 2299 | .so(sout[28]), |
| 2300 | .reset(reset), |
| 2301 | .q(dout[28]) |
| 2302 | ); |
| 2303 | cl_a1_msff_syrst_4x d0_29 ( |
| 2304 | .l1clk(l1clk), |
| 2305 | .siclk(siclk), |
| 2306 | .soclk(soclk), |
| 2307 | .d(fdin[29]), |
| 2308 | .si(sout[30]), |
| 2309 | .so(sout[29]), |
| 2310 | .reset(reset), |
| 2311 | .q(dout[29]) |
| 2312 | ); |
| 2313 | cl_a1_msff_syrst_4x d0_30 ( |
| 2314 | .l1clk(l1clk), |
| 2315 | .siclk(siclk), |
| 2316 | .soclk(soclk), |
| 2317 | .d(fdin[30]), |
| 2318 | .si(sout[31]), |
| 2319 | .so(sout[30]), |
| 2320 | .reset(reset), |
| 2321 | .q(dout[30]) |
| 2322 | ); |
| 2323 | cl_a1_msff_syrst_4x d0_31 ( |
| 2324 | .l1clk(l1clk), |
| 2325 | .siclk(siclk), |
| 2326 | .soclk(soclk), |
| 2327 | .d(fdin[31]), |
| 2328 | .si(sout[32]), |
| 2329 | .so(sout[31]), |
| 2330 | .reset(reset), |
| 2331 | .q(dout[31]) |
| 2332 | ); |
| 2333 | cl_a1_msff_syrst_4x d0_32 ( |
| 2334 | .l1clk(l1clk), |
| 2335 | .siclk(siclk), |
| 2336 | .soclk(soclk), |
| 2337 | .d(fdin[32]), |
| 2338 | .si(scan_in), |
| 2339 | .so(sout[32]), |
| 2340 | .reset(reset), |
| 2341 | .q(dout[32]) |
| 2342 | ); |
| 2343 | |
| 2344 | |
| 2345 | |
| 2346 | |
| 2347 | endmodule |
| 2348 | |
| 2349 | |
| 2350 | |
| 2351 | |
| 2352 | |
| 2353 | |
| 2354 | |
| 2355 | |
| 2356 | |
| 2357 | |
| 2358 | |
| 2359 | |
| 2360 | |
| 2361 | // any PARAMS parms go into naming of macro |
| 2362 | |
| 2363 | module dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_64 ( |
| 2364 | din, |
| 2365 | reset, |
| 2366 | l1clk, |
| 2367 | scan_in, |
| 2368 | siclk, |
| 2369 | soclk, |
| 2370 | dout, |
| 2371 | scan_out); |
| 2372 | wire [63:0] fdin; |
| 2373 | wire [63:1] sout; |
| 2374 | |
| 2375 | input [63:0] din; |
| 2376 | input reset; |
| 2377 | input l1clk; |
| 2378 | input scan_in; |
| 2379 | |
| 2380 | |
| 2381 | input siclk; |
| 2382 | input soclk; |
| 2383 | |
| 2384 | output [63:0] dout; |
| 2385 | output scan_out; |
| 2386 | assign fdin[63:0] = din[63:0] & {64 {reset}}; |
| 2387 | |
| 2388 | |
| 2389 | |
| 2390 | |
| 2391 | |
| 2392 | |
| 2393 | |
| 2394 | |
| 2395 | |
| 2396 | |
| 2397 | |
| 2398 | |
| 2399 | |
| 2400 | |
| 2401 | |
| 2402 | |
| 2403 | |
| 2404 | cl_a1_msff_syrst_4x d0_0 ( |
| 2405 | .l1clk(l1clk), |
| 2406 | .siclk(siclk), |
| 2407 | .soclk(soclk), |
| 2408 | .d(fdin[0]), |
| 2409 | .si(sout[1]), |
| 2410 | .so(scan_out), |
| 2411 | .reset(reset), |
| 2412 | .q(dout[0]) |
| 2413 | ); |
| 2414 | cl_a1_msff_syrst_4x d0_1 ( |
| 2415 | .l1clk(l1clk), |
| 2416 | .siclk(siclk), |
| 2417 | .soclk(soclk), |
| 2418 | .d(fdin[1]), |
| 2419 | .si(sout[2]), |
| 2420 | .so(sout[1]), |
| 2421 | .reset(reset), |
| 2422 | .q(dout[1]) |
| 2423 | ); |
| 2424 | cl_a1_msff_syrst_4x d0_2 ( |
| 2425 | .l1clk(l1clk), |
| 2426 | .siclk(siclk), |
| 2427 | .soclk(soclk), |
| 2428 | .d(fdin[2]), |
| 2429 | .si(sout[3]), |
| 2430 | .so(sout[2]), |
| 2431 | .reset(reset), |
| 2432 | .q(dout[2]) |
| 2433 | ); |
| 2434 | cl_a1_msff_syrst_4x d0_3 ( |
| 2435 | .l1clk(l1clk), |
| 2436 | .siclk(siclk), |
| 2437 | .soclk(soclk), |
| 2438 | .d(fdin[3]), |
| 2439 | .si(sout[4]), |
| 2440 | .so(sout[3]), |
| 2441 | .reset(reset), |
| 2442 | .q(dout[3]) |
| 2443 | ); |
| 2444 | cl_a1_msff_syrst_4x d0_4 ( |
| 2445 | .l1clk(l1clk), |
| 2446 | .siclk(siclk), |
| 2447 | .soclk(soclk), |
| 2448 | .d(fdin[4]), |
| 2449 | .si(sout[5]), |
| 2450 | .so(sout[4]), |
| 2451 | .reset(reset), |
| 2452 | .q(dout[4]) |
| 2453 | ); |
| 2454 | cl_a1_msff_syrst_4x d0_5 ( |
| 2455 | .l1clk(l1clk), |
| 2456 | .siclk(siclk), |
| 2457 | .soclk(soclk), |
| 2458 | .d(fdin[5]), |
| 2459 | .si(sout[6]), |
| 2460 | .so(sout[5]), |
| 2461 | .reset(reset), |
| 2462 | .q(dout[5]) |
| 2463 | ); |
| 2464 | cl_a1_msff_syrst_4x d0_6 ( |
| 2465 | .l1clk(l1clk), |
| 2466 | .siclk(siclk), |
| 2467 | .soclk(soclk), |
| 2468 | .d(fdin[6]), |
| 2469 | .si(sout[7]), |
| 2470 | .so(sout[6]), |
| 2471 | .reset(reset), |
| 2472 | .q(dout[6]) |
| 2473 | ); |
| 2474 | cl_a1_msff_syrst_4x d0_7 ( |
| 2475 | .l1clk(l1clk), |
| 2476 | .siclk(siclk), |
| 2477 | .soclk(soclk), |
| 2478 | .d(fdin[7]), |
| 2479 | .si(sout[8]), |
| 2480 | .so(sout[7]), |
| 2481 | .reset(reset), |
| 2482 | .q(dout[7]) |
| 2483 | ); |
| 2484 | cl_a1_msff_syrst_4x d0_8 ( |
| 2485 | .l1clk(l1clk), |
| 2486 | .siclk(siclk), |
| 2487 | .soclk(soclk), |
| 2488 | .d(fdin[8]), |
| 2489 | .si(sout[9]), |
| 2490 | .so(sout[8]), |
| 2491 | .reset(reset), |
| 2492 | .q(dout[8]) |
| 2493 | ); |
| 2494 | cl_a1_msff_syrst_4x d0_9 ( |
| 2495 | .l1clk(l1clk), |
| 2496 | .siclk(siclk), |
| 2497 | .soclk(soclk), |
| 2498 | .d(fdin[9]), |
| 2499 | .si(sout[10]), |
| 2500 | .so(sout[9]), |
| 2501 | .reset(reset), |
| 2502 | .q(dout[9]) |
| 2503 | ); |
| 2504 | cl_a1_msff_syrst_4x d0_10 ( |
| 2505 | .l1clk(l1clk), |
| 2506 | .siclk(siclk), |
| 2507 | .soclk(soclk), |
| 2508 | .d(fdin[10]), |
| 2509 | .si(sout[11]), |
| 2510 | .so(sout[10]), |
| 2511 | .reset(reset), |
| 2512 | .q(dout[10]) |
| 2513 | ); |
| 2514 | cl_a1_msff_syrst_4x d0_11 ( |
| 2515 | .l1clk(l1clk), |
| 2516 | .siclk(siclk), |
| 2517 | .soclk(soclk), |
| 2518 | .d(fdin[11]), |
| 2519 | .si(sout[12]), |
| 2520 | .so(sout[11]), |
| 2521 | .reset(reset), |
| 2522 | .q(dout[11]) |
| 2523 | ); |
| 2524 | cl_a1_msff_syrst_4x d0_12 ( |
| 2525 | .l1clk(l1clk), |
| 2526 | .siclk(siclk), |
| 2527 | .soclk(soclk), |
| 2528 | .d(fdin[12]), |
| 2529 | .si(sout[13]), |
| 2530 | .so(sout[12]), |
| 2531 | .reset(reset), |
| 2532 | .q(dout[12]) |
| 2533 | ); |
| 2534 | cl_a1_msff_syrst_4x d0_13 ( |
| 2535 | .l1clk(l1clk), |
| 2536 | .siclk(siclk), |
| 2537 | .soclk(soclk), |
| 2538 | .d(fdin[13]), |
| 2539 | .si(sout[14]), |
| 2540 | .so(sout[13]), |
| 2541 | .reset(reset), |
| 2542 | .q(dout[13]) |
| 2543 | ); |
| 2544 | cl_a1_msff_syrst_4x d0_14 ( |
| 2545 | .l1clk(l1clk), |
| 2546 | .siclk(siclk), |
| 2547 | .soclk(soclk), |
| 2548 | .d(fdin[14]), |
| 2549 | .si(sout[15]), |
| 2550 | .so(sout[14]), |
| 2551 | .reset(reset), |
| 2552 | .q(dout[14]) |
| 2553 | ); |
| 2554 | cl_a1_msff_syrst_4x d0_15 ( |
| 2555 | .l1clk(l1clk), |
| 2556 | .siclk(siclk), |
| 2557 | .soclk(soclk), |
| 2558 | .d(fdin[15]), |
| 2559 | .si(sout[16]), |
| 2560 | .so(sout[15]), |
| 2561 | .reset(reset), |
| 2562 | .q(dout[15]) |
| 2563 | ); |
| 2564 | cl_a1_msff_syrst_4x d0_16 ( |
| 2565 | .l1clk(l1clk), |
| 2566 | .siclk(siclk), |
| 2567 | .soclk(soclk), |
| 2568 | .d(fdin[16]), |
| 2569 | .si(sout[17]), |
| 2570 | .so(sout[16]), |
| 2571 | .reset(reset), |
| 2572 | .q(dout[16]) |
| 2573 | ); |
| 2574 | cl_a1_msff_syrst_4x d0_17 ( |
| 2575 | .l1clk(l1clk), |
| 2576 | .siclk(siclk), |
| 2577 | .soclk(soclk), |
| 2578 | .d(fdin[17]), |
| 2579 | .si(sout[18]), |
| 2580 | .so(sout[17]), |
| 2581 | .reset(reset), |
| 2582 | .q(dout[17]) |
| 2583 | ); |
| 2584 | cl_a1_msff_syrst_4x d0_18 ( |
| 2585 | .l1clk(l1clk), |
| 2586 | .siclk(siclk), |
| 2587 | .soclk(soclk), |
| 2588 | .d(fdin[18]), |
| 2589 | .si(sout[19]), |
| 2590 | .so(sout[18]), |
| 2591 | .reset(reset), |
| 2592 | .q(dout[18]) |
| 2593 | ); |
| 2594 | cl_a1_msff_syrst_4x d0_19 ( |
| 2595 | .l1clk(l1clk), |
| 2596 | .siclk(siclk), |
| 2597 | .soclk(soclk), |
| 2598 | .d(fdin[19]), |
| 2599 | .si(sout[20]), |
| 2600 | .so(sout[19]), |
| 2601 | .reset(reset), |
| 2602 | .q(dout[19]) |
| 2603 | ); |
| 2604 | cl_a1_msff_syrst_4x d0_20 ( |
| 2605 | .l1clk(l1clk), |
| 2606 | .siclk(siclk), |
| 2607 | .soclk(soclk), |
| 2608 | .d(fdin[20]), |
| 2609 | .si(sout[21]), |
| 2610 | .so(sout[20]), |
| 2611 | .reset(reset), |
| 2612 | .q(dout[20]) |
| 2613 | ); |
| 2614 | cl_a1_msff_syrst_4x d0_21 ( |
| 2615 | .l1clk(l1clk), |
| 2616 | .siclk(siclk), |
| 2617 | .soclk(soclk), |
| 2618 | .d(fdin[21]), |
| 2619 | .si(sout[22]), |
| 2620 | .so(sout[21]), |
| 2621 | .reset(reset), |
| 2622 | .q(dout[21]) |
| 2623 | ); |
| 2624 | cl_a1_msff_syrst_4x d0_22 ( |
| 2625 | .l1clk(l1clk), |
| 2626 | .siclk(siclk), |
| 2627 | .soclk(soclk), |
| 2628 | .d(fdin[22]), |
| 2629 | .si(sout[23]), |
| 2630 | .so(sout[22]), |
| 2631 | .reset(reset), |
| 2632 | .q(dout[22]) |
| 2633 | ); |
| 2634 | cl_a1_msff_syrst_4x d0_23 ( |
| 2635 | .l1clk(l1clk), |
| 2636 | .siclk(siclk), |
| 2637 | .soclk(soclk), |
| 2638 | .d(fdin[23]), |
| 2639 | .si(sout[24]), |
| 2640 | .so(sout[23]), |
| 2641 | .reset(reset), |
| 2642 | .q(dout[23]) |
| 2643 | ); |
| 2644 | cl_a1_msff_syrst_4x d0_24 ( |
| 2645 | .l1clk(l1clk), |
| 2646 | .siclk(siclk), |
| 2647 | .soclk(soclk), |
| 2648 | .d(fdin[24]), |
| 2649 | .si(sout[25]), |
| 2650 | .so(sout[24]), |
| 2651 | .reset(reset), |
| 2652 | .q(dout[24]) |
| 2653 | ); |
| 2654 | cl_a1_msff_syrst_4x d0_25 ( |
| 2655 | .l1clk(l1clk), |
| 2656 | .siclk(siclk), |
| 2657 | .soclk(soclk), |
| 2658 | .d(fdin[25]), |
| 2659 | .si(sout[26]), |
| 2660 | .so(sout[25]), |
| 2661 | .reset(reset), |
| 2662 | .q(dout[25]) |
| 2663 | ); |
| 2664 | cl_a1_msff_syrst_4x d0_26 ( |
| 2665 | .l1clk(l1clk), |
| 2666 | .siclk(siclk), |
| 2667 | .soclk(soclk), |
| 2668 | .d(fdin[26]), |
| 2669 | .si(sout[27]), |
| 2670 | .so(sout[26]), |
| 2671 | .reset(reset), |
| 2672 | .q(dout[26]) |
| 2673 | ); |
| 2674 | cl_a1_msff_syrst_4x d0_27 ( |
| 2675 | .l1clk(l1clk), |
| 2676 | .siclk(siclk), |
| 2677 | .soclk(soclk), |
| 2678 | .d(fdin[27]), |
| 2679 | .si(sout[28]), |
| 2680 | .so(sout[27]), |
| 2681 | .reset(reset), |
| 2682 | .q(dout[27]) |
| 2683 | ); |
| 2684 | cl_a1_msff_syrst_4x d0_28 ( |
| 2685 | .l1clk(l1clk), |
| 2686 | .siclk(siclk), |
| 2687 | .soclk(soclk), |
| 2688 | .d(fdin[28]), |
| 2689 | .si(sout[29]), |
| 2690 | .so(sout[28]), |
| 2691 | .reset(reset), |
| 2692 | .q(dout[28]) |
| 2693 | ); |
| 2694 | cl_a1_msff_syrst_4x d0_29 ( |
| 2695 | .l1clk(l1clk), |
| 2696 | .siclk(siclk), |
| 2697 | .soclk(soclk), |
| 2698 | .d(fdin[29]), |
| 2699 | .si(sout[30]), |
| 2700 | .so(sout[29]), |
| 2701 | .reset(reset), |
| 2702 | .q(dout[29]) |
| 2703 | ); |
| 2704 | cl_a1_msff_syrst_4x d0_30 ( |
| 2705 | .l1clk(l1clk), |
| 2706 | .siclk(siclk), |
| 2707 | .soclk(soclk), |
| 2708 | .d(fdin[30]), |
| 2709 | .si(sout[31]), |
| 2710 | .so(sout[30]), |
| 2711 | .reset(reset), |
| 2712 | .q(dout[30]) |
| 2713 | ); |
| 2714 | cl_a1_msff_syrst_4x d0_31 ( |
| 2715 | .l1clk(l1clk), |
| 2716 | .siclk(siclk), |
| 2717 | .soclk(soclk), |
| 2718 | .d(fdin[31]), |
| 2719 | .si(sout[32]), |
| 2720 | .so(sout[31]), |
| 2721 | .reset(reset), |
| 2722 | .q(dout[31]) |
| 2723 | ); |
| 2724 | cl_a1_msff_syrst_4x d0_32 ( |
| 2725 | .l1clk(l1clk), |
| 2726 | .siclk(siclk), |
| 2727 | .soclk(soclk), |
| 2728 | .d(fdin[32]), |
| 2729 | .si(sout[33]), |
| 2730 | .so(sout[32]), |
| 2731 | .reset(reset), |
| 2732 | .q(dout[32]) |
| 2733 | ); |
| 2734 | cl_a1_msff_syrst_4x d0_33 ( |
| 2735 | .l1clk(l1clk), |
| 2736 | .siclk(siclk), |
| 2737 | .soclk(soclk), |
| 2738 | .d(fdin[33]), |
| 2739 | .si(sout[34]), |
| 2740 | .so(sout[33]), |
| 2741 | .reset(reset), |
| 2742 | .q(dout[33]) |
| 2743 | ); |
| 2744 | cl_a1_msff_syrst_4x d0_34 ( |
| 2745 | .l1clk(l1clk), |
| 2746 | .siclk(siclk), |
| 2747 | .soclk(soclk), |
| 2748 | .d(fdin[34]), |
| 2749 | .si(sout[35]), |
| 2750 | .so(sout[34]), |
| 2751 | .reset(reset), |
| 2752 | .q(dout[34]) |
| 2753 | ); |
| 2754 | cl_a1_msff_syrst_4x d0_35 ( |
| 2755 | .l1clk(l1clk), |
| 2756 | .siclk(siclk), |
| 2757 | .soclk(soclk), |
| 2758 | .d(fdin[35]), |
| 2759 | .si(sout[36]), |
| 2760 | .so(sout[35]), |
| 2761 | .reset(reset), |
| 2762 | .q(dout[35]) |
| 2763 | ); |
| 2764 | cl_a1_msff_syrst_4x d0_36 ( |
| 2765 | .l1clk(l1clk), |
| 2766 | .siclk(siclk), |
| 2767 | .soclk(soclk), |
| 2768 | .d(fdin[36]), |
| 2769 | .si(sout[37]), |
| 2770 | .so(sout[36]), |
| 2771 | .reset(reset), |
| 2772 | .q(dout[36]) |
| 2773 | ); |
| 2774 | cl_a1_msff_syrst_4x d0_37 ( |
| 2775 | .l1clk(l1clk), |
| 2776 | .siclk(siclk), |
| 2777 | .soclk(soclk), |
| 2778 | .d(fdin[37]), |
| 2779 | .si(sout[38]), |
| 2780 | .so(sout[37]), |
| 2781 | .reset(reset), |
| 2782 | .q(dout[37]) |
| 2783 | ); |
| 2784 | cl_a1_msff_syrst_4x d0_38 ( |
| 2785 | .l1clk(l1clk), |
| 2786 | .siclk(siclk), |
| 2787 | .soclk(soclk), |
| 2788 | .d(fdin[38]), |
| 2789 | .si(sout[39]), |
| 2790 | .so(sout[38]), |
| 2791 | .reset(reset), |
| 2792 | .q(dout[38]) |
| 2793 | ); |
| 2794 | cl_a1_msff_syrst_4x d0_39 ( |
| 2795 | .l1clk(l1clk), |
| 2796 | .siclk(siclk), |
| 2797 | .soclk(soclk), |
| 2798 | .d(fdin[39]), |
| 2799 | .si(sout[40]), |
| 2800 | .so(sout[39]), |
| 2801 | .reset(reset), |
| 2802 | .q(dout[39]) |
| 2803 | ); |
| 2804 | cl_a1_msff_syrst_4x d0_40 ( |
| 2805 | .l1clk(l1clk), |
| 2806 | .siclk(siclk), |
| 2807 | .soclk(soclk), |
| 2808 | .d(fdin[40]), |
| 2809 | .si(sout[41]), |
| 2810 | .so(sout[40]), |
| 2811 | .reset(reset), |
| 2812 | .q(dout[40]) |
| 2813 | ); |
| 2814 | cl_a1_msff_syrst_4x d0_41 ( |
| 2815 | .l1clk(l1clk), |
| 2816 | .siclk(siclk), |
| 2817 | .soclk(soclk), |
| 2818 | .d(fdin[41]), |
| 2819 | .si(sout[42]), |
| 2820 | .so(sout[41]), |
| 2821 | .reset(reset), |
| 2822 | .q(dout[41]) |
| 2823 | ); |
| 2824 | cl_a1_msff_syrst_4x d0_42 ( |
| 2825 | .l1clk(l1clk), |
| 2826 | .siclk(siclk), |
| 2827 | .soclk(soclk), |
| 2828 | .d(fdin[42]), |
| 2829 | .si(sout[43]), |
| 2830 | .so(sout[42]), |
| 2831 | .reset(reset), |
| 2832 | .q(dout[42]) |
| 2833 | ); |
| 2834 | cl_a1_msff_syrst_4x d0_43 ( |
| 2835 | .l1clk(l1clk), |
| 2836 | .siclk(siclk), |
| 2837 | .soclk(soclk), |
| 2838 | .d(fdin[43]), |
| 2839 | .si(sout[44]), |
| 2840 | .so(sout[43]), |
| 2841 | .reset(reset), |
| 2842 | .q(dout[43]) |
| 2843 | ); |
| 2844 | cl_a1_msff_syrst_4x d0_44 ( |
| 2845 | .l1clk(l1clk), |
| 2846 | .siclk(siclk), |
| 2847 | .soclk(soclk), |
| 2848 | .d(fdin[44]), |
| 2849 | .si(sout[45]), |
| 2850 | .so(sout[44]), |
| 2851 | .reset(reset), |
| 2852 | .q(dout[44]) |
| 2853 | ); |
| 2854 | cl_a1_msff_syrst_4x d0_45 ( |
| 2855 | .l1clk(l1clk), |
| 2856 | .siclk(siclk), |
| 2857 | .soclk(soclk), |
| 2858 | .d(fdin[45]), |
| 2859 | .si(sout[46]), |
| 2860 | .so(sout[45]), |
| 2861 | .reset(reset), |
| 2862 | .q(dout[45]) |
| 2863 | ); |
| 2864 | cl_a1_msff_syrst_4x d0_46 ( |
| 2865 | .l1clk(l1clk), |
| 2866 | .siclk(siclk), |
| 2867 | .soclk(soclk), |
| 2868 | .d(fdin[46]), |
| 2869 | .si(sout[47]), |
| 2870 | .so(sout[46]), |
| 2871 | .reset(reset), |
| 2872 | .q(dout[46]) |
| 2873 | ); |
| 2874 | cl_a1_msff_syrst_4x d0_47 ( |
| 2875 | .l1clk(l1clk), |
| 2876 | .siclk(siclk), |
| 2877 | .soclk(soclk), |
| 2878 | .d(fdin[47]), |
| 2879 | .si(sout[48]), |
| 2880 | .so(sout[47]), |
| 2881 | .reset(reset), |
| 2882 | .q(dout[47]) |
| 2883 | ); |
| 2884 | cl_a1_msff_syrst_4x d0_48 ( |
| 2885 | .l1clk(l1clk), |
| 2886 | .siclk(siclk), |
| 2887 | .soclk(soclk), |
| 2888 | .d(fdin[48]), |
| 2889 | .si(sout[49]), |
| 2890 | .so(sout[48]), |
| 2891 | .reset(reset), |
| 2892 | .q(dout[48]) |
| 2893 | ); |
| 2894 | cl_a1_msff_syrst_4x d0_49 ( |
| 2895 | .l1clk(l1clk), |
| 2896 | .siclk(siclk), |
| 2897 | .soclk(soclk), |
| 2898 | .d(fdin[49]), |
| 2899 | .si(sout[50]), |
| 2900 | .so(sout[49]), |
| 2901 | .reset(reset), |
| 2902 | .q(dout[49]) |
| 2903 | ); |
| 2904 | cl_a1_msff_syrst_4x d0_50 ( |
| 2905 | .l1clk(l1clk), |
| 2906 | .siclk(siclk), |
| 2907 | .soclk(soclk), |
| 2908 | .d(fdin[50]), |
| 2909 | .si(sout[51]), |
| 2910 | .so(sout[50]), |
| 2911 | .reset(reset), |
| 2912 | .q(dout[50]) |
| 2913 | ); |
| 2914 | cl_a1_msff_syrst_4x d0_51 ( |
| 2915 | .l1clk(l1clk), |
| 2916 | .siclk(siclk), |
| 2917 | .soclk(soclk), |
| 2918 | .d(fdin[51]), |
| 2919 | .si(sout[52]), |
| 2920 | .so(sout[51]), |
| 2921 | .reset(reset), |
| 2922 | .q(dout[51]) |
| 2923 | ); |
| 2924 | cl_a1_msff_syrst_4x d0_52 ( |
| 2925 | .l1clk(l1clk), |
| 2926 | .siclk(siclk), |
| 2927 | .soclk(soclk), |
| 2928 | .d(fdin[52]), |
| 2929 | .si(sout[53]), |
| 2930 | .so(sout[52]), |
| 2931 | .reset(reset), |
| 2932 | .q(dout[52]) |
| 2933 | ); |
| 2934 | cl_a1_msff_syrst_4x d0_53 ( |
| 2935 | .l1clk(l1clk), |
| 2936 | .siclk(siclk), |
| 2937 | .soclk(soclk), |
| 2938 | .d(fdin[53]), |
| 2939 | .si(sout[54]), |
| 2940 | .so(sout[53]), |
| 2941 | .reset(reset), |
| 2942 | .q(dout[53]) |
| 2943 | ); |
| 2944 | cl_a1_msff_syrst_4x d0_54 ( |
| 2945 | .l1clk(l1clk), |
| 2946 | .siclk(siclk), |
| 2947 | .soclk(soclk), |
| 2948 | .d(fdin[54]), |
| 2949 | .si(sout[55]), |
| 2950 | .so(sout[54]), |
| 2951 | .reset(reset), |
| 2952 | .q(dout[54]) |
| 2953 | ); |
| 2954 | cl_a1_msff_syrst_4x d0_55 ( |
| 2955 | .l1clk(l1clk), |
| 2956 | .siclk(siclk), |
| 2957 | .soclk(soclk), |
| 2958 | .d(fdin[55]), |
| 2959 | .si(sout[56]), |
| 2960 | .so(sout[55]), |
| 2961 | .reset(reset), |
| 2962 | .q(dout[55]) |
| 2963 | ); |
| 2964 | cl_a1_msff_syrst_4x d0_56 ( |
| 2965 | .l1clk(l1clk), |
| 2966 | .siclk(siclk), |
| 2967 | .soclk(soclk), |
| 2968 | .d(fdin[56]), |
| 2969 | .si(sout[57]), |
| 2970 | .so(sout[56]), |
| 2971 | .reset(reset), |
| 2972 | .q(dout[56]) |
| 2973 | ); |
| 2974 | cl_a1_msff_syrst_4x d0_57 ( |
| 2975 | .l1clk(l1clk), |
| 2976 | .siclk(siclk), |
| 2977 | .soclk(soclk), |
| 2978 | .d(fdin[57]), |
| 2979 | .si(sout[58]), |
| 2980 | .so(sout[57]), |
| 2981 | .reset(reset), |
| 2982 | .q(dout[57]) |
| 2983 | ); |
| 2984 | cl_a1_msff_syrst_4x d0_58 ( |
| 2985 | .l1clk(l1clk), |
| 2986 | .siclk(siclk), |
| 2987 | .soclk(soclk), |
| 2988 | .d(fdin[58]), |
| 2989 | .si(sout[59]), |
| 2990 | .so(sout[58]), |
| 2991 | .reset(reset), |
| 2992 | .q(dout[58]) |
| 2993 | ); |
| 2994 | cl_a1_msff_syrst_4x d0_59 ( |
| 2995 | .l1clk(l1clk), |
| 2996 | .siclk(siclk), |
| 2997 | .soclk(soclk), |
| 2998 | .d(fdin[59]), |
| 2999 | .si(sout[60]), |
| 3000 | .so(sout[59]), |
| 3001 | .reset(reset), |
| 3002 | .q(dout[59]) |
| 3003 | ); |
| 3004 | cl_a1_msff_syrst_4x d0_60 ( |
| 3005 | .l1clk(l1clk), |
| 3006 | .siclk(siclk), |
| 3007 | .soclk(soclk), |
| 3008 | .d(fdin[60]), |
| 3009 | .si(sout[61]), |
| 3010 | .so(sout[60]), |
| 3011 | .reset(reset), |
| 3012 | .q(dout[60]) |
| 3013 | ); |
| 3014 | cl_a1_msff_syrst_4x d0_61 ( |
| 3015 | .l1clk(l1clk), |
| 3016 | .siclk(siclk), |
| 3017 | .soclk(soclk), |
| 3018 | .d(fdin[61]), |
| 3019 | .si(sout[62]), |
| 3020 | .so(sout[61]), |
| 3021 | .reset(reset), |
| 3022 | .q(dout[61]) |
| 3023 | ); |
| 3024 | cl_a1_msff_syrst_4x d0_62 ( |
| 3025 | .l1clk(l1clk), |
| 3026 | .siclk(siclk), |
| 3027 | .soclk(soclk), |
| 3028 | .d(fdin[62]), |
| 3029 | .si(sout[63]), |
| 3030 | .so(sout[62]), |
| 3031 | .reset(reset), |
| 3032 | .q(dout[62]) |
| 3033 | ); |
| 3034 | cl_a1_msff_syrst_4x d0_63 ( |
| 3035 | .l1clk(l1clk), |
| 3036 | .siclk(siclk), |
| 3037 | .soclk(soclk), |
| 3038 | .d(fdin[63]), |
| 3039 | .si(scan_in), |
| 3040 | .so(sout[63]), |
| 3041 | .reset(reset), |
| 3042 | .q(dout[63]) |
| 3043 | ); |
| 3044 | |
| 3045 | |
| 3046 | |
| 3047 | |
| 3048 | endmodule |
| 3049 | |
| 3050 | |
| 3051 | |
| 3052 | |
| 3053 | |
| 3054 | |
| 3055 | |
| 3056 | |
| 3057 | |
| 3058 | |
| 3059 | |
| 3060 | |
| 3061 | |
| 3062 | // any PARAMS parms go into naming of macro |
| 3063 | |
| 3064 | module dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_19 ( |
| 3065 | din, |
| 3066 | reset, |
| 3067 | l1clk, |
| 3068 | scan_in, |
| 3069 | siclk, |
| 3070 | soclk, |
| 3071 | dout, |
| 3072 | scan_out); |
| 3073 | wire [18:0] fdin; |
| 3074 | wire [18:1] sout; |
| 3075 | |
| 3076 | input [18:0] din; |
| 3077 | input reset; |
| 3078 | input l1clk; |
| 3079 | input scan_in; |
| 3080 | |
| 3081 | |
| 3082 | input siclk; |
| 3083 | input soclk; |
| 3084 | |
| 3085 | output [18:0] dout; |
| 3086 | output scan_out; |
| 3087 | assign fdin[18:0] = din[18:0] & {19 {reset}}; |
| 3088 | |
| 3089 | |
| 3090 | |
| 3091 | |
| 3092 | |
| 3093 | |
| 3094 | |
| 3095 | |
| 3096 | |
| 3097 | |
| 3098 | |
| 3099 | |
| 3100 | |
| 3101 | |
| 3102 | |
| 3103 | |
| 3104 | |
| 3105 | cl_a1_msff_syrst_4x d0_0 ( |
| 3106 | .l1clk(l1clk), |
| 3107 | .siclk(siclk), |
| 3108 | .soclk(soclk), |
| 3109 | .d(fdin[0]), |
| 3110 | .si(sout[1]), |
| 3111 | .so(scan_out), |
| 3112 | .reset(reset), |
| 3113 | .q(dout[0]) |
| 3114 | ); |
| 3115 | cl_a1_msff_syrst_4x d0_1 ( |
| 3116 | .l1clk(l1clk), |
| 3117 | .siclk(siclk), |
| 3118 | .soclk(soclk), |
| 3119 | .d(fdin[1]), |
| 3120 | .si(sout[2]), |
| 3121 | .so(sout[1]), |
| 3122 | .reset(reset), |
| 3123 | .q(dout[1]) |
| 3124 | ); |
| 3125 | cl_a1_msff_syrst_4x d0_2 ( |
| 3126 | .l1clk(l1clk), |
| 3127 | .siclk(siclk), |
| 3128 | .soclk(soclk), |
| 3129 | .d(fdin[2]), |
| 3130 | .si(sout[3]), |
| 3131 | .so(sout[2]), |
| 3132 | .reset(reset), |
| 3133 | .q(dout[2]) |
| 3134 | ); |
| 3135 | cl_a1_msff_syrst_4x d0_3 ( |
| 3136 | .l1clk(l1clk), |
| 3137 | .siclk(siclk), |
| 3138 | .soclk(soclk), |
| 3139 | .d(fdin[3]), |
| 3140 | .si(sout[4]), |
| 3141 | .so(sout[3]), |
| 3142 | .reset(reset), |
| 3143 | .q(dout[3]) |
| 3144 | ); |
| 3145 | cl_a1_msff_syrst_4x d0_4 ( |
| 3146 | .l1clk(l1clk), |
| 3147 | .siclk(siclk), |
| 3148 | .soclk(soclk), |
| 3149 | .d(fdin[4]), |
| 3150 | .si(sout[5]), |
| 3151 | .so(sout[4]), |
| 3152 | .reset(reset), |
| 3153 | .q(dout[4]) |
| 3154 | ); |
| 3155 | cl_a1_msff_syrst_4x d0_5 ( |
| 3156 | .l1clk(l1clk), |
| 3157 | .siclk(siclk), |
| 3158 | .soclk(soclk), |
| 3159 | .d(fdin[5]), |
| 3160 | .si(sout[6]), |
| 3161 | .so(sout[5]), |
| 3162 | .reset(reset), |
| 3163 | .q(dout[5]) |
| 3164 | ); |
| 3165 | cl_a1_msff_syrst_4x d0_6 ( |
| 3166 | .l1clk(l1clk), |
| 3167 | .siclk(siclk), |
| 3168 | .soclk(soclk), |
| 3169 | .d(fdin[6]), |
| 3170 | .si(sout[7]), |
| 3171 | .so(sout[6]), |
| 3172 | .reset(reset), |
| 3173 | .q(dout[6]) |
| 3174 | ); |
| 3175 | cl_a1_msff_syrst_4x d0_7 ( |
| 3176 | .l1clk(l1clk), |
| 3177 | .siclk(siclk), |
| 3178 | .soclk(soclk), |
| 3179 | .d(fdin[7]), |
| 3180 | .si(sout[8]), |
| 3181 | .so(sout[7]), |
| 3182 | .reset(reset), |
| 3183 | .q(dout[7]) |
| 3184 | ); |
| 3185 | cl_a1_msff_syrst_4x d0_8 ( |
| 3186 | .l1clk(l1clk), |
| 3187 | .siclk(siclk), |
| 3188 | .soclk(soclk), |
| 3189 | .d(fdin[8]), |
| 3190 | .si(sout[9]), |
| 3191 | .so(sout[8]), |
| 3192 | .reset(reset), |
| 3193 | .q(dout[8]) |
| 3194 | ); |
| 3195 | cl_a1_msff_syrst_4x d0_9 ( |
| 3196 | .l1clk(l1clk), |
| 3197 | .siclk(siclk), |
| 3198 | .soclk(soclk), |
| 3199 | .d(fdin[9]), |
| 3200 | .si(sout[10]), |
| 3201 | .so(sout[9]), |
| 3202 | .reset(reset), |
| 3203 | .q(dout[9]) |
| 3204 | ); |
| 3205 | cl_a1_msff_syrst_4x d0_10 ( |
| 3206 | .l1clk(l1clk), |
| 3207 | .siclk(siclk), |
| 3208 | .soclk(soclk), |
| 3209 | .d(fdin[10]), |
| 3210 | .si(sout[11]), |
| 3211 | .so(sout[10]), |
| 3212 | .reset(reset), |
| 3213 | .q(dout[10]) |
| 3214 | ); |
| 3215 | cl_a1_msff_syrst_4x d0_11 ( |
| 3216 | .l1clk(l1clk), |
| 3217 | .siclk(siclk), |
| 3218 | .soclk(soclk), |
| 3219 | .d(fdin[11]), |
| 3220 | .si(sout[12]), |
| 3221 | .so(sout[11]), |
| 3222 | .reset(reset), |
| 3223 | .q(dout[11]) |
| 3224 | ); |
| 3225 | cl_a1_msff_syrst_4x d0_12 ( |
| 3226 | .l1clk(l1clk), |
| 3227 | .siclk(siclk), |
| 3228 | .soclk(soclk), |
| 3229 | .d(fdin[12]), |
| 3230 | .si(sout[13]), |
| 3231 | .so(sout[12]), |
| 3232 | .reset(reset), |
| 3233 | .q(dout[12]) |
| 3234 | ); |
| 3235 | cl_a1_msff_syrst_4x d0_13 ( |
| 3236 | .l1clk(l1clk), |
| 3237 | .siclk(siclk), |
| 3238 | .soclk(soclk), |
| 3239 | .d(fdin[13]), |
| 3240 | .si(sout[14]), |
| 3241 | .so(sout[13]), |
| 3242 | .reset(reset), |
| 3243 | .q(dout[13]) |
| 3244 | ); |
| 3245 | cl_a1_msff_syrst_4x d0_14 ( |
| 3246 | .l1clk(l1clk), |
| 3247 | .siclk(siclk), |
| 3248 | .soclk(soclk), |
| 3249 | .d(fdin[14]), |
| 3250 | .si(sout[15]), |
| 3251 | .so(sout[14]), |
| 3252 | .reset(reset), |
| 3253 | .q(dout[14]) |
| 3254 | ); |
| 3255 | cl_a1_msff_syrst_4x d0_15 ( |
| 3256 | .l1clk(l1clk), |
| 3257 | .siclk(siclk), |
| 3258 | .soclk(soclk), |
| 3259 | .d(fdin[15]), |
| 3260 | .si(sout[16]), |
| 3261 | .so(sout[15]), |
| 3262 | .reset(reset), |
| 3263 | .q(dout[15]) |
| 3264 | ); |
| 3265 | cl_a1_msff_syrst_4x d0_16 ( |
| 3266 | .l1clk(l1clk), |
| 3267 | .siclk(siclk), |
| 3268 | .soclk(soclk), |
| 3269 | .d(fdin[16]), |
| 3270 | .si(sout[17]), |
| 3271 | .so(sout[16]), |
| 3272 | .reset(reset), |
| 3273 | .q(dout[16]) |
| 3274 | ); |
| 3275 | cl_a1_msff_syrst_4x d0_17 ( |
| 3276 | .l1clk(l1clk), |
| 3277 | .siclk(siclk), |
| 3278 | .soclk(soclk), |
| 3279 | .d(fdin[17]), |
| 3280 | .si(sout[18]), |
| 3281 | .so(sout[17]), |
| 3282 | .reset(reset), |
| 3283 | .q(dout[17]) |
| 3284 | ); |
| 3285 | cl_a1_msff_syrst_4x d0_18 ( |
| 3286 | .l1clk(l1clk), |
| 3287 | .siclk(siclk), |
| 3288 | .soclk(soclk), |
| 3289 | .d(fdin[18]), |
| 3290 | .si(scan_in), |
| 3291 | .so(sout[18]), |
| 3292 | .reset(reset), |
| 3293 | .q(dout[18]) |
| 3294 | ); |
| 3295 | |
| 3296 | |
| 3297 | |
| 3298 | |
| 3299 | endmodule |
| 3300 | |
| 3301 | |
| 3302 | |
| 3303 | |
| 3304 | |
| 3305 | |
| 3306 | |
| 3307 | |
| 3308 | |
| 3309 | |
| 3310 | |
| 3311 | |
| 3312 | |
| 3313 | // any PARAMS parms go into naming of macro |
| 3314 | |
| 3315 | module dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_15 ( |
| 3316 | din, |
| 3317 | reset, |
| 3318 | l1clk, |
| 3319 | scan_in, |
| 3320 | siclk, |
| 3321 | soclk, |
| 3322 | dout, |
| 3323 | scan_out); |
| 3324 | wire [14:0] fdin; |
| 3325 | wire [14:1] sout; |
| 3326 | |
| 3327 | input [14:0] din; |
| 3328 | input reset; |
| 3329 | input l1clk; |
| 3330 | input scan_in; |
| 3331 | |
| 3332 | |
| 3333 | input siclk; |
| 3334 | input soclk; |
| 3335 | |
| 3336 | output [14:0] dout; |
| 3337 | output scan_out; |
| 3338 | assign fdin[14:0] = din[14:0] & {15 {reset}}; |
| 3339 | |
| 3340 | |
| 3341 | |
| 3342 | |
| 3343 | |
| 3344 | |
| 3345 | |
| 3346 | |
| 3347 | |
| 3348 | |
| 3349 | |
| 3350 | |
| 3351 | |
| 3352 | |
| 3353 | |
| 3354 | |
| 3355 | |
| 3356 | cl_a1_msff_syrst_4x d0_0 ( |
| 3357 | .l1clk(l1clk), |
| 3358 | .siclk(siclk), |
| 3359 | .soclk(soclk), |
| 3360 | .d(fdin[0]), |
| 3361 | .si(sout[1]), |
| 3362 | .so(scan_out), |
| 3363 | .reset(reset), |
| 3364 | .q(dout[0]) |
| 3365 | ); |
| 3366 | cl_a1_msff_syrst_4x d0_1 ( |
| 3367 | .l1clk(l1clk), |
| 3368 | .siclk(siclk), |
| 3369 | .soclk(soclk), |
| 3370 | .d(fdin[1]), |
| 3371 | .si(sout[2]), |
| 3372 | .so(sout[1]), |
| 3373 | .reset(reset), |
| 3374 | .q(dout[1]) |
| 3375 | ); |
| 3376 | cl_a1_msff_syrst_4x d0_2 ( |
| 3377 | .l1clk(l1clk), |
| 3378 | .siclk(siclk), |
| 3379 | .soclk(soclk), |
| 3380 | .d(fdin[2]), |
| 3381 | .si(sout[3]), |
| 3382 | .so(sout[2]), |
| 3383 | .reset(reset), |
| 3384 | .q(dout[2]) |
| 3385 | ); |
| 3386 | cl_a1_msff_syrst_4x d0_3 ( |
| 3387 | .l1clk(l1clk), |
| 3388 | .siclk(siclk), |
| 3389 | .soclk(soclk), |
| 3390 | .d(fdin[3]), |
| 3391 | .si(sout[4]), |
| 3392 | .so(sout[3]), |
| 3393 | .reset(reset), |
| 3394 | .q(dout[3]) |
| 3395 | ); |
| 3396 | cl_a1_msff_syrst_4x d0_4 ( |
| 3397 | .l1clk(l1clk), |
| 3398 | .siclk(siclk), |
| 3399 | .soclk(soclk), |
| 3400 | .d(fdin[4]), |
| 3401 | .si(sout[5]), |
| 3402 | .so(sout[4]), |
| 3403 | .reset(reset), |
| 3404 | .q(dout[4]) |
| 3405 | ); |
| 3406 | cl_a1_msff_syrst_4x d0_5 ( |
| 3407 | .l1clk(l1clk), |
| 3408 | .siclk(siclk), |
| 3409 | .soclk(soclk), |
| 3410 | .d(fdin[5]), |
| 3411 | .si(sout[6]), |
| 3412 | .so(sout[5]), |
| 3413 | .reset(reset), |
| 3414 | .q(dout[5]) |
| 3415 | ); |
| 3416 | cl_a1_msff_syrst_4x d0_6 ( |
| 3417 | .l1clk(l1clk), |
| 3418 | .siclk(siclk), |
| 3419 | .soclk(soclk), |
| 3420 | .d(fdin[6]), |
| 3421 | .si(sout[7]), |
| 3422 | .so(sout[6]), |
| 3423 | .reset(reset), |
| 3424 | .q(dout[6]) |
| 3425 | ); |
| 3426 | cl_a1_msff_syrst_4x d0_7 ( |
| 3427 | .l1clk(l1clk), |
| 3428 | .siclk(siclk), |
| 3429 | .soclk(soclk), |
| 3430 | .d(fdin[7]), |
| 3431 | .si(sout[8]), |
| 3432 | .so(sout[7]), |
| 3433 | .reset(reset), |
| 3434 | .q(dout[7]) |
| 3435 | ); |
| 3436 | cl_a1_msff_syrst_4x d0_8 ( |
| 3437 | .l1clk(l1clk), |
| 3438 | .siclk(siclk), |
| 3439 | .soclk(soclk), |
| 3440 | .d(fdin[8]), |
| 3441 | .si(sout[9]), |
| 3442 | .so(sout[8]), |
| 3443 | .reset(reset), |
| 3444 | .q(dout[8]) |
| 3445 | ); |
| 3446 | cl_a1_msff_syrst_4x d0_9 ( |
| 3447 | .l1clk(l1clk), |
| 3448 | .siclk(siclk), |
| 3449 | .soclk(soclk), |
| 3450 | .d(fdin[9]), |
| 3451 | .si(sout[10]), |
| 3452 | .so(sout[9]), |
| 3453 | .reset(reset), |
| 3454 | .q(dout[9]) |
| 3455 | ); |
| 3456 | cl_a1_msff_syrst_4x d0_10 ( |
| 3457 | .l1clk(l1clk), |
| 3458 | .siclk(siclk), |
| 3459 | .soclk(soclk), |
| 3460 | .d(fdin[10]), |
| 3461 | .si(sout[11]), |
| 3462 | .so(sout[10]), |
| 3463 | .reset(reset), |
| 3464 | .q(dout[10]) |
| 3465 | ); |
| 3466 | cl_a1_msff_syrst_4x d0_11 ( |
| 3467 | .l1clk(l1clk), |
| 3468 | .siclk(siclk), |
| 3469 | .soclk(soclk), |
| 3470 | .d(fdin[11]), |
| 3471 | .si(sout[12]), |
| 3472 | .so(sout[11]), |
| 3473 | .reset(reset), |
| 3474 | .q(dout[11]) |
| 3475 | ); |
| 3476 | cl_a1_msff_syrst_4x d0_12 ( |
| 3477 | .l1clk(l1clk), |
| 3478 | .siclk(siclk), |
| 3479 | .soclk(soclk), |
| 3480 | .d(fdin[12]), |
| 3481 | .si(sout[13]), |
| 3482 | .so(sout[12]), |
| 3483 | .reset(reset), |
| 3484 | .q(dout[12]) |
| 3485 | ); |
| 3486 | cl_a1_msff_syrst_4x d0_13 ( |
| 3487 | .l1clk(l1clk), |
| 3488 | .siclk(siclk), |
| 3489 | .soclk(soclk), |
| 3490 | .d(fdin[13]), |
| 3491 | .si(sout[14]), |
| 3492 | .so(sout[13]), |
| 3493 | .reset(reset), |
| 3494 | .q(dout[13]) |
| 3495 | ); |
| 3496 | cl_a1_msff_syrst_4x d0_14 ( |
| 3497 | .l1clk(l1clk), |
| 3498 | .siclk(siclk), |
| 3499 | .soclk(soclk), |
| 3500 | .d(fdin[14]), |
| 3501 | .si(scan_in), |
| 3502 | .so(sout[14]), |
| 3503 | .reset(reset), |
| 3504 | .q(dout[14]) |
| 3505 | ); |
| 3506 | |
| 3507 | |
| 3508 | |
| 3509 | |
| 3510 | endmodule |
| 3511 | |
| 3512 | |
| 3513 | |
| 3514 | |
| 3515 | |
| 3516 | |
| 3517 | |
| 3518 | |
| 3519 | |
| 3520 | |
| 3521 | |
| 3522 | |
| 3523 | |
| 3524 | // any PARAMS parms go into naming of macro |
| 3525 | |
| 3526 | module dmu_cb0_msff_ctl_macro__library_a1__reset_1__width_2 ( |
| 3527 | din, |
| 3528 | reset, |
| 3529 | l1clk, |
| 3530 | scan_in, |
| 3531 | siclk, |
| 3532 | soclk, |
| 3533 | dout, |
| 3534 | scan_out); |
| 3535 | wire [1:0] fdin; |
| 3536 | wire [1:1] sout; |
| 3537 | |
| 3538 | input [1:0] din; |
| 3539 | input reset; |
| 3540 | input l1clk; |
| 3541 | input scan_in; |
| 3542 | |
| 3543 | |
| 3544 | input siclk; |
| 3545 | input soclk; |
| 3546 | |
| 3547 | output [1:0] dout; |
| 3548 | output scan_out; |
| 3549 | assign fdin[1:0] = din[1:0] & {2 {reset}}; |
| 3550 | |
| 3551 | |
| 3552 | |
| 3553 | |
| 3554 | |
| 3555 | |
| 3556 | |
| 3557 | |
| 3558 | |
| 3559 | |
| 3560 | |
| 3561 | |
| 3562 | |
| 3563 | |
| 3564 | |
| 3565 | |
| 3566 | |
| 3567 | cl_a1_msff_syrst_4x d0_0 ( |
| 3568 | .l1clk(l1clk), |
| 3569 | .siclk(siclk), |
| 3570 | .soclk(soclk), |
| 3571 | .d(fdin[0]), |
| 3572 | .si(sout[1]), |
| 3573 | .so(scan_out), |
| 3574 | .reset(reset), |
| 3575 | .q(dout[0]) |
| 3576 | ); |
| 3577 | cl_a1_msff_syrst_4x d0_1 ( |
| 3578 | .l1clk(l1clk), |
| 3579 | .siclk(siclk), |
| 3580 | .soclk(soclk), |
| 3581 | .d(fdin[1]), |
| 3582 | .si(scan_in), |
| 3583 | .so(sout[1]), |
| 3584 | .reset(reset), |
| 3585 | .q(dout[1]) |
| 3586 | ); |
| 3587 | |
| 3588 | |
| 3589 | |
| 3590 | |
| 3591 | endmodule |
| 3592 | |
| 3593 | |
| 3594 | |
| 3595 | |
| 3596 | |
| 3597 | |
| 3598 | |
| 3599 | |