| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_clu_crm.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
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| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_clu_crm |
| 36 | ( |
| 37 | // clock/reset |
| 38 | clk, |
| 39 | rst_l, |
| 40 | |
| 41 | // jbc: dma/int cpl port |
| 42 | j2d_di_cmd, |
| 43 | j2d_di_ctag, |
| 44 | j2d_di_cmd_vld, |
| 45 | j2d_d_data, |
| 46 | j2d_d_data_par, |
| 47 | j2d_d_data_err, |
| 48 | j2d_d_data_vld, |
| 49 | |
| 50 | // jbc: pio rd/wr req port |
| 51 | j2d_p_cmd, |
| 52 | j2d_p_addr, |
| 53 | j2d_p_bmsk, |
| 54 | j2d_p_ctag, |
| 55 | j2d_p_cmd_vld, |
| 56 | j2d_p_data, |
| 57 | j2d_p_data_par, |
| 58 | j2d_p_data_vld, |
| 59 | |
| 60 | // ilu: dou-dma status port |
| 61 | k2y_dou_dptr, |
| 62 | k2y_dou_err, |
| 63 | k2y_dou_vld, |
| 64 | |
| 65 | // psb : sbd access port |
| 66 | cl2ps_e_cmd_type, |
| 67 | cl2ps_e_trn, |
| 68 | cl2ps_e_wr_data, |
| 69 | cl2ps_e_req, |
| 70 | ps2cl_e_rd_data, |
| 71 | ps2cl_e_gnt, |
| 72 | |
| 73 | // cmu : epr port |
| 74 | cl2cm_rcd, |
| 75 | cl2cm_rcd_enq, |
| 76 | cm2cl_rcd_full, |
| 77 | |
| 78 | // mmu: tdr port |
| 79 | cl2mm_tdr_rcd, |
| 80 | cl2mm_tdr_vld, |
| 81 | |
| 82 | // dou: data write port |
| 83 | cl2do_dma_data, |
| 84 | cl2do_dma_dpar, |
| 85 | cl2do_dma_addr, |
| 86 | cl2do_dma_wr, |
| 87 | cl2do_pio_data, |
| 88 | cl2do_pio_dpar, |
| 89 | cl2do_pio_addr, |
| 90 | cl2do_pio_wr, |
| 91 | |
| 92 | // ctm : urr port |
| 93 | crm2ctm_rcd_deq, |
| 94 | ctm2crm_rcd, |
| 95 | ctm2crm_rcd_enq, |
| 96 | |
| 97 | // ctm: dma/int tag return port |
| 98 | crm2ctm_tag, |
| 99 | crm2ctm_tag_enq, |
| 100 | |
| 101 | // cru : debug ports |
| 102 | crm_dbg0_bus_a, |
| 103 | crm_dbg0_bus_b, |
| 104 | crm_dbg1_bus_a, |
| 105 | crm_dbg1_bus_b, |
| 106 | cr2cl_dbg_sel_a, |
| 107 | cr2cl_dbg_sel_b, |
| 108 | |
| 109 | // cru : config packet setup |
| 110 | cr2cl_bus_num, |
| 111 | |
| 112 | // from peu, force 1 non-posted pio write outstanding |
| 113 | p2d_npwr_stall_en, |
| 114 | rm2crm_npwr_wrack, |
| 115 | |
| 116 | im2crm_bc_stall_en, |
| 117 | im2crm_ilu_stall_en, |
| 118 | il2cl_gr_16, |
| 119 | |
| 120 | // for stall to keep ehb from filling with pios |
| 121 | d2j_cmd_vld, |
| 122 | d2j_cmd_bit3 |
| 123 | ); |
| 124 | |
| 125 | // >>>>>>>>>>>>>>>>>>>>>>>>> Parameter Declarations <<<<<<<<<<<<<<<<<<<<<<<<< |
| 126 | |
| 127 | // -------------------------------------------------------- |
| 128 | // DMA/INT Command Record (DCR) FIFO Configuration |
| 129 | // -------------------------------------------------------- |
| 130 | |
| 131 | parameter DCR_FDEPTH = 5'd16; |
| 132 | parameter DCR_FDEPTH_MINONE = 4'd15; |
| 133 | parameter DCR_FPTR_WDTH = 4; |
| 134 | |
| 135 | // -------------------------------------------------------- |
| 136 | // PIO Command Record (PCR) FIFO Configuration |
| 137 | // -------------------------------------------------------- |
| 138 | |
| 139 | parameter PCR_FDEPTH = 5'd16; |
| 140 | parameter PCR_FDEPTH_MINONE = 4'd15; |
| 141 | parameter PCR_FPTR_WDTH = 4; |
| 142 | |
| 143 | // -------------------------------------------------------- |
| 144 | // Unsupported Request Record (URR) FIFO Configuration |
| 145 | // -------------------------------------------------------- |
| 146 | |
| 147 | parameter URR_FDEPTH = 4'd6; |
| 148 | parameter URR_FDEPTH_MINONE = 3'd5; |
| 149 | parameter URR_FPTR_WDTH = 3; |
| 150 | |
| 151 | // -------------------------------------------------------- |
| 152 | // DMA/INT Command Record (DCR) Field Definitions |
| 153 | // -------------------------------------------------------- |
| 154 | |
| 155 | // ctag field |
| 156 | parameter DCR_CTAG_LSB = 0; |
| 157 | parameter DCR_CTAG_WDTH = `FIRE_J2D_DI_CTAG_WDTH; |
| 158 | parameter DCR_CTAG_MSB = DCR_CTAG_LSB + DCR_CTAG_WDTH - 1; |
| 159 | |
| 160 | // cmd field |
| 161 | parameter DCR_CMD_LSB = DCR_CTAG_LSB + DCR_CTAG_WDTH; |
| 162 | parameter DCR_CMD_WDTH = `FIRE_J2D_DI_CMD_WDTH; |
| 163 | parameter DCR_CMD_MSB = DCR_CMD_LSB + DCR_CMD_WDTH - 1; |
| 164 | |
| 165 | // total rcd bit-width |
| 166 | parameter DCR_WDTH = DCR_CMD_LSB + DCR_CMD_WDTH; |
| 167 | |
| 168 | parameter FREE_RUNNING = 2'b00, |
| 169 | NPWR_STALL = 2'b01, |
| 170 | POTENTIAL_STALL = 2'b10, |
| 171 | NPRD_STALL = 2'b11; |
| 172 | |
| 173 | // -------------------------------------------------------- |
| 174 | // DMA CTAG Field Definitions |
| 175 | // -------------------------------------------------------- |
| 176 | |
| 177 | // misc field : {pktag[4:0], clsts}/mtag[5:0] |
| 178 | parameter DCTAG_MISC_LSB = 0; |
| 179 | parameter DCTAG_MISC_WDTH = 6; |
| 180 | parameter DCTAG_MISC_MSB = DCTAG_MISC_LSB + DCTAG_MISC_WDTH - 1; |
| 181 | |
| 182 | // dptr field |
| 183 | parameter DCTAG_DPTR_LSB = DCTAG_MISC_LSB + DCTAG_MISC_WDTH; |
| 184 | parameter DCTAG_DPTR_WDTH = 5; |
| 185 | parameter DCTAG_DPTR_MSB = DCTAG_DPTR_LSB + DCTAG_DPTR_WDTH - 1; |
| 186 | |
| 187 | // transaction number field |
| 188 | parameter DCTAG_TRNSNUM_LSB = DCTAG_DPTR_LSB + DCTAG_DPTR_WDTH; |
| 189 | parameter DCTAG_TRNSNUM_WDTH = 4; |
| 190 | parameter DCTAG_TRNSNUM_MSB = DCTAG_TRNSNUM_LSB + DCTAG_TRNSNUM_WDTH - 1; |
| 191 | |
| 192 | // type field |
| 193 | parameter DCTAG_TYP = DCTAG_TRNSNUM_LSB + DCTAG_TRNSNUM_WDTH; |
| 194 | |
| 195 | // -------------------------------------------------------- |
| 196 | // PIO Command Record (PCR) Field Definitions |
| 197 | // -------------------------------------------------------- |
| 198 | |
| 199 | // ctag field |
| 200 | parameter PCR_CTAG_LSB = 0; |
| 201 | parameter PCR_CTAG_WDTH = `FIRE_J2D_P_CTAG_WDTH; |
| 202 | parameter PCR_CTAG_MSB = PCR_CTAG_LSB + PCR_CTAG_WDTH - 1; |
| 203 | |
| 204 | // bmask field |
| 205 | parameter PCR_BMSK_LSB = PCR_CTAG_LSB + PCR_CTAG_WDTH; |
| 206 | parameter PCR_BMSK_WDTH = `FIRE_J2D_P_BMSK_WDTH; |
| 207 | parameter PCR_BMSK_MSB = PCR_BMSK_LSB + PCR_BMSK_WDTH - 1; |
| 208 | |
| 209 | // address field |
| 210 | parameter PCR_ADDR_LSB = PCR_BMSK_LSB + PCR_BMSK_WDTH; |
| 211 | parameter PCR_ADDR_WDTH = `FIRE_J2D_P_ADDR_WDTH; |
| 212 | parameter PCR_ADDR_MSB = PCR_ADDR_LSB + PCR_ADDR_WDTH - 1; |
| 213 | |
| 214 | // cmd field |
| 215 | parameter PCR_CMD_LSB = PCR_ADDR_LSB + PCR_ADDR_WDTH; |
| 216 | parameter PCR_CMD_WDTH = `FIRE_J2D_P_CMD_WDTH; |
| 217 | parameter PCR_CMD_MSB = PCR_CMD_LSB + PCR_CMD_WDTH - 1; |
| 218 | |
| 219 | // total rcd bit-width |
| 220 | parameter PCR_WDTH = PCR_CMD_LSB + PCR_CMD_WDTH; |
| 221 | |
| 222 | // -------------------------------------------------------- |
| 223 | // PIO CTAG Field Definitions |
| 224 | // -------------------------------------------------------- |
| 225 | |
| 226 | /* // trans_id field |
| 227 | // parameter PCTAG_TRNSID_LSB = 0; |
| 228 | // parameter PCTAG_TRNSID_WDTH = 2; |
| 229 | // parameter PCTAG_TRNSID_MSB = PCTAG_TRNSID_LSB + PCTAG_TRNSID_WDTH - 1; |
| 230 | // |
| 231 | // // agent_id field |
| 232 | // parameter PCTAG_AGNTID_LSB = PCTAG_TRNSID_LSB + PCTAG_TRNSID_WDTH; |
| 233 | // parameter PCTAG_AGNTID_WDTH = 4; |
| 234 | // parameter PCTAG_AGNTID_MSB = PCTAG_AGNTID_LSB + PCTAG_AGNTID_WDTH - 1; |
| 235 | */ |
| 236 | // N2, BP 05-24-04 |
| 237 | // // thread_id field |
| 238 | parameter PCTAG_THRDID_LSB = 0; |
| 239 | parameter PCTAG_THRDID_WDTH = 7; |
| 240 | parameter PCTAG_THRDID_MSB = PCTAG_THRDID_LSB + PCTAG_THRDID_WDTH - 1; |
| 241 | |
| 242 | // transaction number field |
| 243 | // parameter PCTAG_TRNSNUM_LSB = PCTAG_AGNTID_LSB + PCTAG_AGNTID_WDTH; |
| 244 | parameter PCTAG_TRNSNUM_LSB = PCTAG_THRDID_LSB + PCTAG_THRDID_WDTH; |
| 245 | parameter PCTAG_TRNSNUM_WDTH = 4; |
| 246 | parameter PCTAG_TRNSNUM_MSB = PCTAG_TRNSNUM_LSB + PCTAG_TRNSNUM_WDTH - 1; |
| 247 | |
| 248 | // >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 249 | |
| 250 | // -------------------------------------------------------- |
| 251 | // Clock/Reset Signals |
| 252 | // -------------------------------------------------------- |
| 253 | |
| 254 | input clk; |
| 255 | input rst_l; |
| 256 | |
| 257 | // -------------------------------------------------------- |
| 258 | // JBC Interface |
| 259 | // -------------------------------------------------------- |
| 260 | |
| 261 | // ----- DMA/INT CPL ----- |
| 262 | |
| 263 | // command port |
| 264 | input [(`FIRE_J2D_DI_CMD_WDTH - 1):0] j2d_di_cmd; |
| 265 | input [(`FIRE_J2D_DI_CTAG_WDTH - 1):0] j2d_di_ctag; |
| 266 | input j2d_di_cmd_vld; |
| 267 | |
| 268 | // data port |
| 269 | input [(`FIRE_J2D_D_DATA_WDTH - 1):0] j2d_d_data; |
| 270 | input [(`FIRE_J2D_D_DPAR_WDTH - 1):0] j2d_d_data_par; |
| 271 | input j2d_d_data_err; |
| 272 | input j2d_d_data_vld; |
| 273 | |
| 274 | // ----- PIO RD/WR REQ ----- |
| 275 | |
| 276 | // command port |
| 277 | input [(`FIRE_J2D_P_CMD_WDTH - 1):0] j2d_p_cmd; |
| 278 | input [(`FIRE_J2D_P_ADDR_WDTH - 1):0] j2d_p_addr; |
| 279 | input [(`FIRE_J2D_P_BMSK_WDTH - 1):0] j2d_p_bmsk; |
| 280 | input [(`FIRE_J2D_P_CTAG_WDTH - 1):0] j2d_p_ctag; |
| 281 | input j2d_p_cmd_vld; |
| 282 | |
| 283 | // data port |
| 284 | input [(`FIRE_J2D_P_DATA_WDTH - 1):0] j2d_p_data; |
| 285 | input [(`FIRE_J2D_P_DPAR_WDTH - 1):0] j2d_p_data_par; |
| 286 | input j2d_p_data_vld; |
| 287 | |
| 288 | // -------------------------------------------------------- |
| 289 | // ILU Interface |
| 290 | // -------------------------------------------------------- |
| 291 | |
| 292 | // ----- DOU-DMA Status Port ----- |
| 293 | output [(`FIRE_DLC_DOU_REL_WDTH - 1):0] k2y_dou_dptr; |
| 294 | output k2y_dou_err; |
| 295 | output k2y_dou_vld; |
| 296 | |
| 297 | // -------------------------------------------------------- |
| 298 | // PSB Interface |
| 299 | // -------------------------------------------------------- |
| 300 | |
| 301 | // ----- Scoreboard Access Port ----- |
| 302 | output [(`FIRE_DLC_PSR_CMD_TYPE_WDTH - 1):0] cl2ps_e_cmd_type; |
| 303 | output [(`FIRE_DLC_PSR_TRN_WDTH - 1):0] cl2ps_e_trn; |
| 304 | output [(`FIRE_DLC_PSR_PIO_DATA_WDTH - 1):0] cl2ps_e_wr_data; |
| 305 | output cl2ps_e_req; |
| 306 | input [(`FIRE_DLC_PSR_DMA_DATA_WDTH - 1):0] ps2cl_e_rd_data; |
| 307 | input ps2cl_e_gnt; |
| 308 | |
| 309 | // -------------------------------------------------------- |
| 310 | // CMU Interface |
| 311 | // -------------------------------------------------------- |
| 312 | |
| 313 | // ----- Egress Packet Record (EPR) Port ----- |
| 314 | output [(`FIRE_DLC_EPR_REC_WDTH - 1):0] cl2cm_rcd; |
| 315 | output cl2cm_rcd_enq; |
| 316 | input cm2cl_rcd_full; |
| 317 | |
| 318 | // -------------------------------------------------------- |
| 319 | // MMU Interface |
| 320 | // -------------------------------------------------------- |
| 321 | |
| 322 | // ----- Tablewalk Data Response (TDR) Port ----- |
| 323 | output [(`FIRE_DLC_TDR_WDTH - 1):0] cl2mm_tdr_rcd; |
| 324 | output cl2mm_tdr_vld; |
| 325 | |
| 326 | // -------------------------------------------------------- |
| 327 | // DOU Interface |
| 328 | // -------------------------------------------------------- |
| 329 | |
| 330 | // ----- DMA Data Buffer Write Port ----- |
| 331 | output [(`FIRE_DLC_CDD_DATA_WDTH - 1):0] cl2do_dma_data; |
| 332 | output [(`FIRE_DLC_CDD_DPAR_WDTH - 1):0] cl2do_dma_dpar; |
| 333 | output [(`FIRE_DLC_CDD_ADDR_WDTH - 1):0] cl2do_dma_addr; |
| 334 | output cl2do_dma_wr; |
| 335 | |
| 336 | // ----- PIO Data Buffer Write Port ----- |
| 337 | output [(`FIRE_DLC_CPD_DATA_WDTH - 1):0] cl2do_pio_data; |
| 338 | output [(`FIRE_DLC_CPD_DPAR_WDTH - 1):0] cl2do_pio_dpar; |
| 339 | output [(`FIRE_DLC_CPD_ADDR_WDTH - 1):0] cl2do_pio_addr; |
| 340 | output cl2do_pio_wr; |
| 341 | |
| 342 | // -------------------------------------------------------- |
| 343 | // CTM Interface |
| 344 | // -------------------------------------------------------- |
| 345 | |
| 346 | // ----- Unsupported Request Record (URR) Port ----- |
| 347 | output crm2ctm_rcd_deq; |
| 348 | input [(`FIRE_DLC_CLU_URR_WDTH - 1):0] ctm2crm_rcd; |
| 349 | input ctm2crm_rcd_enq; |
| 350 | |
| 351 | // ----- DMA/INT Tag Return Port ----- |
| 352 | output [3:0] crm2ctm_tag; |
| 353 | output crm2ctm_tag_enq; |
| 354 | |
| 355 | // ----- from peu force 1 non-posted write outstanding ----- |
| 356 | input p2d_npwr_stall_en; |
| 357 | input rm2crm_npwr_wrack; |
| 358 | |
| 359 | input im2crm_bc_stall_en; |
| 360 | input im2crm_ilu_stall_en; |
| 361 | input il2cl_gr_16; |
| 362 | |
| 363 | |
| 364 | // used for npwr stall to keep ehb from filling |
| 365 | input d2j_cmd_bit3; |
| 366 | input d2j_cmd_vld; |
| 367 | // -------------------------------------------------------- |
| 368 | // CRU Interface |
| 369 | // -------------------------------------------------------- |
| 370 | |
| 371 | // ----- Debug Ports ----- |
| 372 | output [`FIRE_DBG_DATA_BITS] crm_dbg0_bus_a; |
| 373 | output [`FIRE_DBG_DATA_BITS] crm_dbg0_bus_b; |
| 374 | output [`FIRE_DBG_DATA_BITS] crm_dbg1_bus_a; |
| 375 | output [`FIRE_DBG_DATA_BITS] crm_dbg1_bus_b; |
| 376 | input [2:0] cr2cl_dbg_sel_a; |
| 377 | input [2:0] cr2cl_dbg_sel_b; |
| 378 | |
| 379 | // ----- Config Packet Setup ----- |
| 380 | input [`FIRE_PCIE_BUS_NUM_BITS] cr2cl_bus_num; |
| 381 | |
| 382 | // >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<< |
| 383 | |
| 384 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTERS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 385 | |
| 386 | // ********** Flops ********** |
| 387 | |
| 388 | // debug ports |
| 389 | reg [`FIRE_DBG_DATA_BITS] dbg0_bus [0:1]; |
| 390 | reg [`FIRE_DBG_DATA_BITS] dbg1_bus [0:1]; |
| 391 | |
| 392 | // ********** Non-Flops ****** |
| 393 | |
| 394 | // debug ports |
| 395 | reg [2:0] dbg0_sel [0:1]; |
| 396 | reg [`FIRE_DBG_DATA_BITS] nxt_dbg0_bus [0:1]; |
| 397 | reg [2:0] dbg1_sel [0:1]; |
| 398 | reg [`FIRE_DBG_DATA_BITS] nxt_dbg1_bus [0:1]; |
| 399 | |
| 400 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ NETS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 401 | |
| 402 | // -------------------------------------------------------- |
| 403 | // DCR FIFO Interface |
| 404 | // -------------------------------------------------------- |
| 405 | |
| 406 | wire [(DCR_WDTH - 1):0] dcr_fifo_dout; |
| 407 | wire dcr_deq; |
| 408 | wire dcr_fifo_empty; |
| 409 | |
| 410 | // -------------------------------------------------------- |
| 411 | // PCR FIFO Interface |
| 412 | // -------------------------------------------------------- |
| 413 | |
| 414 | wire [(PCR_WDTH - 1):0] pcr_fifo_dout; |
| 415 | wire pcr_deq; |
| 416 | wire pcr_fifo_empty; |
| 417 | |
| 418 | // -------------------------------------------------------- |
| 419 | // URR FIFO Interface |
| 420 | // -------------------------------------------------------- |
| 421 | |
| 422 | wire [(`FIRE_DLC_CLU_URR_WDTH - 1):0] urr_fifo_dout; |
| 423 | wire urr_deq; |
| 424 | wire urr_fifo_empty; |
| 425 | |
| 426 | // -------------------------------------------------------- |
| 427 | // DCR Field Declarations |
| 428 | // -------------------------------------------------------- |
| 429 | |
| 430 | wire [(DCR_CMD_WDTH - 1):0] dcr_cmd; |
| 431 | wire [(DCR_CTAG_WDTH - 1):0] dcr_ctag; |
| 432 | |
| 433 | // -------------------------------------------------------- |
| 434 | // PCR Field Declarations |
| 435 | // -------------------------------------------------------- |
| 436 | |
| 437 | wire [(PCR_CMD_WDTH - 1):0] pcr_cmd; |
| 438 | wire [(PCR_ADDR_WDTH - 1):0] pcr_addr; |
| 439 | wire [(PCR_BMSK_WDTH - 1):0] pcr_bmsk; |
| 440 | wire [(PCR_CTAG_WDTH - 1):0] pcr_ctag; |
| 441 | |
| 442 | // -------------------------------------------------------- |
| 443 | // URR Field Declarations |
| 444 | // -------------------------------------------------------- |
| 445 | |
| 446 | wire [(`FIRE_DLC_CLU_URR_TYP_WDTH - 1):0] urr_typ; |
| 447 | wire [(`FIRE_DLC_CLU_URR_SBDTAG_WDTH - 1):0] urr_sbdtag; |
| 448 | |
| 449 | // -------------------------------------------------------- |
| 450 | // TDR Field Declarations |
| 451 | // -------------------------------------------------------- |
| 452 | |
| 453 | wire tdr_cerr; |
| 454 | wire tdr_derr; |
| 455 | wire [(`FIRE_DLC_TDR_MTAG_WDTH - 1):0] tdr_mtag; |
| 456 | wire [(`FIRE_DLC_TDR_DPAR_WDTH - 1):0] tdr_dpar; |
| 457 | wire [(`FIRE_DLC_TDR_DATA_WDTH - 1):0] tdr_data; |
| 458 | |
| 459 | // -------------------------------------------------------- |
| 460 | // DCR CTAG Field Declarations |
| 461 | // -------------------------------------------------------- |
| 462 | |
| 463 | wire [(DCTAG_MISC_WDTH - 1):0] dcr_ctag_misc; |
| 464 | wire [(DCTAG_DPTR_WDTH - 1):0] dcr_ctag_dptr; |
| 465 | wire [(DCTAG_TRNSNUM_WDTH - 1):0] dcr_ctag_trnsnum; |
| 466 | wire dcr_ctag_typ; |
| 467 | |
| 468 | // -------------------------------------------------------- |
| 469 | // PCR CTAG Field Declarations |
| 470 | // -------------------------------------------------------- |
| 471 | |
| 472 | wire [(PCTAG_TRNSNUM_WDTH - 1):0] pcr_ctag_trnsnum; |
| 473 | // BP N2 5-24-04 |
| 474 | // wire [(PCTAG_AGNTID_WDTH - 1):0] pcr_ctag_agntid; |
| 475 | // wire [(PCTAG_TRNSID_WDTH - 1):0] pcr_ctag_trnsid; |
| 476 | wire [(PCTAG_THRDID_WDTH - 1):0] pcr_ctag_thrdid; |
| 477 | |
| 478 | // -------------------------------------------------------- |
| 479 | // PSB RD_DATA (PSRD) Field Declarations |
| 480 | // -------------------------------------------------------- |
| 481 | |
| 482 | wire [(`FIRE_DLC_PSR_BYTECNT_WDTH - 1):0] psb_rd_bcnt; |
| 483 | wire [(`FIRE_DLC_PSR_LENGTH_WDTH - 1):0] psb_rd_len; |
| 484 | wire [(`FIRE_DLC_PSR_PKSEQ_WDTH - 1):0] psb_rd_pktseq; |
| 485 | wire [(`FIRE_DLC_PSR_CNTX_WDTH - 1):0] psb_rd_cntxtnum; |
| 486 | wire [(`FIRE_DLC_PSR_TRTAG_WDTH - 1):0] psb_rd_sbdtag; |
| 487 | |
| 488 | // -------------------------------------------------------- |
| 489 | // MISC |
| 490 | // -------------------------------------------------------- |
| 491 | |
| 492 | wire [4:0] dcr_pktag; |
| 493 | wire dcr_clsts; |
| 494 | wire pcr_typ; |
| 495 | wire mdo_vld; |
| 496 | wire drd_vld; |
| 497 | wire tdr_vld; |
| 498 | wire [1:0] pkt_sel; |
| 499 | wire epr_ld; |
| 500 | wire start_psb_op; |
| 501 | wire [1:0] psb_op_typ; |
| 502 | wire psb_ld; |
| 503 | wire [1:0] trn_sel; |
| 504 | wire done_psb_op; |
| 505 | wire done_psb_rd; |
| 506 | wire grnt_lck; |
| 507 | wire urr_grnt; |
| 508 | wire pcr_grnt; |
| 509 | wire dcr_grnt; |
| 510 | wire urr_req; |
| 511 | wire pcr_req; |
| 512 | wire dcr_req; |
| 513 | wire pcr_fifo_empty_out; |
| 514 | |
| 515 | // idle checks |
| 516 | wire crm_idle; |
| 517 | wire pktctlfsm_idle; |
| 518 | wire psbctlfsm_idle; |
| 519 | |
| 520 | // -------------------------------------------------------- |
| 521 | // Debug Ports |
| 522 | // -------------------------------------------------------- |
| 523 | |
| 524 | wire [3:0] pktctlfsm_state; |
| 525 | wire [4:0] psbctlfsm_state; |
| 526 | wire [7:0] inmod_dbg0_0; |
| 527 | wire [7:0] inmod_dbg0_1; |
| 528 | wire [7:0] inmod_dbg0_2; |
| 529 | wire [7:0] inmod_dbg0_3; |
| 530 | wire [7:0] inmod_dbg0_4; |
| 531 | wire [7:0] inmod_dbg0_5; |
| 532 | wire [7:0] inmod_dbg0_6; |
| 533 | wire [7:0] inmod_dbg0_7; |
| 534 | wire [7:0] inmod_dbg1_0; |
| 535 | wire [7:0] inmod_dbg1_1; |
| 536 | wire [7:0] inmod_dbg1_2; |
| 537 | wire [7:0] inmod_dbg1_3; |
| 538 | wire [7:0] inmod_dbg1_4; |
| 539 | wire [7:0] inmod_dbg1_5; |
| 540 | wire [7:0] inmod_dbg1_7; |
| 541 | |
| 542 | // >>>>>>>>>>>>>>>>>>>>>>>>> 0-in Checkers <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 543 | |
| 544 | // 0in kndr -var ps2cl_e_gnt |
| 545 | |
| 546 | // >>>>>>>>>>>>>>>>>>>>>>>>> RTL Model <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 547 | |
| 548 | // -------------------------------------------------------- |
| 549 | // IDLE Checker |
| 550 | // -------------------------------------------------------- |
| 551 | |
| 552 | assign crm_idle = (dcr_fifo_empty & pcr_fifo_empty & urr_fifo_empty & |
| 553 | pktctlfsm_idle & psbctlfsm_idle & ~j2d_d_data_vld & |
| 554 | ~j2d_p_data_vld & ~cl2mm_tdr_vld & ~cl2do_dma_wr & |
| 555 | ~cl2do_pio_wr & ~k2y_dou_vld); |
| 556 | |
| 557 | // -------------------------------------------------------- |
| 558 | // Debug Port 0 |
| 559 | // -------------------------------------------------------- |
| 560 | |
| 561 | // ----- debug0 bus assignments ---------------- |
| 562 | |
| 563 | assign inmod_dbg0_0 = {j2d_di_cmd_vld, j2d_d_data_vld, j2d_d_data_err, |
| 564 | j2d_p_cmd_vld, j2d_p_data_vld, cl2cm_rcd_enq, |
| 565 | cm2cl_rcd_full, cl2mm_tdr_vld}; |
| 566 | assign inmod_dbg0_1 = {cl2do_dma_wr, cl2do_dma_addr}; |
| 567 | assign inmod_dbg0_2 = {1'b0, k2y_dou_vld, k2y_dou_err, k2y_dou_dptr}; |
| 568 | assign inmod_dbg0_3 = {1'b0, cl2ps_e_req, ps2cl_e_gnt, cl2ps_e_trn}; |
| 569 | assign inmod_dbg0_4 = {1'b0, cl2do_pio_wr, cl2do_pio_addr}; |
| 570 | assign inmod_dbg0_5 = {1'b0, crm2ctm_rcd_deq, ctm2crm_rcd_enq, |
| 571 | crm2ctm_tag_enq, crm2ctm_tag}; |
| 572 | assign inmod_dbg0_6 = {dcr_fifo_empty, dcr_deq, pcr_fifo_empty, pcr_deq, |
| 573 | urr_fifo_empty, urr_deq, tdr_cerr, tdr_derr}; |
| 574 | assign inmod_dbg0_7 = {dcr_ctag_trnsnum, pcr_ctag_trnsnum}; |
| 575 | |
| 576 | // ----- debug0 port logic --------------------- |
| 577 | |
| 578 | // debug0 select assignments |
| 579 | always @(cr2cl_dbg_sel_a or cr2cl_dbg_sel_b) |
| 580 | begin |
| 581 | dbg0_sel[0] = cr2cl_dbg_sel_a; |
| 582 | dbg0_sel[1] = cr2cl_dbg_sel_b; |
| 583 | end |
| 584 | |
| 585 | // debug0_bus select |
| 586 | always @(dbg0_sel[0] or dbg0_sel[1] or inmod_dbg0_0 or inmod_dbg0_1 or |
| 587 | inmod_dbg0_2 or inmod_dbg0_3 or inmod_dbg0_4 or inmod_dbg0_5 or |
| 588 | inmod_dbg0_6 or inmod_dbg0_7) |
| 589 | begin : dbg0_bus_sel |
| 590 | integer i; |
| 591 | for (i=0; i<2; i=i+1) |
| 592 | begin |
| 593 | case (dbg0_sel[i]) // synopsys infer_mux |
| 594 | 3'b000: nxt_dbg0_bus[i] = inmod_dbg0_0; |
| 595 | 3'b001: nxt_dbg0_bus[i] = inmod_dbg0_1; |
| 596 | 3'b010: nxt_dbg0_bus[i] = inmod_dbg0_2; |
| 597 | 3'b011: nxt_dbg0_bus[i] = inmod_dbg0_3; |
| 598 | 3'b100: nxt_dbg0_bus[i] = inmod_dbg0_4; |
| 599 | 3'b101: nxt_dbg0_bus[i] = inmod_dbg0_5; |
| 600 | 3'b110: nxt_dbg0_bus[i] = inmod_dbg0_6; |
| 601 | 3'b111: nxt_dbg0_bus[i] = inmod_dbg0_7; |
| 602 | endcase |
| 603 | end |
| 604 | end |
| 605 | |
| 606 | // register debug0 busses |
| 607 | always @(posedge clk) |
| 608 | if (~rst_l) |
| 609 | begin : dbg0_bus_reg_reset |
| 610 | integer i; |
| 611 | for (i=0; i<2; i=i+1) |
| 612 | begin |
| 613 | dbg0_bus[i] <= `FIRE_DEBUG_WDTH'b0; |
| 614 | end |
| 615 | end |
| 616 | else begin : dbg0_bus_reg |
| 617 | integer i; |
| 618 | for (i=0; i<2; i=i+1) |
| 619 | begin |
| 620 | dbg0_bus[i] <= nxt_dbg0_bus[i]; |
| 621 | end |
| 622 | end |
| 623 | |
| 624 | // output debug0 busses |
| 625 | assign crm_dbg0_bus_a = dbg0_bus[0]; |
| 626 | assign crm_dbg0_bus_b = dbg0_bus[1]; |
| 627 | |
| 628 | // -------------------------------------------------------- |
| 629 | // Debug Port 1 |
| 630 | // -------------------------------------------------------- |
| 631 | |
| 632 | // ----- debug1 bus assignments ---------------- |
| 633 | |
| 634 | assign inmod_dbg1_0 = {2'b0, dcr_ctag_typ, dcr_clsts, pcr_typ, mdo_vld, |
| 635 | drd_vld, tdr_vld}; |
| 636 | assign inmod_dbg1_1 = {2'b0, epr_ld, psb_ld, pkt_sel, trn_sel}; |
| 637 | assign inmod_dbg1_2 = {3'b0, psb_op_typ, start_psb_op, done_psb_op, |
| 638 | done_psb_rd}; |
| 639 | assign inmod_dbg1_3 = {1'b0, grnt_lck, urr_req, pcr_req, dcr_req, urr_grnt, |
| 640 | pcr_grnt, dcr_grnt}; |
| 641 | assign inmod_dbg1_4 = {4'b0, pktctlfsm_state}; |
| 642 | assign inmod_dbg1_5 = {3'b0, psbctlfsm_state}; |
| 643 | assign inmod_dbg1_7 = {7'b0, crm_idle}; |
| 644 | |
| 645 | // ----- debug1 port logic --------------------- |
| 646 | |
| 647 | // debug1 select assignments |
| 648 | always @(cr2cl_dbg_sel_a or cr2cl_dbg_sel_b) |
| 649 | begin |
| 650 | dbg1_sel[0] = cr2cl_dbg_sel_a; |
| 651 | dbg1_sel[1] = cr2cl_dbg_sel_b; |
| 652 | end |
| 653 | |
| 654 | // debug1_bus select |
| 655 | always @(dbg1_sel[0] or dbg1_sel[1] or inmod_dbg1_0 or inmod_dbg1_1 or |
| 656 | inmod_dbg1_2 or inmod_dbg1_3 or inmod_dbg1_4 or inmod_dbg1_5 or |
| 657 | inmod_dbg1_7) |
| 658 | begin : dbg1_bus_sel |
| 659 | integer i; |
| 660 | for (i=0; i<2; i=i+1) |
| 661 | begin |
| 662 | case (dbg1_sel[i]) // synopsys infer_mux |
| 663 | 3'b000: nxt_dbg1_bus[i] = inmod_dbg1_0; |
| 664 | 3'b001: nxt_dbg1_bus[i] = inmod_dbg1_1; |
| 665 | 3'b010: nxt_dbg1_bus[i] = inmod_dbg1_2; |
| 666 | 3'b011: nxt_dbg1_bus[i] = inmod_dbg1_3; |
| 667 | 3'b100: nxt_dbg1_bus[i] = inmod_dbg1_4; |
| 668 | 3'b101: nxt_dbg1_bus[i] = inmod_dbg1_5; |
| 669 | 3'b110: nxt_dbg1_bus[i] = 8'h0; |
| 670 | 3'b111: nxt_dbg1_bus[i] = inmod_dbg1_7; |
| 671 | endcase |
| 672 | end |
| 673 | end |
| 674 | |
| 675 | // register debug1 busses |
| 676 | always @(posedge clk) |
| 677 | if (~rst_l) |
| 678 | begin : dbg1_bus_reg_reset |
| 679 | integer i; |
| 680 | for (i=0; i<2; i=i+1) |
| 681 | begin |
| 682 | dbg1_bus[i] <= `FIRE_DEBUG_WDTH'b0; |
| 683 | end |
| 684 | end |
| 685 | else begin : dbg1_bus_reg |
| 686 | integer i; |
| 687 | for (i=0; i<2; i=i+1) |
| 688 | begin |
| 689 | dbg1_bus[i] <= nxt_dbg1_bus[i]; |
| 690 | end |
| 691 | end |
| 692 | |
| 693 | // output debug1 busses |
| 694 | assign crm_dbg1_bus_a = dbg1_bus[0]; |
| 695 | assign crm_dbg1_bus_b = dbg1_bus[1]; |
| 696 | |
| 697 | // -------------------------------------------------------- |
| 698 | // DCR Field Assignments |
| 699 | // -------------------------------------------------------- |
| 700 | |
| 701 | // dcr field assignments |
| 702 | assign dcr_cmd = dcr_fifo_dout[DCR_CMD_MSB:DCR_CMD_LSB]; |
| 703 | assign dcr_ctag = dcr_fifo_dout[DCR_CTAG_MSB:DCR_CTAG_LSB]; |
| 704 | |
| 705 | // dcr ctag assignments |
| 706 | assign dcr_ctag_typ = dcr_ctag[DCTAG_TYP]; |
| 707 | assign dcr_ctag_trnsnum = dcr_ctag[DCTAG_TRNSNUM_MSB:DCTAG_TRNSNUM_LSB]; |
| 708 | assign dcr_ctag_dptr = dcr_ctag[DCTAG_DPTR_MSB:DCTAG_DPTR_LSB]; |
| 709 | assign dcr_ctag_misc = dcr_ctag[DCTAG_MISC_MSB:DCTAG_MISC_LSB]; |
| 710 | |
| 711 | // dcr pktag assignment for pktgen |
| 712 | assign dcr_pktag = dcr_ctag_misc[5:1]; |
| 713 | // dcr cl_sts assignment for pktctlfsm |
| 714 | assign dcr_clsts = dcr_ctag_misc[0]; |
| 715 | |
| 716 | // -------------------------------------------------------- |
| 717 | // PCR Field Assignments |
| 718 | // -------------------------------------------------------- |
| 719 | |
| 720 | // pcr field assignments |
| 721 | assign pcr_cmd = pcr_fifo_dout[PCR_CMD_MSB:PCR_CMD_LSB]; |
| 722 | assign pcr_addr = pcr_fifo_dout[PCR_ADDR_MSB:PCR_ADDR_LSB]; |
| 723 | assign pcr_bmsk = pcr_fifo_dout[PCR_BMSK_MSB:PCR_BMSK_LSB]; |
| 724 | assign pcr_ctag = pcr_fifo_dout[PCR_CTAG_MSB:PCR_CTAG_LSB]; |
| 725 | |
| 726 | // pcr ctag assignments |
| 727 | assign pcr_ctag_trnsnum = pcr_ctag[PCTAG_TRNSNUM_MSB:PCTAG_TRNSNUM_LSB]; |
| 728 | //BP n2 5-24-04 |
| 729 | // assign pcr_ctag_agntid = pcr_ctag[PCTAG_AGNTID_MSB:PCTAG_AGNTID_LSB]; |
| 730 | // assign pcr_ctag_trnsid = pcr_ctag[PCTAG_TRNSID_MSB:PCTAG_TRNSID_LSB]; |
| 731 | assign pcr_ctag_thrdid = pcr_ctag[PCTAG_THRDID_MSB:PCTAG_THRDID_LSB]; |
| 732 | |
| 733 | // -------------------------------------------------------- |
| 734 | // URR Field Assignments |
| 735 | // -------------------------------------------------------- |
| 736 | |
| 737 | assign urr_typ = urr_fifo_dout[`FIRE_DLC_CLU_URR_TYP]; |
| 738 | assign urr_sbdtag = urr_fifo_dout[`FIRE_DLC_CLU_URR_SBDTAG]; |
| 739 | |
| 740 | // -------------------------------------------------------- |
| 741 | // PSB RD_DATA Field Assignments |
| 742 | // -------------------------------------------------------- |
| 743 | |
| 744 | assign psb_rd_bcnt = ps2cl_e_rd_data[`FIRE_DLC_PSR_BYTECNT]; |
| 745 | assign psb_rd_len = ps2cl_e_rd_data[`FIRE_DLC_PSR_LENGTH]; |
| 746 | assign psb_rd_pktseq = ps2cl_e_rd_data[`FIRE_DLC_PSR_PKSEQ]; |
| 747 | assign psb_rd_cntxtnum = ps2cl_e_rd_data[`FIRE_DLC_PSR_CNTX]; |
| 748 | assign psb_rd_sbdtag = ps2cl_e_rd_data[`FIRE_DLC_PSR_TRTAG]; |
| 749 | |
| 750 | // -------------------------------------------------------- |
| 751 | // TDR Construction |
| 752 | // -------------------------------------------------------- |
| 753 | |
| 754 | assign cl2mm_tdr_rcd[`FIRE_DLC_TDR_CERR] = tdr_cerr; |
| 755 | assign cl2mm_tdr_rcd[`FIRE_DLC_TDR_DERR] = tdr_derr; |
| 756 | assign cl2mm_tdr_rcd[`FIRE_DLC_TDR_MTAG] = tdr_mtag; |
| 757 | assign cl2mm_tdr_rcd[`FIRE_DLC_TDR_DPAR] = tdr_dpar; |
| 758 | assign cl2mm_tdr_rcd[`FIRE_DLC_TDR_DATA] = tdr_data; |
| 759 | |
| 760 | // >>>>>>>>>>>>>>>>>>>>>>>>> Instantiations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 761 | |
| 762 | // PKTCTLFSM |
| 763 | dmu_clu_crm_pktctlfsm pktctlfsm |
| 764 | ( |
| 765 | // clock/reset |
| 766 | .clk (clk), |
| 767 | .rst_l (rst_l), |
| 768 | |
| 769 | // fsm inputs |
| 770 | .dcr_fifo_empty (dcr_fifo_empty), |
| 771 | .pcr_fifo_empty (pcr_fifo_empty), |
| 772 | .urr_fifo_empty (urr_fifo_empty), |
| 773 | .dcr_grnt (dcr_grnt), |
| 774 | .pcr_grnt (pcr_grnt), |
| 775 | .urr_grnt (urr_grnt), |
| 776 | .cm2cl_rcd_full (cm2cl_rcd_full), |
| 777 | .done_psb_op (done_psb_op), |
| 778 | .pcr_typ (pcr_typ), |
| 779 | .mdo_vld (mdo_vld), |
| 780 | .drd_vld (drd_vld), |
| 781 | .tdr_vld (tdr_vld), |
| 782 | .dcr_clsts (dcr_clsts), |
| 783 | |
| 784 | // fsm outputs |
| 785 | .dcr_req (dcr_req), |
| 786 | .pcr_req (pcr_req), |
| 787 | .urr_req (urr_req), |
| 788 | .dcr_deq (dcr_deq), |
| 789 | .pcr_deq (pcr_deq), |
| 790 | .urr_deq (urr_deq), |
| 791 | .grnt_lck (grnt_lck), |
| 792 | .pkt_sel (pkt_sel), |
| 793 | .epr_ld (epr_ld), |
| 794 | .cl2cm_rcd_enq (cl2cm_rcd_enq), |
| 795 | .crm2ctm_tag_enq (crm2ctm_tag_enq), |
| 796 | .crm2ctm_rcd_deq (crm2ctm_rcd_deq), |
| 797 | .start_psb_op (start_psb_op), |
| 798 | .psb_op_typ (psb_op_typ), |
| 799 | .psb_ld (psb_ld), |
| 800 | .trn_sel (trn_sel), |
| 801 | |
| 802 | // debug port |
| 803 | .pktctlfsm_state (pktctlfsm_state), |
| 804 | |
| 805 | // idle checker port |
| 806 | .pktctlfsm_idle (pktctlfsm_idle) |
| 807 | ); |
| 808 | |
| 809 | // PSBCTLFSM |
| 810 | dmu_clu_crm_psbctlfsm psbctlfsm |
| 811 | ( |
| 812 | // clock/reset |
| 813 | .clk (clk), |
| 814 | .rst_l (rst_l), |
| 815 | |
| 816 | // fsm inputs |
| 817 | .start_psb_op (start_psb_op), |
| 818 | .psb_op_typ (psb_op_typ), |
| 819 | .ps2cl_e_gnt (ps2cl_e_gnt), |
| 820 | |
| 821 | // fsm outputs |
| 822 | .done_psb_op (done_psb_op), |
| 823 | .done_psb_rd (done_psb_rd), |
| 824 | .cl2ps_e_req (cl2ps_e_req), |
| 825 | .cl2ps_e_cmd_type (cl2ps_e_cmd_type), |
| 826 | |
| 827 | // debug port |
| 828 | .psbctlfsm_state (psbctlfsm_state), |
| 829 | |
| 830 | // idle checker port |
| 831 | .psbctlfsm_idle (psbctlfsm_idle) |
| 832 | ); |
| 833 | |
| 834 | // ARBITER |
| 835 | dmu_clu_crm_arb arb |
| 836 | ( |
| 837 | // clock/reset |
| 838 | .clk (clk), |
| 839 | .rst_l (rst_l), |
| 840 | |
| 841 | // ctl port |
| 842 | .grant ({urr_grnt, pcr_grnt, dcr_grnt}), |
| 843 | .req ({urr_req, pcr_req, dcr_req}), |
| 844 | .grnt_lck (grnt_lck) |
| 845 | ); |
| 846 | |
| 847 | // PKTGEN |
| 848 | dmu_clu_crm_pktgen pktgen |
| 849 | ( |
| 850 | // clock |
| 851 | .clk (clk), |
| 852 | .rst_l (rst_l), |
| 853 | |
| 854 | // cmu : epr port |
| 855 | .cl2cm_rcd (cl2cm_rcd), |
| 856 | |
| 857 | // psb : sbd access port |
| 858 | .cl2ps_e_trn (cl2ps_e_trn), |
| 859 | .cl2ps_e_wr_data (cl2ps_e_wr_data), |
| 860 | .psb_rd_bcnt (psb_rd_bcnt), |
| 861 | .psb_rd_len (psb_rd_len), |
| 862 | .psb_rd_pktseq (psb_rd_pktseq), |
| 863 | .psb_rd_cntxtnum (psb_rd_cntxtnum), |
| 864 | .psb_rd_sbdtag (psb_rd_sbdtag), |
| 865 | |
| 866 | // cru : config packet setup |
| 867 | .cr2cl_bus_num (cr2cl_bus_num), |
| 868 | |
| 869 | // ctm : tag return port |
| 870 | .crm2ctm_tag (crm2ctm_tag), |
| 871 | |
| 872 | // pkt_gen sel port |
| 873 | .pkt_sel (pkt_sel), |
| 874 | .psb_ld (psb_ld), |
| 875 | .trn_sel (trn_sel), |
| 876 | .epr_ld (epr_ld), |
| 877 | .done_psb_rd (done_psb_rd), |
| 878 | |
| 879 | // dcr port |
| 880 | .dcr_cmd (dcr_cmd), |
| 881 | .dcr_ctag_typ (dcr_ctag_typ), |
| 882 | .dcr_ctag_trnsnum (dcr_ctag_trnsnum), |
| 883 | .dcr_ctag_dptr (dcr_ctag_dptr), |
| 884 | .dcr_pktag (dcr_pktag), |
| 885 | |
| 886 | // pcr port |
| 887 | .pcr_cmd (pcr_cmd), |
| 888 | .pcr_addr (pcr_addr), |
| 889 | .pcr_bmsk (pcr_bmsk), |
| 890 | .pcr_ctag_trnsnum (pcr_ctag_trnsnum), |
| 891 | //BP n2 5-24-04 |
| 892 | // .pcr_ctag_agntid (pcr_ctag_agntid), |
| 893 | // .pcr_ctag_trnsid (pcr_ctag_trnsid), |
| 894 | .pcr_ctag_thrdid (pcr_ctag_thrdid), |
| 895 | |
| 896 | // urr port |
| 897 | .urr_typ (urr_typ), |
| 898 | .urr_sbdtag (urr_sbdtag), |
| 899 | |
| 900 | // type port |
| 901 | .mdo_vld (mdo_vld), |
| 902 | .drd_vld (drd_vld), |
| 903 | .tdr_vld (tdr_vld), |
| 904 | .pcr_typ (pcr_typ) |
| 905 | ); |
| 906 | |
| 907 | // DATA CTL |
| 908 | dmu_clu_crm_datactl datactl |
| 909 | ( |
| 910 | // clock/reset |
| 911 | .clk (clk), |
| 912 | .rst_l (rst_l), |
| 913 | |
| 914 | // jbc: dma data ctl port |
| 915 | .dctag_typ (j2d_di_ctag[DCTAG_TYP]), |
| 916 | .dctag_dptr (j2d_di_ctag[DCTAG_DPTR_MSB:DCTAG_DPTR_LSB]), |
| 917 | .dctag_misc (j2d_di_ctag[DCTAG_MISC_MSB:DCTAG_MISC_LSB]), |
| 918 | .j2d_di_cmd (j2d_di_cmd), |
| 919 | .j2d_di_cmd_vld (j2d_di_cmd_vld), |
| 920 | .j2d_d_data_err (j2d_d_data_err), |
| 921 | .j2d_d_data_vld (j2d_d_data_vld), |
| 922 | |
| 923 | // jbc: pio data ctl port |
| 924 | .pctag_trnsnum (j2d_p_ctag[PCTAG_TRNSNUM_MSB:PCTAG_TRNSNUM_LSB]), |
| 925 | .j2d_p_cmd_vld (j2d_p_cmd_vld), |
| 926 | .j2d_p_data_vld (j2d_p_data_vld), |
| 927 | |
| 928 | // mmu: tdr port |
| 929 | .tdr_mtag (tdr_mtag), |
| 930 | .tdr_cerr (tdr_cerr), |
| 931 | .cl2mm_tdr_vld (cl2mm_tdr_vld), |
| 932 | |
| 933 | // dou: data ctl port |
| 934 | .cl2do_dma_addr (cl2do_dma_addr), |
| 935 | .cl2do_dma_wr (cl2do_dma_wr), |
| 936 | .cl2do_pio_addr (cl2do_pio_addr), |
| 937 | .cl2do_pio_wr (cl2do_pio_wr), |
| 938 | |
| 939 | // ilu: cacheline sts port |
| 940 | .k2y_dou_dptr (k2y_dou_dptr), |
| 941 | .k2y_dou_err (k2y_dou_err), |
| 942 | .k2y_dou_vld (k2y_dou_vld) |
| 943 | ); |
| 944 | |
| 945 | // DATA PIPE |
| 946 | dmu_clu_crm_datapipe datapipe |
| 947 | ( |
| 948 | // clock |
| 949 | .clk (clk), |
| 950 | .rst_l (rst_l), |
| 951 | |
| 952 | // jbc: dma data port |
| 953 | .j2d_d_data_vld (j2d_d_data_vld), |
| 954 | .j2d_d_data (j2d_d_data), |
| 955 | .j2d_d_data_par (j2d_d_data_par), |
| 956 | .j2d_d_data_err (j2d_d_data_err), |
| 957 | |
| 958 | // jbc: pio data port |
| 959 | .j2d_p_data (j2d_p_data), |
| 960 | .j2d_p_data_par (j2d_p_data_par), |
| 961 | |
| 962 | // mmu: tdr port |
| 963 | .tdr_data (tdr_data), |
| 964 | .tdr_dpar (tdr_dpar), |
| 965 | .tdr_derr (tdr_derr), |
| 966 | |
| 967 | // dou: data port |
| 968 | .cl2do_dma_data (cl2do_dma_data), |
| 969 | .cl2do_dma_dpar (cl2do_dma_dpar), |
| 970 | .cl2do_pio_data (cl2do_pio_data), |
| 971 | .cl2do_pio_dpar (cl2do_pio_dpar) |
| 972 | ); |
| 973 | |
| 974 | // -------------------------------------------------------------------------- |
| 975 | // NOTE: |
| 976 | // *** DCR FIFO *** |
| 977 | // |
| 978 | // the "fifo_full port" is unconnected since this fifo serves as a cmd |
| 979 | // buffer for the JBC-DMC interface. this interface is "cmd push", |
| 980 | // hence no back-pressure ability. this fifo is maximally sized at 16 |
| 981 | // entries according to the credit base specified by the JBC-DMC |
| 982 | // interface protocol. |
| 983 | // -------------------------------------------------------------------------- |
| 984 | |
| 985 | // DCR FIFO |
| 986 | dmu_common_simple_fifo |
| 987 | #(DCR_WDTH, DCR_FDEPTH, DCR_FPTR_WDTH, DCR_FDEPTH_MINONE) dcr_fifo |
| 988 | ( |
| 989 | // clock/reset |
| 990 | .clk (clk), |
| 991 | .rst_l (rst_l), |
| 992 | |
| 993 | // enq port |
| 994 | .data_in ({j2d_di_cmd, j2d_di_ctag}), |
| 995 | .write (j2d_di_cmd_vld), |
| 996 | |
| 997 | // deq port |
| 998 | .data_out (dcr_fifo_dout), |
| 999 | .read (dcr_deq), |
| 1000 | |
| 1001 | // status port |
| 1002 | .fifo_full (), |
| 1003 | .fifo_almost_full (), |
| 1004 | .fifo_empty (dcr_fifo_empty) |
| 1005 | ); |
| 1006 | |
| 1007 | // -------------------------------------------------------------------------- |
| 1008 | // NOTE: |
| 1009 | // *** PCR FIFO *** |
| 1010 | // |
| 1011 | // the "fifo_full port" is unconnected since this fifo serves as a cmd |
| 1012 | // buffer for the JBC-DMC interface. this interface is "cmd push", |
| 1013 | // hence no back-pressure ability. this fifo is maximally sized at 16 |
| 1014 | // entries according to the credit base specified by the JBC-DMC |
| 1015 | // interface protocol. |
| 1016 | // -------------------------------------------------------------------------- |
| 1017 | |
| 1018 | // PCR FIFO |
| 1019 | dmu_common_simple_fifo |
| 1020 | #(PCR_WDTH, PCR_FDEPTH, PCR_FPTR_WDTH, PCR_FDEPTH_MINONE) pcr_fifo |
| 1021 | ( |
| 1022 | // clock/reset |
| 1023 | .clk (clk), |
| 1024 | .rst_l (rst_l), |
| 1025 | |
| 1026 | // enq port |
| 1027 | .data_in ({j2d_p_cmd, j2d_p_addr, j2d_p_bmsk, j2d_p_ctag}), |
| 1028 | .write (j2d_p_cmd_vld), |
| 1029 | |
| 1030 | // deq port |
| 1031 | .data_out (pcr_fifo_dout), |
| 1032 | .read (pcr_deq), |
| 1033 | |
| 1034 | // status port |
| 1035 | .fifo_full (), |
| 1036 | .fifo_almost_full (), |
| 1037 | .fifo_empty (pcr_fifo_empty_out) |
| 1038 | ); |
| 1039 | |
| 1040 | //BP npwr is non-posted pio write |
| 1041 | // 12-02-05 for bug 106560, if PIO write is non-posted(config or I/O write) then |
| 1042 | // if enabled force only 1 outstanding non-posted write |
| 1043 | wire sync_npwr_stall_en; |
| 1044 | reg [1:0] stall_state; |
| 1045 | reg [1:0] next_stall_state; |
| 1046 | wire non_post_write = ( (pcr_cmd[3:0]== 4'b0110) | (pcr_cmd[3:0] == 4'b0111) ) & pcr_deq; |
| 1047 | cl_a1_clksyncff_4x npwr_stall_syncff ( .d(p2d_npwr_stall_en), .si(1'b0), .q( sync_npwr_stall_en), .so(), |
| 1048 | .l1clk(clk), .siclk(1'b0), .soclk(1'b0) ); |
| 1049 | |
| 1050 | reg npwr_stall_d; |
| 1051 | always @(posedge clk) |
| 1052 | if (~rst_l) |
| 1053 | begin |
| 1054 | npwr_stall_d <= 1'b0; |
| 1055 | end |
| 1056 | else if (rm2crm_npwr_wrack ) |
| 1057 | begin |
| 1058 | npwr_stall_d <= 1'b0; |
| 1059 | end |
| 1060 | else if (sync_npwr_stall_en & non_post_write ) |
| 1061 | begin |
| 1062 | npwr_stall_d <= 1'b1; |
| 1063 | end |
| 1064 | else |
| 1065 | begin |
| 1066 | npwr_stall_d <= npwr_stall_d; |
| 1067 | end |
| 1068 | |
| 1069 | reg [4:0] pw_count; |
| 1070 | reg [4:0] nprd_count; |
| 1071 | wire state_stall_decode = ((stall_state == 2'b01) | (stall_state == 2'b11) | |
| 1072 | ((stall_state == 2'b10) & ((nprd_count + pw_count) == 5'b11111) ) ) |
| 1073 | & im2crm_bc_stall_en; |
| 1074 | |
| 1075 | //BP tmp wire npwr_stall = npwr_stall_d & sync_npwr_stall_en; |
| 1076 | wire npwr_stall = (npwr_stall_d & sync_npwr_stall_en & !im2crm_bc_stall_en) | |
| 1077 | state_stall_decode | |
| 1078 | il2cl_gr_16 & im2crm_ilu_stall_en; |
| 1079 | |
| 1080 | |
| 1081 | assign pcr_fifo_empty = npwr_stall | pcr_fifo_empty_out; |
| 1082 | // assign pcr_fifo_empty = pcr_fifo_empty_out; |
| 1083 | |
| 1084 | // -------------------------------------------------------------------------- |
| 1085 | // NOTE: |
| 1086 | // *** ehb full detect *** |
| 1087 | // |
| 1088 | // the following logic keeps the ehb from filling with pio's |
| 1089 | // |
| 1090 | // -------------------------------------------------------------------------- |
| 1091 | |
| 1092 | //0in mutex -var {non_post_rd,post_write,non_post_write}; |
| 1093 | wire non_post_rd = ( (pcr_cmd[3:0] == 4'b1000) | |
| 1094 | (pcr_cmd[3:0] == 4'b1001) | |
| 1095 | (pcr_cmd[3:0] == 4'b1100) | |
| 1096 | (pcr_cmd[3:0] == 4'b1101) | |
| 1097 | (pcr_cmd[3:0] == 4'b1110) | |
| 1098 | (pcr_cmd[3:0] == 4'b1111) ) & pcr_deq; |
| 1099 | |
| 1100 | wire post_write = ( (pcr_cmd[3:0] == 4'b0000) | |
| 1101 | (pcr_cmd[3:0] == 4'b0001) | |
| 1102 | (pcr_cmd[3:0] == 4'b0100) | |
| 1103 | (pcr_cmd[3:0] == 4'b0101) ) & pcr_deq; |
| 1104 | |
| 1105 | // decode pio rd cpls from d2j |
| 1106 | wire non_post_rd_ack = d2j_cmd_vld & (d2j_cmd_bit3 == 1'b1); |
| 1107 | |
| 1108 | // nprd_counter |
| 1109 | //0in max -val 16 -var nprd_count |
| 1110 | always @(posedge clk) |
| 1111 | if (~rst_l | ~im2crm_bc_stall_en) |
| 1112 | begin |
| 1113 | nprd_count <= 5'b0; |
| 1114 | end |
| 1115 | else if (non_post_rd & !non_post_rd_ack ) |
| 1116 | nprd_count <= nprd_count + 5'b1; |
| 1117 | else if (!non_post_rd & non_post_rd_ack ) |
| 1118 | nprd_count <= nprd_count - 5'b1; //0in < underflow |
| 1119 | else |
| 1120 | nprd_count <= nprd_count ; |
| 1121 | |
| 1122 | wire pw_counter_clear = ( (stall_state == 2'b01) & rm2crm_npwr_wrack) | |
| 1123 | ( ((stall_state == 2'b10) | (stall_state == 2'b11)) & (nprd_count == 5'b0) ) |
| 1124 | ; |
| 1125 | // pw_counter |
| 1126 | //0in max -val 31 -var nprd_count |
| 1127 | always @(posedge clk) |
| 1128 | if (~rst_l | ~im2crm_bc_stall_en) |
| 1129 | begin |
| 1130 | pw_count <= 5'b0; |
| 1131 | end |
| 1132 | else if (pw_counter_clear ) |
| 1133 | pw_count <= 5'b0; |
| 1134 | else if (post_write & (stall_state == 2'b10) ) |
| 1135 | pw_count <= pw_count + 5'b1; |
| 1136 | else |
| 1137 | pw_count <= pw_count ; |
| 1138 | |
| 1139 | |
| 1140 | always @(posedge clk) |
| 1141 | if (~rst_l | ~im2crm_bc_stall_en) |
| 1142 | begin |
| 1143 | stall_state <= 2'b0; |
| 1144 | end |
| 1145 | else |
| 1146 | begin |
| 1147 | stall_state <= next_stall_state; |
| 1148 | end |
| 1149 | |
| 1150 | always @( pw_count or nprd_count or post_write or non_post_rd or non_post_write or |
| 1151 | stall_state or rm2crm_npwr_wrack ) begin |
| 1152 | next_stall_state = 2'b00; |
| 1153 | |
| 1154 | case(stall_state) |
| 1155 | FREE_RUNNING: if(post_write) // FREE_RUNNING state_00 |
| 1156 | next_stall_state = 2'b00; |
| 1157 | else if (non_post_write) |
| 1158 | next_stall_state = 2'b01; |
| 1159 | else if (non_post_rd) |
| 1160 | next_stall_state = 2'b10; |
| 1161 | else |
| 1162 | next_stall_state = 2'b00; |
| 1163 | |
| 1164 | NPWR_STALL: if(rm2crm_npwr_wrack & (nprd_count == 5'b0) ) // NPWR_STALL state_01 |
| 1165 | next_stall_state = 2'b00; |
| 1166 | else if (rm2crm_npwr_wrack & (nprd_count != 5'b0) ) |
| 1167 | next_stall_state = 2'b10; |
| 1168 | else |
| 1169 | next_stall_state = 2'b01; |
| 1170 | |
| 1171 | POTENTIAL_STALL: if(non_post_write) // POTENTIAL_STALL state_10 |
| 1172 | next_stall_state = 2'b01; |
| 1173 | else if ((nprd_count == 5'b0) ) |
| 1174 | next_stall_state = 2'b00; |
| 1175 | else if((nprd_count + pw_count) == 5'b11111) |
| 1176 | next_stall_state = 2'b11; |
| 1177 | else |
| 1178 | next_stall_state = 2'b10; |
| 1179 | |
| 1180 | NPRD_STALL: if(non_post_write) // NPRD_STALL state_11 |
| 1181 | next_stall_state = 2'b01; |
| 1182 | else if ((nprd_count == 5'b0) ) |
| 1183 | next_stall_state = 2'b00; |
| 1184 | else if((nprd_count + pw_count) < 5'b11111) |
| 1185 | next_stall_state = 2'b10; |
| 1186 | else |
| 1187 | next_stall_state = 2'b11; |
| 1188 | endcase |
| 1189 | end |
| 1190 | |
| 1191 | |
| 1192 | // -------------------------------------------------------------------------- |
| 1193 | // NOTE: |
| 1194 | // *** URR FIFO *** |
| 1195 | // |
| 1196 | // the "fifo_full port" is unconnected since it is managed as a credit |
| 1197 | // based fifo. the credit management logic is located in the CTM. |
| 1198 | // -------------------------------------------------------------------------- |
| 1199 | |
| 1200 | // URR FIFO |
| 1201 | dmu_common_simple_fifo |
| 1202 | #(`FIRE_DLC_CLU_URR_WDTH, URR_FDEPTH, URR_FPTR_WDTH, URR_FDEPTH_MINONE) urr_fifo |
| 1203 | ( |
| 1204 | // clock/reset |
| 1205 | .clk (clk), |
| 1206 | .rst_l (rst_l), |
| 1207 | |
| 1208 | // enq port |
| 1209 | .data_in (ctm2crm_rcd), |
| 1210 | .write (ctm2crm_rcd_enq), |
| 1211 | |
| 1212 | // deq port |
| 1213 | .data_out (urr_fifo_dout), |
| 1214 | .read (urr_deq), |
| 1215 | |
| 1216 | // status port |
| 1217 | .fifo_full (), |
| 1218 | .fifo_almost_full (), |
| 1219 | .fifo_empty (urr_fifo_empty) |
| 1220 | ); |
| 1221 | |
| 1222 | endmodule // dmu_clu_crm |