| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_clu_ctm_bufmgr.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_clu_ctm_bufmgr |
| 36 | ( |
| 37 | // clock/reset |
| 38 | clk, |
| 39 | rst_l, |
| 40 | |
| 41 | // tmu: diu buffer mgr port |
| 42 | cl2tm_dma_rptr, |
| 43 | cl2tm_int_rptr, |
| 44 | tm2cl_dma_wptr, |
| 45 | tm2cl_pio_wptr, |
| 46 | |
| 47 | // rmu : dou dma buffer rel port |
| 48 | rm2cl_bufrel, |
| 49 | rm2cl_bufrel_enq, |
| 50 | |
| 51 | // diu : data read port |
| 52 | cl2di_addr, |
| 53 | |
| 54 | // dou buffer ctl/sts port |
| 55 | dma_dptr, |
| 56 | dou_space_avail, |
| 57 | dma_dptr_req, |
| 58 | dma_cltot, |
| 59 | |
| 60 | // diu buffer ctl/sts port |
| 61 | diu_dma_empty, |
| 62 | diu_pio_empty, |
| 63 | diu_typ_sel, |
| 64 | inc_dma_blk_addr, |
| 65 | inc_pio_blk_addr, |
| 66 | inc_eqw_blk_addr, |
| 67 | inc_mdo_blk_addr, |
| 68 | ld_diu_addr, |
| 69 | inc_diu_row_ptr, |
| 70 | |
| 71 | // idle checker port |
| 72 | dou_dptr_pool_full |
| 73 | ); |
| 74 | |
| 75 | // synopsys sync_set_reset "rst_l" |
| 76 | |
| 77 | // >>>>>>>>>>>>>>>>>>>>>>>>> Parameter Declarations <<<<<<<<<<<<<<<<<<<<<<<<< |
| 78 | |
| 79 | parameter DOU_DADDR_WDTH = 5; |
| 80 | parameter DOU_DADDR_NUM = 32; |
| 81 | |
| 82 | // >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 83 | |
| 84 | // -------------------------------------------------------- |
| 85 | // Clock/Reset Signals |
| 86 | // -------------------------------------------------------- |
| 87 | |
| 88 | input clk; |
| 89 | input rst_l; |
| 90 | |
| 91 | // -------------------------------------------------------- |
| 92 | // TMU Interface |
| 93 | // -------------------------------------------------------- |
| 94 | |
| 95 | // DIU Buffer Manager Port |
| 96 | output [(`FIRE_DLC_DMA_RPTR_WDTH - 1):0] cl2tm_dma_rptr; |
| 97 | output [(`FIRE_DLC_INT_RPTR_WDTH - 1):0] cl2tm_int_rptr; |
| 98 | input [(`FIRE_DLC_DMA_WPTR_WDTH - 1):0] tm2cl_dma_wptr; |
| 99 | input [(`FIRE_DLC_PIO_WPTR_WDTH - 1):0] tm2cl_pio_wptr; |
| 100 | |
| 101 | // -------------------------------------------------------- |
| 102 | // RMU Interface |
| 103 | // -------------------------------------------------------- |
| 104 | |
| 105 | // DOU DMA Buffer Release Port |
| 106 | input [(`FIRE_DLC_DOU_REL_WDTH - 1):0] rm2cl_bufrel; |
| 107 | input rm2cl_bufrel_enq; |
| 108 | |
| 109 | // -------------------------------------------------------- |
| 110 | // DIU Interface |
| 111 | // -------------------------------------------------------- |
| 112 | |
| 113 | // Data Buffer Read Port |
| 114 | output [(`FIRE_DLC_CRD_ADDR_WDTH - 1):0] cl2di_addr; |
| 115 | |
| 116 | // -------------------------------------------------------- |
| 117 | // DOU Buffer Manager Control Port |
| 118 | // -------------------------------------------------------- |
| 119 | |
| 120 | output [(DOU_DADDR_WDTH - 1):0] dma_dptr; |
| 121 | output dou_space_avail; |
| 122 | input dma_dptr_req; |
| 123 | input [3:0] dma_cltot; |
| 124 | |
| 125 | // -------------------------------------------------------- |
| 126 | // DIU Buffer Manager Control Port |
| 127 | // -------------------------------------------------------- |
| 128 | |
| 129 | // buffer space status |
| 130 | output diu_dma_empty; |
| 131 | output diu_pio_empty; |
| 132 | |
| 133 | // buffer space select |
| 134 | input [1:0] diu_typ_sel; |
| 135 | |
| 136 | // buffer space addr ctl |
| 137 | input inc_dma_blk_addr; |
| 138 | input inc_pio_blk_addr; |
| 139 | input inc_eqw_blk_addr; |
| 140 | input inc_mdo_blk_addr; |
| 141 | |
| 142 | // diu read addr ctl |
| 143 | input ld_diu_addr; |
| 144 | input inc_diu_row_ptr; |
| 145 | |
| 146 | // -------------------------------------------------------- |
| 147 | // IDLE Checker Port |
| 148 | // -------------------------------------------------------- |
| 149 | |
| 150 | output dou_dptr_pool_full; |
| 151 | |
| 152 | // >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<< |
| 153 | |
| 154 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTERS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 155 | |
| 156 | // ********** Flops ********** |
| 157 | |
| 158 | reg [4:0] dma_blk_addr; |
| 159 | reg [3:0] pio_blk_addr; |
| 160 | reg [3:0] eqw_blk_addr; |
| 161 | reg [1:0] mdo_blk_addr; |
| 162 | reg [6:0] diu_addr_8to2; |
| 163 | reg [1:0] diu_addr_1to0; |
| 164 | reg dma_wrp_flag; |
| 165 | reg pio_wrp_flag; |
| 166 | reg eqw_wrp_flag; |
| 167 | reg [(DOU_DADDR_WDTH - 1):0] dma_dptr; |
| 168 | reg [(DOU_DADDR_NUM - 1):0] dou_sts_vctr; |
| 169 | |
| 170 | // ********** Non-Flops ****** |
| 171 | |
| 172 | reg [6:0] nxt_diu_addr_8to2; |
| 173 | reg [(DOU_DADDR_NUM - 1):0] dcd_vec0; |
| 174 | reg [(DOU_DADDR_NUM - 1):0] dptr_ret_dcd; |
| 175 | reg [(DOU_DADDR_NUM - 1):0] dcd_vec1; |
| 176 | reg [(DOU_DADDR_NUM - 1):0] dptr_consume_dcd; |
| 177 | |
| 178 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ NETS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 179 | |
| 180 | wire wrp_eqw_blk_addr; |
| 181 | wire [(DOU_DADDR_NUM - 1):0] nxt_dou_sts_vctr; |
| 182 | wire [8:0] dou_sts_scan; |
| 183 | wire [8:0] dou_sts_chk; |
| 184 | wire [30:0] tmp_a; |
| 185 | wire [7:0] tmp_b; |
| 186 | |
| 187 | // >>>>>>>>>>>>>>>>>>>>>>>>> 0-in Checkers <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 188 | |
| 189 | /* 0in oid |
| 190 | -req dma_dptr_req |
| 191 | -req_id dma_dptr |
| 192 | -ret rm2cl_bufrel_enq |
| 193 | -ret_id rm2cl_bufrel |
| 194 | -max_ids 32 |
| 195 | -max_count_per_id 1 |
| 196 | */ |
| 197 | |
| 198 | // 0in max -var eqw_blk_addr -val 4'hB |
| 199 | |
| 200 | // 0in kndr -var {tm2cl_dma_wptr, tm2cl_pio_wptr} |
| 201 | |
| 202 | // 0in decode -in rm2cl_bufrel -out dcd_vec0 |
| 203 | |
| 204 | // 0in decode -in dma_dptr -out dcd_vec1 |
| 205 | |
| 206 | // >>>>>>>>>>>>>>>>>>>>>>>>> RTL Model <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 207 | |
| 208 | // -------------------------------------------------------- |
| 209 | // IDLE Checker |
| 210 | // -------------------------------------------------------- |
| 211 | |
| 212 | assign dou_dptr_pool_full = &dou_sts_vctr; |
| 213 | |
| 214 | // -------------------------------------------------------- |
| 215 | // DIU Buffer Manager |
| 216 | // -------------------------------------------------------- |
| 217 | |
| 218 | // ----- dma buffer management ---------------------------------------------- |
| 219 | |
| 220 | // diu blk addr gen |
| 221 | always @(posedge clk) |
| 222 | if (~rst_l) |
| 223 | {dma_wrp_flag, dma_blk_addr} <= 6'b0; |
| 224 | else if (inc_dma_blk_addr) |
| 225 | {dma_wrp_flag, dma_blk_addr} <= {dma_wrp_flag, dma_blk_addr} + 1'b1; |
| 226 | |
| 227 | // diu empty indicator |
| 228 | assign diu_dma_empty = ({dma_wrp_flag, dma_blk_addr} == tm2cl_dma_wptr); |
| 229 | |
| 230 | // clu-tmu diu buff management |
| 231 | assign cl2tm_dma_rptr = {dma_wrp_flag, dma_blk_addr}; |
| 232 | |
| 233 | // ----- pio buffer management ---------------------------------------------- |
| 234 | |
| 235 | // diu blk addr gen |
| 236 | always @(posedge clk) |
| 237 | if (~rst_l) |
| 238 | {pio_wrp_flag, pio_blk_addr} <= 5'b0; |
| 239 | else if (inc_pio_blk_addr) |
| 240 | {pio_wrp_flag, pio_blk_addr} <= {pio_wrp_flag, pio_blk_addr} + 1'b1; |
| 241 | |
| 242 | // diu empty indicator |
| 243 | assign diu_pio_empty = ({pio_wrp_flag, pio_blk_addr} == tm2cl_pio_wptr); |
| 244 | |
| 245 | // ----- eqw buffer management ---------------------------------------------- |
| 246 | |
| 247 | // diu eqw addr wrap ctl : eqw consumes diu int addr 0x0-0xB |
| 248 | assign wrp_eqw_blk_addr = (eqw_blk_addr == 4'hB); |
| 249 | |
| 250 | // diu blk addr gen |
| 251 | always @(posedge clk) |
| 252 | if (~rst_l) |
| 253 | begin |
| 254 | eqw_wrp_flag <= 1'b0; |
| 255 | eqw_blk_addr <= 4'b0; |
| 256 | end |
| 257 | else if (inc_eqw_blk_addr) |
| 258 | begin |
| 259 | eqw_wrp_flag <= eqw_wrp_flag ^ wrp_eqw_blk_addr; |
| 260 | eqw_blk_addr <= (eqw_blk_addr + 1'b1) & {4{~wrp_eqw_blk_addr}}; |
| 261 | end |
| 262 | |
| 263 | // clu-tmu diu buff management |
| 264 | assign cl2tm_int_rptr = {eqw_wrp_flag, eqw_blk_addr}; |
| 265 | |
| 266 | // ----- mdo buffer management ---------------------------------------------- |
| 267 | |
| 268 | // mdo blk addr gen |
| 269 | always @(posedge clk) |
| 270 | if (~rst_l) |
| 271 | mdo_blk_addr <= 2'b0; |
| 272 | else if (inc_mdo_blk_addr) |
| 273 | mdo_blk_addr <= mdo_blk_addr + 1'b1; |
| 274 | |
| 275 | // ----- diu read addr generation ------------------------------------------- |
| 276 | |
| 277 | // diu blk addr select : dma, pio, int (eqw), int (mdo) |
| 278 | always @(dma_blk_addr or pio_blk_addr or eqw_blk_addr or mdo_blk_addr or |
| 279 | diu_typ_sel) |
| 280 | begin |
| 281 | case (diu_typ_sel) // synopsys infer_mux |
| 282 | |
| 283 | 2'b00 : // DIU-DMA |
| 284 | nxt_diu_addr_8to2 = {2'b00, dma_blk_addr}; |
| 285 | |
| 286 | 2'b01 : // DIU-PIO |
| 287 | //BP n2 6-23-04 |
| 288 | // nxt_diu_addr_8to2 = {2'b01, 1'b0, pio_blk_addr}; |
| 289 | nxt_diu_addr_8to2 = {2'b01, 1'b0, 2'b00, pio_blk_addr[3:2]}; |
| 290 | |
| 291 | 2'b10 : // DIU-INT (EQW) |
| 292 | nxt_diu_addr_8to2 = {2'b10, 1'b0, eqw_blk_addr}; |
| 293 | |
| 294 | 2'b11 : // DIU-INT (MDO) |
| 295 | nxt_diu_addr_8to2 = {2'b10, 1'b0, 2'b11, mdo_blk_addr}; |
| 296 | |
| 297 | endcase |
| 298 | end |
| 299 | |
| 300 | // diu blk addr reg |
| 301 | always @(posedge clk) |
| 302 | if (~rst_l) |
| 303 | diu_addr_8to2 <= 7'b0; |
| 304 | else if (ld_diu_addr) |
| 305 | diu_addr_8to2 <= nxt_diu_addr_8to2; |
| 306 | |
| 307 | // diu row addr reg |
| 308 | always @(posedge clk) |
| 309 | if (~rst_l) |
| 310 | diu_addr_1to0 <= 2'b0; |
| 311 | //BP n2 6-23-04 |
| 312 | else if ( ld_diu_addr & (diu_typ_sel == 2'b01)) |
| 313 | diu_addr_1to0 <= pio_blk_addr[1:0] ; |
| 314 | else if (inc_diu_row_ptr | ld_diu_addr) |
| 315 | diu_addr_1to0 <= (diu_addr_1to0 + 1'b1) & {2{~ld_diu_addr}}; |
| 316 | |
| 317 | // diu read addr output |
| 318 | assign cl2di_addr = {diu_addr_8to2, diu_addr_1to0}; |
| 319 | |
| 320 | // -------------------------------------------------------- |
| 321 | // DOU Buffer Manager |
| 322 | // -------------------------------------------------------- |
| 323 | |
| 324 | // ----- dou dma dptr management -------------------------------------------- |
| 325 | |
| 326 | // dou dma dptr generator |
| 327 | always @(posedge clk) |
| 328 | if (~rst_l) |
| 329 | dma_dptr <= {DOU_DADDR_WDTH{1'b0}}; |
| 330 | else if (dma_dptr_req) |
| 331 | dma_dptr <= dma_dptr + 1'b1; |
| 332 | |
| 333 | // decoder : dou dma dptr retire |
| 334 | always @(rm2cl_bufrel or rm2cl_bufrel_enq) |
| 335 | begin |
| 336 | dcd_vec0 = {DOU_DADDR_NUM{1'b0}}; |
| 337 | dcd_vec0[rm2cl_bufrel] = 1'b1; |
| 338 | dptr_ret_dcd = dcd_vec0 & {DOU_DADDR_NUM{rm2cl_bufrel_enq}}; |
| 339 | end |
| 340 | |
| 341 | // decoder : dou dma dptr consume |
| 342 | always @(dma_dptr or dma_dptr_req) |
| 343 | begin |
| 344 | dcd_vec1 = {DOU_DADDR_NUM{1'b0}}; |
| 345 | dcd_vec1[dma_dptr] = 1'b1; |
| 346 | dptr_consume_dcd = dcd_vec1 & {DOU_DADDR_NUM{dma_dptr_req}}; |
| 347 | end |
| 348 | |
| 349 | // generate "next dou status" vector |
| 350 | assign nxt_dou_sts_vctr = ((dptr_ret_dcd | dou_sts_vctr) & |
| 351 | ~dptr_consume_dcd); |
| 352 | |
| 353 | // dou status vector: 1 = avail, 0 = used |
| 354 | always @(posedge clk) |
| 355 | if (~rst_l) |
| 356 | dou_sts_vctr <= {DOU_DADDR_NUM{1'b1}}; |
| 357 | else |
| 358 | dou_sts_vctr <= nxt_dou_sts_vctr; |
| 359 | |
| 360 | // ----- dou status check --------------------------------------------------- |
| 361 | |
| 362 | // scan dou status vector |
| 363 | assign {tmp_a, dou_sts_scan} = {dou_sts_vctr[7:0], dou_sts_vctr} >> dma_dptr; |
| 364 | |
| 365 | // dou status check |
| 366 | assign {dou_sts_chk, tmp_b} = {dou_sts_scan, 8'hFF} << (4'h9 - dma_cltot); |
| 367 | |
| 368 | // dou space avail |
| 369 | assign dou_space_avail = &dou_sts_chk; |
| 370 | |
| 371 | endmodule // dmu_clu_ctm_bufmgr |