| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_clu_ctm_cmdgen.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
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| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_clu_ctm_cmdgen |
| 36 | ( |
| 37 | // clock/reset |
| 38 | clk, |
| 39 | rst_l, |
| 40 | |
| 41 | // jbc : cmd port |
| 42 | d2j_cmd, |
| 43 | d2j_addr, |
| 44 | d2j_ctag, |
| 45 | |
| 46 | // crm : urr port |
| 47 | ctm2crm_rcd, |
| 48 | crm2ctm_rcd_deq, |
| 49 | proc_uns, |
| 50 | |
| 51 | // pmu : icr port |
| 52 | icr_typ, |
| 53 | icr_clsts, |
| 54 | icr_addr, |
| 55 | icr_cmdsts, |
| 56 | icr_sbdtag, |
| 57 | |
| 58 | // mmu : tcr port |
| 59 | tcr_addr, |
| 60 | tcr_mtag, |
| 61 | |
| 62 | // tagmgr port |
| 63 | nxt_tag, |
| 64 | |
| 65 | // bufmgr port |
| 66 | dma_dptr, |
| 67 | |
| 68 | // cmd sel port |
| 69 | cmd_req_sel, |
| 70 | |
| 71 | // uns req fifo credit port |
| 72 | uns_req_crdt_avail, |
| 73 | |
| 74 | // icr cmd decode port |
| 75 | mrd_vld, |
| 76 | mwr_vld, |
| 77 | mwr_err, |
| 78 | eqwr_vld, |
| 79 | eqwr_err, |
| 80 | mdo_vld, |
| 81 | uns_vld, |
| 82 | null_vld, |
| 83 | pio16_vld, |
| 84 | pio64_vld, |
| 85 | pio_err |
| 86 | ); |
| 87 | |
| 88 | // >>>>>>>>>>>>>>>>>>>>>>>>> Parameter Declarations <<<<<<<<<<<<<<<<<<<<<<<<< |
| 89 | |
| 90 | // -------------------------------------------------------- |
| 91 | // TAGMGR Configuration |
| 92 | // -------------------------------------------------------- |
| 93 | |
| 94 | parameter TAG_WDTH = 4; |
| 95 | |
| 96 | // -------------------------------------------------------- |
| 97 | // Ingress Command Record (ICR) Type Encoding |
| 98 | // -------------------------------------------------------- |
| 99 | |
| 100 | parameter DMA_MRD_32BIT = 7'b00_00000, |
| 101 | DMA_MRD_64BIT = 7'b01_00000, |
| 102 | DMA_MRDLK_32BIT = 7'b00_00001, |
| 103 | DMA_MRDLK_64BIT = 7'b01_00001, |
| 104 | UNS_REQ = 7'b00_01001, |
| 105 | DMA_MWR_32BIT = 7'b10_00000, |
| 106 | DMA_MWR_64BIT = 7'b11_00000, |
| 107 | MSI_EQ_WR_32BIT = 7'b10_11000, |
| 108 | MSI_EQ_WR_64BIT = 7'b11_11000, |
| 109 | MSG_EQ_WR_32BIT = 7'b10_10000, |
| 110 | MSG_EQ_WR_64BIT = 7'b11_10000, |
| 111 | NULL = 7'b11_11100, |
| 112 | MONDO_REQ = 7'b11_11010, |
| 113 | PIO_CPL = 7'b00_01010, |
| 114 | PIO_CPLD = 7'b10_01010; |
| 115 | |
| 116 | // -------------------------------------------------------- |
| 117 | // CTM-to-CRM Unsupported Request Command Encoding |
| 118 | // -------------------------------------------------------- |
| 119 | |
| 120 | parameter DMA_MRD_ERR = 3'b001, |
| 121 | DMA_MRD_LK = 3'b010, |
| 122 | UNSUPPORTED = 3'b100; |
| 123 | |
| 124 | // -------------------------------------------------------- |
| 125 | // DMC-to-JBC Command Encoding |
| 126 | // -------------------------------------------------------- |
| 127 | |
| 128 | parameter DMA_WRF = 4'b0000, |
| 129 | DMA_WRP = 4'b0001, |
| 130 | DMA_RD = 4'b0010, |
| 131 | DMA_RDS = 4'b0011, |
| 132 | INT = 4'b0100, |
| 133 | PIO_RD16 = 4'b1000, |
| 134 | PIO_RD64 = 4'b1001, |
| 135 | PIO_RDERR_TO = 4'b1010, |
| 136 | PIO_RDERR_BUS = 4'b1011; |
| 137 | |
| 138 | // -------------------------------------------------------- |
| 139 | // ICR Completion Status Encoding |
| 140 | // -------------------------------------------------------- |
| 141 | |
| 142 | parameter UR_CPLSTS = 3'b001, |
| 143 | TO_CPLSTS = 3'b111; |
| 144 | |
| 145 | // -------------------------------------------------------- |
| 146 | // UNSUPPORTED FIFO CREDIT PARAMETERS |
| 147 | // -------------------------------------------------------- |
| 148 | |
| 149 | parameter UNS_CRDTCNT = 3'h6; |
| 150 | parameter UNS_CRDTCNT_WDTH = 3; |
| 151 | |
| 152 | // >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 153 | |
| 154 | // -------------------------------------------------------- |
| 155 | // Clock/Reset |
| 156 | // -------------------------------------------------------- |
| 157 | |
| 158 | input clk; |
| 159 | input rst_l; |
| 160 | |
| 161 | // -------------------------------------------------------- |
| 162 | // JBC Interface |
| 163 | // -------------------------------------------------------- |
| 164 | |
| 165 | // Cmd Port -> DMC Req/Resp |
| 166 | output [(`FIRE_D2J_CMD_WDTH - 1):0] d2j_cmd; |
| 167 | output [(`FIRE_D2J_ADDR_WDTH - 1):0] d2j_addr; |
| 168 | output [(`FIRE_D2J_CTAG_WDTH - 1):0] d2j_ctag; |
| 169 | |
| 170 | // -------------------------------------------------------- |
| 171 | // CRM Interface |
| 172 | // -------------------------------------------------------- |
| 173 | |
| 174 | // Unsupported Request Record (URR) Port |
| 175 | output [(`FIRE_DLC_CLU_URR_WDTH - 1):0] ctm2crm_rcd; |
| 176 | input crm2ctm_rcd_deq; |
| 177 | input proc_uns; |
| 178 | |
| 179 | // -------------------------------------------------------- |
| 180 | // ICR Fields |
| 181 | // -------------------------------------------------------- |
| 182 | |
| 183 | input [(`FIRE_DLC_ICR_TYP_WDTH - 1):0] icr_typ; |
| 184 | input [(`FIRE_DLC_ICR_CLSTS_WDTH - 1):0] icr_clsts; |
| 185 | input [(`FIRE_DLC_ICR_ADDR_WDTH - 1):0] icr_addr; |
| 186 | input [(`FIRE_DLC_ICR_STAT_WDTH - 1):0] icr_cmdsts; |
| 187 | input [(`FIRE_DLC_ICR_SBDTAG_WDTH - 1):0] icr_sbdtag; |
| 188 | |
| 189 | // -------------------------------------------------------- |
| 190 | // TCR Fields |
| 191 | // -------------------------------------------------------- |
| 192 | |
| 193 | input [(`FIRE_DLC_TCR_ADDR_WDTH - 1):0] tcr_addr; |
| 194 | input [(`FIRE_DLC_TCR_MTAG_WDTH - 1):0] tcr_mtag; |
| 195 | |
| 196 | // -------------------------------------------------------- |
| 197 | // Tag Manager - Next Available Tag |
| 198 | // -------------------------------------------------------- |
| 199 | |
| 200 | input [(TAG_WDTH - 1):0] nxt_tag; |
| 201 | |
| 202 | // -------------------------------------------------------- |
| 203 | // Buffer Manager - Next Available DOU DMA Address |
| 204 | // -------------------------------------------------------- |
| 205 | |
| 206 | input [4:0] dma_dptr; |
| 207 | |
| 208 | // -------------------------------------------------------- |
| 209 | // Command Process Select |
| 210 | // -------------------------------------------------------- |
| 211 | |
| 212 | input cmd_req_sel; |
| 213 | |
| 214 | // -------------------------------------------------------- |
| 215 | // UNS Req Fifo-Credit Interface |
| 216 | // -------------------------------------------------------- |
| 217 | |
| 218 | output uns_req_crdt_avail; |
| 219 | |
| 220 | // -------------------------------------------------------- |
| 221 | // ICR Decoded Type Control Signals |
| 222 | // -------------------------------------------------------- |
| 223 | |
| 224 | output mrd_vld; |
| 225 | output mwr_vld; |
| 226 | output mwr_err; |
| 227 | output eqwr_vld; |
| 228 | output eqwr_err; |
| 229 | output mdo_vld; |
| 230 | output uns_vld; |
| 231 | output null_vld; |
| 232 | output pio16_vld; |
| 233 | output pio64_vld; |
| 234 | output pio_err; |
| 235 | |
| 236 | // >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<< |
| 237 | |
| 238 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTERS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 239 | |
| 240 | // ********** Flops ********** |
| 241 | |
| 242 | // Cmd Port -> DMC Req/Resp |
| 243 | reg [(`FIRE_D2J_CMD_WDTH - 1):0] d2j_cmd; |
| 244 | reg [(`FIRE_D2J_ADDR_WDTH - 1):0] d2j_addr; |
| 245 | reg [(`FIRE_D2J_CTAG_WDTH - 1):0] d2j_ctag; |
| 246 | |
| 247 | // Unsupported Request Record (URR) Port |
| 248 | reg [(`FIRE_DLC_CLU_URR_WDTH - 1):0] ctm2crm_rcd; |
| 249 | |
| 250 | // unsupported request fifo credit count |
| 251 | reg [(UNS_CRDTCNT_WDTH - 1):0] q_count_uns; |
| 252 | |
| 253 | // ********** Non-Flops ****** |
| 254 | |
| 255 | // command types |
| 256 | reg [(`FIRE_D2J_CMD_WDTH - 1):0] icr_jbc_cmd; |
| 257 | reg [(`FIRE_DLC_CLU_URR_TYP_WDTH - 1):0] uns_cmd; |
| 258 | |
| 259 | // type control signals |
| 260 | reg mrd_vld; |
| 261 | reg mwr_vld; |
| 262 | reg mwr_err; |
| 263 | reg eqwr_vld; |
| 264 | reg eqwr_err; |
| 265 | reg mdo_vld; |
| 266 | reg uns_vld; |
| 267 | reg null_vld; |
| 268 | reg pio16_vld; |
| 269 | reg pio64_vld; |
| 270 | reg pio_err; |
| 271 | |
| 272 | // jbc cmd structure |
| 273 | reg [(`FIRE_D2J_CMD_WDTH - 1):0] jbc_cmd; |
| 274 | reg [(`FIRE_D2J_ADDR_WDTH - 1):0] jbc_addr; |
| 275 | reg [(`FIRE_D2J_CTAG_WDTH - 1):0] jbc_ctag; |
| 276 | |
| 277 | // next unsupported request fifo credit count |
| 278 | reg [(UNS_CRDTCNT_WDTH - 1):0] nxt_q_count_uns; |
| 279 | |
| 280 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ NETS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 281 | |
| 282 | // unsupported request fifo credit increment |
| 283 | wire q_count_uns_ld; |
| 284 | |
| 285 | // >>>>>>>>>>>>>>>>>>>>>>>>> 0-in Checkers <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 286 | |
| 287 | /* 0in kndr |
| 288 | -var icr_clsts |
| 289 | -active (~`CPU.dmu.dmc.clu.ctm.icr_fifo_empty & |
| 290 | ((icr_typ == DMA_MRD_32BIT) | |
| 291 | (icr_typ == DMA_MRD_64BIT) | |
| 292 | (icr_typ == DMA_MWR_32BIT) | |
| 293 | (icr_typ == DMA_MWR_64BIT) | |
| 294 | (icr_typ == PIO_CPLD))) |
| 295 | */ |
| 296 | |
| 297 | /* 0in kndr |
| 298 | -var icr_addr |
| 299 | -active (~`CPU.dmu.dmc.clu.ctm.icr_fifo_empty & |
| 300 | (((icr_typ == DMA_MRD_32BIT) & ~icr_cmdsts[0]) | |
| 301 | ((icr_typ == DMA_MRD_64BIT) & ~icr_cmdsts[0]) | |
| 302 | ((icr_typ == DMA_MWR_32BIT) & ~icr_cmdsts[0]) | |
| 303 | ((icr_typ == DMA_MWR_64BIT) & ~icr_cmdsts[0]) | |
| 304 | ((icr_typ == MSI_EQ_WR_32BIT) & ~icr_cmdsts[0]) | |
| 305 | ((icr_typ == MSI_EQ_WR_64BIT) & ~icr_cmdsts[0]) | |
| 306 | ((icr_typ == MSG_EQ_WR_32BIT) & ~icr_cmdsts[0]) | |
| 307 | ((icr_typ == MSG_EQ_WR_64BIT) & ~icr_cmdsts[0]) | |
| 308 | (icr_typ == MONDO_REQ))) |
| 309 | */ |
| 310 | |
| 311 | /* 0in kndr |
| 312 | -var icr_addr[5:0] |
| 313 | -active (~`CPU.dmu.dmc.clu.ctm.icr_fifo_empty & |
| 314 | ((icr_typ == PIO_CPL) | |
| 315 | (icr_typ == PIO_CPLD))) |
| 316 | */ |
| 317 | |
| 318 | /* 0in kndr |
| 319 | -var icr_cmdsts[0] |
| 320 | -active (~`CPU.dmu.dmc.clu.ctm.icr_fifo_empty & |
| 321 | ((icr_typ == DMA_MRD_32BIT) | |
| 322 | (icr_typ == DMA_MRD_64BIT) | |
| 323 | (icr_typ == DMA_MWR_32BIT) | |
| 324 | (icr_typ == DMA_MWR_64BIT) | |
| 325 | (icr_typ == MSI_EQ_WR_32BIT) | |
| 326 | (icr_typ == MSI_EQ_WR_64BIT) | |
| 327 | (icr_typ == MSG_EQ_WR_32BIT) | |
| 328 | (icr_typ == MSG_EQ_WR_64BIT))) |
| 329 | */ |
| 330 | |
| 331 | /* 0in kndr |
| 332 | -var icr_cmdsts |
| 333 | -active (~`CPU.dmu.dmc.clu.ctm.icr_fifo_empty & |
| 334 | (icr_typ == PIO_CPL)) |
| 335 | */ |
| 336 | |
| 337 | /* 0in kndr |
| 338 | -var icr_sbdtag |
| 339 | -active (~`CPU.dmu.dmc.clu.ctm.icr_fifo_empty & |
| 340 | ((icr_typ == DMA_MRD_32BIT) | |
| 341 | (icr_typ == DMA_MRD_64BIT) | |
| 342 | (icr_typ == DMA_MRDLK_32BIT) | |
| 343 | (icr_typ == DMA_MRDLK_64BIT) | |
| 344 | (icr_typ == UNS_REQ))) |
| 345 | */ |
| 346 | |
| 347 | /* 0in kndr |
| 348 | -var icr_sbdtag[1:0] |
| 349 | -active (~`CPU.dmu.dmc.clu.ctm.icr_fifo_empty & |
| 350 | (icr_typ == MONDO_REQ)) |
| 351 | */ |
| 352 | |
| 353 | /* 0in kndr |
| 354 | -var icr_sbdtag[3:0] |
| 355 | -active (~`CPU.dmu.dmc.clu.ctm.icr_fifo_empty & |
| 356 | ((icr_typ == PIO_CPL) | |
| 357 | (icr_typ == PIO_CPLD))) |
| 358 | */ |
| 359 | |
| 360 | // 0in max -var q_count_uns -val 6 |
| 361 | |
| 362 | // >>>>>>>>>>>>>>>>>>>>>>>>> RTL Model <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 363 | |
| 364 | // -------------------------------------------------------- |
| 365 | // ICR Command Process (Ingress Command Record) |
| 366 | // -------------------------------------------------------- |
| 367 | |
| 368 | // ----- type decode--------------------------------------------------------- |
| 369 | |
| 370 | always @(icr_typ or icr_clsts or icr_cmdsts) |
| 371 | begin |
| 372 | |
| 373 | // initialization |
| 374 | icr_jbc_cmd = {`FIRE_D2J_CMD_WDTH{1'b0}}; |
| 375 | uns_cmd = {`FIRE_DLC_CLU_URR_TYP_WDTH{1'b0}}; |
| 376 | mrd_vld = 1'b0; |
| 377 | mwr_vld = 1'b0; |
| 378 | mwr_err = 1'b0; |
| 379 | eqwr_vld = 1'b0; |
| 380 | eqwr_err = 1'b0; |
| 381 | mdo_vld = 1'b0; |
| 382 | uns_vld = 1'b0; |
| 383 | null_vld = 1'b0; |
| 384 | pio16_vld = 1'b0; |
| 385 | pio64_vld = 1'b0; |
| 386 | pio_err = 1'b0; |
| 387 | |
| 388 | // ======================================================= |
| 389 | // for dmawr/eqwr |
| 390 | // icr_cmdsts [0] : 1'b0 = no err, 1'b1 = err |
| 391 | // icr_clsts [0] : 1'b0 = full, 1'b1 = partial |
| 392 | // for dmard |
| 393 | // icr_cmdsts [0] : 1'b0 = no err, 1'b1 = err |
| 394 | // for piocpld |
| 395 | // icr_clsts [0] : 1'b0 = pio64, 1'b1 = pio16 |
| 396 | // ======================================================= |
| 397 | |
| 398 | // type decoder |
| 399 | case (icr_typ) |
| 400 | |
| 401 | /* 0in < case -parallel -full |
| 402 | -active ~`CPU.dmu.dmc.clu.ctm.icr_fifo_empty |
| 403 | -message "Illegal ICR type received by CLU" |
| 404 | */ |
| 405 | |
| 406 | DMA_MRD_32BIT, |
| 407 | DMA_MRD_64BIT : |
| 408 | if (icr_cmdsts[0]) |
| 409 | begin |
| 410 | uns_vld = 1'b1; |
| 411 | uns_cmd = DMA_MRD_ERR; |
| 412 | end |
| 413 | else |
| 414 | begin |
| 415 | mrd_vld = 1'b1; |
| 416 | icr_jbc_cmd = DMA_RD; |
| 417 | end |
| 418 | |
| 419 | DMA_MRDLK_32BIT, |
| 420 | DMA_MRDLK_64BIT : |
| 421 | begin |
| 422 | uns_vld = 1'b1; |
| 423 | uns_cmd = DMA_MRD_LK; |
| 424 | end |
| 425 | |
| 426 | UNS_REQ : |
| 427 | begin |
| 428 | uns_vld = 1'b1; |
| 429 | uns_cmd = UNSUPPORTED; |
| 430 | end |
| 431 | |
| 432 | DMA_MWR_32BIT, |
| 433 | DMA_MWR_64BIT : |
| 434 | begin |
| 435 | mwr_vld = ~icr_cmdsts[0]; |
| 436 | mwr_err = icr_cmdsts[0]; |
| 437 | if (icr_clsts) |
| 438 | icr_jbc_cmd = DMA_WRP; |
| 439 | else |
| 440 | icr_jbc_cmd = DMA_WRF; |
| 441 | end |
| 442 | |
| 443 | MSI_EQ_WR_32BIT, |
| 444 | MSI_EQ_WR_64BIT, |
| 445 | MSG_EQ_WR_32BIT, |
| 446 | MSG_EQ_WR_64BIT : |
| 447 | begin |
| 448 | eqwr_vld = ~icr_cmdsts[0]; |
| 449 | eqwr_err = icr_cmdsts[0]; |
| 450 | icr_jbc_cmd = DMA_WRF; |
| 451 | end |
| 452 | |
| 453 | NULL : |
| 454 | begin |
| 455 | null_vld = 1'b1; |
| 456 | end |
| 457 | |
| 458 | MONDO_REQ : |
| 459 | begin |
| 460 | mdo_vld = 1'b1; |
| 461 | icr_jbc_cmd = INT; |
| 462 | end |
| 463 | |
| 464 | PIO_CPL : |
| 465 | begin |
| 466 | pio_err = 1'b1; |
| 467 | |
| 468 | case (icr_cmdsts) |
| 469 | |
| 470 | /* 0in < case -full |
| 471 | -active ~`CPU.dmu.dmc.clu.ctm.icr_fifo_empty |
| 472 | -message "Illegal PIO_CPL error encoding received by CLU" |
| 473 | */ |
| 474 | |
| 475 | UR_CPLSTS : icr_jbc_cmd = PIO_RDERR_BUS; |
| 476 | TO_CPLSTS : icr_jbc_cmd = PIO_RDERR_TO; |
| 477 | endcase |
| 478 | end |
| 479 | |
| 480 | PIO_CPLD : |
| 481 | begin |
| 482 | if (icr_clsts) |
| 483 | begin |
| 484 | pio16_vld = 1'b1; |
| 485 | icr_jbc_cmd = PIO_RD16; |
| 486 | end |
| 487 | else |
| 488 | begin |
| 489 | pio64_vld = 1'b1; |
| 490 | icr_jbc_cmd = PIO_RD64; |
| 491 | end |
| 492 | end |
| 493 | |
| 494 | endcase |
| 495 | end |
| 496 | |
| 497 | // -------------------------------------------------------- |
| 498 | // JBC Command/Address Construction |
| 499 | // -------------------------------------------------------- |
| 500 | |
| 501 | // ----- cmd_typ assignment (ICR/TCR) --------------------------------------- |
| 502 | |
| 503 | always @(icr_jbc_cmd or cmd_req_sel) |
| 504 | if (cmd_req_sel) // 1'b0 = icr, 1'b1 = tcr |
| 505 | jbc_cmd = DMA_RDS; |
| 506 | else |
| 507 | jbc_cmd = icr_jbc_cmd; |
| 508 | |
| 509 | // ----- addr assignment (ICR/TCR) ------------------------------------------ |
| 510 | |
| 511 | always @(icr_addr or tcr_addr or cmd_req_sel) |
| 512 | if (cmd_req_sel) // 1'b0 = icr, 1'b1 = tcr |
| 513 | jbc_addr = tcr_addr; |
| 514 | else |
| 515 | //BP n2 1-01-04 |
| 516 | // jbc_addr = icr_addr; |
| 517 | jbc_addr = {icr_addr[(`FIRE_DLC_ICR_ADDR_WDTH -1):7],icr_addr[5:0]}; |
| 518 | |
| 519 | // ----- ctag assignment (ICR/TCR) ------------------------------------------ |
| 520 | |
| 521 | always @(dma_dptr or tcr_mtag or cmd_req_sel or |
| 522 | nxt_tag or icr_sbdtag or icr_clsts or icr_addr or |
| 523 | pio16_vld or pio64_vld or pio_err) |
| 524 | begin |
| 525 | |
| 526 | jbc_ctag[15] = cmd_req_sel; |
| 527 | //BP n2 5-25-04 |
| 528 | // jbc_ctag[14:11] = nxt_tag; |
| 529 | // jbc_ctag[10] = dma_dptr[4]; |
| 530 | // |
| 531 | // if (~cmd_req_sel & (pio16_vld | pio64_vld | pio_err)) |
| 532 | // jbc_ctag[9:6] = icr_sbdtag[3:0]; |
| 533 | // else |
| 534 | // jbc_ctag[9:6] = dma_dptr[3:0]; |
| 535 | |
| 536 | jbc_ctag[14:12] = nxt_tag[3:1]; |
| 537 | |
| 538 | if (~cmd_req_sel & (pio16_vld | pio64_vld | pio_err)) |
| 539 | jbc_ctag[11:8] = icr_sbdtag[3:0]; |
| 540 | else |
| 541 | jbc_ctag[11:8] = {nxt_tag[0],dma_dptr[4:2]}; |
| 542 | |
| 543 | if (~cmd_req_sel & (pio16_vld | pio64_vld | pio_err)) |
| 544 | jbc_ctag[7:6] = {1'b0,icr_addr[6]}; |
| 545 | else |
| 546 | jbc_ctag[7:6] = dma_dptr[1:0]; |
| 547 | // BP end 5-25-04 change |
| 548 | |
| 549 | if (cmd_req_sel) |
| 550 | jbc_ctag[5:0] = tcr_mtag; |
| 551 | else |
| 552 | if (pio16_vld | pio64_vld | pio_err) |
| 553 | jbc_ctag[5:0] = icr_addr[5:0]; |
| 554 | else |
| 555 | jbc_ctag[5:0] = {icr_sbdtag, icr_clsts}; |
| 556 | |
| 557 | end |
| 558 | |
| 559 | // -------------------------------------------------------- |
| 560 | // CTM-CRM Unsupported Request Fifo-Credit Manager |
| 561 | // -------------------------------------------------------- |
| 562 | |
| 563 | // generate q_count_uns load signal |
| 564 | assign q_count_uns_ld = crm2ctm_rcd_deq ^ proc_uns; |
| 565 | |
| 566 | // credit availability flag |
| 567 | assign uns_req_crdt_avail = |q_count_uns; |
| 568 | |
| 569 | // next q_count |
| 570 | always @(proc_uns or q_count_uns) |
| 571 | if (proc_uns) |
| 572 | nxt_q_count_uns = q_count_uns - 1'b1; |
| 573 | else |
| 574 | nxt_q_count_uns = q_count_uns + 1'b1; |
| 575 | |
| 576 | // current q_count |
| 577 | always @(posedge clk) |
| 578 | if (~rst_l) |
| 579 | q_count_uns <= UNS_CRDTCNT; |
| 580 | else if (q_count_uns_ld) |
| 581 | q_count_uns <= nxt_q_count_uns; |
| 582 | |
| 583 | // -------------------------------------------------------- |
| 584 | // Sequential Logic : DMC-JBC Interface |
| 585 | // -------------------------------------------------------- |
| 586 | |
| 587 | always @(posedge clk) |
| 588 | if (~rst_l) begin |
| 589 | d2j_cmd <= `FIRE_D2J_CMD_WDTH'b0; |
| 590 | d2j_addr <= `FIRE_D2J_ADDR_WDTH'b0; |
| 591 | d2j_ctag <= `FIRE_D2J_CTAG_WDTH'b0; |
| 592 | end |
| 593 | else begin |
| 594 | d2j_cmd <= jbc_cmd; |
| 595 | d2j_addr <= jbc_addr; |
| 596 | d2j_ctag <= jbc_ctag; |
| 597 | end |
| 598 | |
| 599 | // -------------------------------------------------------- |
| 600 | // Sequential Logic : CTM-CRM Interface |
| 601 | // -------------------------------------------------------- |
| 602 | |
| 603 | always @(posedge clk) |
| 604 | if (~rst_l) begin |
| 605 | ctm2crm_rcd[`FIRE_DLC_CLU_URR_TYP] <= `FIRE_DLC_CLU_URR_TYP_WDTH'b0; |
| 606 | ctm2crm_rcd[`FIRE_DLC_CLU_URR_SBDTAG] <= `FIRE_DLC_ICR_SBDTAG_WDTH'b0; |
| 607 | end |
| 608 | else begin |
| 609 | ctm2crm_rcd[`FIRE_DLC_CLU_URR_TYP] <= uns_cmd; |
| 610 | ctm2crm_rcd[`FIRE_DLC_CLU_URR_SBDTAG] <= icr_sbdtag; |
| 611 | end |
| 612 | |
| 613 | endmodule // dmu_clu_ctm_cmdgen |