| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_cmu.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_cmu ( |
| 36 | clk, |
| 37 | rst_l, |
| 38 | |
| 39 | // Debug Ports |
| 40 | cr2cm_dbg_sel_a, // CMU debug select a |
| 41 | cm2cr_dbg_a, // CMU debug output a |
| 42 | cr2cm_dbg_sel_b, // CMU debug select b |
| 43 | cm2cr_dbg_b, // CMU debug output b |
| 44 | |
| 45 | // RCM |
| 46 | mm2cm_rcd_enq, |
| 47 | mm2cm_rcd, |
| 48 | cm2mm_rcd_full, |
| 49 | cm2pm_rcd_enq, |
| 50 | cm2pm_rcd, |
| 51 | pm2cm_rcd_full, |
| 52 | |
| 53 | // TCM |
| 54 | cl2cm_rcd_enq, |
| 55 | cl2cm_rcd, |
| 56 | cm2cl_rcd_full, |
| 57 | cm2rm_rcd_enq, |
| 58 | cm2rm_rcd, |
| 59 | rm2cm_rcd_full, |
| 60 | |
| 61 | // ILU |
| 62 | y2k_mps |
| 63 | ); |
| 64 | |
| 65 | //************************************************ |
| 66 | // PARAMETERS |
| 67 | //************************************************ |
| 68 | |
| 69 | // parameter MM2CM_WDTH = `FIRE_DLC_ISR_REC_WDTH, //79 |
| 70 | // CM2PM_WDTH = `FIRE_DLC_IPR_REC_WDTH, //93 |
| 71 | // CL2CM_WDTH = `FIRE_DLC_EPR_REC_WDTH, //80 |
| 72 | // CM2RM_WDTH = `FIRE_DLC_ERR_REC_WDTH; //70 |
| 73 | |
| 74 | parameter SRMSB = `FIRE_DLC_ISR_MSB, // MM2CM_SRWDTH -1 |
| 75 | IPRMSB = `FIRE_DLC_IPR_MSB, // CM2PM_PRWDTH -1 |
| 76 | EPRMSB = `FIRE_DLC_EPR_MSB, // CL2CM_PRWDTH -1 |
| 77 | RRMSB = `FIRE_DLC_ERR_MSB; // CM2RM_RRWDTH -1 |
| 78 | |
| 79 | // ILU |
| 80 | parameter MPS_WDTH = `FIRE_DLC_MPS; |
| 81 | parameter MPSMSB = MPS_WDTH - 1; |
| 82 | |
| 83 | // CTX |
| 84 | // parameter CTXARRAY_WDTH = 43, // Context CTX entry width |
| 85 | parameter CTXARRAY_WDTH = 44, // Context CTX entry width |
| 86 | CTXARRAYMSB = CTXARRAY_WDTH -1, |
| 87 | CTXADDRLSB = 0, |
| 88 | CTXADDR_WDTH = 5, |
| 89 | CTXADDRMSB = CTXADDRLSB + CTXADDR_WDTH -1; |
| 90 | |
| 91 | // PKSEQ |
| 92 | parameter PSEQARRAY_WDTH = 5, // Context PKSEQ entry width |
| 93 | PSEQARRAYMSB = PSEQARRAY_WDTH -1, |
| 94 | PSEQADDRLSB = 0, |
| 95 | PSEQADDR_WDTH = 5, |
| 96 | PSEQADDRMSB = PSEQADDRLSB + PSEQADDR_WDTH -1; |
| 97 | |
| 98 | // CLST |
| 99 | parameter CLSTARRAY_WDTH = 54, // Context CLST entry width |
| 100 | CLSTARRAYMSB = CLSTARRAY_WDTH -1, |
| 101 | CLSTADDRLSB = 0, |
| 102 | CLSTADDR_WDTH = 4, |
| 103 | CLSTADDRMSB = CLSTADDRLSB + CLSTADDR_WDTH -1; |
| 104 | |
| 105 | parameter RETADDRARRAY_WDTH = 17, |
| 106 | RETADDRMSB = RETADDRARRAY_WDTH -1; |
| 107 | |
| 108 | //************************************************ |
| 109 | // PORTS |
| 110 | //************************************************ |
| 111 | |
| 112 | input clk; // The input clock |
| 113 | input rst_l; // The fifo rst_l |
| 114 | |
| 115 | // RCM |
| 116 | input mm2cm_rcd_enq; |
| 117 | input [SRMSB : 0] mm2cm_rcd; |
| 118 | output cm2mm_rcd_full; |
| 119 | |
| 120 | output cm2pm_rcd_enq; |
| 121 | output [IPRMSB : 0] cm2pm_rcd; |
| 122 | input pm2cm_rcd_full; |
| 123 | |
| 124 | // TCM |
| 125 | input cl2cm_rcd_enq; |
| 126 | input [EPRMSB : 0] cl2cm_rcd; |
| 127 | output cm2cl_rcd_full; |
| 128 | |
| 129 | output cm2rm_rcd_enq; |
| 130 | output [RRMSB : 0] cm2rm_rcd; |
| 131 | input rm2cm_rcd_full; |
| 132 | |
| 133 | //ILU |
| 134 | input [MPSMSB :0] y2k_mps; |
| 135 | |
| 136 | // Debug Ports |
| 137 | input [`FIRE_DLC_CMU_DS_BITS] cr2cm_dbg_sel_a; // CMU debug select a |
| 138 | input [`FIRE_DLC_CMU_DS_BITS] cr2cm_dbg_sel_b; // CMU debug select b |
| 139 | |
| 140 | output [`FIRE_DBG_DATA_BITS] cm2cr_dbg_a; // CMU debug output a |
| 141 | output [`FIRE_DBG_DATA_BITS] cm2cr_dbg_b; // CMU debug output b |
| 142 | |
| 143 | //************************************************ |
| 144 | // SIGNALS |
| 145 | //************************************************ |
| 146 | |
| 147 | wire clk; |
| 148 | wire rst_l; |
| 149 | |
| 150 | wire [MPSMSB :0] y2k_mps; |
| 151 | |
| 152 | // RCM |
| 153 | wire mm2cm_rcd_enq; |
| 154 | wire [SRMSB : 0]mm2cm_rcd; |
| 155 | wire cm2mm_rcd_full; |
| 156 | wire cm2pm_rcd_enq; |
| 157 | wire [IPRMSB : 0]cm2pm_rcd; |
| 158 | wire pm2cm_rcd_full; |
| 159 | |
| 160 | // TCM |
| 161 | wire cl2cm_rcd_enq; |
| 162 | wire [EPRMSB : 0]cl2cm_rcd; |
| 163 | wire cm2cl_rcd_full; |
| 164 | wire cm2rm_rcd_enq; |
| 165 | wire [RRMSB : 0]cm2rm_rcd; |
| 166 | wire rm2cm_rcd_full; |
| 167 | |
| 168 | //RCM - CTX |
| 169 | wire rcm2ctx_ctx_req; |
| 170 | wire ctx2rcm_ctx_gnt; |
| 171 | wire [CTXADDRMSB :0] ctx2rcm_nxctx_addr; |
| 172 | wire [CTXADDRMSB :0] rcm2ctx_ctx_addr; |
| 173 | wire rcm2ctx_ctx_rw; |
| 174 | wire [CTXARRAYMSB : 0] ctx2rcm_cur_ctx; |
| 175 | wire [CTXARRAYMSB : 0] rcm2ctx_ctx; |
| 176 | wire rcm2ctx_seq_req; |
| 177 | wire ctx2rcm_seq_gnt; |
| 178 | wire [PSEQADDRMSB :0] ctx2rcm_nxseq_addr; |
| 179 | wire [PSEQADDRMSB :0] rcm2ctx_pkseq_addr; |
| 180 | wire rcm2ctx_pkseq_rw; |
| 181 | wire [PSEQARRAYMSB : 0] rcm2ctx_pkseq; |
| 182 | |
| 183 | //TCM - CTX |
| 184 | wire [CTXADDRMSB :0] tcm2ctx_ctx_addr; |
| 185 | wire tcm2ctx_ctx_rw; |
| 186 | wire [CTXARRAYMSB : 0] ctx2tcm_cur_ctx; |
| 187 | wire [CTXARRAYMSB : 0] tcm2ctx_ctx; |
| 188 | wire [PSEQADDRMSB :0] tcm2ctx_pkseq_addr; |
| 189 | wire tcm2ctx_pkseq_rw; |
| 190 | wire [PSEQARRAYMSB : 0] ctx2tcm_cur_pkseq; |
| 191 | wire [PSEQARRAYMSB : 0] tcm2ctx_pkseq; |
| 192 | wire tcm2ctx_lst_req; |
| 193 | wire ctx2tcm_lst_gnt; |
| 194 | wire [CLSTADDRMSB :0] ctx2tcm_nxlst_addr; |
| 195 | wire [CLSTADDRMSB :0] tcm2ctx_ctxlst_addr; |
| 196 | wire tcm2ctx_clst_rw; |
| 197 | wire [CLSTARRAYMSB : 0] tcm2ctx_lst; |
| 198 | wire [CLSTARRAYMSB : 0] ctx2tcm_cur_lst; |
| 199 | wire tcm2ctx_ret_req; |
| 200 | wire [RETADDRMSB :0] tcm2ctx_ret_addr; |
| 201 | |
| 202 | // Debug |
| 203 | wire [`FIRE_DLC_CMU_DS_BITS] cr2cm_dbg_sel_a; // CMU debug select a |
| 204 | wire [`FIRE_DLC_CMU_DS_BITS] cr2cm_dbg_sel_b; // CMU debug select b |
| 205 | wire [`FIRE_DBG_DATA_BITS] cm2cr_dbg_a; // CMU debug output a |
| 206 | wire [`FIRE_DBG_DATA_BITS] cm2cr_dbg_b; // CMU debug output b |
| 207 | |
| 208 | // RCM debug |
| 209 | wire [`FIRE_DLC_CMU_RCM_DS_BITS] dbg2rcm_dbg_sel_a; |
| 210 | wire [`FIRE_DLC_CMU_RCM_DS_BITS] dbg2rcm_dbg_sel_b; |
| 211 | wire [`FIRE_DBG_DATA_BITS] rcm2dbg_dbg_a; |
| 212 | wire [`FIRE_DBG_DATA_BITS] rcm2dbg_dbg_b; |
| 213 | |
| 214 | // TCM debug |
| 215 | wire [`FIRE_DLC_CMU_TCM_DS_BITS] dbg2tcm_dbg_sel_a; |
| 216 | wire [`FIRE_DLC_CMU_TCM_DS_BITS] dbg2tcm_dbg_sel_b; |
| 217 | wire [`FIRE_DBG_DATA_BITS] tcm2dbg_dbg_a; |
| 218 | wire [`FIRE_DBG_DATA_BITS] tcm2dbg_dbg_b; |
| 219 | |
| 220 | // CTX debug |
| 221 | wire [`FIRE_DLC_CMU_CTX_DS_BITS] dbg2ctx_dbg_sel_a; |
| 222 | wire [`FIRE_DLC_CMU_CTX_DS_BITS] dbg2ctx_dbg_sel_b; |
| 223 | wire [`FIRE_DBG_DATA_BITS] ctx2dbg_dbg_a; |
| 224 | wire [`FIRE_DBG_DATA_BITS] ctx2dbg_dbg_b; |
| 225 | |
| 226 | |
| 227 | //************************************************ |
| 228 | // MODULES |
| 229 | //************************************************ |
| 230 | |
| 231 | dmu_cmu_rcm rcm ( |
| 232 | .clk (clk), |
| 233 | .rst_l (rst_l), |
| 234 | |
| 235 | // // Debug |
| 236 | .dbg2rcm_dbg_sel_a (dbg2rcm_dbg_sel_a), |
| 237 | .dbg2rcm_dbg_sel_b (dbg2rcm_dbg_sel_b), |
| 238 | .rcm2dbg_dbg_a (rcm2dbg_dbg_a), |
| 239 | .rcm2dbg_dbg_b (rcm2dbg_dbg_b), |
| 240 | |
| 241 | // MMU |
| 242 | .mm2cm_rcd_enq (mm2cm_rcd_enq), |
| 243 | .mm2cm_rcd (mm2cm_rcd), |
| 244 | .cm2mm_rcd_full (cm2mm_rcd_full), |
| 245 | |
| 246 | // PMU |
| 247 | .cm2pm_rcd_enq (cm2pm_rcd_enq), |
| 248 | .cm2pm_rcd (cm2pm_rcd), |
| 249 | .pm2cm_rcd_full (pm2cm_rcd_full), |
| 250 | |
| 251 | // CTX |
| 252 | .rcm2ctx_ctx_req(rcm2ctx_ctx_req), |
| 253 | .ctx2rcm_ctx_gnt (ctx2rcm_ctx_gnt), |
| 254 | .ctx2rcm_nxctx_addr (ctx2rcm_nxctx_addr), |
| 255 | .rcm2ctx_ctx_addr (rcm2ctx_ctx_addr), |
| 256 | .rcm2ctx_ctx_rw (rcm2ctx_ctx_rw), |
| 257 | .ctx2rcm_cur_ctx (ctx2rcm_cur_ctx), |
| 258 | .rcm2ctx_ctx (rcm2ctx_ctx), |
| 259 | .rcm2ctx_seq_req (rcm2ctx_seq_req), |
| 260 | .ctx2rcm_seq_gnt (ctx2rcm_seq_gnt), |
| 261 | .ctx2rcm_nxseq_addr (ctx2rcm_nxseq_addr), |
| 262 | .rcm2ctx_pkseq_addr (rcm2ctx_pkseq_addr), |
| 263 | .rcm2ctx_pkseq_rw (rcm2ctx_pkseq_rw), |
| 264 | .rcm2ctx_pkseq (rcm2ctx_pkseq), |
| 265 | |
| 266 | // ILU |
| 267 | .y2k_mps (y2k_mps) |
| 268 | ); |
| 269 | |
| 270 | dmu_cmu_tcm tcm ( |
| 271 | .clk (clk), |
| 272 | .rst_l (rst_l), |
| 273 | |
| 274 | // Debug |
| 275 | .dbg2tcm_dbg_sel_a (dbg2tcm_dbg_sel_a), |
| 276 | .dbg2tcm_dbg_sel_b (dbg2tcm_dbg_sel_b), |
| 277 | .tcm2dbg_dbg_a (tcm2dbg_dbg_a), |
| 278 | .tcm2dbg_dbg_b (tcm2dbg_dbg_b), |
| 279 | |
| 280 | // CLU |
| 281 | .cl2cm_rcd_enq (cl2cm_rcd_enq), |
| 282 | .cl2cm_rcd (cl2cm_rcd), |
| 283 | .cm2cl_rcd_full (cm2cl_rcd_full), |
| 284 | |
| 285 | // RMU |
| 286 | .cm2rm_rcd_enq (cm2rm_rcd_enq), |
| 287 | .cm2rm_rcd (cm2rm_rcd), |
| 288 | .rm2cm_rcd_full (rm2cm_rcd_full), |
| 289 | |
| 290 | // CTX |
| 291 | .tcm2ctx_ctx_addr (tcm2ctx_ctx_addr), |
| 292 | .tcm2ctx_ctx_rw (tcm2ctx_ctx_rw), |
| 293 | .ctx2tcm_cur_ctx (ctx2tcm_cur_ctx), |
| 294 | .tcm2ctx_ctx (tcm2ctx_ctx), |
| 295 | .tcm2ctx_pkseq_addr (tcm2ctx_pkseq_addr), |
| 296 | .tcm2ctx_pkseq_rw (tcm2ctx_pkseq_rw), |
| 297 | .ctx2tcm_cur_pkseq (ctx2tcm_cur_pkseq), |
| 298 | .tcm2ctx_pkseq (tcm2ctx_pkseq), |
| 299 | .tcm2ctx_lst_req (tcm2ctx_lst_req), |
| 300 | .ctx2tcm_lst_gnt (ctx2tcm_lst_gnt), |
| 301 | .ctx2tcm_nxlst_addr (ctx2tcm_nxlst_addr), |
| 302 | .tcm2ctx_ctxlst_addr (tcm2ctx_ctxlst_addr), |
| 303 | .tcm2ctx_clst_rw (tcm2ctx_clst_rw), |
| 304 | .tcm2ctx_lst (tcm2ctx_lst), |
| 305 | .ctx2tcm_cur_lst (ctx2tcm_cur_lst), |
| 306 | .tcm2ctx_ret_req (tcm2ctx_ret_req), |
| 307 | .tcm2ctx_ret_addr (tcm2ctx_ret_addr) |
| 308 | ); |
| 309 | |
| 310 | dmu_cmu_ctx ctx ( |
| 311 | .clk (clk), |
| 312 | .rst_l (rst_l), |
| 313 | |
| 314 | // Debug |
| 315 | .dbg2ctx_dbg_sel_a (dbg2ctx_dbg_sel_a), |
| 316 | .dbg2ctx_dbg_sel_b (dbg2ctx_dbg_sel_b), |
| 317 | .ctx2dbg_dbg_a (ctx2dbg_dbg_a), |
| 318 | .ctx2dbg_dbg_b (ctx2dbg_dbg_b), |
| 319 | |
| 320 | // RCM |
| 321 | .rcm2ctx_ctx_req(rcm2ctx_ctx_req), |
| 322 | .ctx2rcm_ctx_gnt (ctx2rcm_ctx_gnt), |
| 323 | .ctx2rcm_nxctx_addr (ctx2rcm_nxctx_addr), |
| 324 | .rcm2ctx_ctx_addr (rcm2ctx_ctx_addr), |
| 325 | .rcm2ctx_ctx_rw (rcm2ctx_ctx_rw), |
| 326 | .ctx2rcm_cur_ctx (ctx2rcm_cur_ctx), |
| 327 | .rcm2ctx_ctx (rcm2ctx_ctx), |
| 328 | .rcm2ctx_seq_req (rcm2ctx_seq_req), |
| 329 | .ctx2rcm_seq_gnt (ctx2rcm_seq_gnt), |
| 330 | .ctx2rcm_nxseq_addr (ctx2rcm_nxseq_addr), |
| 331 | .rcm2ctx_pkseq_addr (rcm2ctx_pkseq_addr), |
| 332 | .rcm2ctx_pkseq_rw (rcm2ctx_pkseq_rw), |
| 333 | .rcm2ctx_pkseq (rcm2ctx_pkseq), |
| 334 | |
| 335 | // TCM |
| 336 | .tcm2ctx_ctx_addr (tcm2ctx_ctx_addr), |
| 337 | .tcm2ctx_ctx_rw (tcm2ctx_ctx_rw), |
| 338 | .ctx2tcm_cur_ctx (ctx2tcm_cur_ctx), |
| 339 | .tcm2ctx_ctx (tcm2ctx_ctx), |
| 340 | .tcm2ctx_pkseq_addr (tcm2ctx_pkseq_addr), |
| 341 | .tcm2ctx_pkseq_rw (tcm2ctx_pkseq_rw), |
| 342 | .ctx2tcm_cur_pkseq (ctx2tcm_cur_pkseq), |
| 343 | .tcm2ctx_pkseq (tcm2ctx_pkseq), |
| 344 | .tcm2ctx_lst_req (tcm2ctx_lst_req), |
| 345 | .ctx2tcm_lst_gnt (ctx2tcm_lst_gnt), |
| 346 | .ctx2tcm_nxlst_addr (ctx2tcm_nxlst_addr), |
| 347 | .tcm2ctx_ctxlst_addr (tcm2ctx_ctxlst_addr), |
| 348 | .tcm2ctx_clst_rw (tcm2ctx_clst_rw), |
| 349 | .tcm2ctx_lst (tcm2ctx_lst), |
| 350 | .ctx2tcm_cur_lst (ctx2tcm_cur_lst), |
| 351 | .tcm2ctx_ret_req (tcm2ctx_ret_req), |
| 352 | .tcm2ctx_ret_addr (tcm2ctx_ret_addr) |
| 353 | ); |
| 354 | |
| 355 | dmu_cmu_dbg dbg( |
| 356 | .clk (clk), |
| 357 | .rst_l (rst_l), |
| 358 | |
| 359 | // CMU |
| 360 | .cr2cm_dbg_sel_a (cr2cm_dbg_sel_a), // CMU debug select a |
| 361 | .cr2cm_dbg_sel_b (cr2cm_dbg_sel_b), // CMU debug select b |
| 362 | .cm2cr_dbg_a (cm2cr_dbg_a), // CMU debug output a |
| 363 | .cm2cr_dbg_b (cm2cr_dbg_b), // CMU debug output b |
| 364 | |
| 365 | // RCM |
| 366 | .dbg2rcm_dbg_sel_a (dbg2rcm_dbg_sel_a), // RCM debug select a |
| 367 | .dbg2rcm_dbg_sel_b (dbg2rcm_dbg_sel_b), // RCM debug select b |
| 368 | .rcm2dbg_dbg_a (rcm2dbg_dbg_a), // RCM debug output a |
| 369 | .rcm2dbg_dbg_b (rcm2dbg_dbg_b), // RCM debug output b |
| 370 | |
| 371 | // TCM |
| 372 | .dbg2tcm_dbg_sel_a (dbg2tcm_dbg_sel_a), // TCM debug select a |
| 373 | .dbg2tcm_dbg_sel_b (dbg2tcm_dbg_sel_b), // TCM debug select b |
| 374 | .tcm2dbg_dbg_a (tcm2dbg_dbg_a), // TCM debug output a |
| 375 | .tcm2dbg_dbg_b (tcm2dbg_dbg_b), // TCM debug output b |
| 376 | |
| 377 | // CTX |
| 378 | .dbg2ctx_dbg_sel_a (dbg2ctx_dbg_sel_a), // CTX debug select a |
| 379 | .dbg2ctx_dbg_sel_b (dbg2ctx_dbg_sel_b), // CTX debug select b |
| 380 | .ctx2dbg_dbg_a (ctx2dbg_dbg_a), // CTX debug output a |
| 381 | .ctx2dbg_dbg_b (ctx2dbg_dbg_b) // CTX debug output b |
| 382 | ); |
| 383 | |
| 384 | endmodule |
| 385 | |
| 386 | |